From 7034228792cc561e79ff8600f02884bd4c80e287 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 22 Jan 2013 12:59:30 +0100 Subject: MIPS: Whitespace cleanup. Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/emma/emma2rh.h | 112 +++++++++++++++++----------------- arch/mips/include/asm/emma/markeins.h | 2 +- 2 files changed, 57 insertions(+), 57 deletions(-) (limited to 'arch/mips/include/asm/emma') diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h index c1449d20ef0e..ecf059608bd8 100644 --- a/arch/mips/include/asm/emma/emma2rh.h +++ b/arch/mips/include/asm/emma/emma2rh.h @@ -2,7 +2,7 @@ * Copyright (C) NEC Electronics Corporation 2005-2006 * * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h - * Copyright 2001 MontaVista Software Inc. + * Copyright 2001 MontaVista Software Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -40,7 +40,7 @@ #define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE) #define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE) #define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE) -#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE) +#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE) #define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE) #define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE) #define EMMA2RH_GPIO_DIR (0x110d20+REGBASE) @@ -73,7 +73,7 @@ * Memory map (physical address) * * Note most of the following address must be properly aligned by the - * corresponding size. For example, if PCI_IO_SIZE is 16MB, then + * corresponding size. For example, if PCI_IO_SIZE is 16MB, then * PCI_IO_BASE must be aligned along 16MB boundary. */ @@ -96,8 +96,8 @@ #define EMMA2RH_ROM_BASE 0x1c000000 #define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */ -#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE -#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE +#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE +#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE #define NUM_EMMA2RH_IRQ 96 @@ -169,51 +169,51 @@ static inline u8 emma2rh_in8(u32 offset) **/ /*---------------------------------------------------------------------------*/ -/* CNT - Control register (00H R/W) */ +/* CNT - Control register (00H R/W) */ /*---------------------------------------------------------------------------*/ -#define SPT 0x00000001 -#define STT 0x00000002 -#define ACKE 0x00000004 -#define WTIM 0x00000008 -#define SPIE 0x00000010 -#define WREL 0x00000020 -#define LREL 0x00000040 -#define IICE 0x00000080 -#define CNT_RESERVED 0x000000ff /* reserved bit 0 */ - -#define I2C_EMMA_START (IICE | STT) -#define I2C_EMMA_STOP (IICE | SPT) +#define SPT 0x00000001 +#define STT 0x00000002 +#define ACKE 0x00000004 +#define WTIM 0x00000008 +#define SPIE 0x00000010 +#define WREL 0x00000020 +#define LREL 0x00000040 +#define IICE 0x00000080 +#define CNT_RESERVED 0x000000ff /* reserved bit 0 */ + +#define I2C_EMMA_START (IICE | STT) +#define I2C_EMMA_STOP (IICE | SPT) #define I2C_EMMA_REPSTART I2C_EMMA_START /*---------------------------------------------------------------------------*/ -/* STA - Status register (10H Read) */ +/* STA - Status register (10H Read) */ /*---------------------------------------------------------------------------*/ -#define MSTS 0x00000080 -#define ALD 0x00000040 -#define EXC 0x00000020 -#define COI 0x00000010 -#define TRC 0x00000008 -#define ACKD 0x00000004 -#define STD 0x00000002 -#define SPD 0x00000001 +#define MSTS 0x00000080 +#define ALD 0x00000040 +#define EXC 0x00000020 +#define COI 0x00000010 +#define TRC 0x00000008 +#define ACKD 0x00000004 +#define STD 0x00000002 +#define SPD 0x00000001 /*---------------------------------------------------------------------------*/ -/* CSEL - Clock select register (20H R/W) */ +/* CSEL - Clock select register (20H R/W) */ /*---------------------------------------------------------------------------*/ -#define FCL 0x00000080 -#define ND50 0x00000040 -#define CLD 0x00000020 -#define DAD 0x00000010 -#define SMC 0x00000008 -#define DFC 0x00000004 -#define CL 0x00000003 -#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */ - -#define FAST397 0x0000008b -#define FAST297 0x0000008a -#define FAST347 0x0000000b -#define FAST260 0x0000000a -#define FAST130 0x00000008 +#define FCL 0x00000080 +#define ND50 0x00000040 +#define CLD 0x00000020 +#define DAD 0x00000010 +#define SMC 0x00000008 +#define DFC 0x00000004 +#define CL 0x00000003 +#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */ + +#define FAST397 0x0000008b +#define FAST297 0x0000008a +#define FAST347 0x0000000b +#define FAST260 0x0000000a +#define FAST130 0x00000008 #define STANDARD108 0x00000083 #define STANDARD83 0x00000082 #define STANDARD95 0x00000003 @@ -222,32 +222,32 @@ static inline u8 emma2rh_in8(u32 offset) #define STANDARD71 0x00000000 /*---------------------------------------------------------------------------*/ -/* SVA - Slave address register (30H R/W) */ +/* SVA - Slave address register (30H R/W) */ /*---------------------------------------------------------------------------*/ -#define SVA 0x000000fe +#define SVA 0x000000fe /*---------------------------------------------------------------------------*/ -/* SHR - Shift register (40H R/W) */ +/* SHR - Shift register (40H R/W) */ /*---------------------------------------------------------------------------*/ -#define SR 0x000000ff +#define SR 0x000000ff /*---------------------------------------------------------------------------*/ -/* INT - Interrupt register (50H R/W) */ -/* INTM - Interrupt mask register (60H R/W) */ +/* INT - Interrupt register (50H R/W) */ +/* INTM - Interrupt mask register (60H R/W) */ /*---------------------------------------------------------------------------*/ -#define INTE0 0x00000001 +#define INTE0 0x00000001 /*********************************************************************** * I2C registers *********************************************************************** */ -#define I2C_EMMA_CNT 0x00 -#define I2C_EMMA_STA 0x10 -#define I2C_EMMA_CSEL 0x20 -#define I2C_EMMA_SVA 0x30 -#define I2C_EMMA_SHR 0x40 -#define I2C_EMMA_INT 0x50 -#define I2C_EMMA_INTM 0x60 +#define I2C_EMMA_CNT 0x00 +#define I2C_EMMA_STA 0x10 +#define I2C_EMMA_CSEL 0x20 +#define I2C_EMMA_SVA 0x30 +#define I2C_EMMA_SHR 0x40 +#define I2C_EMMA_INT 0x50 +#define I2C_EMMA_INTM 0x60 /* * include the board dependent part diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h index bf2d229c2dae..e55a67477820 100644 --- a/arch/mips/include/asm/emma/markeins.h +++ b/arch/mips/include/asm/emma/markeins.h @@ -2,7 +2,7 @@ * Copyright (C) NEC Electronics Corporation 2005-2006 * * This file based on include/asm-mips/ddb5xxx/ddb5xxx.h - * Copyright 2001 MontaVista Software Inc. + * Copyright 2001 MontaVista Software Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by -- cgit v1.2.3