From 4302e5d53b9166d45317e3ddf0a7a9dab3efd43b Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 5 Mar 2009 11:45:48 +0100 Subject: MIPS: compat: Implement is_compat_task. This is a build fix required after "x86-64: seccomp: fix 32/64 syscall hole" (commit 5b1017404aea6d2e552e991b3fd814d839e9cd67). MIPS doesn't have the issue that was fixed for x86-64 by that patch. This also doesn't solve the N32 issue which is that N32 seccomp processes will be treated as non-compat processes thus only have access to N64 syscalls. Signed-off-by: Ralf Baechle Signed-off-by: Linus Torvalds --- arch/mips/include/asm/compat.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h index ac5d541368e9..6c5b40905dd6 100644 --- a/arch/mips/include/asm/compat.h +++ b/arch/mips/include/asm/compat.h @@ -3,6 +3,8 @@ /* * Architecture specific compatibility types */ +#include +#include #include #include #include @@ -218,4 +220,9 @@ struct compat_shmid64_ds { compat_ulong_t __unused2; }; +static inline int is_compat_task(void) +{ + return test_thread_flag(TIF_32BIT); +} + #endif /* _ASM_COMPAT_H */ -- cgit v1.2.3 From a644b2774d41409519bb33a16bd577cb41bb3095 Mon Sep 17 00:00:00 2001 From: Shinya Kuribayashi Date: Tue, 3 Mar 2009 18:05:51 +0900 Subject: MIPS: NEC VR5500 processor support fixup Current VR5500 processor support lacks of some functions which are expected to be configured/synthesized on arch initialization. Here're some VR5500A spec notes: * All execution hazards are handled in hardware. * Once VR5500A stops the operation of the pipeline by WAIT instruction, it could return from the standby mode only when either a reset, NMI request, or all enabled interrupts is/are detected. In other words, if interrupts are disabled by Status.IE=0, it keeps in standby mode even when interrupts are internally asserted. Notes on WAIT: The operation of the processor is undefined if WAIT insn is in the branch delay slot. The operation is also undefined if WAIT insn is executed when Status.EXL and Status.ERL are set to 1. * VR5500A core only implements the Load prefetch. With these changes, it boots fine. Signed-off-by: Shinya Kuribayashi Signed-off-by: Ralf Baechle --- arch/mips/include/asm/hazards.h | 3 ++- arch/mips/include/asm/prefetch.h | 2 +- arch/mips/kernel/cpu-probe.c | 1 + arch/mips/mm/page.c | 3 ++- arch/mips/mm/tlbex.c | 1 + 5 files changed, 7 insertions(+), 3 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 43baed16a109..134e1fc8f4d6 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -138,7 +138,8 @@ do { \ __instruction_hazard(); \ } while (0) -#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ + defined(CONFIG_CPU_R5500) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h index 17850834ccb0..a56594f360ee 100644 --- a/arch/mips/include/asm/prefetch.h +++ b/arch/mips/include/asm/prefetch.h @@ -26,7 +26,7 @@ * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in * current versions due to erratum G105. * - * VR7701 only implements the Load prefetch. + * VR5500 (including VR5701 and VR7701) only implement load prefetch. * * Finally MIPS32 and MIPS64 implement all of the following hints. */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index a7162a4484cf..1bdbcad3bb74 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -149,6 +149,7 @@ void __init check_wait(void) case CPU_R4650: case CPU_R4700: case CPU_R5000: + case CPU_R5500: case CPU_NEVADA: case CPU_4KC: case CPU_4KEC: diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 1417c6494858..48060c635acd 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void) */ cache_line_size = cpu_dcache_line_size(); switch (current_cpu_type()) { + case CPU_R5500: case CPU_TX49XX: - /* TX49 supports only Pref_Load */ + /* These processors only support the Pref_Load. */ pref_bias_copy_load = 256; break; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 42942038d0fd..f335cf6cdd78 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -318,6 +318,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_BCM4710: case CPU_LOONGSON2: case CPU_CAVIUM_OCTEON: + case CPU_R5500: if (m4kc_tlbp_war()) uasm_i_nop(p); tlbw(p); -- cgit v1.2.3 From 3b289d6e35a1a535c19a5b079f0500526754e650 Mon Sep 17 00:00:00 2001 From: Zhang Le Date: Thu, 12 Mar 2009 18:00:50 +0800 Subject: MIPS: Fix TIF_32BIT undefined problem when seccomp is disabled Signed-off-by: Zhang Le Signed-off-by: Ralf Baechle --- arch/mips/include/asm/seccomp.h | 4 ---- arch/mips/include/asm/thread_info.h | 6 ++++++ 2 files changed, 6 insertions(+), 4 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h index a6772e9507f5..ae6306ebdcad 100644 --- a/arch/mips/include/asm/seccomp.h +++ b/arch/mips/include/asm/seccomp.h @@ -15,8 +15,6 @@ */ #ifdef CONFIG_MIPS32_O32 -#define TIF_32BIT TIF_32BIT_REGS - #define __NR_seccomp_read_32 4003 #define __NR_seccomp_write_32 4004 #define __NR_seccomp_exit_32 4001 @@ -24,8 +22,6 @@ #elif defined(CONFIG_MIPS32_N32) -#define TIF_32BIT _TIF_32BIT_ADDR - #define __NR_seccomp_read_32 6000 #define __NR_seccomp_write_32 6001 #define __NR_seccomp_exit_32 6058 diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 3f76de73c943..676aa2ae1913 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -127,6 +127,12 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define TIF_LOAD_WATCH 25 /* If set, load watch registers */ #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ +#ifdef CONFIG_MIPS32_O32 +#define TIF_32BIT TIF_32BIT_REGS +#elif defined(CONFIG_MIPS32_N32) +#define TIF_32BIT _TIF_32BIT_ADDR +#endif /* CONFIG_MIPS32_O32 */ + #define _TIF_SYSCALL_TRACE (1< Date: Mon, 23 Mar 2009 22:14:55 +0100 Subject: MIPS: Change {set,clear,change}_c0_ to return old value. This is more standard and useful and need for the following fix to work correctly. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mipsregs.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/mips/include') diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 0417516503f6..526f327475ce 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1391,11 +1391,11 @@ static inline void tlb_write_random(void) static inline unsigned int \ set_c0_##name(unsigned int set) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ + new = res | set; \ + write_c0_##name(new); \ \ return res; \ } \ @@ -1403,24 +1403,24 @@ set_c0_##name(unsigned int set) \ static inline unsigned int \ clear_c0_##name(unsigned int clear) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ + new = res & ~clear; \ + write_c0_##name(new); \ \ return res; \ } \ \ static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ +change_c0_##name(unsigned int change, unsigned int val) \ { \ - unsigned int res; \ + unsigned int res, new; \ \ res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ + new = res & ~change; \ + new |= (val & change); \ + write_c0_##name(new); \ \ return res; \ } -- cgit v1.2.3