From 7034228792cc561e79ff8600f02884bd4c80e287 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 22 Jan 2013 12:59:30 +0100 Subject: MIPS: Whitespace cleanup. Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle --- arch/mips/math-emu/cp1emu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/mips/math-emu/cp1emu.c') diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 47c77e7ffbf8..afb5a0bcf7a5 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -169,7 +169,7 @@ static int isBranchInstr(mips_instruction * i) /* * In the Linux kernel, we support selection of FPR format on the - * basis of the Status.FR bit. If an FPU is not present, the FR bit + * basis of the Status.FR bit. If an FPU is not present, the FR bit * is hardwired to zero, which would imply a 32-bit FPU even for * 64-bit CPUs so we rather look at TIF_32BIT_REGS. * FPU emu is slow and bulky and optimizing this function offers fairly @@ -234,7 +234,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, if (xcp->cp0_cause & CAUSEF_BD) { /* * The instruction to be emulated is in a branch delay slot - * which means that we have to emulate the branch instruction + * which means that we have to emulate the branch instruction * BEFORE we do the cop1 instruction. * * This branch could be a COP1 branch, but in that case we @@ -1335,8 +1335,8 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, else { /* * The 'ieee754_csr' is an alias of - * ctx->fcr31. No need to copy ctx->fcr31 to - * ieee754_csr. But ieee754_csr.rm is ieee + * ctx->fcr31. No need to copy ctx->fcr31 to + * ieee754_csr. But ieee754_csr.rm is ieee * library modes. (not mips rounding mode) */ /* convert to ieee library modes */ -- cgit v1.2.3