From 81857db913e9782546d29b52cd3efc80c0145c23 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 4 Nov 2015 11:50:06 +0100 Subject: MIPS: ralink: Add support for mt7688 MT7688 is similar tot he MT7628 but has a different wifi radio. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11439/ Signed-off-by: Ralf Baechle --- arch/mips/ralink/mt7620.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) (limited to 'arch/mips/ralink') diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 2ea5ff6dc22e..4d1a0339dd54 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -40,6 +40,12 @@ /* is this a MT7620 or a MT7628 */ enum mt762x_soc_type mt762x_soc; +/* EFUSE bits */ +#define EFUSE_MT7688 0x100000 + +/* DRAM type bit */ +#define DRAM_TYPE_MT7628_MASK 0x1 + /* does the board have sdram or ddram */ static int dram_type; @@ -227,6 +233,12 @@ static struct rt2880_pmx_group mt7628an_pinmux_data[] = { { 0 } }; +static inline int is_mt76x8(void) +{ + return mt762x_soc == MT762X_SOC_MT7628AN || + mt762x_soc == MT762X_SOC_MT7688; +} + static __init u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) { @@ -381,7 +393,7 @@ void __init ralink_clk_init(void) #define RINT(x) ((x) / 1000000) #define RFRAC(x) (((x) / 1000) % 1000) - if (mt762x_soc == MT762X_SOC_MT7628AN) { + if (is_mt76x8()) { if (xtal_rate == MHZ(40)) cpu_rate = MHZ(580); else @@ -511,8 +523,15 @@ void prom_soc_init(struct ralink_soc_info *soc_info) #endif } } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { - mt762x_soc = MT762X_SOC_MT7628AN; - name = "MT7628AN"; + u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); + + if (efuse & EFUSE_MT7688) { + mt762x_soc = MT762X_SOC_MT7688; + name = "MT7688"; + } else { + mt762x_soc = MT762X_SOC_MT7628AN; + name = "MT7628AN"; + } soc_info->compatible = "ralink,mt7628an-soc"; } else { panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); @@ -525,10 +544,14 @@ void prom_soc_init(struct ralink_soc_info *soc_info) (rev & CHIP_REV_ECO_MASK)); cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); - dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK; + if (is_mt76x8()) + dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; + else + dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & + SYSCFG0_DRAM_TYPE_MASK; soc_info->mem_base = MT7620_DRAM_BASE; - if (mt762x_soc == MT762X_SOC_MT7628AN) + if (is_mt76x8()) mt7628_dram_init(soc_info); else mt7620_dram_init(soc_info); @@ -541,7 +564,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info) pr_info("Digital PMU set to %s control\n", (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); - if (mt762x_soc == MT762X_SOC_MT7628AN) + if (is_mt76x8()) rt2880_pinmux_data = mt7628an_pinmux_data; else rt2880_pinmux_data = mt7620a_pinmux_data; -- cgit v1.2.3 From 418d29c8706170c6801998e48341181b274a47a8 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 4 Nov 2015 11:50:07 +0100 Subject: MIPS: ralink: Unify SoC id handling This makes detection a lot easier for audio, wifi, ... drivers. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11440/ Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-ralink/mt7620.h | 7 ------- arch/mips/include/asm/mach-ralink/ralink_regs.h | 17 +++++++++++++++++ arch/mips/include/asm/mach-ralink/rt305x.h | 21 ++++++--------------- arch/mips/ralink/mt7620.c | 15 ++++++--------- arch/mips/ralink/prom.c | 5 +++++ arch/mips/ralink/rt288x.c | 1 + arch/mips/ralink/rt305x.c | 12 +++++------- arch/mips/ralink/rt3883.c | 2 ++ 8 files changed, 42 insertions(+), 38 deletions(-) (limited to 'arch/mips/ralink') diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h index 590681af4bed..455d406e8ddf 100644 --- a/arch/mips/include/asm/mach-ralink/mt7620.h +++ b/arch/mips/include/asm/mach-ralink/mt7620.h @@ -13,13 +13,6 @@ #ifndef _MT7620_REGS_H_ #define _MT7620_REGS_H_ -enum mt762x_soc_type { - MT762X_SOC_UNKNOWN = 0, - MT762X_SOC_MT7620A, - MT762X_SOC_MT7620N, - MT762X_SOC_MT7628AN, -}; - #define MT7620_SYSC_BASE 0x10000000 #define SYSC_REG_CHIP_NAME0 0x00 diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h index bd93014490df..4c9fba68c8b2 100644 --- a/arch/mips/include/asm/mach-ralink/ralink_regs.h +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h @@ -13,6 +13,23 @@ #ifndef _RALINK_REGS_H_ #define _RALINK_REGS_H_ +enum ralink_soc_type { + RALINK_UNKNOWN = 0, + RT2880_SOC, + RT3883_SOC, + RT305X_SOC_RT3050, + RT305X_SOC_RT3052, + RT305X_SOC_RT3350, + RT305X_SOC_RT3352, + RT305X_SOC_RT5350, + MT762X_SOC_MT7620A, + MT762X_SOC_MT7620N, + MT762X_SOC_MT7621AT, + MT762X_SOC_MT7628AN, + MT762X_SOC_MT7688, +}; +extern enum ralink_soc_type ralink_soc; + extern __iomem void *rt_sysc_membase; extern __iomem void *rt_memc_membase; diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h index 96f731bac79a..2eea79331a14 100644 --- a/arch/mips/include/asm/mach-ralink/rt305x.h +++ b/arch/mips/include/asm/mach-ralink/rt305x.h @@ -13,25 +13,16 @@ #ifndef _RT305X_REGS_H_ #define _RT305X_REGS_H_ -enum rt305x_soc_type { - RT305X_SOC_UNKNOWN = 0, - RT305X_SOC_RT3050, - RT305X_SOC_RT3052, - RT305X_SOC_RT3350, - RT305X_SOC_RT3352, - RT305X_SOC_RT5350, -}; - -extern enum rt305x_soc_type rt305x_soc; +extern enum ralink_soc_type ralink_soc; static inline int soc_is_rt3050(void) { - return rt305x_soc == RT305X_SOC_RT3050; + return ralink_soc == RT305X_SOC_RT3050; } static inline int soc_is_rt3052(void) { - return rt305x_soc == RT305X_SOC_RT3052; + return ralink_soc == RT305X_SOC_RT3052; } static inline int soc_is_rt305x(void) @@ -41,17 +32,17 @@ static inline int soc_is_rt305x(void) static inline int soc_is_rt3350(void) { - return rt305x_soc == RT305X_SOC_RT3350; + return ralink_soc == RT305X_SOC_RT3350; } static inline int soc_is_rt3352(void) { - return rt305x_soc == RT305X_SOC_RT3352; + return ralink_soc == RT305X_SOC_RT3352; } static inline int soc_is_rt5350(void) { - return rt305x_soc == RT305X_SOC_RT5350; + return ralink_soc == RT305X_SOC_RT5350; } #define RT305X_SYSC_BASE 0x10000000 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 4d1a0339dd54..f3a4a08f2e71 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -37,9 +37,6 @@ #define PMU1_CFG 0x8C #define DIG_SW_SEL BIT(25) -/* is this a MT7620 or a MT7628 */ -enum mt762x_soc_type mt762x_soc; - /* EFUSE bits */ #define EFUSE_MT7688 0x100000 @@ -235,8 +232,8 @@ static struct rt2880_pmx_group mt7628an_pinmux_data[] = { static inline int is_mt76x8(void) { - return mt762x_soc == MT762X_SOC_MT7628AN || - mt762x_soc == MT762X_SOC_MT7688; + return ralink_soc == MT762X_SOC_MT7628AN || + ralink_soc == MT762X_SOC_MT7688; } static __init u32 @@ -511,11 +508,11 @@ void prom_soc_init(struct ralink_soc_info *soc_info) if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) { if (bga) { - mt762x_soc = MT762X_SOC_MT7620A; + ralink_soc = MT762X_SOC_MT7620A; name = "MT7620A"; soc_info->compatible = "ralink,mt7620a-soc"; } else { - mt762x_soc = MT762X_SOC_MT7620N; + ralink_soc = MT762X_SOC_MT7620N; name = "MT7620N"; soc_info->compatible = "ralink,mt7620n-soc"; #ifdef CONFIG_PCI @@ -526,10 +523,10 @@ void prom_soc_init(struct ralink_soc_info *soc_info) u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); if (efuse & EFUSE_MT7688) { - mt762x_soc = MT762X_SOC_MT7688; + ralink_soc = MT762X_SOC_MT7688; name = "MT7688"; } else { - mt762x_soc = MT762X_SOC_MT7628AN; + ralink_soc = MT762X_SOC_MT7628AN; name = "MT7628AN"; } soc_info->compatible = "ralink,mt7628an-soc"; diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c index 09419f67da39..39a9142f71be 100644 --- a/arch/mips/ralink/prom.c +++ b/arch/mips/ralink/prom.c @@ -15,11 +15,16 @@ #include #include +#include + #include "common.h" struct ralink_soc_info soc_info; struct rt2880_pmx_group *rt2880_pinmux_data = NULL; +enum ralink_soc_type ralink_soc; +EXPORT_SYMBOL_GPL(ralink_soc); + const char *get_system_type(void) { return soc_info.sys_type; diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c index 738cec865f41..844f5cd55c8f 100644 --- a/arch/mips/ralink/rt288x.c +++ b/arch/mips/ralink/rt288x.c @@ -119,4 +119,5 @@ void prom_soc_init(struct ralink_soc_info *soc_info) soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; rt2880_pinmux_data = rt2880_pinmux_data_act; + ralink_soc == RT2880_SOC; } diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c index c40776ab67db..7e11f001e8ff 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -21,8 +21,6 @@ #include "common.h" -enum rt305x_soc_type rt305x_soc; - static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; static struct rt2880_pmx_func uartf_func[] = { @@ -235,24 +233,24 @@ void prom_soc_init(struct ralink_soc_info *soc_info) icache_sets = (read_c0_config1() >> 22) & 7; if (icache_sets == 1) { - rt305x_soc = RT305X_SOC_RT3050; + ralink_soc = RT305X_SOC_RT3050; name = "RT3050"; soc_info->compatible = "ralink,rt3050-soc"; } else { - rt305x_soc = RT305X_SOC_RT3052; + ralink_soc = RT305X_SOC_RT3052; name = "RT3052"; soc_info->compatible = "ralink,rt3052-soc"; } } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { - rt305x_soc = RT305X_SOC_RT3350; + ralink_soc = RT305X_SOC_RT3350; name = "RT3350"; soc_info->compatible = "ralink,rt3350-soc"; } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { - rt305x_soc = RT305X_SOC_RT3352; + ralink_soc = RT305X_SOC_RT3352; name = "RT3352"; soc_info->compatible = "ralink,rt3352-soc"; } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { - rt305x_soc = RT305X_SOC_RT5350; + ralink_soc = RT305X_SOC_RT5350; name = "RT5350"; soc_info->compatible = "ralink,rt5350-soc"; } else { diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c index 86a535c770d8..582995aaaf4e 100644 --- a/arch/mips/ralink/rt3883.c +++ b/arch/mips/ralink/rt3883.c @@ -153,4 +153,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info) soc_info->mem_size_max = RT3883_MEM_SIZE_MAX; rt2880_pinmux_data = rt3883_pinmux_data; + + ralink_soc == RT3883_SOC; } -- cgit v1.2.3 From b361bd762e7724e660a44955ae4840aa984e3871 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 4 Nov 2015 11:50:08 +0100 Subject: MIPS: ralink: Fix usb issue during frequency scaling If the USB HCD is running and the cpu is scaled too low, then the USB stops working. Increase the idle speed of the core to fix this if the kernel is built with USB support. The "magic" values are taken from the Ralink SDK Kernel. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11441/ Signed-off-by: Ralf Baechle --- arch/mips/ralink/mt7620.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/mips/ralink') diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index f3a4a08f2e71..55ddf09d8676 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -37,6 +37,12 @@ #define PMU1_CFG 0x8C #define DIG_SW_SEL BIT(25) +/* clock scaling */ +#define CLKCFG_FDIV_MASK 0x1f00 +#define CLKCFG_FDIV_USB_VAL 0x0300 +#define CLKCFG_FFRAC_MASK 0x001f +#define CLKCFG_FFRAC_USB_VAL 0x0003 + /* EFUSE bits */ #define EFUSE_MT7688 0x100000 @@ -432,6 +438,20 @@ void __init ralink_clk_init(void) ralink_clk_add("10000b00.spi", sys_rate); ralink_clk_add("10000c00.uartlite", periph_rate); ralink_clk_add("10180000.wmac", xtal_rate); + + if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) { + /* + * When the CPU goes into sleep mode, the BUS clock will be + * too low for USB to function properly. Adjust the busses + * fractional divider to fix this + */ + u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG); + + val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK); + val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL; + + rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG); + } } void __init ralink_of_remap(void) -- cgit v1.2.3 From 73afa6c4208257ea1733a03918fea731a18131e7 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 5 Nov 2015 03:59:58 +0100 Subject: MIPS: ralink: Add tty detection MT7688 has several uarts that can be used for console. There are several boards in the wild, that use ttyS1 or ttyS2. This patch applies a simply autodetection routine to figure out which ttyS the bootloader used as console. The uarts come up in 6 bit mode by default. The bootloader will have set 8 bit mode on the console. Find that 8bit tty and use it. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11459/ Signed-off-by: Ralf Baechle --- arch/mips/ralink/early_printk.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/mips/ralink') diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c index 255d695ec8c6..3c59ffe5f5f5 100644 --- a/arch/mips/ralink/early_printk.c +++ b/arch/mips/ralink/early_printk.c @@ -25,11 +25,13 @@ #define MT7628_CHIP_NAME1 0x20203832 #define UART_REG_TX 0x04 +#define UART_REG_LCR 0x0c #define UART_REG_LSR 0x14 #define UART_REG_LSR_RT2880 0x1c static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE); static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE); +static int init_complete; static inline void uart_w32(u32 val, unsigned reg) { @@ -47,8 +49,32 @@ static inline int soc_is_mt7628(void) (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1); } +static void find_uart_base(void) +{ + int i; + + if (!soc_is_mt7628()) + return; + + for (i = 0; i < 3; i++) { + u32 reg = uart_r32(UART_REG_LCR + (0x100 * i)); + + if (!reg) + continue; + + uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + + (0x100 * i)); + break; + } +} + void prom_putchar(unsigned char ch) { + if (!init_complete) { + find_uart_base(); + init_complete = 1; + } + if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) { uart_w32(ch, UART_TX); while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0) -- cgit v1.2.3 From 37bcc03f97e05cc65ce87d3b2fdcd4e5b28ce06c Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 4 Nov 2015 11:50:10 +0100 Subject: MIPS: ralink: Fix invalid tick count The current code adds the delta twice, which is obviously wrong. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11443/ Signed-off-by: Ralf Baechle --- arch/mips/ralink/cevt-rt3352.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips/ralink') diff --git a/arch/mips/ralink/cevt-rt3352.c b/arch/mips/ralink/cevt-rt3352.c index a8e70a9f274b..e46f91f971c5 100644 --- a/arch/mips/ralink/cevt-rt3352.c +++ b/arch/mips/ralink/cevt-rt3352.c @@ -48,7 +48,7 @@ static int systick_next_event(unsigned long delta, sdev = container_of(evt, struct systick_device, dev); count = ioread32(sdev->membase + SYSTICK_COUNT); count = (count + delta) % SYSTICK_FREQ; - iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE); + iowrite32(count, sdev->membase + SYSTICK_COMPARE); return 0; } -- cgit v1.2.3 From bc19f5d677c10f323650e6bb5fe45ab5fb11e9a9 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 4 Nov 2015 11:50:11 +0100 Subject: MIPS: ralink: Remove check for CONFIG_PCI on non-PCI SoCs The code currently panics if PCI is enabled but the SoC has no PCI bus. This check is superfluous as the driver only loads if enabled in the devicetree. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11444/ Signed-off-by: Ralf Baechle --- arch/mips/ralink/mt7620.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/mips/ralink') diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 55ddf09d8676..dfb04fcedb04 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -535,9 +535,6 @@ void prom_soc_init(struct ralink_soc_info *soc_info) ralink_soc = MT762X_SOC_MT7620N; name = "MT7620N"; soc_info->compatible = "ralink,mt7620n-soc"; -#ifdef CONFIG_PCI - panic("mt7620n is only supported for non pci kernels"); -#endif } } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); -- cgit v1.2.3 From 81ab9f6c5ff8565e4cba330e340a8979a10521d7 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 4 Nov 2015 11:50:12 +0100 Subject: MIPS: ralink: Don't set pm_power_off Setting pm_power_off is apprently wrong and makes drivers such as gpio-poweroff not work. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11445/ Signed-off-by: Ralf Baechle --- arch/mips/ralink/reset.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/mips/ralink') diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c index 55c7ec59df3c..ee26d45e48e7 100644 --- a/arch/mips/ralink/reset.c +++ b/arch/mips/ralink/reset.c @@ -98,7 +98,6 @@ static int __init mips_reboot_setup(void) { _machine_restart = ralink_restart; _machine_halt = ralink_halt; - pm_power_off = ralink_halt; return 0; } -- cgit v1.2.3 From 1a93520504aa035f037e7e255aee670561a38946 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 4 Nov 2015 11:50:13 +0100 Subject: MIPS: ralink: Put the pci bus into reset state before rebooting the SoC Some pcie cards have problems after a reboot without this. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11446/ Signed-off-by: Ralf Baechle --- arch/mips/ralink/reset.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/mips/ralink') diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c index ee26d45e48e7..ee117c4bc4a3 100644 --- a/arch/mips/ralink/reset.c +++ b/arch/mips/ralink/reset.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -18,8 +19,10 @@ #include /* Reset Control */ -#define SYSC_REG_RESET_CTRL 0x034 -#define RSTCTL_RESET_SYSTEM BIT(0) +#define SYSC_REG_RESET_CTRL 0x034 + +#define RSTCTL_RESET_PCI BIT(26) +#define RSTCTL_RESET_SYSTEM BIT(0) static int ralink_assert_device(struct reset_controller_dev *rcdev, unsigned long id) @@ -83,6 +86,11 @@ void ralink_rst_init(void) static void ralink_restart(char *command) { + if (IS_ENABLED(CONFIG_PCI)) { + rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL); + mdelay(50); + } + local_irq_disable(); rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL); unreachable(); -- cgit v1.2.3 From 69ebed7dc9311ea383dd0b9542c823a51b20e679 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Wed, 4 Nov 2015 11:50:14 +0100 Subject: MIPS: ralink: Add missing clock on rt305x The rt305x support is missing a clock required by the ethernet driver. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11447/ Signed-off-by: Ralf Baechle --- arch/mips/ralink/rt305x.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips/ralink') diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c index 7e11f001e8ff..9e4572592065 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -199,6 +199,7 @@ void __init ralink_clk_init(void) } ralink_clk_add("cpu", cpu_rate); + ralink_clk_add("sys", sys_rate); ralink_clk_add("10000b00.spi", sys_rate); ralink_clk_add("10000100.timer", wdt_rate); ralink_clk_add("10000120.watchdog", wdt_rate); -- cgit v1.2.3 From 2bcef9b457bbe159a5e3843e2578d8195e0b1c56 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Mon, 12 Oct 2015 13:13:03 +0200 Subject: MIPS: Make MIPS_CMDLINE_DTB default Seval of-enabled machines (bmips, lantiq, xlp, pistachio, ralink) copied the arguments from dtb to arcs_command_line to prevent the kernel from overwriting them. Since there is now an option to keep the dtb arguments, default to the new option remove the "backup" to arcs_command_line in case of USE_OF is enabled, except for those platforms that still take the bootloader arguments or do not use any at all. Signed-off-by: Jonas Gorski Cc: linux-mips@linux-mips.org Cc: Kevin Cernekee Cc: Florian Fainelli Cc: Zubair Lutfullah Kakakhel Cc: James Hogan Cc: John Crispin Cc: Ganesan Ramalingam Cc: Jayachandran C Cc: Andrew Bresticker Cc: James Hartley Patchwork: https://patchwork.linux-mips.org/patch/11285/ Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 3 +++ arch/mips/bmips/setup.c | 1 - arch/mips/lantiq/prom.c | 2 -- arch/mips/netlogic/xlp/dt.c | 1 - arch/mips/pistachio/init.c | 1 - arch/mips/ralink/of.c | 2 -- 6 files changed, 3 insertions(+), 7 deletions(-) (limited to 'arch/mips/ralink') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e3e65ae681c8..a65341a03712 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2751,6 +2751,9 @@ endchoice choice prompt "Kernel command line type" if !CMDLINE_OVERRIDE + default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \ + !MIPS_MALTA && !MIPS_SEAD3 && \ + !CAVIUM_OCTEON_SOC default MIPS_CMDLINE_FROM_BOOTLOADER config MIPS_CMDLINE_FROM_DTB diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c index 526ec2789bb9..5b16d2955fbb 100644 --- a/arch/mips/bmips/setup.c +++ b/arch/mips/bmips/setup.c @@ -157,7 +157,6 @@ void __init plat_mem_setup(void) panic("no dtb found"); __dt_setup_arch(dtb); - strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); for (q = bmips_quirk_list; q->quirk_fn; q++) { if (of_flat_dt_is_compatible(of_get_flat_dt_root(), diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index 0db099ecc016..297bcaa6b5d3 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -77,8 +77,6 @@ void __init plat_mem_setup(void) * parsed resulting in our memory appearing */ __dt_setup_arch(__dtb_start); - - strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); } void __init device_tree_init(void) diff --git a/arch/mips/netlogic/xlp/dt.c b/arch/mips/netlogic/xlp/dt.c index a625bdb6d6aa..856a6e6d296e 100644 --- a/arch/mips/netlogic/xlp/dt.c +++ b/arch/mips/netlogic/xlp/dt.c @@ -87,7 +87,6 @@ void __init *xlp_dt_init(void *fdtp) void __init xlp_early_init_devtree(void) { __dt_setup_arch(xlp_fdt_blob); - strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); } void __init device_tree_init(void) diff --git a/arch/mips/pistachio/init.c b/arch/mips/pistachio/init.c index 8bd8ebb20a72..96ba2cc9ad3e 100644 --- a/arch/mips/pistachio/init.c +++ b/arch/mips/pistachio/init.c @@ -58,7 +58,6 @@ void __init plat_mem_setup(void) panic("Device-tree not present"); __dt_setup_arch((void *)fw_arg1); - strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); plat_setup_iocoherency(); } diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index 0d30dcd63246..f9eda5d8f82c 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -74,8 +74,6 @@ void __init plat_mem_setup(void) */ __dt_setup_arch(__dtb_start); - strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE); - of_scan_flat_dt(early_init_dt_find_memory, NULL); if (memory_dtb) of_scan_flat_dt(early_init_dt_scan_memory, NULL); -- cgit v1.2.3