From f7ca74904dab2f9157fb17463b4fcaf641cc370d Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Mon, 27 Feb 2023 09:09:11 +0100 Subject: MIPS: BCM47XX: Add support for Huawei B593u-12 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's a BCM5358 based home router. One of very few bcm47xx devices with cellular modems (here: LTE). Signed-off-by: Rafał Miłecki Reviewed-by: Florian Fainelli Signed-off-by: Thomas Bogendoerfer --- arch/mips/bcm47xx/board.c | 1 + arch/mips/bcm47xx/leds.c | 8 ++++++++ arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 + 3 files changed, 10 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/bcm47xx/board.c b/arch/mips/bcm47xx/board.c index 90fb48b046c0..b487f687f62d 100644 --- a/arch/mips/bcm47xx/board.c +++ b/arch/mips/bcm47xx/board.c @@ -193,6 +193,7 @@ struct bcm47xx_board_type_list1 bcm47xx_board_list_board_id[] __initconst = { /* boardtype, boardnum, boardrev */ static const struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = { + {{BCM47XX_BOARD_HUAWEI_B593U_12, "Huawei B593u-12"}, "0x053d", "1234", "0x1301"}, {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"}, {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, diff --git a/arch/mips/bcm47xx/leds.c b/arch/mips/bcm47xx/leds.c index 8e257d0896d2..64e37505b9b4 100644 --- a/arch/mips/bcm47xx/leds.c +++ b/arch/mips/bcm47xx/leds.c @@ -222,6 +222,11 @@ bcm47xx_leds_dlink_dir330[] __initconst = { /* Huawei */ +static const struct gpio_led +bcm47xx_leds_huawei_b593u_12[] __initconst = { + BCM47XX_GPIO_LED(5, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), +}; + static const struct gpio_led bcm47xx_leds_huawei_e970[] __initconst = { BCM47XX_GPIO_LED(0, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), @@ -672,6 +677,9 @@ void __init bcm47xx_leds_register(void) bcm47xx_set_pdata(bcm47xx_leds_dlink_dir330); break; + case BCM47XX_BOARD_HUAWEI_B593U_12: + bcm47xx_set_pdata(bcm47xx_leds_huawei_b593u_12); + break; case BCM47XX_BOARD_HUAWEI_E970: bcm47xx_set_pdata(bcm47xx_leds_huawei_e970); break; diff --git a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h index 3c401f11655e..4bd8c86ec6c3 100644 --- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h +++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h @@ -53,6 +53,7 @@ enum bcm47xx_board { BCM47XX_BOARD_DLINK_DIR130, BCM47XX_BOARD_DLINK_DIR330, + BCM47XX_BOARD_HUAWEI_B593U_12, BCM47XX_BOARD_HUAWEI_E970, BCM47XX_BOARD_LINKSYS_E900V1, -- cgit v1.2.3 From 5bd3990723bdf43333b2c268cc6644cb1961125b Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 21 Feb 2023 13:16:54 +0000 Subject: MIPS: Loongson64: Prefix ipi register address pointers with __iomem They are truely mmio pointers, so give them proper prefix. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/smp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index 660e1de4412a..c268c6dd1ef1 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -27,11 +27,11 @@ DEFINE_PER_CPU(int, cpu_state); #define LS_IPI_IRQ (MIPS_CPU_IRQ_BASE + 6) -static void *ipi_set0_regs[16]; -static void *ipi_clear0_regs[16]; -static void *ipi_status0_regs[16]; -static void *ipi_en0_regs[16]; -static void *ipi_mailbox_buf[16]; +static void __iomem *ipi_set0_regs[16]; +static void __iomem *ipi_clear0_regs[16]; +static void __iomem *ipi_status0_regs[16]; +static void __iomem *ipi_en0_regs[16]; +static void __iomem *ipi_mailbox_buf[16]; static uint32_t core0_c0count[NR_CPUS]; /* read a 32bit value from ipi register */ -- cgit v1.2.3 From ac24cc1835c8e6400230f0bf50e6ba0ab75cb09f Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 21 Feb 2023 13:16:55 +0000 Subject: MIPS: Loongson64: smp: Use nudge_writes instead of wbflush wbflush here intends to let other cores see the results ASAP, nudge_writes fits this purpose better. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/smp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index c268c6dd1ef1..e9d91da7fe24 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -42,13 +42,13 @@ static uint32_t core0_c0count[NR_CPUS]; #define loongson3_ipi_write32(action, addr) \ do { \ writel(action, addr); \ - __wbflush(); \ + nudge_writes(); \ } while (0) /* write a 64bit value to ipi register */ #define loongson3_ipi_write64(action, addr) \ do { \ writeq(action, addr); \ - __wbflush(); \ + nudge_writes(); \ } while (0) static u32 (*ipi_read_clear)(int cpu); @@ -418,7 +418,7 @@ static irqreturn_t loongson3_ipi_interrupt(int irq, void *dev_id) c0count = c0count ? c0count : 1; for (i = 1; i < nr_cpu_ids; i++) core0_c0count[i] = c0count; - __wbflush(); /* Let others see the result ASAP */ + nudge_writes(); /* Let others see the result ASAP */ } return IRQ_HANDLED; -- cgit v1.2.3 From 227003cb5325298a26276f49bebbfaf39d903be4 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 21 Feb 2023 13:16:56 +0000 Subject: MIPS: Loongson64: smp: Correct nudge_writes usage Previously every write to SMP regisers are followed by nudge_writes, this incures a huge performance penalty because nudge_writes involves SYNC, which will be globalized on chip. Only set off nudge_writes when we really want other cores to see the result ASAP. Also replace read/write functions to relaxed version because we don't need extra barriers to protect against DMA. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson64/smp.c | 38 ++++++++++++-------------------------- 1 file changed, 12 insertions(+), 26 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c index e9d91da7fe24..90c783981197 100644 --- a/arch/mips/loongson64/smp.c +++ b/arch/mips/loongson64/smp.c @@ -34,23 +34,6 @@ static void __iomem *ipi_en0_regs[16]; static void __iomem *ipi_mailbox_buf[16]; static uint32_t core0_c0count[NR_CPUS]; -/* read a 32bit value from ipi register */ -#define loongson3_ipi_read32(addr) readl(addr) -/* read a 64bit value from ipi register */ -#define loongson3_ipi_read64(addr) readq(addr) -/* write a 32bit value to ipi register */ -#define loongson3_ipi_write32(action, addr) \ - do { \ - writel(action, addr); \ - nudge_writes(); \ - } while (0) -/* write a 64bit value to ipi register */ -#define loongson3_ipi_write64(action, addr) \ - do { \ - writeq(action, addr); \ - nudge_writes(); \ - } while (0) - static u32 (*ipi_read_clear)(int cpu); static void (*ipi_write_action)(int cpu, u32 action); static void (*ipi_write_enable)(int cpu); @@ -136,26 +119,28 @@ static u32 legacy_ipi_read_clear(int cpu) u32 action; /* Load the ipi register to figure out what we're supposed to do */ - action = loongson3_ipi_read32(ipi_status0_regs[cpu_logical_map(cpu)]); + action = readl_relaxed(ipi_status0_regs[cpu_logical_map(cpu)]); /* Clear the ipi register to clear the interrupt */ - loongson3_ipi_write32(action, ipi_clear0_regs[cpu_logical_map(cpu)]); + writel_relaxed(action, ipi_clear0_regs[cpu_logical_map(cpu)]); + nudge_writes(); return action; } static void legacy_ipi_write_action(int cpu, u32 action) { - loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]); + writel_relaxed((u32)action, ipi_set0_regs[cpu]); + nudge_writes(); } static void legacy_ipi_write_enable(int cpu) { - loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); + writel_relaxed(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); } static void legacy_ipi_clear_buf(int cpu) { - loongson3_ipi_write64(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); + writeq_relaxed(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); } static void legacy_ipi_write_buf(int cpu, struct task_struct *idle) @@ -171,14 +156,15 @@ static void legacy_ipi_write_buf(int cpu, struct task_struct *idle) pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", cpu, startargs[0], startargs[1], startargs[2]); - loongson3_ipi_write64(startargs[3], + writeq_relaxed(startargs[3], ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18); - loongson3_ipi_write64(startargs[2], + writeq_relaxed(startargs[2], ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10); - loongson3_ipi_write64(startargs[1], + writeq_relaxed(startargs[1], ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8); - loongson3_ipi_write64(startargs[0], + writeq_relaxed(startargs[0], ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); + nudge_writes(); } static void csr_ipi_probe(void) -- cgit v1.2.3 From 162e134aedcacc9ab9d5648349ceb5409f9ec880 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 21 Feb 2023 13:16:57 +0000 Subject: MIPS: Loongson64: Remove CPU_HAS_WB Q: Do we have really have write buffer A: Yes, on newer Loongson processors there is a "store fill buffer" that will collect *cached* writes, on all Loongson processors AXI crossbar will buffer all writes. Q: Then why do we want to remove CPU_HAS_WB? A: Because CPU_HAS_WB introduces wbflush, which intends to flush all write reuqests to mmio device. We won't be affected by store fill buffer because it won't buffer uncached writes. And a regular memory barrier is sufficient to flush crossbar write buffer. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 1 - arch/mips/loongson64/setup.c | 15 --------------- 2 files changed, 16 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e2f3ca73f40d..6f275ace27be 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -490,7 +490,6 @@ config MACH_LOONGSON64 select BOARD_SCACHE select CSRC_R4K select CEVT_R4K - select CPU_HAS_WB select FORCE_PCI select ISA select I8259 diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c index 3cd11c2b308b..257038e18779 100644 --- a/arch/mips/loongson64/setup.c +++ b/arch/mips/loongson64/setup.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include @@ -17,20 +16,6 @@ void *loongson_fdt_blob; -static void wbflush_loongson(void) -{ - asm(".set\tpush\n\t" - ".set\tnoreorder\n\t" - ".set mips3\n\t" - "sync\n\t" - "nop\n\t" - ".set\tpop\n\t" - ".set mips0\n\t"); -} - -void (*__wbflush)(void) = wbflush_loongson; -EXPORT_SYMBOL(__wbflush); - void __init plat_mem_setup(void) { if (loongson_fdt_blob) -- cgit v1.2.3 From 7b76ab837522fd6aa72b25d1c5460995095fedc0 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 21 Feb 2023 13:16:58 +0000 Subject: MIPS: Loongson64: Opt-out war_io_reorder_wmb It is clearly stated on "Loongson 3A3000/3B3000 processor user manual vol 2" that "All access requests using a non-cached algorithm are executed in a blocking order. That is, before the current read request data is returned to the processor, all subsequent requests are blocked and issued; All subsequent requests are blocked until the write request data has been sent or the issued write request has not received a write reply from the final receiver." Which means uncached read/write is strongly ordered. So we won't need this workaround. This option was introduced when we add initial support for GS464E, it looks like a misinterpretation of another section in the manual saying we need barriers to ensure MMIO order against DMA requests. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index e6d5ccaa309e..cc28d207a061 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -210,7 +210,7 @@ void iounmap(const volatile void __iomem *addr); #define ioremap_wc(offset, size) \ ioremap_prot((offset), (size), boot_cpu_data.writecombine) -#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64) +#if defined(CONFIG_CPU_CAVIUM_OCTEON) #define war_io_reorder_wmb() wmb() #else #define war_io_reorder_wmb() barrier() -- cgit v1.2.3 From 13a9d0bea9d1cb119c9ce59c95b51cbb954827cc Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:57:55 +0100 Subject: mips: ralink: rt305x: define RT305X_SYSC_BASE with __iomem So that RT305X_SYSC_BASE can be used later in multiple functions without needing to repeat this __iomem declaration each time Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-ralink/rt305x.h | 3 ++- arch/mips/ralink/rt305x.c | 8 +++----- 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h index 4d8e8c8d83ce..ef58f7bff957 100644 --- a/arch/mips/include/asm/mach-ralink/rt305x.h +++ b/arch/mips/include/asm/mach-ralink/rt305x.h @@ -43,7 +43,8 @@ static inline int soc_is_rt5350(void) return ralink_soc == RT305X_SOC_RT5350; } -#define RT305X_SYSC_BASE 0x10000000 +#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) +#define RT305X_SYSC_BASE IOMEM(0x10000000) #define SYSC_REG_CHIP_NAME0 0x00 #define SYSC_REG_CHIP_NAME1 0x04 diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c index 8b095a9dcb15..135a46517763 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -21,11 +21,10 @@ static unsigned long rt5350_get_mem_size(void) { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); unsigned long ret; u32 t; - t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG); + t = __raw_readl(RT305X_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG); t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) & RT5350_SYSCFG0_DRAM_SIZE_MASK; @@ -142,14 +141,13 @@ void __init ralink_of_remap(void) void __init prom_soc_init(struct ralink_soc_info *soc_info) { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); unsigned char *name; u32 n0; u32 n1; u32 id; - n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); - n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); + n0 = __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME0); + n1 = __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME1); if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { unsigned long icache_sets; -- cgit v1.2.3 From 0def2164c94aa504bd2a3575e74a5f7fd86f5587 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:57:56 +0100 Subject: mips: ralink: rt305x: soc queries and tests as functions Move the SoC register value queries and tests to specific functions, to remove repetition of logic. No functional changes intended Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/ralink/rt305x.c | 97 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 77 insertions(+), 20 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c index 135a46517763..a24143c739ee 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -139,52 +139,109 @@ void __init ralink_of_remap(void) panic("Failed to remap core resources"); } -void __init prom_soc_init(struct ralink_soc_info *soc_info) +static unsigned int __init rt305x_get_soc_name0(void) +{ + return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME0); +} + +static unsigned int __init rt305x_get_soc_name1(void) { - unsigned char *name; - u32 n0; - u32 n1; - u32 id; + return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME1); +} - n0 = __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME0); - n1 = __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_NAME1); +static bool __init rt3052_soc_valid(void) +{ + if (rt305x_get_soc_name0() == RT3052_CHIP_NAME0 && + rt305x_get_soc_name1() == RT3052_CHIP_NAME1) + return true; + else + return false; +} - if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) { +static bool __init rt3350_soc_valid(void) +{ + if (rt305x_get_soc_name0() == RT3350_CHIP_NAME0 && + rt305x_get_soc_name1() == RT3350_CHIP_NAME1) + return true; + else + return false; +} + +static bool __init rt3352_soc_valid(void) +{ + if (rt305x_get_soc_name0() == RT3352_CHIP_NAME0 && + rt305x_get_soc_name1() == RT3352_CHIP_NAME1) + return true; + else + return false; +} + +static bool __init rt5350_soc_valid(void) +{ + if (rt305x_get_soc_name0() == RT5350_CHIP_NAME0 && + rt305x_get_soc_name1() == RT5350_CHIP_NAME1) + return true; + else + return false; +} + +static const char __init *rt305x_get_soc_name(struct ralink_soc_info *soc_info) +{ + if (rt3052_soc_valid()) { unsigned long icache_sets; icache_sets = (read_c0_config1() >> 22) & 7; if (icache_sets == 1) { ralink_soc = RT305X_SOC_RT3050; - name = "RT3050"; soc_info->compatible = "ralink,rt3050-soc"; + return "RT3050"; } else { ralink_soc = RT305X_SOC_RT3052; - name = "RT3052"; soc_info->compatible = "ralink,rt3052-soc"; + return "RT3052"; } - } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) { + } else if (rt3350_soc_valid()) { ralink_soc = RT305X_SOC_RT3350; - name = "RT3350"; soc_info->compatible = "ralink,rt3350-soc"; - } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) { + return "RT3350"; + } else if (rt3352_soc_valid()) { ralink_soc = RT305X_SOC_RT3352; - name = "RT3352"; soc_info->compatible = "ralink,rt3352-soc"; - } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) { + return "RT3352"; + } else if (rt5350_soc_valid()) { ralink_soc = RT305X_SOC_RT5350; - name = "RT5350"; soc_info->compatible = "ralink,rt5350-soc"; + return "RT5350"; } else { - panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1); + panic("rt305x: unknown SoC, n0:%08x n1:%08x", + rt305x_get_soc_name0(), rt305x_get_soc_name1()); } +} + +static unsigned int __init rt305x_get_soc_id(void) +{ + return __raw_readl(RT305X_SYSC_BASE + SYSC_REG_CHIP_ID); +} + +static unsigned int __init rt305x_get_soc_ver(void) +{ + return (rt305x_get_soc_id() >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK; +} - id = __raw_readl(sysc + SYSC_REG_CHIP_ID); +static unsigned int __init rt305x_get_soc_rev(void) +{ + return (rt305x_get_soc_id() & CHIP_ID_REV_MASK); +} + +void __init prom_soc_init(struct ralink_soc_info *soc_info) +{ + const char *name = rt305x_get_soc_name(soc_info); snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, "Ralink %s id:%u rev:%u", name, - (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, - (id & CHIP_ID_REV_MASK)); + rt305x_get_soc_ver(), + rt305x_get_soc_rev()); soc_info->mem_base = RT305X_SDRAM_BASE; if (soc_is_rt5350()) { -- cgit v1.2.3 From bf27860fcabdd61d4bd33ce9488dc68bae5c7107 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:57:57 +0100 Subject: mips: ralink: rt305x: introduce 'soc_device' initialization RT305x SoCs have their own 'ralink_soc_info' structure with some information about the soc itself. In order to be able to retrieve this information from driver code and avoid architecture dependencies for retrieving these details introduce this 'soc_device'. Set 'data' pointer points to the struct 'ralink_soc_info' to be able to export also current soc information using this mechanism. We need to select 'SOC_BUS' in Kconfig configuration for these SoCs. Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/ralink/Kconfig | 1 + arch/mips/ralink/rt305x.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 83e61e147b90..0b0459f1f83e 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -32,6 +32,7 @@ choice config SOC_RT305X bool "RT305x" + select SOC_BUS config SOC_RT3883 bool "RT3883" diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c index a24143c739ee..d8dcc5cc66cc 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include @@ -19,6 +21,8 @@ #include "common.h" +static struct ralink_soc_info *soc_info_ptr; + static unsigned long rt5350_get_mem_size(void) { unsigned long ret; @@ -233,6 +237,46 @@ static unsigned int __init rt305x_get_soc_rev(void) return (rt305x_get_soc_id() & CHIP_ID_REV_MASK); } +static const char __init *rt305x_get_soc_id_name(void) +{ + if (soc_is_rt3050()) + return "rt3050"; + else if (soc_is_rt3052()) + return "rt3052"; + else if (soc_is_rt3350()) + return "rt3350"; + else if (soc_is_rt3352()) + return "rt3352"; + else if (soc_is_rt5350()) + return "rt5350"; + else + return "invalid"; +} + +static int __init rt305x_soc_dev_init(void) +{ + struct soc_device *soc_dev; + struct soc_device_attribute *soc_dev_attr; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = "Ralink"; + soc_dev_attr->soc_id = rt305x_get_soc_id_name(); + + soc_dev_attr->data = soc_info_ptr; + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr); + return PTR_ERR(soc_dev); + } + + return 0; +} +device_initcall(rt305x_soc_dev_init); + void __init prom_soc_init(struct ralink_soc_info *soc_info) { const char *name = rt305x_get_soc_name(soc_info); @@ -253,4 +297,6 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; } + + soc_info_ptr = soc_info; } -- cgit v1.2.3 From 7edb1775846ebc5a7f4d5085ff6d712ed137a460 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:57:58 +0100 Subject: mips: ralink: rt3883: define RT3883_SYSC_BASE with __iomem So that RT3883_SYSC_BASE can be used later in multiple functions without needing to repeat this __iomem declaration each time Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-ralink/rt3883.h | 4 +++- arch/mips/ralink/rt3883.c | 7 +++---- 2 files changed, 6 insertions(+), 5 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h index f250de9c055b..ad25d5e8d2dc 100644 --- a/arch/mips/include/asm/mach-ralink/rt3883.h +++ b/arch/mips/include/asm/mach-ralink/rt3883.h @@ -10,8 +10,10 @@ #include +#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) + #define RT3883_SDRAM_BASE 0x00000000 -#define RT3883_SYSC_BASE 0x10000000 +#define RT3883_SYSC_BASE IOMEM(0x10000000) #define RT3883_TIMER_BASE 0x10000100 #define RT3883_INTC_BASE 0x10000200 #define RT3883_MEMC_BASE 0x10000300 diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c index d9875f146d66..fa215c07558d 100644 --- a/arch/mips/ralink/rt3883.c +++ b/arch/mips/ralink/rt3883.c @@ -72,15 +72,14 @@ void __init ralink_of_remap(void) void __init prom_soc_init(struct ralink_soc_info *soc_info) { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE); const char *name; u32 n0; u32 n1; u32 id; - n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3); - n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7); - id = __raw_readl(sysc + RT3883_SYSC_REG_REVID); + n0 = __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID0_3); + n1 = __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID4_7); + id = __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_REVID); if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) { soc_info->compatible = "ralink,rt3883-soc"; -- cgit v1.2.3 From 89f9b3041e7eddfcfa7260d7e0d2846b21f316d1 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:57:59 +0100 Subject: mips: ralink: rt3883: soc queries and tests as functions Move the SoC register value queries and tests to specific functions, to remove repetition of logic. No functional changes intended Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/ralink/rt3883.c | 64 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 48 insertions(+), 16 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c index fa215c07558d..6f8541a4bc8e 100644 --- a/arch/mips/ralink/rt3883.c +++ b/arch/mips/ralink/rt3883.c @@ -70,29 +70,61 @@ void __init ralink_of_remap(void) panic("Failed to remap core resources"); } -void __init prom_soc_init(struct ralink_soc_info *soc_info) +static unsigned int __init rt3883_get_soc_name0(void) +{ + return __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID0_3); +} + +static unsigned int __init rt3883_get_soc_name1(void) +{ + return __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID4_7); +} + +static bool __init rt3883_soc_valid(void) +{ + if (rt3883_get_soc_name0() == RT3883_CHIP_NAME0 && + rt3883_get_soc_name1() == RT3883_CHIP_NAME1) + return true; + else + return false; +} + +static const char __init *rt3883_get_soc_name(void) +{ + if (rt3883_soc_valid()) + return "RT3883"; + else + return "invalid"; +} + +static unsigned int __init rt3883_get_soc_id(void) { - const char *name; - u32 n0; - u32 n1; - u32 id; + return __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_REVID); +} - n0 = __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID0_3); - n1 = __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_CHIPID4_7); - id = __raw_readl(RT3883_SYSC_BASE + RT3883_SYSC_REG_REVID); +static unsigned int __init rt3883_get_soc_ver(void) +{ + return (rt3883_get_soc_id() >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK; +} - if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) { +static unsigned int __init rt3883_get_soc_rev(void) +{ + return (rt3883_get_soc_id() & RT3883_REVID_ECO_ID_MASK); +} + +void __init prom_soc_init(struct ralink_soc_info *soc_info) +{ + if (rt3883_soc_valid()) soc_info->compatible = "ralink,rt3883-soc"; - name = "RT3883"; - } else { - panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1); - } + else + panic("rt3883: unknown SoC, n0:%08x n1:%08x", + rt3883_get_soc_name0(), rt3883_get_soc_name1()); snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, "Ralink %s ver:%u eco:%u", - name, - (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK, - (id & RT3883_REVID_ECO_ID_MASK)); + rt3883_get_soc_name(), + rt3883_get_soc_ver(), + rt3883_get_soc_rev()); soc_info->mem_base = RT3883_SDRAM_BASE; soc_info->mem_size_min = RT3883_MEM_SIZE_MIN; -- cgit v1.2.3 From 2165248f68b5f3e27faac844795e6691e1ee7777 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:58:00 +0100 Subject: mips: ralink: rt3883: introduce 'soc_device' initialization RT3883 SoC have its own 'ralink_soc_info' structure with some information about the soc itself. In order to be able to retrieve this information from driver code and avoid architecture dependencies for retrieving these details introduce this 'soc_device'. Set 'data' pointer points to the struct 'ralink_soc_info' to be able to export also current soc information using this mechanism. We need to select 'SOC_BUS' in Kconfig configuration for these SoCs. Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/ralink/Kconfig | 1 + arch/mips/ralink/rt3883.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 0b0459f1f83e..e2a43a59fc81 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -37,6 +37,7 @@ choice config SOC_RT3883 bool "RT3883" select HAVE_PCI + select SOC_BUS config SOC_MT7620 bool "MT7620/8" diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c index 6f8541a4bc8e..cca887af378f 100644 --- a/arch/mips/ralink/rt3883.c +++ b/arch/mips/ralink/rt3883.c @@ -10,6 +10,8 @@ #include #include +#include +#include #include #include @@ -17,6 +19,8 @@ #include "common.h" +static struct ralink_soc_info *soc_info_ptr; + void __init ralink_clk_init(void) { unsigned long cpu_rate, sys_rate; @@ -112,6 +116,30 @@ static unsigned int __init rt3883_get_soc_rev(void) return (rt3883_get_soc_id() & RT3883_REVID_ECO_ID_MASK); } +static int __init rt3883_soc_dev_init(void) +{ + struct soc_device *soc_dev; + struct soc_device_attribute *soc_dev_attr; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = "Ralink"; + soc_dev_attr->soc_id = rt3883_get_soc_name(); + + soc_dev_attr->data = soc_info_ptr; + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr); + return PTR_ERR(soc_dev); + } + + return 0; +} +device_initcall(rt3883_soc_dev_init); + void __init prom_soc_init(struct ralink_soc_info *soc_info) { if (rt3883_soc_valid()) @@ -131,4 +159,5 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) soc_info->mem_size_max = RT3883_MEM_SIZE_MAX; ralink_soc = RT3883_SOC; + soc_info_ptr = soc_info; } -- cgit v1.2.3 From 1e688601d18d3d872ffaad70c599e8c1a1d788a0 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:58:01 +0100 Subject: mips: ralink: rt288x: define RT2880_SYSC_BASE with __iomem So that RT2880_SYSC_BASE can be used later in multiple functions without needing to repeat this __iomem declaration each time Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-ralink/rt288x.h | 3 ++- arch/mips/ralink/rt288x.c | 7 +++---- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h index 5f213534f0f5..66a999cd1d80 100644 --- a/arch/mips/include/asm/mach-ralink/rt288x.h +++ b/arch/mips/include/asm/mach-ralink/rt288x.h @@ -11,7 +11,8 @@ #ifndef _RT288X_REGS_H_ #define _RT288X_REGS_H_ -#define RT2880_SYSC_BASE 0x00300000 +#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) +#define RT2880_SYSC_BASE IOMEM(0x00300000) #define SYSC_REG_CHIP_NAME0 0x00 #define SYSC_REG_CHIP_NAME1 0x04 diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c index 493335db2fe1..12f339138c4c 100644 --- a/arch/mips/ralink/rt288x.c +++ b/arch/mips/ralink/rt288x.c @@ -59,15 +59,14 @@ void __init ralink_of_remap(void) void __init prom_soc_init(struct ralink_soc_info *soc_info) { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE); const char *name; u32 n0; u32 n1; u32 id; - n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); - n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); - id = __raw_readl(sysc + SYSC_REG_CHIP_ID); + n0 = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0); + n1 = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME1); + id = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_ID); if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) { soc_info->compatible = "ralink,r2880-soc"; -- cgit v1.2.3 From 5a5aa151bdccea934d4a84086661538b60a09a42 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:58:02 +0100 Subject: mips: ralink: rt288x: soc queries and tests as functions Move the SoC register value queries and tests to specific functions, to remove repetition of logic. No functional changes intended Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/ralink/rt288x.c | 63 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 47 insertions(+), 16 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c index 12f339138c4c..a417b8b89b94 100644 --- a/arch/mips/ralink/rt288x.c +++ b/arch/mips/ralink/rt288x.c @@ -57,29 +57,60 @@ void __init ralink_of_remap(void) panic("Failed to remap core resources"); } -void __init prom_soc_init(struct ralink_soc_info *soc_info) +static unsigned int __init rt2880_get_soc_name0(void) { - const char *name; - u32 n0; - u32 n1; - u32 id; + return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0); +} - n0 = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0); - n1 = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME1); - id = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_ID); +static unsigned int __init rt2880_get_soc_name1(void) +{ + return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME1); +} - if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) { +static bool __init rt2880_soc_valid(void) +{ + if (rt2880_get_soc_name0() == RT2880_CHIP_NAME0 && + rt2880_get_soc_name1() == RT2880_CHIP_NAME1) + return true; + else + return false; +} + +static const char __init *rt2880_get_soc_name(void) +{ + if (rt2880_soc_valid()) + return "RT2880"; + else + return "invalid"; +} + +static unsigned int __init rt2880_get_soc_id(void) +{ + return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_ID); +} + +static unsigned int __init rt2880_get_soc_ver(void) +{ + return (rt2880_get_soc_id() >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK; +} + +static unsigned int __init rt2880_get_soc_rev(void) +{ + return (rt2880_get_soc_id() & CHIP_ID_REV_MASK); +} +void __init prom_soc_init(struct ralink_soc_info *soc_info) +{ + if (rt2880_soc_valid()) soc_info->compatible = "ralink,r2880-soc"; - name = "RT2880"; - } else { - panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1); - } + else + panic("rt288x: unknown SoC, n0:%08x n1:%08x", + rt2880_get_soc_name0(), rt2880_get_soc_name1()); snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, "Ralink %s id:%u rev:%u", - name, - (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, - (id & CHIP_ID_REV_MASK)); + rt2880_get_soc_name(), + rt2880_get_soc_ver(), + rt2880_get_soc_rev()); soc_info->mem_base = RT2880_SDRAM_BASE; soc_info->mem_size_min = RT2880_MEM_SIZE_MIN; -- cgit v1.2.3 From 7a26b384c44cfa9ea65799dc375619c96608ecad Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:58:03 +0100 Subject: mips: ralink: rt288x: introduce 'soc_device' initialization RT288X SoCs have their own 'ralink_soc_info' structure with some information about the soc itself. In order to be able to retrieve this information from driver code and avoid architecture dependencies for retrieving these details introduce this 'soc_device'. Set 'data' pointer points to the struct 'ralink_soc_info' to be able to export also current soc information using this mechanism. We need to select 'SOC_BUS' in Kconfig configuration for these SoCs. Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/ralink/Kconfig | 1 + arch/mips/ralink/rt288x.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index e2a43a59fc81..e8b8fb35d33d 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -29,6 +29,7 @@ choice select MIPS_AUTO_PFN_OFFSET select MIPS_L1_CACHE_SHIFT_4 select HAVE_PCI + select SOC_BUS config SOC_RT305X bool "RT305x" diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c index a417b8b89b94..456ba0b2599e 100644 --- a/arch/mips/ralink/rt288x.c +++ b/arch/mips/ralink/rt288x.c @@ -10,6 +10,8 @@ #include #include +#include +#include #include #include @@ -17,6 +19,8 @@ #include "common.h" +static struct ralink_soc_info *soc_info_ptr; + void __init ralink_clk_init(void) { unsigned long cpu_rate, wmac_rate = 40000000; @@ -98,6 +102,31 @@ static unsigned int __init rt2880_get_soc_rev(void) { return (rt2880_get_soc_id() & CHIP_ID_REV_MASK); } + +static int __init rt2880_soc_dev_init(void) +{ + struct soc_device *soc_dev; + struct soc_device_attribute *soc_dev_attr; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = "Ralink"; + soc_dev_attr->soc_id = rt2880_get_soc_name(); + + soc_dev_attr->data = soc_info_ptr; + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr); + return PTR_ERR(soc_dev); + } + + return 0; +} +device_initcall(rt2880_soc_dev_init); + void __init prom_soc_init(struct ralink_soc_info *soc_info) { if (rt2880_soc_valid()) @@ -117,4 +146,5 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; ralink_soc = RT2880_SOC; + soc_info_ptr = soc_info; } -- cgit v1.2.3 From 217cf927e7c6ab41dc276442600f1309613ad417 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:58:04 +0100 Subject: mips: ralink: mt7620: define MT7620_SYSC_BASE with __iomem So that MT7620_SYSC_BASE can be used later in multiple functions without needing to repeat this __iomem declaration each time Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-ralink/mt7620.h | 3 ++- arch/mips/ralink/mt7620.c | 15 +++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h index d51dfad8f543..3e37705ea9cf 100644 --- a/arch/mips/include/asm/mach-ralink/mt7620.h +++ b/arch/mips/include/asm/mach-ralink/mt7620.h @@ -11,7 +11,8 @@ #ifndef _MT7620_REGS_H_ #define _MT7620_REGS_H_ -#define MT7620_SYSC_BASE 0x10000000 +#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x))) +#define MT7620_SYSC_BASE IOMEM(0x10000000) #define SYSC_REG_CHIP_NAME0 0x00 #define SYSC_REG_CHIP_NAME1 0x04 diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index ae1fa0391c88..c13b73b6ee3f 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -326,7 +326,6 @@ mt7628_dram_init(struct ralink_soc_info *soc_info) void __init prom_soc_init(struct ralink_soc_info *soc_info) { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE); unsigned char *name = NULL; u32 n0; u32 n1; @@ -336,9 +335,9 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) u32 pmu1; u32 bga; - n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0); - n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1); - rev = __raw_readl(sysc + SYSC_REG_CHIP_REV); + n0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0); + n1 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1); + rev = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV); bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) { @@ -352,7 +351,7 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) soc_info->compatible = "ralink,mt7620n-soc"; } } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { - u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG); + u32 efuse = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG); if (efuse & EFUSE_MT7688) { ralink_soc = MT762X_SOC_MT7688; @@ -372,7 +371,7 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, (rev & CHIP_REV_ECO_MASK)); - cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0); + cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0); if (is_mt76x8()) { dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; } else { @@ -388,8 +387,8 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) else mt7620_dram_init(soc_info); - pmu0 = __raw_readl(sysc + PMU0_CFG); - pmu1 = __raw_readl(sysc + PMU1_CFG); + pmu0 = __raw_readl(MT7620_SYSC_BASE + PMU0_CFG); + pmu1 = __raw_readl(MT7620_SYSC_BASE + PMU1_CFG); pr_info("Analog PMU set to %s control\n", (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); -- cgit v1.2.3 From 727ea3c77dd9b94d994708a148b82df76a47fa79 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:58:05 +0100 Subject: mips: ralink: mt7620: soc queries and tests as functions Move the SoC register value queries and tests to specific functions, to remove repetition of logic. No functional changes intended Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/ralink/mt7620.c | 94 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 72 insertions(+), 22 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index c13b73b6ee3f..8604d91f3375 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -324,34 +324,76 @@ mt7628_dram_init(struct ralink_soc_info *soc_info) } } -void __init prom_soc_init(struct ralink_soc_info *soc_info) +static unsigned int __init mt7620_get_soc_name0(void) { - unsigned char *name = NULL; - u32 n0; - u32 n1; - u32 rev; - u32 cfg0; - u32 pmu0; - u32 pmu1; - u32 bga; + return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0); +} + +static unsigned int __init mt7620_get_soc_name1(void) +{ + return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1); +} + +static bool __init mt7620_soc_valid(void) +{ + if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 && + mt7620_get_soc_name1() == MT7620_CHIP_NAME1) + return true; + else + return false; +} + +static bool __init mt7628_soc_valid(void) +{ + if (mt7620_get_soc_name0() == MT7620_CHIP_NAME0 && + mt7620_get_soc_name1() == MT7628_CHIP_NAME1) + return true; + else + return false; +} - n0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME0); - n1 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_NAME1); - rev = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV); - bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; +static unsigned int __init mt7620_get_rev(void) +{ + return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_CHIP_REV); +} + +static unsigned int __init mt7620_get_bga(void) +{ + return (mt7620_get_rev() >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK; +} + +static unsigned int __init mt7620_get_efuse(void) +{ + return __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG); +} + +static unsigned int __init mt7620_get_soc_ver(void) +{ + return (mt7620_get_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK; +} + +static unsigned int __init mt7620_get_soc_eco(void) +{ + return (mt7620_get_rev() & CHIP_REV_ECO_MASK); +} + +static const char __init *mt7620_get_soc_name(struct ralink_soc_info *soc_info) +{ + if (mt7620_soc_valid()) { + u32 bga = mt7620_get_bga(); - if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) { if (bga) { ralink_soc = MT762X_SOC_MT7620A; - name = "MT7620A"; soc_info->compatible = "ralink,mt7620a-soc"; + return "MT7620A"; } else { ralink_soc = MT762X_SOC_MT7620N; - name = "MT7620N"; soc_info->compatible = "ralink,mt7620n-soc"; + return "MT7620N"; } - } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) { - u32 efuse = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_EFUSE_CFG); + } else if (mt7628_soc_valid()) { + u32 efuse = mt7620_get_efuse(); + unsigned char *name = NULL; if (efuse & EFUSE_MT7688) { ralink_soc = MT762X_SOC_MT7688; @@ -361,15 +403,23 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) name = "MT7628AN"; } soc_info->compatible = "ralink,mt7628an-soc"; + return name; } else { - panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1); + panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", + mt7620_get_soc_name0(), mt7620_get_soc_name1()); } +} + +void __init prom_soc_init(struct ralink_soc_info *soc_info) +{ + const char *name = mt7620_get_soc_name(soc_info); + u32 cfg0; + u32 pmu0; + u32 pmu1; snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN, "MediaTek %s ver:%u eco:%u", - name, - (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, - (rev & CHIP_REV_ECO_MASK)); + name, mt7620_get_soc_ver(), mt7620_get_soc_eco()); cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0); if (is_mt76x8()) { -- cgit v1.2.3 From 83552892b772dfc4639a4f2da075bbb5d605b788 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Mon, 27 Feb 2023 11:58:06 +0100 Subject: mips: ralink: mt7620: introduce 'soc_device' initialization MT7620 SoCs have their own 'ralink_soc_info' structure with some information about the soc itself. In order to be able to retrieve this information from driver code and avoid architecture dependencies for retrieving these details introduce this 'soc_device'. Set 'data' pointer points to the struct 'ralink_soc_info' to be able to export also current soc information using this mechanism. We need to select 'SOC_BUS' in Kconfig configuration for these SoCs. Signed-off-by: Sergio Paracuellos Signed-off-by: Thomas Bogendoerfer --- arch/mips/ralink/Kconfig | 1 + arch/mips/ralink/mt7620.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index e8b8fb35d33d..08c012a2591f 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -44,6 +44,7 @@ choice bool "MT7620/8" select CPU_MIPSR2_IRQ_VI select HAVE_PCI + select SOC_BUS config SOC_MT7621 bool "MT7621" diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 8604d91f3375..4435f50b8d24 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include @@ -49,6 +51,8 @@ /* does the board have sdram or ddram */ static int dram_type; +static struct ralink_soc_info *soc_info_ptr; + static __init u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) { @@ -410,6 +414,44 @@ static const char __init *mt7620_get_soc_name(struct ralink_soc_info *soc_info) } } +static const char __init *mt7620_get_soc_id_name(void) +{ + if (ralink_soc == MT762X_SOC_MT7620A) + return "mt7620a"; + else if (ralink_soc == MT762X_SOC_MT7620N) + return "mt7620n"; + else if (ralink_soc == MT762X_SOC_MT7688) + return "mt7688"; + else if (ralink_soc == MT762X_SOC_MT7628AN) + return "mt7628n"; + else + return "invalid"; +} + +static int __init mt7620_soc_dev_init(void) +{ + struct soc_device *soc_dev; + struct soc_device_attribute *soc_dev_attr; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->family = "Ralink"; + soc_dev_attr->soc_id = mt7620_get_soc_id_name(); + + soc_dev_attr->data = soc_info_ptr; + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr); + return PTR_ERR(soc_dev); + } + + return 0; +} +device_initcall(mt7620_soc_dev_init); + void __init prom_soc_init(struct ralink_soc_info *soc_info) { const char *name = mt7620_get_soc_name(soc_info); @@ -444,4 +486,6 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); pr_info("Digital PMU set to %s control\n", (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); + + soc_info_ptr = soc_info; } -- cgit v1.2.3 From 9c99b4880d178a3cc6f42634b995d526a86f746b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:46:56 -0600 Subject: mips: Use of_property_read_bool() for boolean properties It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. Convert reading boolean properties to to of_property_read_bool(). Signed-off-by: Rob Herring Signed-off-by: Thomas Bogendoerfer --- arch/mips/pci/pci-lantiq.c | 2 +- arch/mips/pci/pci-rt3883.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index d967e4c0cf24..79e29bf42a24 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c @@ -118,7 +118,7 @@ static int ltq_pci_startup(struct platform_device *pdev) /* and enable the clocks */ clk_enable(clk_pci); - if (of_find_property(node, "lantiq,external-clock", NULL)) + if (of_property_read_bool(node, "lantiq,external-clock")) clk_enable(clk_external); else clk_disable(clk_external); diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c index d59888aaed81..4ac68a534e4f 100644 --- a/arch/mips/pci/pci-rt3883.c +++ b/arch/mips/pci/pci-rt3883.c @@ -419,7 +419,7 @@ static int rt3883_pci_probe(struct platform_device *pdev) /* find the interrupt controller child node */ for_each_child_of_node(np, child) { - if (of_get_property(child, "interrupt-controller", NULL)) { + if (of_property_read_bool(child, "interrupt-controller")) { rpc->intc_of_node = child; break; } -- cgit v1.2.3 From 1150e181a14666a77dde80252f2b5cbaea69a498 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Wed, 15 Mar 2023 14:45:48 +0100 Subject: MIPS: sibyte: remove no longer needed board_mem_region With the direct use of memblock interface board_mem_region is no longer needed. Signed-off-by: Thomas Bogendoerfer --- arch/mips/sibyte/common/cfe.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c index 1a504294d85f..2503f60271e8 100644 --- a/arch/mips/sibyte/common/cfe.c +++ b/arch/mips/sibyte/common/cfe.c @@ -35,11 +35,6 @@ #endif #endif -#define SIBYTE_MAX_MEM_REGIONS 8 -phys_addr_t board_mem_region_addrs[SIBYTE_MAX_MEM_REGIONS]; -phys_addr_t board_mem_region_sizes[SIBYTE_MAX_MEM_REGIONS]; -unsigned int board_mem_region_count; - int cfe_cons_handle; #ifdef CONFIG_BLK_DEV_INITRD @@ -141,16 +136,6 @@ static __init void prom_meminit(void) size -= 512; memblock_add(addr, size); } - board_mem_region_addrs[board_mem_region_count] = addr; - board_mem_region_sizes[board_mem_region_count] = size; - board_mem_region_count++; - if (board_mem_region_count == - SIBYTE_MAX_MEM_REGIONS) { - /* - * Too many regions. Need to configure more - */ - while(1); - } } } #ifdef CONFIG_BLK_DEV_INITRD -- cgit v1.2.3 From b984d7b56dfcf71648102e227120bdc247562d00 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Wed, 15 Mar 2023 14:55:09 +0100 Subject: MIPS: sibyte: Remove unused config option SIBYTE_BCM1x55 SIBYTE_BCM1x55 is not selected anywhere, so let's get rid of it. Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kbuild.platforms | 1 - arch/mips/sibyte/Kconfig | 13 +------------ arch/mips/sibyte/Makefile | 2 -- arch/mips/sibyte/Platform | 4 ---- arch/mips/sibyte/common/bus_watcher.c | 4 ++-- arch/mips/sibyte/common/cfe.c | 2 +- arch/mips/sibyte/common/sb_tbprof.c | 10 +++++----- arch/mips/sibyte/swarm/setup.c | 6 +++--- 8 files changed, 12 insertions(+), 30 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index 5d04438ee12e..caad195ba5c1 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -29,7 +29,6 @@ platform-$(CONFIG_SGI_IP30) += sgi-ip30/ platform-$(CONFIG_SGI_IP32) += sgi-ip32/ platform-$(CONFIG_SIBYTE_BCM112X) += sibyte/ platform-$(CONFIG_SIBYTE_SB1250) += sibyte/ -platform-$(CONFIG_SIBYTE_BCM1x55) += sibyte/ platform-$(CONFIG_SIBYTE_BCM1x80) += sibyte/ platform-$(CONFIG_SNI_RM) += sni/ platform-$(CONFIG_MACH_TX49XX) += txx9/ diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index 470d46183677..c437bc02dd08 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig @@ -58,16 +58,6 @@ config SIBYTE_BCM1x80 select SIBYTE_SB1xxx_SOC select SYS_SUPPORTS_SMP -config SIBYTE_BCM1x55 - bool - select CEVT_BCM1480 - select CSRC_BCM1480 - select HAVE_PCI - select IRQ_MIPS_CPU - select SIBYTE_SB1xxx_SOC - select SIBYTE_HAS_ZBUS_PROFILING - select SYS_SUPPORTS_SMP - config SIBYTE_SB1xxx_SOC bool select IRQ_MIPS_CPU @@ -143,8 +133,7 @@ config SIBYTE_CFE_CONSOLE config SIBYTE_BUS_WATCHER bool "Support for Bus Watcher statistics" depends on SIBYTE_SB1xxx_SOC && \ - (SIBYTE_BCM112X || SIBYTE_SB1250 || \ - SIBYTE_BCM1x55 || SIBYTE_BCM1x80) + (SIBYTE_BCM112X || SIBYTE_SB1250 || SIBYTE_BCM1x80) help Handle and keep statistics on the bus error interrupts (COR_ECC, BAD_ECC, IO_BUS). diff --git a/arch/mips/sibyte/Makefile b/arch/mips/sibyte/Makefile index d015c4d79c3e..ca0d57824d56 100644 --- a/arch/mips/sibyte/Makefile +++ b/arch/mips/sibyte/Makefile @@ -6,8 +6,6 @@ obj-$(CONFIG_SIBYTE_BCM112X) += sb1250/ obj-$(CONFIG_SIBYTE_BCM112X) += common/ obj-$(CONFIG_SIBYTE_SB1250) += sb1250/ obj-$(CONFIG_SIBYTE_SB1250) += common/ -obj-$(CONFIG_SIBYTE_BCM1x55) += bcm1480/ -obj-$(CONFIG_SIBYTE_BCM1x55) += common/ obj-$(CONFIG_SIBYTE_BCM1x80) += bcm1480/ obj-$(CONFIG_SIBYTE_BCM1x80) += common/ diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform index 65b2225b76b2..304b4d16dfbf 100644 --- a/arch/mips/sibyte/Platform +++ b/arch/mips/sibyte/Platform @@ -13,10 +13,6 @@ cflags-$(CONFIG_SIBYTE_SB1250) += \ -I$(srctree)/arch/mips/include/asm/mach-sibyte \ -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL -cflags-$(CONFIG_SIBYTE_BCM1x55) += \ - -I$(srctree)/arch/mips/include/asm/mach-sibyte \ - -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL - cflags-$(CONFIG_SIBYTE_BCM1x80) += \ -I$(srctree)/arch/mips/include/asm/mach-sibyte \ -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL diff --git a/arch/mips/sibyte/common/bus_watcher.c b/arch/mips/sibyte/common/bus_watcher.c index d43291473f76..a296d2c51841 100644 --- a/arch/mips/sibyte/common/bus_watcher.c +++ b/arch/mips/sibyte/common/bus_watcher.c @@ -24,7 +24,7 @@ #include #include #include -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#ifdef CONFIG_SIBYTE_BCM1x80 #include #endif @@ -71,7 +71,7 @@ void check_bus_watcher(void) #if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) /* Use non-destructive register */ status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG)); -#elif defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#elif defined(CONFIG_SIBYTE_BCM1x80) /* Use non-destructive register */ /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */ status = csr_in32(IOADDR(A_BCM1480_BUS_ERR_STATUS_DEBUG)); diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c index 2503f60271e8..2cb90dbbe843 100644 --- a/arch/mips/sibyte/common/cfe.c +++ b/arch/mips/sibyte/common/cfe.c @@ -295,7 +295,7 @@ void __init prom_init(void) #if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) register_smp_ops(&sb_smp_ops); #endif -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#ifdef CONFIG_SIBYTE_BCM1x80 register_smp_ops(&bcm1480_smp_ops); #endif } diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c index bc47681e825a..004a08469a39 100644 --- a/arch/mips/sibyte/common/sb_tbprof.c +++ b/arch/mips/sibyte/common/sb_tbprof.c @@ -23,7 +23,7 @@ #include #include -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#ifdef CONFIG_SIBYTE_BCM1x80 #include #include #include @@ -35,7 +35,7 @@ #error invalid SiByte UART configuration #endif -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#ifdef CONFIG_SIBYTE_BCM1x80 #undef K_INT_TRACE_FREEZE #define K_INT_TRACE_FREEZE K_BCM1480_INT_TRACE_FREEZE #undef K_INT_PERF_CNT @@ -157,7 +157,7 @@ static void arm_tb(void) * a previous interrupt request. This means that bus profiling * requires ALL of the SCD perf counters. */ -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#ifdef CONFIG_SIBYTE_BCM1x80 __raw_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | /* keep counters 0,2,3,4,5,6,7 as is */ V_SPC_CFG_SRC1(1), /* counter 1 counts cycles */ @@ -290,7 +290,7 @@ static int sbprof_zbprof_start(struct file *filp) * pass them through. I am exploiting my knowledge that * cp0_status masks out IP[5]. krw */ -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#ifdef CONFIG_SIBYTE_BCM1x80 __raw_writeq(K_BCM1480_INT_MAP_I3, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + ((K_BCM1480_INT_PERF_CNT & 0x3f) << 3))); @@ -343,7 +343,7 @@ static int sbprof_zbprof_start(struct file *filp) __raw_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7)); /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */ -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#ifdef CONFIG_SIBYTE_BCM1x80 __raw_writeq(1ULL << (K_BCM1480_INT_PERF_CNT & 0x3f), IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_TRACE_L))); #else diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 72a31eeeebba..9e7a1e305f61 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -24,7 +24,7 @@ #include #include #include -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#ifdef CONFIG_SIBYTE_BCM1x80 #include #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) #include @@ -34,7 +34,7 @@ #include #include -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#ifdef CONFIG_SIBYTE_BCM1x80 extern void bcm1480_setup(void); #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) extern void sb1250_setup(void); @@ -114,7 +114,7 @@ int update_persistent_clock64(struct timespec64 now) void __init plat_mem_setup(void) { -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) +#ifdef CONFIG_SIBYTE_BCM1x80 bcm1480_setup(); #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) sb1250_setup(); -- cgit v1.2.3 From a0136c28a2d8e03d0cb2f707cd1c837a8e0884e9 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Wed, 15 Mar 2023 15:12:02 +0100 Subject: MIPS: sibyte: Remove Sibyte CARMEL and CRHINE board support Looks like these boards were nether in active use, so let's remove them. Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 18 -------------- arch/mips/include/asm/sibyte/board.h | 6 +---- arch/mips/include/asm/sibyte/carmel.h | 45 ----------------------------------- arch/mips/include/asm/sibyte/swarm.h | 5 ---- arch/mips/sibyte/Kconfig | 9 ------- arch/mips/sibyte/Makefile | 4 ---- arch/mips/sibyte/Platform | 4 ---- arch/mips/sibyte/swarm/setup.c | 6 ----- 8 files changed, 1 insertion(+), 96 deletions(-) delete mode 100644 arch/mips/include/asm/sibyte/carmel.h (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6f275ace27be..88afd252bcc3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -794,24 +794,6 @@ config SGI_IP32 help If you want this kernel to run on SGI O2 workstation, say Y here. -config SIBYTE_CRHINE - bool "Sibyte BCM91120C-CRhine" - select BOOT_ELF32 - select SIBYTE_BCM1120 - select SWAP_IO_SPACE - select SYS_HAS_CPU_SB1 - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - -config SIBYTE_CARMEL - bool "Sibyte BCM91120x-Carmel" - select BOOT_ELF32 - select SIBYTE_BCM1120 - select SWAP_IO_SPACE - select SYS_HAS_CPU_SB1 - select SYS_SUPPORTS_BIG_ENDIAN - select SYS_SUPPORTS_LITTLE_ENDIAN - config SIBYTE_CRHONE bool "Sibyte BCM91125C-CRhone" select BOOT_ELF32 diff --git a/arch/mips/include/asm/sibyte/board.h b/arch/mips/include/asm/sibyte/board.h index 20fe2f16c97e..03463faa4244 100644 --- a/arch/mips/include/asm/sibyte/board.h +++ b/arch/mips/include/asm/sibyte/board.h @@ -7,7 +7,7 @@ #define _SIBYTE_BOARD_H #if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \ - defined(CONFIG_SIBYTE_CRHINE) || defined(CONFIG_SIBYTE_LITTLESUR) + defined(CONFIG_SIBYTE_LITTLESUR) #include #endif @@ -15,10 +15,6 @@ #include #endif -#ifdef CONFIG_SIBYTE_CARMEL -#include -#endif - #ifdef CONFIG_SIBYTE_BIGSUR #include #endif diff --git a/arch/mips/include/asm/sibyte/carmel.h b/arch/mips/include/asm/sibyte/carmel.h deleted file mode 100644 index c6730d7a6392..000000000000 --- a/arch/mips/include/asm/sibyte/carmel.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2002 Broadcom Corporation - */ -#ifndef __ASM_SIBYTE_CARMEL_H -#define __ASM_SIBYTE_CARMEL_H - -#include -#include - -#define SIBYTE_BOARD_NAME "Carmel" - -#define GPIO_PHY_INTERRUPT 2 -#define GPIO_NONMASKABLE_INT 3 -#define GPIO_CF_INSERTED 6 -#define GPIO_MONTEREY_RESET 7 -#define GPIO_QUADUART_INT 8 -#define GPIO_CF_INT 9 -#define GPIO_FPGA_CCLK 10 -#define GPIO_FPGA_DOUT 11 -#define GPIO_FPGA_DIN 12 -#define GPIO_FPGA_PGM 13 -#define GPIO_FPGA_DONE 14 -#define GPIO_FPGA_INIT 15 - -#define LEDS_CS 2 -#define LEDS_PHYS 0x100C0000 -#define MLEDS_CS 3 -#define MLEDS_PHYS 0x100A0000 -#define UART_CS 4 -#define UART_PHYS 0x100D0000 -#define ARAVALI_CS 5 -#define ARAVALI_PHYS 0x11000000 -#define IDE_CS 6 -#define IDE_PHYS 0x100B0000 -#define ARAVALI2_CS 7 -#define ARAVALI2_PHYS 0x100E0000 - -#if defined(CONFIG_SIBYTE_CARMEL) -#define K_GPIO_GB_IDE 9 -#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) -#endif - - -#endif /* __ASM_SIBYTE_CARMEL_H */ diff --git a/arch/mips/include/asm/sibyte/swarm.h b/arch/mips/include/asm/sibyte/swarm.h index 947122f487ed..49ea7a645c15 100644 --- a/arch/mips/include/asm/sibyte/swarm.h +++ b/arch/mips/include/asm/sibyte/swarm.h @@ -24,11 +24,6 @@ #define SIBYTE_HAVE_PCMCIA 0 #define SIBYTE_HAVE_IDE 0 #endif -#ifdef CONFIG_SIBYTE_CRHINE -#define SIBYTE_BOARD_NAME "BCM91120C (CRhine)" -#define SIBYTE_HAVE_PCMCIA 0 -#define SIBYTE_HAVE_IDE 0 -#endif /* Generic bus chip selects */ #define LEDS_CS 3 diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index c437bc02dd08..c4596d49edf1 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig @@ -10,15 +10,6 @@ config SIBYTE_SB1250 select SIBYTE_SB1xxx_SOC select SYS_SUPPORTS_SMP -config SIBYTE_BCM1120 - bool - select CEVT_SB1250 - select CSRC_SB1250 - select IRQ_MIPS_CPU - select SIBYTE_BCM112X - select SIBYTE_HAS_ZBUS_PROFILING - select SIBYTE_SB1xxx_SOC - config SIBYTE_BCM1125 bool select CEVT_SB1250 diff --git a/arch/mips/sibyte/Makefile b/arch/mips/sibyte/Makefile index ca0d57824d56..47078353fe8a 100644 --- a/arch/mips/sibyte/Makefile +++ b/arch/mips/sibyte/Makefile @@ -10,15 +10,11 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += bcm1480/ obj-$(CONFIG_SIBYTE_BCM1x80) += common/ # -# Sibyte BCM91120x (Carmel) board -# Sibyte BCM91120C (CRhine) board # Sibyte BCM91125C (CRhone) board # Sibyte BCM91125E (Rhone) board # Sibyte SWARM board # Sibyte BCM91x80 (BigSur) board # -obj-$(CONFIG_SIBYTE_CARMEL) += swarm/ -obj-$(CONFIG_SIBYTE_CRHINE) += swarm/ obj-$(CONFIG_SIBYTE_CRHONE) += swarm/ obj-$(CONFIG_SIBYTE_RHONE) += swarm/ obj-$(CONFIG_SIBYTE_SENTOSA) += swarm/ diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform index 304b4d16dfbf..937108e41f13 100644 --- a/arch/mips/sibyte/Platform +++ b/arch/mips/sibyte/Platform @@ -18,16 +18,12 @@ cflags-$(CONFIG_SIBYTE_BCM1x80) += \ -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL # -# Sibyte BCM91120x (Carmel) board -# Sibyte BCM91120C (CRhine) board # Sibyte BCM91125C (CRhone) board # Sibyte BCM91125E (Rhone) board # Sibyte BCM91250A (SWARM) board # Sibyte BCM91250C2 (LittleSur) board # Sibyte BCM91x80 (BigSur) board # -load-$(CONFIG_SIBYTE_CARMEL) := 0xffffffff80100000 -load-$(CONFIG_SIBYTE_CRHINE) := 0xffffffff80100000 load-$(CONFIG_SIBYTE_CRHONE) := 0xffffffff80100000 load-$(CONFIG_SIBYTE_RHONE) := 0xffffffff80100000 load-$(CONFIG_SIBYTE_SENTOSA) := 0xffffffff80100000 diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 9e7a1e305f61..76683993cdd3 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -146,12 +146,6 @@ void __init plat_mem_setup(void) #ifdef LEDS_PHYS -#ifdef CONFIG_SIBYTE_CARMEL -/* XXXKW need to detect Monterey/LittleSur/etc */ -#undef LEDS_PHYS -#define LEDS_PHYS MLEDS_PHYS -#endif - void setleds(char *str) { void *reg; -- cgit v1.2.3 From 0345234720ca5601b59f20570f71139f5ad4d229 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Wed, 15 Mar 2023 15:21:24 +0100 Subject: MIPS: sibyte: Replace BCM1125H with SB1250 option SIBYTE_BCM1125H is identical to SIBYTE_SB1250, so remove one of them. Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 2 +- arch/mips/sibyte/Kconfig | 11 ----------- 2 files changed, 1 insertion(+), 12 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 88afd252bcc3..fd7ed68cdb91 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -807,7 +807,7 @@ config SIBYTE_CRHONE config SIBYTE_RHONE bool "Sibyte BCM91125E-Rhone" select BOOT_ELF32 - select SIBYTE_BCM1125H + select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 select SYS_SUPPORTS_BIG_ENDIAN diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index c4596d49edf1..5fb92fe84149 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig @@ -20,17 +20,6 @@ config SIBYTE_BCM1125 select SIBYTE_HAS_ZBUS_PROFILING select SIBYTE_SB1xxx_SOC -config SIBYTE_BCM1125H - bool - select CEVT_SB1250 - select CSRC_SB1250 - select HAVE_PCI - select IRQ_MIPS_CPU - select SIBYTE_BCM112X - select SIBYTE_ENABLE_LDT_IF_PCI - select SIBYTE_HAS_ZBUS_PROFILING - select SIBYTE_SB1xxx_SOC - config SIBYTE_BCM112X bool select CEVT_SB1250 -- cgit v1.2.3 From a45e5fe792349315827b483eb23b307df47c6c6c Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Thu, 16 Mar 2023 12:49:52 +0100 Subject: MIPS: ath79: remove obsolete ATH79_DEV_* configs Commit 85b9686dae30 ("MIPS: ath79: drop platform device registration code") removes all files arch/mips/ath79/dev-*.[ch], adjusts the Makefile, but misses to adjust the Kconfig file. Hence, since then, the configs ATH79_DEV_* are really dead. Commit 3a77e0d75eed ("MIPS: ath79: drop machfiles") already removes all configs that select ATH79_DEV_* config. So at that point, they was not a way to enable them with a kernel build configuration. Remove these obsolete ATH79_DEV_* configs. Signed-off-by: Lukas Bulwahn Signed-off-by: Thomas Bogendoerfer --- arch/mips/ath79/Kconfig | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig index 7367416642cb..04154128c4de 100644 --- a/arch/mips/ath79/Kconfig +++ b/arch/mips/ath79/Kconfig @@ -29,20 +29,4 @@ config SOC_QCA955X config PCI_AR724X def_bool n -config ATH79_DEV_GPIO_BUTTONS - def_bool n - -config ATH79_DEV_LEDS_GPIO - def_bool n - -config ATH79_DEV_SPI - def_bool n - -config ATH79_DEV_USB - def_bool n - -config ATH79_DEV_WMAC - depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X) - def_bool n - endif -- cgit v1.2.3 From d703e5a6ffa73fba8e9023190c53d4458cc09a06 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Fri, 24 Mar 2023 11:08:48 +0100 Subject: mips: Remove obsolete configs IRQ_MSP_CIC and IRQ_MSP_SLP Commit 1b00767fd8e1 ("MIPS: Remove PMC MSP71xx platform") removes all uses of the config IRQ_MSP_CIC and IRQ_MSP_SLP. Remove these two obsolete configs IRQ_MSP_CIC and IRQ_MSP_SLP. Signed-off-by: Lukas Bulwahn Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index fd7ed68cdb91..b91086b0ae22 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1164,12 +1164,6 @@ config SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_HUGE_TLB_SUPPORT def_bool HUGETLB_PAGE || TRANSPARENT_HUGEPAGE -config IRQ_MSP_SLP - bool - -config IRQ_MSP_CIC - bool - config IRQ_TXX9 bool -- cgit v1.2.3 From ed6a0b6e9fd78e167d0488331d1695c6c84192be Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Sun, 19 Mar 2023 11:31:48 -0500 Subject: MIPS: octeon: Use of_address_to_resource() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace of_get_address() and of_translate_address() calls with single call to of_address_to_resource(). Signed-off-by: Rob Herring Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/octeon-irq.c | 35 +++++++++++++++-------------------- 1 file changed, 15 insertions(+), 20 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index fd8043f6ff8a..064e2409377a 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -2290,7 +2290,7 @@ static irqreturn_t octeon_irq_cib_handler(int my_irq, void *data) static int __init octeon_irq_init_cib(struct device_node *ciu_node, struct device_node *parent) { - const __be32 *addr; + struct resource res; u32 val; struct octeon_irq_cib_host_data *host_data; int parent_irq; @@ -2309,21 +2309,19 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node, return -ENOMEM; raw_spin_lock_init(&host_data->lock); - addr = of_get_address(ciu_node, 0, NULL, NULL); - if (!addr) { + r = of_address_to_resource(ciu_node, 0, &res); + if (r) { pr_err("ERROR: Couldn't acquire reg(0) %pOFn\n", ciu_node); - return -EINVAL; + return r; } - host_data->raw_reg = (u64)phys_to_virt( - of_translate_address(ciu_node, addr)); + host_data->raw_reg = (u64)phys_to_virt(res.start); - addr = of_get_address(ciu_node, 1, NULL, NULL); - if (!addr) { + r = of_address_to_resource(ciu_node, 1, &res); + if (r) { pr_err("ERROR: Couldn't acquire reg(1) %pOFn\n", ciu_node); - return -EINVAL; + return r; } - host_data->en_reg = (u64)phys_to_virt( - of_translate_address(ciu_node, addr)); + host_data->en_reg = (u64)phys_to_virt(res.start); r = of_property_read_u32(ciu_node, "cavium,max-bits", &val); if (r) { @@ -2874,11 +2872,11 @@ static struct irq_chip octeon_irq_chip_ciu3_mbox = { static int __init octeon_irq_init_ciu3(struct device_node *ciu_node, struct device_node *parent) { - int i; + int i, ret; int node; struct irq_domain *domain; struct octeon_ciu3_info *ciu3_info; - const __be32 *zero_addr; + struct resource res; u64 base_addr; union cvmx_ciu3_const consts; @@ -2888,14 +2886,11 @@ static int __init octeon_irq_init_ciu3(struct device_node *ciu_node, if (!ciu3_info) return -ENOMEM; - zero_addr = of_get_address(ciu_node, 0, NULL, NULL); - if (WARN_ON(!zero_addr)) - return -EINVAL; - - base_addr = of_translate_address(ciu_node, zero_addr); - base_addr = (u64)phys_to_virt(base_addr); + ret = of_address_to_resource(ciu_node, 0, &res); + if (WARN_ON(ret)) + return ret; - ciu3_info->ciu3_addr = base_addr; + ciu3_info->ciu3_addr = base_addr = phys_to_virt(res.start); ciu3_info->node = node; consts.u64 = cvmx_read_csr(base_addr + CIU3_CONST); -- cgit v1.2.3 From 6be87d61c427e63c33d9cea8dc2e20cd06700882 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 22 Feb 2023 13:24:23 +0000 Subject: MIPS: Always select ARCH_HAS_SETUP_DMA_OPS arch_setup_dma_ops on MIPS sets coherency information in struct device. It's essential for per-device coherency to work. Select it for all non-coherent platforms. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b91086b0ae22..fa72d906916f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -134,7 +134,6 @@ choice config MIPS_GENERIC_KERNEL bool "Generic board-agnostic MIPS kernel" - select ARCH_HAS_SETUP_DMA_OPS select MIPS_GENERIC select BOOT_RAW select BUILTIN_DTB @@ -1069,6 +1068,7 @@ config DMA_NONCOHERENT # by pgprot_writcombine can be mixed, and the latter sometimes provides # significant advantages. # + select ARCH_HAS_SETUP_DMA_OPS select ARCH_HAS_DMA_WRITE_COMBINE select ARCH_HAS_DMA_PREP_COHERENT select ARCH_HAS_SYNC_DMA_FOR_DEVICE -- cgit v1.2.3 From e0b7fd1207a8ec47091439fb62dd87ca6f5b4ad3 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 22 Feb 2023 13:24:24 +0000 Subject: MIPS: Always select ARCH_HAS_SYNC_DMA_FOR_CPU for noncoherent platforms As now we are telling the necessity of post DMA flush per CPU type, there is no need to select ARCH_HAS_SYNC_DMA_FOR_CPU on per platform bias, just select it unconditionally and we can sort it at runtime. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index fa72d906916f..2082efdb411b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -115,7 +115,6 @@ config MACH_INGENIC select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_ZBOOT select DMA_NONCOHERENT - select ARCH_HAS_SYNC_DMA_FOR_CPU select IRQ_MIPS_CPU select PINCTRL select GPIOLIB @@ -1071,6 +1070,7 @@ config DMA_NONCOHERENT select ARCH_HAS_SETUP_DMA_OPS select ARCH_HAS_DMA_WRITE_COMBINE select ARCH_HAS_DMA_PREP_COHERENT + select ARCH_HAS_SYNC_DMA_FOR_CPU select ARCH_HAS_SYNC_DMA_FOR_DEVICE select ARCH_HAS_DMA_SET_UNCACHED select DMA_NONCOHERENT_MMAP @@ -1828,11 +1828,9 @@ config SYS_HAS_CPU_MIPS32_R3_5 config SYS_HAS_CPU_MIPS32_R5 bool - select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT config SYS_HAS_CPU_MIPS32_R6 bool - select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT config SYS_HAS_CPU_MIPS64_R1 bool @@ -1842,15 +1840,12 @@ config SYS_HAS_CPU_MIPS64_R2 config SYS_HAS_CPU_MIPS64_R5 bool - select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT config SYS_HAS_CPU_MIPS64_R6 bool - select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT config SYS_HAS_CPU_P5600 bool - select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT config SYS_HAS_CPU_R3000 bool @@ -1875,7 +1870,6 @@ config SYS_HAS_CPU_NEVADA config SYS_HAS_CPU_R10000 bool - select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT config SYS_HAS_CPU_RM7000 bool @@ -1904,7 +1898,6 @@ config SYS_HAS_CPU_BMIPS4380 config SYS_HAS_CPU_BMIPS5000 bool select SYS_HAS_CPU_BMIPS - select ARCH_HAS_SYNC_DMA_FOR_CPU # # CPU may reorder R->R, R->W, W->R, W->W -- cgit v1.2.3 From 600efe35d54961dd026f04c6ea5b4074b3284c87 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 22 Feb 2023 13:24:25 +0000 Subject: MIPS: c-r4k: Always install dma flush functions As nowadays DMA coherence is managed per device, it is possible to have a system that is defaulted to coherent dma but still have noncoherent device that needs to use those flush functions. Just install them unconditionally. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/c-r4k.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index a549fa98c2f4..7d447050a20b 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1867,15 +1867,9 @@ void r4k_cache_init(void) __local_flush_icache_user_range = local_r4k_flush_icache_user_range; #ifdef CONFIG_DMA_NONCOHERENT - if (dma_default_coherent) { - _dma_cache_wback_inv = (void *)cache_noop; - _dma_cache_wback = (void *)cache_noop; - _dma_cache_inv = (void *)cache_noop; - } else { - _dma_cache_wback_inv = r4k_dma_cache_wback_inv; - _dma_cache_wback = r4k_dma_cache_wback_inv; - _dma_cache_inv = r4k_dma_cache_inv; - } + _dma_cache_wback_inv = r4k_dma_cache_wback_inv; + _dma_cache_wback = r4k_dma_cache_wback_inv; + _dma_cache_inv = r4k_dma_cache_inv; #endif /* CONFIG_DMA_NONCOHERENT */ build_clear_page(); -- cgit v1.2.3 From 101f26c72825c5dba1dfe826e4202a9a04b435c6 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 27 Mar 2023 10:35:22 +0200 Subject: MIPS: octeon: Fix compile error Commit ed6a0b6e9fd7 ("MIPS: octeon: Use of_address_to_resource()") lost a cast, which causes a compile error. Fixes: ed6a0b6e9fd7 ("MIPS: octeon: Use of_address_to_resource()") Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/octeon-irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 064e2409377a..8425a6b38aa2 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -2890,7 +2890,7 @@ static int __init octeon_irq_init_ciu3(struct device_node *ciu_node, if (WARN_ON(ret)) return ret; - ciu3_info->ciu3_addr = base_addr = phys_to_virt(res.start); + ciu3_info->ciu3_addr = base_addr = (u64)phys_to_virt(res.start); ciu3_info->node = node; consts.u64 = cvmx_read_csr(base_addr + CIU3_CONST); -- cgit v1.2.3 From 393a759647061bc29c1d62f83c7d36cacc912a89 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:40 +0100 Subject: MIPS: Move declaration of bcache ops to cache.c bcache is not tied to CPU's cache interface. Just move those declaration to cache.c so it can be avaialble to CPU with all cache types. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/cache.h | 2 ++ arch/mips/mm/c-r4k.c | 14 -------------- arch/mips/mm/cache.c | 19 +++++++++++++++++++ 3 files changed, 21 insertions(+), 14 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h index 29187e12b861..3424a7908c0f 100644 --- a/arch/mips/include/asm/cache.h +++ b/arch/mips/include/asm/cache.h @@ -16,4 +16,6 @@ #define __read_mostly __section(".data..read_mostly") +extern void cache_noop(void); + #endif /* _ASM_CACHE_H */ diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 7d447050a20b..5599b9c9a737 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -110,20 +110,6 @@ static unsigned long dcache_size __read_mostly; static unsigned long vcache_size __read_mostly; static unsigned long scache_size __read_mostly; -/* - * Dummy cache handling routines for machines without boardcaches - */ -static void cache_noop(void) {} - -static struct bcache_ops no_sc_ops = { - .bc_enable = (void *)cache_noop, - .bc_disable = (void *)cache_noop, - .bc_wback_inv = (void *)cache_noop, - .bc_inv = (void *)cache_noop -}; - -struct bcache_ops *bcops = &no_sc_ops; - #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 11b3e7ddafd5..7dba4b5c02c3 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -56,6 +57,24 @@ EXPORT_SYMBOL_GPL(local_flush_data_cache_page); EXPORT_SYMBOL(flush_data_cache_page); EXPORT_SYMBOL(flush_icache_all); +/* + * Dummy cache handling routine + */ + +void cache_noop(void) {} + +#ifdef CONFIG_BOARD_SCACHE + +static struct bcache_ops no_sc_ops = { + .bc_enable = (void *)cache_noop, + .bc_disable = (void *)cache_noop, + .bc_wback_inv = (void *)cache_noop, + .bc_inv = (void *)cache_noop +}; + +struct bcache_ops *bcops = &no_sc_ops; +#endif + #ifdef CONFIG_DMA_NONCOHERENT /* DMA cache operations. */ -- cgit v1.2.3 From aa45787c0db0a5f7b21bd16b917ff44761a2c6ac Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:41 +0100 Subject: MIPS: smp-cps: Disable coherence setup for unsupported ISA We don't know how to do coherence setup on ISA before MIPS Release 1. As CPS support only servers simulation purpose on those cores, and simulators are always coherent, just disable initialization code and provide user a warning in case coherence is not setup properly. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/cps-vec.S | 5 +++++ arch/mips/kernel/smp-cps.c | 5 +++++ 2 files changed, 10 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 8ef492da827f..64ecfdac6580 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -116,6 +116,8 @@ not_nmi: li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS mtc0 t0, CP0_STATUS + /* We don't know how to do coherence setup on earlier ISA */ +#if MIPS_ISA_REV > 0 /* Skip cache & coherence setup if we're already coherent */ lw s7, GCR_CL_COHERENCE_OFS(s1) bnez s7, 1f @@ -129,6 +131,7 @@ not_nmi: li t0, 0xff sw t0, GCR_CL_COHERENCE_OFS(s1) ehb +#endif /* MIPS_ISA_REV > 0 */ /* Set Kseg0 CCA to that in s0 */ 1: mfc0 t0, CP0_CONFIG @@ -515,6 +518,7 @@ LEAF(mips_cps_boot_vpes) nop END(mips_cps_boot_vpes) +#if MIPS_ISA_REV > 0 LEAF(mips_cps_cache_init) /* * Clear the bits used to index the caches. Note that the architecture @@ -588,6 +592,7 @@ dcache_done: jr ra nop END(mips_cps_cache_init) +#endif /* MIPS_ISA_REV > 0 */ #if defined(CONFIG_MIPS_CPS_PM) && defined(CONFIG_CPU_PM) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 4fc288bb85b9..f968a319d87f 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -361,6 +361,8 @@ out: static void cps_init_secondary(void) { + int core = cpu_core(¤t_cpu_data); + /* Disable MT - we only want to run 1 TC per VPE */ if (cpu_has_mipsmt) dmt(); @@ -376,6 +378,9 @@ static void cps_init_secondary(void) BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); } + if (core > 0 && !read_gcr_cl_coherence()) + pr_warn("Core %u is not in coherent domain\n", core); + if (cpu_has_veic) clear_c0_status(ST0_IM); else -- cgit v1.2.3 From e1aa1dfef69320141f5d00eddbf279b41e70d4e7 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:42 +0100 Subject: MIPS: mips-cm: Check availability of config registers Prevent reading unsupported config register during probing process. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/mips-cm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index b4f7d950c846..3f00788b0871 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -181,11 +181,16 @@ static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags); phys_addr_t __mips_cm_phys_base(void) { - u32 config3 = read_c0_config3(); unsigned long cmgcr; /* Check the CMGCRBase register is implemented */ - if (!(config3 & MIPS_CONF3_CMGCR)) + if (!(read_c0_config() & MIPS_CONF_M)) + return 0; + + if (!(read_c0_config2() & MIPS_CONF_M)) + return 0; + + if (!(read_c0_config3() & MIPS_CONF3_CMGCR)) return 0; /* Read the address from CMGCRBase */ -- cgit v1.2.3 From 918d779569dafd81fce4257c552aa4205c918c4a Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:43 +0100 Subject: MIPS: Octeon: Opt-out 4k_cache feature Octeon has a different cache interface with traditional R4K one, just opt-out this flag for octeon to avoid run R4K cache initialization code accidentally. Also remove ISA level assumption for 4k cache. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/cpu-features.h | 2 +- arch/mips/kernel/cpu-probe.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index c0983130a44c..c613426b0bfc 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -118,7 +118,7 @@ #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) #endif #ifndef cpu_has_4k_cache -#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) +#define cpu_has_4k_cache __opt(MIPS_CPU_4K_CACHE) #endif #ifndef cpu_has_octeon_cache #define cpu_has_octeon_cache 0 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 7ddf07f255f3..6d15a398d389 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1602,6 +1602,8 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); + /* Octeon has different cache interface */ + c->options &= ~MIPS_CPU_4K_CACHE; switch (c->processor_id & PRID_IMP_MASK) { case PRID_IMP_CAVIUM_CN38XX: case PRID_IMP_CAVIUM_CN31XX: -- cgit v1.2.3 From f641519409a73403ee6612b8648b95a688ab85c2 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:44 +0100 Subject: MIPS: cpu-features: Enable octeon_cache by cpu_type cpu_has_octeon_cache was tied to 0 for generic cpu-features, whith this generic kernel built for octeon CPU won't boot. Just enable this flag by cpu_type. It won't hurt orther platforms because compiler will eliminate the code path on other processors. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/cpu-features.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index c613426b0bfc..51a1737b03d0 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -121,7 +121,24 @@ #define cpu_has_4k_cache __opt(MIPS_CPU_4K_CACHE) #endif #ifndef cpu_has_octeon_cache -#define cpu_has_octeon_cache 0 +#define cpu_has_octeon_cache \ +({ \ + int __res; \ + \ + switch (current_cpu_type()) { \ + case CPU_CAVIUM_OCTEON: \ + case CPU_CAVIUM_OCTEON_PLUS: \ + case CPU_CAVIUM_OCTEON2: \ + case CPU_CAVIUM_OCTEON3: \ + __res = 1; \ + break; \ + \ + default: \ + __res = 0; \ + } \ + \ + __res; \ +}) #endif /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ #ifndef cpu_has_fpu -- cgit v1.2.3 From 6e90049162b92e683641966e4cdc67febe3c8fc5 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:45 +0100 Subject: MIPS: c-octeon: Provide alternative SMP cache flush function Currently c-octeon relies on octeon's own smp function to flush I-Cache. However this function is not available on generic platform. Just use smp_call_function_many on generic platform. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/c-octeon.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index c7ed589de882..b7393b61cfa7 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -83,8 +83,13 @@ static void octeon_flush_icache_all_cores(struct vm_area_struct *vma) else mask = *cpu_online_mask; cpumask_clear_cpu(cpu, &mask); +#ifdef CONFIG_CAVIUM_OCTEON_SOC for_each_cpu(cpu, &mask) octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH); +#else + smp_call_function_many(&mask, (smp_call_func_t)octeon_local_flush_icache, + NULL, 1); +#endif preempt_enable(); #endif -- cgit v1.2.3 From b6007ff809682350515936539eb91a2e8a5f799c Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:46 +0100 Subject: MIPS: Octeon: Allow CVMSEG to be disabled Don't include cvmseg states into thread_status when CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE is not defined or 0. Fix compile for kernel without this feature. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/processor.h | 7 ++++++- arch/mips/kernel/asm-offsets.c | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 3fde1ff72bd1..ae2cd37a38f0 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -202,11 +202,13 @@ struct octeon_cop2_state { #define COP2_INIT \ .cp2 = {0,}, +#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ + CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 struct octeon_cvmseg_state { unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE] [cpu_dcache_line_size() / sizeof(unsigned long)]; }; - +#endif #else #define COP2_INIT #endif @@ -263,7 +265,10 @@ struct thread_struct { unsigned long trap_nr; #ifdef CONFIG_CPU_CAVIUM_OCTEON struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128))); +#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ + CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128))); +#endif #endif struct mips_abi *abi; }; diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index c4501897b870..40fd4051bb3d 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -306,7 +306,10 @@ void output_octeon_cop2_state_defines(void) OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw); OFFSET(OCTEON_CP2_SHA3, octeon_cop2_state, cop2_sha3); OFFSET(THREAD_CP2, task_struct, thread.cp2); +#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ + CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg); +#endif BLANK(); } #endif -- cgit v1.2.3 From 194a835210521282ad31e8f7047556318611f596 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:47 +0100 Subject: MIPS: Loongson: Move arch cflags to MIPS top level Makefile Arch cflags should be independent to Platform. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Makefile | 38 ++++++++++++++++++++++++++++++++++++++ arch/mips/loongson2ef/Platform | 35 ----------------------------------- arch/mips/loongson64/Platform | 16 ---------------- 3 files changed, 38 insertions(+), 51 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 04e46ec24319..a7a4ee66a9d3 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -181,9 +181,47 @@ endif cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap +# Some -march= flags enable MMI instructions, and GCC complains about that +# support being enabled alongside -msoft-float. Thus explicitly disable MMI. +cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi) +ifdef CONFIG_CPU_LOONGSON64 +cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap +cflags-$(CONFIG_CC_IS_GCC) += -march=loongson3a +cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2 +endif +cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-mno-loongson-mmi) + cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) +ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS +cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop +cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump +endif + +# +# Some versions of binutils, not currently mainline as of 2019/02/04, support +# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction +# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a +# description). +# +# We disable this in order to prevent the assembler meddling with the +# instruction that labels refer to, ie. if we label an ll instruction: +# +# 1: ll v0, 0(a0) +# +# ...then with the assembler fix applied the label may actually point at a sync +# instruction inserted by the assembler, and if we were using the label in an +# exception table the table would no longer contain the address of the ll +# instruction. +# +# Avoid this by explicitly disabling that assembler behaviour. If upstream +# binutils does not merge support for the flag then we can revisit & remove +# this later - for now it ensures vendor toolchains don't cause problems. +# +cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,) # For smartmips configurations, there are hundreds of warnings due to ISA overrides # in assembly and header files. smartmips is only supported for MIPS32r1 onwards diff --git a/arch/mips/loongson2ef/Platform b/arch/mips/loongson2ef/Platform index c6f7a4b95997..d446b705fba4 100644 --- a/arch/mips/loongson2ef/Platform +++ b/arch/mips/loongson2ef/Platform @@ -2,41 +2,6 @@ # Loongson Processors' Support # -cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -# -# Some versions of binutils, not currently mainline as of 2019/02/04, support -# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction -# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a -# description). -# -# We disable this in order to prevent the assembler meddling with the -# instruction that labels refer to, ie. if we label an ll instruction: -# -# 1: ll v0, 0(a0) -# -# ...then with the assembler fix applied the label may actually point at a sync -# instruction inserted by the assembler, and if we were using the label in an -# exception table the table would no longer contain the address of the ll -# instruction. -# -# Avoid this by explicitly disabling that assembler behaviour. If upstream -# binutils does not merge support for the flag then we can revisit & remove -# this later - for now it ensures vendor toolchains don't cause problems. -# -cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-Wa$(comma)-mno-fix-loongson3-llsc,) - -# Enable the workarounds for Loongson2f -ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS -cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop -cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump -endif - -# Some -march= flags enable MMI instructions, and GCC complains about that -# support being enabled alongside -msoft-float. Thus explicitly disable MMI. -cflags-y += $(call cc-option,-mno-loongson-mmi) - # # Loongson Machines' Support # diff --git a/arch/mips/loongson64/Platform b/arch/mips/loongson64/Platform index 473404cae1c4..49c9889e3d56 100644 --- a/arch/mips/loongson64/Platform +++ b/arch/mips/loongson64/Platform @@ -1,19 +1,3 @@ -# -# Loongson Processors' Support -# - - -cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap - -ifdef CONFIG_CPU_LOONGSON64 -cflags-$(CONFIG_CC_IS_GCC) += -march=loongson3a -cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2 -endif - -# Some -march= flags enable MMI instructions, and GCC complains about that -# support being enabled alongside -msoft-float. Thus explicitly disable MMI. -cflags-y += $(call cc-option,-mno-loongson-mmi) - # # Loongson Machines' Support # -- cgit v1.2.3 From 0c6ff92773a9c004c44af47b0609f67dcc97ba82 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:48 +0100 Subject: MIPS: Loongson: Don't select platform features with CPU ARCH_HAS_PHYS_TO_DMA and GPIOLIB are all platform level features they shouldn't be selected with CPU. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 2 -- arch/mips/loongson2ef/Kconfig | 3 +++ 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2082efdb411b..54a6ba91226e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1341,7 +1341,6 @@ config CPU_LOONGSON2F bool "Loongson 2F" depends on SYS_HAS_CPU_LOONGSON2F select CPU_LOONGSON2EF - select GPIOLIB help The Loongson 2F processor implements the MIPS III instruction set with many extensions. @@ -1763,7 +1762,6 @@ config CPU_LOONGSON2EF select CPU_SUPPORTS_64BIT_KERNEL select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES - select ARCH_HAS_PHYS_TO_DMA config CPU_LOONGSON32 bool diff --git a/arch/mips/loongson2ef/Kconfig b/arch/mips/loongson2ef/Kconfig index 96dc6eba4310..f93eb6f42238 100644 --- a/arch/mips/loongson2ef/Kconfig +++ b/arch/mips/loongson2ef/Kconfig @@ -7,6 +7,7 @@ choice config LEMOTE_FULOONG2E bool "Lemote Fuloong(2e) mini-PC" select ARCH_SPARSEMEM_ENABLE + select ARCH_HAS_PHYS_TO_DMA select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_SERIO select CEVT_R4K @@ -36,6 +37,7 @@ config LEMOTE_FULOONG2E config LEMOTE_MACH2F bool "Lemote Loongson 2F family machines" select ARCH_SPARSEMEM_ENABLE + select ARCH_HAS_PHYS_TO_DMA select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_SERIO select BOARD_SCACHE @@ -46,6 +48,7 @@ config LEMOTE_MACH2F select CSRC_R4K if ! MIPS_EXTERNAL_TIMER select DMA_NONCOHERENT select GENERIC_ISA_DMA_SUPPORT_BROKEN + select GPIOLIB select FORCE_PCI select I8259 select IRQ_MIPS_CPU -- cgit v1.2.3 From 78073b8f1ffe4085309808815746403209bfd6bc Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:49 +0100 Subject: MIPS: Octeon: Disable CVMSEG by default on other platforms QEMU can't emulate CVMSEG on generic platform for now. Just disable it by default. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/cavium-octeon/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index c1899f109e19..450e979ef5d9 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -14,7 +14,8 @@ config CAVIUM_CN63XXP1 config CAVIUM_OCTEON_CVMSEG_SIZE int "Number of L1 cache lines reserved for CVMSEG memory" range 0 54 - default 1 + default 0 if !CAVIUM_OCTEON_SOC + default 1 if CAVIUM_OCTEON_SOC help CVMSEG LM is a segment that accesses portions of the dcache as a local memory; the larger CVMSEG is, the smaller the cache is. -- cgit v1.2.3 From 03be534e1bac6d92cbcebdddfc4242e1e3588350 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:50 +0100 Subject: MIPS: Add board config for virt board Aligned with QEMU MIPS virt board. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/configs/generic/board-virt.config | 38 +++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 arch/mips/configs/generic/board-virt.config (limited to 'arch/mips') diff --git a/arch/mips/configs/generic/board-virt.config b/arch/mips/configs/generic/board-virt.config new file mode 100644 index 000000000000..5594f9e5c3a8 --- /dev/null +++ b/arch/mips/configs/generic/board-virt.config @@ -0,0 +1,38 @@ +CONFIG_COMMON_CLK=y + +CONFIG_GOLDFISH=y +CONFIG_GOLDFISH_PIC=y + +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_HOST_GENERIC=y + +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_SYSCON_REBOOT_MODE=y + +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_GOLDFISH=y + +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y + +CONFIG_MTD=y +CONFIG_MTD_CFI=y + +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_XHCI_HCD=y + +CONFIG_VIRTIO_CONSOLE=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTIO_NET=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y -- cgit v1.2.3 From de34007751aaba992373f2d659001a846aeb8811 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:51 +0100 Subject: MIPS: generic: Enable all CPUs supported by virt board in Kconfig Enable extra CPUs that may be supported by virt board, including R4x00 (R4000 in QEMU), Cavium Octeon (Octeon68XX in QEMU), loongson2e, loongson2f. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 54a6ba91226e..a975f140ae82 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -153,12 +153,16 @@ config MIPS_GENERIC_KERNEL select PCI_DRIVERS_GENERIC select SMP_UP if SMP select SWAP_IO_SPACE + select SYS_HAS_CPU_CAVIUM_OCTEON + select SYS_HAS_CPU_LOONGSON2E + select SYS_HAS_CPU_LOONGSON2F select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_CPU_MIPS32_R6 select SYS_HAS_CPU_MIPS64_R1 select SYS_HAS_CPU_MIPS64_R2 select SYS_HAS_CPU_MIPS64_R6 + select SYS_HAS_CPU_R4X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN -- cgit v1.2.3 From db9947cea855eb0b0cbf9724a3aa69f7b39b3d73 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 3 Apr 2023 11:41:10 +0200 Subject: MIPS: mm: Remove unused *cache_page_indexed flush functions The *cache_page_indexed flush functions are no (longer) used. Signed-off-by: Thomas Bogendoerfer --- arch/mips/mm/c-r4k.c | 100 --------------------------------------------------- 1 file changed, 100 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 5599b9c9a737..dd31b1007919 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -187,24 +187,6 @@ static void r4k_blast_dcache_user_page_setup(void) #endif -static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); - -static void r4k_blast_dcache_page_indexed_setup(void) -{ - unsigned long dc_lsize = cpu_dcache_line_size(); - - if (dc_lsize == 0) - r4k_blast_dcache_page_indexed = (void *)cache_noop; - else if (dc_lsize == 16) - r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; - else if (dc_lsize == 32) - r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; - else if (dc_lsize == 64) - r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed; - else if (dc_lsize == 128) - r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed; -} - void (* r4k_blast_dcache)(void); EXPORT_SYMBOL(r4k_blast_dcache); @@ -266,39 +248,6 @@ static inline void tx49_blast_icache32(void) addr | ws, 32); } -static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) -{ - unsigned long flags; - - local_irq_save(flags); - blast_icache32_page_indexed(page); - local_irq_restore(flags); -} - -static inline void tx49_blast_icache32_page_indexed(unsigned long page) -{ - unsigned long indexmask = current_cpu_data.icache.waysize - 1; - unsigned long start = INDEX_BASE + (page & indexmask); - unsigned long end = start + PAGE_SIZE; - unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; - unsigned long ws_end = current_cpu_data.icache.ways << - current_cpu_data.icache.waybit; - unsigned long ws, addr; - - CACHE32_UNROLL32_ALIGN2; - /* I'm in even chunk. blast odd chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start + 0x400; addr < end; addr += 0x400 * 2) - cache_unroll(32, kernel_cache, Index_Invalidate_I, - addr | ws, 32); - CACHE32_UNROLL32_ALIGN; - /* I'm in odd chunk. blast even chunks */ - for (ws = 0; ws < ws_end; ws += ws_inc) - for (addr = start; addr < end; addr += 0x400 * 2) - cache_unroll(32, kernel_cache, Index_Invalidate_I, - addr | ws, 32); -} - static void (* r4k_blast_icache_page)(unsigned long addr); static void r4k_blast_icache_page_setup(void) @@ -341,34 +290,6 @@ static void r4k_blast_icache_user_page_setup(void) #endif -static void (* r4k_blast_icache_page_indexed)(unsigned long addr); - -static void r4k_blast_icache_page_indexed_setup(void) -{ - unsigned long ic_lsize = cpu_icache_line_size(); - - if (ic_lsize == 0) - r4k_blast_icache_page_indexed = (void *)cache_noop; - else if (ic_lsize == 16) - r4k_blast_icache_page_indexed = blast_icache16_page_indexed; - else if (ic_lsize == 32) { - if (IS_ENABLED(CONFIG_WAR_R4600_V1_INDEX_ICACHEOP) && - cpu_is_r4600_v1_x()) - r4k_blast_icache_page_indexed = - blast_icache32_r4600_v1_page_indexed; - else if (IS_ENABLED(CONFIG_WAR_TX49XX_ICACHE_INDEX_INV)) - r4k_blast_icache_page_indexed = - tx49_blast_icache32_page_indexed; - else if (current_cpu_type() == CPU_LOONGSON2EF) - r4k_blast_icache_page_indexed = - loongson2_blast_icache32_page_indexed; - else - r4k_blast_icache_page_indexed = - blast_icache32_page_indexed; - } else if (ic_lsize == 64) - r4k_blast_icache_page_indexed = blast_icache64_page_indexed; -} - void (* r4k_blast_icache)(void); EXPORT_SYMBOL(r4k_blast_icache); @@ -414,24 +335,6 @@ static void r4k_blast_scache_page_setup(void) r4k_blast_scache_page = blast_scache128_page; } -static void (* r4k_blast_scache_page_indexed)(unsigned long addr); - -static void r4k_blast_scache_page_indexed_setup(void) -{ - unsigned long sc_lsize = cpu_scache_line_size(); - - if (scache_size == 0) - r4k_blast_scache_page_indexed = (void *)cache_noop; - else if (sc_lsize == 16) - r4k_blast_scache_page_indexed = blast_scache16_page_indexed; - else if (sc_lsize == 32) - r4k_blast_scache_page_indexed = blast_scache32_page_indexed; - else if (sc_lsize == 64) - r4k_blast_scache_page_indexed = blast_scache64_page_indexed; - else if (sc_lsize == 128) - r4k_blast_scache_page_indexed = blast_scache128_page_indexed; -} - static void (* r4k_blast_scache)(void); static void r4k_blast_scache_setup(void) @@ -1807,13 +1710,10 @@ void r4k_cache_init(void) setup_scache(); r4k_blast_dcache_page_setup(); - r4k_blast_dcache_page_indexed_setup(); r4k_blast_dcache_setup(); r4k_blast_icache_page_setup(); - r4k_blast_icache_page_indexed_setup(); r4k_blast_icache_setup(); r4k_blast_scache_page_setup(); - r4k_blast_scache_page_indexed_setup(); r4k_blast_scache_setup(); r4k_blast_scache_node_setup(); #ifdef CONFIG_EVA -- cgit v1.2.3 From 461ba3e7e663a5c87e7b388b073904149b199593 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 3 Apr 2023 11:41:11 +0200 Subject: MIPS: Remove no longer used ide.h There are only three drivers left using ide.h, which are all m68k only. Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/ide.h | 13 --- arch/mips/include/asm/mach-generic/ide.h | 138 ------------------------------- 2 files changed, 151 deletions(-) delete mode 100644 arch/mips/include/asm/ide.h delete mode 100644 arch/mips/include/asm/mach-generic/ide.h (limited to 'arch/mips') diff --git a/arch/mips/include/asm/ide.h b/arch/mips/include/asm/ide.h deleted file mode 100644 index bb674c3b0303..000000000000 --- a/arch/mips/include/asm/ide.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This file contains the MIPS architecture specific IDE code. - */ -#ifndef __ASM_IDE_H -#define __ASM_IDE_H - -#include - -#endif /* __ASM_IDE_H */ diff --git a/arch/mips/include/asm/mach-generic/ide.h b/arch/mips/include/asm/mach-generic/ide.h deleted file mode 100644 index 4ae5fbcb15a5..000000000000 --- a/arch/mips/include/asm/mach-generic/ide.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994-1996 Linus Torvalds & authors - * - * Copied from i386; many of the especially older MIPS or ISA-based platforms - * are basically identical. Using this file probably implies i8259 PIC - * support in a system but the very least interrupt numbers 0 - 15 need to - * be put aside for legacy devices. - */ -#ifndef __ASM_MACH_GENERIC_IDE_H -#define __ASM_MACH_GENERIC_IDE_H - -#ifdef __KERNEL__ - -#include -#include -#include - -/* MIPS port and memory-mapped I/O string operations. */ -static inline void __ide_flush_prologue(void) -{ -#ifdef CONFIG_SMP - if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) - preempt_disable(); -#endif -} - -static inline void __ide_flush_epilogue(void) -{ -#ifdef CONFIG_SMP - if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) - preempt_enable(); -#endif -} - -static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) -{ - if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) { - unsigned long end = addr + size; - - while (addr < end) { - local_flush_data_cache_page((void *)addr); - addr += PAGE_SIZE; - } - } -} - -/* - * insw() and gang might be called with interrupts disabled, so we can't - * send IPIs for flushing due to the potencial of deadlocks, see the comment - * above smp_call_function() in arch/mips/kernel/smp.c. We work around the - * problem by disabling preemption so we know we actually perform the flush - * on the processor that actually has the lines to be flushed which hopefully - * is even better for performance anyway. - */ -static inline void __ide_insw(unsigned long port, void *addr, - unsigned int count) -{ - __ide_flush_prologue(); - insw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); -} - -static inline void __ide_insl(unsigned long port, void *addr, unsigned int count) -{ - __ide_flush_prologue(); - insl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); -} - -static inline void __ide_outsw(unsigned long port, const void *addr, - unsigned long count) -{ - __ide_flush_prologue(); - outsw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); -} - -static inline void __ide_outsl(unsigned long port, const void *addr, - unsigned long count) -{ - __ide_flush_prologue(); - outsl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); -} - -static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count) -{ - __ide_flush_prologue(); - readsw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); -} - -static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count) -{ - __ide_flush_prologue(); - readsl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); -} - -static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count) -{ - __ide_flush_prologue(); - writesw(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 2); - __ide_flush_epilogue(); -} - -static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count) -{ - __ide_flush_prologue(); - writesl(port, addr, count); - __ide_flush_dcache_range((unsigned long)addr, count * 4); - __ide_flush_epilogue(); -} - -/* ide_insw calls insw, not __ide_insw. Why? */ -#undef insw -#undef insl -#undef outsw -#undef outsl -#define insw(port, addr, count) __ide_insw(port, addr, count) -#define insl(port, addr, count) __ide_insl(port, addr, count) -#define outsw(port, addr, count) __ide_outsw(port, addr, count) -#define outsl(port, addr, count) __ide_outsl(port, addr, count) - -#endif /* __KERNEL__ */ - -#endif /* __ASM_MACH_GENERIC_IDE_H */ -- cgit v1.2.3 From c86df6c0d4fee0028bb208705bcceae548164fde Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Mon, 3 Apr 2023 11:41:12 +0200 Subject: MIPS: mm: Remove local_cache_flush_page After ide.h is gone, there are no users of local_cache_flush_page() left. Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/cacheflush.h | 1 - arch/mips/mm/c-r3k.c | 5 ----- arch/mips/mm/c-r4k.c | 3 --- arch/mips/mm/cache.c | 2 -- 4 files changed, 11 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h index b3dc9c589442..d8d3f80f9fc0 100644 --- a/arch/mips/include/asm/cacheflush.h +++ b/arch/mips/include/asm/cacheflush.h @@ -110,7 +110,6 @@ extern void copy_from_user_page(struct vm_area_struct *vma, unsigned long len); extern void (*flush_icache_all)(void); -extern void (*local_flush_data_cache_page)(void * addr); extern void (*flush_data_cache_page)(unsigned long addr); /* Run kernel code uncached, useful for cache probing functions. */ diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index df6755ca1892..5869df848fab 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -261,10 +261,6 @@ static void r3k_flush_cache_page(struct vm_area_struct *vma, r3k_flush_icache_range(kaddr, kaddr + PAGE_SIZE); } -static void local_r3k_flush_data_cache_page(void *addr) -{ -} - static void r3k_flush_data_cache_page(unsigned long addr) { } @@ -302,7 +298,6 @@ void r3k_cache_init(void) __flush_kernel_vmap_range = r3k_flush_kernel_vmap_range; - local_flush_data_cache_page = local_r3k_flush_data_cache_page; flush_data_cache_page = r3k_flush_data_cache_page; _dma_cache_wback_inv = r3k_dma_cache_wback_inv; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index dd31b1007919..4b6554b48923 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1745,7 +1745,6 @@ void r4k_cache_init(void) __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range; flush_icache_all = r4k_flush_icache_all; - local_flush_data_cache_page = local_r4k_flush_data_cache_page; flush_data_cache_page = r4k_flush_data_cache_page; flush_icache_range = r4k_flush_icache_range; local_flush_icache_range = local_r4k_flush_icache_range; @@ -1788,7 +1787,6 @@ void r4k_cache_init(void) /* I$ fills from D$ just by emptying the write buffers */ flush_cache_page = (void *)b5k_instruction_hazard; flush_cache_range = (void *)b5k_instruction_hazard; - local_flush_data_cache_page = (void *)b5k_instruction_hazard; flush_data_cache_page = (void *)b5k_instruction_hazard; flush_icache_range = (void *)b5k_instruction_hazard; local_flush_icache_range = (void *)b5k_instruction_hazard; @@ -1808,7 +1806,6 @@ void r4k_cache_init(void) flush_cache_range = (void *)cache_noop; flush_icache_all = (void *)cache_noop; flush_data_cache_page = (void *)cache_noop; - local_flush_data_cache_page = (void *)cache_noop; break; } } diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 7dba4b5c02c3..d21cf8c6cf6c 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -49,11 +49,9 @@ void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size); EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range); /* MIPS specific cache operations */ -void (*local_flush_data_cache_page)(void * addr); void (*flush_data_cache_page)(unsigned long addr); void (*flush_icache_all)(void); -EXPORT_SYMBOL_GPL(local_flush_data_cache_page); EXPORT_SYMBOL(flush_data_cache_page); EXPORT_SYMBOL(flush_icache_all); -- cgit v1.2.3 From 275aca650e76e203e3efc71835d7195e18d2e718 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Tue, 4 Apr 2023 14:18:41 -0700 Subject: MIPS: Drop unused positional parameter in local_irq_{dis,en}able When building with clang's integrated assembler, it points out that the CONFIG_CPU_HAS_DIEI versions of local_irq_enable and local_irq_disable have a named parameter that is not used in the body of the macro and it thinks that $8 is a positional parameter, rather than a register: arch/mips/include/asm/asmmacro.h:48:2: warning: macro defined with named parameters which are not used in macro body, possible positional parameter found in body which will have no effect .macro local_irq_enable reg=$8 ^ The comment above the function that performs this check in LLVM notes that the warning may trigger in this case, even though it is not problematic. It is easy enough to clean this up by just omitting the named parameter for this version of the macro, as it is entirely unused. Reported-by: Nick Desaulniers Link: https://github.com/ClangBuiltLinux/linux/issues/1415 Link: https://github.com/llvm/llvm-project/commit/81c944cadb7f9e55b3517b7423a820e2577b9279 Signed-off-by: Nathan Chancellor Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/asmmacro.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index 1c4438f3f2ab..067a635d3bc8 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -45,12 +45,12 @@ #endif #ifdef CONFIG_CPU_HAS_DIEI - .macro local_irq_enable reg=t0 + .macro local_irq_enable ei irq_enable_hazard .endm - .macro local_irq_disable reg=t0 + .macro local_irq_disable di irq_disable_hazard .endm -- cgit v1.2.3 From 045c340c86f8a9d7cb675e179dc6297caa6ebc01 Mon Sep 17 00:00:00 2001 From: Aleksander Jan Bajkowski Date: Wed, 29 Mar 2023 23:03:28 +0200 Subject: MIPS: lantiq: remove unused function declaration The removed function declaration is a leftover of the old gphy firmware loader, that has been removed in d5103604f78e1afc29e586785af540c82b573f3a. Signed-off-by: Aleksander Jan Bajkowski Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 4790cfa190d6..c2e0acb755cd 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -94,9 +94,6 @@ extern __iomem void *ltq_cgu_membase; #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) -/* allow booting xrx200 phys */ -int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr); - /* request a non-gpio and set the PIO config */ #define PMU_PPE BIT(13) extern void ltq_pmu_enable(unsigned int module); -- cgit v1.2.3 From 7fb6f7b0af6742601e0efe315c78c26e88d30ff1 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Wed, 5 Apr 2023 20:51:27 +0200 Subject: MIPS: Remove deprecated CONFIG_MIPS_CMP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 5cac93b35c14 ("MIPS: Deprecate CONFIG_MIPS_CMP") deprecated CONFIG_MIPS_CMP and after 9 years it's time to remove it. Signed-off-by: Thomas Bogendoerfer Reviewed-by: Jiaxun Yang Acked-by: Marc Zyngier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 34 +------ arch/mips/include/asm/rtlx.h | 1 - arch/mips/include/asm/smp-ops.h | 16 ---- arch/mips/include/asm/vpe.h | 4 - arch/mips/kernel/Makefile | 3 - arch/mips/kernel/rtlx-cmp.c | 122 ------------------------ arch/mips/kernel/smp-cmp.c | 148 ---------------------------- arch/mips/kernel/vpe-cmp.c | 180 ----------------------------------- arch/mips/kernel/vpe.c | 2 +- arch/mips/mti-malta/Makefile | 2 - arch/mips/mti-malta/malta-amon.c | 88 ----------------- arch/mips/mti-malta/malta-init.c | 2 - arch/mips/mti-malta/malta-platform.c | 2 - arch/mips/ralink/mt7621.c | 2 - drivers/irqchip/irq-mips-gic.c | 26 ----- 15 files changed, 3 insertions(+), 629 deletions(-) delete mode 100644 arch/mips/kernel/rtlx-cmp.c delete mode 100644 arch/mips/kernel/smp-cmp.c delete mode 100644 arch/mips/kernel/vpe-cmp.c delete mode 100644 arch/mips/mti-malta/malta-amon.c (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a975f140ae82..61fca312a2c5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -568,7 +568,6 @@ config MIPS_MALTA select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_MICROMIPS select SYS_SUPPORTS_MIPS16 - select SYS_SUPPORTS_MIPS_CMP select SYS_SUPPORTS_MIPS_CPS select SYS_SUPPORTS_MULTITHREADING select SYS_SUPPORTS_RELOCATABLE @@ -2270,15 +2269,10 @@ config MIPS_VPE_LOADER Includes a loader for loading an elf relocatable object onto another VPE and running it. -config MIPS_VPE_LOADER_CMP - bool - default "y" - depends on MIPS_VPE_LOADER && MIPS_CMP - config MIPS_VPE_LOADER_MT bool default "y" - depends on MIPS_VPE_LOADER && !MIPS_CMP + depends on MIPS_VPE_LOADER config MIPS_VPE_LOADER_TOM bool "Load VPE program into memory hidden from linux" @@ -2294,31 +2288,10 @@ config MIPS_VPE_APSP_API bool "Enable support for AP/SP API (RTLX)" depends on MIPS_VPE_LOADER -config MIPS_VPE_APSP_API_CMP - bool - default "y" - depends on MIPS_VPE_APSP_API && MIPS_CMP - config MIPS_VPE_APSP_API_MT bool default "y" - depends on MIPS_VPE_APSP_API && !MIPS_CMP - -config MIPS_CMP - bool "MIPS CMP framework support (DEPRECATED)" - depends on SYS_SUPPORTS_MIPS_CMP && !CPU_MIPSR6 - select SMP - select SYNC_R4K - select SYS_SUPPORTS_SMP - select WEAK_ORDERING - default n - help - Select this if you are using a bootloader which implements the "CMP - framework" protocol (ie. YAMON) and want your kernel to make use of - its ability to start secondary CPUs. - - Unless you have a specific need, you should use CONFIG_MIPS_CPS - instead of this. + depends on MIPS_VPE_APSP_API config MIPS_CPS bool "MIPS Coherent Processing System support" @@ -2774,9 +2747,6 @@ config HOTPLUG_CPU config SMP_UP bool -config SYS_SUPPORTS_MIPS_CMP - bool - config SYS_SUPPORTS_MIPS_CPS bool diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h index c1020654876e..a72785b4bbf4 100644 --- a/arch/mips/include/asm/rtlx.h +++ b/arch/mips/include/asm/rtlx.h @@ -81,7 +81,6 @@ struct rtlx_channel { extern struct rtlx_info { unsigned long id; enum rtlx_state state; - int ap_int_pending; /* Status of 0 or 1 for CONFIG_MIPS_CMP only */ struct rtlx_channel channel[RTLX_CHANNELS]; } *rtlx; diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h index 864aea803984..0145bbfb5efb 100644 --- a/arch/mips/include/asm/smp-ops.h +++ b/arch/mips/include/asm/smp-ops.h @@ -80,22 +80,6 @@ static inline int register_up_smp_ops(void) #endif } -static inline int register_cmp_smp_ops(void) -{ -#ifdef CONFIG_MIPS_CMP - extern const struct plat_smp_ops cmp_smp_ops; - - if (!mips_cm_present()) - return -ENODEV; - - register_smp_ops(&cmp_smp_ops); - - return 0; -#else - return -ENODEV; -#endif -} - static inline int register_vsmp_smp_ops(void) { #ifdef CONFIG_MIPS_MT_SMP diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index ef7e07829607..61fd4d0aeda4 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -29,12 +29,8 @@ static inline int aprp_cpu_index(void) { -#ifdef CONFIG_MIPS_CMP - return setup_max_cpus; -#else extern int tclimit; return tclimit; -#endif } enum vpe_state { diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 5d1addac5e28..853a43ee4b44 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -58,16 +58,13 @@ obj-$(CONFIG_CPU_BMIPS) += smp-bmips.o bmips_vec.o bmips_5xxx_init.o obj-$(CONFIG_MIPS_MT) += mips-mt.o obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o -obj-$(CONFIG_MIPS_CMP) += smp-cmp.o obj-$(CONFIG_MIPS_CPS) += smp-cps.o cps-vec.o obj-$(CONFIG_MIPS_CPS_NS16550) += cps-vec-ns16550.o obj-$(CONFIG_MIPS_SPRAM) += spram.o obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o -obj-$(CONFIG_MIPS_VPE_LOADER_CMP) += vpe-cmp.o obj-$(CONFIG_MIPS_VPE_LOADER_MT) += vpe-mt.o obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o -obj-$(CONFIG_MIPS_VPE_APSP_API_CMP) += rtlx-cmp.o obj-$(CONFIG_MIPS_VPE_APSP_API_MT) += rtlx-mt.o obj-$(CONFIG_MIPS_MSC) += irq-msc01.o diff --git a/arch/mips/kernel/rtlx-cmp.c b/arch/mips/kernel/rtlx-cmp.c deleted file mode 100644 index d26dcc4b46e7..000000000000 --- a/arch/mips/kernel/rtlx-cmp.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2013 Imagination Technologies Ltd. - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -static int major; - -static void rtlx_interrupt(void) -{ - int i; - struct rtlx_info *info; - struct rtlx_info **p = vpe_get_shared(aprp_cpu_index()); - - if (p == NULL || *p == NULL) - return; - - info = *p; - - if (info->ap_int_pending == 1 && smp_processor_id() == 0) { - for (i = 0; i < RTLX_CHANNELS; i++) { - wake_up(&channel_wqs[i].lx_queue); - wake_up(&channel_wqs[i].rt_queue); - } - info->ap_int_pending = 0; - } -} - -void _interrupt_sp(void) -{ - smp_send_reschedule(aprp_cpu_index()); -} - -int __init rtlx_module_init(void) -{ - struct device *dev; - int i, err; - - if (!cpu_has_mipsmt) { - pr_warn("VPE loader: not a MIPS MT capable processor\n"); - return -ENODEV; - } - - if (num_possible_cpus() - aprp_cpu_index() < 1) { - pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" - "Pass maxcpus= argument as kernel argument\n"); - - return -ENODEV; - } - - major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops); - if (major < 0) { - pr_err("rtlx_module_init: unable to register device\n"); - return major; - } - - /* initialise the wait queues */ - for (i = 0; i < RTLX_CHANNELS; i++) { - init_waitqueue_head(&channel_wqs[i].rt_queue); - init_waitqueue_head(&channel_wqs[i].lx_queue); - atomic_set(&channel_wqs[i].in_open, 0); - mutex_init(&channel_wqs[i].mutex); - - dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, - "%s%d", RTLX_MODULE_NAME, i); - if (IS_ERR(dev)) { - while (i--) - device_destroy(mt_class, MKDEV(major, i)); - - err = PTR_ERR(dev); - goto out_chrdev; - } - } - - /* set up notifiers */ - rtlx_notify.start = rtlx_starting; - rtlx_notify.stop = rtlx_stopping; - vpe_notify(aprp_cpu_index(), &rtlx_notify); - - if (cpu_has_vint) { - aprp_hook = rtlx_interrupt; - } else { - pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); - err = -ENODEV; - goto out_class; - } - - return 0; - -out_class: - for (i = 0; i < RTLX_CHANNELS; i++) - device_destroy(mt_class, MKDEV(major, i)); -out_chrdev: - unregister_chrdev(major, RTLX_MODULE_NAME); - - return err; -} - -void __exit rtlx_module_exit(void) -{ - int i; - - for (i = 0; i < RTLX_CHANNELS; i++) - device_destroy(mt_class, MKDEV(major, i)); - - unregister_chrdev(major, RTLX_MODULE_NAME); - - aprp_hook = NULL; -} diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c deleted file mode 100644 index 76f5824cdb00..000000000000 --- a/arch/mips/kernel/smp-cmp.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * - * Copyright (C) 2007 MIPS Technologies, Inc. - * Chris Dearman (chris@mips.com) - */ - -#undef DEBUG - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void cmp_init_secondary(void) -{ - struct cpuinfo_mips *c __maybe_unused = ¤t_cpu_data; - - /* Assume GIC is present */ - change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | - STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); - - /* Enable per-cpu interrupts: platform specific */ - -#ifdef CONFIG_MIPS_MT_SMP - if (cpu_has_mipsmt) - cpu_set_vpe_id(c, (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & - TCBIND_CURVPE); -#endif -} - -static void cmp_smp_finish(void) -{ - pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__); - - /* CDFIXME: remove this? */ - write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); - -#ifdef CONFIG_MIPS_MT_FPAFF - /* If we have an FPU, enroll ourselves in the FPU-full mask */ - if (cpu_has_fpu) - cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask); -#endif /* CONFIG_MIPS_MT_FPAFF */ - - local_irq_enable(); -} - -/* - * Setup the PC, SP, and GP of a secondary processor and start it running - * smp_bootstrap is the place to resume from - * __KSTK_TOS(idle) is apparently the stack pointer - * (unsigned long)idle->thread_info the gp - */ -static int cmp_boot_secondary(int cpu, struct task_struct *idle) -{ - struct thread_info *gp = task_thread_info(idle); - unsigned long sp = __KSTK_TOS(idle); - unsigned long pc = (unsigned long)&smp_bootstrap; - unsigned long a0 = 0; - - pr_debug("SMPCMP: CPU%d: %s cpu %d\n", smp_processor_id(), - __func__, cpu); - -#if 0 - /* Needed? */ - flush_icache_range((unsigned long)gp, - (unsigned long)(gp + sizeof(struct thread_info))); -#endif - - amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0); - return 0; -} - -/* - * Common setup before any secondaries are started - */ -void __init cmp_smp_setup(void) -{ - int i; - int ncpu = 0; - - pr_debug("SMPCMP: CPU%d: %s\n", smp_processor_id(), __func__); - -#ifdef CONFIG_MIPS_MT_FPAFF - /* If we have an FPU, enroll ourselves in the FPU-full mask */ - if (cpu_has_fpu) - cpumask_set_cpu(0, &mt_fpu_cpumask); -#endif /* CONFIG_MIPS_MT_FPAFF */ - - for (i = 1; i < NR_CPUS; i++) { - if (amon_cpu_avail(i)) { - set_cpu_possible(i, true); - __cpu_number_map[i] = ++ncpu; - __cpu_logical_map[ncpu] = i; - } - } - - if (cpu_has_mipsmt) { - unsigned int nvpe = 1; -#ifdef CONFIG_MIPS_MT_SMP - unsigned int mvpconf0 = read_c0_mvpconf0(); - - nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; -#endif - smp_num_siblings = nvpe; - } - pr_info("Detected %i available secondary CPU(s)\n", ncpu); -} - -void __init cmp_prepare_cpus(unsigned int max_cpus) -{ - pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n", - smp_processor_id(), __func__, max_cpus); - -#ifdef CONFIG_MIPS_MT - /* - * FIXME: some of these options are per-system, some per-core and - * some per-cpu - */ - mips_mt_set_cpuoptions(); -#endif - -} - -const struct plat_smp_ops cmp_smp_ops = { - .send_ipi_single = mips_smp_send_ipi_single, - .send_ipi_mask = mips_smp_send_ipi_mask, - .init_secondary = cmp_init_secondary, - .smp_finish = cmp_smp_finish, - .boot_secondary = cmp_boot_secondary, - .smp_setup = cmp_smp_setup, - .prepare_cpus = cmp_prepare_cpus, -}; diff --git a/arch/mips/kernel/vpe-cmp.c b/arch/mips/kernel/vpe-cmp.c deleted file mode 100644 index 92140edb3ce3..000000000000 --- a/arch/mips/kernel/vpe-cmp.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2013 Imagination Technologies Ltd. - */ -#include -#include -#include -#include -#include - -#include - -static int major; - -void cleanup_tc(struct tc *tc) -{ - -} - -static ssize_t store_kill(struct device *dev, struct device_attribute *attr, - const char *buf, size_t len) -{ - struct vpe *vpe = get_vpe(aprp_cpu_index()); - struct vpe_notifications *notifier; - - list_for_each_entry(notifier, &vpe->notify, list) - notifier->stop(aprp_cpu_index()); - - release_progmem(vpe->load_addr); - vpe->state = VPE_STATE_UNUSED; - - return len; -} -static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill); - -static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr, - char *buf) -{ - struct vpe *vpe = get_vpe(aprp_cpu_index()); - - return sprintf(buf, "%d\n", vpe->ntcs); -} - -static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr, - const char *buf, size_t len) -{ - struct vpe *vpe = get_vpe(aprp_cpu_index()); - unsigned long new; - int ret; - - ret = kstrtoul(buf, 0, &new); - if (ret < 0) - return ret; - - /* APRP can only reserve one TC in a VPE and no more. */ - if (new != 1) - return -EINVAL; - - vpe->ntcs = new; - - return len; -} -static DEVICE_ATTR_RW(ntcs); - -static struct attribute *vpe_attrs[] = { - &dev_attr_kill.attr, - &dev_attr_ntcs.attr, - NULL, -}; -ATTRIBUTE_GROUPS(vpe); - -static void vpe_device_release(struct device *cd) -{ -} - -static struct class vpe_class = { - .name = "vpe", - .owner = THIS_MODULE, - .dev_release = vpe_device_release, - .dev_groups = vpe_groups, -}; - -static struct device vpe_device; - -int __init vpe_module_init(void) -{ - struct vpe *v = NULL; - struct tc *t; - int err; - - if (!cpu_has_mipsmt) { - pr_warn("VPE loader: not a MIPS MT capable processor\n"); - return -ENODEV; - } - - if (num_possible_cpus() - aprp_cpu_index() < 1) { - pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" - "Pass maxcpus= argument as kernel argument\n"); - return -ENODEV; - } - - major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops); - if (major < 0) { - pr_warn("VPE loader: unable to register character device\n"); - return major; - } - - err = class_register(&vpe_class); - if (err) { - pr_err("vpe_class registration failed\n"); - goto out_chrdev; - } - - device_initialize(&vpe_device); - vpe_device.class = &vpe_class; - vpe_device.parent = NULL; - dev_set_name(&vpe_device, "vpe_sp"); - vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR); - err = device_add(&vpe_device); - if (err) { - pr_err("Adding vpe_device failed\n"); - goto out_class; - } - - t = alloc_tc(aprp_cpu_index()); - if (!t) { - pr_warn("VPE: unable to allocate TC\n"); - err = -ENOMEM; - goto out_dev; - } - - /* VPE */ - v = alloc_vpe(aprp_cpu_index()); - if (v == NULL) { - pr_warn("VPE: unable to allocate VPE\n"); - kfree(t); - err = -ENOMEM; - goto out_dev; - } - - v->ntcs = 1; - - /* add the tc to the list of this vpe's tc's. */ - list_add(&t->tc, &v->tc); - - /* TC */ - t->pvpe = v; /* set the parent vpe */ - - return 0; - -out_dev: - device_del(&vpe_device); - -out_class: - put_device(&vpe_device); - class_unregister(&vpe_class); - -out_chrdev: - unregister_chrdev(major, VPE_MODULE_NAME); - - return err; -} - -void __exit vpe_module_exit(void) -{ - struct vpe *v, *n; - - device_unregister(&vpe_device); - class_unregister(&vpe_class); - unregister_chrdev(major, VPE_MODULE_NAME); - - /* No locking needed here */ - list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) - if (v->state != VPE_STATE_UNUSED) - release_vpe(v); -} diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 13294972707b..343d2597ed76 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -795,7 +795,7 @@ static int vpe_open(struct inode *inode, struct file *filp) static int vpe_release(struct inode *inode, struct file *filp) { -#if defined(CONFIG_MIPS_VPE_LOADER_MT) || defined(CONFIG_MIPS_VPE_LOADER_CMP) +#ifdef CONFIG_MIPS_VPE_LOADER_MT struct vpe *v; Elf_Ehdr *hdr; int ret = 0; diff --git a/arch/mips/mti-malta/Makefile b/arch/mips/mti-malta/Makefile index 13bbd12bfa65..bb2c706e11b0 100644 --- a/arch/mips/mti-malta/Makefile +++ b/arch/mips/mti-malta/Makefile @@ -14,6 +14,4 @@ obj-y += malta-platform.o obj-y += malta-setup.o obj-y += malta-time.o -obj-$(CONFIG_MIPS_CMP) += malta-amon.o - CFLAGS_malta-dtshim.o = -I$(src)/../../../scripts/dtc/libfdt diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c deleted file mode 100644 index 84ac523b0ce0..000000000000 --- a/arch/mips/mti-malta/malta-amon.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2007 MIPS Technologies, Inc. All rights reserved. - * Copyright (C) 2013 Imagination Technologies Ltd. - * - * Arbitrary Monitor Interface - */ -#include -#include - -#include -#include -#include -#include - -int amon_cpu_avail(int cpu) -{ - struct cpulaunch *launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); - - if (cpu < 0 || cpu >= NCPULAUNCH) { - pr_debug("avail: cpu%d is out of range\n", cpu); - return 0; - } - - launch += cpu; - if (!(launch->flags & LAUNCH_FREADY)) { - pr_debug("avail: cpu%d is not ready\n", cpu); - return 0; - } - if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) { - pr_debug("avail: too late.. cpu%d is already gone\n", cpu); - return 0; - } - - return 1; -} - -int amon_cpu_start(int cpu, - unsigned long pc, unsigned long sp, - unsigned long gp, unsigned long a0) -{ - volatile struct cpulaunch *launch = - (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); - - if (!amon_cpu_avail(cpu)) - return -1; - if (cpu == smp_processor_id()) { - pr_debug("launch: I am cpu%d!\n", cpu); - return -1; - } - launch += cpu; - - pr_debug("launch: starting cpu%d\n", cpu); - - launch->pc = pc; - launch->gp = gp; - launch->sp = sp; - launch->a0 = a0; - - smp_wmb(); /* Target must see parameters before go */ - launch->flags |= LAUNCH_FGO; - smp_wmb(); /* Target must see go before we poll */ - - while ((launch->flags & LAUNCH_FGONE) == 0) - ; - smp_rmb(); /* Target will be updating flags soon */ - pr_debug("launch: cpu%d gone!\n", cpu); - - return 0; -} - -#ifdef CONFIG_MIPS_VPE_LOADER_CMP -int vpe_run(struct vpe *v) -{ - struct vpe_notifications *n; - - if (amon_cpu_start(aprp_cpu_index(), v->__start, 0, 0, 0) < 0) - return -1; - - list_for_each_entry(n, &v->notify, list) - n->start(VPE_MODULE_MINOR); - - return 0; -} -#endif diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index b03cac5fdc02..000d6d50520a 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -289,8 +289,6 @@ mips_pci_controller: if (!register_cps_smp_ops()) return; - if (!register_cmp_smp_ops()) - return; if (!register_vsmp_smp_ops()) return; register_up_smp_ops(); diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c index 4ffbcc58c6f6..6961a23aefe9 100644 --- a/arch/mips/mti-malta/malta-platform.c +++ b/arch/mips/mti-malta/malta-platform.c @@ -43,7 +43,6 @@ static struct plat_serial8250_port uart8250_data[] = { SMC_PORT(0x3F8, 4), SMC_PORT(0x2F8, 3), -#ifndef CONFIG_MIPS_CMP { .mapbase = 0x1f000900, /* The CBUS UART */ .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2, @@ -53,7 +52,6 @@ static struct plat_serial8250_port uart8250_data[] = { .flags = CBUS_UART_FLAGS, .regshift = 3, }, -#endif { }, }; diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index bbf5811afbf2..c3fbab50b95c 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -217,8 +217,6 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) if (!register_cps_smp_ops()) return; - if (!register_cmp_smp_ops()) - return; if (!register_vsmp_smp_ops()) return; } diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 1a6a7a672ad7..046c355e120b 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -54,7 +54,6 @@ static DEFINE_SPINLOCK(gic_lock); static struct irq_domain *gic_irq_domain; static int gic_shared_intrs; static unsigned int gic_cpu_pin; -static unsigned int timer_cpu_pin; static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller; #ifdef CONFIG_GENERIC_IRQ_IPI @@ -499,9 +498,6 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, */ switch (intr) { case GIC_LOCAL_INT_TIMER: - /* CONFIG_MIPS_CMP workaround (see __gic_init) */ - map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin; - fallthrough; case GIC_LOCAL_INT_PERFCTR: case GIC_LOCAL_INT_FDC: /* @@ -795,34 +791,12 @@ static int __init gic_of_init(struct device_node *node, if (cpu_has_veic) { /* Always use vector 1 in EIC mode */ gic_cpu_pin = 0; - timer_cpu_pin = gic_cpu_pin; set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET, __gic_irq_dispatch); } else { gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET; irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec, gic_irq_dispatch); - /* - * With the CMP implementation of SMP (deprecated), other CPUs - * are started by the bootloader and put into a timer based - * waiting poll loop. We must not re-route those CPU's local - * timer interrupts as the wait instruction will never finish, - * so just handle whatever CPU interrupt it is routed to by - * default. - * - * This workaround should be removed when CMP support is - * dropped. - */ - if (IS_ENABLED(CONFIG_MIPS_CMP) && - gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) { - timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP; - irq_set_chained_handler(MIPS_CPU_IRQ_BASE + - GIC_CPU_PIN_OFFSET + - timer_cpu_pin, - gic_irq_dispatch); - } else { - timer_cpu_pin = gic_cpu_pin; - } } gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS + -- cgit v1.2.3 From ee1809ed7bc456a72dc8410b475b73021a3a68d5 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 11 Apr 2023 12:14:26 +0100 Subject: MIPS: fw: Allow firmware to pass a empty env fw_getenv will use env entry to determine style of env, however it is legal for firmware to just pass a empty list. Check if first entry exist before running strchr to avoid null pointer dereference. Cc: stable@vger.kernel.org Link: https://github.com/clbr/n64bootloader/issues/5 Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/fw/lib/cmdline.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/fw/lib/cmdline.c b/arch/mips/fw/lib/cmdline.c index f24cbb4a39b5..892765b742bb 100644 --- a/arch/mips/fw/lib/cmdline.c +++ b/arch/mips/fw/lib/cmdline.c @@ -53,7 +53,7 @@ char *fw_getenv(char *envname) { char *result = NULL; - if (_fw_envp != NULL) { + if (_fw_envp != NULL && fw_envp(0) != NULL) { /* * Return a pointer to the given environment variable. * YAMON uses "name", "value" pairs, while U-Boot uses -- cgit v1.2.3 From f5748b8c79d1eea924c50487bdb33351f58ef7bb Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 11 Apr 2023 15:17:47 +0800 Subject: MIPS: Use def_bool y for ARCH_SUPPORTS_UPROBES Like all the other archs, use def_bool y for ARCH_SUPPORTS_UPROBES, then no need to select ARCH_SUPPORTS_UPROBES. Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 61fca312a2c5..47944eb5d7e3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -16,7 +16,6 @@ config MIPS select ARCH_HAS_UBSAN_SANITIZE_ALL select ARCH_HAS_GCOV_PROFILE_ALL select ARCH_KEEP_MEMBLOCK - select ARCH_SUPPORTS_UPROBES select ARCH_USE_BUILTIN_BSWAP select ARCH_USE_CMPXCHG_LOCKREF if 64BIT select ARCH_USE_MEMTEST @@ -1059,7 +1058,7 @@ config FW_CFE bool config ARCH_SUPPORTS_UPROBES - bool + def_bool y config DMA_NONCOHERENT bool -- cgit v1.2.3 From afa624ff96e8e79136a46ddaf6debb030546d7c6 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 11 Apr 2023 15:17:48 +0800 Subject: MIPS: Remove set_swbp() in uprobes.c set_swbp() in arch/mips/kernel/uprobes.c is same with the weak version in kernel/events/uprobes.c, remove it. Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/uprobes.c | 18 ------------------ 1 file changed, 18 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/uprobes.c b/arch/mips/kernel/uprobes.c index 6c063aa188e6..6b630ed4438d 100644 --- a/arch/mips/kernel/uprobes.c +++ b/arch/mips/kernel/uprobes.c @@ -207,24 +207,6 @@ unsigned long arch_uretprobe_hijack_return_addr( return ra; } -/** - * set_swbp - store breakpoint at a given address. - * @auprobe: arch specific probepoint information. - * @mm: the probed process address space. - * @vaddr: the virtual address to insert the opcode. - * - * For mm @mm, store the breakpoint instruction at @vaddr. - * Return 0 (success) or a negative errno. - * - * This version overrides the weak version in kernel/events/uprobes.c. - * It is required to handle MIPS16 and microMIPS. - */ -int __weak set_swbp(struct arch_uprobe *auprobe, struct mm_struct *mm, - unsigned long vaddr) -{ - return uprobe_write_opcode(auprobe, mm, vaddr, UPROBE_SWBP_INSN); -} - void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr, void *src, unsigned long len) { -- cgit v1.2.3 From f0e7c06f2be9673d008e866bff1a97e1823637e9 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 11 Apr 2023 12:12:20 +0100 Subject: MIPS: loongson2ef: Add missing break in cs5536_isa Fixes build error: arch/mips/loongson2ef/common/cs5536/cs5536_isa.c:217:2: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough] default: ^ arch/mips/loongson2ef/common/cs5536/cs5536_isa.c:217:2: note: insert 'break;' to avoid fall-through default: ^ break; Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/loongson2ef/common/cs5536/cs5536_isa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/loongson2ef/common/cs5536/cs5536_isa.c b/arch/mips/loongson2ef/common/cs5536/cs5536_isa.c index 5ad38f86ee62..d60dd9992377 100644 --- a/arch/mips/loongson2ef/common/cs5536/cs5536_isa.c +++ b/arch/mips/loongson2ef/common/cs5536/cs5536_isa.c @@ -213,7 +213,7 @@ void pci_isa_write_reg(int reg, u32 value) lo |= 0x00000063; _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); } - + break; default: /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */ break; -- cgit v1.2.3 From 6ca176fa3a23652513a9d593a6742fb896c7c49f Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 11 Apr 2023 12:12:24 +0100 Subject: MIPS: octeon_switch: Remove duplicated labels EXPORT macro already have labels defined by itself. Remove duplicated labels outside to silent assembler warnings. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/octeon_switch.S | 6 ------ 1 file changed, 6 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S index 896080b445c2..9b7c8ab6f08c 100644 --- a/arch/mips/kernel/octeon_switch.S +++ b/arch/mips/kernel/octeon_switch.S @@ -428,7 +428,6 @@ done_restore: jr ra nop .space 30 * 4, 0 -octeon_mult_save_end: EXPORT(octeon_mult_save_end) END(octeon_mult_save) @@ -448,7 +447,6 @@ octeon_mult_save_end: sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */ jr ra sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */ -octeon_mult_save2_end: EXPORT(octeon_mult_save2_end) END(octeon_mult_save2) @@ -480,7 +478,6 @@ octeon_mult_save2_end: sd $10, PT_MPL+(4*8)(sp) /* store MPL4 */ jr ra sd $11, PT_MPL+(5*8)(sp) /* store MPL5 */ -octeon_mult_save3_end: EXPORT(octeon_mult_save3_end) END(octeon_mult_save3) .set pop @@ -498,7 +495,6 @@ octeon_mult_save3_end: jr ra nop .space 30 * 4, 0 -octeon_mult_restore_end: EXPORT(octeon_mult_restore_end) END(octeon_mult_restore) @@ -517,7 +513,6 @@ octeon_mult_restore_end: mtp1 v0 /* P1 */ jr ra mtp0 v1 /* P0 */ -octeon_mult_restore2_end: EXPORT(octeon_mult_restore2_end) END(octeon_mult_restore2) @@ -548,7 +543,6 @@ octeon_mult_restore2_end: .word 0x714b000b /* mtp2 $10, $11 restore P2 and P5 */ -octeon_mult_restore3_end: EXPORT(octeon_mult_restore3_end) END(octeon_mult_restore3) .set pop -- cgit v1.2.3 From 20470a68a049de3b118e31ab01474c622934c500 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Wed, 12 Apr 2023 15:21:38 +0200 Subject: Revert "MIPS: generic: Enable all CPUs supported by virt board in Kconfig" This reverts commit de34007751aaba992373f2d659001a846aeb8811. There are too many build errors, which needs to be sorted out first. Signed-off-by: Thomas Bogendoerfer --- arch/mips/Kconfig | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 47944eb5d7e3..7629e671381b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -152,16 +152,12 @@ config MIPS_GENERIC_KERNEL select PCI_DRIVERS_GENERIC select SMP_UP if SMP select SWAP_IO_SPACE - select SYS_HAS_CPU_CAVIUM_OCTEON - select SYS_HAS_CPU_LOONGSON2E - select SYS_HAS_CPU_LOONGSON2F select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_HAS_CPU_MIPS32_R6 select SYS_HAS_CPU_MIPS64_R1 select SYS_HAS_CPU_MIPS64_R2 select SYS_HAS_CPU_MIPS64_R6 - select SYS_HAS_CPU_R4X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN -- cgit v1.2.3 From 95b5baf81001a80a8dd8b35306694db163bcb423 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Fri, 21 Apr 2023 09:11:26 -0700 Subject: MIPS: Mark check_bugs() as __init After commit ac7c3e4ff401 ("compiler: enable CONFIG_OPTIMIZE_INLINING forcibly"), a compiler may choose not to inline a function marked with just 'inline'. If check_bugs() is not inlined into start_kernel(), which occurs when building with clang after commit 9ea7e6b62c2b ("init: Mark [arch_call_]rest_init() __noreturn"), modpost complains with: WARNING: modpost: vmlinux.o: section mismatch in reference: check_bugs (section: .text) -> check_bugs32 (section: .init.text) check_bugs() is only called from start_kernel(), which itself is marked __init, so there would not be any issues at run time. Make it obvious to modpost that this call chain is safe by marking check_bugs() as __init, which fixes the warning. Reported-by: Naresh Kamboju Link: https://lore.kernel.org/CA+G9fYt+4e57Gdy6cix=LeNK6XqWoui8du=mZWu=cf8vPYocKw@mail.gmail.com/ Signed-off-by: Nathan Chancellor Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/bugs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h index d72dc6e1cf3c..047e14227c45 100644 --- a/arch/mips/include/asm/bugs.h +++ b/arch/mips/include/asm/bugs.h @@ -30,7 +30,7 @@ static inline void check_bugs_early(void) check_bugs64_early(); } -static inline void check_bugs(void) +static inline void __init check_bugs(void) { unsigned int cpu = smp_processor_id(); -- cgit v1.2.3 From f4670a1b30f886e843258ca4a69c442811a90302 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Fri, 21 Apr 2023 09:11:27 -0700 Subject: MIPS: Sink body of check_bugs_early() into its only call site If check_bugs_early() is not inlined, which a compiler is free to do after commit ac7c3e4ff401 ("compiler: enable CONFIG_OPTIMIZE_INLINING forcibly"), modpost would warn that check_bugs_early(), a non-init function, refers to check_bugs64_early(), which is marked __init. This would not result in any run time issues, as check_bugs_early() is only called from setup_arch(), which is marked __init. To avoid this potential warning, just sink the body of check_bugs_early() into its single call site in setup_arch(). Signed-off-by: Nathan Chancellor Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/bugs.h | 6 ------ arch/mips/kernel/setup.c | 3 ++- 2 files changed, 2 insertions(+), 7 deletions(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h index 047e14227c45..653f78f3a685 100644 --- a/arch/mips/include/asm/bugs.h +++ b/arch/mips/include/asm/bugs.h @@ -24,12 +24,6 @@ extern void check_bugs64_early(void); extern void check_bugs32(void); extern void check_bugs64(void); -static inline void check_bugs_early(void) -{ - if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64)) - check_bugs64_early(); -} - static inline void __init check_bugs(void) { unsigned int cpu = smp_processor_id(); diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index f1c88f8a1dc5..febdc5564638 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -786,7 +786,8 @@ void __init setup_arch(char **cmdline_p) setup_early_printk(); #endif cpu_report(); - check_bugs_early(); + if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64)) + check_bugs64_early(); #if defined(CONFIG_VT) #if defined(CONFIG_VGA_CONSOLE) -- cgit v1.2.3 From 1492c6b1874ac5ed57d8ffef89e2b5c59f804aa8 Mon Sep 17 00:00:00 2001 From: Henry Willard Date: Wed, 12 Apr 2023 15:29:53 -0600 Subject: MIPS: Don't clear _PAGE_SPECIAL in _PAGE_CHG_MASK In the special case where p = mmap(NULL, ALLOC_SIZE, PROT_READ, MAP_PRIVATE | MAP_ANONYMOUS | MAP_POPULATE, -1, 0); is followed by rc = mprotect(p, ALLOC_SIZE, PROT_NONE); the _PAGE_SPECIAL bit in the page tables will be cleared by mistake and the later unmapped operations will incorrectly modify the struct page for the the zero page. This sequence occurs in the madvise05 test of the Linux Test Project suite of tests. This was discovered while testing an older version of the kernel (5.4.17) on a MIPS device. Unfortunately, support for this device is not available in newer kernels, so I can't test this with the latest Linux kernel code. It looks like the problem exists in newer kernels, but I can't verify it. Except for the LTP test, this sequence of calls is probably not common. Passing it along in the hope it will be useful to someone. Signed-off-by: Henry Willard Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/pgtable-bits.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/mips') diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 2362842ee2b5..1c576679aa87 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -280,6 +280,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED) #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \ - _PAGE_SOFT_DIRTY | _PFN_MASK | _CACHE_MASK) + _PAGE_SOFT_DIRTY | _PFN_MASK | \ + _CACHE_MASK | _PAGE_SPECIAL) #endif /* _ASM_PGTABLE_BITS_H */ -- cgit v1.2.3 From 46e614cc91f7bd6f7872e434e6bcfda44454aac3 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Sun, 23 Apr 2023 09:38:03 +0800 Subject: MIPS: uprobes: Restore thread.trap_nr thread.trap_nr is saved in arch_uprobe_pre_xol(), it should be restored in arch_uprobe_{post,abort}_xol() accordingly, actually it was only done in the post function, just do it in the abort function too, this change is similar with x86 and powerpc. Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/uprobes.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/mips') diff --git a/arch/mips/kernel/uprobes.c b/arch/mips/kernel/uprobes.c index 6b630ed4438d..401b148f8917 100644 --- a/arch/mips/kernel/uprobes.c +++ b/arch/mips/kernel/uprobes.c @@ -191,6 +191,7 @@ void arch_uprobe_abort_xol(struct arch_uprobe *aup, { struct uprobe_task *utask = current->utask; + current->thread.trap_nr = utask->autask.saved_trap_nr; instruction_pointer_set(regs, utask->vaddr); } -- cgit v1.2.3