From 1fc7db2401d62df5a0b19250ddf3bb89d430dd86 Mon Sep 17 00:00:00 2001 From: John David Anglin Date: Wed, 30 Mar 2022 14:42:30 +0000 Subject: parisc: Don't enforce DMA completion order in cache flushes The only place we need to ensure all outstanding cache coherence operations are complete is in invalidate_kernel_vmap_range. All parisc drivers synchronize DMA operations internally and do not call invalidate_kernel_vmap_range. We only need this for non-coherent I/O operations. Signed-off-by: John David Anglin Signed-off-by: Helge Deller --- arch/parisc/kernel/cache.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/parisc/kernel/cache.c') diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c index 0fd04073d4b6..c8a11fcecf4c 100644 --- a/arch/parisc/kernel/cache.c +++ b/arch/parisc/kernel/cache.c @@ -754,6 +754,9 @@ void invalidate_kernel_vmap_range(void *vaddr, int size) unsigned long start = (unsigned long)vaddr; unsigned long end = start + size; + /* Ensure DMA is complete */ + asm_syncdma(); + if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) && (unsigned long)size >= parisc_cache_flush_threshold) { flush_tlb_kernel_range(start, end); -- cgit v1.2.3