From 84d727a109081684c2e01b811cb0d6dc3b9380ca Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 9 Oct 2008 16:58:19 +0000 Subject: powerpc/4xx: Add support for ISA holes on 4xx PCI/X/E This adds support for ISA memory holes on the PCI, PCI-X and PCI-E busses of the 4xx platforms. The patch includes changes to the Bamboo and Canyonlands device-trees to add such a hole, others can be updated separately. The ISA memory hole is an additional outbound window configured in the bridge to generate PCI cycles in the low memory addresses, thus allowing to access things such as the hard-decoded VGA aperture at 0xa0000..0xbffff or other similar things. It's made accessible to userspace via the new legacy_mem file in sysfs for which support was added by a previous patch. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Josh Boyer --- arch/powerpc/boot/dts/canyonlands.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/powerpc/boot/dts/canyonlands.dts') diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts index 79fe412c11c9..0c6d3184dada 100644 --- a/arch/powerpc/boot/dts/canyonlands.dts +++ b/arch/powerpc/boot/dts/canyonlands.dts @@ -343,6 +343,7 @@ * later cannot be changed */ ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ @@ -373,6 +374,7 @@ * later cannot be changed */ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ @@ -414,6 +416,7 @@ * later cannot be changed */ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 + 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; /* Inbound 2GB range starting at 0 */ -- cgit v1.2.3 From cd85400a022335a92fa3c25827179a7ad5e02225 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 5 Dec 2008 01:58:49 +0000 Subject: powerpc/4xx: Add L2 cache node to AMCC Canyonlands dts file With this patch the L2 cache is enabled on Canyonlands to increase the overall performance. There is a known cache coherency issue with the L2 cache, but this is related to the high bandwidth (HB) PLB segment where the memory address is 0x8.xxxx.xxxx (low bandwidth PLB segment is mapped to 0x0.xxxx.xxxx). Since this HB address is currently unused it is safe to enable the L2 cache. Signed-off-by: Stefan Roese Signed-off-by: Josh Boyer --- arch/powerpc/boot/dts/canyonlands.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/powerpc/boot/dts/canyonlands.dts') diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts index 0c6d3184dada..8b5ba8261a36 100644 --- a/arch/powerpc/boot/dts/canyonlands.dts +++ b/arch/powerpc/boot/dts/canyonlands.dts @@ -40,6 +40,7 @@ d-cache-size = <32768>; dcr-controller; dcr-access-method = "native"; + next-level-cache = <&L2C0>; }; }; @@ -104,6 +105,16 @@ dcr-reg = <0x00c 0x002>; }; + L2C0: l2c { + compatible = "ibm,l2-cache-460ex", "ibm,l2-cache"; + dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ + 0x030 0x008>; /* L2 cache DCR's */ + cache-line-size = <32>; /* 32 bytes */ + cache-size = <262144>; /* L2, 256K */ + interrupt-parent = <&UIC1>; + interrupts = <11 1>; + }; + plb { compatible = "ibm,plb-460ex", "ibm,plb4"; #address-cells = <2>; -- cgit v1.2.3