From 98a5f361b8625c6f4841d6ba013bbf0e80d08147 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Fri, 3 Feb 2017 17:20:07 +1100 Subject: powerpc: Add new cache geometry aux vectors This adds AUX vectors for the L1I,D, L2 and L3 cache levels providing for each cache level the size of the cache in bytes and the geometry (line size and number of ways). We chose to not use the existing alpha/sh definition which packs all the information in a single entry per cache level as it is too restricted to represent some of the geometries used on POWER. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Ellerman --- arch/powerpc/include/asm/cache.h | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/powerpc/include/asm/cache.h') diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index d7cf60f87604..5a90292afbad 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -38,6 +38,7 @@ struct ppc_cache_info { u32 log_block_size; u32 blocks_per_page; u32 sets; + u32 assoc; }; struct ppc64_caches { -- cgit v1.2.3