From f6b0df55cad252fedd60aa2ba75a0207d0006283 Mon Sep 17 00:00:00 2001 From: "Aneesh Kumar K.V" Date: Sat, 1 Apr 2017 20:11:47 +0530 Subject: powerpc/mm/radix: Don't do page walk cache flush when doing full mm flush For fullmm tlb flush, we do a flush with RIC_FLUSH_ALL which will invalidate all related caches (radix__tlb_flush()). Hence the pwc flush is not needed. Signed-off-by: Aneesh Kumar K.V Acked-by: Anton Blanchard Signed-off-by: Michael Ellerman --- arch/powerpc/mm/tlb-radix.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/powerpc/mm/tlb-radix.c') diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c index 83dc1ccc2fa1..f3e58bd60d1a 100644 --- a/arch/powerpc/mm/tlb-radix.c +++ b/arch/powerpc/mm/tlb-radix.c @@ -129,6 +129,12 @@ void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr) { unsigned long pid; struct mm_struct *mm = tlb->mm; + /* + * If we are doing a full mm flush, we will do a tlb flush + * with RIC_FLUSH_ALL later. + */ + if (tlb->fullmm) + return; preempt_disable(); @@ -195,6 +201,12 @@ void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr) unsigned long pid; struct mm_struct *mm = tlb->mm; + /* + * If we are doing a full mm flush, we will do a tlb flush + * with RIC_FLUSH_ALL later. + */ + if (tlb->fullmm) + return; preempt_disable(); pid = mm->context.id; -- cgit v1.2.3