From 9149fb3b8e6913eeb0c80010afef9c55892f6e61 Mon Sep 17 00:00:00 2001 From: Eugene Surovegin Date: Sat, 3 Sep 2005 15:55:40 -0700 Subject: [PATCH] ppc32: add 440GX rev.F cputable entry Add PowerPC 440GX rev.F cputable entry. Signed-off-by: Eugene Surovegin Cc: Benjamin Herrenschmidt Cc: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/ppc/kernel/cputable.c') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 8a3d74f2531e..22c187c1f53f 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -922,6 +922,16 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, + { /* 440GX Rev. F */ + .pvr_mask = 0xf0000fff, + .pvr_value = 0x50000894, + .cpu_name = "440GX Rev. F", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, + .icache_bsize = 32, + .dcache_bsize = 32, + }, #endif /* CONFIG_44x */ #ifdef CONFIG_FSL_BOOKE { /* e200z5 */ -- cgit v1.2.3 From 656de7e46901fe3228b592e1d9fc89c353f0fa4e Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Sat, 3 Sep 2005 15:55:42 -0700 Subject: [PATCH] ppc32: add cputable entry for 440SP Rev. A Adds the appropriate cputable entry for PPC440SP so cache line sizes are configured correctly. Signed-off-by: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/ppc/kernel/cputable.c') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 22c187c1f53f..61382341bb01 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -932,6 +932,16 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, + { /* 440SP Rev. A */ + .pvr_mask = 0xff000fff, + .pvr_value = 0x53000891, + .cpu_name = "440SP Rev. A", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, + .icache_bsize = 32, + .dcache_bsize = 32, + }, #endif /* CONFIG_44x */ #ifdef CONFIG_FSL_BOOKE { /* e200z5 */ -- cgit v1.2.3 From ac1ff0477cbe640a6a3652a0cd1aa78026f19246 Mon Sep 17 00:00:00 2001 From: Arthur Othieno Date: Sat, 3 Sep 2005 15:55:51 -0700 Subject: [PATCH] ppc32: Re-order cputable for 750CXe DD2.4 entry "745/755" (pvr_value:0x00083000) is a catch-all entry. Since arch/ppc/kernel/misc.S:identify_cpu() returns on first match, move this lower in the table so 750CXe DD2.4 (pvr_value:0x00083214) may be correctly enumerated. Signed-off-by: Arthur Othieno Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/ppc/kernel/cputable.c') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 61382341bb01..9ab2fad5e56d 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -198,20 +198,6 @@ struct cpu_spec cpu_specs[] = { .num_pmcs = 4, .cpu_setup = __setup_cpu_750 }, - { /* 745/755 */ - .pvr_mask = 0xfffff000, - .pvr_value = 0x00083000, - .cpu_name = "745/755", - .cpu_features = CPU_FTR_COMMON | - CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | - CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | - CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, - .cpu_user_features = COMMON_PPC, - .icache_bsize = 32, - .dcache_bsize = 32, - .num_pmcs = 4, - .cpu_setup = __setup_cpu_750 - }, { /* 750CX (80100 and 8010x?) */ .pvr_mask = 0xfffffff0, .pvr_value = 0x00080100, @@ -254,6 +240,20 @@ struct cpu_spec cpu_specs[] = { .num_pmcs = 4, .cpu_setup = __setup_cpu_750cx }, + { /* 745/755 */ + .pvr_mask = 0xfffff000, + .pvr_value = 0x00083000, + .cpu_name = "745/755", + .cpu_features = CPU_FTR_COMMON | + CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | + CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | + CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, + .cpu_user_features = COMMON_PPC, + .icache_bsize = 32, + .dcache_bsize = 32, + .num_pmcs = 4, + .cpu_setup = __setup_cpu_750 + }, { /* 750FX rev 1.x */ .pvr_mask = 0xffffff00, .pvr_value = 0x70000100, -- cgit v1.2.3 From 7c31625aa844d549cbb8a7aafb94ec4fde8b54a3 Mon Sep 17 00:00:00 2001 From: Arthur Othieno Date: Sat, 3 Sep 2005 15:55:52 -0700 Subject: [PATCH] ppc32: Add cputable entry for 750CXe DD2.4 ("Gekko") Add a table entry for 750CXe DD2.4 ("Gekko") as found in the GameCube from Nintendo: http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/291C8D0EF3EAEC1687256B72005C745C#C1 Signed-off-by: Arthur Othieno Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cputable.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/ppc/kernel/cputable.c') diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 9ab2fad5e56d..fa6df9d4af05 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -240,6 +240,20 @@ struct cpu_spec cpu_specs[] = { .num_pmcs = 4, .cpu_setup = __setup_cpu_750cx }, + { /* 750CXe "Gekko" (83214) */ + .pvr_mask = 0xffffffff, + .pvr_value = 0x00083214, + .cpu_name = "750CXe", + .cpu_features = CPU_FTR_COMMON | + CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | + CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | + CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, + .cpu_user_features = COMMON_PPC, + .icache_bsize = 32, + .dcache_bsize = 32, + .num_pmcs = 4, + .cpu_setup = __setup_cpu_750cx + }, { /* 745/755 */ .pvr_mask = 0xfffff000, .pvr_value = 0x00083000, -- cgit v1.2.3 From bbde630b553d349307fe719486bc06f8cf9c1a2d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 3 Sep 2005 15:55:55 -0700 Subject: [PATCH] ppc32: Added cputable entry for 7448 Added cputable entry for 7448 as well adding it to checks for saving and restoring of cpu state. Signed-off-by: Kumar Gala Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/cpu_setup_6xx.S | 4 ++++ arch/ppc/kernel/cputable.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) (limited to 'arch/ppc/kernel/cputable.c') diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S index 3fb1fb619d2c..bd037caa4055 100644 --- a/arch/ppc/kernel/cpu_setup_6xx.S +++ b/arch/ppc/kernel/cpu_setup_6xx.S @@ -327,6 +327,7 @@ _GLOBAL(__save_cpu_setup) cmplwi cr4,r3,0x8002 /* 7457 */ cmplwi cr5,r3,0x8003 /* 7447A */ cmplwi cr6,r3,0x7000 /* 750FX */ + cmplwi cr7,r3,0x8004 /* 7448 */ /* cr1 is 7400 || 7410 */ cror 4*cr1+eq,4*cr1+eq,4*cr2+eq /* cr0 is 74xx */ @@ -334,6 +335,7 @@ _GLOBAL(__save_cpu_setup) cror 4*cr0+eq,4*cr0+eq,4*cr4+eq cror 4*cr0+eq,4*cr0+eq,4*cr1+eq cror 4*cr0+eq,4*cr0+eq,4*cr5+eq + cror 4*cr0+eq,4*cr0+eq,4*cr7+eq bne 1f /* Backup 74xx specific regs */ mfspr r4,SPRN_MSSCR0 @@ -396,6 +398,7 @@ _GLOBAL(__restore_cpu_setup) cmplwi cr4,r3,0x8002 /* 7457 */ cmplwi cr5,r3,0x8003 /* 7447A */ cmplwi cr6,r3,0x7000 /* 750FX */ + cmplwi cr7,r3,0x8004 /* 7448 */ /* cr1 is 7400 || 7410 */ cror 4*cr1+eq,4*cr1+eq,4*cr2+eq /* cr0 is 74xx */ @@ -403,6 +406,7 @@ _GLOBAL(__restore_cpu_setup) cror 4*cr0+eq,4*cr0+eq,4*cr4+eq cror 4*cr0+eq,4*cr0+eq,4*cr1+eq cror 4*cr0+eq,4*cr0+eq,4*cr5+eq + cror 4*cr0+eq,4*cr0+eq,4*cr7+eq bne 2f /* Restore 74xx specific regs */ lwz r4,CS_MSSCR0(r5) diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index fa6df9d4af05..546e1ea4cafa 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c @@ -550,6 +550,22 @@ struct cpu_spec cpu_specs[] = { .num_pmcs = 6, .cpu_setup = __setup_cpu_745x }, + { /* 7448 */ + .pvr_mask = 0xffff0000, + .pvr_value = 0x80040000, + .cpu_name = "7448", + .cpu_features = CPU_FTR_COMMON | + CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | + CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | + CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | + CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | + CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT, + .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP, + .icache_bsize = 32, + .dcache_bsize = 32, + .num_pmcs = 6, + .cpu_setup = __setup_cpu_745x + }, { /* 82xx (8240, 8245, 8260 are all 603e cores) */ .pvr_mask = 0x7fff0000, .pvr_value = 0x00810000, -- cgit v1.2.3