From 30aacebed0f0619f23ce84df7c59ad033ca08d77 Mon Sep 17 00:00:00 2001 From: Eugene Surovegin Date: Tue, 25 Apr 2006 01:22:44 -0700 Subject: [PATCH] ppc32: add 440GX erratum 440_43 workaround This patch adds workaround for PPC 440GX erratum 440_43. According to this erratum spurious MachineChecks (caused by L1 cache parity) can happen during DataTLB miss processing. We disable L1 cache parity checking for 440GX rev.C and rev.F Signed-off-by: Eugene Surovegin Signed-off-by: Paul Mackerras --- arch/ppc/syslib/ibm440gx_common.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/ppc/syslib/ibm440gx_common.h') diff --git a/arch/ppc/syslib/ibm440gx_common.h b/arch/ppc/syslib/ibm440gx_common.h index a2ab9fab8e34..a03ec6022e8f 100644 --- a/arch/ppc/syslib/ibm440gx_common.h +++ b/arch/ppc/syslib/ibm440gx_common.h @@ -29,6 +29,10 @@ void ibm440gx_get_clocks(struct ibm44x_clocks*, unsigned int sys_clk, unsigned int ser_clk) __init; +/* common 440GX platform init */ +void ibm440gx_platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) __init; + /* Enable L2 cache */ void ibm440gx_l2c_enable(void) __init; -- cgit v1.2.3