From 32b62f446827f696cc474a6d83cea93693c5ed49 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Fri, 25 Mar 2016 15:52:35 +0100 Subject: perf/x86/amd: Cleanup Fam10h NB event constraints Avoid allocating the AMD NB event constraints data structure when not needed. This gets rid of x86_max_cores usage and avoids allocating this on AMD Core Perfctr supporting hardware (which has separate MSRs for NB events). Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Borislav Petkov Cc: aherrmann@suse.com Cc: Rui Huang Cc: Borislav Petkov Cc: jencce.kernel@gmail.com Link: http://lkml.kernel.org/r/20160320124629.GY6375@twins.programming.kicks-ass.net Signed-off-by: Thomas Gleixner --- arch/x86/events/perf_event.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/x86/events/perf_event.h') diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index ba6ef18528c9..716d0482f5db 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -607,6 +607,11 @@ struct x86_pmu { */ atomic_t lbr_exclusive[x86_lbr_exclusive_max]; + /* + * AMD bits + */ + unsigned int amd_nb_constraints : 1; + /* * Extra registers for events */ -- cgit v1.2.3