From 6ec7026ac01f3db039e0428db1f37590685ad3e7 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 7 Mar 2016 01:36:33 +0300 Subject: xtensa: use context structure for debug exceptions With implementation of data breakpoints debug exceptions raised when PS.EXCM is set need to be handled, e.g. window overflow code can write to watched userspace address. Currently debug exception handler uses EXCSAVE and DEPC SRs to save temporary registers, but DEPC may not be available when PS.EXCM is set and more space will be needed to save additional state. Reorganize debug context: create per-CPU structure debug_table instance and store its address in the EXCSAVE instead of debug_exception function address. Expand this structure when more save space is needed. Signed-off-by: Max Filippov --- arch/xtensa/kernel/traps.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/xtensa/kernel/traps.c') diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index a8b8dae4139a..e4764f216a7a 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c @@ -157,6 +157,8 @@ COPROCESSOR(7), DEFINE_PER_CPU(unsigned long, exc_table[EXC_TABLE_SIZE/4]); +DEFINE_PER_CPU(struct debug_table, debug_table); + void die(const char*, struct pt_regs*, long); static inline void @@ -372,6 +374,15 @@ static void trap_init_excsave(void) __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (excsave1)); } +static void trap_init_debug(void) +{ + unsigned long debugsave = (unsigned long)this_cpu_ptr(&debug_table); + + this_cpu_ptr(&debug_table)->debug_exception = debug_exception; + __asm__ __volatile__("wsr %0, excsave" __stringify(XCHAL_DEBUGLEVEL) + :: "a"(debugsave)); +} + /* * Initialize dispatch tables. * @@ -415,12 +426,14 @@ void __init trap_init(void) /* Initialize EXCSAVE_1 to hold the address of the exception table. */ trap_init_excsave(); + trap_init_debug(); } #ifdef CONFIG_SMP void secondary_trap_init(void) { trap_init_excsave(); + trap_init_debug(); } #endif -- cgit v1.2.3