From a33f1788192d13165594f8ec6975dbae34502ec9 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Sun, 8 Sep 2013 09:43:29 +0200 Subject: ARM: OMAP3: Add secure function omap_smc3() which calling instruction smc #1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Here is new version (v4) of omap secure part patch: Other secure functions omap_smc1() and omap_smc2() calling instruction smc #0 but Nokia RX-51 board needs to call smc #1 for PPA access. Signed-off-by: Ivaylo Dimitrov Signed-off-by: Pali Rohár Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap-secure.h | 1 + arch/arm/mach-omap2/omap-smc.S | 21 ++++++++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 0e729170c46b..c4586f42ea98 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -51,6 +51,7 @@ extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, u32 arg3, u32 arg4); extern u32 omap_smc2(u32 id, u32 falg, u32 pargs); +extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs); extern phys_addr_t omap_secure_ram_mempool_base(void); extern int omap_secure_ram_reserve_memblock(void); diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S index f6441c13cd8c..fd90125bffc7 100644 --- a/arch/arm/mach-omap2/omap-smc.S +++ b/arch/arm/mach-omap2/omap-smc.S @@ -1,9 +1,11 @@ /* - * OMAP44xx secure APIs file. + * OMAP34xx and OMAP44xx secure APIs file. * * Copyright (C) 2010 Texas Instruments, Inc. * Written by Santosh Shilimkar * + * Copyright (C) 2012 Ivaylo Dimitrov + * Copyright (C) 2013 Pali Rohár * * This program is free software,you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -54,6 +56,23 @@ ENTRY(omap_smc2) ldmfd sp!, {r4-r12, pc} ENDPROC(omap_smc2) +/** + * u32 omap_smc3(u32 service_id, u32 process_id, u32 flag, u32 pargs) + * Low level common routine for secure HAL and PPA APIs via smc #1 + * r0 - @service_id: Secure Service ID + * r1 - @process_id: Process ID + * r2 - @flag: Flag to indicate the criticality of operation + * r3 - @pargs: Physical address of parameter list + */ +ENTRY(omap_smc3) + stmfd sp!, {r4-r11, lr} + mov r12, r0 @ Copy the secure service ID + mov r6, #0xff @ Indicate new Task call + dsb @ Memory Barrier (not sure if needed, copied from omap_smc2) + smc #1 @ Call PPA service + ldmfd sp!, {r4-r11, pc} +ENDPROC(omap_smc3) + ENTRY(omap_modify_auxcoreboot0) stmfd sp!, {r1-r12, lr} ldr r12, =0x104 -- cgit v1.2.3 From 4748a7240284b0f68bd47a66365c2cd561939830 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Wed, 18 Sep 2013 21:43:56 +0200 Subject: ARM: OMAP3: RX-51: ARM errata 430973 workaround MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Closed and signed Nokia X-Loader bootloader stored in RX-51 nand does not set IBE bit in ACTLR and starting kernel in non-secure mode. So direct write to ACTLR by our kernel does not working and the code for ARM errata 430973 in commit 7ce236fcd6fd45b0441a2d49acb2ceb2de2e8a47 that sets IBE bit is a noop. In order to have workaround for ARM errata 430973 from non-secure world on RX-51 we needs Secure Monitor Call to set IBE BIT in ACTLR. This patch adds RX-51 specific secure support code and sets IBE bit in ACTLR during board init code for ARM errata 430973 workaround. Note that new function rx51_secure_dispatcher() differs from existing omap_secure_dispatcher(). It calling omap_smc3() and param[0] is nargs+1. ARM errata 430973 workaround is needed for thumb-2 ISA compiled userspace binaries. Without this workaround thumb-2 binaries crashing. So with this patch it is possible to recompile and run applications/binaries with thumb-2 ISA on RX-51. Signed-off-by: Ivaylo Dimitrov Signed-off-by: Pali Rohár Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-rx51.c | 12 ++++++++ arch/arm/mach-omap2/omap-secure.c | 65 +++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/omap-secure.h | 11 +++++++ 3 files changed, 88 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index 7735105561d8..db168c9627a1 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c @@ -2,6 +2,8 @@ * Board support file for Nokia N900 (aka RX-51). * * Copyright (C) 2007, 2008 Nokia + * Copyright (C) 2012 Ivaylo Dimitrov + * Copyright (C) 2013 Pali Rohár * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -31,7 +33,9 @@ #include "mux.h" #include "gpmc.h" #include "pm.h" +#include "soc.h" #include "sdram-nokia.h" +#include "omap-secure.h" #define RX51_GPIO_SLEEP_IND 162 @@ -103,6 +107,14 @@ static void __init rx51_init(void) usb_musb_init(&musb_board_data); rx51_peripherals_init(); + if (omap_type() == OMAP2_DEVICE_TYPE_SEC) { +#ifdef CONFIG_ARM_ERRATA_430973 + pr_info("RX-51: Enabling ARM errata 430973 workaround\n"); + /* set IBE to 1 */ + rx51_secure_update_aux_cr(BIT(6), 0); +#endif + } + /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index b970440cffca..146a7c4e2a13 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -3,6 +3,8 @@ * * Copyright (C) 2011 Texas Instruments, Inc. * Santosh Shilimkar + * Copyright (C) 2012 Ivaylo Dimitrov + * Copyright (C) 2013 Pali Rohár * * * This program is free software,you can redistribute it and/or modify @@ -70,3 +72,66 @@ phys_addr_t omap_secure_ram_mempool_base(void) { return omap_secure_memblock_base; } + +/** + * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls + * @idx: The PPA API index + * @process: Process ID + * @flag: The flag indicating criticality of operation + * @nargs: Number of valid arguments out of four. + * @arg1, arg2, arg3 args4: Parameters passed to secure API + * + * Return the non-zero error value on failure. + * + * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because + * it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1 + */ +u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, + u32 arg1, u32 arg2, u32 arg3, u32 arg4) +{ + u32 ret; + u32 param[5]; + + param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */ + param[1] = arg1; + param[2] = arg2; + param[3] = arg3; + param[4] = arg4; + + /* + * Secure API needs physical address + * pointer for the parameters + */ + local_irq_disable(); + local_fiq_disable(); + flush_cache_all(); + outer_clean_range(__pa(param), __pa(param + 5)); + ret = omap_smc3(idx, process, flag, __pa(param)); + flush_cache_all(); + local_fiq_enable(); + local_irq_enable(); + + return ret; +} + +/** + * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register + * @set_bits: bits to set in ACR + * @clr_bits: bits to clear in ACR + * + * Return the non-zero error value on failure. +*/ +u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits) +{ + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + + return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR, + 0, + FLAG_START_CRITICAL, + 1, acr, 0, 0, 0); +} diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index c4586f42ea98..51b59c686a53 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -3,6 +3,8 @@ * * Copyright (C) 2011 Texas Instruments, Inc. * Santosh Shilimkar + * Copyright (C) 2012 Ivaylo Dimitrov + * Copyright (C) 2013 Pali Rohár * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -46,6 +48,11 @@ #define OMAP4_PPA_L2_POR_INDEX 0x23 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 +/* Secure RX-51 PPA (Primary Protected Application) APIs */ +#define RX51_PPA_HWRNG 29 +#define RX51_PPA_L2_INVAL 40 +#define RX51_PPA_WRITE_ACR 42 + #ifndef __ASSEMBLER__ extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, @@ -55,6 +62,10 @@ extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs); extern phys_addr_t omap_secure_ram_mempool_base(void); extern int omap_secure_ram_reserve_memblock(void); +extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, + u32 arg1, u32 arg2, u32 arg3, u32 arg4); +extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); + #ifdef CONFIG_OMAP4_ERRATA_I688 extern int omap_barrier_reserve_memblock(void); #else -- cgit v1.2.3 From d2065e2b5bb3ec986f0f3ba044a81a136767d0b4 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Fri, 20 Sep 2013 15:25:07 +0200 Subject: RX-51: Add support for OMAP3 ROM Random Number Generator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adding this driver as platform device and only for RX-51 until somebody test if it working also on other OMAP3 HS devices and until there will be generic ARM way to deal with SMC calls. Signed-off-by: Pali Rohár [tony@atomide.com: folded in the clock alias change] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-rx51-peripherals.c | 19 +++++++++++++++++++ arch/arm/mach-omap2/cclock3xxx_data.c | 1 + arch/arm/mach-omap2/omap-secure.c | 11 +++++++++++ arch/arm/mach-omap2/omap-secure.h | 1 + 4 files changed, 32 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index c3270c0f1fce..497d2604c7c5 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -57,6 +57,8 @@ #include "common-board-devices.h" #include "gpmc.h" #include "gpmc-onenand.h" +#include "soc.h" +#include "omap-secure.h" #define SYSTEM_REV_B_USES_VAUX3 0x1699 #define SYSTEM_REV_S_USES_VAUX3 0x8 @@ -1289,6 +1291,22 @@ static void __init rx51_init_twl4030_hwmon(void) platform_device_register(&madc_hwmon); } +static struct platform_device omap3_rom_rng_device = { + .name = "omap3-rom-rng", + .id = -1, + .dev = { + .platform_data = rx51_secure_rng_call, + }, +}; + +static void __init rx51_init_omap3_rom_rng(void) +{ + if (omap_type() == OMAP2_DEVICE_TYPE_SEC) { + pr_info("RX-51: Registring OMAP3 HWRNG device\n"); + platform_device_register(&omap3_rom_rng_device); + } +} + void __init rx51_peripherals_init(void) { rx51_i2c_init(); @@ -1309,5 +1327,6 @@ void __init rx51_peripherals_init(void) rx51_charger_init(); rx51_init_twl4030_hwmon(); + rx51_init_omap3_rom_rng(); } diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c index 334b76745900..03a2829beb8e 100644 --- a/arch/arm/mach-omap2/cclock3xxx_data.c +++ b/arch/arm/mach-omap2/cclock3xxx_data.c @@ -3275,6 +3275,7 @@ static struct omap_clk omap36xx_clks[] = { static struct omap_clk omap34xx_omap36xx_clks[] = { CLK(NULL, "aes1_ick", &aes1_ick), CLK("omap_rng", "ick", &rng_ick), + CLK("omap3-rom-rng", "ick", &rng_ick), CLK(NULL, "sha11_ick", &sha11_ick), CLK(NULL, "des1_ick", &des1_ick), CLK(NULL, "cam_mclk", &cam_mclk), diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c index 146a7c4e2a13..5ac122e88f67 100644 --- a/arch/arm/mach-omap2/omap-secure.c +++ b/arch/arm/mach-omap2/omap-secure.c @@ -135,3 +135,14 @@ u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits) FLAG_START_CRITICAL, 1, acr, 0, 0, 0); } + +/** + * rx51_secure_rng_call: Routine for HW random generator + */ +u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag) +{ + return rx51_secure_dispatcher(RX51_PPA_HWRNG, + 0, + NO_FLAG, + 3, ptr, count, flag, 0); +} diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 51b59c686a53..f6cabb0033fc 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -65,6 +65,7 @@ extern int omap_secure_ram_reserve_memblock(void); extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, u32 arg1, u32 arg2, u32 arg3, u32 arg4); extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); +extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); #ifdef CONFIG_OMAP4_ERRATA_I688 extern int omap_barrier_reserve_memblock(void); -- cgit v1.2.3