From bbbcf64360bb32c8eab46020b78a0c0e0de4c40c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 18 Jan 2019 23:52:24 +0100 Subject: ARM: dts: meson8b: add the temperature calibration data for the SAR ADC The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 9faf70a6ed9a..fe84a8c3ce81 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -407,6 +407,11 @@ compatible = "amlogic,meson8b-efuse"; clocks = <&clkc CLKID_EFUSE>; clock-names = "core"; + + temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; }; ðmac { @@ -505,6 +510,9 @@ clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_SAR_ADC>; clock-names = "clkin", "core"; + amlogic,hhi-sysctrl = <&hhi>; + nvmem-cells = <&temperature_calib>; + nvmem-cell-names = "temperature_calib"; }; &sdio { -- cgit v1.2.3