From ce2e572cfe7b2fc3f0e9da4aa7bc61a2c2c51fc7 Mon Sep 17 00:00:00 2001 From: Daniel J Blueman <daniel@numascale.com> Date: Mon, 21 Sep 2015 18:02:25 +0800 Subject: x86/numachip: Introduce Numachip2 timer mechanisms Add 1GHz 64-bit Numachip2 clocksource timer support for accurate system-wide timekeeping, as core TSCs are unsynchronised. Additionally, add a per-core clockevent mechanism that interrupts via the platform IPI vector after a programmed period. [ tglx: Taking it through x86 due to dependencies ] Signed-off-by: Daniel J Blueman <daniel@numascale.com> Acked-by: Steffen Persvold <sp@numascale.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Link: http://lkml.kernel.org/r/1442829745-29311-1-git-send-email-daniel@numascale.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de> --- arch/x86/include/asm/numachip/numachip_csr.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch') diff --git a/arch/x86/include/asm/numachip/numachip_csr.h b/arch/x86/include/asm/numachip/numachip_csr.h index e09d845ce406..29719eecdc2e 100644 --- a/arch/x86/include/asm/numachip/numachip_csr.h +++ b/arch/x86/include/asm/numachip/numachip_csr.h @@ -59,6 +59,10 @@ static inline void write_lcsr(unsigned long offset, unsigned int val) #define NUMACHIP2_LCSR_BASE 0xf0000000UL #define NUMACHIP2_LCSR_SIZE 0x1000000UL #define NUMACHIP2_APIC_ICR 0x100000 +#define NUMACHIP2_TIMER_DEADLINE 0x200000 +#define NUMACHIP2_TIMER_INT 0x200008 +#define NUMACHIP2_TIMER_NOW 0x200018 +#define NUMACHIP2_TIMER_RESET 0x200020 static inline void __iomem *numachip2_lcsr_address(unsigned long offset) { @@ -86,4 +90,9 @@ static inline void numachip2_write64_lcsr(unsigned long offset, u64 val) writeq(val, numachip2_lcsr_address(offset)); } +static inline unsigned int numachip2_timer(void) +{ + return (smp_processor_id() % 48) << 6; +} + #endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */ -- cgit v1.2.3