From 33707260422475385c6f33f526c71805a3dc5dab Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 8 Feb 2017 09:28:15 +1300 Subject: clk: mvebu: Expand mv98dx3236-core-clock support The initial implementation in commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency. Port code from the Marvell supplied Linux kernel to support different PLL frequencies and provide clock gating support. Signed-off-by: Chris Packham Signed-off-by: Stephen Boyd --- drivers/clk/mvebu/armada-xp.c | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'drivers/clk/mvebu/armada-xp.c') diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c index 890a863ae0d0..0ec44ae9a2a2 100644 --- a/drivers/clk/mvebu/armada-xp.c +++ b/drivers/clk/mvebu/armada-xp.c @@ -232,16 +232,3 @@ static void __init axp_clk_init(struct device_node *np) mvebu_clk_gating_setup(cgnp, axp_gating_desc); } CLK_OF_DECLARE(axp_clk, "marvell,armada-xp-core-clock", axp_clk_init); - -static void __init mv98dx3236_clk_init(struct device_node *np) -{ - struct device_node *cgnp = - of_find_compatible_node(NULL, NULL, "marvell,armada-xp-gating-clock"); - - mvebu_coreclk_setup(np, &mv98dx3236_coreclks); - - if (cgnp) - mvebu_clk_gating_setup(cgnp, mv98dx3236_gating_desc); -} -CLK_OF_DECLARE(mv98dx3236_clk, "marvell,mv98dx3236-core-clock", - mv98dx3236_clk_init); -- cgit v1.2.3