From 9e2631313c463c11645db046beb9bdecaf28b62f Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 15 Jan 2014 10:47:24 -0800 Subject: clk: qcom: Add support for phase locked loops (PLLs) Add support for Qualcomm's PLLs (phase locked loops). This is sufficient enough to be able to determine the rate the PLL is running at. We can add rate setting support later when it's needed. Signed-off-by: Stephen Boyd Signed-off-by: Mike Turquette --- drivers/clk/qcom/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/qcom/Makefile') diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index f9faa8fa9392..7871e235c2b1 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-regmap.o +clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-pll.o -- cgit v1.2.3