From c8b088224c25ef4f5270f9de6a3516181b63f38c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 12 Apr 2022 17:13:12 +0100 Subject: clk: renesas: Add support for RZ/G2UL SoC The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are not present on RZ/G2UL. This patch adds minimal clock and reset entries required to boot the system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/clk/renesas/rzg2l-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/clk/renesas/rzg2l-cpg.c') diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index f626d2704477..1ce35f65682b 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -945,6 +945,12 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev) } static const struct of_device_id rzg2l_cpg_match[] = { +#ifdef CONFIG_CLK_R9A07G043 + { + .compatible = "renesas,r9a07g043-cpg", + .data = &r9a07g043_cpg_info, + }, +#endif #ifdef CONFIG_CLK_R9A07G044 { .compatible = "renesas,r9a07g044-cpg", -- cgit v1.2.3