From b9e4ba541607e6ee9c6c8493f51198fe3af03aec Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Thu, 3 Jul 2014 02:02:37 +0200 Subject: clk: rockchip: add clock controller for rk3288 Add the clock tree definition for the new rk3288 SoC. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz Signed-off-by: Mike Turquette --- drivers/clk/rockchip/clk.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/clk/rockchip/clk.h') diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 32c334d7fc87..887cbdeca2aa 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -40,6 +40,15 @@ #define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110) #define RK2928_MISC_CON 0x134 +#define RK3288_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3288_MODE_CON 0x50 +#define RK3288_CLKSEL_CON(x) (x * 0x4 + 0x60) +#define RK3288_CLKGATE_CON(x) (x * 0x4 + 0x160) +#define RK3288_GLB_SRST_FST 0x1b0 +#define RK3288_GLB_SRST_SND 0x1b4 +#define RK3288_SOFTRST_CON(x) (x * 0x4 + 0x1b8) +#define RK3288_MISC_CON 0x1e8 + enum rockchip_pll_type { pll_rk3066, }; -- cgit v1.2.3