From 4f4f85fa0b96a35429ebb4bc278d70ae0f72113c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 29 Jul 2014 10:17:53 +0200 Subject: clk: tegra: Implement memory-controller clock The memory controller clock runs either at half or the same frequency as the EMC clock. Reviewed-By: Tomeu Vizoso Acked-by: Mike Turquette Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk-divider.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/clk/tegra/clk-divider.c') diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index 290f9c1a3749..59a5714dfe18 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -185,3 +185,16 @@ struct clk *tegra_clk_register_divider(const char *name, return clk; } + +static const struct clk_div_table mc_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 1 }, + { .val = 0, .div = 0 }, +}; + +struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, + void __iomem *reg, spinlock_t *lock) +{ + return clk_register_divider_table(NULL, name, parent_name, 0, reg, + 16, 1, 0, mc_div_table, lock); +} -- cgit v1.2.3