From 1ec7032ad517714108cc53a6ee7067276ca21e80 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 20 Apr 2015 14:34:57 +0200 Subject: clk: tegra: Add fixed factor peripheral clock type Some of the peripheral clocks on Tegra are derived from one of the top- level PLLs with a fixed factor. Support these clocks by implementing the ->enable() and ->disable() callbacks using the peripheral clock register banks and the ->recalc_rate() by dividing the parent rate by the fixed factor. Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/clk/tegra/clk.h') diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 3ef530a8989d..7264f17e269e 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -516,6 +516,23 @@ struct clk *tegra_clk_register_periph_gate(const char *name, const char *parent_name, u8 gate_flags, void __iomem *clk_base, unsigned long flags, int clk_num, int *enable_refcnt); +struct tegra_clk_periph_fixed { + struct clk_hw hw; + void __iomem *base; + const struct tegra_clk_periph_regs *regs; + unsigned int mul; + unsigned int div; + unsigned int num; +}; + +struct clk *tegra_clk_register_periph_fixed(const char *name, + const char *parent, + unsigned long flags, + void __iomem *base, + unsigned int mul, + unsigned int div, + unsigned int num); + /** * struct clk-periph - peripheral clock * -- cgit v1.2.3