From 2db2fcd7a2e3036bc4c9937c686abadb9d32524c Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 19 Mar 2020 22:02:21 +0300 Subject: clk: tegra20: Use custom CCLK implementation We're going to use the generic cpufreq-dt driver on Tegra20 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra20 SoCs to use that implementation. Acked-by: Peter De Schrijver Tested-by: Peter Geis Tested-by: Marcel Ziswiler Tested-by: Jasper Korten Tested-by: David Heidelberg Tested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/clk/tegra/clk-tegra20.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/clk/tegra') diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 085feb04e913..3efc651b42e3 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -391,6 +391,8 @@ static struct tegra_clk_pll_params pll_x_params = { .lock_delay = 300, .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, }; static struct tegra_clk_pll_params pll_e_params = { @@ -702,9 +704,10 @@ static void tegra20_super_clk_init(void) struct clk *clk; /* CCLK */ - clk = tegra_clk_register_super_mux("cclk", cclk_parents, + clk = tegra_clk_register_super_cclk("cclk", cclk_parents, ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT, - clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL); + clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK, + NULL); clks[TEGRA20_CLK_CCLK] = clk; /* SCLK */ -- cgit v1.2.3