From 30bd3b56db37a2c2eb6d3bb14ce02156807c79ed Mon Sep 17 00:00:00 2001 From: Malcolm Priestley <tvboxspy@gmail.com> Date: Sun, 13 Feb 2011 20:12:15 -0300 Subject: [media] DM04/QQBOX Fix issue with firmware release and cold reset Fix issue where firmware does not release on cold reset. Also, default firmware never cold resets in multi tuner environment. Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/lmedm04.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/lmedm04.c b/drivers/media/dvb/dvb-usb/lmedm04.c index f2db01212ca1..3c521db0a130 100644 --- a/drivers/media/dvb/dvb-usb/lmedm04.c +++ b/drivers/media/dvb/dvb-usb/lmedm04.c @@ -747,7 +747,7 @@ static int lme_firmware_switch(struct usb_device *udev, int cold) fw_lme = fw_s0194; ret = request_firmware(&fw, fw_lme, &udev->dev); if (ret == 0) { - cold = 0;/*lme2510-s0194 cannot cold reset*/ + cold = 0; break; } dvb_usb_lme2510_firmware = TUNER_LG; @@ -769,8 +769,10 @@ static int lme_firmware_switch(struct usb_device *udev, int cold) case TUNER_S7395: fw_lme = fw_c_s7395; ret = request_firmware(&fw, fw_lme, &udev->dev); - if (ret == 0) + if (ret == 0) { + cold = 0; break; + } dvb_usb_lme2510_firmware = TUNER_LG; case TUNER_LG: fw_lme = fw_c_lg; @@ -796,14 +798,14 @@ static int lme_firmware_switch(struct usb_device *udev, int cold) ret = lme2510_download_firmware(udev, fw); } + release_firmware(fw); + if (cold) { info("FRM Changing to %s firmware", fw_lme); lme_coldreset(udev); return -ENODEV; } - release_firmware(fw); - return ret; } @@ -1220,5 +1222,5 @@ module_exit(lme2510_module_exit); MODULE_AUTHOR("Malcolm Priestley <tvboxspy@gmail.com>"); MODULE_DESCRIPTION("LME2510(C) DVB-S USB2.0"); -MODULE_VERSION("1.80"); +MODULE_VERSION("1.81"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From abd34d8d6b213c792c1a06fd75488595c5fb6d3f Mon Sep 17 00:00:00 2001 From: Bjørn Mork <bjorn@mork.no> Date: Mon, 21 Mar 2011 11:35:56 -0300 Subject: [media] use pci_dev->revision MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit pci_setup_device() has saved the PCI revision in the pci_dev struct since Linux 2.6.23. Use it. Cc: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Bjørn Mork <bjorn@mork.no> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/common/saa7146_core.c | 7 +------ drivers/media/dvb/b2c2/flexcop-pci.c | 4 +--- drivers/media/dvb/bt8xx/bt878.c | 2 +- drivers/media/dvb/mantis/mantis_pci.c | 5 ++--- drivers/media/video/bt8xx/bttv-driver.c | 2 +- drivers/media/video/cx18/cx18-driver.c | 2 +- drivers/media/video/cx23885/cx23885-core.c | 2 +- drivers/media/video/cx88/cx88-mpeg.c | 2 +- drivers/media/video/cx88/cx88-video.c | 2 +- drivers/media/video/ivtv/ivtv-driver.c | 4 +--- drivers/media/video/saa7134/saa7134-core.c | 2 +- drivers/media/video/saa7164/saa7164-core.c | 2 +- drivers/media/video/zoran/zoran_card.c | 2 +- 13 files changed, 14 insertions(+), 24 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/common/saa7146_core.c b/drivers/media/common/saa7146_core.c index 9f47e383c57a..9af2140b57a4 100644 --- a/drivers/media/common/saa7146_core.c +++ b/drivers/media/common/saa7146_core.c @@ -378,12 +378,7 @@ static int saa7146_init_one(struct pci_dev *pci, const struct pci_device_id *ent dev->pci = pci; /* get chip-revision; this is needed to enable bug-fixes */ - err = pci_read_config_dword(pci, PCI_CLASS_REVISION, &dev->revision); - if (err < 0) { - ERR(("pci_read_config_dword() failed.\n")); - goto err_disable; - } - dev->revision &= 0xf; + dev->revision = pci->revision; /* remap the memory from virtual to physical address */ diff --git a/drivers/media/dvb/b2c2/flexcop-pci.c b/drivers/media/dvb/b2c2/flexcop-pci.c index 03f96d6ca894..44f8fb5f17ff 100644 --- a/drivers/media/dvb/b2c2/flexcop-pci.c +++ b/drivers/media/dvb/b2c2/flexcop-pci.c @@ -290,10 +290,8 @@ static void flexcop_pci_dma_exit(struct flexcop_pci *fc_pci) static int flexcop_pci_init(struct flexcop_pci *fc_pci) { int ret; - u8 card_rev; - pci_read_config_byte(fc_pci->pdev, PCI_CLASS_REVISION, &card_rev); - info("card revision %x", card_rev); + info("card revision %x", fc_pci->pdev->revision); if ((ret = pci_enable_device(fc_pci->pdev)) != 0) return ret; diff --git a/drivers/media/dvb/bt8xx/bt878.c b/drivers/media/dvb/bt8xx/bt878.c index 99d62094f908..b34fa95185e4 100644 --- a/drivers/media/dvb/bt8xx/bt878.c +++ b/drivers/media/dvb/bt8xx/bt878.c @@ -460,7 +460,7 @@ static int __devinit bt878_probe(struct pci_dev *dev, goto fail0; } - pci_read_config_byte(dev, PCI_CLASS_REVISION, &bt->revision); + bt->revision = dev->revision; pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); diff --git a/drivers/media/dvb/mantis/mantis_pci.c b/drivers/media/dvb/mantis/mantis_pci.c index 10a432a79d00..371558af2d96 100644 --- a/drivers/media/dvb/mantis/mantis_pci.c +++ b/drivers/media/dvb/mantis/mantis_pci.c @@ -48,7 +48,7 @@ int __devinit mantis_pci_init(struct mantis_pci *mantis) { - u8 revision, latency; + u8 latency; struct mantis_hwconfig *config = mantis->hwconfig; struct pci_dev *pdev = mantis->pdev; int err, ret = 0; @@ -95,9 +95,8 @@ int __devinit mantis_pci_init(struct mantis_pci *mantis) } pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency); - pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision); mantis->latency = latency; - mantis->revision = revision; + mantis->revision = pdev->revision; dprintk(MANTIS_ERROR, 0, " Mantis Rev %d [%04x:%04x], ", mantis->revision, diff --git a/drivers/media/video/bt8xx/bttv-driver.c b/drivers/media/video/bt8xx/bttv-driver.c index 91399c94cd18..a97cf2750bd9 100644 --- a/drivers/media/video/bt8xx/bttv-driver.c +++ b/drivers/media/video/bt8xx/bttv-driver.c @@ -4303,7 +4303,7 @@ static int __devinit bttv_probe(struct pci_dev *dev, goto fail0; } - pci_read_config_byte(dev, PCI_CLASS_REVISION, &btv->revision); + btv->revision = dev->revision; pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); printk(KERN_INFO "bttv%d: Bt%d (rev %d) at %s, ", bttv_num,btv->id, btv->revision, pci_name(dev)); diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c index 321c1b79794c..841ea4ef6200 100644 --- a/drivers/media/video/cx18/cx18-driver.c +++ b/drivers/media/video/cx18/cx18-driver.c @@ -818,7 +818,7 @@ static int cx18_setup_pci(struct cx18 *cx, struct pci_dev *pci_dev, cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config_word(pci_dev, PCI_COMMAND, cmd); - pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &cx->card_rev); + cx->card_rev = pci_dev->revision; pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &pci_latency); if (pci_latency < 64 && cx18_pci_latency) { diff --git a/drivers/media/video/cx23885/cx23885-core.c b/drivers/media/video/cx23885/cx23885-core.c index 9933810b4e33..64d9b2136ff6 100644 --- a/drivers/media/video/cx23885/cx23885-core.c +++ b/drivers/media/video/cx23885/cx23885-core.c @@ -2045,7 +2045,7 @@ static int __devinit cx23885_initdev(struct pci_dev *pci_dev, } /* print pci info */ - pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); + dev->pci_rev = pci_dev->revision; pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, " "latency: %d, mmio: 0x%llx\n", dev->name, diff --git a/drivers/media/video/cx88/cx88-mpeg.c b/drivers/media/video/cx88/cx88-mpeg.c index addf9545e9bf..9b500e691a5c 100644 --- a/drivers/media/video/cx88/cx88-mpeg.c +++ b/drivers/media/video/cx88/cx88-mpeg.c @@ -474,7 +474,7 @@ static int cx8802_init_common(struct cx8802_dev *dev) return -EIO; } - pci_read_config_byte(dev->pci, PCI_CLASS_REVISION, &dev->pci_rev); + dev->pci_rev = dev->pci->revision; pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER, &dev->pci_lat); printk(KERN_INFO "%s/2: found at %s, rev: %d, irq: %d, " "latency: %d, mmio: 0x%llx\n", dev->core->name, diff --git a/drivers/media/video/cx88/cx88-video.c b/drivers/media/video/cx88/cx88-video.c index 287a41ee1c4f..b1f734dccea0 100644 --- a/drivers/media/video/cx88/cx88-video.c +++ b/drivers/media/video/cx88/cx88-video.c @@ -1832,7 +1832,7 @@ static int __devinit cx8800_initdev(struct pci_dev *pci_dev, dev->core = core; /* print pci info */ - pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); + dev->pci_rev = pci_dev->revision; pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, " "latency: %d, mmio: 0x%llx\n", core->name, diff --git a/drivers/media/video/ivtv/ivtv-driver.c b/drivers/media/video/ivtv/ivtv-driver.c index 39946420b301..a4e4dfdbc2f2 100644 --- a/drivers/media/video/ivtv/ivtv-driver.c +++ b/drivers/media/video/ivtv/ivtv-driver.c @@ -810,7 +810,6 @@ static int ivtv_setup_pci(struct ivtv *itv, struct pci_dev *pdev, const struct pci_device_id *pci_id) { u16 cmd; - u8 card_rev; unsigned char pci_latency; IVTV_DEBUG_INFO("Enabling pci device\n"); @@ -857,7 +856,6 @@ static int ivtv_setup_pci(struct ivtv *itv, struct pci_dev *pdev, } IVTV_DEBUG_INFO("Bus Mastering Enabled.\n"); - pci_read_config_byte(pdev, PCI_CLASS_REVISION, &card_rev); pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency); if (pci_latency < 64 && ivtv_pci_latency) { @@ -874,7 +872,7 @@ static int ivtv_setup_pci(struct ivtv *itv, struct pci_dev *pdev, IVTV_DEBUG_INFO("%d (rev %d) at %02x:%02x.%x, " "irq: %d, latency: %d, memory: 0x%lx\n", - pdev->device, card_rev, pdev->bus->number, + pdev->device, pdev->revision, pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), pdev->irq, pci_latency, (unsigned long)itv->base_addr); diff --git a/drivers/media/video/saa7134/saa7134-core.c b/drivers/media/video/saa7134/saa7134-core.c index 41f836fc93ec..f9be737ba6f4 100644 --- a/drivers/media/video/saa7134/saa7134-core.c +++ b/drivers/media/video/saa7134/saa7134-core.c @@ -927,7 +927,7 @@ static int __devinit saa7134_initdev(struct pci_dev *pci_dev, } /* print pci info */ - pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); + dev->pci_rev = pci_dev->revision; pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); printk(KERN_INFO "%s: found at %s, rev: %d, irq: %d, " "latency: %d, mmio: 0x%llx\n", dev->name, diff --git a/drivers/media/video/saa7164/saa7164-core.c b/drivers/media/video/saa7164/saa7164-core.c index b813aec1e456..3b7d7b4e3034 100644 --- a/drivers/media/video/saa7164/saa7164-core.c +++ b/drivers/media/video/saa7164/saa7164-core.c @@ -1247,7 +1247,7 @@ static int __devinit saa7164_initdev(struct pci_dev *pci_dev, } /* print pci info */ - pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev); + dev->pci_rev = pci_dev->revision; pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, " "latency: %d, mmio: 0x%llx\n", dev->name, diff --git a/drivers/media/video/zoran/zoran_card.c b/drivers/media/video/zoran/zoran_card.c index 9f2bac519647..ba6878b2d663 100644 --- a/drivers/media/video/zoran/zoran_card.c +++ b/drivers/media/video/zoran/zoran_card.c @@ -1230,7 +1230,7 @@ static int __devinit zoran_probe(struct pci_dev *pdev, mutex_init(&zr->other_lock); if (pci_enable_device(pdev)) goto zr_unreg; - pci_read_config_byte(zr->pci_dev, PCI_CLASS_REVISION, &zr->revision); + zr->revision = zr->pci_dev->revision; dprintk(1, KERN_INFO -- cgit v1.2.3 From 0618ece01fdedcd3e775d9d43acc2c2a661a0c54 Mon Sep 17 00:00:00 2001 From: Bjørn Mork <bjorn@mork.no> Date: Tue, 22 Mar 2011 10:22:17 -0300 Subject: [media] mantis: trivial module parameter documentation fix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The default for "verbose" is 0. Update description to match. Signed-off-by: Bjørn Mork <bjorn@mork.no> Acked-by: Manu Abraham <manu@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/mantis/hopper_cards.c | 2 +- drivers/media/dvb/mantis/mantis_cards.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/mantis/hopper_cards.c b/drivers/media/dvb/mantis/hopper_cards.c index 70e73afefb3d..1402062f2c89 100644 --- a/drivers/media/dvb/mantis/hopper_cards.c +++ b/drivers/media/dvb/mantis/hopper_cards.c @@ -44,7 +44,7 @@ static unsigned int verbose; module_param(verbose, int, 0644); -MODULE_PARM_DESC(verbose, "verbose startup messages, default is 1 (yes)"); +MODULE_PARM_DESC(verbose, "verbose startup messages, default is 0 (no)"); #define DRIVER_NAME "Hopper" diff --git a/drivers/media/dvb/mantis/mantis_cards.c b/drivers/media/dvb/mantis/mantis_cards.c index 40da225098cc..05cbb9d95727 100644 --- a/drivers/media/dvb/mantis/mantis_cards.c +++ b/drivers/media/dvb/mantis/mantis_cards.c @@ -52,7 +52,7 @@ static unsigned int verbose; module_param(verbose, int, 0644); -MODULE_PARM_DESC(verbose, "verbose startup messages, default is 1 (yes)"); +MODULE_PARM_DESC(verbose, "verbose startup messages, default is 0 (no)"); static int devs; -- cgit v1.2.3 From 126f1e61887085aa2c2cfa7644aee8295a94e1f7 Mon Sep 17 00:00:00 2001 From: Ralph Metzler <rjkm@metzlerbros.de> Date: Sat, 12 Mar 2011 23:44:33 -0500 Subject: drx: add initial drx-d driver These are the original drx-d sources, extracted from Ralph Metzler's GPL'd ngene driver. No modifications/cleanup have yet been made. In fact, no measures have been taken to see if the code even compiles. Signed-off-by Ralph Metzler <rjkm@metzlerbros.de> Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd.h | 57 + drivers/media/dvb/frontends/drxd_firm.c | 943 ++ drivers/media/dvb/frontends/drxd_firm.h | 120 + drivers/media/dvb/frontends/drxd_hard.c | 2831 +++++ drivers/media/dvb/frontends/drxd_map_firm.h | 14484 ++++++++++++++++++++++++++ drivers/media/dvb/frontends/drxd_micro.h | 1498 +++ 6 files changed, 19933 insertions(+) create mode 100644 drivers/media/dvb/frontends/drxd.h create mode 100644 drivers/media/dvb/frontends/drxd_firm.c create mode 100644 drivers/media/dvb/frontends/drxd_firm.h create mode 100644 drivers/media/dvb/frontends/drxd_hard.c create mode 100644 drivers/media/dvb/frontends/drxd_map_firm.h create mode 100644 drivers/media/dvb/frontends/drxd_micro.h (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h new file mode 100644 index 000000000000..9b11dc835c44 --- /dev/null +++ b/drivers/media/dvb/frontends/drxd.h @@ -0,0 +1,57 @@ +/* + * drxd.h: DRXD DVB-T demodulator driver + * + * Copyright (C) 2005-2007 Micronas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _DRXD_H_ +#define _DRXD_H_ + +#include <linux/types.h> +#include <linux/i2c.h> + +struct drxd_config +{ + u8 index; + + u8 pll_address; + u8 pll_type; +#define DRXD_PLL_NONE 0 +#define DRXD_PLL_DTT7520X 1 +#define DRXD_PLL_MT3X0823 2 + + u32 clock; + + u8 demod_address; + u8 demoda_address; + u8 demod_revision; + + u32 IF; + int (*pll_set) (void *priv, void *priv_params, + u8 pll_addr, u8 demoda_addr, s32 *off); + s16 (*osc_deviation) (void *priv, s16 dev, int flag); +}; + +extern +struct dvb_frontend *drxd_attach(const struct drxd_config *config, + void *priv, struct i2c_adapter *i2c, + struct device *dev); +extern int drxd_config_i2c(struct dvb_frontend *, int); +#endif diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c new file mode 100644 index 000000000000..b27e928b94c1 --- /dev/null +++ b/drivers/media/dvb/frontends/drxd_firm.c @@ -0,0 +1,943 @@ +/* + * drxd_firm.c : DRXD firmware tables + * + * Copyright (C) 2006-2007 Micronas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +/* TODO: generate this file with a script from a settings file */ + +/* Contains A2 firmware version: 1.4.2 + * Contains B1 firmware version: 3.3.33 + * Contains settings from driver 1.4.23 +*/ + +#include "drxd_firm.h" + +#define ADDRESS(x) ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF) +#define LENGTH(x) ((x) & 0xFF), (((x)>>8) & 0xFF) + +/* Is written via block write, must be little endian */ +#define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF) + +#define WRBLOCK(a,l) ADDRESS(a),LENGTH(l) +#define WR16(a,d) ADDRESS(a),LENGTH(1),DATA16(d) + +#define END_OF_TABLE 0xFF,0xFF,0xFF,0xFF + +/* HI firmware patches */ + +#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A +#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */ + +u8_t DRXD_InitAtomicRead[] = +{ + WRBLOCK(HI_TR_FUNC_ADDR,HI_TR_FUNC_SIZE), + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x60, 0x04, /* r0rami.dt -> ring.xba; */ + 0x61, 0x04, /* r0rami.dt -> ring.xad; */ + 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */ + 0x40, 0x00, /* (long immediate) */ + 0x64, 0x04, /* r0rami.dt -> ring.len; */ + 0x65, 0x04, /* r0rami.dt -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x38, 0x00, /* 0 -> jumps.ad; */ + END_OF_TABLE +}; + +/* Pins D0 and D1 of the parallel MPEG output can be used + to set the I2C address of a device. */ + +#define HI_RST_FUNC_ADDR ( HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE) +#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */ + +/* D0 Version */ +u8_t DRXD_HiI2cPatch_1[] = +{ + WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE), + 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */ + 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x24, 0x00, /* 0 -> ring.len; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ + 0x63, 0x00, /* &data+1 -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0x0F, 0x04, /* r0ram.dt -> and.op; */ + 0x1C, 0x06, /* reg0.dt -> and.tr; */ + 0xCF, 0x04, /* and.rs -> add.op; */ + 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ + 0xD0, 0x04, /* add.rs -> add.tr; */ + 0xC8, 0x04, /* add.rs -> reg0.dt; */ + 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ + 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ + + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + + /* Force quick and dirty reset */ + WR16(B_HI_CT_REG_COMM_STATE__A,0), + END_OF_TABLE +}; + +/* D0,D1 Version */ +u8_t DRXD_HiI2cPatch_3[] = +{ + WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE), + 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */ + 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x24, 0x00, /* 0 -> ring.len; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ + 0x63, 0x00, /* &data+1 -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0x0F, 0x04, /* r0ram.dt -> and.op; */ + 0x1C, 0x06, /* reg0.dt -> and.tr; */ + 0xCF, 0x04, /* and.rs -> add.op; */ + 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ + 0xD0, 0x04, /* add.rs -> add.tr; */ + 0xC8, 0x04, /* add.rs -> reg0.dt; */ + 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ + 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ + + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), + + /* Force quick and dirty reset */ + WR16(B_HI_CT_REG_COMM_STATE__A,0), + END_OF_TABLE +}; + +u8_t DRXD_ResetCEFR[] = +{ + WRBLOCK(CE_REG_FR_TREAL00__A, 57), + 0x52,0x00, /* CE_REG_FR_TREAL00__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG00__A */ + 0x52,0x00, /* CE_REG_FR_TREAL01__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG01__A */ + 0x52,0x00, /* CE_REG_FR_TREAL02__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG02__A */ + 0x52,0x00, /* CE_REG_FR_TREAL03__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG03__A */ + 0x52,0x00, /* CE_REG_FR_TREAL04__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG04__A */ + 0x52,0x00, /* CE_REG_FR_TREAL05__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG05__A */ + 0x52,0x00, /* CE_REG_FR_TREAL06__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG06__A */ + 0x52,0x00, /* CE_REG_FR_TREAL07__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG07__A */ + 0x52,0x00, /* CE_REG_FR_TREAL08__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG08__A */ + 0x52,0x00, /* CE_REG_FR_TREAL09__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG09__A */ + 0x52,0x00, /* CE_REG_FR_TREAL10__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG10__A */ + 0x52,0x00, /* CE_REG_FR_TREAL11__A */ + 0x00,0x00, /* CE_REG_FR_TIMAG11__A */ + + 0x52,0x00, /* CE_REG_FR_MID_TAP__A */ + + 0x0B,0x00, /* CE_REG_FR_SQS_G00__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G01__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G02__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G03__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G04__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G05__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G06__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G07__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G08__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G09__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G10__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G11__A */ + 0x0B,0x00, /* CE_REG_FR_SQS_G12__A */ + + 0xFF,0x01, /* CE_REG_FR_RIO_G00__A */ + 0x90,0x01, /* CE_REG_FR_RIO_G01__A */ + 0x0B,0x01, /* CE_REG_FR_RIO_G02__A */ + 0xC8,0x00, /* CE_REG_FR_RIO_G03__A */ + 0xA0,0x00, /* CE_REG_FR_RIO_G04__A */ + 0x85,0x00, /* CE_REG_FR_RIO_G05__A */ + 0x72,0x00, /* CE_REG_FR_RIO_G06__A */ + 0x64,0x00, /* CE_REG_FR_RIO_G07__A */ + 0x59,0x00, /* CE_REG_FR_RIO_G08__A */ + 0x50,0x00, /* CE_REG_FR_RIO_G09__A */ + 0x49,0x00, /* CE_REG_FR_RIO_G10__A */ + + 0x10,0x00, /* CE_REG_FR_MODE__A */ + 0x78,0x00, /* CE_REG_FR_SQS_TRH__A */ + 0x00,0x00, /* CE_REG_FR_RIO_GAIN__A */ + 0x00,0x02, /* CE_REG_FR_BYPASS__A */ + 0x0D,0x00, /* CE_REG_FR_PM_SET__A */ + 0x07,0x00, /* CE_REG_FR_ERR_SH__A */ + 0x04,0x00, /* CE_REG_FR_MAN_SH__A */ + 0x06,0x00, /* CE_REG_FR_TAP_SH__A */ + + END_OF_TABLE +}; + + +u8_t DRXD_InitFEA2_1[] = +{ + WRBLOCK(FE_AD_REG_PD__A , 3), + 0x00,0x00, /* FE_AD_REG_PD__A */ + 0x01,0x00, /* FE_AD_REG_INVEXT__A */ + 0x00,0x00, /* FE_AD_REG_CLKNEG__A */ + + WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A , 2), + 0x10,0x00, /* FE_AG_REG_DCE_AUR_CNT__A */ + 0x10,0x00, /* FE_AG_REG_DCE_RUR_CNT__A */ + + WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A , 2), + 0x0E,0x00, /* FE_AG_REG_ACE_AUR_CNT__A */ + 0x00,0x00, /* FE_AG_REG_ACE_RUR_CNT__A */ + + WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A , 5), + 0x04,0x00, /* FE_AG_REG_EGC_FLA_RGN__A */ + 0x1F,0x00, /* FE_AG_REG_EGC_SLO_RGN__A */ + 0x00,0x00, /* FE_AG_REG_EGC_JMP_PSN__A */ + 0x00,0x00, /* FE_AG_REG_EGC_FLA_INC__A */ + 0x00,0x00, /* FE_AG_REG_EGC_FLA_DEC__A */ + + WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A , 2), + 0xFF,0x01, /* FE_AG_REG_GC1_AGC_MAX__A */ + 0x00,0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */ + + WRBLOCK(FE_AG_REG_IND_WIN__A , 29), + 0x00,0x00, /* FE_AG_REG_IND_WIN__A */ + 0x05,0x00, /* FE_AG_REG_IND_THD_LOL__A */ + 0x0F,0x00, /* FE_AG_REG_IND_THD_HIL__A */ + 0x00,0x00, /* FE_AG_REG_IND_DEL__A don't care */ + 0x1E,0x00, /* FE_AG_REG_IND_PD1_WRI__A */ + 0x0C,0x00, /* FE_AG_REG_PDA_AUR_CNT__A */ + 0x00,0x00, /* FE_AG_REG_PDA_RUR_CNT__A */ + 0x00,0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */ + 0x00,0x00, /* FE_AG_REG_PDC_RUR_CNT__A */ + 0x01,0x00, /* FE_AG_REG_PDC_SET_LVL__A */ + 0x02,0x00, /* FE_AG_REG_PDC_FLA_RGN__A */ + 0x00,0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */ + 0xFF,0xFF, /* FE_AG_REG_PDC_FLA_STP__A */ + 0xFF,0xFF, /* FE_AG_REG_PDC_SLO_STP__A */ + 0x00,0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */ + 0x00,0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */ + 0x02,0x00, /* FE_AG_REG_PDC_MAX__A */ + 0x0C,0x00, /* FE_AG_REG_TGA_AUR_CNT__A */ + 0x00,0x00, /* FE_AG_REG_TGA_RUR_CNT__A */ + 0x00,0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */ + 0x00,0x00, /* FE_AG_REG_TGC_RUR_CNT__A */ + 0x22,0x00, /* FE_AG_REG_TGC_SET_LVL__A */ + 0x15,0x00, /* FE_AG_REG_TGC_FLA_RGN__A */ + 0x00,0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */ + 0x01,0x00, /* FE_AG_REG_TGC_FLA_STP__A */ + 0x0A,0x00, /* FE_AG_REG_TGC_SLO_STP__A */ + 0x00,0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */ + 0x10,0x00, /* FE_AG_REG_FGA_AUR_CNT__A */ + 0x10,0x00, /* FE_AG_REG_FGA_RUR_CNT__A */ + + WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A , 2), + 0x00,0x00, /* FE_AG_REG_BGC_FGC_WRI__A */ + 0x00,0x00, /* FE_AG_REG_BGC_CGC_WRI__A */ + + WRBLOCK(FE_FD_REG_SCL__A , 3), + 0x05,0x00, /* FE_FD_REG_SCL__A */ + 0x03,0x00, /* FE_FD_REG_MAX_LEV__A */ + 0x05,0x00, /* FE_FD_REG_NR__A */ + + WRBLOCK(FE_CF_REG_SCL__A , 5), + 0x16,0x00, /* FE_CF_REG_SCL__A */ + 0x04,0x00, /* FE_CF_REG_MAX_LEV__A */ + 0x06,0x00, /* FE_CF_REG_NR__A */ + 0x00,0x00, /* FE_CF_REG_IMP_VAL__A */ + 0x01,0x00, /* FE_CF_REG_MEAS_VAL__A */ + + WRBLOCK(FE_CU_REG_FRM_CNT_RST__A , 2), + 0x00,0x08, /* FE_CU_REG_FRM_CNT_RST__A */ + 0x00,0x00, /* FE_CU_REG_FRM_CNT_STR__A */ + + END_OF_TABLE +}; + + /* with PGA */ +/* WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0004), */ + /* without PGA */ +/* WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0001), */ +/* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/ +/* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ + +u8_t DRXD_InitFEA2_2[] = +{ + WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010), + WR16(FE_AG_REG_FGM_WRI__A , 48), + /* Activate measurement, activate scale */ + WR16(FE_FD_REG_MEAS_VAL__A , 0x0001), + + WR16(FE_CU_REG_COMM_EXEC__A, 0x0001), + WR16(FE_CF_REG_COMM_EXEC__A, 0x0001), + WR16(FE_IF_REG_COMM_EXEC__A, 0x0001), + WR16(FE_FD_REG_COMM_EXEC__A, 0x0001), + WR16(FE_FS_REG_COMM_EXEC__A, 0x0001), + WR16(FE_AD_REG_COMM_EXEC__A , 0x0001), + WR16(FE_AG_REG_COMM_EXEC__A , 0x0001), + WR16(FE_AG_REG_AG_MODE_LOP__A , 0x895E), + + END_OF_TABLE +}; + +u8_t DRXD_InitFEB1_1[] = +{ + WR16(B_FE_AD_REG_PD__A ,0x0000 ), + WR16(B_FE_AD_REG_CLKNEG__A ,0x0000 ), + WR16(B_FE_AG_REG_BGC_FGC_WRI__A ,0x0000 ), + WR16(B_FE_AG_REG_BGC_CGC_WRI__A ,0x0000 ), + WR16(B_FE_AG_REG_AG_MODE_LOP__A ,0x000a ), + WR16(B_FE_AG_REG_IND_PD1_WRI__A ,35 ), + WR16(B_FE_AG_REG_IND_WIN__A ,0 ), + WR16(B_FE_AG_REG_IND_THD_LOL__A ,8 ), + WR16(B_FE_AG_REG_IND_THD_HIL__A ,8 ), + WR16(B_FE_CF_REG_IMP_VAL__A ,1 ), + WR16(B_FE_AG_REG_EGC_FLA_RGN__A ,7 ), + END_OF_TABLE +}; + /* with PGA */ +/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */ + /* without PGA */ +/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , + B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/ +/* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005*/ +/* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ + +u8_t DRXD_InitFEB1_2[] = +{ + WR16(B_FE_COMM_EXEC__A ,0x0001 ), + + /* RF-AGC setup */ + WR16(B_FE_AG_REG_PDA_AUR_CNT__A , 0x0C ), + WR16(B_FE_AG_REG_PDC_SET_LVL__A , 0x01 ), + WR16(B_FE_AG_REG_PDC_FLA_RGN__A , 0x02 ), + WR16(B_FE_AG_REG_PDC_FLA_STP__A , 0xFFFF ), + WR16(B_FE_AG_REG_PDC_SLO_STP__A , 0xFFFF ), + WR16(B_FE_AG_REG_PDC_MAX__A , 0x02 ), + WR16(B_FE_AG_REG_TGA_AUR_CNT__A , 0x0C ), + WR16(B_FE_AG_REG_TGC_SET_LVL__A , 0x22 ), + WR16(B_FE_AG_REG_TGC_FLA_RGN__A , 0x15 ), + WR16(B_FE_AG_REG_TGC_FLA_STP__A , 0x01 ), + WR16(B_FE_AG_REG_TGC_SLO_STP__A , 0x0A ), + + WR16(B_FE_CU_REG_DIV_NFC_CLP__A , 0 ), + WR16(B_FE_CU_REG_CTR_NFC_OCR__A , 25000 ), + WR16(B_FE_CU_REG_CTR_NFC_ICR__A , 1 ), + END_OF_TABLE +}; + +u8_t DRXD_InitCPA2[] = +{ + WRBLOCK(CP_REG_BR_SPL_OFFSET__A , 2), + 0x07,0x00, /* CP_REG_BR_SPL_OFFSET__A */ + 0x0A,0x00, /* CP_REG_BR_STR_DEL__A */ + + WRBLOCK(CP_REG_RT_ANG_INC0__A , 4), + 0x00,0x00, /* CP_REG_RT_ANG_INC0__A */ + 0x00,0x00, /* CP_REG_RT_ANG_INC1__A */ + 0x03,0x00, /* CP_REG_RT_DETECT_ENA__A */ + 0x03,0x00, /* CP_REG_RT_DETECT_TRH__A */ + + WRBLOCK(CP_REG_AC_NEXP_OFFS__A , 5), + 0x32,0x00, /* CP_REG_AC_NEXP_OFFS__A */ + 0x62,0x00, /* CP_REG_AC_AVER_POW__A */ + 0x82,0x00, /* CP_REG_AC_MAX_POW__A */ + 0x26,0x00, /* CP_REG_AC_WEIGHT_MAN__A */ + 0x0F,0x00, /* CP_REG_AC_WEIGHT_EXP__A */ + + WRBLOCK(CP_REG_AC_AMP_MODE__A ,2), + 0x02,0x00, /* CP_REG_AC_AMP_MODE__A */ + 0x01,0x00, /* CP_REG_AC_AMP_FIX__A */ + + WR16(CP_REG_INTERVAL__A , 0x0005 ), + WR16(CP_REG_RT_EXP_MARG__A , 0x0004 ), + WR16(CP_REG_AC_ANG_MODE__A , 0x0003 ), + + WR16(CP_REG_COMM_EXEC__A , 0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_InitCPB1[] = +{ + WR16(B_CP_REG_BR_SPL_OFFSET__A ,0x0008 ), + WR16(B_CP_COMM_EXEC__A ,0x0001 ), + END_OF_TABLE +}; + + +u8_t DRXD_InitCEA2[] = +{ + WRBLOCK(CE_REG_AVG_POW__A , 4), + 0x62,0x00, /* CE_REG_AVG_POW__A */ + 0x78,0x00, /* CE_REG_MAX_POW__A */ + 0x62,0x00, /* CE_REG_ATT__A */ + 0x17,0x00, /* CE_REG_NRED__A */ + + WRBLOCK(CE_REG_NE_ERR_SELECT__A , 2), + 0x07,0x00, /* CE_REG_NE_ERR_SELECT__A */ + 0xEB,0xFF, /* CE_REG_NE_TD_CAL__A */ + + WRBLOCK(CE_REG_NE_MIXAVG__A , 2), + 0x06,0x00, /* CE_REG_NE_MIXAVG__A */ + 0x00,0x00, /* CE_REG_NE_NUPD_OFS__A */ + + WRBLOCK(CE_REG_PE_NEXP_OFFS__A , 2), + 0x00,0x00, /* CE_REG_PE_NEXP_OFFS__A */ + 0x00,0x00, /* CE_REG_PE_TIMESHIFT__A */ + + WRBLOCK(CE_REG_TP_A0_TAP_NEW__A , 3), + 0x00,0x01, /* CE_REG_TP_A0_TAP_NEW__A */ + 0x01,0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */ + 0x0E,0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */ + + WRBLOCK(CE_REG_TP_A1_TAP_NEW__A , 3), + 0x00,0x00, /* CE_REG_TP_A1_TAP_NEW__A */ + 0x01,0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */ + 0x0A,0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */ + + WRBLOCK(CE_REG_FI_SHT_INCR__A , 2), + 0x12,0x00, /* CE_REG_FI_SHT_INCR__A */ + 0x0C,0x00, /* CE_REG_FI_EXP_NORM__A */ + + WRBLOCK(CE_REG_IR_INPUTSEL__A , 3), + 0x00,0x00, /* CE_REG_IR_INPUTSEL__A */ + 0x00,0x00, /* CE_REG_IR_STARTPOS__A */ + 0xFF,0x00, /* CE_REG_IR_NEXP_THRES__A */ + + + WR16(CE_REG_TI_NEXP_OFFS__A ,0x0000), + + END_OF_TABLE +}; + +u8_t DRXD_InitCEB1[] = +{ + WR16(B_CE_REG_TI_PHN_ENABLE__A ,0x0001), + WR16(B_CE_REG_FR_PM_SET__A ,0x000D), + + END_OF_TABLE +}; + +u8_t DRXD_InitEQA2[] = +{ + WRBLOCK(EQ_REG_OT_QNT_THRES0__A , 4), + 0x1E,0x00, /* EQ_REG_OT_QNT_THRES0__A */ + 0x1F,0x00, /* EQ_REG_OT_QNT_THRES1__A */ + 0x06,0x00, /* EQ_REG_OT_CSI_STEP__A */ + 0x02,0x00, /* EQ_REG_OT_CSI_OFFSET__A */ + + WR16(EQ_REG_TD_REQ_SMB_CNT__A ,0x0200 ), + WR16(EQ_REG_IS_CLIP_EXP__A ,0x001F ), + WR16(EQ_REG_SN_OFFSET__A ,(u16_t)(-7) ), + WR16(EQ_REG_RC_SEL_CAR__A ,0x0002 ), + WR16(EQ_REG_COMM_EXEC__A ,0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_InitEQB1[] = +{ + WR16(B_EQ_REG_COMM_EXEC__A ,0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_ResetECRAM[] = +{ + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A , 0x0000 ), + WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), + END_OF_TABLE +}; + +u8_t DRXD_InitECA2[] = +{ + WRBLOCK( EC_SB_REG_CSI_HI__A , 6), + 0x1F,0x00, /* EC_SB_REG_CSI_HI__A */ + 0x1E,0x00, /* EC_SB_REG_CSI_LO__A */ + 0x01,0x00, /* EC_SB_REG_SMB_TGL__A */ + 0x7F,0x00, /* EC_SB_REG_SNR_HI__A */ + 0x7F,0x00, /* EC_SB_REG_SNR_MID__A */ + 0x7F,0x00, /* EC_SB_REG_SNR_LO__A */ + + WRBLOCK( EC_RS_REG_REQ_PCK_CNT__A , 2), + 0x00,0x10, /* EC_RS_REG_REQ_PCK_CNT__A */ + DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */ + + WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5), + 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ + 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ + 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ + 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ + 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ + + WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2), + 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ + 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ + + WRBLOCK( EC_OC_REG_RCN_MODE__A , 7), + 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */ + 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ + 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ + 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */ + 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */ + 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */ + 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ + + WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2), + 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ + 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ + + WR16(EC_SB_REG_CSI_OFS__A , 0x0001 ), + WR16(EC_VD_REG_FORCE__A , 0x0002 ), + WR16(EC_VD_REG_REQ_SMB_CNT__A , 0x0001 ), + WR16(EC_VD_REG_RLK_ENA__A , 0x0001 ), + WR16(EC_OD_REG_SYNC__A , 0x0664 ), + WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ), + WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ), + /* Output zero on monitorbus pads, power saving */ + WR16(EC_OC_REG_OCR_MON_UOS__A , + ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | + EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | + EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ), + WR16(EC_OC_REG_OCR_MON_WRI__A, + EC_OC_REG_OCR_MON_WRI_INIT ), + +/* CHK_ERROR(ResetECRAM(demod)); */ + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A , 0x0000 ), + WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), + + WR16(EC_SB_REG_COMM_EXEC__A , 0x0001 ), + WR16(EC_VD_REG_COMM_EXEC__A , 0x0001 ), + WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ), + WR16(EC_RS_REG_COMM_EXEC__A , 0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_InitECB1[] = +{ + WR16(B_EC_SB_REG_CSI_OFS0__A ,0x0001 ), + WR16(B_EC_SB_REG_CSI_OFS1__A ,0x0001 ), + WR16(B_EC_SB_REG_CSI_OFS2__A ,0x0001 ), + WR16(B_EC_SB_REG_CSI_LO__A ,0x000c ), + WR16(B_EC_SB_REG_CSI_HI__A ,0x0018 ), + WR16(B_EC_SB_REG_SNR_HI__A ,0x007f ), + WR16(B_EC_SB_REG_SNR_MID__A ,0x007f ), + WR16(B_EC_SB_REG_SNR_LO__A ,0x007f ), + + WR16(B_EC_OC_REG_DTO_CLKMODE__A ,0x0002 ), + WR16(B_EC_OC_REG_DTO_PER__A ,0x0006 ), + WR16(B_EC_OC_REG_DTO_BUR__A ,0x0001 ), + WR16(B_EC_OC_REG_RCR_CLKMODE__A ,0x0000 ), + WR16(B_EC_OC_REG_RCN_GAI_LVL__A ,0x000D ), + WR16(B_EC_OC_REG_OC_MPG_SIO__A ,0x0000 ), + + /* Needed because shadow registers do not have correct default value */ + WR16(B_EC_OC_REG_RCN_CST_LOP__A ,0x1000 ), + WR16(B_EC_OC_REG_RCN_CST_HIP__A ,0x0000 ), + WR16(B_EC_OC_REG_RCN_CRA_LOP__A ,0x0000 ), + WR16(B_EC_OC_REG_RCN_CRA_HIP__A ,0x00C0 ), + WR16(B_EC_OC_REG_RCN_CLP_LOP__A ,0x0000 ), + WR16(B_EC_OC_REG_RCN_CLP_HIP__A ,0x00C0 ), + WR16(B_EC_OC_REG_DTO_INC_LOP__A ,0x0000 ), + WR16(B_EC_OC_REG_DTO_INC_HIP__A ,0x00C0 ), + + WR16(B_EC_OD_REG_SYNC__A ,0x0664 ), + WR16(B_EC_RS_REG_REQ_PCK_CNT__A ,0x1000 ), + +/* CHK_ERROR(ResetECRAM(demod)); */ + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A , 0x0000 ), + WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), + + WR16(B_EC_SB_REG_COMM_EXEC__A , 0x0001 ), + WR16(B_EC_VD_REG_COMM_EXEC__A , 0x0001 ), + WR16(B_EC_OD_REG_COMM_EXEC__A , 0x0001 ), + WR16(B_EC_RS_REG_COMM_EXEC__A , 0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_ResetECA2[] = +{ + + WR16(EC_OC_REG_COMM_EXEC__A , 0x0000 ), + WR16(EC_OD_REG_COMM_EXEC__A , 0x0000 ), + + WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5), + 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ + 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ + 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ + 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ + 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ + + WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2), + 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ + 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ + + WRBLOCK( EC_OC_REG_RCN_MODE__A , 7), + 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */ + 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ + 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ + 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */ + 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */ + 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */ + 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ + + WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2), + 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ + 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ + + WR16(EC_OD_REG_SYNC__A , 0x0664 ), + WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ), + WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ), + /* Output zero on monitorbus pads, power saving */ + WR16(EC_OC_REG_OCR_MON_UOS__A , + ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | + EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | + EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ), + WR16(EC_OC_REG_OCR_MON_WRI__A, + EC_OC_REG_OCR_MON_WRI_INIT ), + +/* CHK_ERROR(ResetECRAM(demod)); */ + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A , 0x0000 ), + WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), + + WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_InitSC[] = +{ + WR16(SC_COMM_EXEC__A, 0 ), + WR16(SC_COMM_STATE__A, 0 ), + +#ifdef COMPILE_FOR_QT + WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100 ), +#endif + + /* SC is not started, this is done in SetChannels() */ + END_OF_TABLE +}; + +/* Diversity settings */ + +u8_t DRXD_InitDiversityFront[] = +{ + /* Start demod ********* RF in , diversity out *****************************/ + WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | + B_SC_RA_RAM_CONFIG_FREQSCAN__M ), + + WR16( B_SC_RA_RAM_LC_ABS_2K__A, 0x7), + WR16( B_SC_RA_RAM_LC_ABS_8K__A, 0x7), + WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ), + WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ), + WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ), + WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ), + + WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ), + WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ), + WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ), + WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ), + + WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7), + WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4), + WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7), + WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4), + WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500), + + WR16( B_CC_REG_DIVERSITY__A, 0x0001 ), + WR16( B_EC_OC_REG_OC_MODE_HIP__A, 0x0010 ), + WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | + B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | + B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ), + + + /* 0x2a ),*/ /* CE to PASS mux */ + + END_OF_TABLE +}; + +u8_t DRXD_InitDiversityEnd[] = +{ + /* End demod *********** combining RF in and diversity in, MPEG TS out *****/ + /* disable near/far; switch on timing slave mode */ + WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | + B_SC_RA_RAM_CONFIG_FREQSCAN__M | + B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M | + B_SC_RA_RAM_CONFIG_SLAVE__M | + B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M +/* MV from CtrlDiversity */ + ), +#ifdef DRXDDIV_SRMM_SLAVING + WR16( SC_RA_RAM_LC_ABS_2K__A, 0x3c7), + WR16( SC_RA_RAM_LC_ABS_8K__A, 0x3c7), +#else + WR16( SC_RA_RAM_LC_ABS_2K__A, 0x7), + WR16( SC_RA_RAM_LC_ABS_8K__A, 0x7), +#endif + + WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ), + WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ), + WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ), + WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ), + + WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ), + WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ), + WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ), + WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ), + + WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7), + WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4), + WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7), + WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4), + WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500), + + WR16( B_CC_REG_DIVERSITY__A, 0x0001 ), + END_OF_TABLE +}; + +u8_t DRXD_DisableDiversity[] = +{ + WR16( B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE), + WR16( B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE), + WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE ), + WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE ), + + WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE ), + WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE ), + WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE ), + + WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE), + WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE), + WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE), + WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE), + WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE), + + + WR16( B_CC_REG_DIVERSITY__A, 0x0000 ), + WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT ), /* combining disabled*/ + + END_OF_TABLE +}; + +u8_t DRXD_StartDiversityFront[] = +{ + /* Start demod, RF in and diversity out, no combining */ + WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ), + WR16( B_FE_AD_REG_FDB_IN__A, 0x0 ), + WR16( B_FE_AD_REG_INVEXT__A, 0x0 ), + WR16( B_EQ_REG_COMM_MB__A, 0x12 ), /* EQ to MB out */ + WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */ + B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | + B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ), + + WR16( SC_RA_RAM_ECHO_SHIFT_LIM__A, 2 ), + + END_OF_TABLE +}; + +u8_t DRXD_StartDiversityEnd[] = +{ + /* End demod, combining RF in and diversity in, MPEG TS out */ + WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ), /* disable impulse noise cruncher */ + WR16( B_FE_AD_REG_INVEXT__A, 0x0 ), /* clock inversion (for sohard board) */ + WR16( B_CP_REG_BR_STR_DEL__A, 10 ), /* apperently no mb delay matching is best */ + + WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */ + B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | + B_EQ_REG_RC_SEL_CAR_PASS_A_CC | + B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC ), + + END_OF_TABLE +}; + +u8_t DRXD_DiversityDelay8MHZ[] = +{ + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 1000 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 800 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4800 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 4000 - 50 ), + END_OF_TABLE +}; + +u8_t DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */ +{ + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 900 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 600 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4500 - 50 ), + WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 3500 - 50 ), + END_OF_TABLE +}; + +#include "drxd_micro.h" diff --git a/drivers/media/dvb/frontends/drxd_firm.h b/drivers/media/dvb/frontends/drxd_firm.h new file mode 100644 index 000000000000..fa704cbf7664 --- /dev/null +++ b/drivers/media/dvb/frontends/drxd_firm.h @@ -0,0 +1,120 @@ +/* + * drxd_firm.h + * + * Copyright (C) 2006-2007 Micronas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _DRXD_FIRM_H_ +#define _DRXD_FIRM_H_ + +#include "drxd_map_firm.h" + +typedef unsigned char u8_t; +typedef unsigned short u16_t; +typedef unsigned long u32_t; + +#define VERSION_MAJOR 1 +#define VERSION_MINOR 4 +#define VERSION_PATCH 23 + +#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A + +#define DRXD_MAX_RETRIES (1000) +#define HI_I2C_DELAY 84 +#define HI_I2C_BRIDGE_DELAY 750 + +#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */ +#define EQ_TD_TPS_PWR_QPSK 0x016a +#define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195 +#define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195 +#define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E +#define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE +#define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F +#define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F +#define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8 +#define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D + +#define DRXD_DEF_AG_PWD_CONSUMER 0x000E +#define DRXD_DEF_AG_PWD_PRO 0x0000 +#define DRXD_DEF_AG_AGC_SIO 0x0000 + +#define DRXD_FE_CTRL_MAX 1023 + +#define DRXD_OSCDEV_DO_SCAN (16) + +#define DRXD_OSCDEV_DONT_SCAN (0) + +#define DRXD_OSCDEV_STEP (275) + +#define DRXD_SCAN_TIMEOUT (650) + + +#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) +#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) +#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) + +#define IRLEN_COARSE_8K (10) +#define IRLEN_FINE_8K (10) +#define IRLEN_COARSE_2K (7) +#define IRLEN_FINE_2K (9) +#define DIFF_INVALID (511) +#define DIFF_TARGET (4) +#define DIFF_MARGIN (1) + + +extern u8_t DRXD_InitAtomicRead[]; +extern u8_t DRXD_HiI2cPatch_1[]; +extern u8_t DRXD_HiI2cPatch_3[]; + +extern u8_t DRXD_InitSC[]; + +extern u8_t DRXD_ResetCEFR[]; +extern u8_t DRXD_InitFEA2_1[]; +extern u8_t DRXD_InitFEA2_2[]; +extern u8_t DRXD_InitCPA2[]; +extern u8_t DRXD_InitCEA2[]; +extern u8_t DRXD_InitEQA2[]; +extern u8_t DRXD_InitECA2[]; +extern u8_t DRXD_ResetECA2[]; +extern u8_t DRXD_ResetECRAM[]; + +extern u8_t DRXD_A2_microcode[]; +extern u32_t DRXD_A2_microcode_length; + +extern u8_t DRXD_InitFEB1_1[]; +extern u8_t DRXD_InitFEB1_2[]; +extern u8_t DRXD_InitCPB1[]; +extern u8_t DRXD_InitCEB1[]; +extern u8_t DRXD_InitEQB1[]; +extern u8_t DRXD_InitECB1[]; + +extern u8_t DRXD_InitDiversityFront[]; +extern u8_t DRXD_InitDiversityEnd[]; +extern u8_t DRXD_DisableDiversity[]; +extern u8_t DRXD_StartDiversityFront[]; +extern u8_t DRXD_StartDiversityEnd[]; + +extern u8_t DRXD_DiversityDelay8MHZ[]; +extern u8_t DRXD_DiversityDelay6MHZ[]; + +extern u8_t DRXD_B1_microcode[]; +extern u32_t DRXD_B1_microcode_length; + +#endif diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c new file mode 100644 index 000000000000..c4835b32e6d9 --- /dev/null +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -0,0 +1,2831 @@ +/* + * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1 + * + * Copyright (C) 2003-2007 Micronas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/firmware.h> +#include <linux/i2c.h> +#include <linux/version.h> +#include <asm/div64.h> + +#include "dvb_frontend.h" +#include "drxd.h" +#include "drxd_firm.h" + +#define CHK_ERROR(s) if( (status = s)<0 ) break +#define CHUNK_SIZE 48 + +#define DRX_I2C_RMW 0x10 +#define DRX_I2C_BROADCAST 0x20 +#define DRX_I2C_CLEARCRC 0x80 +#define DRX_I2C_SINGLE_MASTER 0xC0 +#define DRX_I2C_MODEFLAGS 0xC0 +#define DRX_I2C_FLAGS 0xF0 + +#ifndef SIZEOF_ARRAY +#define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0])) +#endif + +#define DEFAULT_LOCK_TIMEOUT 1100 + +#define DRX_CHANNEL_AUTO 0 +#define DRX_CHANNEL_HIGH 1 +#define DRX_CHANNEL_LOW 2 + +#define DRX_LOCK_MPEG 1 +#define DRX_LOCK_FEC 2 +#define DRX_LOCK_DEMOD 4 + + +/****************************************************************************/ + +enum CSCDState { + CSCD_INIT = 0, + CSCD_SET, + CSCD_SAVED +}; + +enum CDrxdState { + DRXD_UNINITIALIZED = 0, + DRXD_STOPPED, + DRXD_STARTED +}; + +enum AGC_CTRL_MODE { + AGC_CTRL_AUTO = 0, + AGC_CTRL_USER, + AGC_CTRL_OFF +}; + +enum OperationMode { + OM_Default, + OM_DVBT_Diversity_Front, + OM_DVBT_Diversity_End +}; + +struct SCfgAgc { + enum AGC_CTRL_MODE ctrlMode; + u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ + u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */ + u16 minOutputLevel;/* range [0, ... , 1023], 1/n of fullscale range */ + u16 maxOutputLevel;/* range [0, ... , 1023], 1/n of fullscale range */ + u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */ + + u16 R1; + u16 R2; + u16 R3; +}; + +struct SNoiseCal { + int cpOpt; + u16 cpNexpOfs; + u16 tdCal2k; + u16 tdCal8k; +}; + +enum app_env { + APPENV_STATIC = 0, + APPENV_PORTABLE = 1, + APPENV_MOBILE = 2 +}; + +enum EIFFilter { + IFFILTER_SAW = 0, + IFFILTER_DISCRETE = 1 +}; + +struct drxd_state { + struct dvb_frontend frontend; + struct dvb_frontend_ops ops; + struct dvb_frontend_parameters param; + + const struct firmware *fw; + struct device *dev; + + struct i2c_adapter *i2c; + void *priv; + struct drxd_config config; + + int i2c_access; + int init_done; + struct semaphore mutex; + + u8 chip_adr; + u16 hi_cfg_timing_div; + u16 hi_cfg_bridge_delay; + u16 hi_cfg_wakeup_key; + u16 hi_cfg_ctrl; + + u16 intermediate_freq; + u16 osc_clock_freq; + + enum CSCDState cscd_state; + enum CDrxdState drxd_state; + + u16 sys_clock_freq; + s16 osc_clock_deviation; + u16 expected_sys_clock_freq; + + u16 insert_rs_byte; + u16 enable_parallel; + + int operation_mode; + + struct SCfgAgc if_agc_cfg; + struct SCfgAgc rf_agc_cfg; + + struct SNoiseCal noise_cal; + + u32 fe_fs_add_incr; + u32 org_fe_fs_add_incr; + u16 current_fe_if_incr; + + u16 m_FeAgRegAgPwd; + u16 m_FeAgRegAgAgcSio; + + u16 m_EcOcRegOcModeLop; + u16 m_EcOcRegSncSncLvl; + u8 *m_InitAtomicRead; + u8 *m_HiI2cPatch; + + u8 *m_ResetCEFR; + u8 *m_InitFE_1; + u8 *m_InitFE_2; + u8 *m_InitCP; + u8 *m_InitCE; + u8 *m_InitEQ; + u8 *m_InitSC; + u8 *m_InitEC; + u8 *m_ResetECRAM; + u8 *m_InitDiversityFront; + u8 *m_InitDiversityEnd; + u8 *m_DisableDiversity; + u8 *m_StartDiversityFront; + u8 *m_StartDiversityEnd; + + u8 *m_DiversityDelay8MHZ; + u8 *m_DiversityDelay6MHZ; + + u8 *microcode; + u32 microcode_length; + + int type_A; + int PGA; + int diversity; + int tuner_mirrors; + + enum app_env app_env_default; + enum app_env app_env_diversity; + +}; + + +/****************************************************************************/ +/* I2C **********************************************************************/ +/****************************************************************************/ + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = { .addr=adr, .flags=0, .buf=data, .len=len }; + + if (i2c_transfer(adap, &msg, 1) != 1) + return -1; + return 0; +} + +static int i2c_read(struct i2c_adapter *adap, + u8 adr, u8 *msg, int len, u8 *answ, int alen) +{ + struct i2c_msg msgs[2] = { { .addr=adr, .flags=0, + .buf=msg, .len=len }, + { .addr=adr, .flags=I2C_M_RD, + .buf=answ, .len=alen } }; + if (i2c_transfer(adap, msgs, 2) != 2) + return -1; + return 0; +} + +inline u32 MulDiv32(u32 a, u32 b, u32 c) +{ + u64 tmp64; + + tmp64=(u64)a*(u64)b; + do_div(tmp64, c); + + return (u32) tmp64; +} + +static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) +{ + u8 adr=state->config.demod_address; + u8 mm1[4]={reg&0xff, (reg>>16)&0xff, + flags|((reg>>24)&0xff), (reg>>8)&0xff}; + u8 mm2[2]; + if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2)<0) + return -1; + if (data) + *data=mm2[0]|(mm2[1]<<8); + return mm2[0]|(mm2[1]<<8); +} + +static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) +{ + u8 adr=state->config.demod_address; + u8 mm1[4]={reg&0xff, (reg>>16)&0xff, + flags|((reg>>24)&0xff), (reg>>8)&0xff}; + u8 mm2[4]; + + if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4)<0) + return -1; + if (data) + *data=mm2[0]|(mm2[1]<<8)|(mm2[2]<<16)|(mm2[3]<<24); + return 0; +} + +static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) +{ + u8 adr=state->config.demod_address; + u8 mm[6]={ reg&0xff, (reg>>16)&0xff, + flags|((reg>>24)&0xff), (reg>>8)&0xff, + data&0xff, (data>>8)&0xff }; + + if (i2c_write(state->i2c, adr, mm, 6)<0) + return -1; + return 0; +} + +static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) +{ + u8 adr=state->config.demod_address; + u8 mm[8]={ reg&0xff, (reg>>16)&0xff, + flags|((reg>>24)&0xff), (reg>>8)&0xff, + data&0xff, (data>>8)&0xff, + (data>>16)&0xff, (data>>24)&0xff }; + + if (i2c_write(state->i2c, adr, mm, 8)<0) + return -1; + return 0; +} + +static int write_chunk(struct drxd_state *state, + u32 reg, u8 *data, u32 len, u8 flags) +{ + u8 adr=state->config.demod_address; + u8 mm[CHUNK_SIZE+4]={ reg&0xff, (reg>>16)&0xff, + flags|((reg>>24)&0xff), (reg>>8)&0xff }; + int i; + + for (i=0; i<len; i++) + mm[4+i]=data[i]; + if (i2c_write(state->i2c, adr, mm, 4+len)<0) { + printk("error in write_chunk\n"); + return -1; + } + return 0; +} + +static int WriteBlock(struct drxd_state *state, + u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags) +{ + while(BlockSize > 0) { + u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize; + + if (write_chunk(state, Address, pBlock, Chunk, Flags)<0) + return -1; + pBlock += Chunk; + Address += (Chunk >> 1); + BlockSize -= Chunk; + } + return 0; +} + +static int WriteTable(struct drxd_state *state, u8 *pTable) +{ + int status = 0; + + if( pTable == NULL ) + return 0; + + while(!status) { + u16 Length; + u32 Address = pTable[0]|(pTable[1]<<8)| + (pTable[2]<<16)|(pTable[3]<<24); + + if (Address==0xFFFFFFFF) + break; + pTable += sizeof(u32); + + Length = pTable[0]|(pTable[1]<<8); + pTable += sizeof(u16); + if (!Length) + break; + status = WriteBlock(state, Address, Length*2, pTable, 0); + pTable += (Length*2); + } + return status; +} + + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +static int ResetCEFR(struct drxd_state *state) +{ + return WriteTable(state, state->m_ResetCEFR); +} + +static int InitCP(struct drxd_state *state) +{ + return WriteTable(state, state->m_InitCP); +} + +static int InitCE(struct drxd_state *state) +{ + int status; + enum app_env AppEnv = state->app_env_default; + + do { + CHK_ERROR(WriteTable(state, state->m_InitCE)); + + if (state->operation_mode == OM_DVBT_Diversity_Front || + state->operation_mode == OM_DVBT_Diversity_End ) { + AppEnv = state->app_env_diversity; + } + if ( AppEnv == APPENV_STATIC ) { + CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0000,0)); + } else if( AppEnv == APPENV_PORTABLE ) { + CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0001,0)); + } else if( AppEnv == APPENV_MOBILE && state->type_A ) { + CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0002,0)); + } else if( AppEnv == APPENV_MOBILE && !state->type_A ) { + CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0006,0)); + } + + /* start ce */ + CHK_ERROR(Write16(state,B_CE_REG_COMM_EXEC__A,0x0001,0)); + } while(0); + return status; +} + +static int StopOC(struct drxd_state *state) +{ + int status = 0; + u16 ocSyncLvl = 0; + u16 ocModeLop = state->m_EcOcRegOcModeLop; + u16 dtoIncLop = 0; + u16 dtoIncHip = 0; + + do { + /* Store output configuration */ + CHK_ERROR(Read16(state, EC_OC_REG_SNC_ISC_LVL__A, + &ocSyncLvl, 0));; + /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, + &ocModeLop)); */ + state->m_EcOcRegSncSncLvl = ocSyncLvl; + /* m_EcOcRegOcModeLop = ocModeLop; */ + + /* Flush FIFO (byte-boundary) at fixed rate */ + CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_LOP__A, + &dtoIncLop,0 )); + CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_HIP__A, + &dtoIncHip,0 )); + CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_LOP__A, + dtoIncLop,0 )); + CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_HIP__A, + dtoIncHip,0 )); + ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M); + ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC; + CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, + ocModeLop,0 )); + CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, + EC_OC_REG_COMM_EXEC_CTL_HOLD,0 )); + + msleep(1); + /* Output pins to '0' */ + CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A, + EC_OC_REG_OCR_MPG_UOS__M,0 )); + + /* Force the OC out of sync */ + ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M); + CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A, + ocSyncLvl,0 )); + ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M); + ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE; + ocModeLop |= 0x2; /* Magically-out-of-sync */ + CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, + ocModeLop,0 )); + CHK_ERROR(Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0,0 )); + CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, + EC_OC_REG_COMM_EXEC_CTL_ACTIVE,0 )); + } while(0); + + return status; +} + +static int StartOC(struct drxd_state *state) +{ + int status=0; + + do { + /* Stop OC */ + CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, + EC_OC_REG_COMM_EXEC_CTL_HOLD,0 )); + + /* Restore output configuration */ + CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A, + state->m_EcOcRegSncSncLvl,0 )); + CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, + state->m_EcOcRegOcModeLop,0 )); + + /* Output pins active again */ + CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A, + EC_OC_REG_OCR_MPG_UOS_INIT,0 )); + + /* Start OC */ + CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, + EC_OC_REG_COMM_EXEC_CTL_ACTIVE,0 )); + } while(0); + return status; +} + +static int InitEQ(struct drxd_state *state) +{ + return WriteTable(state, state->m_InitEQ); +} + +static int InitEC(struct drxd_state *state) +{ + return WriteTable(state, state->m_InitEC); +} + +static int InitSC(struct drxd_state *state) +{ + return WriteTable(state, state->m_InitSC); +} + +static int InitAtomicRead(struct drxd_state *state) +{ + return WriteTable(state, state->m_InitAtomicRead); +} + +static int CorrectSysClockDeviation(struct drxd_state *state); + +static int DRX_GetLockStatus(struct drxd_state *state, u32 *pLockStatus) +{ + u16 ScRaRamLock = 0; + const u16 mpeg_lock_mask = ( SC_RA_RAM_LOCK_MPEG__M | + SC_RA_RAM_LOCK_FEC__M | + SC_RA_RAM_LOCK_DEMOD__M ); + const u16 fec_lock_mask = ( SC_RA_RAM_LOCK_FEC__M | + SC_RA_RAM_LOCK_DEMOD__M ); + const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M ; + + int status; + + *pLockStatus=0; + + status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000 ); + if(status<0) { + printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n", + status); + return status; + } + + if( state->drxd_state != DRXD_STARTED ) + return 0; + + if ( (ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask ) { + *pLockStatus|=DRX_LOCK_MPEG; + CorrectSysClockDeviation(state); + } + + if ( (ScRaRamLock & fec_lock_mask) == fec_lock_mask ) + *pLockStatus|=DRX_LOCK_FEC; + + if ( (ScRaRamLock & demod_lock_mask) == demod_lock_mask ) + *pLockStatus|=DRX_LOCK_DEMOD; + return 0; +} + +/****************************************************************************/ + +static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) +{ + int status; + + if( cfg->outputLevel > DRXD_FE_CTRL_MAX ) + return -1; + + if( cfg->ctrlMode == AGC_CTRL_USER ) { + do { + u16 FeAgRegPm1AgcWri; + u16 FeAgRegAgModeLop; + + CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A, + &FeAgRegAgModeLop,0)); + FeAgRegAgModeLop &= + (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); + FeAgRegAgModeLop |= + FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC; + CHK_ERROR(Write16(state,FE_AG_REG_AG_MODE_LOP__A, + FeAgRegAgModeLop,0)); + + FeAgRegPm1AgcWri = (u16)(cfg->outputLevel & + FE_AG_REG_PM1_AGC_WRI__M); + CHK_ERROR(Write16(state,FE_AG_REG_PM1_AGC_WRI__A, + FeAgRegPm1AgcWri,0)); + } + while(0); + } else if( cfg->ctrlMode == AGC_CTRL_AUTO ) { + if ( ( (cfg->maxOutputLevel) < (cfg->minOutputLevel) ) || + ( (cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX ) || + ( (cfg->speed) > DRXD_FE_CTRL_MAX ) || + ( (cfg->settleLevel) > DRXD_FE_CTRL_MAX ) + ) + return (-1); + do { + u16 FeAgRegAgModeLop; + u16 FeAgRegEgcSetLvl; + u16 slope, offset; + + /* == Mode == */ + + CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A, + &FeAgRegAgModeLop,0)); + FeAgRegAgModeLop &= + (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); + FeAgRegAgModeLop |= + FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC; + CHK_ERROR(Write16(state,FE_AG_REG_AG_MODE_LOP__A, + FeAgRegAgModeLop,0)); + + /* == Settle level == */ + + FeAgRegEgcSetLvl = (u16)(( cfg->settleLevel >> 1 ) & + FE_AG_REG_EGC_SET_LVL__M ); + CHK_ERROR(Write16(state,FE_AG_REG_EGC_SET_LVL__A, + FeAgRegEgcSetLvl,0)); + + /* == Min/Max == */ + + slope = (u16)(( cfg->maxOutputLevel - + cfg->minOutputLevel )/2); + offset = (u16)(( cfg->maxOutputLevel + + cfg->minOutputLevel )/2 - 511); + + CHK_ERROR(Write16(state,FE_AG_REG_GC1_AGC_RIC__A, + slope,0)); + CHK_ERROR(Write16(state,FE_AG_REG_GC1_AGC_OFF__A, + offset,0)); + + /* == Speed == */ + { + const u16 maxRur = 8; + const u16 slowIncrDecLUT[]={ 3, 4, 4, 5, 6 }; + const u16 fastIncrDecLUT[]={ 14, 15, 15, 16, + 17, 18, 18, 19, + 20, 21, 22, 23, + 24, 26, 27, 28, + 29, 31}; + + u16 fineSteps = (DRXD_FE_CTRL_MAX+1)/ + (maxRur+1); + u16 fineSpeed = (u16)(cfg->speed - + ((cfg->speed/ + fineSteps)* + fineSteps)); + u16 invRurCount= (u16)(cfg->speed / + fineSteps); + u16 rurCount; + if ( invRurCount > maxRur ) + { + rurCount = 0; + fineSpeed += fineSteps; + } else { + rurCount = maxRur - invRurCount; + } + + /* + fastInc = default * + (2^(fineSpeed/fineSteps)) + => range[default...2*default> + slowInc = default * + (2^(fineSpeed/fineSteps)) + */ + { + u16 fastIncrDec = + fastIncrDecLUT[fineSpeed/ + ((fineSteps/ + (14+1))+1) ]; + u16 slowIncrDec = slowIncrDecLUT[ + fineSpeed/(fineSteps/(3+1)) ]; + + CHK_ERROR(Write16(state, + FE_AG_REG_EGC_RUR_CNT__A, + rurCount, 0)); + CHK_ERROR(Write16(state, + FE_AG_REG_EGC_FAS_INC__A, + fastIncrDec, 0)); + CHK_ERROR(Write16(state, + FE_AG_REG_EGC_FAS_DEC__A, + fastIncrDec, 0)); + CHK_ERROR(Write16(state, + FE_AG_REG_EGC_SLO_INC__A, + slowIncrDec, 0)); + CHK_ERROR(Write16(state, + FE_AG_REG_EGC_SLO_DEC__A, + slowIncrDec, 0)); + } + } + } while(0); + + } else { + /* No OFF mode for IF control */ + return (-1); + } + return status; +} + + +static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) +{ + int status = 0; + + if( cfg->outputLevel > DRXD_FE_CTRL_MAX ) + return -1; + + if( cfg->ctrlMode == AGC_CTRL_USER ) { + do { + u16 AgModeLop=0; + u16 level = ( cfg->outputLevel ); + + if (level == DRXD_FE_CTRL_MAX ) + level++; + + CHK_ERROR( Write16(state,FE_AG_REG_PM2_AGC_WRI__A, + level, 0x0000 )); + + /*==== Mode ====*/ + + /* Powerdown PD2, WRI source */ + state->m_FeAgRegAgPwd &= + ~(FE_AG_REG_AG_PWD_PWD_PD2__M); + state->m_FeAgRegAgPwd |= + FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; + CHK_ERROR( Write16(state,FE_AG_REG_AG_PWD__A, + state->m_FeAgRegAgPwd,0x0000 )); + + CHK_ERROR( Read16(state,FE_AG_REG_AG_MODE_LOP__A, + &AgModeLop,0x0000 )); + AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M | + FE_AG_REG_AG_MODE_LOP_MODE_E__M)); + AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | + FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC ); + CHK_ERROR( Write16(state,FE_AG_REG_AG_MODE_LOP__A, + AgModeLop,0x0000 )); + + + /* enable AGC2 pin */ + { + u16 FeAgRegAgAgcSio = 0; + CHK_ERROR( Read16(state, + FE_AG_REG_AG_AGC_SIO__A, + &FeAgRegAgAgcSio, 0x0000 )); + FeAgRegAgAgcSio &= + ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); + FeAgRegAgAgcSio |= + FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; + CHK_ERROR( Write16(state, + FE_AG_REG_AG_AGC_SIO__A, + FeAgRegAgAgcSio, 0x0000 )); + } + + } while(0); + } else if( cfg->ctrlMode == AGC_CTRL_AUTO ) { + u16 AgModeLop=0; + + do { + u16 level; + /* Automatic control */ + /* Powerup PD2, AGC2 as output, TGC source */ + (state->m_FeAgRegAgPwd) &= + ~(FE_AG_REG_AG_PWD_PWD_PD2__M); + (state->m_FeAgRegAgPwd) |= + FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; + CHK_ERROR(Write16(state,FE_AG_REG_AG_PWD__A, + (state->m_FeAgRegAgPwd),0x0000 )); + + CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A, + &AgModeLop,0x0000 )); + AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M | + FE_AG_REG_AG_MODE_LOP_MODE_E__M)); + AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | + FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC ); + CHK_ERROR(Write16(state, + FE_AG_REG_AG_MODE_LOP__A, + AgModeLop, 0x0000 )); + /* Settle level */ + level = ( (( cfg->settleLevel )>>4) & + FE_AG_REG_TGC_SET_LVL__M ); + CHK_ERROR(Write16(state, + FE_AG_REG_TGC_SET_LVL__A, + level,0x0000 )); + + /* Min/max: don't care */ + + /* Speed: TODO */ + + /* enable AGC2 pin */ + { + u16 FeAgRegAgAgcSio = 0; + CHK_ERROR( Read16(state, + FE_AG_REG_AG_AGC_SIO__A, + &FeAgRegAgAgcSio, 0x0000 )); + FeAgRegAgAgcSio &= + ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); + FeAgRegAgAgcSio |= + FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; + CHK_ERROR( Write16(state, + FE_AG_REG_AG_AGC_SIO__A, + FeAgRegAgAgcSio, 0x0000 )); + } + + } while(0); + } else { + u16 AgModeLop=0; + + do { + /* No RF AGC control */ + /* Powerdown PD2, AGC2 as output, WRI source */ + (state->m_FeAgRegAgPwd) &= + ~(FE_AG_REG_AG_PWD_PWD_PD2__M); + (state->m_FeAgRegAgPwd) |= + FE_AG_REG_AG_PWD_PWD_PD2_ENABLE; + CHK_ERROR(Write16(state, + FE_AG_REG_AG_PWD__A, + (state->m_FeAgRegAgPwd),0x0000 )); + + CHK_ERROR(Read16(state, + FE_AG_REG_AG_MODE_LOP__A, + &AgModeLop,0x0000 )); + AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M | + FE_AG_REG_AG_MODE_LOP_MODE_E__M)); + AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | + FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC ); + CHK_ERROR(Write16(state, + FE_AG_REG_AG_MODE_LOP__A, + AgModeLop,0x0000 )); + + /* set FeAgRegAgAgcSio AGC2 (RF) as input */ + { + u16 FeAgRegAgAgcSio = 0; + CHK_ERROR( Read16(state, + FE_AG_REG_AG_AGC_SIO__A, + &FeAgRegAgAgcSio, 0x0000 )); + FeAgRegAgAgcSio &= + ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); + FeAgRegAgAgcSio |= + FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT; + CHK_ERROR( Write16(state, + FE_AG_REG_AG_AGC_SIO__A, + FeAgRegAgAgcSio, 0x0000 )); + } + } while(0); + } + return status; +} + +static int ReadIFAgc(struct drxd_state *state, u32 *pValue) +{ + int status = 0; + + *pValue = 0; + if( state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF ) { + u16 Value; + status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A,&Value,0); + Value &= FE_AG_REG_GC1_AGC_DAT__M; + if(status>=0) { + /* 3.3V + | + R1 + | + Vin - R3 - * -- Vout + | + R2 + | + GND + */ + u32 R1 = state->if_agc_cfg.R1; + u32 R2 = state->if_agc_cfg.R2; + u32 R3 = state->if_agc_cfg.R3; + + u32 Vmax = (3300 * R2) / ( R1 + R2 ); + u32 Rpar = ( R2 * R3 ) / ( R3 + R2 ); + u32 Vmin = (3300 * Rpar ) / ( R1 + Rpar ); + u32 Vout = Vmin + (( Vmax - Vmin ) * Value) / 1024; + + *pValue = Vout; + } + } + return status; +} + +static int DownloadMicrocode(struct drxd_state *state, + const u8 *pMCImage, u32 Length) +{ + u8 *pSrc; + u16 Flags; + u32 Address; + u16 nBlocks; + u16 BlockSize; + u16 BlockCRC; + u32 offset=0; + int i, status=0; + + pSrc=(u8 *) pMCImage; + Flags = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + nBlocks = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + + for(i=0; i<nBlocks; i++ ) { + Address=(pSrc[0] << 24) | (pSrc[1] << 16) | + (pSrc[2] << 8) | pSrc[3]; + pSrc += sizeof(u32); offset += sizeof(u32); + + BlockSize = ( (pSrc[0] << 8) | pSrc[1] ) * sizeof(u16); + pSrc += sizeof(u16); offset += sizeof(u16); + + Flags = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + + BlockCRC = (pSrc[0] << 8) | pSrc[1]; + pSrc += sizeof(u16); offset += sizeof(u16); + + status = WriteBlock(state,Address,BlockSize, + pSrc,DRX_I2C_CLEARCRC); + if (status<0) + break; + pSrc += BlockSize; + offset += BlockSize; + } + + return status; +} + +static int HI_Command(struct drxd_state *state, u16 cmd, u16 *pResult) +{ + u32 nrRetries = 0; + u16 waitCmd; + int status; + + if ((status=Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0))<0) + return status; + + do { + nrRetries+=1; + if (nrRetries>DRXD_MAX_RETRIES) { + status=-1; + break; + }; + status=Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); + } while (waitCmd!=0); + + if (status>=0) + status=Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); + return status; +} + +static int HI_CfgCommand(struct drxd_state *state) +{ + int status=0; + + down(&state->mutex); + Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, + HI_RA_RAM_SRV_RST_KEY_ACT, 0); + Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); + Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, + state->hi_cfg_bridge_delay, 0); + Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); + Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); + + Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, + HI_RA_RAM_SRV_RST_KEY_ACT, 0); + + if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)== + HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) + status=Write16(state, HI_RA_RAM_SRV_CMD__A, + HI_RA_RAM_SRV_CMD_CONFIG, 0); + else + status=HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0); + up(&state->mutex); + return status; +} + +static int InitHI(struct drxd_state *state) +{ + state->hi_cfg_wakeup_key = (state->chip_adr); + /* port/bridge/power down ctrl */ + state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; + return HI_CfgCommand(state); +} + +static int HI_ResetCommand(struct drxd_state *state) +{ + int status; + + down(&state->mutex); + status=Write16(state, HI_RA_RAM_SRV_RST_KEY__A, + HI_RA_RAM_SRV_RST_KEY_ACT, 0); + if (status==0) + status=HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0); + up(&state->mutex); + msleep(1); + return status; +} + +static int DRX_ConfigureI2CBridge(struct drxd_state *state, + int bEnableBridge) +{ + state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); + if ( bEnableBridge ) + state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; + else + state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; + + return HI_CfgCommand(state); +} + +#define HI_TR_WRITE 0x9 +#define HI_TR_READ 0xA +#define HI_TR_READ_WRITE 0xB +#define HI_TR_BROADCAST 0x4 + +#if 0 +static int AtomicReadBlock(struct drxd_state *state, + u32 Addr, u16 DataSize, u8 *pData, u8 Flags) +{ + int status; + int i=0; + + /* Parameter check */ + if ( (!pData) || ( (DataSize & 1)!=0 ) ) + return -1; + + down(&state->mutex); + + do { + /* Instruct HI to read n bytes */ + /* TODO use proper names forthese egisters */ + CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_KEY__A, + (HI_TR_FUNC_ADDR & 0xFFFF), 0)); + CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_DIV__A, + (u16)(Addr >> 16), 0)); + CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_BDL__A, + (u16)(Addr & 0xFFFF), 0)); + CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_WUP__A, + (u16)((DataSize/2) - 1), 0)); + CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_ACT__A, + HI_TR_READ, 0)); + + CHK_ERROR( HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE,0)); + + } while(0); + + if (status>=0) { + for (i = 0; i < (DataSize/2); i += 1) { + u16 word; + + status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i), + &word, 0); + if( status<0) + break; + pData[2*i] = (u8) (word & 0xFF); + pData[(2*i) + 1] = (u8) (word >> 8 ); + } + } + up(&state->mutex); + return status; +} + +static int AtomicReadReg32(struct drxd_state *state, + u32 Addr, u32 *pData, u8 Flags) +{ + u8 buf[sizeof (u32)]; + int status; + + if (!pData) + return -1; + status=AtomicReadBlock(state, Addr, sizeof (u32), buf, Flags); + *pData = (((u32) buf[0]) << 0) + + (((u32) buf[1]) << 8) + + (((u32) buf[2]) << 16) + + (((u32) buf[3]) << 24); + return status; +} +#endif + +static int StopAllProcessors(struct drxd_state *state) +{ + return Write16(state, HI_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST); +} + +static int EnableAndResetMB(struct drxd_state *state) +{ + if (state->type_A) { + /* disable? monitor bus observe @ EC_OC */ + Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000); + } + + /* do inverse broadcast, followed by explicit write to HI */ + Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST); + Write16(state, HI_COMM_MB__A, 0x0000, 0x0000); + return 0; +} + +static int InitCC(struct drxd_state *state) +{ + if (state->osc_clock_freq == 0 || + state->osc_clock_freq > 20000 || + (state->osc_clock_freq % 4000 ) != 0 ) { + printk("invalid osc frequency %d\n", state->osc_clock_freq); + return -1; + } + + Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); + Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL | + CC_REG_PLL_MODE_PUMP_CUR_12, 0); + Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq/4000, 0); + Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0); + Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); + + return 0; +} + +static int ResetECOD(struct drxd_state *state) +{ + int status = 0; + + if(state->type_A ) + status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); + else + status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); + + if (!(status<0)) + status = WriteTable(state, state->m_ResetECRAM); + if (!(status<0)) + status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); + return status; +} + + +/* Configure PGA switch */ + +static int SetCfgPga(struct drxd_state *state, int pgaSwitch) +{ + int status; + u16 AgModeLop = 0; + u16 AgModeHip = 0; + do { + if ( pgaSwitch ) { + /* PGA on */ + /* fine gain */ + CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, + &AgModeLop, 0x0000)); + AgModeLop&=(~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); + AgModeLop|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC; + CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, + AgModeLop, 0x0000)); + + /* coarse gain */ + CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, + &AgModeHip, 0x0000)); + AgModeHip&=(~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); + AgModeHip|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC ; + CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, + AgModeHip, 0x0000)); + + /* enable fine and coarse gain, enable AAF, + no ext resistor */ + CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, + B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, + 0x0000)); + } else { + /* PGA off, bypass */ + + /* fine gain */ + CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, + &AgModeLop, 0x0000)); + AgModeLop&=(~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); + AgModeLop|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC ; + CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, + AgModeLop, 0x0000)); + + /* coarse gain */ + CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, + &AgModeHip, 0x0000)); + AgModeHip&=(~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); + AgModeHip|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC ; + CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, + AgModeHip, 0x0000)); + + /* disable fine and coarse gain, enable AAF, + no ext resistor */ + CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, + B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, + 0x0000)); + } + } + while(0); + return status; +} + +static int InitFE(struct drxd_state *state) +{ + int status; + + do + { + CHK_ERROR( WriteTable(state, state->m_InitFE_1)); + + if( state->type_A ) { + status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, + FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0); + } else { + if (state->PGA) + status = SetCfgPga(state, 0); + else + status = + Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, + B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0); + } + + if (status<0) break; + CHK_ERROR( Write16( state, FE_AG_REG_AG_AGC_SIO__A, + state->m_FeAgRegAgAgcSio, 0x0000)); + CHK_ERROR( Write16( state, FE_AG_REG_AG_PWD__A,state->m_FeAgRegAgPwd, + 0x0000)); + + CHK_ERROR( WriteTable(state, state->m_InitFE_2)); + + + } while(0); + + return status; +} + +static int InitFT(struct drxd_state *state) +{ + /* + norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk + SC stuff + */ + return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000 ); +} + +static int SC_WaitForReady(struct drxd_state *state) +{ + u16 curCmd; + int i; + + for(i = 0; i < DRXD_MAX_RETRIES; i += 1 ) + { + int status = Read16(state, SC_RA_RAM_CMD__A,&curCmd,0); + if (status==0 || curCmd == 0 ) + return status; + } + return -1; +} + +static int SC_SendCommand(struct drxd_state *state, u16 cmd) +{ + int status=0; + u16 errCode; + + Write16(state, SC_RA_RAM_CMD__A,cmd,0); + SC_WaitForReady(state); + + Read16(state, SC_RA_RAM_CMD_ADDR__A,&errCode,0); + + if( errCode == 0xFFFF ) + { + printk("Command Error\n"); + status = -1; + } + + return status; +} + +static int SC_ProcStartCommand(struct drxd_state *state, + u16 subCmd,u16 param0,u16 param1) +{ + int status=0; + u16 scExec; + + down(&state->mutex); + do { + Read16(state, SC_COMM_EXEC__A, &scExec, 0); + if (scExec != 1) { + status=-1; + break; + } + SC_WaitForReady(state); + Write16(state, SC_RA_RAM_CMD_ADDR__A,subCmd,0); + Write16(state, SC_RA_RAM_PARAM1__A,param1,0); + Write16(state, SC_RA_RAM_PARAM0__A,param0,0); + + SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); + } while(0); + up(&state->mutex); + return status; +} + + +static int SC_SetPrefParamCommand(struct drxd_state *state, + u16 subCmd,u16 param0,u16 param1) +{ + int status; + + down(&state->mutex); + do { + CHK_ERROR( SC_WaitForReady(state) ); + CHK_ERROR( Write16(state,SC_RA_RAM_CMD_ADDR__A,subCmd,0) ); + CHK_ERROR( Write16(state,SC_RA_RAM_PARAM1__A,param1,0) ); + CHK_ERROR( Write16(state,SC_RA_RAM_PARAM0__A,param0,0) ); + + CHK_ERROR( SC_SendCommand(state, + SC_RA_RAM_CMD_SET_PREF_PARAM) ); + } while(0); + up(&state->mutex); + return status; +} + +#if 0 +static int SC_GetOpParamCommand(struct drxd_state *state, u16 *result) +{ + int status=0; + + down(&state->mutex); + do { + CHK_ERROR( SC_WaitForReady(state) ); + CHK_ERROR( SC_SendCommand(state, + SC_RA_RAM_CMD_GET_OP_PARAM) ); + CHK_ERROR( Read16(state, SC_RA_RAM_PARAM0__A,result, 0 ) ); + } while(0); + up(&state->mutex); + return status; +} +#endif + +static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) +{ + int status; + + do { + u16 EcOcRegIprInvMpg = 0; + u16 EcOcRegOcModeLop = 0; + u16 EcOcRegOcModeHip = 0; + u16 EcOcRegOcMpgSio = 0; + + /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, + &EcOcRegOcModeLop, 0));*/ + + if( state->operation_mode == OM_DVBT_Diversity_Front ) + { + if ( bEnableOutput ) + { + EcOcRegOcModeHip |= + B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR; + } + else + EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; + EcOcRegOcModeLop |= + EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; + } + else + { + EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; + + if (bEnableOutput) + EcOcRegOcMpgSio &= + (~(EC_OC_REG_OC_MPG_SIO__M)); + else + EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; + + /* Don't Insert RS Byte */ + if( state->insert_rs_byte ) + { + EcOcRegOcModeLop &= + (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M)); + EcOcRegOcModeHip &= + (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); + EcOcRegOcModeHip |= + EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE; + } else { + EcOcRegOcModeLop |= + EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; + EcOcRegOcModeHip &= + (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); + EcOcRegOcModeHip |= + EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE; + } + + /* Mode = Parallel */ + if( state->enable_parallel ) + EcOcRegOcModeLop &= + (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M)); + else + EcOcRegOcModeLop |= + EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL; + } + /* Invert Data */ + /* EcOcRegIprInvMpg |= 0x00FF; */ + EcOcRegIprInvMpg &= (~(0x00FF)); + + /* Invert Error ( we don't use the pin ) */ + /* EcOcRegIprInvMpg |= 0x0100; */ + EcOcRegIprInvMpg &= (~(0x0100)); + + /* Invert Start ( we don't use the pin ) */ + /* EcOcRegIprInvMpg |= 0x0200; */ + EcOcRegIprInvMpg &= (~(0x0200)); + + /* Invert Valid ( we don't use the pin ) */ + /* EcOcRegIprInvMpg |= 0x0400; */ + EcOcRegIprInvMpg &= (~(0x0400)); + + /* Invert Clock */ + /* EcOcRegIprInvMpg |= 0x0800; */ + EcOcRegIprInvMpg &= (~(0x0800)); + + /* EcOcRegOcModeLop =0x05; */ + CHK_ERROR( Write16(state, EC_OC_REG_IPR_INV_MPG__A, + EcOcRegIprInvMpg, 0)); + CHK_ERROR( Write16(state, EC_OC_REG_OC_MODE_LOP__A, + EcOcRegOcModeLop, 0) ); + CHK_ERROR( Write16(state, EC_OC_REG_OC_MODE_HIP__A, + EcOcRegOcModeHip, 0x0000 ) ); + CHK_ERROR( Write16(state, EC_OC_REG_OC_MPG_SIO__A, + EcOcRegOcMpgSio, 0) ); + } while(0); + return status; +} + +static int SetDeviceTypeId(struct drxd_state *state) +{ + int status = 0; + u16 deviceId = 0 ; + + do { + CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); + /* TODO: why twice? */ + CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); + printk( "drxd: deviceId = %04x\n",deviceId); + + state->type_A = 0; + state->PGA = 0; + state->diversity = 0; + if (deviceId == 0) { /* on A2 only 3975 available */ + state->type_A = 1; + printk("DRX3975D-A2\n"); + } else { + deviceId >>= 12; + printk("DRX397%dD-B1\n",deviceId); + switch(deviceId) { + case 4: + state->diversity = 1; + case 3: + case 7: + state->PGA = 1; + break; + case 6: + state->diversity = 1; + case 5: + case 8: + break; + default: + status = -1; + break; + } + } + } while(0); + + if (status<0) + return status; + + /* Init Table selection */ + state->m_InitAtomicRead = DRXD_InitAtomicRead; + state->m_InitSC = DRXD_InitSC; + state->m_ResetECRAM = DRXD_ResetECRAM; + if (state->type_A) { + state->m_ResetCEFR = DRXD_ResetCEFR; + state->m_InitFE_1 = DRXD_InitFEA2_1; + state->m_InitFE_2 = DRXD_InitFEA2_2; + state->m_InitCP = DRXD_InitCPA2; + state->m_InitCE = DRXD_InitCEA2; + state->m_InitEQ = DRXD_InitEQA2; + state->m_InitEC = DRXD_InitECA2; + state->microcode = DRXD_A2_microcode; + state->microcode_length = DRXD_A2_microcode_length; + } else { + state->m_ResetCEFR = NULL; + state->m_InitFE_1 = DRXD_InitFEB1_1; + state->m_InitFE_2 = DRXD_InitFEB1_2; + state->m_InitCP = DRXD_InitCPB1; + state->m_InitCE = DRXD_InitCEB1; + state->m_InitEQ = DRXD_InitEQB1; + state->m_InitEC = DRXD_InitECB1; + state->microcode = DRXD_B1_microcode; + state->microcode_length = DRXD_B1_microcode_length; + } + if (state->diversity) { + state->m_InitDiversityFront = DRXD_InitDiversityFront; + state->m_InitDiversityEnd = DRXD_InitDiversityEnd; + state->m_DisableDiversity = DRXD_DisableDiversity; + state->m_StartDiversityFront = DRXD_StartDiversityFront; + state->m_StartDiversityEnd = DRXD_StartDiversityEnd; + state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; + state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; + } else { + state->m_InitDiversityFront = NULL; + state->m_InitDiversityEnd = NULL; + state->m_DisableDiversity = NULL; + state->m_StartDiversityFront = NULL; + state->m_StartDiversityEnd = NULL; + state->m_DiversityDelay8MHZ = NULL; + state->m_DiversityDelay6MHZ = NULL; + } + + return status; +} + +static int CorrectSysClockDeviation(struct drxd_state *state) +{ + int status; + s32 incr = 0; + s32 nomincr = 0; + u32 bandwidth=0; + u32 sysClockInHz=0; + u32 sysClockFreq=0; /* in kHz */ + s16 oscClockDeviation; + s16 Diff; + + do { + /* Retrieve bandwidth and incr, sanity check */ + + /* These accesses should be AtomicReadReg32, but that + causes trouble (at least for diversity */ + CHK_ERROR( Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, + ((u32 *)&nomincr),0 )); + CHK_ERROR( Read32(state, FE_IF_REG_INCR0__A, + (u32 *) &incr,0 )); + + if( state->type_A ) { + if( (nomincr - incr < -500) || + (nomincr - incr > 500 ) ) + break; + } else { + if( (nomincr - incr < -2000 ) || + (nomincr - incr > 2000 ) ) + break; + } + + switch( state->param.u.ofdm.bandwidth ) + { + case BANDWIDTH_8_MHZ : + bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; + break; + case BANDWIDTH_7_MHZ : + bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; + break; + case BANDWIDTH_6_MHZ : + bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; + break; + default : + return -1; + break; + } + + /* Compute new sysclock value + sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */ + incr += (1<<23); + sysClockInHz = MulDiv32(incr,bandwidth,1<<21); + sysClockFreq= (u32)(sysClockInHz/1000); + /* rounding */ + if ( ( sysClockInHz%1000 ) > 500 ) + { + sysClockFreq++; + } + + /* Compute clock deviation in ppm */ + oscClockDeviation = (u16) ( + (((s32)(sysClockFreq) - + (s32)(state->expected_sys_clock_freq))* + 1000000L)/(s32)(state->expected_sys_clock_freq) ); + + Diff = oscClockDeviation - state->osc_clock_deviation; + /*printk("sysclockdiff=%d\n", Diff);*/ + if( Diff >= -200 && Diff <= 200 ) { + state->sys_clock_freq = (u16) sysClockFreq; + if( oscClockDeviation != + state->osc_clock_deviation ) { + if (state->config.osc_deviation) { + state->config.osc_deviation( + state->priv, + oscClockDeviation, 1); + state->osc_clock_deviation= + oscClockDeviation; + } + } + /* switch OFF SRMM scan in SC */ + CHK_ERROR( Write16( state, + SC_RA_RAM_SAMPLE_RATE_COUNT__A, + DRXD_OSCDEV_DONT_SCAN,0)); + /* overrule FE_IF internal value for + proper re-locking */ + CHK_ERROR( Write16( state, SC_RA_RAM_IF_SAVE__AX, + state->current_fe_if_incr, 0)); + state->cscd_state = CSCD_SAVED; + } + } while(0); + + return (status); +} + +static int DRX_Stop(struct drxd_state *state) +{ + int status; + + if( state->drxd_state != DRXD_STARTED ) + return 0; + + do { + if (state->cscd_state != CSCD_SAVED ) { + u32 lock; + CHK_ERROR( DRX_GetLockStatus(state, &lock)); + } + + CHK_ERROR(StopOC(state)); + + state->drxd_state = DRXD_STOPPED; + + CHK_ERROR( ConfigureMPEGOutput(state, 0) ); + + if(state->type_A ) { + /* Stop relevant processors off the device */ + CHK_ERROR( Write16(state, EC_OD_REG_COMM_EXEC__A, + 0x0000, 0x0000)); + + CHK_ERROR( Write16(state, SC_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0 )); + CHK_ERROR( Write16(state, LC_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0 )); + } else { + /* Stop all processors except HI & CC & FE */ + CHK_ERROR(Write16(state, + B_SC_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0 )); + CHK_ERROR(Write16(state, + B_LC_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0 )); + CHK_ERROR(Write16(state, + B_FT_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0 )); + CHK_ERROR(Write16(state, + B_CP_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0 )); + CHK_ERROR(Write16(state, + B_CE_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0 )); + CHK_ERROR(Write16(state, + B_EQ_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0 )); + CHK_ERROR(Write16(state, + EC_OD_REG_COMM_EXEC__A, + 0x0000, 0 )); + } + + } while(0); + return status; +} + + +int SetOperationMode(struct drxd_state *state, int oMode) +{ + int status; + + do { + if (state->drxd_state != DRXD_STOPPED) { + status = -1; + break; + } + + if (oMode == state->operation_mode) { + status = 0; + break; + } + + if (oMode != OM_Default && !state->diversity) { + status = -1; + break; + } + + switch(oMode) + { + case OM_DVBT_Diversity_Front: + status = WriteTable(state, + state->m_InitDiversityFront); + break; + case OM_DVBT_Diversity_End: + status = WriteTable(state, + state->m_InitDiversityEnd); + break; + case OM_Default: + /* We need to check how to + get DRXD out of diversity */ + default: + status = WriteTable(state, state->m_DisableDiversity); + break; + } + } while(0); + + if (!status) + state->operation_mode = oMode; + return status; +} + + + +static int StartDiversity(struct drxd_state *state) +{ + int status=0; + u16 rcControl; + + do { + if (state->operation_mode == OM_DVBT_Diversity_Front) { + CHK_ERROR(WriteTable(state, + state->m_StartDiversityFront)); + } else if( state->operation_mode == OM_DVBT_Diversity_End ) { + CHK_ERROR(WriteTable(state, + state->m_StartDiversityEnd)); + if( state->param.u.ofdm.bandwidth == + BANDWIDTH_8_MHZ ) { + CHK_ERROR( + WriteTable(state, + state-> + m_DiversityDelay8MHZ)); + } else { + CHK_ERROR( + WriteTable(state, + state-> + m_DiversityDelay6MHZ)); + } + + CHK_ERROR(Read16(state, + B_EQ_REG_RC_SEL_CAR__A, + &rcControl,0)); + rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M); + rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON | + /* combining enabled */ + B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | + B_EQ_REG_RC_SEL_CAR_PASS_A_CC | + B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC; + CHK_ERROR(Write16(state, + B_EQ_REG_RC_SEL_CAR__A, + rcControl,0)); + } + } while(0); + return status; +} + + +static int SetFrequencyShift(struct drxd_state *state, + u32 offsetFreq, int channelMirrored) +{ + int negativeShift = (state->tuner_mirrors == channelMirrored); + + /* Handle all mirroring + * + * Note: ADC mirroring (aliasing) is implictly handled by limiting + * feFsRegAddInc to 28 bits below + * (if the result before masking is more than 28 bits, this means + * that the ADC is mirroring. + * The masking is in fact the aliasing of the ADC) + * + */ + + /* Compute register value, unsigned computation */ + state->fe_fs_add_incr = MulDiv32( state->intermediate_freq + + offsetFreq, + 1<<28, state->sys_clock_freq); + /* Remove integer part */ + state->fe_fs_add_incr &= 0x0FFFFFFFL; + if (negativeShift) + { + state->fe_fs_add_incr = ((1<<28) - state->fe_fs_add_incr); + } + + /* Save the frequency shift without tunerOffset compensation + for CtrlGetChannel. */ + state->org_fe_fs_add_incr = MulDiv32( state->intermediate_freq, + 1<<28, state->sys_clock_freq); + /* Remove integer part */ + state->org_fe_fs_add_incr &= 0x0FFFFFFFL; + if (negativeShift) + state->org_fe_fs_add_incr = ((1L<<28) - + state->org_fe_fs_add_incr); + + return Write32(state, FE_FS_REG_ADD_INC_LOP__A, + state->fe_fs_add_incr, 0); +} + +static int SetCfgNoiseCalibration (struct drxd_state *state, + struct SNoiseCal* noiseCal ) +{ + u16 beOptEna; + int status=0; + + do { + CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A, + &beOptEna, 0)); + if (noiseCal->cpOpt) + { + beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); + } else { + beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); + CHK_ERROR(Write16(state, CP_REG_AC_NEXP_OFFS__A, + noiseCal->cpNexpOfs, 0)); + } + CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A, + beOptEna, 0)); + + if( !state->type_A ) + { + CHK_ERROR(Write16( state, + B_SC_RA_RAM_CO_TD_CAL_2K__A, + noiseCal->tdCal2k,0)); + CHK_ERROR(Write16( state, + B_SC_RA_RAM_CO_TD_CAL_8K__A, + noiseCal->tdCal8k,0)); + } + } while(0); + + return status; +} + +static int DRX_Start(struct drxd_state *state, s32 off) +{ + struct dvb_ofdm_parameters *p = &state->param.u.ofdm; + int status; + + u16 transmissionParams = 0; + u16 operationMode = 0; + u16 qpskTdTpsPwr = 0; + u16 qam16TdTpsPwr = 0; + u16 qam64TdTpsPwr = 0; + u32 feIfIncr = 0; + u32 bandwidth = 0; + int mirrorFreqSpect; + + u16 qpskSnCeGain = 0; + u16 qam16SnCeGain = 0; + u16 qam64SnCeGain = 0; + u16 qpskIsGainMan = 0; + u16 qam16IsGainMan = 0; + u16 qam64IsGainMan = 0; + u16 qpskIsGainExp = 0; + u16 qam16IsGainExp = 0; + u16 qam64IsGainExp = 0; + u16 bandwidthParam = 0; + + if (off<0) + off=(off-500)/1000; + else + off=(off+500)/1000; + + do { + if (state->drxd_state != DRXD_STOPPED) + return -1; + CHK_ERROR( ResetECOD(state) ); + if (state->type_A) { + CHK_ERROR( InitSC(state) ); + } else { + CHK_ERROR( InitFT(state) ); + CHK_ERROR( InitCP(state) ); + CHK_ERROR( InitCE(state) ); + CHK_ERROR( InitEQ(state) ); + CHK_ERROR( InitSC(state) ); + } + + /* Restore current IF & RF AGC settings */ + + CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg )); + CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg )); + + mirrorFreqSpect=( state->param.inversion==INVERSION_ON); + + switch (p->transmission_mode) { + default: /* Not set, detect it automatically */ + operationMode |= SC_RA_RAM_OP_AUTO_MODE__M; + /* fall through , try first guess DRX_FFTMODE_8K */ + case TRANSMISSION_MODE_8K : + transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K; + if (state->type_A) { + CHK_ERROR( Write16(state, + EC_SB_REG_TR_MODE__A, + EC_SB_REG_TR_MODE_8K, + 0x0000 )); + qpskSnCeGain = 99; + qam16SnCeGain = 83; + qam64SnCeGain = 67; + } + break; + case TRANSMISSION_MODE_2K : + transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K; + if (state->type_A) { + CHK_ERROR( Write16(state, + EC_SB_REG_TR_MODE__A, + EC_SB_REG_TR_MODE_2K, + 0x0000 )); + qpskSnCeGain = 97; + qam16SnCeGain = 71; + qam64SnCeGain = 65; + } + break; + } + + switch( p->guard_interval ) + { + case GUARD_INTERVAL_1_4: + transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; + break; + case GUARD_INTERVAL_1_8: + transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8; + break; + case GUARD_INTERVAL_1_16: + transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16; + break; + case GUARD_INTERVAL_1_32: + transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32; + break; + default: /* Not set, detect it automatically */ + operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M; + /* try first guess 1/4 */ + transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; + break; + } + + switch( p->hierarchy_information ) + { + case HIERARCHY_1: + transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1; + if (state->type_A) { + CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, + 0x0001, 0x0000 ) ); + CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, + 0x0001, 0x0000 ) ); + + qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; + qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1; + qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1; + + qpskIsGainMan = + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; + qam16IsGainMan = + SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; + qam64IsGainMan = + SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; + + qpskIsGainExp = + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; + qam16IsGainExp = + SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; + qam64IsGainExp = + SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; + } + break; + + case HIERARCHY_2: + transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2; + if (state->type_A) { + CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, + 0x0002, 0x0000 ) ); + CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, + 0x0002, 0x0000 ) ); + + qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; + qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2; + qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2; + + qpskIsGainMan = + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; + qam16IsGainMan = + SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE; + qam64IsGainMan = + SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE; + + qpskIsGainExp = + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; + qam16IsGainExp = + SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE; + qam64IsGainExp = + SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE; + } + break; + case HIERARCHY_4: + transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4; + if (state->type_A) { + CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, + 0x0003, 0x0000 )); + CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, + 0x0003, 0x0000 ) ); + + qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; + qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4; + qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4; + + qpskIsGainMan = + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; + qam16IsGainMan = + SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE; + qam64IsGainMan = + SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE; + + qpskIsGainExp = + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; + qam16IsGainExp = + SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE; + qam64IsGainExp = + SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE; + } + break; + case HIERARCHY_AUTO: + default: + /* Not set, detect it automatically, start with none */ + operationMode |= SC_RA_RAM_OP_AUTO_HIER__M; + transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO; + if (state->type_A) { + CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, + 0x0000, 0x0000 ) ); + CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, + 0x0000, 0x0000 ) ); + + qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK; + qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN; + qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN; + + qpskIsGainMan = + SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE; + qam16IsGainMan = + SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; + qam64IsGainMan = + SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; + + qpskIsGainExp = + SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE; + qam16IsGainExp = + SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; + qam64IsGainExp = + SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; + } + break; + } + CHK_ERROR( status ); + + switch( p->constellation ) { + default: + operationMode |= SC_RA_RAM_OP_AUTO_CONST__M; + /* fall through , try first guess + DRX_CONSTELLATION_QAM64 */ + case QAM_64: + transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64; + if (state->type_A) { + CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, + 0x0002, 0x0000 ) ); + CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, + EC_SB_REG_CONST_64QAM, + 0x0000) ); + CHK_ERROR(Write16(state, + EC_SB_REG_SCALE_MSB__A, + 0x0020, 0x0000 ) ); + CHK_ERROR(Write16(state, + EC_SB_REG_SCALE_BIT2__A, + 0x0008, 0x0000 ) ); + CHK_ERROR(Write16(state, + EC_SB_REG_SCALE_LSB__A, + 0x0002, 0x0000 ) ); + + CHK_ERROR(Write16(state, + EQ_REG_TD_TPS_PWR_OFS__A, + qam64TdTpsPwr, 0x0000 ) ); + CHK_ERROR( Write16(state,EQ_REG_SN_CEGAIN__A, + qam64SnCeGain, 0x0000 )); + CHK_ERROR( Write16(state,EQ_REG_IS_GAIN_MAN__A, + qam64IsGainMan, 0x0000 )); + CHK_ERROR( Write16(state,EQ_REG_IS_GAIN_EXP__A, + qam64IsGainExp, 0x0000 )); + } + break; + case QPSK : + transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK; + if (state->type_A) { + CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, + 0x0000, 0x0000 ) ); + CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, + EC_SB_REG_CONST_QPSK, + 0x0000) ); + CHK_ERROR(Write16(state, + EC_SB_REG_SCALE_MSB__A, + 0x0010, 0x0000 ) ); + CHK_ERROR(Write16(state, + EC_SB_REG_SCALE_BIT2__A, + 0x0000, 0x0000 ) ); + CHK_ERROR(Write16(state, + EC_SB_REG_SCALE_LSB__A, + 0x0000, 0x0000 ) ); + + CHK_ERROR(Write16(state, + EQ_REG_TD_TPS_PWR_OFS__A, + qpskTdTpsPwr, 0x0000 ) ); + CHK_ERROR( Write16(state, EQ_REG_SN_CEGAIN__A, + qpskSnCeGain, 0x0000 )); + CHK_ERROR( Write16(state, + EQ_REG_IS_GAIN_MAN__A, + qpskIsGainMan, 0x0000 )); + CHK_ERROR( Write16(state, + EQ_REG_IS_GAIN_EXP__A, + qpskIsGainExp, 0x0000 )); + } + break; + + case QAM_16: + transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16; + if (state->type_A) { + CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, + 0x0001, 0x0000 ) ); + CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, + EC_SB_REG_CONST_16QAM, + 0x0000) ); + CHK_ERROR(Write16(state, + EC_SB_REG_SCALE_MSB__A, + 0x0010, 0x0000 ) ); + CHK_ERROR(Write16(state, + EC_SB_REG_SCALE_BIT2__A, + 0x0004, 0x0000 ) ); + CHK_ERROR(Write16(state, + EC_SB_REG_SCALE_LSB__A, + 0x0000, 0x0000 ) ); + + CHK_ERROR(Write16(state, + EQ_REG_TD_TPS_PWR_OFS__A, + qam16TdTpsPwr, 0x0000 ) ); + CHK_ERROR( Write16(state, EQ_REG_SN_CEGAIN__A, + qam16SnCeGain, 0x0000 )); + CHK_ERROR( Write16(state, + EQ_REG_IS_GAIN_MAN__A, + qam16IsGainMan, 0x0000 )); + CHK_ERROR( Write16(state, + EQ_REG_IS_GAIN_EXP__A, + qam16IsGainExp, 0x0000 )); + } + break; + + } + CHK_ERROR( status ); + + switch (DRX_CHANNEL_HIGH) { + default: + case DRX_CHANNEL_AUTO: + case DRX_CHANNEL_LOW: + transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO; + CHK_ERROR( Write16(state, EC_SB_REG_PRIOR__A, + EC_SB_REG_PRIOR_LO, 0x0000 )); + break; + case DRX_CHANNEL_HIGH: + transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI; + CHK_ERROR( Write16(state, EC_SB_REG_PRIOR__A, + EC_SB_REG_PRIOR_HI, 0x0000 )); + break; + + } + + switch( p->code_rate_HP ) + { + case FEC_1_2: + transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2; + if (state->type_A) { + CHK_ERROR( Write16(state, + EC_VD_REG_SET_CODERATE__A, + EC_VD_REG_SET_CODERATE_C1_2, + 0x0000 ) ); + } + break; + default: + operationMode |= SC_RA_RAM_OP_AUTO_RATE__M; + case FEC_2_3 : + transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3; + if (state->type_A) { + CHK_ERROR( Write16(state, + EC_VD_REG_SET_CODERATE__A, + EC_VD_REG_SET_CODERATE_C2_3, + 0x0000 ) ); + } + break; + case FEC_3_4 : + transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4; + if (state->type_A) { + CHK_ERROR( Write16(state, + EC_VD_REG_SET_CODERATE__A, + EC_VD_REG_SET_CODERATE_C3_4, + 0x0000 ) ); + } + break; + case FEC_5_6 : + transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6; + if (state->type_A) { + CHK_ERROR( Write16(state, + EC_VD_REG_SET_CODERATE__A, + EC_VD_REG_SET_CODERATE_C5_6, + 0x0000 ) ); + } + break; + case FEC_7_8 : + transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8; + if (state->type_A) { + CHK_ERROR( Write16(state, + EC_VD_REG_SET_CODERATE__A, + EC_VD_REG_SET_CODERATE_C7_8, + 0x0000 ) ); + } + break; + } + CHK_ERROR( status ); + + /* First determine real bandwidth (Hz) */ + /* Also set delay for impulse noise cruncher (only A2) */ + /* Also set parameters for EC_OC fix, note + EC_OC_REG_TMD_HIL_MAR is changed + by SC for fix for some 8K,1/8 guard but is restored by + InitEC and ResetEC + functions */ + switch( p->bandwidth ) + { + case BANDWIDTH_AUTO: + case BANDWIDTH_8_MHZ: + /* (64/7)*(8/8)*1000000 */ + bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; + + bandwidthParam = 0; + status = Write16(state, + FE_AG_REG_IND_DEL__A , 50 , 0x0000 ); + break; + case BANDWIDTH_7_MHZ: + /* (64/7)*(7/8)*1000000 */ + bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; + bandwidthParam =0x4807; /*binary:0100 1000 0000 0111 */ + status = Write16(state, + FE_AG_REG_IND_DEL__A , 59 , 0x0000 ); + break; + case BANDWIDTH_6_MHZ: + /* (64/7)*(6/8)*1000000 */ + bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; + bandwidthParam =0x0F07; /*binary: 0000 1111 0000 0111*/ + status = Write16(state, + FE_AG_REG_IND_DEL__A , 71 , 0x0000 ); + break; + } + CHK_ERROR( status ); + + CHK_ERROR( Write16(state, + SC_RA_RAM_BAND__A, bandwidthParam, 0x0000)); + + { + u16 sc_config; + CHK_ERROR(Read16(state, + SC_RA_RAM_CONFIG__A, &sc_config, 0)); + + /* enable SLAVE mode in 2k 1/32 to + prevent timing change glitches */ + if ( (p->transmission_mode==TRANSMISSION_MODE_2K) && + (p->guard_interval==GUARD_INTERVAL_1_32) ) { + /* enable slave */ + sc_config |= SC_RA_RAM_CONFIG_SLAVE__M; + } else { + /* disable slave */ + sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M; + } + CHK_ERROR( Write16(state, + SC_RA_RAM_CONFIG__A, sc_config,0 )); + } + + CHK_ERROR( SetCfgNoiseCalibration(state, &state->noise_cal)); + + if (state->cscd_state == CSCD_INIT ) + { + /* switch on SRMM scan in SC */ + CHK_ERROR( Write16(state, + SC_RA_RAM_SAMPLE_RATE_COUNT__A, + DRXD_OSCDEV_DO_SCAN, 0x0000 )); +/* CHK_ERROR( Write16( SC_RA_RAM_SAMPLE_RATE_STEP__A, + DRXD_OSCDEV_STEP , 0x0000 ));*/ + state->cscd_state = CSCD_SET; + } + + + /* Now compute FE_IF_REG_INCR */ + /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) => + ((SysFreq / BandWidth) * (2^21) ) - (2^23)*/ + feIfIncr = MulDiv32(state->sys_clock_freq*1000, + ( 1ULL<< 21 ), bandwidth) - (1<<23) ; + CHK_ERROR( Write16(state, + FE_IF_REG_INCR0__A, + (u16)(feIfIncr & FE_IF_REG_INCR0__M ), + 0x0000) ); + CHK_ERROR( Write16(state, + FE_IF_REG_INCR1__A, + (u16)((feIfIncr >> FE_IF_REG_INCR0__W) & + FE_IF_REG_INCR1__M ), 0x0000) ); + /* Bandwidth setting done */ + + /* Mirror & frequency offset */ + SetFrequencyShift(state, off, mirrorFreqSpect); + + /* Start SC, write channel settings to SC */ + + /* Enable SC after setting all other parameters */ + CHK_ERROR( Write16(state, SC_COMM_STATE__A, 0, 0x0000)); + CHK_ERROR( Write16(state, SC_COMM_EXEC__A, 1, 0x0000)); + + /* Write SC parameter registers, operation mode */ +#if 1 + operationMode =( SC_RA_RAM_OP_AUTO_MODE__M | + SC_RA_RAM_OP_AUTO_GUARD__M | + SC_RA_RAM_OP_AUTO_CONST__M | + SC_RA_RAM_OP_AUTO_HIER__M | + SC_RA_RAM_OP_AUTO_RATE__M ); +#endif + CHK_ERROR( SC_SetPrefParamCommand(state, 0x0000, + transmissionParams, + operationMode) ); + + /* Start correct processes to get in lock */ + CHK_ERROR( SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, + SC_RA_RAM_SW_EVENT_RUN_NMASK__M, + SC_RA_RAM_LOCKTRACK_MIN) ); + + CHK_ERROR( StartOC(state) ); + + if( state->operation_mode != OM_Default ) { + CHK_ERROR(StartDiversity(state)); + } + + state->drxd_state = DRXD_STARTED; + } while(0); + + return status; +} + +static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) +{ + u32 ulRfAgcOutputLevel = 0xffffffff; + u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */ + u32 ulRfAgcMinLevel = 0; /* Currently unused */ + u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */ + u32 ulRfAgcSpeed = 0; /* Currently unused */ + u32 ulRfAgcMode = 0;/*2; Off */ + u32 ulRfAgcR1 = 820; + u32 ulRfAgcR2 = 2200; + u32 ulRfAgcR3 = 150; + u32 ulIfAgcMode = 0; /* Auto */ + u32 ulIfAgcOutputLevel = 0xffffffff; + u32 ulIfAgcSettleLevel = 0xffffffff; + u32 ulIfAgcMinLevel = 0xffffffff; + u32 ulIfAgcMaxLevel = 0xffffffff; + u32 ulIfAgcSpeed = 0xffffffff; + u32 ulIfAgcR1 = 820; + u32 ulIfAgcR2 = 2200; + u32 ulIfAgcR3 = 150; + u32 ulClock = state->config.clock; + u32 ulSerialMode = 0; + u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */ + u32 ulHiI2cDelay = HI_I2C_DELAY; + u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY; + u32 ulHiI2cPatch = 0; + u32 ulEnvironment = APPENV_PORTABLE; + u32 ulEnvironmentDiversity = APPENV_MOBILE; + u32 ulIFFilter = IFFILTER_SAW; + + state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; + state->if_agc_cfg.outputLevel = 0; + state->if_agc_cfg.settleLevel = 140; + state->if_agc_cfg.minOutputLevel = 0; + state->if_agc_cfg.maxOutputLevel = 1023; + state->if_agc_cfg.speed = 904; + + if( ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX ) + { + state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; + state->if_agc_cfg.outputLevel = (u16)(ulIfAgcOutputLevel); + } + + if( ulIfAgcMode == 0 && + ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX && + ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX && + ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX && + ulIfAgcSpeed <= DRXD_FE_CTRL_MAX + ) + { + state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; + state->if_agc_cfg.settleLevel = (u16)(ulIfAgcSettleLevel); + state->if_agc_cfg.minOutputLevel = (u16)(ulIfAgcMinLevel); + state->if_agc_cfg.maxOutputLevel = (u16)(ulIfAgcMaxLevel); + state->if_agc_cfg.speed = (u16)(ulIfAgcSpeed); + } + + state->if_agc_cfg.R1 = (u16)(ulIfAgcR1); + state->if_agc_cfg.R2 = (u16)(ulIfAgcR2); + state->if_agc_cfg.R3 = (u16)(ulIfAgcR3); + + state->rf_agc_cfg.R1 = (u16)(ulRfAgcR1); + state->rf_agc_cfg.R2 = (u16)(ulRfAgcR2); + state->rf_agc_cfg.R3 = (u16)(ulRfAgcR3); + + state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; + /* rest of the RFAgcCfg structure currently unused */ + if (ulRfAgcMode==1 && ulRfAgcOutputLevel<=DRXD_FE_CTRL_MAX) { + state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; + state->rf_agc_cfg.outputLevel = (u16)(ulRfAgcOutputLevel); + } + + if( ulRfAgcMode == 0 && + ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX && + ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX && + ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX && + ulRfAgcSpeed <= DRXD_FE_CTRL_MAX + ) + { + state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; + state->rf_agc_cfg.settleLevel = (u16)(ulRfAgcSettleLevel); + state->rf_agc_cfg.minOutputLevel = (u16)(ulRfAgcMinLevel); + state->rf_agc_cfg.maxOutputLevel = (u16)(ulRfAgcMaxLevel); + state->rf_agc_cfg.speed = (u16)(ulRfAgcSpeed); + } + + if( ulRfAgcMode == 2 ) + { + state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; + } + + if (ulEnvironment <= 2) + state->app_env_default = (enum app_env) + (ulEnvironment); + if (ulEnvironmentDiversity <= 2) + state->app_env_diversity = (enum app_env) + (ulEnvironmentDiversity); + + if( ulIFFilter == IFFILTER_DISCRETE ) + { + /* discrete filter */ + state->noise_cal.cpOpt = 0; + state->noise_cal.cpNexpOfs = 40; + state->noise_cal.tdCal2k = -40; + state->noise_cal.tdCal8k = -24; + } else { + /* SAW filter */ + state->noise_cal.cpOpt = 1; + state->noise_cal.cpNexpOfs = 0; + state->noise_cal.tdCal2k = -21; + state->noise_cal.tdCal8k = -24; + } + state->m_EcOcRegOcModeLop = (u16)(ulEcOcRegOcModeLop); + + state->chip_adr = (state->config.demod_address<<1)|1; + switch( ulHiI2cPatch ) + { + case 1 : state->m_HiI2cPatch = DRXD_HiI2cPatch_1; break; + case 3 : state->m_HiI2cPatch = DRXD_HiI2cPatch_3; break; + default: + state->m_HiI2cPatch = NULL; + } + + /* modify tuner and clock attributes */ + state->intermediate_freq = (u16)(IntermediateFrequency/1000); + /* expected system clock frequency in kHz */ + state->expected_sys_clock_freq = 48000; + /* real system clock frequency in kHz */ + state->sys_clock_freq = 48000; + state->osc_clock_freq = (u16) ulClock; + state->osc_clock_deviation = 0; + state->cscd_state = CSCD_INIT; + state->drxd_state = DRXD_UNINITIALIZED; + + state->PGA=0; + state->type_A=0; + state->tuner_mirrors=0; + + /* modify MPEG output attributes */ + state->insert_rs_byte = 0; + state->enable_parallel = (ulSerialMode != 1); + + /* Timing div, 250ns/Psys */ + /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ + + state->hi_cfg_timing_div = (u16)((state->sys_clock_freq/1000)* + ulHiI2cDelay)/1000 ; + /* Bridge delay, uses oscilator clock */ + /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ + state->hi_cfg_bridge_delay = (u16)((state->osc_clock_freq/1000) * + ulHiI2cBridgeDelay)/1000 ; + + state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; + /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */ + state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; + return 0; +} + +int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) +{ + int status=0; + u32 driverVersion; + + if (state->init_done) + return 0; + + CDRXD(state, state->config.IF ? state->config.IF : 36000000); + + do { + state->operation_mode = OM_Default; + + CHK_ERROR( SetDeviceTypeId(state) ); + + /* Apply I2c address patch to B1 */ + if( !state->type_A && state->m_HiI2cPatch != NULL ) + CHK_ERROR(WriteTable(state, state->m_HiI2cPatch)); + + if (state->type_A) { + /* HI firmware patch for UIO readout, + avoid clearing of result register */ + CHK_ERROR(Write16(state, 0x43012D, 0x047f, 0)); + } + + CHK_ERROR( HI_ResetCommand(state)); + + CHK_ERROR(StopAllProcessors(state)); + CHK_ERROR(InitCC(state)); + + state->osc_clock_deviation = 0; + + if (state->config.osc_deviation) + state->osc_clock_deviation = + state->config.osc_deviation(state->priv, + 0, 0); + { + /* Handle clock deviation */ + s32 devB; + s32 devA = (s32)(state->osc_clock_deviation) * + (s32)(state->expected_sys_clock_freq); + /* deviation in kHz */ + s32 deviation = ( devA /(1000000L)); + /* rounding, signed */ + if ( devA > 0 ) + devB=(2); + else + devB=(-2); + if ( (devB*(devA%1000000L)>1000000L ) ) + { + /* add +1 or -1 */ + deviation += (devB/2); + } + + state->sys_clock_freq=(u16)((state-> + expected_sys_clock_freq)+ + deviation); + } + CHK_ERROR(InitHI(state)); + CHK_ERROR(InitAtomicRead(state)); + + CHK_ERROR(EnableAndResetMB(state)); + if (state->type_A) + CHK_ERROR(ResetCEFR(state)); + + if (fw) { + CHK_ERROR(DownloadMicrocode(state, fw, fw_size)); + } else { + CHK_ERROR(DownloadMicrocode(state, state->microcode, + state->microcode_length)); + } + + if (state->PGA) { + state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; + SetCfgPga(state, 0); /* PGA = 0 dB */ + } else { + state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; + } + + state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; + + CHK_ERROR(InitFE(state)); + CHK_ERROR(InitFT(state)); + CHK_ERROR(InitCP(state)); + CHK_ERROR(InitCE(state)); + CHK_ERROR(InitEQ(state)); + CHK_ERROR(InitEC(state)); + CHK_ERROR(InitSC(state)); + + CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg)); + CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg)); + + state->cscd_state = CSCD_INIT; + CHK_ERROR(Write16(state, SC_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0)); + CHK_ERROR(Write16(state, LC_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0 )); + + + driverVersion = (((VERSION_MAJOR/10) << 4) + + (VERSION_MAJOR%10)) << 24; + driverVersion += (((VERSION_MINOR/10) << 4) + + (VERSION_MINOR%10)) << 16; + driverVersion += ((VERSION_PATCH/1000)<<12) + + ((VERSION_PATCH/100)<<8) + + ((VERSION_PATCH/10 )<< 4) + + (VERSION_PATCH%10 ); + + CHK_ERROR(Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, + driverVersion,0 )); + + CHK_ERROR( StopOC(state) ); + + state->drxd_state = DRXD_STOPPED; + state->init_done=1; + status=0; + } while (0); + return status; +} + +int DRXD_status(struct drxd_state *state, u32 *pLockStatus) +{ + DRX_GetLockStatus(state, pLockStatus); + + /*if (*pLockStatus&DRX_LOCK_MPEG)*/ + if (*pLockStatus&DRX_LOCK_FEC) { + ConfigureMPEGOutput(state, 1); + /* Get status again, in case we have MPEG lock now */ + /*DRX_GetLockStatus(state, pLockStatus);*/ + } + + return 0; +} + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + +static int drxd_read_signal_strength(struct dvb_frontend *fe, + u16 *strength) +{ + struct drxd_state *state = fe->demodulator_priv; + u32 value; + int res; + + res=ReadIFAgc(state, &value); + if (res<0) + *strength=0; + else + *strength=0xffff-(value<<4); + return 0; +} + + +static int drxd_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct drxd_state *state = fe->demodulator_priv; + u32 lock; + + DRXD_status(state, &lock); + *status=0; + /* No MPEG lock in V255 firmware, bug ? */ +#if 1 + if (lock&DRX_LOCK_MPEG) + *status|=FE_HAS_LOCK; +#else + if (lock&DRX_LOCK_FEC) + *status|=FE_HAS_LOCK; +#endif + if (lock&DRX_LOCK_FEC) + *status|=FE_HAS_VITERBI|FE_HAS_SYNC; + if (lock&DRX_LOCK_DEMOD) + *status|=FE_HAS_CARRIER|FE_HAS_SIGNAL; + + return 0; +} + +static int drxd_init(struct dvb_frontend *fe) +{ + struct drxd_state *state=fe->demodulator_priv; + int err=0; + +/* if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */ + return DRXD_init(state, 0, 0); + + err=DRXD_init(state, state->fw->data, state->fw->size); + release_firmware(state->fw); + return err; +} + +int drxd_config_i2c(struct dvb_frontend *fe, int onoff) +{ + struct drxd_state *state=fe->demodulator_priv; + + return DRX_ConfigureI2CBridge(state, onoff); +} + +static int drxd_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *sets) +{ + sets->min_delay_ms=10000; + sets->max_drift=0; + sets->step_size=0; + return 0; +} + +static int drxd_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + *ber = 0; + return 0; +} + +static int drxd_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + *snr=0; + return 0; +} + +static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + *ucblocks=0; + return 0; +} + +static int drxd_sleep(struct dvb_frontend* fe) +{ + struct drxd_state *state=fe->demodulator_priv; + + ConfigureMPEGOutput(state, 0); + return 0; +} + +static int drxd_get_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *param) +{ + return 0; +} + +static int drxd_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) +{ + return drxd_config_i2c(fe, enable); +} + +static int drxd_set_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *param) +{ + struct drxd_state *state=fe->demodulator_priv; + s32 off=0; + + state->param=*param; + DRX_Stop(state); + + if (fe->ops.tuner_ops.set_params) { + fe->ops.tuner_ops.set_params(fe, param); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); + } + + /* FIXME: move PLL drivers */ + if (state->config.pll_set && + state->config.pll_set(state->priv, param, + state->config.pll_address, + state->config.demoda_address, + &off)<0) { + printk("Error in pll_set\n"); + return -1; + } + + msleep(200); + + return DRX_Start(state, off); +} + + +static void drxd_release(struct dvb_frontend *fe) +{ + struct drxd_state *state = fe->demodulator_priv; + + kfree(state); +} + +static struct dvb_frontend_ops drxd_ops = { + + .info = { + .name = "Micronas DRXD DVB-T", + .type = FE_OFDM, + .frequency_min = 47125000, + .frequency_max = 855250000, + .frequency_stepsize = 166667, + .frequency_tolerance = 0, + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | + FE_CAN_FEC_AUTO | + FE_CAN_QAM_16 | FE_CAN_QAM_64 | + FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | + FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | + FE_CAN_MUTE_TS + }, + + .release = drxd_release, + .init = drxd_init, + .sleep = drxd_sleep, + .i2c_gate_ctrl = drxd_i2c_gate_ctrl, + + .set_frontend = drxd_set_frontend, + .get_frontend = drxd_get_frontend, + .get_tune_settings = drxd_get_tune_settings, + + .read_status = drxd_read_status, + .read_ber = drxd_read_ber, + .read_signal_strength = drxd_read_signal_strength, + .read_snr = drxd_read_snr, + .read_ucblocks = drxd_read_ucblocks, +}; + +struct dvb_frontend *drxd_attach(const struct drxd_config *config, + void *priv, struct i2c_adapter *i2c, + struct device *dev) +{ + struct drxd_state *state = NULL; + + state=kmalloc(sizeof(struct drxd_state), GFP_KERNEL); + if (!state) + return NULL; + memset(state, 0, sizeof(*state)); + + memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops)); + state->dev=dev; + state->config=*config; + state->i2c=i2c; + state->priv=priv; + + sema_init(&state->mutex, 1); + + if (Read16(state, 0, 0, 0)<0) + goto error; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) + state->frontend.ops=&state->ops; +#else + memcpy(&state->frontend.ops, &drxd_ops, + sizeof(struct dvb_frontend_ops)); +#endif + state->frontend.demodulator_priv=state; + ConfigureMPEGOutput(state, 0); + return &state->frontend; + +error: + printk("drxd: not found\n"); + kfree(state); + return NULL; +} + +MODULE_DESCRIPTION("DRXD driver"); +MODULE_AUTHOR("Micronas"); +MODULE_LICENSE("GPL"); + +EXPORT_SYMBOL(drxd_attach); +EXPORT_SYMBOL(drxd_config_i2c); diff --git a/drivers/media/dvb/frontends/drxd_map_firm.h b/drivers/media/dvb/frontends/drxd_map_firm.h new file mode 100644 index 000000000000..3523cfee7479 --- /dev/null +++ b/drivers/media/dvb/frontends/drxd_map_firm.h @@ -0,0 +1,14484 @@ +/* + * drx3973d_map_firm.h + * + * Copyright (C) 2006-2007 Micronas + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 only, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DRX3973D_MAP__H__ +#define __DRX3973D_MAP__H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define HI_SID 0x10 + + + + + +#define HI_COMM_EXEC__A 0x400000 +#define HI_COMM_EXEC__W 3 +#define HI_COMM_EXEC__M 0x7 +#define HI_COMM_EXEC_CTL__B 0 +#define HI_COMM_EXEC_CTL__W 3 +#define HI_COMM_EXEC_CTL__M 0x7 +#define HI_COMM_EXEC_CTL_STOP 0x0 +#define HI_COMM_EXEC_CTL_ACTIVE 0x1 +#define HI_COMM_EXEC_CTL_HOLD 0x2 +#define HI_COMM_EXEC_CTL_STEP 0x3 +#define HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define HI_COMM_STATE__A 0x400001 +#define HI_COMM_STATE__W 16 +#define HI_COMM_STATE__M 0xFFFF +#define HI_COMM_MB__A 0x400002 +#define HI_COMM_MB__W 16 +#define HI_COMM_MB__M 0xFFFF +#define HI_COMM_SERVICE0__A 0x400003 +#define HI_COMM_SERVICE0__W 16 +#define HI_COMM_SERVICE0__M 0xFFFF +#define HI_COMM_SERVICE1__A 0x400004 +#define HI_COMM_SERVICE1__W 16 +#define HI_COMM_SERVICE1__M 0xFFFF +#define HI_COMM_INT_STA__A 0x400007 +#define HI_COMM_INT_STA__W 16 +#define HI_COMM_INT_STA__M 0xFFFF +#define HI_COMM_INT_MSK__A 0x400008 +#define HI_COMM_INT_MSK__W 16 +#define HI_COMM_INT_MSK__M 0xFFFF + + + + + + +#define HI_CT_REG_COMM_EXEC__A 0x410000 +#define HI_CT_REG_COMM_EXEC__W 3 +#define HI_CT_REG_COMM_EXEC__M 0x7 +#define HI_CT_REG_COMM_EXEC_CTL__B 0 +#define HI_CT_REG_COMM_EXEC_CTL__W 3 +#define HI_CT_REG_COMM_EXEC_CTL__M 0x7 +#define HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define HI_CT_REG_COMM_STATE__A 0x410001 +#define HI_CT_REG_COMM_STATE__W 10 +#define HI_CT_REG_COMM_STATE__M 0x3FF +#define HI_CT_REG_COMM_SERVICE0__A 0x410003 +#define HI_CT_REG_COMM_SERVICE0__W 16 +#define HI_CT_REG_COMM_SERVICE0__M 0xFFFF +#define HI_CT_REG_COMM_SERVICE1__A 0x410004 +#define HI_CT_REG_COMM_SERVICE1__W 16 +#define HI_CT_REG_COMM_SERVICE1__M 0xFFFF +#define HI_CT_REG_COMM_SERVICE1_HI__B 0 +#define HI_CT_REG_COMM_SERVICE1_HI__W 1 +#define HI_CT_REG_COMM_SERVICE1_HI__M 0x1 + + +#define HI_CT_REG_COMM_INT_STA__A 0x410007 +#define HI_CT_REG_COMM_INT_STA__W 1 +#define HI_CT_REG_COMM_INT_STA__M 0x1 +#define HI_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define HI_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + + +#define HI_CT_REG_COMM_INT_MSK__A 0x410008 +#define HI_CT_REG_COMM_INT_MSK__W 1 +#define HI_CT_REG_COMM_INT_MSK__M 0x1 +#define HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + + + + +#define HI_CT_REG_CTL_STK__AX 0x410010 +#define HI_CT_REG_CTL_STK__XSZ 4 +#define HI_CT_REG_CTL_STK__W 10 +#define HI_CT_REG_CTL_STK__M 0x3FF + +#define HI_CT_REG_CTL_BPT_IDX__A 0x41001F +#define HI_CT_REG_CTL_BPT_IDX__W 1 +#define HI_CT_REG_CTL_BPT_IDX__M 0x1 + +#define HI_CT_REG_CTL_BPT__A 0x410020 +#define HI_CT_REG_CTL_BPT__W 10 +#define HI_CT_REG_CTL_BPT__M 0x3FF + + + + + + +#define HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 +#define HI_RA_RAM_SLV0_FLG_SMM__W 1 +#define HI_RA_RAM_SLV0_FLG_SMM__M 0x1 +#define HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 +#define HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 + + +#define HI_RA_RAM_SLV0_DEV_ID__A 0x420011 +#define HI_RA_RAM_SLV0_DEV_ID__W 7 +#define HI_RA_RAM_SLV0_DEV_ID__M 0x7F + +#define HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 +#define HI_RA_RAM_SLV0_FLG_CRC__W 1 +#define HI_RA_RAM_SLV0_FLG_CRC__M 0x1 +#define HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 +#define HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 + + +#define HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 +#define HI_RA_RAM_SLV0_FLG_ACC__W 3 +#define HI_RA_RAM_SLV0_FLG_ACC__M 0x7 +#define HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 +#define HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 +#define HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 +#define HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 +#define HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 +#define HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 +#define HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 +#define HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 +#define HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 +#define HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 + + +#define HI_RA_RAM_SLV0_STATE__A 0x420014 +#define HI_RA_RAM_SLV0_STATE__W 1 +#define HI_RA_RAM_SLV0_STATE__M 0x1 +#define HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 +#define HI_RA_RAM_SLV0_STATE_DATA 0x1 + + +#define HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 +#define HI_RA_RAM_SLV0_BLK_BNK__W 12 +#define HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF +#define HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 +#define HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 +#define HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F +#define HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 +#define HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 +#define HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 + + +#define HI_RA_RAM_SLV0_ADDR__A 0x420016 +#define HI_RA_RAM_SLV0_ADDR__W 16 +#define HI_RA_RAM_SLV0_ADDR__M 0xFFFF + +#define HI_RA_RAM_SLV0_CRC__A 0x420017 +#define HI_RA_RAM_SLV0_CRC__W 16 +#define HI_RA_RAM_SLV0_CRC__M 0xFFFF + +#define HI_RA_RAM_SLV0_READBACK__A 0x420018 +#define HI_RA_RAM_SLV0_READBACK__W 16 +#define HI_RA_RAM_SLV0_READBACK__M 0xFFFF + + + + +#define HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 +#define HI_RA_RAM_SLV1_FLG_SMM__W 1 +#define HI_RA_RAM_SLV1_FLG_SMM__M 0x1 +#define HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 +#define HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 + + +#define HI_RA_RAM_SLV1_DEV_ID__A 0x420021 +#define HI_RA_RAM_SLV1_DEV_ID__W 7 +#define HI_RA_RAM_SLV1_DEV_ID__M 0x7F + +#define HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 +#define HI_RA_RAM_SLV1_FLG_CRC__W 1 +#define HI_RA_RAM_SLV1_FLG_CRC__M 0x1 +#define HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 +#define HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 + + +#define HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 +#define HI_RA_RAM_SLV1_FLG_ACC__W 3 +#define HI_RA_RAM_SLV1_FLG_ACC__M 0x7 +#define HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 +#define HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 +#define HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 +#define HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 +#define HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 +#define HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 +#define HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 +#define HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 +#define HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 +#define HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 + + +#define HI_RA_RAM_SLV1_STATE__A 0x420024 +#define HI_RA_RAM_SLV1_STATE__W 1 +#define HI_RA_RAM_SLV1_STATE__M 0x1 +#define HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 +#define HI_RA_RAM_SLV1_STATE_DATA 0x1 + + +#define HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 +#define HI_RA_RAM_SLV1_BLK_BNK__W 12 +#define HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF +#define HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 +#define HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 +#define HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F +#define HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 +#define HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 +#define HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 + + +#define HI_RA_RAM_SLV1_ADDR__A 0x420026 +#define HI_RA_RAM_SLV1_ADDR__W 16 +#define HI_RA_RAM_SLV1_ADDR__M 0xFFFF + +#define HI_RA_RAM_SLV1_CRC__A 0x420027 +#define HI_RA_RAM_SLV1_CRC__W 16 +#define HI_RA_RAM_SLV1_CRC__M 0xFFFF + +#define HI_RA_RAM_SLV1_READBACK__A 0x420028 +#define HI_RA_RAM_SLV1_READBACK__W 16 +#define HI_RA_RAM_SLV1_READBACK__M 0xFFFF + + + + +#define HI_RA_RAM_SRV_SEM__A 0x420030 +#define HI_RA_RAM_SRV_SEM__W 1 +#define HI_RA_RAM_SRV_SEM__M 0x1 +#define HI_RA_RAM_SRV_SEM_FREE 0x0 +#define HI_RA_RAM_SRV_SEM_CLAIMED 0x1 + + +#define HI_RA_RAM_SRV_RES__A 0x420031 +#define HI_RA_RAM_SRV_RES__W 3 +#define HI_RA_RAM_SRV_RES__M 0x7 +#define HI_RA_RAM_SRV_RES_OK 0x0 +#define HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 +#define HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 +#define HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 +#define HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 + + +#define HI_RA_RAM_SRV_CMD__A 0x420032 +#define HI_RA_RAM_SRV_CMD__W 3 +#define HI_RA_RAM_SRV_CMD__M 0x7 +#define HI_RA_RAM_SRV_CMD_NULL 0x0 +#define HI_RA_RAM_SRV_CMD_UIO 0x1 +#define HI_RA_RAM_SRV_CMD_RESET 0x2 +#define HI_RA_RAM_SRV_CMD_CONFIG 0x3 +#define HI_RA_RAM_SRV_CMD_COPY 0x4 +#define HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 +#define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 + + +#define HI_RA_RAM_SRV_PAR__AX 0x420033 +#define HI_RA_RAM_SRV_PAR__XSZ 5 +#define HI_RA_RAM_SRV_PAR__W 16 +#define HI_RA_RAM_SRV_PAR__M 0xFFFF + + + +#define HI_RA_RAM_SRV_NOP_RES__A 0x420031 +#define HI_RA_RAM_SRV_NOP_RES__W 3 +#define HI_RA_RAM_SRV_NOP_RES__M 0x7 +#define HI_RA_RAM_SRV_NOP_RES_OK 0x0 +#define HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 + + + +#define HI_RA_RAM_SRV_UIO_RES__A 0x420031 +#define HI_RA_RAM_SRV_UIO_RES__W 3 +#define HI_RA_RAM_SRV_UIO_RES__M 0x7 +#define HI_RA_RAM_SRV_UIO_RES_LO 0x0 +#define HI_RA_RAM_SRV_UIO_RES_HI 0x1 + +#define HI_RA_RAM_SRV_UIO_KEY__A 0x420033 +#define HI_RA_RAM_SRV_UIO_KEY__W 16 +#define HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF +#define HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 + +#define HI_RA_RAM_SRV_UIO_SEL__A 0x420034 +#define HI_RA_RAM_SRV_UIO_SEL__W 2 +#define HI_RA_RAM_SRV_UIO_SEL__M 0x3 +#define HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 +#define HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 + +#define HI_RA_RAM_SRV_UIO_SET__A 0x420035 +#define HI_RA_RAM_SRV_UIO_SET__W 2 +#define HI_RA_RAM_SRV_UIO_SET__M 0x3 +#define HI_RA_RAM_SRV_UIO_SET_OUT__B 0 +#define HI_RA_RAM_SRV_UIO_SET_OUT__W 1 +#define HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 +#define HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 +#define HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 +#define HI_RA_RAM_SRV_UIO_SET_DIR__B 1 +#define HI_RA_RAM_SRV_UIO_SET_DIR__W 1 +#define HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 +#define HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 +#define HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 + + + +#define HI_RA_RAM_SRV_RST_RES__A 0x420031 +#define HI_RA_RAM_SRV_RST_RES__W 1 +#define HI_RA_RAM_SRV_RST_RES__M 0x1 +#define HI_RA_RAM_SRV_RST_RES_OK 0x0 +#define HI_RA_RAM_SRV_RST_RES_ERROR 0x1 + +#define HI_RA_RAM_SRV_RST_KEY__A 0x420033 +#define HI_RA_RAM_SRV_RST_KEY__W 16 +#define HI_RA_RAM_SRV_RST_KEY__M 0xFFFF +#define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 + + + +#define HI_RA_RAM_SRV_CFG_RES__A 0x420031 +#define HI_RA_RAM_SRV_CFG_RES__W 1 +#define HI_RA_RAM_SRV_CFG_RES__M 0x1 +#define HI_RA_RAM_SRV_CFG_RES_OK 0x0 +#define HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 + +#define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 +#define HI_RA_RAM_SRV_CFG_KEY__W 16 +#define HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF +#define HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 + + +#define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 +#define HI_RA_RAM_SRV_CFG_DIV__W 5 +#define HI_RA_RAM_SRV_CFG_DIV__M 0x1F + +#define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 +#define HI_RA_RAM_SRV_CFG_BDL__W 6 +#define HI_RA_RAM_SRV_CFG_BDL__M 0x3F + +#define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 +#define HI_RA_RAM_SRV_CFG_WUP__W 8 +#define HI_RA_RAM_SRV_CFG_WUP__M 0xFF + +#define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 +#define HI_RA_RAM_SRV_CFG_ACT__W 4 +#define HI_RA_RAM_SRV_CFG_ACT__M 0xF +#define HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 +#define HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 +#define HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 +#define HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 +#define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 +#define HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 +#define HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 +#define HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 +#define HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 +#define HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 +#define HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 +#define HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 +#define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 +#define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 +#define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 +#define HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 +#define HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 +#define HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 +#define HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 +#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 + + + +#define HI_RA_RAM_SRV_CPY_RES__A 0x420031 +#define HI_RA_RAM_SRV_CPY_RES__W 1 +#define HI_RA_RAM_SRV_CPY_RES__M 0x1 +#define HI_RA_RAM_SRV_CPY_RES_OK 0x0 +#define HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 + + +#define HI_RA_RAM_SRV_CPY_SBB__A 0x420033 +#define HI_RA_RAM_SRV_CPY_SBB__W 12 +#define HI_RA_RAM_SRV_CPY_SBB__M 0xFFF +#define HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 +#define HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 +#define HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F +#define HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 +#define HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 +#define HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 + + +#define HI_RA_RAM_SRV_CPY_SAD__A 0x420034 +#define HI_RA_RAM_SRV_CPY_SAD__W 16 +#define HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF + +#define HI_RA_RAM_SRV_CPY_LEN__A 0x420035 +#define HI_RA_RAM_SRV_CPY_LEN__W 16 +#define HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF + +#define HI_RA_RAM_SRV_CPY_DBB__A 0x420033 +#define HI_RA_RAM_SRV_CPY_DBB__W 12 +#define HI_RA_RAM_SRV_CPY_DBB__M 0xFFF +#define HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 +#define HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 +#define HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F +#define HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 +#define HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 +#define HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 + + +#define HI_RA_RAM_SRV_CPY_DAD__A 0x420034 +#define HI_RA_RAM_SRV_CPY_DAD__W 16 +#define HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF + + + +#define HI_RA_RAM_SRV_TRM_RES__A 0x420031 +#define HI_RA_RAM_SRV_TRM_RES__W 2 +#define HI_RA_RAM_SRV_TRM_RES__M 0x3 +#define HI_RA_RAM_SRV_TRM_RES_OK 0x0 +#define HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 +#define HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 + + +#define HI_RA_RAM_SRV_TRM_MST__A 0x420033 +#define HI_RA_RAM_SRV_TRM_MST__W 12 +#define HI_RA_RAM_SRV_TRM_MST__M 0xFFF + +#define HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 +#define HI_RA_RAM_SRV_TRM_SEQ__W 7 +#define HI_RA_RAM_SRV_TRM_SEQ__M 0x7F + +#define HI_RA_RAM_SRV_TRM_TRM__A 0x420035 +#define HI_RA_RAM_SRV_TRM_TRM__W 15 +#define HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF +#define HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 +#define HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 +#define HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF + + +#define HI_RA_RAM_SRV_TRM_DBB__A 0x420033 +#define HI_RA_RAM_SRV_TRM_DBB__W 12 +#define HI_RA_RAM_SRV_TRM_DBB__M 0xFFF +#define HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 +#define HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 +#define HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F +#define HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 +#define HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 +#define HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 + + +#define HI_RA_RAM_SRV_TRM_DAD__A 0x420034 +#define HI_RA_RAM_SRV_TRM_DAD__W 16 +#define HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF + + + + +#define HI_RA_RAM_USR_BEGIN__A 0x420040 +#define HI_RA_RAM_USR_BEGIN__W 16 +#define HI_RA_RAM_USR_BEGIN__M 0xFFFF + +#define HI_RA_RAM_USR_END__A 0x42007F +#define HI_RA_RAM_USR_END__W 16 +#define HI_RA_RAM_USR_END__M 0xFFFF + + + + + + +#define HI_IF_RAM_TRP_BPT0__AX 0x430000 +#define HI_IF_RAM_TRP_BPT0__XSZ 2 +#define HI_IF_RAM_TRP_BPT0__W 12 +#define HI_IF_RAM_TRP_BPT0__M 0xFFF + +#define HI_IF_RAM_TRP_STKU__AX 0x430002 +#define HI_IF_RAM_TRP_STKU__XSZ 2 +#define HI_IF_RAM_TRP_STKU__W 12 +#define HI_IF_RAM_TRP_STKU__M 0xFFF + + + + +#define HI_IF_RAM_USR_BEGIN__A 0x430200 +#define HI_IF_RAM_USR_BEGIN__W 12 +#define HI_IF_RAM_USR_BEGIN__M 0xFFF + +#define HI_IF_RAM_USR_END__A 0x4303FF +#define HI_IF_RAM_USR_END__W 12 +#define HI_IF_RAM_USR_END__M 0xFFF + + + + + +#define SC_SID 0x11 + + + + + +#define SC_COMM_EXEC__A 0x800000 +#define SC_COMM_EXEC__W 3 +#define SC_COMM_EXEC__M 0x7 +#define SC_COMM_EXEC_CTL__B 0 +#define SC_COMM_EXEC_CTL__W 3 +#define SC_COMM_EXEC_CTL__M 0x7 +#define SC_COMM_EXEC_CTL_STOP 0x0 +#define SC_COMM_EXEC_CTL_ACTIVE 0x1 +#define SC_COMM_EXEC_CTL_HOLD 0x2 +#define SC_COMM_EXEC_CTL_STEP 0x3 +#define SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define SC_COMM_STATE__A 0x800001 +#define SC_COMM_STATE__W 16 +#define SC_COMM_STATE__M 0xFFFF +#define SC_COMM_MB__A 0x800002 +#define SC_COMM_MB__W 16 +#define SC_COMM_MB__M 0xFFFF +#define SC_COMM_SERVICE0__A 0x800003 +#define SC_COMM_SERVICE0__W 16 +#define SC_COMM_SERVICE0__M 0xFFFF +#define SC_COMM_SERVICE1__A 0x800004 +#define SC_COMM_SERVICE1__W 16 +#define SC_COMM_SERVICE1__M 0xFFFF +#define SC_COMM_INT_STA__A 0x800007 +#define SC_COMM_INT_STA__W 16 +#define SC_COMM_INT_STA__M 0xFFFF +#define SC_COMM_INT_MSK__A 0x800008 +#define SC_COMM_INT_MSK__W 16 +#define SC_COMM_INT_MSK__M 0xFFFF + + + + + + +#define SC_CT_REG_COMM_EXEC__A 0x810000 +#define SC_CT_REG_COMM_EXEC__W 3 +#define SC_CT_REG_COMM_EXEC__M 0x7 +#define SC_CT_REG_COMM_EXEC_CTL__B 0 +#define SC_CT_REG_COMM_EXEC_CTL__W 3 +#define SC_CT_REG_COMM_EXEC_CTL__M 0x7 +#define SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define SC_CT_REG_COMM_STATE__A 0x810001 +#define SC_CT_REG_COMM_STATE__W 10 +#define SC_CT_REG_COMM_STATE__M 0x3FF +#define SC_CT_REG_COMM_SERVICE0__A 0x810003 +#define SC_CT_REG_COMM_SERVICE0__W 16 +#define SC_CT_REG_COMM_SERVICE0__M 0xFFFF +#define SC_CT_REG_COMM_SERVICE1__A 0x810004 +#define SC_CT_REG_COMM_SERVICE1__W 16 +#define SC_CT_REG_COMM_SERVICE1__M 0xFFFF +#define SC_CT_REG_COMM_SERVICE1_SC__B 1 +#define SC_CT_REG_COMM_SERVICE1_SC__W 1 +#define SC_CT_REG_COMM_SERVICE1_SC__M 0x2 + + +#define SC_CT_REG_COMM_INT_STA__A 0x810007 +#define SC_CT_REG_COMM_INT_STA__W 1 +#define SC_CT_REG_COMM_INT_STA__M 0x1 +#define SC_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define SC_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + + +#define SC_CT_REG_COMM_INT_MSK__A 0x810008 +#define SC_CT_REG_COMM_INT_MSK__W 1 +#define SC_CT_REG_COMM_INT_MSK__M 0x1 +#define SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + + + + +#define SC_CT_REG_CTL_STK__AX 0x810010 +#define SC_CT_REG_CTL_STK__XSZ 4 +#define SC_CT_REG_CTL_STK__W 10 +#define SC_CT_REG_CTL_STK__M 0x3FF + +#define SC_CT_REG_CTL_BPT_IDX__A 0x81001F +#define SC_CT_REG_CTL_BPT_IDX__W 1 +#define SC_CT_REG_CTL_BPT_IDX__M 0x1 + +#define SC_CT_REG_CTL_BPT__A 0x810020 +#define SC_CT_REG_CTL_BPT__W 10 +#define SC_CT_REG_CTL_BPT__M 0x3FF + + + + + +#define SC_RA_RAM_PARAM0__A 0x820040 +#define SC_RA_RAM_PARAM0__W 16 +#define SC_RA_RAM_PARAM0__M 0xFFFF +#define SC_RA_RAM_PARAM1__A 0x820041 +#define SC_RA_RAM_PARAM1__W 16 +#define SC_RA_RAM_PARAM1__M 0xFFFF +#define SC_RA_RAM_CMD_ADDR__A 0x820042 +#define SC_RA_RAM_CMD_ADDR__W 16 +#define SC_RA_RAM_CMD_ADDR__M 0xFFFF +#define SC_RA_RAM_CMD__A 0x820043 +#define SC_RA_RAM_CMD__W 16 +#define SC_RA_RAM_CMD__M 0xFFFF +#define SC_RA_RAM_CMD_NULL 0x0 +#define SC_RA_RAM_CMD_PROC_START 0x1 +#define SC_RA_RAM_CMD_PROC_TRIGGER 0x2 +#define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +#define SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 +#define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 +#define SC_RA_RAM_CMD_USER_IO 0x6 +#define SC_RA_RAM_CMD_SET_TIMER 0x7 +#define SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 +#define SC_RA_RAM_CMD_MAX 0x8 +#define SC_RA_RAM_CMDBLOCK__C 0x4 + +#define SC_RA_RAM_PROC_ACTIVATE__A 0x820044 +#define SC_RA_RAM_PROC_ACTIVATE__W 16 +#define SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF +#define SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF +#define SC_RA_RAM_PROC_TERMINATED__A 0x820045 +#define SC_RA_RAM_PROC_TERMINATED__W 16 +#define SC_RA_RAM_PROC_TERMINATED__M 0xFFFF +#define SC_RA_RAM_SW_EVENT__A 0x820046 +#define SC_RA_RAM_SW_EVENT__W 14 +#define SC_RA_RAM_SW_EVENT__M 0x3FFF +#define SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 +#define SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 +#define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 +#define SC_RA_RAM_SW_EVENT_RUN__B 1 +#define SC_RA_RAM_SW_EVENT_RUN__W 1 +#define SC_RA_RAM_SW_EVENT_RUN__M 0x2 +#define SC_RA_RAM_SW_EVENT_TERMINATE__B 2 +#define SC_RA_RAM_SW_EVENT_TERMINATE__W 1 +#define SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 +#define SC_RA_RAM_SW_EVENT_FT_START__B 3 +#define SC_RA_RAM_SW_EVENT_FT_START__W 1 +#define SC_RA_RAM_SW_EVENT_FT_START__M 0x8 +#define SC_RA_RAM_SW_EVENT_FI_START__B 4 +#define SC_RA_RAM_SW_EVENT_FI_START__W 1 +#define SC_RA_RAM_SW_EVENT_FI_START__M 0x10 +#define SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 +#define SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 +#define SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 +#define SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 +#define SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 +#define SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 +#define SC_RA_RAM_SW_EVENT_CE_IR__B 7 +#define SC_RA_RAM_SW_EVENT_CE_IR__W 1 +#define SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 +#define SC_RA_RAM_SW_EVENT_FE_FD__B 8 +#define SC_RA_RAM_SW_EVENT_FE_FD__W 1 +#define SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 +#define SC_RA_RAM_SW_EVENT_FE_CF__B 9 +#define SC_RA_RAM_SW_EVENT_FE_CF__W 1 +#define SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__B 10 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__W 1 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__M 0x400 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__B 11 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__W 1 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__M 0x800 + +#define SC_RA_RAM_LOCKTRACK__A 0x820047 +#define SC_RA_RAM_LOCKTRACK__W 16 +#define SC_RA_RAM_LOCKTRACK__M 0xFFFF +#define SC_RA_RAM_LOCKTRACK_NULL 0x0 +#define SC_RA_RAM_LOCKTRACK_MIN 0x1 +#define SC_RA_RAM_LOCKTRACK_RESET 0x1 +#define SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 +#define SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 +#define SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 +#define SC_RA_RAM_LOCKTRACK_P_DETECT_MIRROR 0x5 +#define SC_RA_RAM_LOCKTRACK_LC 0x6 +#define SC_RA_RAM_LOCKTRACK_P_ECHO 0x7 +#define SC_RA_RAM_LOCKTRACK_NE_INIT 0x8 +#define SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x9 +#define SC_RA_RAM_LOCKTRACK_TRACK 0xA +#define SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xB +#define SC_RA_RAM_LOCKTRACK_SR_SCANNING 0xC +#define SC_RA_RAM_LOCKTRACK_MAX 0xD + + + +#define SC_RA_RAM_OP_PARAM__A 0x820048 +#define SC_RA_RAM_OP_PARAM__W 13 +#define SC_RA_RAM_OP_PARAM__M 0x1FFF +#define SC_RA_RAM_OP_PARAM_MODE__B 0 +#define SC_RA_RAM_OP_PARAM_MODE__W 2 +#define SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +#define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +#define SC_RA_RAM_OP_PARAM_GUARD__B 2 +#define SC_RA_RAM_OP_PARAM_GUARD__W 2 +#define SC_RA_RAM_OP_PARAM_GUARD__M 0xC +#define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 +#define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 +#define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 +#define SC_RA_RAM_OP_PARAM_GUARD_4 0xC +#define SC_RA_RAM_OP_PARAM_CONST__B 4 +#define SC_RA_RAM_OP_PARAM_CONST__W 2 +#define SC_RA_RAM_OP_PARAM_CONST__M 0x30 +#define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 +#define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +#define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +#define SC_RA_RAM_OP_PARAM_HIER__B 6 +#define SC_RA_RAM_OP_PARAM_HIER__W 3 +#define SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 +#define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 +#define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 +#define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 +#define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 +#define SC_RA_RAM_OP_PARAM_RATE__B 9 +#define SC_RA_RAM_OP_PARAM_RATE__W 3 +#define SC_RA_RAM_OP_PARAM_RATE__M 0xE00 +#define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 +#define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 +#define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 +#define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 +#define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 +#define SC_RA_RAM_OP_PARAM_PRIO__B 12 +#define SC_RA_RAM_OP_PARAM_PRIO__W 1 +#define SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 +#define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 +#define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 + +#define SC_RA_RAM_OP_AUTO__A 0x820049 +#define SC_RA_RAM_OP_AUTO__W 6 +#define SC_RA_RAM_OP_AUTO__M 0x3F +#define SC_RA_RAM_OP_AUTO__PRE 0x1F +#define SC_RA_RAM_OP_AUTO_MODE__B 0 +#define SC_RA_RAM_OP_AUTO_MODE__W 1 +#define SC_RA_RAM_OP_AUTO_MODE__M 0x1 +#define SC_RA_RAM_OP_AUTO_GUARD__B 1 +#define SC_RA_RAM_OP_AUTO_GUARD__W 1 +#define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 +#define SC_RA_RAM_OP_AUTO_CONST__B 2 +#define SC_RA_RAM_OP_AUTO_CONST__W 1 +#define SC_RA_RAM_OP_AUTO_CONST__M 0x4 +#define SC_RA_RAM_OP_AUTO_HIER__B 3 +#define SC_RA_RAM_OP_AUTO_HIER__W 1 +#define SC_RA_RAM_OP_AUTO_HIER__M 0x8 +#define SC_RA_RAM_OP_AUTO_RATE__B 4 +#define SC_RA_RAM_OP_AUTO_RATE__W 1 +#define SC_RA_RAM_OP_AUTO_RATE__M 0x10 +#define SC_RA_RAM_OP_AUTO_PRIO__B 5 +#define SC_RA_RAM_OP_AUTO_PRIO__W 1 +#define SC_RA_RAM_OP_AUTO_PRIO__M 0x20 + +#define SC_RA_RAM_PILOT_STATUS__A 0x82004A +#define SC_RA_RAM_PILOT_STATUS__W 16 +#define SC_RA_RAM_PILOT_STATUS__M 0xFFFF +#define SC_RA_RAM_PILOT_STATUS_OK 0x0 +#define SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 +#define SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 + +#define SC_RA_RAM_LOCK__A 0x82004B +#define SC_RA_RAM_LOCK__W 4 +#define SC_RA_RAM_LOCK__M 0xF +#define SC_RA_RAM_LOCK_DEMOD__B 0 +#define SC_RA_RAM_LOCK_DEMOD__W 1 +#define SC_RA_RAM_LOCK_DEMOD__M 0x1 +#define SC_RA_RAM_LOCK_FEC__B 1 +#define SC_RA_RAM_LOCK_FEC__W 1 +#define SC_RA_RAM_LOCK_FEC__M 0x2 +#define SC_RA_RAM_LOCK_MPEG__B 2 +#define SC_RA_RAM_LOCK_MPEG__W 1 +#define SC_RA_RAM_LOCK_MPEG__M 0x4 +#define SC_RA_RAM_LOCK_NODVBT__B 3 +#define SC_RA_RAM_LOCK_NODVBT__W 1 +#define SC_RA_RAM_LOCK_NODVBT__M 0x8 + + + +#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C +#define SC_RA_RAM_BE_OPT_ENA__W 5 +#define SC_RA_RAM_BE_OPT_ENA__M 0x1F +#define SC_RA_RAM_BE_OPT_ENA__PRE 0x14 +#define SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 +#define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 +#define SC_RA_RAM_BE_OPT_ENA_COCHANNEL 0x2 +#define SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 +#define SC_RA_RAM_BE_OPT_ENA_MAX 0x5 + +#define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D +#define SC_RA_RAM_BE_OPT_DELAY__W 16 +#define SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF +#define SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 +#define SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E +#define SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 +#define SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF +#define SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 +#define SC_RA_RAM_ECHO_THRES__A 0x82004F +#define SC_RA_RAM_ECHO_THRES__W 16 +#define SC_RA_RAM_ECHO_THRES__M 0xFFFF +#define SC_RA_RAM_ECHO_THRES__PRE 0x2A +#define SC_RA_RAM_CONFIG__A 0x820050 +#define SC_RA_RAM_CONFIG__W 16 +#define SC_RA_RAM_CONFIG__M 0xFFFF +#define SC_RA_RAM_CONFIG__PRE 0x54 +#define SC_RA_RAM_CONFIG_ID__B 0 +#define SC_RA_RAM_CONFIG_ID__W 1 +#define SC_RA_RAM_CONFIG_ID__M 0x1 +#define SC_RA_RAM_CONFIG_ID_PRO 0x0 +#define SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 +#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 +#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 +#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 +#define SC_RA_RAM_CONFIG_FR_ENABLE__B 2 +#define SC_RA_RAM_CONFIG_FR_ENABLE__W 1 +#define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 +#define SC_RA_RAM_CONFIG_MIXMODE__B 3 +#define SC_RA_RAM_CONFIG_MIXMODE__W 1 +#define SC_RA_RAM_CONFIG_MIXMODE__M 0x8 +#define SC_RA_RAM_CONFIG_FREQSCAN__B 4 +#define SC_RA_RAM_CONFIG_FREQSCAN__W 1 +#define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 +#define SC_RA_RAM_CONFIG_SLAVE__B 5 +#define SC_RA_RAM_CONFIG_SLAVE__W 1 +#define SC_RA_RAM_CONFIG_SLAVE__M 0x20 +#define SC_RA_RAM_CONFIG_FAR_OFF__B 6 +#define SC_RA_RAM_CONFIG_FAR_OFF__W 1 +#define SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 +#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 +#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 +#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 +#define SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 +#define SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 +#define SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 +#define SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 +#define SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 +#define SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 + + + +#define SC_RA_RAM_PILOT_THRES_SPD__A 0x820051 +#define SC_RA_RAM_PILOT_THRES_SPD__W 16 +#define SC_RA_RAM_PILOT_THRES_SPD__M 0xFFFF +#define SC_RA_RAM_PILOT_THRES_SPD__PRE 0x4 +#define SC_RA_RAM_PILOT_THRES_CPD__A 0x820052 +#define SC_RA_RAM_PILOT_THRES_CPD__W 16 +#define SC_RA_RAM_PILOT_THRES_CPD__M 0xFFFF +#define SC_RA_RAM_PILOT_THRES_CPD__PRE 0x4 +#define SC_RA_RAM_PILOT_THRES_FREQSCAN__A 0x820053 +#define SC_RA_RAM_PILOT_THRES_FREQSCAN__W 16 +#define SC_RA_RAM_PILOT_THRES_FREQSCAN__M 0xFFFF +#define SC_RA_RAM_PILOT_THRES_FREQSCAN__PRE 0x406 + + + +#define SC_RA_RAM_CO_THRES_8K__A 0x820055 +#define SC_RA_RAM_CO_THRES_8K__W 16 +#define SC_RA_RAM_CO_THRES_8K__M 0xFFFF +#define SC_RA_RAM_CO_THRES_8K__PRE 0x10E +#define SC_RA_RAM_CO_THRES_2K__A 0x820056 +#define SC_RA_RAM_CO_THRES_2K__W 16 +#define SC_RA_RAM_CO_THRES_2K__M 0xFFFF +#define SC_RA_RAM_CO_THRES_2K__PRE 0x208 +#define SC_RA_RAM_CO_LEVEL__A 0x820057 +#define SC_RA_RAM_CO_LEVEL__W 16 +#define SC_RA_RAM_CO_LEVEL__M 0xFFFF +#define SC_RA_RAM_CO_DETECT__A 0x820058 +#define SC_RA_RAM_CO_DETECT__W 16 +#define SC_RA_RAM_CO_DETECT__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__A 0x820059 +#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__PRE 0xFFDB +#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__A 0x82005A +#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__PRE 0xFFEB +#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__A 0x82005B +#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__PRE 0xFFFB +#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__A 0x82005C +#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__PRE 0xFFDD +#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__A 0x82005D +#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__PRE 0xFFED +#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__A 0x82005E +#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__PRE 0xFFFD +#define SC_RA_RAM_MOTION_OFFSET__A 0x82005F +#define SC_RA_RAM_MOTION_OFFSET__W 16 +#define SC_RA_RAM_MOTION_OFFSET__M 0xFFFF +#define SC_RA_RAM_MOTION_OFFSET__PRE 0x2 +#define SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 +#define SC_RA_RAM_STATE_PROC_STOP__XSZ 12 +#define SC_RA_RAM_STATE_PROC_STOP__W 16 +#define SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF +#define SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE +#define SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 +#define SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_10__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_11__PRE 0xFFFE +#define SC_RA_RAM_STATE_PROC_STOP_12__PRE 0xFFFE +#define SC_RA_RAM_STATE_PROC_START__AX 0x820070 +#define SC_RA_RAM_STATE_PROC_START__XSZ 12 +#define SC_RA_RAM_STATE_PROC_START__W 16 +#define SC_RA_RAM_STATE_PROC_START__M 0xFFFF +#define SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 +#define SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 +#define SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 +#define SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 +#define SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 +#define SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_START_7__PRE 0x10 +#define SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_START_9__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_START_10__PRE 0x30 +#define SC_RA_RAM_STATE_PROC_START_11__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_START_12__PRE 0x0 +#define SC_RA_RAM_IF_SAVE__AX 0x82008E +#define SC_RA_RAM_IF_SAVE__XSZ 2 +#define SC_RA_RAM_IF_SAVE__W 16 +#define SC_RA_RAM_IF_SAVE__M 0xFFFF +#define SC_RA_RAM_FR_THRES__A 0x82007D +#define SC_RA_RAM_FR_THRES__W 16 +#define SC_RA_RAM_FR_THRES__M 0xFFFF +#define SC_RA_RAM_FR_THRES__PRE 0x1A2C +#define SC_RA_RAM_STATUS__A 0x82007E +#define SC_RA_RAM_STATUS__W 16 +#define SC_RA_RAM_STATUS__M 0xFFFF +#define SC_RA_RAM_NF_BORDER_INIT__A 0x82007F +#define SC_RA_RAM_NF_BORDER_INIT__W 16 +#define SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF +#define SC_RA_RAM_NF_BORDER_INIT__PRE 0x500 +#define SC_RA_RAM_TIMER__A 0x820080 +#define SC_RA_RAM_TIMER__W 16 +#define SC_RA_RAM_TIMER__M 0xFFFF +#define SC_RA_RAM_FI_OFFSET__A 0x820081 +#define SC_RA_RAM_FI_OFFSET__W 16 +#define SC_RA_RAM_FI_OFFSET__M 0xFFFF +#define SC_RA_RAM_FI_OFFSET__PRE 0x382 +#define SC_RA_RAM_ECHO_GUARD__A 0x820082 +#define SC_RA_RAM_ECHO_GUARD__W 16 +#define SC_RA_RAM_ECHO_GUARD__M 0xFFFF +#define SC_RA_RAM_ECHO_GUARD__PRE 0x18 + + + +#define SC_RA_RAM_IR_FREQ__A 0x8200D0 +#define SC_RA_RAM_IR_FREQ__W 16 +#define SC_RA_RAM_IR_FREQ__M 0xFFFF +#define SC_RA_RAM_IR_FREQ__PRE 0x0 + + + + + +#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 +#define SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 +#define SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 +#define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 +#define SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 +#define SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 +#define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 +#define SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 +#define SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 + + + +#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 +#define SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 +#define SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 +#define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 +#define SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 +#define SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 +#define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 +#define SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 +#define SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 + + + + + +#define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 +#define SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 +#define SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF +#define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 +#define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 +#define SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 +#define SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF +#define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 +#define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 +#define SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 +#define SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF +#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 + + + +#define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA +#define SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 +#define SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF +#define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB +#define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB +#define SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 +#define SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF +#define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 +#define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC +#define SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 +#define SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF +#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 + + + +#define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD +#define SC_RA_RAM_ECHO_SHIFT_LIM__W 16 +#define SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF +#define SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0xFFFF +#define SC_RA_RAM_ECHO_AGE__A 0x8200DE +#define SC_RA_RAM_ECHO_AGE__W 16 +#define SC_RA_RAM_ECHO_AGE__M 0xFFFF +#define SC_RA_RAM_ECHO_AGE__PRE 0xFFFF +#define SC_RA_RAM_ECHO_FILTER__A 0x8200DF +#define SC_RA_RAM_ECHO_FILTER__W 16 +#define SC_RA_RAM_ECHO_FILTER__M 0xFFFF +#define SC_RA_RAM_ECHO_FILTER__PRE 0x2 + + + + + +#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 +#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 +#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF +#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 +#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 +#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 +#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF +#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 +#define SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 +#define SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 +#define SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF +#define SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 + + + +#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 +#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 +#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF +#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE +#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 +#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 +#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF +#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 +#define SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 +#define SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 +#define SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF +#define SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 + + + +#define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 +#define SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 +#define SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF +#define SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x10 +#define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 +#define SC_RA_RAM_SAMPLE_RATE_STEP__W 16 +#define SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF +#define SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x113 + + + +#define SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA +#define SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 +#define SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF +#define SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 +#define SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB +#define SC_RA_RAM_TPS_TIMEOUT__W 16 +#define SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF +#define SC_RA_RAM_BAND__A 0x8200EC +#define SC_RA_RAM_BAND__W 16 +#define SC_RA_RAM_BAND__M 0xFFFF +#define SC_RA_RAM_BAND__PRE 0x0 +#define SC_RA_RAM_BAND_INTERVAL__B 0 +#define SC_RA_RAM_BAND_INTERVAL__W 4 +#define SC_RA_RAM_BAND_INTERVAL__M 0xF +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 + +#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED +#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 +#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF +#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 +#define SC_RA_RAM_REG__AX 0x8200F0 +#define SC_RA_RAM_REG__XSZ 2 +#define SC_RA_RAM_REG__W 16 +#define SC_RA_RAM_REG__M 0xFFFF +#define SC_RA_RAM_BREAK__A 0x8200F2 +#define SC_RA_RAM_BREAK__W 16 +#define SC_RA_RAM_BREAK__M 0xFFFF +#define SC_RA_RAM_BOOTCOUNT__A 0x8200F3 +#define SC_RA_RAM_BOOTCOUNT__W 16 +#define SC_RA_RAM_BOOTCOUNT__M 0xFFFF + + + +#define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 +#define SC_RA_RAM_LC_ABS_2K__W 16 +#define SC_RA_RAM_LC_ABS_2K__M 0xFFFF +#define SC_RA_RAM_LC_ABS_2K__PRE 0x1F +#define SC_RA_RAM_LC_ABS_8K__A 0x8200F5 +#define SC_RA_RAM_LC_ABS_8K__W 16 +#define SC_RA_RAM_LC_ABS_8K__M 0xFFFF +#define SC_RA_RAM_LC_ABS_8K__PRE 0x1F + + + + + +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__A 0x8200F6 +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__W 16 +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__M 0xFFFF +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__PRE 0x1 +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__A 0x8200F7 +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__W 16 +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__M 0xFFFF +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__PRE 0x0 + + + +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__A 0x8200F8 +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__W 16 +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__M 0xFFFF +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__PRE 0x3 +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__A 0x8200F9 +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__W 16 +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__M 0xFFFF +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__PRE 0x2 +#define SC_RA_RAM_RELOCK__A 0x8200FE +#define SC_RA_RAM_RELOCK__W 16 +#define SC_RA_RAM_RELOCK__M 0xFFFF +#define SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF +#define SC_RA_RAM_STACKUNDERFLOW__W 16 +#define SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF + + + +#define SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 +#define SC_RA_RAM_NF_MAXECHOTOKEN__W 16 +#define SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF +#define SC_RA_RAM_NF_PREPOST__A 0x820149 +#define SC_RA_RAM_NF_PREPOST__W 16 +#define SC_RA_RAM_NF_PREPOST__M 0xFFFF +#define SC_RA_RAM_NF_PREBORDER__A 0x82014A +#define SC_RA_RAM_NF_PREBORDER__W 16 +#define SC_RA_RAM_NF_PREBORDER__M 0xFFFF +#define SC_RA_RAM_NF_START__A 0x82014B +#define SC_RA_RAM_NF_START__W 16 +#define SC_RA_RAM_NF_START__M 0xFFFF +#define SC_RA_RAM_NF_MINISI__AX 0x82014C +#define SC_RA_RAM_NF_MINISI__XSZ 2 +#define SC_RA_RAM_NF_MINISI__W 16 +#define SC_RA_RAM_NF_MINISI__M 0xFFFF +#define SC_RA_RAM_NF_MAXECHO__A 0x82014E +#define SC_RA_RAM_NF_MAXECHO__W 16 +#define SC_RA_RAM_NF_MAXECHO__M 0xFFFF +#define SC_RA_RAM_NF_NRECHOES__A 0x82014F +#define SC_RA_RAM_NF_NRECHOES__W 16 +#define SC_RA_RAM_NF_NRECHOES__M 0xFFFF +#define SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 +#define SC_RA_RAM_NF_ECHOTABLE__XSZ 16 +#define SC_RA_RAM_NF_ECHOTABLE__W 16 +#define SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF + + + + + +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6 +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 + + + +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 + + + +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 + + + +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 + + + +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 + + + +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 + + + +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 + + + +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5 +#define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE +#define SC_RA_RAM_DRIVER_VERSION__XSZ 2 +#define SC_RA_RAM_DRIVER_VERSION__W 16 +#define SC_RA_RAM_DRIVER_VERSION__M 0xFFFF +#define SC_RA_RAM_EVENT0_MIN 0x7 +#define SC_RA_RAM_EVENT0_FE_CU 0x7 +#define SC_RA_RAM_EVENT0_CE 0xA +#define SC_RA_RAM_EVENT0_EQ 0xE +#define SC_RA_RAM_EVENT0_MAX 0xF +#define SC_RA_RAM_EVENT1_MIN 0x8 +#define SC_RA_RAM_EVENT1_EC_OD 0x8 +#define SC_RA_RAM_EVENT1_LC 0xC +#define SC_RA_RAM_EVENT1_MAX 0xD +#define SC_RA_RAM_PROC_LOCKTRACK 0x0 +#define SC_RA_RAM_PROC_MODE_GUARD 0x1 +#define SC_RA_RAM_PROC_PILOTS 0x2 +#define SC_RA_RAM_PROC_FESTART_ADJUST 0x3 +#define SC_RA_RAM_PROC_ECHO 0x4 +#define SC_RA_RAM_PROC_BE_OPT 0x5 +#define SC_RA_RAM_PROC_EQ 0x7 +#define SC_RA_RAM_PROC_MAX 0x8 + + + + + + +#define SC_IF_RAM_TRP_RST__AX 0x830000 +#define SC_IF_RAM_TRP_RST__XSZ 2 +#define SC_IF_RAM_TRP_RST__W 12 +#define SC_IF_RAM_TRP_RST__M 0xFFF + +#define SC_IF_RAM_TRP_BPT0__AX 0x830002 +#define SC_IF_RAM_TRP_BPT0__XSZ 2 +#define SC_IF_RAM_TRP_BPT0__W 12 +#define SC_IF_RAM_TRP_BPT0__M 0xFFF + +#define SC_IF_RAM_TRP_STKU__AX 0x830004 +#define SC_IF_RAM_TRP_STKU__XSZ 2 +#define SC_IF_RAM_TRP_STKU__W 12 +#define SC_IF_RAM_TRP_STKU__M 0xFFF + + + + +#define SC_IF_RAM_VERSION_MA_MI__A 0x830FFE +#define SC_IF_RAM_VERSION_MA_MI__W 12 +#define SC_IF_RAM_VERSION_MA_MI__M 0xFFF + +#define SC_IF_RAM_VERSION_PATCH__A 0x830FFF +#define SC_IF_RAM_VERSION_PATCH__W 12 +#define SC_IF_RAM_VERSION_PATCH__M 0xFFF + + + + + + + + + +#define FE_COMM_EXEC__A 0xC00000 +#define FE_COMM_EXEC__W 3 +#define FE_COMM_EXEC__M 0x7 +#define FE_COMM_EXEC_CTL__B 0 +#define FE_COMM_EXEC_CTL__W 3 +#define FE_COMM_EXEC_CTL__M 0x7 +#define FE_COMM_EXEC_CTL_STOP 0x0 +#define FE_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_COMM_EXEC_CTL_HOLD 0x2 +#define FE_COMM_EXEC_CTL_STEP 0x3 +#define FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define FE_COMM_STATE__A 0xC00001 +#define FE_COMM_STATE__W 16 +#define FE_COMM_STATE__M 0xFFFF +#define FE_COMM_MB__A 0xC00002 +#define FE_COMM_MB__W 16 +#define FE_COMM_MB__M 0xFFFF +#define FE_COMM_SERVICE0__A 0xC00003 +#define FE_COMM_SERVICE0__W 16 +#define FE_COMM_SERVICE0__M 0xFFFF +#define FE_COMM_SERVICE1__A 0xC00004 +#define FE_COMM_SERVICE1__W 16 +#define FE_COMM_SERVICE1__M 0xFFFF +#define FE_COMM_INT_STA__A 0xC00007 +#define FE_COMM_INT_STA__W 16 +#define FE_COMM_INT_STA__M 0xFFFF +#define FE_COMM_INT_MSK__A 0xC00008 +#define FE_COMM_INT_MSK__W 16 +#define FE_COMM_INT_MSK__M 0xFFFF + + + + + +#define FE_AD_SID 0x1 + + + + + + +#define FE_AD_REG_COMM_EXEC__A 0xC10000 +#define FE_AD_REG_COMM_EXEC__W 3 +#define FE_AD_REG_COMM_EXEC__M 0x7 +#define FE_AD_REG_COMM_EXEC_CTL__B 0 +#define FE_AD_REG_COMM_EXEC_CTL__W 3 +#define FE_AD_REG_COMM_EXEC_CTL__M 0x7 +#define FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define FE_AD_REG_COMM_MB__A 0xC10002 +#define FE_AD_REG_COMM_MB__W 2 +#define FE_AD_REG_COMM_MB__M 0x3 +#define FE_AD_REG_COMM_MB_CTR__B 0 +#define FE_AD_REG_COMM_MB_CTR__W 1 +#define FE_AD_REG_COMM_MB_CTR__M 0x1 +#define FE_AD_REG_COMM_MB_CTR_OFF 0x0 +#define FE_AD_REG_COMM_MB_CTR_ON 0x1 +#define FE_AD_REG_COMM_MB_OBS__B 1 +#define FE_AD_REG_COMM_MB_OBS__W 1 +#define FE_AD_REG_COMM_MB_OBS__M 0x2 +#define FE_AD_REG_COMM_MB_OBS_OFF 0x0 +#define FE_AD_REG_COMM_MB_OBS_ON 0x2 + +#define FE_AD_REG_COMM_SERVICE0__A 0xC10003 +#define FE_AD_REG_COMM_SERVICE0__W 10 +#define FE_AD_REG_COMM_SERVICE0__M 0x3FF +#define FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 +#define FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 +#define FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 + +#define FE_AD_REG_COMM_SERVICE1__A 0xC10004 +#define FE_AD_REG_COMM_SERVICE1__W 11 +#define FE_AD_REG_COMM_SERVICE1__M 0x7FF + +#define FE_AD_REG_COMM_INT_STA__A 0xC10007 +#define FE_AD_REG_COMM_INT_STA__W 2 +#define FE_AD_REG_COMM_INT_STA__M 0x3 +#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 +#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 +#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 + + +#define FE_AD_REG_COMM_INT_MSK__A 0xC10008 +#define FE_AD_REG_COMM_INT_MSK__W 2 +#define FE_AD_REG_COMM_INT_MSK__M 0x3 +#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 +#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 +#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 + + +#define FE_AD_REG_CUR_SEL__A 0xC10010 +#define FE_AD_REG_CUR_SEL__W 2 +#define FE_AD_REG_CUR_SEL__M 0x3 +#define FE_AD_REG_CUR_SEL_INIT 0x2 + + +#define FE_AD_REG_OVERFLOW__A 0xC10011 +#define FE_AD_REG_OVERFLOW__W 1 +#define FE_AD_REG_OVERFLOW__M 0x1 +#define FE_AD_REG_OVERFLOW_INIT 0x0 + + +#define FE_AD_REG_FDB_IN__A 0xC10012 +#define FE_AD_REG_FDB_IN__W 1 +#define FE_AD_REG_FDB_IN__M 0x1 +#define FE_AD_REG_FDB_IN_INIT 0x0 + + +#define FE_AD_REG_PD__A 0xC10013 +#define FE_AD_REG_PD__W 1 +#define FE_AD_REG_PD__M 0x1 +#define FE_AD_REG_PD_INIT 0x1 + + +#define FE_AD_REG_INVEXT__A 0xC10014 +#define FE_AD_REG_INVEXT__W 1 +#define FE_AD_REG_INVEXT__M 0x1 +#define FE_AD_REG_INVEXT_INIT 0x0 + + +#define FE_AD_REG_CLKNEG__A 0xC10015 +#define FE_AD_REG_CLKNEG__W 1 +#define FE_AD_REG_CLKNEG__M 0x1 +#define FE_AD_REG_CLKNEG_INIT 0x0 + + +#define FE_AD_REG_MON_IN_MUX__A 0xC10016 +#define FE_AD_REG_MON_IN_MUX__W 2 +#define FE_AD_REG_MON_IN_MUX__M 0x3 +#define FE_AD_REG_MON_IN_MUX_INIT 0x0 + + +#define FE_AD_REG_MON_IN5__A 0xC10017 +#define FE_AD_REG_MON_IN5__W 10 +#define FE_AD_REG_MON_IN5__M 0x3FF +#define FE_AD_REG_MON_IN5_INIT 0x0 + + +#define FE_AD_REG_MON_IN4__A 0xC10018 +#define FE_AD_REG_MON_IN4__W 10 +#define FE_AD_REG_MON_IN4__M 0x3FF +#define FE_AD_REG_MON_IN4_INIT 0x0 + + +#define FE_AD_REG_MON_IN3__A 0xC10019 +#define FE_AD_REG_MON_IN3__W 10 +#define FE_AD_REG_MON_IN3__M 0x3FF +#define FE_AD_REG_MON_IN3_INIT 0x0 + + +#define FE_AD_REG_MON_IN2__A 0xC1001A +#define FE_AD_REG_MON_IN2__W 10 +#define FE_AD_REG_MON_IN2__M 0x3FF +#define FE_AD_REG_MON_IN2_INIT 0x0 + + +#define FE_AD_REG_MON_IN1__A 0xC1001B +#define FE_AD_REG_MON_IN1__W 10 +#define FE_AD_REG_MON_IN1__M 0x3FF +#define FE_AD_REG_MON_IN1_INIT 0x0 + + +#define FE_AD_REG_MON_IN0__A 0xC1001C +#define FE_AD_REG_MON_IN0__W 10 +#define FE_AD_REG_MON_IN0__M 0x3FF +#define FE_AD_REG_MON_IN0_INIT 0x0 + + +#define FE_AD_REG_MON_IN_VAL__A 0xC1001D +#define FE_AD_REG_MON_IN_VAL__W 1 +#define FE_AD_REG_MON_IN_VAL__M 0x1 +#define FE_AD_REG_MON_IN_VAL_INIT 0x0 + + +#define FE_AD_REG_CTR_CLK_O__A 0xC1001E +#define FE_AD_REG_CTR_CLK_O__W 1 +#define FE_AD_REG_CTR_CLK_O__M 0x1 +#define FE_AD_REG_CTR_CLK_O_INIT 0x0 + + +#define FE_AD_REG_CTR_CLK_E_O__A 0xC1001F +#define FE_AD_REG_CTR_CLK_E_O__W 1 +#define FE_AD_REG_CTR_CLK_E_O__M 0x1 +#define FE_AD_REG_CTR_CLK_E_O_INIT 0x1 + + +#define FE_AD_REG_CTR_VAL_O__A 0xC10020 +#define FE_AD_REG_CTR_VAL_O__W 1 +#define FE_AD_REG_CTR_VAL_O__M 0x1 +#define FE_AD_REG_CTR_VAL_O_INIT 0x0 + + +#define FE_AD_REG_CTR_VAL_E_O__A 0xC10021 +#define FE_AD_REG_CTR_VAL_E_O__W 1 +#define FE_AD_REG_CTR_VAL_E_O__M 0x1 +#define FE_AD_REG_CTR_VAL_E_O_INIT 0x1 + + +#define FE_AD_REG_CTR_DATA_O__A 0xC10022 +#define FE_AD_REG_CTR_DATA_O__W 10 +#define FE_AD_REG_CTR_DATA_O__M 0x3FF +#define FE_AD_REG_CTR_DATA_O_INIT 0x0 + + +#define FE_AD_REG_CTR_DATA_E_O__A 0xC10023 +#define FE_AD_REG_CTR_DATA_E_O__W 10 +#define FE_AD_REG_CTR_DATA_E_O__M 0x3FF +#define FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF + + + + + +#define FE_AG_SID 0x2 + + + + + + +#define FE_AG_REG_COMM_EXEC__A 0xC20000 +#define FE_AG_REG_COMM_EXEC__W 3 +#define FE_AG_REG_COMM_EXEC__M 0x7 +#define FE_AG_REG_COMM_EXEC_CTL__B 0 +#define FE_AG_REG_COMM_EXEC_CTL__W 3 +#define FE_AG_REG_COMM_EXEC_CTL__M 0x7 +#define FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 + +#define FE_AG_REG_COMM_STATE__A 0xC20001 +#define FE_AG_REG_COMM_STATE__W 4 +#define FE_AG_REG_COMM_STATE__M 0xF + +#define FE_AG_REG_COMM_MB__A 0xC20002 +#define FE_AG_REG_COMM_MB__W 2 +#define FE_AG_REG_COMM_MB__M 0x3 +#define FE_AG_REG_COMM_MB_CTR__B 0 +#define FE_AG_REG_COMM_MB_CTR__W 1 +#define FE_AG_REG_COMM_MB_CTR__M 0x1 +#define FE_AG_REG_COMM_MB_CTR_OFF 0x0 +#define FE_AG_REG_COMM_MB_CTR_ON 0x1 +#define FE_AG_REG_COMM_MB_OBS__B 1 +#define FE_AG_REG_COMM_MB_OBS__W 1 +#define FE_AG_REG_COMM_MB_OBS__M 0x2 +#define FE_AG_REG_COMM_MB_OBS_OFF 0x0 +#define FE_AG_REG_COMM_MB_OBS_ON 0x2 + + +#define FE_AG_REG_COMM_SERVICE0__A 0xC20003 +#define FE_AG_REG_COMM_SERVICE0__W 10 +#define FE_AG_REG_COMM_SERVICE0__M 0x3FF + +#define FE_AG_REG_COMM_SERVICE1__A 0xC20004 +#define FE_AG_REG_COMM_SERVICE1__W 11 +#define FE_AG_REG_COMM_SERVICE1__M 0x7FF + +#define FE_AG_REG_COMM_INT_STA__A 0xC20007 +#define FE_AG_REG_COMM_INT_STA__W 8 +#define FE_AG_REG_COMM_INT_STA__M 0xFF +#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 +#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 +#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 +#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 +#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 +#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 +#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 +#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 +#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 +#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 +#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 +#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 +#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__B 6 +#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__M 0x40 +#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 +#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 + + +#define FE_AG_REG_COMM_INT_MSK__A 0xC20008 +#define FE_AG_REG_COMM_INT_MSK__W 8 +#define FE_AG_REG_COMM_INT_MSK__M 0xFF +#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 +#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 +#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 +#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 +#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 +#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 +#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 +#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 +#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 +#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 +#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 +#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 +#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__B 6 +#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__M 0x40 +#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 +#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 + + +#define FE_AG_REG_AG_MODE_LOP__A 0xC20010 +#define FE_AG_REG_AG_MODE_LOP__W 16 +#define FE_AG_REG_AG_MODE_LOP__M 0xFFFF +#define FE_AG_REG_AG_MODE_LOP_INIT 0x0 + +#define FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 +#define FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 +#define FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 + +#define FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 +#define FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 + +#define FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 +#define FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 +#define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 + +#define FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 +#define FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 +#define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 + +#define FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 +#define FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 +#define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 + +#define FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 +#define FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 +#define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 + +#define FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 +#define FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 +#define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 + +#define FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 +#define FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 +#define FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 + +#define FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 +#define FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 +#define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 + +#define FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 +#define FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 +#define FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 + +#define FE_AG_REG_AG_MODE_LOP_MODE_A__B 10 +#define FE_AG_REG_AG_MODE_LOP_MODE_A__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_A__M 0x400 +#define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_B 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_CB 0x400 + +#define FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 +#define FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 +#define FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 + +#define FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 +#define FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 +#define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 + +#define FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 +#define FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 +#define FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 + +#define FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 +#define FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 +#define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 + +#define FE_AG_REG_AG_MODE_LOP_MODE_F__B 15 +#define FE_AG_REG_AG_MODE_LOP_MODE_F__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_F__M 0x8000 +#define FE_AG_REG_AG_MODE_LOP_MODE_F_DISABLE 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_F_ENABLE 0x8000 + + +#define FE_AG_REG_AG_MODE_HIP__A 0xC20011 +#define FE_AG_REG_AG_MODE_HIP__W 2 +#define FE_AG_REG_AG_MODE_HIP__M 0x3 +#define FE_AG_REG_AG_MODE_HIP_INIT 0x0 + +#define FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 +#define FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 +#define FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 +#define FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 +#define FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 + +#define FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 +#define FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 +#define FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 +#define FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 +#define FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 + + +#define FE_AG_REG_AG_PGA_MODE__A 0xC20012 +#define FE_AG_REG_AG_PGA_MODE__W 3 +#define FE_AG_REG_AG_PGA_MODE__M 0x7 +#define FE_AG_REG_AG_PGA_MODE_INIT 0x0 +#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 +#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 + + +#define FE_AG_REG_AG_AGC_SIO__A 0xC20013 +#define FE_AG_REG_AG_AGC_SIO__W 2 +#define FE_AG_REG_AG_AGC_SIO__M 0x3 +#define FE_AG_REG_AG_AGC_SIO_INIT 0x3 + +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 + +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 + + +#define FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 +#define FE_AG_REG_AG_AGC_USR_DAT__W 2 +#define FE_AG_REG_AG_AGC_USR_DAT__M 0x3 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 + + +#define FE_AG_REG_AG_PWD__A 0xC20015 +#define FE_AG_REG_AG_PWD__W 5 +#define FE_AG_REG_AG_PWD__M 0x1F +#define FE_AG_REG_AG_PWD_INIT 0x1F + +#define FE_AG_REG_AG_PWD_PWD_PD1__B 0 +#define FE_AG_REG_AG_PWD_PWD_PD1__W 1 +#define FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 +#define FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 +#define FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 + +#define FE_AG_REG_AG_PWD_PWD_PD2__B 1 +#define FE_AG_REG_AG_PWD_PWD_PD2__W 1 +#define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 +#define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 +#define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 + +#define FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 +#define FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 +#define FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 +#define FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 +#define FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 + +#define FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 +#define FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 +#define FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 +#define FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 +#define FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 + +#define FE_AG_REG_AG_PWD_PWD_AAF__B 4 +#define FE_AG_REG_AG_PWD_PWD_AAF__W 1 +#define FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 +#define FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 +#define FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 + + +#define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 +#define FE_AG_REG_DCE_AUR_CNT__W 5 +#define FE_AG_REG_DCE_AUR_CNT__M 0x1F +#define FE_AG_REG_DCE_AUR_CNT_INIT 0x0 + + +#define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 +#define FE_AG_REG_DCE_RUR_CNT__W 5 +#define FE_AG_REG_DCE_RUR_CNT__M 0x1F +#define FE_AG_REG_DCE_RUR_CNT_INIT 0x0 + + +#define FE_AG_REG_DCE_AVE_DAT__A 0xC20018 +#define FE_AG_REG_DCE_AVE_DAT__W 10 +#define FE_AG_REG_DCE_AVE_DAT__M 0x3FF + +#define FE_AG_REG_DEC_AVE_WRI__A 0xC20019 +#define FE_AG_REG_DEC_AVE_WRI__W 10 +#define FE_AG_REG_DEC_AVE_WRI__M 0x3FF +#define FE_AG_REG_DEC_AVE_WRI_INIT 0x0 + + +#define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A +#define FE_AG_REG_ACE_AUR_CNT__W 5 +#define FE_AG_REG_ACE_AUR_CNT__M 0x1F +#define FE_AG_REG_ACE_AUR_CNT_INIT 0x0 + + +#define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B +#define FE_AG_REG_ACE_RUR_CNT__W 5 +#define FE_AG_REG_ACE_RUR_CNT__M 0x1F +#define FE_AG_REG_ACE_RUR_CNT_INIT 0x0 + + +#define FE_AG_REG_ACE_AVE_DAT__A 0xC2001C +#define FE_AG_REG_ACE_AVE_DAT__W 10 +#define FE_AG_REG_ACE_AVE_DAT__M 0x3FF + +#define FE_AG_REG_AEC_AVE_INC__A 0xC2001D +#define FE_AG_REG_AEC_AVE_INC__W 10 +#define FE_AG_REG_AEC_AVE_INC__M 0x3FF +#define FE_AG_REG_AEC_AVE_INC_INIT 0x0 + + +#define FE_AG_REG_AEC_AVE_DAT__A 0xC2001E +#define FE_AG_REG_AEC_AVE_DAT__W 10 +#define FE_AG_REG_AEC_AVE_DAT__M 0x3FF + +#define FE_AG_REG_AEC_CLP_LVL__A 0xC2001F +#define FE_AG_REG_AEC_CLP_LVL__W 16 +#define FE_AG_REG_AEC_CLP_LVL__M 0xFFFF +#define FE_AG_REG_AEC_CLP_LVL_INIT 0x0 + + +#define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 +#define FE_AG_REG_CDR_RUR_CNT__W 5 +#define FE_AG_REG_CDR_RUR_CNT__M 0x1F +#define FE_AG_REG_CDR_RUR_CNT_INIT 0x0 + + +#define FE_AG_REG_CDR_CLP_DAT__A 0xC20021 +#define FE_AG_REG_CDR_CLP_DAT__W 16 +#define FE_AG_REG_CDR_CLP_DAT__M 0xFFFF + +#define FE_AG_REG_CDR_CLP_POS__A 0xC20022 +#define FE_AG_REG_CDR_CLP_POS__W 10 +#define FE_AG_REG_CDR_CLP_POS__M 0x3FF +#define FE_AG_REG_CDR_CLP_POS_INIT 0x0 + + +#define FE_AG_REG_CDR_CLP_NEG__A 0xC20023 +#define FE_AG_REG_CDR_CLP_NEG__W 10 +#define FE_AG_REG_CDR_CLP_NEG__M 0x3FF +#define FE_AG_REG_CDR_CLP_NEG_INIT 0x0 + + +#define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 +#define FE_AG_REG_EGC_RUR_CNT__W 5 +#define FE_AG_REG_EGC_RUR_CNT__M 0x1F +#define FE_AG_REG_EGC_RUR_CNT_INIT 0x0 + + +#define FE_AG_REG_EGC_SET_LVL__A 0xC20025 +#define FE_AG_REG_EGC_SET_LVL__W 9 +#define FE_AG_REG_EGC_SET_LVL__M 0x1FF +#define FE_AG_REG_EGC_SET_LVL_INIT 0x0 + + +#define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 +#define FE_AG_REG_EGC_FLA_RGN__W 9 +#define FE_AG_REG_EGC_FLA_RGN__M 0x1FF +#define FE_AG_REG_EGC_FLA_RGN_INIT 0x0 + + +#define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 +#define FE_AG_REG_EGC_SLO_RGN__W 9 +#define FE_AG_REG_EGC_SLO_RGN__M 0x1FF +#define FE_AG_REG_EGC_SLO_RGN_INIT 0x0 + + +#define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 +#define FE_AG_REG_EGC_JMP_PSN__W 4 +#define FE_AG_REG_EGC_JMP_PSN__M 0xF +#define FE_AG_REG_EGC_JMP_PSN_INIT 0x0 + + +#define FE_AG_REG_EGC_FLA_INC__A 0xC20029 +#define FE_AG_REG_EGC_FLA_INC__W 16 +#define FE_AG_REG_EGC_FLA_INC__M 0xFFFF +#define FE_AG_REG_EGC_FLA_INC_INIT 0x0 + + +#define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A +#define FE_AG_REG_EGC_FLA_DEC__W 16 +#define FE_AG_REG_EGC_FLA_DEC__M 0xFFFF +#define FE_AG_REG_EGC_FLA_DEC_INIT 0x0 + + +#define FE_AG_REG_EGC_SLO_INC__A 0xC2002B +#define FE_AG_REG_EGC_SLO_INC__W 16 +#define FE_AG_REG_EGC_SLO_INC__M 0xFFFF +#define FE_AG_REG_EGC_SLO_INC_INIT 0x0 + + +#define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C +#define FE_AG_REG_EGC_SLO_DEC__W 16 +#define FE_AG_REG_EGC_SLO_DEC__M 0xFFFF +#define FE_AG_REG_EGC_SLO_DEC_INIT 0x0 + + +#define FE_AG_REG_EGC_FAS_INC__A 0xC2002D +#define FE_AG_REG_EGC_FAS_INC__W 16 +#define FE_AG_REG_EGC_FAS_INC__M 0xFFFF +#define FE_AG_REG_EGC_FAS_INC_INIT 0x0 + + +#define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E +#define FE_AG_REG_EGC_FAS_DEC__W 16 +#define FE_AG_REG_EGC_FAS_DEC__M 0xFFFF +#define FE_AG_REG_EGC_FAS_DEC_INIT 0x0 + + +#define FE_AG_REG_EGC_MAP_DAT__A 0xC2002F +#define FE_AG_REG_EGC_MAP_DAT__W 16 +#define FE_AG_REG_EGC_MAP_DAT__M 0xFFFF + +#define FE_AG_REG_PM1_AGC_WRI__A 0xC20030 +#define FE_AG_REG_PM1_AGC_WRI__W 11 +#define FE_AG_REG_PM1_AGC_WRI__M 0x7FF +#define FE_AG_REG_PM1_AGC_WRI_INIT 0x0 + + +#define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 +#define FE_AG_REG_GC1_AGC_RIC__W 16 +#define FE_AG_REG_GC1_AGC_RIC__M 0xFFFF +#define FE_AG_REG_GC1_AGC_RIC_INIT 0x0 + + +#define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 +#define FE_AG_REG_GC1_AGC_OFF__W 16 +#define FE_AG_REG_GC1_AGC_OFF__M 0xFFFF +#define FE_AG_REG_GC1_AGC_OFF_INIT 0x0 + + +#define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 +#define FE_AG_REG_GC1_AGC_MAX__W 10 +#define FE_AG_REG_GC1_AGC_MAX__M 0x3FF +#define FE_AG_REG_GC1_AGC_MAX_INIT 0x0 + + +#define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 +#define FE_AG_REG_GC1_AGC_MIN__W 10 +#define FE_AG_REG_GC1_AGC_MIN__M 0x3FF +#define FE_AG_REG_GC1_AGC_MIN_INIT 0x0 + + +#define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 +#define FE_AG_REG_GC1_AGC_DAT__W 10 +#define FE_AG_REG_GC1_AGC_DAT__M 0x3FF + +#define FE_AG_REG_PM2_AGC_WRI__A 0xC20036 +#define FE_AG_REG_PM2_AGC_WRI__W 11 +#define FE_AG_REG_PM2_AGC_WRI__M 0x7FF +#define FE_AG_REG_PM2_AGC_WRI_INIT 0x0 + + +#define FE_AG_REG_GC2_AGC_RIC__A 0xC20037 +#define FE_AG_REG_GC2_AGC_RIC__W 16 +#define FE_AG_REG_GC2_AGC_RIC__M 0xFFFF +#define FE_AG_REG_GC2_AGC_RIC_INIT 0x0 + + +#define FE_AG_REG_GC2_AGC_OFF__A 0xC20038 +#define FE_AG_REG_GC2_AGC_OFF__W 16 +#define FE_AG_REG_GC2_AGC_OFF__M 0xFFFF +#define FE_AG_REG_GC2_AGC_OFF_INIT 0x0 + + +#define FE_AG_REG_GC2_AGC_MAX__A 0xC20039 +#define FE_AG_REG_GC2_AGC_MAX__W 10 +#define FE_AG_REG_GC2_AGC_MAX__M 0x3FF +#define FE_AG_REG_GC2_AGC_MAX_INIT 0x0 + + +#define FE_AG_REG_GC2_AGC_MIN__A 0xC2003A +#define FE_AG_REG_GC2_AGC_MIN__W 10 +#define FE_AG_REG_GC2_AGC_MIN__M 0x3FF +#define FE_AG_REG_GC2_AGC_MIN_INIT 0x0 + + +#define FE_AG_REG_GC2_AGC_DAT__A 0xC2003B +#define FE_AG_REG_GC2_AGC_DAT__W 10 +#define FE_AG_REG_GC2_AGC_DAT__M 0x3FF + +#define FE_AG_REG_IND_WIN__A 0xC2003C +#define FE_AG_REG_IND_WIN__W 5 +#define FE_AG_REG_IND_WIN__M 0x1F +#define FE_AG_REG_IND_WIN_INIT 0x0 + + +#define FE_AG_REG_IND_THD_LOL__A 0xC2003D +#define FE_AG_REG_IND_THD_LOL__W 6 +#define FE_AG_REG_IND_THD_LOL__M 0x3F +#define FE_AG_REG_IND_THD_LOL_INIT 0x0 + + +#define FE_AG_REG_IND_THD_HIL__A 0xC2003E +#define FE_AG_REG_IND_THD_HIL__W 6 +#define FE_AG_REG_IND_THD_HIL__M 0x3F +#define FE_AG_REG_IND_THD_HIL_INIT 0x0 + + +#define FE_AG_REG_IND_DEL__A 0xC2003F +#define FE_AG_REG_IND_DEL__W 7 +#define FE_AG_REG_IND_DEL__M 0x7F +#define FE_AG_REG_IND_DEL_INIT 0x0 + + +#define FE_AG_REG_IND_PD1_WRI__A 0xC20040 +#define FE_AG_REG_IND_PD1_WRI__W 6 +#define FE_AG_REG_IND_PD1_WRI__M 0x3F +#define FE_AG_REG_IND_PD1_WRI_INIT 0x1F + + +#define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 +#define FE_AG_REG_PDA_AUR_CNT__W 5 +#define FE_AG_REG_PDA_AUR_CNT__M 0x1F +#define FE_AG_REG_PDA_AUR_CNT_INIT 0x0 + + +#define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 +#define FE_AG_REG_PDA_RUR_CNT__W 5 +#define FE_AG_REG_PDA_RUR_CNT__M 0x1F +#define FE_AG_REG_PDA_RUR_CNT_INIT 0x0 + + +#define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 +#define FE_AG_REG_PDA_AVE_DAT__W 6 +#define FE_AG_REG_PDA_AVE_DAT__M 0x3F + +#define FE_AG_REG_PDC_RUR_CNT__A 0xC20044 +#define FE_AG_REG_PDC_RUR_CNT__W 5 +#define FE_AG_REG_PDC_RUR_CNT__M 0x1F +#define FE_AG_REG_PDC_RUR_CNT_INIT 0x0 + + +#define FE_AG_REG_PDC_SET_LVL__A 0xC20045 +#define FE_AG_REG_PDC_SET_LVL__W 6 +#define FE_AG_REG_PDC_SET_LVL__M 0x3F +#define FE_AG_REG_PDC_SET_LVL_INIT 0x10 + + +#define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 +#define FE_AG_REG_PDC_FLA_RGN__W 6 +#define FE_AG_REG_PDC_FLA_RGN__M 0x3F +#define FE_AG_REG_PDC_FLA_RGN_INIT 0x0 + + +#define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 +#define FE_AG_REG_PDC_JMP_PSN__W 3 +#define FE_AG_REG_PDC_JMP_PSN__M 0x7 +#define FE_AG_REG_PDC_JMP_PSN_INIT 0x0 + + +#define FE_AG_REG_PDC_FLA_STP__A 0xC20048 +#define FE_AG_REG_PDC_FLA_STP__W 16 +#define FE_AG_REG_PDC_FLA_STP__M 0xFFFF +#define FE_AG_REG_PDC_FLA_STP_INIT 0x0 + + +#define FE_AG_REG_PDC_SLO_STP__A 0xC20049 +#define FE_AG_REG_PDC_SLO_STP__W 16 +#define FE_AG_REG_PDC_SLO_STP__M 0xFFFF +#define FE_AG_REG_PDC_SLO_STP_INIT 0x0 + + +#define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A +#define FE_AG_REG_PDC_PD2_WRI__W 6 +#define FE_AG_REG_PDC_PD2_WRI__M 0x3F +#define FE_AG_REG_PDC_PD2_WRI_INIT 0x0 + + +#define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B +#define FE_AG_REG_PDC_MAP_DAT__W 6 +#define FE_AG_REG_PDC_MAP_DAT__M 0x3F + +#define FE_AG_REG_PDC_MAX__A 0xC2004C +#define FE_AG_REG_PDC_MAX__W 6 +#define FE_AG_REG_PDC_MAX__M 0x3F +#define FE_AG_REG_PDC_MAX_INIT 0x2 + + +#define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D +#define FE_AG_REG_TGA_AUR_CNT__W 5 +#define FE_AG_REG_TGA_AUR_CNT__M 0x1F +#define FE_AG_REG_TGA_AUR_CNT_INIT 0x0 + + +#define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E +#define FE_AG_REG_TGA_RUR_CNT__W 5 +#define FE_AG_REG_TGA_RUR_CNT__M 0x1F +#define FE_AG_REG_TGA_RUR_CNT_INIT 0x0 + + +#define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F +#define FE_AG_REG_TGA_AVE_DAT__W 6 +#define FE_AG_REG_TGA_AVE_DAT__M 0x3F + +#define FE_AG_REG_TGC_RUR_CNT__A 0xC20050 +#define FE_AG_REG_TGC_RUR_CNT__W 5 +#define FE_AG_REG_TGC_RUR_CNT__M 0x1F +#define FE_AG_REG_TGC_RUR_CNT_INIT 0x0 + + +#define FE_AG_REG_TGC_SET_LVL__A 0xC20051 +#define FE_AG_REG_TGC_SET_LVL__W 6 +#define FE_AG_REG_TGC_SET_LVL__M 0x3F +#define FE_AG_REG_TGC_SET_LVL_INIT 0x0 + + +#define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 +#define FE_AG_REG_TGC_FLA_RGN__W 6 +#define FE_AG_REG_TGC_FLA_RGN__M 0x3F +#define FE_AG_REG_TGC_FLA_RGN_INIT 0x0 + + +#define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 +#define FE_AG_REG_TGC_JMP_PSN__W 4 +#define FE_AG_REG_TGC_JMP_PSN__M 0xF +#define FE_AG_REG_TGC_JMP_PSN_INIT 0x0 + + +#define FE_AG_REG_TGC_FLA_STP__A 0xC20054 +#define FE_AG_REG_TGC_FLA_STP__W 16 +#define FE_AG_REG_TGC_FLA_STP__M 0xFFFF +#define FE_AG_REG_TGC_FLA_STP_INIT 0x0 + + +#define FE_AG_REG_TGC_SLO_STP__A 0xC20055 +#define FE_AG_REG_TGC_SLO_STP__W 16 +#define FE_AG_REG_TGC_SLO_STP__M 0xFFFF +#define FE_AG_REG_TGC_SLO_STP_INIT 0x0 + + +#define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 +#define FE_AG_REG_TGC_MAP_DAT__W 10 +#define FE_AG_REG_TGC_MAP_DAT__M 0x3FF + +#define FE_AG_REG_FGA_AUR_CNT__A 0xC20057 +#define FE_AG_REG_FGA_AUR_CNT__W 5 +#define FE_AG_REG_FGA_AUR_CNT__M 0x1F +#define FE_AG_REG_FGA_AUR_CNT_INIT 0x0 + + +#define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 +#define FE_AG_REG_FGA_RUR_CNT__W 5 +#define FE_AG_REG_FGA_RUR_CNT__M 0x1F +#define FE_AG_REG_FGA_RUR_CNT_INIT 0x0 + + +#define FE_AG_REG_FGA_AVE_DAT__A 0xC20059 +#define FE_AG_REG_FGA_AVE_DAT__W 10 +#define FE_AG_REG_FGA_AVE_DAT__M 0x3FF + +#define FE_AG_REG_FGC_RUR_CNT__A 0xC2005A +#define FE_AG_REG_FGC_RUR_CNT__W 5 +#define FE_AG_REG_FGC_RUR_CNT__M 0x1F +#define FE_AG_REG_FGC_RUR_CNT_INIT 0x0 + + +#define FE_AG_REG_FGC_SET_LVL__A 0xC2005B +#define FE_AG_REG_FGC_SET_LVL__W 9 +#define FE_AG_REG_FGC_SET_LVL__M 0x1FF +#define FE_AG_REG_FGC_SET_LVL_INIT 0x0 + + +#define FE_AG_REG_FGC_FLA_RGN__A 0xC2005C +#define FE_AG_REG_FGC_FLA_RGN__W 9 +#define FE_AG_REG_FGC_FLA_RGN__M 0x1FF +#define FE_AG_REG_FGC_FLA_RGN_INIT 0x0 + + +#define FE_AG_REG_FGC_JMP_PSN__A 0xC2005D +#define FE_AG_REG_FGC_JMP_PSN__W 4 +#define FE_AG_REG_FGC_JMP_PSN__M 0xF +#define FE_AG_REG_FGC_JMP_PSN_INIT 0x0 + + +#define FE_AG_REG_FGC_FLA_STP__A 0xC2005E +#define FE_AG_REG_FGC_FLA_STP__W 16 +#define FE_AG_REG_FGC_FLA_STP__M 0xFFFF +#define FE_AG_REG_FGC_FLA_STP_INIT 0x0 + + +#define FE_AG_REG_FGC_SLO_STP__A 0xC2005F +#define FE_AG_REG_FGC_SLO_STP__W 16 +#define FE_AG_REG_FGC_SLO_STP__M 0xFFFF +#define FE_AG_REG_FGC_SLO_STP_INIT 0x0 + + +#define FE_AG_REG_FGC_MAP_DAT__A 0xC20060 +#define FE_AG_REG_FGC_MAP_DAT__W 10 +#define FE_AG_REG_FGC_MAP_DAT__M 0x3FF + +#define FE_AG_REG_FGM_WRI__A 0xC20061 +#define FE_AG_REG_FGM_WRI__W 10 +#define FE_AG_REG_FGM_WRI__M 0x3FF +#define FE_AG_REG_FGM_WRI_INIT 0x20 + + +#define FE_AG_REG_BGC_RUR_CNT__A 0xC20062 +#define FE_AG_REG_BGC_RUR_CNT__W 5 +#define FE_AG_REG_BGC_RUR_CNT__M 0x1F +#define FE_AG_REG_BGC_RUR_CNT_INIT 0x0 + + +#define FE_AG_REG_BGC_SET_LVL__A 0xC20063 +#define FE_AG_REG_BGC_SET_LVL__W 9 +#define FE_AG_REG_BGC_SET_LVL__M 0x1FF +#define FE_AG_REG_BGC_SET_LVL_INIT 0x0 + + +#define FE_AG_REG_BGC_FLA_RGN__A 0xC20064 +#define FE_AG_REG_BGC_FLA_RGN__W 9 +#define FE_AG_REG_BGC_FLA_RGN__M 0x1FF +#define FE_AG_REG_BGC_FLA_RGN_INIT 0x0 + + +#define FE_AG_REG_BGC_JMP_PSN__A 0xC20065 +#define FE_AG_REG_BGC_JMP_PSN__W 4 +#define FE_AG_REG_BGC_JMP_PSN__M 0xF +#define FE_AG_REG_BGC_JMP_PSN_INIT 0x0 + + +#define FE_AG_REG_BGC_FLA_STP__A 0xC20066 +#define FE_AG_REG_BGC_FLA_STP__W 16 +#define FE_AG_REG_BGC_FLA_STP__M 0xFFFF +#define FE_AG_REG_BGC_FLA_STP_INIT 0x0 + + +#define FE_AG_REG_BGC_SLO_STP__A 0xC20067 +#define FE_AG_REG_BGC_SLO_STP__W 16 +#define FE_AG_REG_BGC_SLO_STP__M 0xFFFF +#define FE_AG_REG_BGC_SLO_STP_INIT 0x0 + + +#define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 +#define FE_AG_REG_BGC_FGC_WRI__W 4 +#define FE_AG_REG_BGC_FGC_WRI__M 0xF +#define FE_AG_REG_BGC_FGC_WRI_INIT 0x7 + + +#define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 +#define FE_AG_REG_BGC_CGC_WRI__W 2 +#define FE_AG_REG_BGC_CGC_WRI__M 0x3 +#define FE_AG_REG_BGC_CGC_WRI_INIT 0x1 + + +#define FE_AG_REG_BGC_FGC_DAT__A 0xC2006A +#define FE_AG_REG_BGC_FGC_DAT__W 4 +#define FE_AG_REG_BGC_FGC_DAT__M 0xF + + + + + +#define FE_FS_SID 0x3 + + + + + + +#define FE_FS_REG_COMM_EXEC__A 0xC30000 +#define FE_FS_REG_COMM_EXEC__W 3 +#define FE_FS_REG_COMM_EXEC__M 0x7 +#define FE_FS_REG_COMM_EXEC_CTL__B 0 +#define FE_FS_REG_COMM_EXEC_CTL__W 3 +#define FE_FS_REG_COMM_EXEC_CTL__M 0x7 +#define FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 + +#define FE_FS_REG_COMM_STATE__A 0xC30001 +#define FE_FS_REG_COMM_STATE__W 4 +#define FE_FS_REG_COMM_STATE__M 0xF + +#define FE_FS_REG_COMM_MB__A 0xC30002 +#define FE_FS_REG_COMM_MB__W 3 +#define FE_FS_REG_COMM_MB__M 0x7 +#define FE_FS_REG_COMM_MB_CTR__B 0 +#define FE_FS_REG_COMM_MB_CTR__W 1 +#define FE_FS_REG_COMM_MB_CTR__M 0x1 +#define FE_FS_REG_COMM_MB_CTR_OFF 0x0 +#define FE_FS_REG_COMM_MB_CTR_ON 0x1 +#define FE_FS_REG_COMM_MB_OBS__B 1 +#define FE_FS_REG_COMM_MB_OBS__W 1 +#define FE_FS_REG_COMM_MB_OBS__M 0x2 +#define FE_FS_REG_COMM_MB_OBS_OFF 0x0 +#define FE_FS_REG_COMM_MB_OBS_ON 0x2 +#define FE_FS_REG_COMM_MB_MUX__B 2 +#define FE_FS_REG_COMM_MB_MUX__W 1 +#define FE_FS_REG_COMM_MB_MUX__M 0x4 +#define FE_FS_REG_COMM_MB_MUX_REAL 0x0 +#define FE_FS_REG_COMM_MB_MUX_IMAG 0x4 + + +#define FE_FS_REG_COMM_SERVICE0__A 0xC30003 +#define FE_FS_REG_COMM_SERVICE0__W 10 +#define FE_FS_REG_COMM_SERVICE0__M 0x3FF + +#define FE_FS_REG_COMM_SERVICE1__A 0xC30004 +#define FE_FS_REG_COMM_SERVICE1__W 11 +#define FE_FS_REG_COMM_SERVICE1__M 0x7FF + +#define FE_FS_REG_COMM_ACT__A 0xC30005 +#define FE_FS_REG_COMM_ACT__W 2 +#define FE_FS_REG_COMM_ACT__M 0x3 + +#define FE_FS_REG_COMM_CNT__A 0xC30006 +#define FE_FS_REG_COMM_CNT__W 16 +#define FE_FS_REG_COMM_CNT__M 0xFFFF + +#define FE_FS_REG_ADD_INC_LOP__A 0xC30010 +#define FE_FS_REG_ADD_INC_LOP__W 16 +#define FE_FS_REG_ADD_INC_LOP__M 0xFFFF +#define FE_FS_REG_ADD_INC_LOP_INIT 0x0 + + +#define FE_FS_REG_ADD_INC_HIP__A 0xC30011 +#define FE_FS_REG_ADD_INC_HIP__W 12 +#define FE_FS_REG_ADD_INC_HIP__M 0xFFF +#define FE_FS_REG_ADD_INC_HIP_INIT 0x0 + + +#define FE_FS_REG_ADD_OFF__A 0xC30012 +#define FE_FS_REG_ADD_OFF__W 12 +#define FE_FS_REG_ADD_OFF__M 0xFFF +#define FE_FS_REG_ADD_OFF_INIT 0x0 + + +#define FE_FS_REG_ADD_OFF_VAL__A 0xC30013 +#define FE_FS_REG_ADD_OFF_VAL__W 1 +#define FE_FS_REG_ADD_OFF_VAL__M 0x1 +#define FE_FS_REG_ADD_OFF_VAL_INIT 0x0 + + + + + +#define FE_FD_SID 0x4 + + + + + + +#define FE_FD_REG_COMM_EXEC__A 0xC40000 +#define FE_FD_REG_COMM_EXEC__W 3 +#define FE_FD_REG_COMM_EXEC__M 0x7 +#define FE_FD_REG_COMM_EXEC_CTL__B 0 +#define FE_FD_REG_COMM_EXEC_CTL__W 3 +#define FE_FD_REG_COMM_EXEC_CTL__M 0x7 +#define FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define FE_FD_REG_COMM_MB__A 0xC40002 +#define FE_FD_REG_COMM_MB__W 3 +#define FE_FD_REG_COMM_MB__M 0x7 +#define FE_FD_REG_COMM_MB_CTR__B 0 +#define FE_FD_REG_COMM_MB_CTR__W 1 +#define FE_FD_REG_COMM_MB_CTR__M 0x1 +#define FE_FD_REG_COMM_MB_CTR_OFF 0x0 +#define FE_FD_REG_COMM_MB_CTR_ON 0x1 +#define FE_FD_REG_COMM_MB_OBS__B 1 +#define FE_FD_REG_COMM_MB_OBS__W 1 +#define FE_FD_REG_COMM_MB_OBS__M 0x2 +#define FE_FD_REG_COMM_MB_OBS_OFF 0x0 +#define FE_FD_REG_COMM_MB_OBS_ON 0x2 + +#define FE_FD_REG_COMM_SERVICE0__A 0xC40003 +#define FE_FD_REG_COMM_SERVICE0__W 10 +#define FE_FD_REG_COMM_SERVICE0__M 0x3FF +#define FE_FD_REG_COMM_SERVICE1__A 0xC40004 +#define FE_FD_REG_COMM_SERVICE1__W 11 +#define FE_FD_REG_COMM_SERVICE1__M 0x7FF + +#define FE_FD_REG_COMM_INT_STA__A 0xC40007 +#define FE_FD_REG_COMM_INT_STA__W 1 +#define FE_FD_REG_COMM_INT_STA__M 0x1 +#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + + +#define FE_FD_REG_COMM_INT_MSK__A 0xC40008 +#define FE_FD_REG_COMM_INT_MSK__W 1 +#define FE_FD_REG_COMM_INT_MSK__M 0x1 +#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + + +#define FE_FD_REG_SCL__A 0xC40010 +#define FE_FD_REG_SCL__W 6 +#define FE_FD_REG_SCL__M 0x3F + +#define FE_FD_REG_MAX_LEV__A 0xC40011 +#define FE_FD_REG_MAX_LEV__W 3 +#define FE_FD_REG_MAX_LEV__M 0x7 + +#define FE_FD_REG_NR__A 0xC40012 +#define FE_FD_REG_NR__W 5 +#define FE_FD_REG_NR__M 0x1F + +#define FE_FD_REG_MEAS_SEL__A 0xC40013 +#define FE_FD_REG_MEAS_SEL__W 1 +#define FE_FD_REG_MEAS_SEL__M 0x1 + +#define FE_FD_REG_MEAS_VAL__A 0xC40014 +#define FE_FD_REG_MEAS_VAL__W 1 +#define FE_FD_REG_MEAS_VAL__M 0x1 + +#define FE_FD_REG_MAX__A 0xC40015 +#define FE_FD_REG_MAX__W 16 +#define FE_FD_REG_MAX__M 0xFFFF + +#define FE_FD_REG_POWER__A 0xC40016 +#define FE_FD_REG_POWER__W 10 +#define FE_FD_REG_POWER__M 0x3FF + + + + + +#define FE_IF_SID 0x5 + + + + + + +#define FE_IF_REG_COMM_EXEC__A 0xC50000 +#define FE_IF_REG_COMM_EXEC__W 3 +#define FE_IF_REG_COMM_EXEC__M 0x7 +#define FE_IF_REG_COMM_EXEC_CTL__B 0 +#define FE_IF_REG_COMM_EXEC_CTL__W 3 +#define FE_IF_REG_COMM_EXEC_CTL__M 0x7 +#define FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define FE_IF_REG_COMM_MB__A 0xC50002 +#define FE_IF_REG_COMM_MB__W 3 +#define FE_IF_REG_COMM_MB__M 0x7 +#define FE_IF_REG_COMM_MB_CTR__B 0 +#define FE_IF_REG_COMM_MB_CTR__W 1 +#define FE_IF_REG_COMM_MB_CTR__M 0x1 +#define FE_IF_REG_COMM_MB_CTR_OFF 0x0 +#define FE_IF_REG_COMM_MB_CTR_ON 0x1 +#define FE_IF_REG_COMM_MB_OBS__B 1 +#define FE_IF_REG_COMM_MB_OBS__W 1 +#define FE_IF_REG_COMM_MB_OBS__M 0x2 +#define FE_IF_REG_COMM_MB_OBS_OFF 0x0 +#define FE_IF_REG_COMM_MB_OBS_ON 0x2 + + +#define FE_IF_REG_INCR0__A 0xC50010 +#define FE_IF_REG_INCR0__W 16 +#define FE_IF_REG_INCR0__M 0xFFFF +#define FE_IF_REG_INCR0_INIT 0x0 + + +#define FE_IF_REG_INCR1__A 0xC50011 +#define FE_IF_REG_INCR1__W 8 +#define FE_IF_REG_INCR1__M 0xFF +#define FE_IF_REG_INCR1_INIT 0x28 + + + + + +#define FE_CF_SID 0x6 + + + + + + +#define FE_CF_REG_COMM_EXEC__A 0xC60000 +#define FE_CF_REG_COMM_EXEC__W 3 +#define FE_CF_REG_COMM_EXEC__M 0x7 +#define FE_CF_REG_COMM_EXEC_CTL__B 0 +#define FE_CF_REG_COMM_EXEC_CTL__W 3 +#define FE_CF_REG_COMM_EXEC_CTL__M 0x7 +#define FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define FE_CF_REG_COMM_MB__A 0xC60002 +#define FE_CF_REG_COMM_MB__W 3 +#define FE_CF_REG_COMM_MB__M 0x7 +#define FE_CF_REG_COMM_MB_CTR__B 0 +#define FE_CF_REG_COMM_MB_CTR__W 1 +#define FE_CF_REG_COMM_MB_CTR__M 0x1 +#define FE_CF_REG_COMM_MB_CTR_OFF 0x0 +#define FE_CF_REG_COMM_MB_CTR_ON 0x1 +#define FE_CF_REG_COMM_MB_OBS__B 1 +#define FE_CF_REG_COMM_MB_OBS__W 1 +#define FE_CF_REG_COMM_MB_OBS__M 0x2 +#define FE_CF_REG_COMM_MB_OBS_OFF 0x0 +#define FE_CF_REG_COMM_MB_OBS_ON 0x2 + +#define FE_CF_REG_COMM_SERVICE0__A 0xC60003 +#define FE_CF_REG_COMM_SERVICE0__W 10 +#define FE_CF_REG_COMM_SERVICE0__M 0x3FF +#define FE_CF_REG_COMM_SERVICE1__A 0xC60004 +#define FE_CF_REG_COMM_SERVICE1__W 11 +#define FE_CF_REG_COMM_SERVICE1__M 0x7FF + +#define FE_CF_REG_COMM_INT_STA__A 0xC60007 +#define FE_CF_REG_COMM_INT_STA__W 2 +#define FE_CF_REG_COMM_INT_STA__M 0x3 +#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + + +#define FE_CF_REG_COMM_INT_MSK__A 0xC60008 +#define FE_CF_REG_COMM_INT_MSK__W 2 +#define FE_CF_REG_COMM_INT_MSK__M 0x3 +#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + + +#define FE_CF_REG_SCL__A 0xC60010 +#define FE_CF_REG_SCL__W 9 +#define FE_CF_REG_SCL__M 0x1FF + +#define FE_CF_REG_MAX_LEV__A 0xC60011 +#define FE_CF_REG_MAX_LEV__W 3 +#define FE_CF_REG_MAX_LEV__M 0x7 + +#define FE_CF_REG_NR__A 0xC60012 +#define FE_CF_REG_NR__W 5 +#define FE_CF_REG_NR__M 0x1F + +#define FE_CF_REG_IMP_VAL__A 0xC60013 +#define FE_CF_REG_IMP_VAL__W 1 +#define FE_CF_REG_IMP_VAL__M 0x1 + +#define FE_CF_REG_MEAS_VAL__A 0xC60014 +#define FE_CF_REG_MEAS_VAL__W 1 +#define FE_CF_REG_MEAS_VAL__M 0x1 + +#define FE_CF_REG_MAX__A 0xC60015 +#define FE_CF_REG_MAX__W 16 +#define FE_CF_REG_MAX__M 0xFFFF + +#define FE_CF_REG_POWER__A 0xC60016 +#define FE_CF_REG_POWER__W 10 +#define FE_CF_REG_POWER__M 0x3FF + + + + + +#define FE_CU_SID 0x7 + + + + + + +#define FE_CU_REG_COMM_EXEC__A 0xC70000 +#define FE_CU_REG_COMM_EXEC__W 3 +#define FE_CU_REG_COMM_EXEC__M 0x7 +#define FE_CU_REG_COMM_EXEC_CTL__B 0 +#define FE_CU_REG_COMM_EXEC_CTL__W 3 +#define FE_CU_REG_COMM_EXEC_CTL__M 0x7 +#define FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 + +#define FE_CU_REG_COMM_STATE__A 0xC70001 +#define FE_CU_REG_COMM_STATE__W 4 +#define FE_CU_REG_COMM_STATE__M 0xF + +#define FE_CU_REG_COMM_MB__A 0xC70002 +#define FE_CU_REG_COMM_MB__W 3 +#define FE_CU_REG_COMM_MB__M 0x7 +#define FE_CU_REG_COMM_MB_CTR__B 0 +#define FE_CU_REG_COMM_MB_CTR__W 1 +#define FE_CU_REG_COMM_MB_CTR__M 0x1 +#define FE_CU_REG_COMM_MB_CTR_OFF 0x0 +#define FE_CU_REG_COMM_MB_CTR_ON 0x1 +#define FE_CU_REG_COMM_MB_OBS__B 1 +#define FE_CU_REG_COMM_MB_OBS__W 1 +#define FE_CU_REG_COMM_MB_OBS__M 0x2 +#define FE_CU_REG_COMM_MB_OBS_OFF 0x0 +#define FE_CU_REG_COMM_MB_OBS_ON 0x2 +#define FE_CU_REG_COMM_MB_MUX__B 2 +#define FE_CU_REG_COMM_MB_MUX__W 1 +#define FE_CU_REG_COMM_MB_MUX__M 0x4 +#define FE_CU_REG_COMM_MB_MUX_REAL 0x0 +#define FE_CU_REG_COMM_MB_MUX_IMAG 0x4 + + +#define FE_CU_REG_COMM_SERVICE0__A 0xC70003 +#define FE_CU_REG_COMM_SERVICE0__W 10 +#define FE_CU_REG_COMM_SERVICE0__M 0x3FF + +#define FE_CU_REG_COMM_SERVICE1__A 0xC70004 +#define FE_CU_REG_COMM_SERVICE1__W 11 +#define FE_CU_REG_COMM_SERVICE1__M 0x7FF + +#define FE_CU_REG_COMM_ACT__A 0xC70005 +#define FE_CU_REG_COMM_ACT__W 2 +#define FE_CU_REG_COMM_ACT__M 0x3 + +#define FE_CU_REG_COMM_CNT__A 0xC70006 +#define FE_CU_REG_COMM_CNT__W 16 +#define FE_CU_REG_COMM_CNT__M 0xFFFF + +#define FE_CU_REG_COMM_INT_STA__A 0xC70007 +#define FE_CU_REG_COMM_INT_STA__W 2 +#define FE_CU_REG_COMM_INT_STA__M 0x3 +#define FE_CU_REG_COMM_INT_STA_FE_START__B 0 +#define FE_CU_REG_COMM_INT_STA_FE_START__W 1 +#define FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 +#define FE_CU_REG_COMM_INT_STA_FT_START__B 1 +#define FE_CU_REG_COMM_INT_STA_FT_START__W 1 +#define FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 + + +#define FE_CU_REG_COMM_INT_MSK__A 0xC70008 +#define FE_CU_REG_COMM_INT_MSK__W 2 +#define FE_CU_REG_COMM_INT_MSK__M 0x3 +#define FE_CU_REG_COMM_INT_MSK_FE_START__B 0 +#define FE_CU_REG_COMM_INT_MSK_FE_START__W 1 +#define FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 +#define FE_CU_REG_COMM_INT_MSK_FT_START__B 1 +#define FE_CU_REG_COMM_INT_MSK_FT_START__W 1 +#define FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 + + +#define FE_CU_REG_MODE__A 0xC70010 +#define FE_CU_REG_MODE__W 3 +#define FE_CU_REG_MODE__M 0x7 +#define FE_CU_REG_MODE_INIT 0x0 + +#define FE_CU_REG_MODE_FFT__B 0 +#define FE_CU_REG_MODE_FFT__W 1 +#define FE_CU_REG_MODE_FFT__M 0x1 +#define FE_CU_REG_MODE_FFT_M8K 0x0 +#define FE_CU_REG_MODE_FFT_M2K 0x1 + +#define FE_CU_REG_MODE_COR__B 1 +#define FE_CU_REG_MODE_COR__W 1 +#define FE_CU_REG_MODE_COR__M 0x2 +#define FE_CU_REG_MODE_COR_OFF 0x0 +#define FE_CU_REG_MODE_COR_ON 0x2 + +#define FE_CU_REG_MODE_IFD__B 2 +#define FE_CU_REG_MODE_IFD__W 1 +#define FE_CU_REG_MODE_IFD__M 0x4 +#define FE_CU_REG_MODE_IFD_ENABLE 0x0 +#define FE_CU_REG_MODE_IFD_DISABLE 0x4 + + +#define FE_CU_REG_FRM_CNT_RST__A 0xC70011 +#define FE_CU_REG_FRM_CNT_RST__W 15 +#define FE_CU_REG_FRM_CNT_RST__M 0x7FFF +#define FE_CU_REG_FRM_CNT_RST_INIT 0x0 + + +#define FE_CU_REG_FRM_CNT_STR__A 0xC70012 +#define FE_CU_REG_FRM_CNT_STR__W 15 +#define FE_CU_REG_FRM_CNT_STR__M 0x7FFF +#define FE_CU_REG_FRM_CNT_STR_INIT 0x0 + + +#define FE_CU_REG_FRM_SMP_CNT__A 0xC70013 +#define FE_CU_REG_FRM_SMP_CNT__W 15 +#define FE_CU_REG_FRM_SMP_CNT__M 0x7FFF + +#define FE_CU_REG_FRM_SMB_CNT__A 0xC70014 +#define FE_CU_REG_FRM_SMB_CNT__W 16 +#define FE_CU_REG_FRM_SMB_CNT__M 0xFFFF + +#define FE_CU_REG_CMP_MAX_DAT__A 0xC70015 +#define FE_CU_REG_CMP_MAX_DAT__W 12 +#define FE_CU_REG_CMP_MAX_DAT__M 0xFFF + +#define FE_CU_REG_CMP_MAX_ADR__A 0xC70016 +#define FE_CU_REG_CMP_MAX_ADR__W 10 +#define FE_CU_REG_CMP_MAX_ADR__M 0x3FF + +#define FE_CU_REG_CTR_NF1_WLO__A 0xC70017 +#define FE_CU_REG_CTR_NF1_WLO__W 15 +#define FE_CU_REG_CTR_NF1_WLO__M 0x7FFF +#define FE_CU_REG_CTR_NF1_WLO_INIT 0x0 + + +#define FE_CU_REG_CTR_NF1_WHI__A 0xC70018 +#define FE_CU_REG_CTR_NF1_WHI__W 15 +#define FE_CU_REG_CTR_NF1_WHI__M 0x7FFF +#define FE_CU_REG_CTR_NF1_WHI_INIT 0x0 + + +#define FE_CU_REG_CTR_NF2_WLO__A 0xC70019 +#define FE_CU_REG_CTR_NF2_WLO__W 15 +#define FE_CU_REG_CTR_NF2_WLO__M 0x7FFF +#define FE_CU_REG_CTR_NF2_WLO_INIT 0x0 + + +#define FE_CU_REG_CTR_NF2_WHI__A 0xC7001A +#define FE_CU_REG_CTR_NF2_WHI__W 15 +#define FE_CU_REG_CTR_NF2_WHI__M 0x7FFF +#define FE_CU_REG_CTR_NF2_WHI_INIT 0x0 + + +#define FE_CU_REG_DIV_NF1_REA__A 0xC7001B +#define FE_CU_REG_DIV_NF1_REA__W 12 +#define FE_CU_REG_DIV_NF1_REA__M 0xFFF + +#define FE_CU_REG_DIV_NF1_IMA__A 0xC7001C +#define FE_CU_REG_DIV_NF1_IMA__W 12 +#define FE_CU_REG_DIV_NF1_IMA__M 0xFFF + +#define FE_CU_REG_DIV_NF2_REA__A 0xC7001D +#define FE_CU_REG_DIV_NF2_REA__W 12 +#define FE_CU_REG_DIV_NF2_REA__M 0xFFF + +#define FE_CU_REG_DIV_NF2_IMA__A 0xC7001E +#define FE_CU_REG_DIV_NF2_IMA__W 12 +#define FE_CU_REG_DIV_NF2_IMA__M 0xFFF + + + +#define FE_CU_BUF_RAM__A 0xC80000 + + + +#define FE_CU_CMP_RAM__A 0xC90000 + + + + + +#define FT_SID 0x8 + + + + + +#define FT_COMM_EXEC__A 0x1000000 +#define FT_COMM_EXEC__W 3 +#define FT_COMM_EXEC__M 0x7 +#define FT_COMM_EXEC_CTL__B 0 +#define FT_COMM_EXEC_CTL__W 3 +#define FT_COMM_EXEC_CTL__M 0x7 +#define FT_COMM_EXEC_CTL_STOP 0x0 +#define FT_COMM_EXEC_CTL_ACTIVE 0x1 +#define FT_COMM_EXEC_CTL_HOLD 0x2 +#define FT_COMM_EXEC_CTL_STEP 0x3 +#define FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define FT_COMM_STATE__A 0x1000001 +#define FT_COMM_STATE__W 16 +#define FT_COMM_STATE__M 0xFFFF +#define FT_COMM_MB__A 0x1000002 +#define FT_COMM_MB__W 16 +#define FT_COMM_MB__M 0xFFFF +#define FT_COMM_SERVICE0__A 0x1000003 +#define FT_COMM_SERVICE0__W 16 +#define FT_COMM_SERVICE0__M 0xFFFF +#define FT_COMM_SERVICE1__A 0x1000004 +#define FT_COMM_SERVICE1__W 16 +#define FT_COMM_SERVICE1__M 0xFFFF +#define FT_COMM_INT_STA__A 0x1000007 +#define FT_COMM_INT_STA__W 16 +#define FT_COMM_INT_STA__M 0xFFFF +#define FT_COMM_INT_MSK__A 0x1000008 +#define FT_COMM_INT_MSK__W 16 +#define FT_COMM_INT_MSK__M 0xFFFF + + + + + + +#define FT_REG_COMM_EXEC__A 0x1010000 +#define FT_REG_COMM_EXEC__W 3 +#define FT_REG_COMM_EXEC__M 0x7 +#define FT_REG_COMM_EXEC_CTL__B 0 +#define FT_REG_COMM_EXEC_CTL__W 3 +#define FT_REG_COMM_EXEC_CTL__M 0x7 +#define FT_REG_COMM_EXEC_CTL_STOP 0x0 +#define FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FT_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define FT_REG_COMM_MB__A 0x1010002 +#define FT_REG_COMM_MB__W 3 +#define FT_REG_COMM_MB__M 0x7 +#define FT_REG_COMM_MB_CTR__B 0 +#define FT_REG_COMM_MB_CTR__W 1 +#define FT_REG_COMM_MB_CTR__M 0x1 +#define FT_REG_COMM_MB_CTR_OFF 0x0 +#define FT_REG_COMM_MB_CTR_ON 0x1 +#define FT_REG_COMM_MB_OBS__B 1 +#define FT_REG_COMM_MB_OBS__W 1 +#define FT_REG_COMM_MB_OBS__M 0x2 +#define FT_REG_COMM_MB_OBS_OFF 0x0 +#define FT_REG_COMM_MB_OBS_ON 0x2 + +#define FT_REG_COMM_SERVICE0__A 0x1010003 +#define FT_REG_COMM_SERVICE0__W 10 +#define FT_REG_COMM_SERVICE0__M 0x3FF +#define FT_REG_COMM_SERVICE0_FT__B 8 +#define FT_REG_COMM_SERVICE0_FT__W 1 +#define FT_REG_COMM_SERVICE0_FT__M 0x100 + +#define FT_REG_COMM_SERVICE1__A 0x1010004 +#define FT_REG_COMM_SERVICE1__W 11 +#define FT_REG_COMM_SERVICE1__M 0x7FF + +#define FT_REG_COMM_INT_STA__A 0x1010007 +#define FT_REG_COMM_INT_STA__W 2 +#define FT_REG_COMM_INT_STA__M 0x3 +#define FT_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define FT_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define FT_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + + +#define FT_REG_COMM_INT_MSK__A 0x1010008 +#define FT_REG_COMM_INT_MSK__W 2 +#define FT_REG_COMM_INT_MSK__M 0x3 +#define FT_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define FT_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define FT_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + + +#define FT_REG_MODE_2K__A 0x1010010 +#define FT_REG_MODE_2K__W 1 +#define FT_REG_MODE_2K__M 0x1 +#define FT_REG_MODE_2K_MODE_8K 0x0 +#define FT_REG_MODE_2K_MODE_2K 0x1 +#define FT_REG_MODE_2K_INIT 0x0 + + +#define FT_REG_BUS_MOD__A 0x1010011 +#define FT_REG_BUS_MOD__W 1 +#define FT_REG_BUS_MOD__M 0x1 +#define FT_REG_BUS_MOD_INPUT 0x0 +#define FT_REG_BUS_MOD_PILOT 0x1 +#define FT_REG_BUS_MOD_INIT 0x0 + + +#define FT_REG_BUS_REAL__A 0x1010012 +#define FT_REG_BUS_REAL__W 10 +#define FT_REG_BUS_REAL__M 0x3FF +#define FT_REG_BUS_REAL_INIT 0x0 + + +#define FT_REG_BUS_IMAG__A 0x1010013 +#define FT_REG_BUS_IMAG__W 10 +#define FT_REG_BUS_IMAG__M 0x3FF +#define FT_REG_BUS_IMAG_INIT 0x0 + + +#define FT_REG_BUS_VAL__A 0x1010014 +#define FT_REG_BUS_VAL__W 1 +#define FT_REG_BUS_VAL__M 0x1 +#define FT_REG_BUS_VAL_INIT 0x0 + + +#define FT_REG_PEAK__A 0x1010015 +#define FT_REG_PEAK__W 11 +#define FT_REG_PEAK__M 0x7FF +#define FT_REG_PEAK_INIT 0x0 + + +#define FT_REG_NORM_OFF__A 0x1010016 +#define FT_REG_NORM_OFF__W 4 +#define FT_REG_NORM_OFF__M 0xF +#define FT_REG_NORM_OFF_INIT 0x2 + + + +#define FT_ST1_RAM__A 0x1020000 + + + +#define FT_ST2_RAM__A 0x1030000 + + + +#define FT_ST3_RAM__A 0x1040000 + + + +#define FT_ST5_RAM__A 0x1050000 + + + +#define FT_ST6_RAM__A 0x1060000 + + + +#define FT_ST8_RAM__A 0x1070000 + + + +#define FT_ST9_RAM__A 0x1080000 + + + + + +#define CP_SID 0x9 + + + + + +#define CP_COMM_EXEC__A 0x1400000 +#define CP_COMM_EXEC__W 3 +#define CP_COMM_EXEC__M 0x7 +#define CP_COMM_EXEC_CTL__B 0 +#define CP_COMM_EXEC_CTL__W 3 +#define CP_COMM_EXEC_CTL__M 0x7 +#define CP_COMM_EXEC_CTL_STOP 0x0 +#define CP_COMM_EXEC_CTL_ACTIVE 0x1 +#define CP_COMM_EXEC_CTL_HOLD 0x2 +#define CP_COMM_EXEC_CTL_STEP 0x3 +#define CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define CP_COMM_STATE__A 0x1400001 +#define CP_COMM_STATE__W 16 +#define CP_COMM_STATE__M 0xFFFF +#define CP_COMM_MB__A 0x1400002 +#define CP_COMM_MB__W 16 +#define CP_COMM_MB__M 0xFFFF +#define CP_COMM_SERVICE0__A 0x1400003 +#define CP_COMM_SERVICE0__W 16 +#define CP_COMM_SERVICE0__M 0xFFFF +#define CP_COMM_SERVICE1__A 0x1400004 +#define CP_COMM_SERVICE1__W 16 +#define CP_COMM_SERVICE1__M 0xFFFF +#define CP_COMM_INT_STA__A 0x1400007 +#define CP_COMM_INT_STA__W 16 +#define CP_COMM_INT_STA__M 0xFFFF +#define CP_COMM_INT_MSK__A 0x1400008 +#define CP_COMM_INT_MSK__W 16 +#define CP_COMM_INT_MSK__M 0xFFFF + + + + + + +#define CP_REG_COMM_EXEC__A 0x1410000 +#define CP_REG_COMM_EXEC__W 3 +#define CP_REG_COMM_EXEC__M 0x7 +#define CP_REG_COMM_EXEC_CTL__B 0 +#define CP_REG_COMM_EXEC_CTL__W 3 +#define CP_REG_COMM_EXEC_CTL__M 0x7 +#define CP_REG_COMM_EXEC_CTL_STOP 0x0 +#define CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define CP_REG_COMM_EXEC_CTL_HOLD 0x2 +#define CP_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define CP_REG_COMM_MB__A 0x1410002 +#define CP_REG_COMM_MB__W 3 +#define CP_REG_COMM_MB__M 0x7 +#define CP_REG_COMM_MB_CTR__B 0 +#define CP_REG_COMM_MB_CTR__W 1 +#define CP_REG_COMM_MB_CTR__M 0x1 +#define CP_REG_COMM_MB_CTR_OFF 0x0 +#define CP_REG_COMM_MB_CTR_ON 0x1 +#define CP_REG_COMM_MB_OBS__B 1 +#define CP_REG_COMM_MB_OBS__W 1 +#define CP_REG_COMM_MB_OBS__M 0x2 +#define CP_REG_COMM_MB_OBS_OFF 0x0 +#define CP_REG_COMM_MB_OBS_ON 0x2 + +#define CP_REG_COMM_SERVICE0__A 0x1410003 +#define CP_REG_COMM_SERVICE0__W 10 +#define CP_REG_COMM_SERVICE0__M 0x3FF +#define CP_REG_COMM_SERVICE0_CP__B 9 +#define CP_REG_COMM_SERVICE0_CP__W 1 +#define CP_REG_COMM_SERVICE0_CP__M 0x200 + +#define CP_REG_COMM_SERVICE1__A 0x1410004 +#define CP_REG_COMM_SERVICE1__W 11 +#define CP_REG_COMM_SERVICE1__M 0x7FF + +#define CP_REG_COMM_INT_STA__A 0x1410007 +#define CP_REG_COMM_INT_STA__W 2 +#define CP_REG_COMM_INT_STA__M 0x3 +#define CP_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define CP_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + + +#define CP_REG_COMM_INT_MSK__A 0x1410008 +#define CP_REG_COMM_INT_MSK__W 2 +#define CP_REG_COMM_INT_MSK__M 0x3 +#define CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + + +#define CP_REG_MODE_2K__A 0x1410010 +#define CP_REG_MODE_2K__W 1 +#define CP_REG_MODE_2K__M 0x1 +#define CP_REG_MODE_2K_INIT 0x0 + + +#define CP_REG_INTERVAL__A 0x1410011 +#define CP_REG_INTERVAL__W 4 +#define CP_REG_INTERVAL__M 0xF +#define CP_REG_INTERVAL_INIT 0x5 + + +#define CP_REG_SKIP_START0__A 0x1410012 +#define CP_REG_SKIP_START0__W 13 +#define CP_REG_SKIP_START0__M 0x1FFF +#define CP_REG_SKIP_START0_INIT 0x0 + + +#define CP_REG_SKIP_STOP0__A 0x1410013 +#define CP_REG_SKIP_STOP0__W 13 +#define CP_REG_SKIP_STOP0__M 0x1FFF +#define CP_REG_SKIP_STOP0_INIT 0x0 + + +#define CP_REG_SKIP_START1__A 0x1410014 +#define CP_REG_SKIP_START1__W 13 +#define CP_REG_SKIP_START1__M 0x1FFF +#define CP_REG_SKIP_START1_INIT 0x0 + + +#define CP_REG_SKIP_STOP1__A 0x1410015 +#define CP_REG_SKIP_STOP1__W 13 +#define CP_REG_SKIP_STOP1__M 0x1FFF +#define CP_REG_SKIP_STOP1_INIT 0x0 + + +#define CP_REG_SKIP_START2__A 0x1410016 +#define CP_REG_SKIP_START2__W 13 +#define CP_REG_SKIP_START2__M 0x1FFF +#define CP_REG_SKIP_START2_INIT 0x0 + + +#define CP_REG_SKIP_STOP2__A 0x1410017 +#define CP_REG_SKIP_STOP2__W 13 +#define CP_REG_SKIP_STOP2__M 0x1FFF +#define CP_REG_SKIP_STOP2_INIT 0x0 + + +#define CP_REG_SKIP_ENA__A 0x1410018 +#define CP_REG_SKIP_ENA__W 3 +#define CP_REG_SKIP_ENA__M 0x7 + +#define CP_REG_SKIP_ENA_CPL__B 0 +#define CP_REG_SKIP_ENA_CPL__W 1 +#define CP_REG_SKIP_ENA_CPL__M 0x1 + +#define CP_REG_SKIP_ENA_SPD__B 1 +#define CP_REG_SKIP_ENA_SPD__W 1 +#define CP_REG_SKIP_ENA_SPD__M 0x2 + +#define CP_REG_SKIP_ENA_CPD__B 2 +#define CP_REG_SKIP_ENA_CPD__W 1 +#define CP_REG_SKIP_ENA_CPD__M 0x4 +#define CP_REG_SKIP_ENA_INIT 0x0 + + +#define CP_REG_BR_MODE_MIX__A 0x1410020 +#define CP_REG_BR_MODE_MIX__W 1 +#define CP_REG_BR_MODE_MIX__M 0x1 +#define CP_REG_BR_MODE_MIX_INIT 0x0 + + +#define CP_REG_BR_SMB_NR__A 0x1410021 +#define CP_REG_BR_SMB_NR__W 3 +#define CP_REG_BR_SMB_NR__M 0x7 + +#define CP_REG_BR_SMB_NR_SMB__B 0 +#define CP_REG_BR_SMB_NR_SMB__W 2 +#define CP_REG_BR_SMB_NR_SMB__M 0x3 + +#define CP_REG_BR_SMB_NR_VAL__B 2 +#define CP_REG_BR_SMB_NR_VAL__W 1 +#define CP_REG_BR_SMB_NR_VAL__M 0x4 +#define CP_REG_BR_SMB_NR_INIT 0x0 + + +#define CP_REG_BR_CP_SMB_NR__A 0x1410022 +#define CP_REG_BR_CP_SMB_NR__W 2 +#define CP_REG_BR_CP_SMB_NR__M 0x3 +#define CP_REG_BR_CP_SMB_NR_INIT 0x0 + + +#define CP_REG_BR_SPL_OFFSET__A 0x1410023 +#define CP_REG_BR_SPL_OFFSET__W 3 +#define CP_REG_BR_SPL_OFFSET__M 0x7 +#define CP_REG_BR_SPL_OFFSET_INIT 0x0 + + +#define CP_REG_BR_STR_DEL__A 0x1410024 +#define CP_REG_BR_STR_DEL__W 10 +#define CP_REG_BR_STR_DEL__M 0x3FF +#define CP_REG_BR_STR_DEL_INIT 0xA + + +#define CP_REG_RT_ANG_INC0__A 0x1410030 +#define CP_REG_RT_ANG_INC0__W 16 +#define CP_REG_RT_ANG_INC0__M 0xFFFF +#define CP_REG_RT_ANG_INC0_INIT 0x0 + + +#define CP_REG_RT_ANG_INC1__A 0x1410031 +#define CP_REG_RT_ANG_INC1__W 8 +#define CP_REG_RT_ANG_INC1__M 0xFF +#define CP_REG_RT_ANG_INC1_INIT 0x0 + + +#define CP_REG_RT_DETECT_ENA__A 0x1410032 +#define CP_REG_RT_DETECT_ENA__W 2 +#define CP_REG_RT_DETECT_ENA__M 0x3 + +#define CP_REG_RT_DETECT_ENA_SCATTERED__B 0 +#define CP_REG_RT_DETECT_ENA_SCATTERED__W 1 +#define CP_REG_RT_DETECT_ENA_SCATTERED__M 0x1 + +#define CP_REG_RT_DETECT_ENA_CONTINUOUS__B 1 +#define CP_REG_RT_DETECT_ENA_CONTINUOUS__W 1 +#define CP_REG_RT_DETECT_ENA_CONTINUOUS__M 0x2 +#define CP_REG_RT_DETECT_ENA_INIT 0x0 + + +#define CP_REG_RT_DETECT_TRH__A 0x1410033 +#define CP_REG_RT_DETECT_TRH__W 2 +#define CP_REG_RT_DETECT_TRH__M 0x3 +#define CP_REG_RT_DETECT_TRH_INIT 0x3 + + +#define CP_REG_RT_SPD_RELIABLE__A 0x1410034 +#define CP_REG_RT_SPD_RELIABLE__W 3 +#define CP_REG_RT_SPD_RELIABLE__M 0x7 +#define CP_REG_RT_SPD_RELIABLE_INIT 0x0 + + +#define CP_REG_RT_SPD_DIRECTION__A 0x1410035 +#define CP_REG_RT_SPD_DIRECTION__W 1 +#define CP_REG_RT_SPD_DIRECTION__M 0x1 +#define CP_REG_RT_SPD_DIRECTION_INIT 0x0 + + +#define CP_REG_RT_SPD_MOD__A 0x1410036 +#define CP_REG_RT_SPD_MOD__W 2 +#define CP_REG_RT_SPD_MOD__M 0x3 +#define CP_REG_RT_SPD_MOD_INIT 0x0 + + +#define CP_REG_RT_SPD_SMB__A 0x1410037 +#define CP_REG_RT_SPD_SMB__W 2 +#define CP_REG_RT_SPD_SMB__M 0x3 +#define CP_REG_RT_SPD_SMB_INIT 0x0 + + +#define CP_REG_RT_CPD_MODE__A 0x1410038 +#define CP_REG_RT_CPD_MODE__W 3 +#define CP_REG_RT_CPD_MODE__M 0x7 + +#define CP_REG_RT_CPD_MODE_MOD3__B 0 +#define CP_REG_RT_CPD_MODE_MOD3__W 2 +#define CP_REG_RT_CPD_MODE_MOD3__M 0x3 + +#define CP_REG_RT_CPD_MODE_ADD__B 2 +#define CP_REG_RT_CPD_MODE_ADD__W 1 +#define CP_REG_RT_CPD_MODE_ADD__M 0x4 +#define CP_REG_RT_CPD_MODE_INIT 0x0 + + +#define CP_REG_RT_CPD_RELIABLE__A 0x1410039 +#define CP_REG_RT_CPD_RELIABLE__W 3 +#define CP_REG_RT_CPD_RELIABLE__M 0x7 +#define CP_REG_RT_CPD_RELIABLE_INIT 0x0 + + +#define CP_REG_RT_CPD_BIN__A 0x141003A +#define CP_REG_RT_CPD_BIN__W 5 +#define CP_REG_RT_CPD_BIN__M 0x1F +#define CP_REG_RT_CPD_BIN_INIT 0x0 + + +#define CP_REG_RT_CPD_MAX__A 0x141003B +#define CP_REG_RT_CPD_MAX__W 4 +#define CP_REG_RT_CPD_MAX__M 0xF +#define CP_REG_RT_CPD_MAX_INIT 0x0 + + +#define CP_REG_RT_SUPR_VAL__A 0x141003C +#define CP_REG_RT_SUPR_VAL__W 2 +#define CP_REG_RT_SUPR_VAL__M 0x3 + +#define CP_REG_RT_SUPR_VAL_CE__B 0 +#define CP_REG_RT_SUPR_VAL_CE__W 1 +#define CP_REG_RT_SUPR_VAL_CE__M 0x1 + +#define CP_REG_RT_SUPR_VAL_DL__B 1 +#define CP_REG_RT_SUPR_VAL_DL__W 1 +#define CP_REG_RT_SUPR_VAL_DL__M 0x2 +#define CP_REG_RT_SUPR_VAL_INIT 0x0 + + +#define CP_REG_RT_EXP_AVE__A 0x141003D +#define CP_REG_RT_EXP_AVE__W 5 +#define CP_REG_RT_EXP_AVE__M 0x1F +#define CP_REG_RT_EXP_AVE_INIT 0x0 + + +#define CP_REG_RT_EXP_MARG__A 0x141003E +#define CP_REG_RT_EXP_MARG__W 5 +#define CP_REG_RT_EXP_MARG__M 0x1F +#define CP_REG_RT_EXP_MARG_INIT 0x0 + + +#define CP_REG_AC_NEXP_OFFS__A 0x1410040 +#define CP_REG_AC_NEXP_OFFS__W 8 +#define CP_REG_AC_NEXP_OFFS__M 0xFF +#define CP_REG_AC_NEXP_OFFS_INIT 0x0 + + +#define CP_REG_AC_AVER_POW__A 0x1410041 +#define CP_REG_AC_AVER_POW__W 8 +#define CP_REG_AC_AVER_POW__M 0xFF +#define CP_REG_AC_AVER_POW_INIT 0x5F + + +#define CP_REG_AC_MAX_POW__A 0x1410042 +#define CP_REG_AC_MAX_POW__W 8 +#define CP_REG_AC_MAX_POW__M 0xFF +#define CP_REG_AC_MAX_POW_INIT 0x7A + + +#define CP_REG_AC_WEIGHT_MAN__A 0x1410043 +#define CP_REG_AC_WEIGHT_MAN__W 6 +#define CP_REG_AC_WEIGHT_MAN__M 0x3F +#define CP_REG_AC_WEIGHT_MAN_INIT 0x31 + + +#define CP_REG_AC_WEIGHT_EXP__A 0x1410044 +#define CP_REG_AC_WEIGHT_EXP__W 5 +#define CP_REG_AC_WEIGHT_EXP__M 0x1F +#define CP_REG_AC_WEIGHT_EXP_INIT 0x10 + + +#define CP_REG_AC_GAIN_MAN__A 0x1410045 +#define CP_REG_AC_GAIN_MAN__W 16 +#define CP_REG_AC_GAIN_MAN__M 0xFFFF +#define CP_REG_AC_GAIN_MAN_INIT 0x0 + + +#define CP_REG_AC_GAIN_EXP__A 0x1410046 +#define CP_REG_AC_GAIN_EXP__W 5 +#define CP_REG_AC_GAIN_EXP__M 0x1F +#define CP_REG_AC_GAIN_EXP_INIT 0x0 + + +#define CP_REG_AC_AMP_MODE__A 0x1410047 +#define CP_REG_AC_AMP_MODE__W 2 +#define CP_REG_AC_AMP_MODE__M 0x3 +#define CP_REG_AC_AMP_MODE_NEW 0x0 +#define CP_REG_AC_AMP_MODE_OLD 0x1 +#define CP_REG_AC_AMP_MODE_FIXED 0x2 +#define CP_REG_AC_AMP_MODE_INIT 0x2 + + +#define CP_REG_AC_AMP_FIX__A 0x1410048 +#define CP_REG_AC_AMP_FIX__W 14 +#define CP_REG_AC_AMP_FIX__M 0x3FFF +#define CP_REG_AC_AMP_FIX_INIT 0x1FF + + +#define CP_REG_AC_AMP_READ__A 0x1410049 +#define CP_REG_AC_AMP_READ__W 14 +#define CP_REG_AC_AMP_READ__M 0x3FFF +#define CP_REG_AC_AMP_READ_INIT 0x0 + + +#define CP_REG_AC_ANG_MODE__A 0x141004A +#define CP_REG_AC_ANG_MODE__W 2 +#define CP_REG_AC_ANG_MODE__M 0x3 +#define CP_REG_AC_ANG_MODE_NEW 0x0 +#define CP_REG_AC_ANG_MODE_OLD 0x1 +#define CP_REG_AC_ANG_MODE_NO_INT 0x2 +#define CP_REG_AC_ANG_MODE_OFFSET 0x3 +#define CP_REG_AC_ANG_MODE_INIT 0x3 + + +#define CP_REG_AC_ANG_OFFS__A 0x141004B +#define CP_REG_AC_ANG_OFFS__W 14 +#define CP_REG_AC_ANG_OFFS__M 0x3FFF +#define CP_REG_AC_ANG_OFFS_INIT 0x0 + + +#define CP_REG_AC_ANG_READ__A 0x141004C +#define CP_REG_AC_ANG_READ__W 16 +#define CP_REG_AC_ANG_READ__M 0xFFFF +#define CP_REG_AC_ANG_READ_INIT 0x0 + + +#define CP_REG_DL_MB_WR_ADDR__A 0x1410050 +#define CP_REG_DL_MB_WR_ADDR__W 15 +#define CP_REG_DL_MB_WR_ADDR__M 0x7FFF +#define CP_REG_DL_MB_WR_ADDR_INIT 0x0 + + +#define CP_REG_DL_MB_WR_CTR__A 0x1410051 +#define CP_REG_DL_MB_WR_CTR__W 5 +#define CP_REG_DL_MB_WR_CTR__M 0x1F + +#define CP_REG_DL_MB_WR_CTR_WORD__B 2 +#define CP_REG_DL_MB_WR_CTR_WORD__W 3 +#define CP_REG_DL_MB_WR_CTR_WORD__M 0x1C + +#define CP_REG_DL_MB_WR_CTR_OBS__B 1 +#define CP_REG_DL_MB_WR_CTR_OBS__W 1 +#define CP_REG_DL_MB_WR_CTR_OBS__M 0x2 + +#define CP_REG_DL_MB_WR_CTR_CTR__B 0 +#define CP_REG_DL_MB_WR_CTR_CTR__W 1 +#define CP_REG_DL_MB_WR_CTR_CTR__M 0x1 +#define CP_REG_DL_MB_WR_CTR_INIT 0x0 + + +#define CP_REG_DL_MB_RD_ADDR__A 0x1410052 +#define CP_REG_DL_MB_RD_ADDR__W 15 +#define CP_REG_DL_MB_RD_ADDR__M 0x7FFF +#define CP_REG_DL_MB_RD_ADDR_INIT 0x0 + + +#define CP_REG_DL_MB_RD_CTR__A 0x1410053 +#define CP_REG_DL_MB_RD_CTR__W 11 +#define CP_REG_DL_MB_RD_CTR__M 0x7FF + +#define CP_REG_DL_MB_RD_CTR_TEST__B 10 +#define CP_REG_DL_MB_RD_CTR_TEST__W 1 +#define CP_REG_DL_MB_RD_CTR_TEST__M 0x400 + +#define CP_REG_DL_MB_RD_CTR_OFFSET__B 8 +#define CP_REG_DL_MB_RD_CTR_OFFSET__W 2 +#define CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 + +#define CP_REG_DL_MB_RD_CTR_VALID__B 5 +#define CP_REG_DL_MB_RD_CTR_VALID__W 3 +#define CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 + +#define CP_REG_DL_MB_RD_CTR_WORD__B 2 +#define CP_REG_DL_MB_RD_CTR_WORD__W 3 +#define CP_REG_DL_MB_RD_CTR_WORD__M 0x1C + +#define CP_REG_DL_MB_RD_CTR_OBS__B 1 +#define CP_REG_DL_MB_RD_CTR_OBS__W 1 +#define CP_REG_DL_MB_RD_CTR_OBS__M 0x2 + +#define CP_REG_DL_MB_RD_CTR_CTR__B 0 +#define CP_REG_DL_MB_RD_CTR_CTR__W 1 +#define CP_REG_DL_MB_RD_CTR_CTR__M 0x1 +#define CP_REG_DL_MB_RD_CTR_INIT 0x0 + + + +#define CP_BR_BUF_RAM__A 0x1420000 + + + +#define CP_BR_CPL_RAM__A 0x1430000 + + + +#define CP_PB_DL0_RAM__A 0x1440000 + + + +#define CP_PB_DL1_RAM__A 0x1450000 + + + +#define CP_PB_DL2_RAM__A 0x1460000 + + + + + +#define CE_SID 0xA + + + + + +#define CE_COMM_EXEC__A 0x1800000 +#define CE_COMM_EXEC__W 3 +#define CE_COMM_EXEC__M 0x7 +#define CE_COMM_EXEC_CTL__B 0 +#define CE_COMM_EXEC_CTL__W 3 +#define CE_COMM_EXEC_CTL__M 0x7 +#define CE_COMM_EXEC_CTL_STOP 0x0 +#define CE_COMM_EXEC_CTL_ACTIVE 0x1 +#define CE_COMM_EXEC_CTL_HOLD 0x2 +#define CE_COMM_EXEC_CTL_STEP 0x3 +#define CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define CE_COMM_STATE__A 0x1800001 +#define CE_COMM_STATE__W 16 +#define CE_COMM_STATE__M 0xFFFF +#define CE_COMM_MB__A 0x1800002 +#define CE_COMM_MB__W 16 +#define CE_COMM_MB__M 0xFFFF +#define CE_COMM_SERVICE0__A 0x1800003 +#define CE_COMM_SERVICE0__W 16 +#define CE_COMM_SERVICE0__M 0xFFFF +#define CE_COMM_SERVICE1__A 0x1800004 +#define CE_COMM_SERVICE1__W 16 +#define CE_COMM_SERVICE1__M 0xFFFF +#define CE_COMM_INT_STA__A 0x1800007 +#define CE_COMM_INT_STA__W 16 +#define CE_COMM_INT_STA__M 0xFFFF +#define CE_COMM_INT_MSK__A 0x1800008 +#define CE_COMM_INT_MSK__W 16 +#define CE_COMM_INT_MSK__M 0xFFFF + + + + + + +#define CE_REG_COMM_EXEC__A 0x1810000 +#define CE_REG_COMM_EXEC__W 3 +#define CE_REG_COMM_EXEC__M 0x7 +#define CE_REG_COMM_EXEC_CTL__B 0 +#define CE_REG_COMM_EXEC_CTL__W 3 +#define CE_REG_COMM_EXEC_CTL__M 0x7 +#define CE_REG_COMM_EXEC_CTL_STOP 0x0 +#define CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define CE_REG_COMM_EXEC_CTL_HOLD 0x2 +#define CE_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define CE_REG_COMM_MB__A 0x1810002 +#define CE_REG_COMM_MB__W 4 +#define CE_REG_COMM_MB__M 0xF +#define CE_REG_COMM_MB_CTR__B 0 +#define CE_REG_COMM_MB_CTR__W 1 +#define CE_REG_COMM_MB_CTR__M 0x1 +#define CE_REG_COMM_MB_CTR_OFF 0x0 +#define CE_REG_COMM_MB_CTR_ON 0x1 +#define CE_REG_COMM_MB_OBS__B 1 +#define CE_REG_COMM_MB_OBS__W 1 +#define CE_REG_COMM_MB_OBS__M 0x2 +#define CE_REG_COMM_MB_OBS_OFF 0x0 +#define CE_REG_COMM_MB_OBS_ON 0x2 +#define CE_REG_COMM_MB_OBS_SEL__B 2 +#define CE_REG_COMM_MB_OBS_SEL__W 2 +#define CE_REG_COMM_MB_OBS_SEL__M 0xC +#define CE_REG_COMM_MB_OBS_SEL_FI 0x0 +#define CE_REG_COMM_MB_OBS_SEL_TP 0x4 +#define CE_REG_COMM_MB_OBS_SEL_TI 0x8 +#define CE_REG_COMM_MB_OBS_SEL_FR 0x8 + +#define CE_REG_COMM_SERVICE0__A 0x1810003 +#define CE_REG_COMM_SERVICE0__W 10 +#define CE_REG_COMM_SERVICE0__M 0x3FF +#define CE_REG_COMM_SERVICE0_FT__B 8 +#define CE_REG_COMM_SERVICE0_FT__W 1 +#define CE_REG_COMM_SERVICE0_FT__M 0x100 + +#define CE_REG_COMM_SERVICE1__A 0x1810004 +#define CE_REG_COMM_SERVICE1__W 11 +#define CE_REG_COMM_SERVICE1__M 0x7FF + +#define CE_REG_COMM_INT_STA__A 0x1810007 +#define CE_REG_COMM_INT_STA__W 3 +#define CE_REG_COMM_INT_STA__M 0x7 +#define CE_REG_COMM_INT_STA_CE_PE__B 0 +#define CE_REG_COMM_INT_STA_CE_PE__W 1 +#define CE_REG_COMM_INT_STA_CE_PE__M 0x1 +#define CE_REG_COMM_INT_STA_CE_IR__B 1 +#define CE_REG_COMM_INT_STA_CE_IR__W 1 +#define CE_REG_COMM_INT_STA_CE_IR__M 0x2 +#define CE_REG_COMM_INT_STA_CE_FI__B 2 +#define CE_REG_COMM_INT_STA_CE_FI__W 1 +#define CE_REG_COMM_INT_STA_CE_FI__M 0x4 + + +#define CE_REG_COMM_INT_MSK__A 0x1810008 +#define CE_REG_COMM_INT_MSK__W 3 +#define CE_REG_COMM_INT_MSK__M 0x7 +#define CE_REG_COMM_INT_MSK_CE_PE__B 0 +#define CE_REG_COMM_INT_MSK_CE_PE__W 1 +#define CE_REG_COMM_INT_MSK_CE_PE__M 0x1 +#define CE_REG_COMM_INT_MSK_CE_IR__B 1 +#define CE_REG_COMM_INT_MSK_CE_IR__W 1 +#define CE_REG_COMM_INT_MSK_CE_IR__M 0x2 +#define CE_REG_COMM_INT_MSK_CE_FI__B 2 +#define CE_REG_COMM_INT_MSK_CE_FI__W 1 +#define CE_REG_COMM_INT_MSK_CE_FI__M 0x4 + + +#define CE_REG_2K__A 0x1810010 +#define CE_REG_2K__W 1 +#define CE_REG_2K__M 0x1 +#define CE_REG_2K_INIT 0x0 + + +#define CE_REG_TAPSET__A 0x1810011 +#define CE_REG_TAPSET__W 2 +#define CE_REG_TAPSET__M 0x3 + + + +#define CE_REG_TAPSET_MOTION_INIT 0x0 + +#define CE_REG_TAPSET_MOTION_NO 0x0 + +#define CE_REG_TAPSET_MOTION_LOW 0x1 + +#define CE_REG_TAPSET_MOTION_HIGH 0x2 + +#define CE_REG_TAPSET_MOTION_UNDEFINED 0x3 + + +#define CE_REG_AVG_POW__A 0x1810012 +#define CE_REG_AVG_POW__W 8 +#define CE_REG_AVG_POW__M 0xFF +#define CE_REG_AVG_POW_INIT 0x0 + + +#define CE_REG_MAX_POW__A 0x1810013 +#define CE_REG_MAX_POW__W 8 +#define CE_REG_MAX_POW__M 0xFF +#define CE_REG_MAX_POW_INIT 0x0 + + +#define CE_REG_ATT__A 0x1810014 +#define CE_REG_ATT__W 8 +#define CE_REG_ATT__M 0xFF +#define CE_REG_ATT_INIT 0x0 + + +#define CE_REG_NRED__A 0x1810015 +#define CE_REG_NRED__W 6 +#define CE_REG_NRED__M 0x3F +#define CE_REG_NRED_INIT 0x0 + + +#define CE_REG_PU_SIGN__A 0x1810020 +#define CE_REG_PU_SIGN__W 1 +#define CE_REG_PU_SIGN__M 0x1 +#define CE_REG_PU_SIGN_INIT 0x0 + + +#define CE_REG_PU_MIX__A 0x1810021 +#define CE_REG_PU_MIX__W 7 +#define CE_REG_PU_MIX__M 0x7F +#define CE_REG_PU_MIX_INIT 0x0 + + +#define CE_REG_PB_PILOT_REQ__A 0x1810030 +#define CE_REG_PB_PILOT_REQ__W 15 +#define CE_REG_PB_PILOT_REQ__M 0x7FFF +#define CE_REG_PB_PILOT_REQ_INIT 0x0 +#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 +#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 +#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 +#define CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 +#define CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 +#define CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF + + +#define CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 +#define CE_REG_PB_PILOT_REQ_VALID__W 1 +#define CE_REG_PB_PILOT_REQ_VALID__M 0x1 +#define CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 + + +#define CE_REG_PB_FREEZE__A 0x1810032 +#define CE_REG_PB_FREEZE__W 1 +#define CE_REG_PB_FREEZE__M 0x1 +#define CE_REG_PB_FREEZE_INIT 0x0 + + +#define CE_REG_PB_PILOT_EXP__A 0x1810038 +#define CE_REG_PB_PILOT_EXP__W 4 +#define CE_REG_PB_PILOT_EXP__M 0xF +#define CE_REG_PB_PILOT_EXP_INIT 0x0 + + +#define CE_REG_PB_PILOT_REAL__A 0x1810039 +#define CE_REG_PB_PILOT_REAL__W 10 +#define CE_REG_PB_PILOT_REAL__M 0x3FF +#define CE_REG_PB_PILOT_REAL_INIT 0x0 + + +#define CE_REG_PB_PILOT_IMAG__A 0x181003A +#define CE_REG_PB_PILOT_IMAG__W 10 +#define CE_REG_PB_PILOT_IMAG__M 0x3FF +#define CE_REG_PB_PILOT_IMAG_INIT 0x0 + + +#define CE_REG_PB_SMBNR__A 0x181003B +#define CE_REG_PB_SMBNR__W 5 +#define CE_REG_PB_SMBNR__M 0x1F +#define CE_REG_PB_SMBNR_INIT 0x0 + + +#define CE_REG_NE_PILOT_REQ__A 0x1810040 +#define CE_REG_NE_PILOT_REQ__W 12 +#define CE_REG_NE_PILOT_REQ__M 0xFFF +#define CE_REG_NE_PILOT_REQ_INIT 0x0 + + +#define CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 +#define CE_REG_NE_PILOT_REQ_VALID__W 2 +#define CE_REG_NE_PILOT_REQ_VALID__M 0x3 +#define CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 +#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 +#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 +#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 +#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 +#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 +#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 + + +#define CE_REG_NE_PILOT_DATA__A 0x1810042 +#define CE_REG_NE_PILOT_DATA__W 10 +#define CE_REG_NE_PILOT_DATA__M 0x3FF +#define CE_REG_NE_PILOT_DATA_INIT 0x0 + + +#define CE_REG_NE_ERR_SELECT__A 0x1810043 +#define CE_REG_NE_ERR_SELECT__W 3 +#define CE_REG_NE_ERR_SELECT__M 0x7 +#define CE_REG_NE_ERR_SELECT_INIT 0x0 + +#define CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 +#define CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 +#define CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 + +#define CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 +#define CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 +#define CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 + +#define CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 +#define CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 +#define CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 + + +#define CE_REG_NE_TD_CAL__A 0x1810044 +#define CE_REG_NE_TD_CAL__W 9 +#define CE_REG_NE_TD_CAL__M 0x1FF +#define CE_REG_NE_TD_CAL_INIT 0x0 + + +#define CE_REG_NE_FD_CAL__A 0x1810045 +#define CE_REG_NE_FD_CAL__W 9 +#define CE_REG_NE_FD_CAL__M 0x1FF +#define CE_REG_NE_FD_CAL_INIT 0x0 + + +#define CE_REG_NE_MIXAVG__A 0x1810046 +#define CE_REG_NE_MIXAVG__W 3 +#define CE_REG_NE_MIXAVG__M 0x7 +#define CE_REG_NE_MIXAVG_INIT 0x0 + + +#define CE_REG_NE_NUPD_OFS__A 0x1810047 +#define CE_REG_NE_NUPD_OFS__W 7 +#define CE_REG_NE_NUPD_OFS__M 0x7F +#define CE_REG_NE_NUPD_OFS_INIT 0x0 + + +#define CE_REG_NE_TD_POW__A 0x1810048 +#define CE_REG_NE_TD_POW__W 15 +#define CE_REG_NE_TD_POW__M 0x7FFF +#define CE_REG_NE_TD_POW_INIT 0x0 + +#define CE_REG_NE_TD_POW_EXPONENT__B 10 +#define CE_REG_NE_TD_POW_EXPONENT__W 5 +#define CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 + +#define CE_REG_NE_TD_POW_MANTISSA__B 0 +#define CE_REG_NE_TD_POW_MANTISSA__W 10 +#define CE_REG_NE_TD_POW_MANTISSA__M 0x3FF + + +#define CE_REG_NE_FD_POW__A 0x1810049 +#define CE_REG_NE_FD_POW__W 15 +#define CE_REG_NE_FD_POW__M 0x7FFF +#define CE_REG_NE_FD_POW_INIT 0x0 + +#define CE_REG_NE_FD_POW_EXPONENT__B 10 +#define CE_REG_NE_FD_POW_EXPONENT__W 5 +#define CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 + +#define CE_REG_NE_FD_POW_MANTISSA__B 0 +#define CE_REG_NE_FD_POW_MANTISSA__W 10 +#define CE_REG_NE_FD_POW_MANTISSA__M 0x3FF + + +#define CE_REG_NE_NEXP_AVG__A 0x181004A +#define CE_REG_NE_NEXP_AVG__W 8 +#define CE_REG_NE_NEXP_AVG__M 0xFF +#define CE_REG_NE_NEXP_AVG_INIT 0x0 + + +#define CE_REG_NE_OFFSET__A 0x181004B +#define CE_REG_NE_OFFSET__W 9 +#define CE_REG_NE_OFFSET__M 0x1FF +#define CE_REG_NE_OFFSET_INIT 0x0 + + +#define CE_REG_PE_NEXP_OFFS__A 0x1810050 +#define CE_REG_PE_NEXP_OFFS__W 8 +#define CE_REG_PE_NEXP_OFFS__M 0xFF +#define CE_REG_PE_NEXP_OFFS_INIT 0x0 + + +#define CE_REG_PE_TIMESHIFT__A 0x1810051 +#define CE_REG_PE_TIMESHIFT__W 14 +#define CE_REG_PE_TIMESHIFT__M 0x3FFF +#define CE_REG_PE_TIMESHIFT_INIT 0x0 + + +#define CE_REG_PE_DIF_REAL_L__A 0x1810052 +#define CE_REG_PE_DIF_REAL_L__W 16 +#define CE_REG_PE_DIF_REAL_L__M 0xFFFF +#define CE_REG_PE_DIF_REAL_L_INIT 0x0 + + +#define CE_REG_PE_DIF_IMAG_L__A 0x1810053 +#define CE_REG_PE_DIF_IMAG_L__W 16 +#define CE_REG_PE_DIF_IMAG_L__M 0xFFFF +#define CE_REG_PE_DIF_IMAG_L_INIT 0x0 + + +#define CE_REG_PE_DIF_REAL_R__A 0x1810054 +#define CE_REG_PE_DIF_REAL_R__W 16 +#define CE_REG_PE_DIF_REAL_R__M 0xFFFF +#define CE_REG_PE_DIF_REAL_R_INIT 0x0 + + +#define CE_REG_PE_DIF_IMAG_R__A 0x1810055 +#define CE_REG_PE_DIF_IMAG_R__W 16 +#define CE_REG_PE_DIF_IMAG_R__M 0xFFFF +#define CE_REG_PE_DIF_IMAG_R_INIT 0x0 + + +#define CE_REG_PE_ABS_REAL_L__A 0x1810056 +#define CE_REG_PE_ABS_REAL_L__W 16 +#define CE_REG_PE_ABS_REAL_L__M 0xFFFF +#define CE_REG_PE_ABS_REAL_L_INIT 0x0 + + +#define CE_REG_PE_ABS_IMAG_L__A 0x1810057 +#define CE_REG_PE_ABS_IMAG_L__W 16 +#define CE_REG_PE_ABS_IMAG_L__M 0xFFFF +#define CE_REG_PE_ABS_IMAG_L_INIT 0x0 + + +#define CE_REG_PE_ABS_REAL_R__A 0x1810058 +#define CE_REG_PE_ABS_REAL_R__W 16 +#define CE_REG_PE_ABS_REAL_R__M 0xFFFF +#define CE_REG_PE_ABS_REAL_R_INIT 0x0 + + +#define CE_REG_PE_ABS_IMAG_R__A 0x1810059 +#define CE_REG_PE_ABS_IMAG_R__W 16 +#define CE_REG_PE_ABS_IMAG_R__M 0xFFFF +#define CE_REG_PE_ABS_IMAG_R_INIT 0x0 + + +#define CE_REG_PE_ABS_EXP_L__A 0x181005A +#define CE_REG_PE_ABS_EXP_L__W 5 +#define CE_REG_PE_ABS_EXP_L__M 0x1F +#define CE_REG_PE_ABS_EXP_L_INIT 0x0 + + +#define CE_REG_PE_ABS_EXP_R__A 0x181005B +#define CE_REG_PE_ABS_EXP_R__W 5 +#define CE_REG_PE_ABS_EXP_R__M 0x1F +#define CE_REG_PE_ABS_EXP_R_INIT 0x0 + + +#define CE_REG_TP_UPDATE_MODE__A 0x1810060 +#define CE_REG_TP_UPDATE_MODE__W 1 +#define CE_REG_TP_UPDATE_MODE__M 0x1 +#define CE_REG_TP_UPDATE_MODE_INIT 0x0 + + +#define CE_REG_TP_LMS_TAP_ON__A 0x1810061 +#define CE_REG_TP_LMS_TAP_ON__W 1 +#define CE_REG_TP_LMS_TAP_ON__M 0x1 + +#define CE_REG_TP_A0_TAP_NEW__A 0x1810064 +#define CE_REG_TP_A0_TAP_NEW__W 10 +#define CE_REG_TP_A0_TAP_NEW__M 0x3FF + +#define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 +#define CE_REG_TP_A0_TAP_NEW_VALID__W 1 +#define CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 + +#define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 +#define CE_REG_TP_A0_MU_LMS_STEP__W 5 +#define CE_REG_TP_A0_MU_LMS_STEP__M 0x1F + +#define CE_REG_TP_A0_TAP_CURR__A 0x1810067 +#define CE_REG_TP_A0_TAP_CURR__W 10 +#define CE_REG_TP_A0_TAP_CURR__M 0x3FF + +#define CE_REG_TP_A1_TAP_NEW__A 0x1810068 +#define CE_REG_TP_A1_TAP_NEW__W 10 +#define CE_REG_TP_A1_TAP_NEW__M 0x3FF + +#define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 +#define CE_REG_TP_A1_TAP_NEW_VALID__W 1 +#define CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 + +#define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A +#define CE_REG_TP_A1_MU_LMS_STEP__W 5 +#define CE_REG_TP_A1_MU_LMS_STEP__M 0x1F + +#define CE_REG_TP_A1_TAP_CURR__A 0x181006B +#define CE_REG_TP_A1_TAP_CURR__W 10 +#define CE_REG_TP_A1_TAP_CURR__M 0x3FF + +#define CE_REG_TP_DOPP_ENERGY__A 0x181006C +#define CE_REG_TP_DOPP_ENERGY__W 15 +#define CE_REG_TP_DOPP_ENERGY__M 0x7FFF +#define CE_REG_TP_DOPP_ENERGY_INIT 0x0 + +#define CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 +#define CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 +#define CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 + +#define CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 +#define CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 +#define CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF + + +#define CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D +#define CE_REG_TP_DOPP_DIFF_ENERGY__W 15 +#define CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF +#define CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 + +#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 +#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 +#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 + +#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 +#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 +#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF + + +#define CE_REG_TP_A0_TAP_ENERGY__A 0x181006E +#define CE_REG_TP_A0_TAP_ENERGY__W 15 +#define CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF +#define CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 + +#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 +#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 +#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 + +#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 +#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 +#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF + + +#define CE_REG_TP_A1_TAP_ENERGY__A 0x181006F +#define CE_REG_TP_A1_TAP_ENERGY__W 15 +#define CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF +#define CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 + +#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 +#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 +#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 + +#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 +#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 +#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF + + +#define CE_REG_TI_NEXP_OFFS__A 0x1810070 +#define CE_REG_TI_NEXP_OFFS__W 8 +#define CE_REG_TI_NEXP_OFFS__M 0xFF +#define CE_REG_TI_NEXP_OFFS_INIT 0x0 + + +#define CE_REG_TI_PEAK__A 0x1810071 +#define CE_REG_TI_PEAK__W 8 +#define CE_REG_TI_PEAK__M 0xFF +#define CE_REG_TI_PEAK_INIT 0x0 + + +#define CE_REG_FI_SHT_INCR__A 0x1810090 +#define CE_REG_FI_SHT_INCR__W 7 +#define CE_REG_FI_SHT_INCR__M 0x7F +#define CE_REG_FI_SHT_INCR_INIT 0x9 + + +#define CE_REG_FI_EXP_NORM__A 0x1810091 +#define CE_REG_FI_EXP_NORM__W 4 +#define CE_REG_FI_EXP_NORM__M 0xF +#define CE_REG_FI_EXP_NORM_INIT 0x4 + + +#define CE_REG_FI_SUPR_VAL__A 0x1810092 +#define CE_REG_FI_SUPR_VAL__W 1 +#define CE_REG_FI_SUPR_VAL__M 0x1 +#define CE_REG_FI_SUPR_VAL_INIT 0x1 + + +#define CE_REG_IR_INPUTSEL__A 0x18100A0 +#define CE_REG_IR_INPUTSEL__W 1 +#define CE_REG_IR_INPUTSEL__M 0x1 +#define CE_REG_IR_INPUTSEL_INIT 0x0 + + +#define CE_REG_IR_STARTPOS__A 0x18100A1 +#define CE_REG_IR_STARTPOS__W 8 +#define CE_REG_IR_STARTPOS__M 0xFF +#define CE_REG_IR_STARTPOS_INIT 0x0 + + +#define CE_REG_IR_NEXP_THRES__A 0x18100A2 +#define CE_REG_IR_NEXP_THRES__W 8 +#define CE_REG_IR_NEXP_THRES__M 0xFF +#define CE_REG_IR_NEXP_THRES_INIT 0x0 + + +#define CE_REG_IR_LENGTH__A 0x18100A3 +#define CE_REG_IR_LENGTH__W 4 +#define CE_REG_IR_LENGTH__M 0xF +#define CE_REG_IR_LENGTH_INIT 0x0 + + +#define CE_REG_IR_FREQ__A 0x18100A4 +#define CE_REG_IR_FREQ__W 11 +#define CE_REG_IR_FREQ__M 0x7FF +#define CE_REG_IR_FREQ_INIT 0x0 + + +#define CE_REG_IR_FREQINC__A 0x18100A5 +#define CE_REG_IR_FREQINC__W 11 +#define CE_REG_IR_FREQINC__M 0x7FF +#define CE_REG_IR_FREQINC_INIT 0x0 + + +#define CE_REG_IR_KAISINC__A 0x18100A6 +#define CE_REG_IR_KAISINC__W 15 +#define CE_REG_IR_KAISINC__M 0x7FFF +#define CE_REG_IR_KAISINC_INIT 0x0 + + +#define CE_REG_IR_CTL__A 0x18100A7 +#define CE_REG_IR_CTL__W 3 +#define CE_REG_IR_CTL__M 0x7 +#define CE_REG_IR_CTL_INIT 0x0 + + +#define CE_REG_IR_REAL__A 0x18100A8 +#define CE_REG_IR_REAL__W 16 +#define CE_REG_IR_REAL__M 0xFFFF +#define CE_REG_IR_REAL_INIT 0x0 + + +#define CE_REG_IR_IMAG__A 0x18100A9 +#define CE_REG_IR_IMAG__W 16 +#define CE_REG_IR_IMAG__M 0xFFFF +#define CE_REG_IR_IMAG_INIT 0x0 + + +#define CE_REG_IR_INDEX__A 0x18100AA +#define CE_REG_IR_INDEX__W 12 +#define CE_REG_IR_INDEX__M 0xFFF +#define CE_REG_IR_INDEX_INIT 0x0 + + + + +#define CE_REG_FR_TREAL00__A 0x1820010 +#define CE_REG_FR_TREAL00__W 11 +#define CE_REG_FR_TREAL00__M 0x7FF +#define CE_REG_FR_TREAL00_INIT 0x52 + + +#define CE_REG_FR_TIMAG00__A 0x1820011 +#define CE_REG_FR_TIMAG00__W 11 +#define CE_REG_FR_TIMAG00__M 0x7FF +#define CE_REG_FR_TIMAG00_INIT 0x0 + + +#define CE_REG_FR_TREAL01__A 0x1820012 +#define CE_REG_FR_TREAL01__W 11 +#define CE_REG_FR_TREAL01__M 0x7FF +#define CE_REG_FR_TREAL01_INIT 0x52 + + +#define CE_REG_FR_TIMAG01__A 0x1820013 +#define CE_REG_FR_TIMAG01__W 11 +#define CE_REG_FR_TIMAG01__M 0x7FF +#define CE_REG_FR_TIMAG01_INIT 0x0 + + +#define CE_REG_FR_TREAL02__A 0x1820014 +#define CE_REG_FR_TREAL02__W 11 +#define CE_REG_FR_TREAL02__M 0x7FF +#define CE_REG_FR_TREAL02_INIT 0x52 + + +#define CE_REG_FR_TIMAG02__A 0x1820015 +#define CE_REG_FR_TIMAG02__W 11 +#define CE_REG_FR_TIMAG02__M 0x7FF +#define CE_REG_FR_TIMAG02_INIT 0x0 + + +#define CE_REG_FR_TREAL03__A 0x1820016 +#define CE_REG_FR_TREAL03__W 11 +#define CE_REG_FR_TREAL03__M 0x7FF +#define CE_REG_FR_TREAL03_INIT 0x52 + + +#define CE_REG_FR_TIMAG03__A 0x1820017 +#define CE_REG_FR_TIMAG03__W 11 +#define CE_REG_FR_TIMAG03__M 0x7FF +#define CE_REG_FR_TIMAG03_INIT 0x0 + + +#define CE_REG_FR_TREAL04__A 0x1820018 +#define CE_REG_FR_TREAL04__W 11 +#define CE_REG_FR_TREAL04__M 0x7FF +#define CE_REG_FR_TREAL04_INIT 0x52 + + +#define CE_REG_FR_TIMAG04__A 0x1820019 +#define CE_REG_FR_TIMAG04__W 11 +#define CE_REG_FR_TIMAG04__M 0x7FF +#define CE_REG_FR_TIMAG04_INIT 0x0 + + +#define CE_REG_FR_TREAL05__A 0x182001A +#define CE_REG_FR_TREAL05__W 11 +#define CE_REG_FR_TREAL05__M 0x7FF +#define CE_REG_FR_TREAL05_INIT 0x52 + + +#define CE_REG_FR_TIMAG05__A 0x182001B +#define CE_REG_FR_TIMAG05__W 11 +#define CE_REG_FR_TIMAG05__M 0x7FF +#define CE_REG_FR_TIMAG05_INIT 0x0 + + +#define CE_REG_FR_TREAL06__A 0x182001C +#define CE_REG_FR_TREAL06__W 11 +#define CE_REG_FR_TREAL06__M 0x7FF +#define CE_REG_FR_TREAL06_INIT 0x52 + + +#define CE_REG_FR_TIMAG06__A 0x182001D +#define CE_REG_FR_TIMAG06__W 11 +#define CE_REG_FR_TIMAG06__M 0x7FF +#define CE_REG_FR_TIMAG06_INIT 0x0 + + +#define CE_REG_FR_TREAL07__A 0x182001E +#define CE_REG_FR_TREAL07__W 11 +#define CE_REG_FR_TREAL07__M 0x7FF +#define CE_REG_FR_TREAL07_INIT 0x52 + + +#define CE_REG_FR_TIMAG07__A 0x182001F +#define CE_REG_FR_TIMAG07__W 11 +#define CE_REG_FR_TIMAG07__M 0x7FF +#define CE_REG_FR_TIMAG07_INIT 0x0 + + +#define CE_REG_FR_TREAL08__A 0x1820020 +#define CE_REG_FR_TREAL08__W 11 +#define CE_REG_FR_TREAL08__M 0x7FF +#define CE_REG_FR_TREAL08_INIT 0x52 + + +#define CE_REG_FR_TIMAG08__A 0x1820021 +#define CE_REG_FR_TIMAG08__W 11 +#define CE_REG_FR_TIMAG08__M 0x7FF +#define CE_REG_FR_TIMAG08_INIT 0x0 + + +#define CE_REG_FR_TREAL09__A 0x1820022 +#define CE_REG_FR_TREAL09__W 11 +#define CE_REG_FR_TREAL09__M 0x7FF +#define CE_REG_FR_TREAL09_INIT 0x52 + + +#define CE_REG_FR_TIMAG09__A 0x1820023 +#define CE_REG_FR_TIMAG09__W 11 +#define CE_REG_FR_TIMAG09__M 0x7FF +#define CE_REG_FR_TIMAG09_INIT 0x0 + + +#define CE_REG_FR_TREAL10__A 0x1820024 +#define CE_REG_FR_TREAL10__W 11 +#define CE_REG_FR_TREAL10__M 0x7FF +#define CE_REG_FR_TREAL10_INIT 0x52 + + +#define CE_REG_FR_TIMAG10__A 0x1820025 +#define CE_REG_FR_TIMAG10__W 11 +#define CE_REG_FR_TIMAG10__M 0x7FF +#define CE_REG_FR_TIMAG10_INIT 0x0 + + +#define CE_REG_FR_TREAL11__A 0x1820026 +#define CE_REG_FR_TREAL11__W 11 +#define CE_REG_FR_TREAL11__M 0x7FF +#define CE_REG_FR_TREAL11_INIT 0x52 + + +#define CE_REG_FR_TIMAG11__A 0x1820027 +#define CE_REG_FR_TIMAG11__W 11 +#define CE_REG_FR_TIMAG11__M 0x7FF +#define CE_REG_FR_TIMAG11_INIT 0x0 + + +#define CE_REG_FR_MID_TAP__A 0x1820028 +#define CE_REG_FR_MID_TAP__W 11 +#define CE_REG_FR_MID_TAP__M 0x7FF +#define CE_REG_FR_MID_TAP_INIT 0x51 + + +#define CE_REG_FR_SQS_G00__A 0x1820029 +#define CE_REG_FR_SQS_G00__W 8 +#define CE_REG_FR_SQS_G00__M 0xFF +#define CE_REG_FR_SQS_G00_INIT 0xB + + +#define CE_REG_FR_SQS_G01__A 0x182002A +#define CE_REG_FR_SQS_G01__W 8 +#define CE_REG_FR_SQS_G01__M 0xFF +#define CE_REG_FR_SQS_G01_INIT 0xB + + +#define CE_REG_FR_SQS_G02__A 0x182002B +#define CE_REG_FR_SQS_G02__W 8 +#define CE_REG_FR_SQS_G02__M 0xFF +#define CE_REG_FR_SQS_G02_INIT 0xB + + +#define CE_REG_FR_SQS_G03__A 0x182002C +#define CE_REG_FR_SQS_G03__W 8 +#define CE_REG_FR_SQS_G03__M 0xFF +#define CE_REG_FR_SQS_G03_INIT 0xB + + +#define CE_REG_FR_SQS_G04__A 0x182002D +#define CE_REG_FR_SQS_G04__W 8 +#define CE_REG_FR_SQS_G04__M 0xFF +#define CE_REG_FR_SQS_G04_INIT 0xB + + +#define CE_REG_FR_SQS_G05__A 0x182002E +#define CE_REG_FR_SQS_G05__W 8 +#define CE_REG_FR_SQS_G05__M 0xFF +#define CE_REG_FR_SQS_G05_INIT 0xB + + +#define CE_REG_FR_SQS_G06__A 0x182002F +#define CE_REG_FR_SQS_G06__W 8 +#define CE_REG_FR_SQS_G06__M 0xFF +#define CE_REG_FR_SQS_G06_INIT 0xB + + +#define CE_REG_FR_SQS_G07__A 0x1820030 +#define CE_REG_FR_SQS_G07__W 8 +#define CE_REG_FR_SQS_G07__M 0xFF +#define CE_REG_FR_SQS_G07_INIT 0xB + + +#define CE_REG_FR_SQS_G08__A 0x1820031 +#define CE_REG_FR_SQS_G08__W 8 +#define CE_REG_FR_SQS_G08__M 0xFF +#define CE_REG_FR_SQS_G08_INIT 0xB + + +#define CE_REG_FR_SQS_G09__A 0x1820032 +#define CE_REG_FR_SQS_G09__W 8 +#define CE_REG_FR_SQS_G09__M 0xFF +#define CE_REG_FR_SQS_G09_INIT 0xB + + +#define CE_REG_FR_SQS_G10__A 0x1820033 +#define CE_REG_FR_SQS_G10__W 8 +#define CE_REG_FR_SQS_G10__M 0xFF +#define CE_REG_FR_SQS_G10_INIT 0xB + + +#define CE_REG_FR_SQS_G11__A 0x1820034 +#define CE_REG_FR_SQS_G11__W 8 +#define CE_REG_FR_SQS_G11__M 0xFF +#define CE_REG_FR_SQS_G11_INIT 0xB + + +#define CE_REG_FR_SQS_G12__A 0x1820035 +#define CE_REG_FR_SQS_G12__W 8 +#define CE_REG_FR_SQS_G12__M 0xFF +#define CE_REG_FR_SQS_G12_INIT 0x5 + + +#define CE_REG_FR_RIO_G00__A 0x1820036 +#define CE_REG_FR_RIO_G00__W 9 +#define CE_REG_FR_RIO_G00__M 0x1FF +#define CE_REG_FR_RIO_G00_INIT 0x1FF + + +#define CE_REG_FR_RIO_G01__A 0x1820037 +#define CE_REG_FR_RIO_G01__W 9 +#define CE_REG_FR_RIO_G01__M 0x1FF +#define CE_REG_FR_RIO_G01_INIT 0x190 + + +#define CE_REG_FR_RIO_G02__A 0x1820038 +#define CE_REG_FR_RIO_G02__W 9 +#define CE_REG_FR_RIO_G02__M 0x1FF +#define CE_REG_FR_RIO_G02_INIT 0x10B + + +#define CE_REG_FR_RIO_G03__A 0x1820039 +#define CE_REG_FR_RIO_G03__W 9 +#define CE_REG_FR_RIO_G03__M 0x1FF +#define CE_REG_FR_RIO_G03_INIT 0xC8 + + +#define CE_REG_FR_RIO_G04__A 0x182003A +#define CE_REG_FR_RIO_G04__W 9 +#define CE_REG_FR_RIO_G04__M 0x1FF +#define CE_REG_FR_RIO_G04_INIT 0xA0 + + +#define CE_REG_FR_RIO_G05__A 0x182003B +#define CE_REG_FR_RIO_G05__W 9 +#define CE_REG_FR_RIO_G05__M 0x1FF +#define CE_REG_FR_RIO_G05_INIT 0x85 + + +#define CE_REG_FR_RIO_G06__A 0x182003C +#define CE_REG_FR_RIO_G06__W 9 +#define CE_REG_FR_RIO_G06__M 0x1FF +#define CE_REG_FR_RIO_G06_INIT 0x72 + + +#define CE_REG_FR_RIO_G07__A 0x182003D +#define CE_REG_FR_RIO_G07__W 9 +#define CE_REG_FR_RIO_G07__M 0x1FF +#define CE_REG_FR_RIO_G07_INIT 0x64 + + +#define CE_REG_FR_RIO_G08__A 0x182003E +#define CE_REG_FR_RIO_G08__W 9 +#define CE_REG_FR_RIO_G08__M 0x1FF +#define CE_REG_FR_RIO_G08_INIT 0x59 + + +#define CE_REG_FR_RIO_G09__A 0x182003F +#define CE_REG_FR_RIO_G09__W 9 +#define CE_REG_FR_RIO_G09__M 0x1FF +#define CE_REG_FR_RIO_G09_INIT 0x50 + + +#define CE_REG_FR_RIO_G10__A 0x1820040 +#define CE_REG_FR_RIO_G10__W 9 +#define CE_REG_FR_RIO_G10__M 0x1FF +#define CE_REG_FR_RIO_G10_INIT 0x49 + + +#define CE_REG_FR_MODE__A 0x1820041 +#define CE_REG_FR_MODE__W 6 +#define CE_REG_FR_MODE__M 0x3F + +#define CE_REG_FR_MODE_UPDATE_ENABLE__B 0 +#define CE_REG_FR_MODE_UPDATE_ENABLE__W 1 +#define CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 + +#define CE_REG_FR_MODE_ERROR_SHIFT__B 1 +#define CE_REG_FR_MODE_ERROR_SHIFT__W 1 +#define CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 + +#define CE_REG_FR_MODE_NEXP_UPDATE__B 2 +#define CE_REG_FR_MODE_NEXP_UPDATE__W 1 +#define CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 + +#define CE_REG_FR_MODE_MANUAL_SHIFT__B 3 +#define CE_REG_FR_MODE_MANUAL_SHIFT__W 1 +#define CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 + +#define CE_REG_FR_MODE_SQUASH_MODE__B 4 +#define CE_REG_FR_MODE_SQUASH_MODE__W 1 +#define CE_REG_FR_MODE_SQUASH_MODE__M 0x10 + +#define CE_REG_FR_MODE_UPDATE_MODE__B 5 +#define CE_REG_FR_MODE_UPDATE_MODE__W 1 +#define CE_REG_FR_MODE_UPDATE_MODE__M 0x20 +#define CE_REG_FR_MODE_INIT 0x3E + + +#define CE_REG_FR_SQS_TRH__A 0x1820042 +#define CE_REG_FR_SQS_TRH__W 8 +#define CE_REG_FR_SQS_TRH__M 0xFF +#define CE_REG_FR_SQS_TRH_INIT 0x80 + + +#define CE_REG_FR_RIO_GAIN__A 0x1820043 +#define CE_REG_FR_RIO_GAIN__W 3 +#define CE_REG_FR_RIO_GAIN__M 0x7 +#define CE_REG_FR_RIO_GAIN_INIT 0x2 + + +#define CE_REG_FR_BYPASS__A 0x1820044 +#define CE_REG_FR_BYPASS__W 10 +#define CE_REG_FR_BYPASS__M 0x3FF + +#define CE_REG_FR_BYPASS_RUN_IN__B 0 +#define CE_REG_FR_BYPASS_RUN_IN__W 4 +#define CE_REG_FR_BYPASS_RUN_IN__M 0xF + +#define CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 +#define CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 +#define CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 + +#define CE_REG_FR_BYPASS_TOTAL__B 9 +#define CE_REG_FR_BYPASS_TOTAL__W 1 +#define CE_REG_FR_BYPASS_TOTAL__M 0x200 +#define CE_REG_FR_BYPASS_INIT 0x13B + + +#define CE_REG_FR_PM_SET__A 0x1820045 +#define CE_REG_FR_PM_SET__W 4 +#define CE_REG_FR_PM_SET__M 0xF +#define CE_REG_FR_PM_SET_INIT 0x4 + + +#define CE_REG_FR_ERR_SH__A 0x1820046 +#define CE_REG_FR_ERR_SH__W 4 +#define CE_REG_FR_ERR_SH__M 0xF +#define CE_REG_FR_ERR_SH_INIT 0x4 + + +#define CE_REG_FR_MAN_SH__A 0x1820047 +#define CE_REG_FR_MAN_SH__W 4 +#define CE_REG_FR_MAN_SH__M 0xF +#define CE_REG_FR_MAN_SH_INIT 0x7 + + +#define CE_REG_FR_TAP_SH__A 0x1820048 +#define CE_REG_FR_TAP_SH__W 3 +#define CE_REG_FR_TAP_SH__M 0x7 +#define CE_REG_FR_TAP_SH_INIT 0x3 + + +#define CE_REG_FR_CLIP__A 0x1820049 +#define CE_REG_FR_CLIP__W 9 +#define CE_REG_FR_CLIP__M 0x1FF +#define CE_REG_FR_CLIP_INIT 0x49 + + + +#define CE_PB_RAM__A 0x1830000 + + + +#define CE_NE_RAM__A 0x1840000 + + + + + +#define EQ_SID 0xE + + + + + +#define EQ_COMM_EXEC__A 0x1C00000 +#define EQ_COMM_EXEC__W 3 +#define EQ_COMM_EXEC__M 0x7 +#define EQ_COMM_EXEC_CTL__B 0 +#define EQ_COMM_EXEC_CTL__W 3 +#define EQ_COMM_EXEC_CTL__M 0x7 +#define EQ_COMM_EXEC_CTL_STOP 0x0 +#define EQ_COMM_EXEC_CTL_ACTIVE 0x1 +#define EQ_COMM_EXEC_CTL_HOLD 0x2 +#define EQ_COMM_EXEC_CTL_STEP 0x3 +#define EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define EQ_COMM_STATE__A 0x1C00001 +#define EQ_COMM_STATE__W 16 +#define EQ_COMM_STATE__M 0xFFFF +#define EQ_COMM_MB__A 0x1C00002 +#define EQ_COMM_MB__W 16 +#define EQ_COMM_MB__M 0xFFFF +#define EQ_COMM_SERVICE0__A 0x1C00003 +#define EQ_COMM_SERVICE0__W 16 +#define EQ_COMM_SERVICE0__M 0xFFFF +#define EQ_COMM_SERVICE1__A 0x1C00004 +#define EQ_COMM_SERVICE1__W 16 +#define EQ_COMM_SERVICE1__M 0xFFFF +#define EQ_COMM_INT_STA__A 0x1C00007 +#define EQ_COMM_INT_STA__W 16 +#define EQ_COMM_INT_STA__M 0xFFFF +#define EQ_COMM_INT_MSK__A 0x1C00008 +#define EQ_COMM_INT_MSK__W 16 +#define EQ_COMM_INT_MSK__M 0xFFFF + + + + + + +#define EQ_REG_COMM_EXEC__A 0x1C10000 +#define EQ_REG_COMM_EXEC__W 3 +#define EQ_REG_COMM_EXEC__M 0x7 +#define EQ_REG_COMM_EXEC_CTL__B 0 +#define EQ_REG_COMM_EXEC_CTL__W 3 +#define EQ_REG_COMM_EXEC_CTL__M 0x7 +#define EQ_REG_COMM_EXEC_CTL_STOP 0x0 +#define EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EQ_REG_COMM_EXEC_CTL_HOLD 0x2 +#define EQ_REG_COMM_EXEC_CTL_STEP 0x3 + +#define EQ_REG_COMM_STATE__A 0x1C10001 +#define EQ_REG_COMM_STATE__W 4 +#define EQ_REG_COMM_STATE__M 0xF + +#define EQ_REG_COMM_MB__A 0x1C10002 +#define EQ_REG_COMM_MB__W 6 +#define EQ_REG_COMM_MB__M 0x3F +#define EQ_REG_COMM_MB_CTR__B 0 +#define EQ_REG_COMM_MB_CTR__W 1 +#define EQ_REG_COMM_MB_CTR__M 0x1 +#define EQ_REG_COMM_MB_CTR_OFF 0x0 +#define EQ_REG_COMM_MB_CTR_ON 0x1 +#define EQ_REG_COMM_MB_OBS__B 1 +#define EQ_REG_COMM_MB_OBS__W 1 +#define EQ_REG_COMM_MB_OBS__M 0x2 +#define EQ_REG_COMM_MB_OBS_OFF 0x0 +#define EQ_REG_COMM_MB_OBS_ON 0x2 +#define EQ_REG_COMM_MB_CTR_MUX__B 2 +#define EQ_REG_COMM_MB_CTR_MUX__W 2 +#define EQ_REG_COMM_MB_CTR_MUX__M 0xC +#define EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 +#define EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 +#define EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 +#define EQ_REG_COMM_MB_OBS_MUX__B 4 +#define EQ_REG_COMM_MB_OBS_MUX__W 2 +#define EQ_REG_COMM_MB_OBS_MUX__M 0x30 +#define EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 +#define EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 +#define EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 +#define EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 + + +#define EQ_REG_COMM_SERVICE0__A 0x1C10003 +#define EQ_REG_COMM_SERVICE0__W 10 +#define EQ_REG_COMM_SERVICE0__M 0x3FF + +#define EQ_REG_COMM_SERVICE1__A 0x1C10004 +#define EQ_REG_COMM_SERVICE1__W 11 +#define EQ_REG_COMM_SERVICE1__M 0x7FF + +#define EQ_REG_COMM_INT_STA__A 0x1C10007 +#define EQ_REG_COMM_INT_STA__W 2 +#define EQ_REG_COMM_INT_STA__M 0x3 +#define EQ_REG_COMM_INT_STA_TPS_RDY__B 0 +#define EQ_REG_COMM_INT_STA_TPS_RDY__W 1 +#define EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 +#define EQ_REG_COMM_INT_STA_ERR_RDY__B 1 +#define EQ_REG_COMM_INT_STA_ERR_RDY__W 1 +#define EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 + + +#define EQ_REG_COMM_INT_MSK__A 0x1C10008 +#define EQ_REG_COMM_INT_MSK__W 2 +#define EQ_REG_COMM_INT_MSK__M 0x3 +#define EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 +#define EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 +#define EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 +#define EQ_REG_COMM_INT_MSK_MER_RDY__B 1 +#define EQ_REG_COMM_INT_MSK_MER_RDY__W 1 +#define EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 + + +#define EQ_REG_IS_MODE__A 0x1C10014 +#define EQ_REG_IS_MODE__W 4 +#define EQ_REG_IS_MODE__M 0xF +#define EQ_REG_IS_MODE_INIT 0x0 + +#define EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 +#define EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 +#define EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 +#define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 +#define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 + +#define EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 +#define EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 +#define EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 +#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 +#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 + + +#define EQ_REG_IS_GAIN_MAN__A 0x1C10015 +#define EQ_REG_IS_GAIN_MAN__W 10 +#define EQ_REG_IS_GAIN_MAN__M 0x3FF +#define EQ_REG_IS_GAIN_MAN_INIT 0x0 + + +#define EQ_REG_IS_GAIN_EXP__A 0x1C10016 +#define EQ_REG_IS_GAIN_EXP__W 5 +#define EQ_REG_IS_GAIN_EXP__M 0x1F +#define EQ_REG_IS_GAIN_EXP_INIT 0x0 + + +#define EQ_REG_IS_CLIP_EXP__A 0x1C10017 +#define EQ_REG_IS_CLIP_EXP__W 5 +#define EQ_REG_IS_CLIP_EXP__M 0x1F +#define EQ_REG_IS_CLIP_EXP_INIT 0x0 + + +#define EQ_REG_DV_MODE__A 0x1C1001E +#define EQ_REG_DV_MODE__W 4 +#define EQ_REG_DV_MODE__M 0xF +#define EQ_REG_DV_MODE_INIT 0x0 + +#define EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 +#define EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 +#define EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 +#define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 +#define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 + +#define EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 +#define EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 +#define EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 +#define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 +#define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 + +#define EQ_REG_DV_MODE_CLP_REA_ENA__B 2 +#define EQ_REG_DV_MODE_CLP_REA_ENA__W 1 +#define EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 +#define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 +#define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 + +#define EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 +#define EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 +#define EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 +#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 +#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 + + +#define EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F +#define EQ_REG_DV_POS_CLIP_DAT__W 16 +#define EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF + +#define EQ_REG_SN_MODE__A 0x1C10028 +#define EQ_REG_SN_MODE__W 8 +#define EQ_REG_SN_MODE__M 0xFF +#define EQ_REG_SN_MODE_INIT 0x0 + +#define EQ_REG_SN_MODE_MODE_0__B 0 +#define EQ_REG_SN_MODE_MODE_0__W 1 +#define EQ_REG_SN_MODE_MODE_0__M 0x1 +#define EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 + +#define EQ_REG_SN_MODE_MODE_1__B 1 +#define EQ_REG_SN_MODE_MODE_1__W 1 +#define EQ_REG_SN_MODE_MODE_1__M 0x2 +#define EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 + +#define EQ_REG_SN_MODE_MODE_2__B 2 +#define EQ_REG_SN_MODE_MODE_2__W 1 +#define EQ_REG_SN_MODE_MODE_2__M 0x4 +#define EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 + +#define EQ_REG_SN_MODE_MODE_3__B 3 +#define EQ_REG_SN_MODE_MODE_3__W 1 +#define EQ_REG_SN_MODE_MODE_3__M 0x8 +#define EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 + +#define EQ_REG_SN_MODE_MODE_4__B 4 +#define EQ_REG_SN_MODE_MODE_4__W 1 +#define EQ_REG_SN_MODE_MODE_4__M 0x10 +#define EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 + +#define EQ_REG_SN_MODE_MODE_5__B 5 +#define EQ_REG_SN_MODE_MODE_5__W 1 +#define EQ_REG_SN_MODE_MODE_5__M 0x20 +#define EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 + +#define EQ_REG_SN_MODE_MODE_6__B 6 +#define EQ_REG_SN_MODE_MODE_6__W 1 +#define EQ_REG_SN_MODE_MODE_6__M 0x40 +#define EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 +#define EQ_REG_SN_MODE_MODE_6_STATIC 0x40 + +#define EQ_REG_SN_MODE_MODE_7__B 7 +#define EQ_REG_SN_MODE_MODE_7__W 1 +#define EQ_REG_SN_MODE_MODE_7__M 0x80 +#define EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 +#define EQ_REG_SN_MODE_MODE_7_STATIC 0x80 + + +#define EQ_REG_SN_PFIX__A 0x1C10029 +#define EQ_REG_SN_PFIX__W 8 +#define EQ_REG_SN_PFIX__M 0xFF +#define EQ_REG_SN_PFIX_INIT 0x0 + + +#define EQ_REG_SN_CEGAIN__A 0x1C1002A +#define EQ_REG_SN_CEGAIN__W 8 +#define EQ_REG_SN_CEGAIN__M 0xFF +#define EQ_REG_SN_CEGAIN_INIT 0x0 + + +#define EQ_REG_SN_OFFSET__A 0x1C1002B +#define EQ_REG_SN_OFFSET__W 6 +#define EQ_REG_SN_OFFSET__M 0x3F +#define EQ_REG_SN_OFFSET_INIT 0x0 + + +#define EQ_REG_SN_NULLIFY__A 0x1C1002C +#define EQ_REG_SN_NULLIFY__W 6 +#define EQ_REG_SN_NULLIFY__M 0x3F +#define EQ_REG_SN_NULLIFY_INIT 0x0 + + +#define EQ_REG_SN_SQUASH__A 0x1C1002D +#define EQ_REG_SN_SQUASH__W 10 +#define EQ_REG_SN_SQUASH__M 0x3FF +#define EQ_REG_SN_SQUASH_INIT 0x0 + +#define EQ_REG_SN_SQUASH_MAN__B 0 +#define EQ_REG_SN_SQUASH_MAN__W 6 +#define EQ_REG_SN_SQUASH_MAN__M 0x3F + +#define EQ_REG_SN_SQUASH_EXP__B 6 +#define EQ_REG_SN_SQUASH_EXP__W 4 +#define EQ_REG_SN_SQUASH_EXP__M 0x3C0 + + + + +#define EQ_REG_RC_SEL_CAR__A 0x1C10032 +#define EQ_REG_RC_SEL_CAR__W 6 +#define EQ_REG_RC_SEL_CAR__M 0x3F +#define EQ_REG_RC_SEL_CAR_INIT 0x0 +#define EQ_REG_RC_SEL_CAR_DIV__B 0 +#define EQ_REG_RC_SEL_CAR_DIV__W 1 +#define EQ_REG_RC_SEL_CAR_DIV__M 0x1 +#define EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 +#define EQ_REG_RC_SEL_CAR_DIV_ON 0x1 + +#define EQ_REG_RC_SEL_CAR_PASS__B 1 +#define EQ_REG_RC_SEL_CAR_PASS__W 2 +#define EQ_REG_RC_SEL_CAR_PASS__M 0x6 +#define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 +#define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 +#define EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 +#define EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 + +#define EQ_REG_RC_SEL_CAR_LOCAL__B 3 +#define EQ_REG_RC_SEL_CAR_LOCAL__W 2 +#define EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 +#define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 +#define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 +#define EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 +#define EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 + +#define EQ_REG_RC_SEL_CAR_MEAS__B 5 +#define EQ_REG_RC_SEL_CAR_MEAS__W 1 +#define EQ_REG_RC_SEL_CAR_MEAS__M 0x20 +#define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 +#define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 + + +#define EQ_REG_RC_STS__A 0x1C10033 +#define EQ_REG_RC_STS__W 12 +#define EQ_REG_RC_STS__M 0xFFF + +#define EQ_REG_RC_STS_DIFF__B 0 +#define EQ_REG_RC_STS_DIFF__W 9 +#define EQ_REG_RC_STS_DIFF__M 0x1FF + +#define EQ_REG_RC_STS_FIRST__B 9 +#define EQ_REG_RC_STS_FIRST__W 1 +#define EQ_REG_RC_STS_FIRST__M 0x200 +#define EQ_REG_RC_STS_FIRST_A_CE 0x0 +#define EQ_REG_RC_STS_FIRST_B_DRI 0x200 + +#define EQ_REG_RC_STS_SELEC__B 10 +#define EQ_REG_RC_STS_SELEC__W 1 +#define EQ_REG_RC_STS_SELEC__M 0x400 +#define EQ_REG_RC_STS_SELEC_A_CE 0x0 +#define EQ_REG_RC_STS_SELEC_B_DRI 0x400 + +#define EQ_REG_RC_STS_OVERFLOW__B 11 +#define EQ_REG_RC_STS_OVERFLOW__W 1 +#define EQ_REG_RC_STS_OVERFLOW__M 0x800 +#define EQ_REG_RC_STS_OVERFLOW_NO 0x0 +#define EQ_REG_RC_STS_OVERFLOW_YES 0x800 + + +#define EQ_REG_OT_CONST__A 0x1C10046 +#define EQ_REG_OT_CONST__W 2 +#define EQ_REG_OT_CONST__M 0x3 +#define EQ_REG_OT_CONST_INIT 0x0 + + +#define EQ_REG_OT_ALPHA__A 0x1C10047 +#define EQ_REG_OT_ALPHA__W 2 +#define EQ_REG_OT_ALPHA__M 0x3 +#define EQ_REG_OT_ALPHA_INIT 0x0 + + +#define EQ_REG_OT_QNT_THRES0__A 0x1C10048 +#define EQ_REG_OT_QNT_THRES0__W 5 +#define EQ_REG_OT_QNT_THRES0__M 0x1F +#define EQ_REG_OT_QNT_THRES0_INIT 0x0 + + +#define EQ_REG_OT_QNT_THRES1__A 0x1C10049 +#define EQ_REG_OT_QNT_THRES1__W 5 +#define EQ_REG_OT_QNT_THRES1__M 0x1F +#define EQ_REG_OT_QNT_THRES1_INIT 0x0 + + +#define EQ_REG_OT_CSI_STEP__A 0x1C1004A +#define EQ_REG_OT_CSI_STEP__W 4 +#define EQ_REG_OT_CSI_STEP__M 0xF +#define EQ_REG_OT_CSI_STEP_INIT 0x0 + + +#define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B +#define EQ_REG_OT_CSI_OFFSET__W 7 +#define EQ_REG_OT_CSI_OFFSET__M 0x7F +#define EQ_REG_OT_CSI_OFFSET_INIT 0x0 + + + + +#define EQ_REG_TD_TPS_INIT__A 0x1C10050 +#define EQ_REG_TD_TPS_INIT__W 1 +#define EQ_REG_TD_TPS_INIT__M 0x1 +#define EQ_REG_TD_TPS_INIT_INIT 0x0 +#define EQ_REG_TD_TPS_INIT_POS 0x0 +#define EQ_REG_TD_TPS_INIT_NEG 0x1 + + +#define EQ_REG_TD_TPS_SYNC__A 0x1C10051 +#define EQ_REG_TD_TPS_SYNC__W 16 +#define EQ_REG_TD_TPS_SYNC__M 0xFFFF +#define EQ_REG_TD_TPS_SYNC_INIT 0x0 +#define EQ_REG_TD_TPS_SYNC_ODD 0x35EE +#define EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 + + +#define EQ_REG_TD_TPS_LEN__A 0x1C10052 +#define EQ_REG_TD_TPS_LEN__W 6 +#define EQ_REG_TD_TPS_LEN__M 0x3F +#define EQ_REG_TD_TPS_LEN_INIT 0x0 +#define EQ_REG_TD_TPS_LEN_DEF 0x17 +#define EQ_REG_TD_TPS_LEN_ID_SUP 0x1F + + +#define EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 +#define EQ_REG_TD_TPS_FRM_NMB__W 2 +#define EQ_REG_TD_TPS_FRM_NMB__M 0x3 +#define EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 +#define EQ_REG_TD_TPS_FRM_NMB_1 0x0 +#define EQ_REG_TD_TPS_FRM_NMB_2 0x1 +#define EQ_REG_TD_TPS_FRM_NMB_3 0x2 +#define EQ_REG_TD_TPS_FRM_NMB_4 0x3 + + +#define EQ_REG_TD_TPS_CONST__A 0x1C10054 +#define EQ_REG_TD_TPS_CONST__W 2 +#define EQ_REG_TD_TPS_CONST__M 0x3 +#define EQ_REG_TD_TPS_CONST_INIT 0x0 +#define EQ_REG_TD_TPS_CONST_QPSK 0x0 +#define EQ_REG_TD_TPS_CONST_16QAM 0x1 +#define EQ_REG_TD_TPS_CONST_64QAM 0x2 + + +#define EQ_REG_TD_TPS_HINFO__A 0x1C10055 +#define EQ_REG_TD_TPS_HINFO__W 3 +#define EQ_REG_TD_TPS_HINFO__M 0x7 +#define EQ_REG_TD_TPS_HINFO_INIT 0x0 +#define EQ_REG_TD_TPS_HINFO_NH 0x0 +#define EQ_REG_TD_TPS_HINFO_H1 0x1 +#define EQ_REG_TD_TPS_HINFO_H2 0x2 +#define EQ_REG_TD_TPS_HINFO_H4 0x3 + + +#define EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 +#define EQ_REG_TD_TPS_CODE_HP__W 3 +#define EQ_REG_TD_TPS_CODE_HP__M 0x7 +#define EQ_REG_TD_TPS_CODE_HP_INIT 0x0 +#define EQ_REG_TD_TPS_CODE_HP_1_2 0x0 +#define EQ_REG_TD_TPS_CODE_HP_2_3 0x1 +#define EQ_REG_TD_TPS_CODE_HP_3_4 0x2 +#define EQ_REG_TD_TPS_CODE_HP_5_6 0x3 +#define EQ_REG_TD_TPS_CODE_HP_7_8 0x4 + + +#define EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 +#define EQ_REG_TD_TPS_CODE_LP__W 3 +#define EQ_REG_TD_TPS_CODE_LP__M 0x7 +#define EQ_REG_TD_TPS_CODE_LP_INIT 0x0 +#define EQ_REG_TD_TPS_CODE_LP_1_2 0x0 +#define EQ_REG_TD_TPS_CODE_LP_2_3 0x1 +#define EQ_REG_TD_TPS_CODE_LP_3_4 0x2 +#define EQ_REG_TD_TPS_CODE_LP_5_6 0x3 +#define EQ_REG_TD_TPS_CODE_LP_7_8 0x4 + + +#define EQ_REG_TD_TPS_GUARD__A 0x1C10058 +#define EQ_REG_TD_TPS_GUARD__W 2 +#define EQ_REG_TD_TPS_GUARD__M 0x3 +#define EQ_REG_TD_TPS_GUARD_INIT 0x0 +#define EQ_REG_TD_TPS_GUARD_32 0x0 +#define EQ_REG_TD_TPS_GUARD_16 0x1 +#define EQ_REG_TD_TPS_GUARD_08 0x2 +#define EQ_REG_TD_TPS_GUARD_04 0x3 + + +#define EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 +#define EQ_REG_TD_TPS_TR_MODE__W 2 +#define EQ_REG_TD_TPS_TR_MODE__M 0x3 +#define EQ_REG_TD_TPS_TR_MODE_INIT 0x0 +#define EQ_REG_TD_TPS_TR_MODE_2K 0x0 +#define EQ_REG_TD_TPS_TR_MODE_8K 0x1 + + +#define EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A +#define EQ_REG_TD_TPS_CELL_ID_HI__W 8 +#define EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF +#define EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 + + +#define EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B +#define EQ_REG_TD_TPS_CELL_ID_LO__W 8 +#define EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF +#define EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 + + +#define EQ_REG_TD_TPS_RSV__A 0x1C1005C +#define EQ_REG_TD_TPS_RSV__W 6 +#define EQ_REG_TD_TPS_RSV__M 0x3F +#define EQ_REG_TD_TPS_RSV_INIT 0x0 + + +#define EQ_REG_TD_TPS_BCH__A 0x1C1005D +#define EQ_REG_TD_TPS_BCH__W 14 +#define EQ_REG_TD_TPS_BCH__M 0x3FFF +#define EQ_REG_TD_TPS_BCH_INIT 0x0 + + +#define EQ_REG_TD_SQR_ERR_I__A 0x1C1005E +#define EQ_REG_TD_SQR_ERR_I__W 16 +#define EQ_REG_TD_SQR_ERR_I__M 0xFFFF +#define EQ_REG_TD_SQR_ERR_I_INIT 0x0 + + +#define EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F +#define EQ_REG_TD_SQR_ERR_Q__W 16 +#define EQ_REG_TD_SQR_ERR_Q__M 0xFFFF +#define EQ_REG_TD_SQR_ERR_Q_INIT 0x0 + + +#define EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 +#define EQ_REG_TD_SQR_ERR_EXP__W 4 +#define EQ_REG_TD_SQR_ERR_EXP__M 0xF +#define EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 + + +#define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 +#define EQ_REG_TD_REQ_SMB_CNT__W 16 +#define EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF +#define EQ_REG_TD_REQ_SMB_CNT_INIT 0x0 + + +#define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 +#define EQ_REG_TD_TPS_PWR_OFS__W 16 +#define EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF +#define EQ_REG_TD_TPS_PWR_OFS_INIT 0x0 + + + + + + + + + +#define EC_COMM_EXEC__A 0x2000000 +#define EC_COMM_EXEC__W 3 +#define EC_COMM_EXEC__M 0x7 +#define EC_COMM_EXEC_CTL__B 0 +#define EC_COMM_EXEC_CTL__W 3 +#define EC_COMM_EXEC_CTL__M 0x7 +#define EC_COMM_EXEC_CTL_STOP 0x0 +#define EC_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_COMM_EXEC_CTL_HOLD 0x2 +#define EC_COMM_EXEC_CTL_STEP 0x3 +#define EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define EC_COMM_STATE__A 0x2000001 +#define EC_COMM_STATE__W 16 +#define EC_COMM_STATE__M 0xFFFF +#define EC_COMM_MB__A 0x2000002 +#define EC_COMM_MB__W 16 +#define EC_COMM_MB__M 0xFFFF +#define EC_COMM_SERVICE0__A 0x2000003 +#define EC_COMM_SERVICE0__W 16 +#define EC_COMM_SERVICE0__M 0xFFFF +#define EC_COMM_SERVICE1__A 0x2000004 +#define EC_COMM_SERVICE1__W 16 +#define EC_COMM_SERVICE1__M 0xFFFF +#define EC_COMM_INT_STA__A 0x2000007 +#define EC_COMM_INT_STA__W 16 +#define EC_COMM_INT_STA__M 0xFFFF +#define EC_COMM_INT_MSK__A 0x2000008 +#define EC_COMM_INT_MSK__W 16 +#define EC_COMM_INT_MSK__M 0xFFFF + + + + + +#define EC_SB_SID 0x16 + + + + + +#define EC_SB_REG_COMM_EXEC__A 0x2010000 +#define EC_SB_REG_COMM_EXEC__W 3 +#define EC_SB_REG_COMM_EXEC__M 0x7 +#define EC_SB_REG_COMM_EXEC_CTL__B 0 +#define EC_SB_REG_COMM_EXEC_CTL__W 3 +#define EC_SB_REG_COMM_EXEC_CTL__M 0x7 +#define EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 +#define EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define EC_SB_REG_COMM_STATE__A 0x2010001 +#define EC_SB_REG_COMM_STATE__W 4 +#define EC_SB_REG_COMM_STATE__M 0xF +#define EC_SB_REG_COMM_MB__A 0x2010002 +#define EC_SB_REG_COMM_MB__W 2 +#define EC_SB_REG_COMM_MB__M 0x3 +#define EC_SB_REG_COMM_MB_CTR__B 0 +#define EC_SB_REG_COMM_MB_CTR__W 1 +#define EC_SB_REG_COMM_MB_CTR__M 0x1 +#define EC_SB_REG_COMM_MB_CTR_OFF 0x0 +#define EC_SB_REG_COMM_MB_CTR_ON 0x1 +#define EC_SB_REG_COMM_MB_OBS__B 1 +#define EC_SB_REG_COMM_MB_OBS__W 1 +#define EC_SB_REG_COMM_MB_OBS__M 0x2 +#define EC_SB_REG_COMM_MB_OBS_OFF 0x0 +#define EC_SB_REG_COMM_MB_OBS_ON 0x2 + + +#define EC_SB_REG_TR_MODE__A 0x2010010 +#define EC_SB_REG_TR_MODE__W 1 +#define EC_SB_REG_TR_MODE__M 0x1 +#define EC_SB_REG_TR_MODE_INIT 0x0 +#define EC_SB_REG_TR_MODE_8K 0x0 +#define EC_SB_REG_TR_MODE_2K 0x1 + + +#define EC_SB_REG_CONST__A 0x2010011 +#define EC_SB_REG_CONST__W 2 +#define EC_SB_REG_CONST__M 0x3 +#define EC_SB_REG_CONST_INIT 0x2 +#define EC_SB_REG_CONST_QPSK 0x0 +#define EC_SB_REG_CONST_16QAM 0x1 +#define EC_SB_REG_CONST_64QAM 0x2 + + +#define EC_SB_REG_ALPHA__A 0x2010012 +#define EC_SB_REG_ALPHA__W 3 +#define EC_SB_REG_ALPHA__M 0x7 + +#define EC_SB_REG_ALPHA_INIT 0x0 + +#define EC_SB_REG_ALPHA_NH 0x0 + +#define EC_SB_REG_ALPHA_H1 0x1 + +#define EC_SB_REG_ALPHA_H2 0x2 + +#define EC_SB_REG_ALPHA_H4 0x3 + + +#define EC_SB_REG_PRIOR__A 0x2010013 +#define EC_SB_REG_PRIOR__W 1 +#define EC_SB_REG_PRIOR__M 0x1 +#define EC_SB_REG_PRIOR_INIT 0x0 +#define EC_SB_REG_PRIOR_HI 0x0 +#define EC_SB_REG_PRIOR_LO 0x1 + + +#define EC_SB_REG_CSI_HI__A 0x2010014 +#define EC_SB_REG_CSI_HI__W 5 +#define EC_SB_REG_CSI_HI__M 0x1F +#define EC_SB_REG_CSI_HI_INIT 0x1F +#define EC_SB_REG_CSI_HI_MAX 0x1F +#define EC_SB_REG_CSI_HI_MIN 0x0 +#define EC_SB_REG_CSI_HI_TAG 0x0 + + +#define EC_SB_REG_CSI_LO__A 0x2010015 +#define EC_SB_REG_CSI_LO__W 5 +#define EC_SB_REG_CSI_LO__M 0x1F +#define EC_SB_REG_CSI_LO_INIT 0x1F +#define EC_SB_REG_CSI_LO_MAX 0x1F +#define EC_SB_REG_CSI_LO_MIN 0x0 +#define EC_SB_REG_CSI_LO_TAG 0x0 + + +#define EC_SB_REG_SMB_TGL__A 0x2010016 +#define EC_SB_REG_SMB_TGL__W 1 +#define EC_SB_REG_SMB_TGL__M 0x1 +#define EC_SB_REG_SMB_TGL_OFF 0x0 +#define EC_SB_REG_SMB_TGL_ON 0x1 + + +#define EC_SB_REG_SNR_HI__A 0x2010017 +#define EC_SB_REG_SNR_HI__W 8 +#define EC_SB_REG_SNR_HI__M 0xFF +#define EC_SB_REG_SNR_HI_INIT 0xFF +#define EC_SB_REG_SNR_HI_MAX 0xFF +#define EC_SB_REG_SNR_HI_MIN 0x0 +#define EC_SB_REG_SNR_HI_TAG 0x0 + + +#define EC_SB_REG_SNR_MID__A 0x2010018 +#define EC_SB_REG_SNR_MID__W 8 +#define EC_SB_REG_SNR_MID__M 0xFF +#define EC_SB_REG_SNR_MID_INIT 0xFF +#define EC_SB_REG_SNR_MID_MAX 0xFF +#define EC_SB_REG_SNR_MID_MIN 0x0 +#define EC_SB_REG_SNR_MID_TAG 0x0 + + +#define EC_SB_REG_SNR_LO__A 0x2010019 +#define EC_SB_REG_SNR_LO__W 8 +#define EC_SB_REG_SNR_LO__M 0xFF +#define EC_SB_REG_SNR_LO_INIT 0xFF +#define EC_SB_REG_SNR_LO_MAX 0xFF +#define EC_SB_REG_SNR_LO_MIN 0x0 +#define EC_SB_REG_SNR_LO_TAG 0x0 + + +#define EC_SB_REG_SCALE_MSB__A 0x201001A +#define EC_SB_REG_SCALE_MSB__W 6 +#define EC_SB_REG_SCALE_MSB__M 0x3F +#define EC_SB_REG_SCALE_MSB_INIT 0x30 +#define EC_SB_REG_SCALE_MSB_MAX 0x3F + + +#define EC_SB_REG_SCALE_BIT2__A 0x201001B +#define EC_SB_REG_SCALE_BIT2__W 6 +#define EC_SB_REG_SCALE_BIT2__M 0x3F +#define EC_SB_REG_SCALE_BIT2_INIT 0x20 +#define EC_SB_REG_SCALE_BIT2_MAX 0x3F + + +#define EC_SB_REG_SCALE_LSB__A 0x201001C +#define EC_SB_REG_SCALE_LSB__W 6 +#define EC_SB_REG_SCALE_LSB__M 0x3F +#define EC_SB_REG_SCALE_LSB_INIT 0x10 +#define EC_SB_REG_SCALE_LSB_MAX 0x3F + + +#define EC_SB_REG_CSI_OFS__A 0x201001D +#define EC_SB_REG_CSI_OFS__W 4 +#define EC_SB_REG_CSI_OFS__M 0xF +#define EC_SB_REG_CSI_OFS_INIT 0x1 +#define EC_SB_REG_CSI_OFS_ADD__B 0 +#define EC_SB_REG_CSI_OFS_ADD__W 3 +#define EC_SB_REG_CSI_OFS_ADD__M 0x7 +#define EC_SB_REG_CSI_OFS_DIS__B 3 +#define EC_SB_REG_CSI_OFS_DIS__W 1 +#define EC_SB_REG_CSI_OFS_DIS__M 0x8 +#define EC_SB_REG_CSI_OFS_DIS_ENA 0x0 +#define EC_SB_REG_CSI_OFS_DIS_DIS 0x8 + + + +#define EC_SB_SD_RAM__A 0x2020000 + + + +#define EC_SB_BD0_RAM__A 0x2030000 + + + +#define EC_SB_BD1_RAM__A 0x2040000 + + + + + +#define EC_VD_SID 0x17 + + + + + +#define EC_VD_REG_COMM_EXEC__A 0x2090000 +#define EC_VD_REG_COMM_EXEC__W 3 +#define EC_VD_REG_COMM_EXEC__M 0x7 +#define EC_VD_REG_COMM_EXEC_CTL__B 0 +#define EC_VD_REG_COMM_EXEC_CTL__W 3 +#define EC_VD_REG_COMM_EXEC_CTL__M 0x7 +#define EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 +#define EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define EC_VD_REG_COMM_STATE__A 0x2090001 +#define EC_VD_REG_COMM_STATE__W 4 +#define EC_VD_REG_COMM_STATE__M 0xF +#define EC_VD_REG_COMM_MB__A 0x2090002 +#define EC_VD_REG_COMM_MB__W 2 +#define EC_VD_REG_COMM_MB__M 0x3 +#define EC_VD_REG_COMM_MB_CTR__B 0 +#define EC_VD_REG_COMM_MB_CTR__W 1 +#define EC_VD_REG_COMM_MB_CTR__M 0x1 +#define EC_VD_REG_COMM_MB_CTR_OFF 0x0 +#define EC_VD_REG_COMM_MB_CTR_ON 0x1 +#define EC_VD_REG_COMM_MB_OBS__B 1 +#define EC_VD_REG_COMM_MB_OBS__W 1 +#define EC_VD_REG_COMM_MB_OBS__M 0x2 +#define EC_VD_REG_COMM_MB_OBS_OFF 0x0 +#define EC_VD_REG_COMM_MB_OBS_ON 0x2 + +#define EC_VD_REG_COMM_SERVICE0__A 0x2090003 +#define EC_VD_REG_COMM_SERVICE0__W 16 +#define EC_VD_REG_COMM_SERVICE0__M 0xFFFF +#define EC_VD_REG_COMM_SERVICE1__A 0x2090004 +#define EC_VD_REG_COMM_SERVICE1__W 16 +#define EC_VD_REG_COMM_SERVICE1__M 0xFFFF +#define EC_VD_REG_COMM_INT_STA__A 0x2090007 +#define EC_VD_REG_COMM_INT_STA__W 1 +#define EC_VD_REG_COMM_INT_STA__M 0x1 +#define EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 +#define EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 +#define EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 + +#define EC_VD_REG_COMM_INT_MSK__A 0x2090008 +#define EC_VD_REG_COMM_INT_MSK__W 1 +#define EC_VD_REG_COMM_INT_MSK__M 0x1 +#define EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 +#define EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 +#define EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 + + +#define EC_VD_REG_FORCE__A 0x2090010 +#define EC_VD_REG_FORCE__W 2 +#define EC_VD_REG_FORCE__M 0x3 +#define EC_VD_REG_FORCE_INIT 0x0 +#define EC_VD_REG_FORCE_FREE 0x0 +#define EC_VD_REG_FORCE_PROP 0x1 +#define EC_VD_REG_FORCE_FORCED 0x2 +#define EC_VD_REG_FORCE_FIXED 0x3 + + +#define EC_VD_REG_SET_CODERATE__A 0x2090011 +#define EC_VD_REG_SET_CODERATE__W 3 +#define EC_VD_REG_SET_CODERATE__M 0x7 +#define EC_VD_REG_SET_CODERATE_INIT 0x0 +#define EC_VD_REG_SET_CODERATE_C1_2 0x0 +#define EC_VD_REG_SET_CODERATE_C2_3 0x1 +#define EC_VD_REG_SET_CODERATE_C3_4 0x2 +#define EC_VD_REG_SET_CODERATE_C5_6 0x3 +#define EC_VD_REG_SET_CODERATE_C7_8 0x4 + + +#define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 +#define EC_VD_REG_REQ_SMB_CNT__W 16 +#define EC_VD_REG_REQ_SMB_CNT__M 0xFFFF +#define EC_VD_REG_REQ_SMB_CNT_INIT 0x0 + + +#define EC_VD_REG_REQ_BIT_CNT__A 0x2090013 +#define EC_VD_REG_REQ_BIT_CNT__W 16 +#define EC_VD_REG_REQ_BIT_CNT__M 0xFFFF +#define EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF + + +#define EC_VD_REG_RLK_ENA__A 0x2090014 +#define EC_VD_REG_RLK_ENA__W 1 +#define EC_VD_REG_RLK_ENA__M 0x1 +#define EC_VD_REG_RLK_ENA_INIT 0x0 +#define EC_VD_REG_RLK_ENA_OFF 0x0 +#define EC_VD_REG_RLK_ENA_ON 0x1 + + +#define EC_VD_REG_VAL__A 0x2090015 +#define EC_VD_REG_VAL__W 2 +#define EC_VD_REG_VAL__M 0x3 +#define EC_VD_REG_VAL_INIT 0x0 +#define EC_VD_REG_VAL_CODE 0x1 +#define EC_VD_REG_VAL_CNT 0x2 + + +#define EC_VD_REG_GET_CODERATE__A 0x2090016 +#define EC_VD_REG_GET_CODERATE__W 3 +#define EC_VD_REG_GET_CODERATE__M 0x7 +#define EC_VD_REG_GET_CODERATE_INIT 0x0 +#define EC_VD_REG_GET_CODERATE_C1_2 0x0 +#define EC_VD_REG_GET_CODERATE_C2_3 0x1 +#define EC_VD_REG_GET_CODERATE_C3_4 0x2 +#define EC_VD_REG_GET_CODERATE_C5_6 0x3 +#define EC_VD_REG_GET_CODERATE_C7_8 0x4 + + +#define EC_VD_REG_ERR_BIT_CNT__A 0x2090017 +#define EC_VD_REG_ERR_BIT_CNT__W 16 +#define EC_VD_REG_ERR_BIT_CNT__M 0xFFFF +#define EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF + + +#define EC_VD_REG_IN_BIT_CNT__A 0x2090018 +#define EC_VD_REG_IN_BIT_CNT__W 16 +#define EC_VD_REG_IN_BIT_CNT__M 0xFFFF +#define EC_VD_REG_IN_BIT_CNT_INIT 0x0 + + +#define EC_VD_REG_STS__A 0x2090019 +#define EC_VD_REG_STS__W 1 +#define EC_VD_REG_STS__M 0x1 +#define EC_VD_REG_STS_INIT 0x0 +#define EC_VD_REG_STS_NO_LOCK 0x0 +#define EC_VD_REG_STS_IN_LOCK 0x1 + + +#define EC_VD_REG_RLK_CNT__A 0x209001A +#define EC_VD_REG_RLK_CNT__W 16 +#define EC_VD_REG_RLK_CNT__M 0xFFFF +#define EC_VD_REG_RLK_CNT_INIT 0x0 + + + +#define EC_VD_TB0_RAM__A 0x20A0000 + + + +#define EC_VD_TB1_RAM__A 0x20B0000 + + + +#define EC_VD_TB2_RAM__A 0x20C0000 + + + +#define EC_VD_TB3_RAM__A 0x20D0000 + + + +#define EC_VD_RE_RAM__A 0x2100000 + + + + + +#define EC_OD_SID 0x18 + + + + + + +#define EC_OD_REG_COMM_EXEC__A 0x2110000 +#define EC_OD_REG_COMM_EXEC__W 3 +#define EC_OD_REG_COMM_EXEC__M 0x7 +#define EC_OD_REG_COMM_EXEC_CTL__B 0 +#define EC_OD_REG_COMM_EXEC_CTL__W 3 +#define EC_OD_REG_COMM_EXEC_CTL__M 0x7 +#define EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 +#define EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define EC_OD_REG_COMM_MB__A 0x2110002 +#define EC_OD_REG_COMM_MB__W 3 +#define EC_OD_REG_COMM_MB__M 0x7 +#define EC_OD_REG_COMM_MB_CTR__B 0 +#define EC_OD_REG_COMM_MB_CTR__W 1 +#define EC_OD_REG_COMM_MB_CTR__M 0x1 +#define EC_OD_REG_COMM_MB_CTR_OFF 0x0 +#define EC_OD_REG_COMM_MB_CTR_ON 0x1 +#define EC_OD_REG_COMM_MB_OBS__B 1 +#define EC_OD_REG_COMM_MB_OBS__W 1 +#define EC_OD_REG_COMM_MB_OBS__M 0x2 +#define EC_OD_REG_COMM_MB_OBS_OFF 0x0 +#define EC_OD_REG_COMM_MB_OBS_ON 0x2 + +#define EC_OD_REG_COMM_SERVICE0__A 0x2110003 +#define EC_OD_REG_COMM_SERVICE0__W 10 +#define EC_OD_REG_COMM_SERVICE0__M 0x3FF +#define EC_OD_REG_COMM_SERVICE1__A 0x2110004 +#define EC_OD_REG_COMM_SERVICE1__W 11 +#define EC_OD_REG_COMM_SERVICE1__M 0x7FF + +#define EC_OD_REG_COMM_ACTIVATE__A 0x2110005 +#define EC_OD_REG_COMM_ACTIVATE__W 2 +#define EC_OD_REG_COMM_ACTIVATE__M 0x3 + +#define EC_OD_REG_COMM_COUNT__A 0x2110006 +#define EC_OD_REG_COMM_COUNT__W 16 +#define EC_OD_REG_COMM_COUNT__M 0xFFFF + +#define EC_OD_REG_COMM_INT_STA__A 0x2110007 +#define EC_OD_REG_COMM_INT_STA__W 2 +#define EC_OD_REG_COMM_INT_STA__M 0x3 +#define EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 +#define EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 +#define EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 +#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 +#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 +#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 + + +#define EC_OD_REG_COMM_INT_MSK__A 0x2110008 +#define EC_OD_REG_COMM_INT_MSK__W 2 +#define EC_OD_REG_COMM_INT_MSK__M 0x3 +#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 +#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 +#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 +#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 +#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 +#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 + + +#define EC_OD_REG_SYNC__A 0x2110010 +#define EC_OD_REG_SYNC__W 12 +#define EC_OD_REG_SYNC__M 0xFFF +#define EC_OD_REG_SYNC_NR_SYNC__B 0 +#define EC_OD_REG_SYNC_NR_SYNC__W 5 +#define EC_OD_REG_SYNC_NR_SYNC__M 0x1F +#define EC_OD_REG_SYNC_IN_SYNC__B 5 +#define EC_OD_REG_SYNC_IN_SYNC__W 4 +#define EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 +#define EC_OD_REG_SYNC_OUT_SYNC__B 9 +#define EC_OD_REG_SYNC_OUT_SYNC__W 3 +#define EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 + + +#define EC_OD_REG_NOSYNC__A 0x2110011 +#define EC_OD_REG_NOSYNC__W 8 +#define EC_OD_REG_NOSYNC__M 0xFF + + + +#define EC_OD_DEINT_RAM__A 0x2120000 + + + + + +#define EC_RS_SID 0x19 + + + + + +#define EC_RS_REG_COMM_EXEC__A 0x2130000 +#define EC_RS_REG_COMM_EXEC__W 3 +#define EC_RS_REG_COMM_EXEC__M 0x7 +#define EC_RS_REG_COMM_EXEC_CTL__B 0 +#define EC_RS_REG_COMM_EXEC_CTL__W 3 +#define EC_RS_REG_COMM_EXEC_CTL__M 0x7 +#define EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 +#define EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define EC_RS_REG_COMM_STATE__A 0x2130001 +#define EC_RS_REG_COMM_STATE__W 4 +#define EC_RS_REG_COMM_STATE__M 0xF +#define EC_RS_REG_COMM_MB__A 0x2130002 +#define EC_RS_REG_COMM_MB__W 2 +#define EC_RS_REG_COMM_MB__M 0x3 +#define EC_RS_REG_COMM_MB_CTR__B 0 +#define EC_RS_REG_COMM_MB_CTR__W 1 +#define EC_RS_REG_COMM_MB_CTR__M 0x1 +#define EC_RS_REG_COMM_MB_CTR_OFF 0x0 +#define EC_RS_REG_COMM_MB_CTR_ON 0x1 +#define EC_RS_REG_COMM_MB_OBS__B 1 +#define EC_RS_REG_COMM_MB_OBS__W 1 +#define EC_RS_REG_COMM_MB_OBS__M 0x2 +#define EC_RS_REG_COMM_MB_OBS_OFF 0x0 +#define EC_RS_REG_COMM_MB_OBS_ON 0x2 + +#define EC_RS_REG_COMM_SERVICE0__A 0x2130003 +#define EC_RS_REG_COMM_SERVICE0__W 16 +#define EC_RS_REG_COMM_SERVICE0__M 0xFFFF +#define EC_RS_REG_COMM_SERVICE1__A 0x2130004 +#define EC_RS_REG_COMM_SERVICE1__W 16 +#define EC_RS_REG_COMM_SERVICE1__M 0xFFFF +#define EC_RS_REG_COMM_INT_STA__A 0x2130007 +#define EC_RS_REG_COMM_INT_STA__W 1 +#define EC_RS_REG_COMM_INT_STA__M 0x1 +#define EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 +#define EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 +#define EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 + +#define EC_RS_REG_COMM_INT_MSK__A 0x2130008 +#define EC_RS_REG_COMM_INT_MSK__W 1 +#define EC_RS_REG_COMM_INT_MSK__M 0x1 +#define EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 +#define EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 +#define EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 + + +#define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 +#define EC_RS_REG_REQ_PCK_CNT__W 16 +#define EC_RS_REG_REQ_PCK_CNT__M 0xFFFF +#define EC_RS_REG_REQ_PCK_CNT_INIT 0xFF + + +#define EC_RS_REG_VAL__A 0x2130011 +#define EC_RS_REG_VAL__W 1 +#define EC_RS_REG_VAL__M 0x1 +#define EC_RS_REG_VAL_INIT 0x0 +#define EC_RS_REG_VAL_PCK 0x1 + + +#define EC_RS_REG_ERR_PCK_CNT__A 0x2130012 +#define EC_RS_REG_ERR_PCK_CNT__W 16 +#define EC_RS_REG_ERR_PCK_CNT__M 0xFFFF +#define EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF + + +#define EC_RS_REG_ERR_SMB_CNT__A 0x2130013 +#define EC_RS_REG_ERR_SMB_CNT__W 16 +#define EC_RS_REG_ERR_SMB_CNT__M 0xFFFF +#define EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF + + +#define EC_RS_REG_ERR_BIT_CNT__A 0x2130014 +#define EC_RS_REG_ERR_BIT_CNT__W 16 +#define EC_RS_REG_ERR_BIT_CNT__M 0xFFFF +#define EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF + + +#define EC_RS_REG_IN_PCK_CNT__A 0x2130015 +#define EC_RS_REG_IN_PCK_CNT__W 16 +#define EC_RS_REG_IN_PCK_CNT__M 0xFFFF +#define EC_RS_REG_IN_PCK_CNT_INIT 0x0 + + + +#define EC_RS_EC_RAM__A 0x2140000 + + + + + +#define EC_OC_SID 0x1A + + + + + + +#define EC_OC_REG_COMM_EXEC__A 0x2150000 +#define EC_OC_REG_COMM_EXEC__W 3 +#define EC_OC_REG_COMM_EXEC__M 0x7 +#define EC_OC_REG_COMM_EXEC_CTL__B 0 +#define EC_OC_REG_COMM_EXEC_CTL__W 3 +#define EC_OC_REG_COMM_EXEC_CTL__M 0x7 +#define EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 +#define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 +#define EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 + +#define EC_OC_REG_COMM_STATE__A 0x2150001 +#define EC_OC_REG_COMM_STATE__W 4 +#define EC_OC_REG_COMM_STATE__M 0xF + +#define EC_OC_REG_COMM_MB__A 0x2150002 +#define EC_OC_REG_COMM_MB__W 2 +#define EC_OC_REG_COMM_MB__M 0x3 +#define EC_OC_REG_COMM_MB_CTR__B 0 +#define EC_OC_REG_COMM_MB_CTR__W 1 +#define EC_OC_REG_COMM_MB_CTR__M 0x1 +#define EC_OC_REG_COMM_MB_CTR_OFF 0x0 +#define EC_OC_REG_COMM_MB_CTR_ON 0x1 +#define EC_OC_REG_COMM_MB_OBS__B 1 +#define EC_OC_REG_COMM_MB_OBS__W 1 +#define EC_OC_REG_COMM_MB_OBS__M 0x2 +#define EC_OC_REG_COMM_MB_OBS_OFF 0x0 +#define EC_OC_REG_COMM_MB_OBS_ON 0x2 + + +#define EC_OC_REG_COMM_SERVICE0__A 0x2150003 +#define EC_OC_REG_COMM_SERVICE0__W 10 +#define EC_OC_REG_COMM_SERVICE0__M 0x3FF + +#define EC_OC_REG_COMM_SERVICE1__A 0x2150004 +#define EC_OC_REG_COMM_SERVICE1__W 11 +#define EC_OC_REG_COMM_SERVICE1__M 0x7FF + +#define EC_OC_REG_COMM_INT_STA__A 0x2150007 +#define EC_OC_REG_COMM_INT_STA__W 6 +#define EC_OC_REG_COMM_INT_STA__M 0x3F +#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 +#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 +#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 +#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 +#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 +#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 +#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 +#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 +#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 +#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 +#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 +#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 +#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 +#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 +#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 +#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 +#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 +#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 + + +#define EC_OC_REG_COMM_INT_MSK__A 0x2150008 +#define EC_OC_REG_COMM_INT_MSK__W 6 +#define EC_OC_REG_COMM_INT_MSK__M 0x3F +#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 +#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 +#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 +#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 +#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 +#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 +#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 +#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 +#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 +#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 +#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 +#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 +#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 +#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 +#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 +#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 +#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 +#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 + + +#define EC_OC_REG_OC_MODE_LOP__A 0x2150010 +#define EC_OC_REG_OC_MODE_LOP__W 16 +#define EC_OC_REG_OC_MODE_LOP__M 0xFFFF +#define EC_OC_REG_OC_MODE_LOP_INIT 0x0 + +#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 +#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 +#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 +#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 + +#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 +#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 +#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 +#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 +#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 + +#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 +#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 +#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 +#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 + +#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 +#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 +#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 +#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 + +#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 +#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 +#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 + +#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 +#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 +#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 + +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 + +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 + +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 + +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 + +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 + +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 + +#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 +#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 +#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 + +#define EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 +#define EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 +#define EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 +#define EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 + + +#define EC_OC_REG_OC_MODE_HIP__A 0x2150011 +#define EC_OC_REG_OC_MODE_HIP__W 14 +#define EC_OC_REG_OC_MODE_HIP__M 0x3FFF +#define EC_OC_REG_OC_MODE_HIP_INIT 0x0 + +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 + +#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 +#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 + +#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 +#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 +#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 +#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 + +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 + +#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 +#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 +#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 + +#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 +#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 +#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 +#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 + +#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 +#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 +#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 +#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 + +#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 +#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 +#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 + +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 + +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 + +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 + +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 + +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 + +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 + + +#define EC_OC_REG_OC_MPG_SIO__A 0x2150012 +#define EC_OC_REG_OC_MPG_SIO__W 12 +#define EC_OC_REG_OC_MPG_SIO__M 0xFFF +#define EC_OC_REG_OC_MPG_SIO_INIT 0xFFF + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 + + +#define EC_OC_REG_OC_MON_SIO__A 0x2150013 +#define EC_OC_REG_OC_MON_SIO__W 12 +#define EC_OC_REG_OC_MON_SIO__M 0xFFF +#define EC_OC_REG_OC_MON_SIO_INIT 0xFFF + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__B 0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__M 0x1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_0_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_0_INPUT 0x1 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__B 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__M 0x2 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_1_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_1_INPUT 0x2 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__B 2 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__M 0x4 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_2_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_2_INPUT 0x4 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__B 3 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__M 0x8 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_3_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_3_INPUT 0x8 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__B 4 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__M 0x10 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_4_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_4_INPUT 0x10 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__B 5 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__M 0x20 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_5_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_5_INPUT 0x20 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__B 6 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__M 0x40 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_6_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_6_INPUT 0x40 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__B 7 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__M 0x80 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_7_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_7_INPUT 0x80 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__B 8 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__M 0x100 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_8_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_8_INPUT 0x100 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__B 9 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__M 0x200 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_9_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_9_INPUT 0x200 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__B 10 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__M 0x400 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_10_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_10_INPUT 0x400 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__B 11 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__M 0x800 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_INPUT 0x800 + + +#define EC_OC_REG_DTO_INC_LOP__A 0x2150014 +#define EC_OC_REG_DTO_INC_LOP__W 16 +#define EC_OC_REG_DTO_INC_LOP__M 0xFFFF +#define EC_OC_REG_DTO_INC_LOP_INIT 0x0 + + +#define EC_OC_REG_DTO_INC_HIP__A 0x2150015 +#define EC_OC_REG_DTO_INC_HIP__W 8 +#define EC_OC_REG_DTO_INC_HIP__M 0xFF +#define EC_OC_REG_DTO_INC_HIP_INIT 0x0 + + +#define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 +#define EC_OC_REG_SNC_ISC_LVL__W 12 +#define EC_OC_REG_SNC_ISC_LVL__M 0xFFF +#define EC_OC_REG_SNC_ISC_LVL_INIT 0x0 + +#define EC_OC_REG_SNC_ISC_LVL_ISC__B 0 +#define EC_OC_REG_SNC_ISC_LVL_ISC__W 4 +#define EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF + +#define EC_OC_REG_SNC_ISC_LVL_OSC__B 4 +#define EC_OC_REG_SNC_ISC_LVL_OSC__W 4 +#define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 + +#define EC_OC_REG_SNC_ISC_LVL_NSC__B 8 +#define EC_OC_REG_SNC_ISC_LVL_NSC__W 4 +#define EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 + + +#define EC_OC_REG_SNC_NSC_LVL__A 0x2150017 +#define EC_OC_REG_SNC_NSC_LVL__W 8 +#define EC_OC_REG_SNC_NSC_LVL__M 0xFF +#define EC_OC_REG_SNC_NSC_LVL_INIT 0x0 + + +#define EC_OC_REG_SNC_SNC_MODE__A 0x2150019 +#define EC_OC_REG_SNC_SNC_MODE__W 2 +#define EC_OC_REG_SNC_SNC_MODE__M 0x3 +#define EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 +#define EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 +#define EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 + + +#define EC_OC_REG_SNC_PCK_NMB__A 0x215001A +#define EC_OC_REG_SNC_PCK_NMB__W 16 +#define EC_OC_REG_SNC_PCK_NMB__M 0xFFFF + +#define EC_OC_REG_SNC_PCK_CNT__A 0x215001B +#define EC_OC_REG_SNC_PCK_CNT__W 16 +#define EC_OC_REG_SNC_PCK_CNT__M 0xFFFF + +#define EC_OC_REG_SNC_PCK_ERR__A 0x215001C +#define EC_OC_REG_SNC_PCK_ERR__W 16 +#define EC_OC_REG_SNC_PCK_ERR__M 0xFFFF + +#define EC_OC_REG_TMD_TOP_MODE__A 0x215001D +#define EC_OC_REG_TMD_TOP_MODE__W 2 +#define EC_OC_REG_TMD_TOP_MODE__M 0x3 +#define EC_OC_REG_TMD_TOP_MODE_INIT 0x0 +#define EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 +#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 +#define EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 +#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 + + +#define EC_OC_REG_TMD_TOP_CNT__A 0x215001E +#define EC_OC_REG_TMD_TOP_CNT__W 10 +#define EC_OC_REG_TMD_TOP_CNT__M 0x3FF +#define EC_OC_REG_TMD_TOP_CNT_INIT 0x0 + + +#define EC_OC_REG_TMD_HIL_MAR__A 0x215001F +#define EC_OC_REG_TMD_HIL_MAR__W 10 +#define EC_OC_REG_TMD_HIL_MAR__M 0x3FF +#define EC_OC_REG_TMD_HIL_MAR_INIT 0x0 + + +#define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 +#define EC_OC_REG_TMD_LOL_MAR__W 10 +#define EC_OC_REG_TMD_LOL_MAR__M 0x3FF +#define EC_OC_REG_TMD_LOL_MAR_INIT 0x0 + + +#define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 +#define EC_OC_REG_TMD_CUR_CNT__W 4 +#define EC_OC_REG_TMD_CUR_CNT__M 0xF +#define EC_OC_REG_TMD_CUR_CNT_INIT 0x0 + + +#define EC_OC_REG_TMD_IUR_CNT__A 0x2150022 +#define EC_OC_REG_TMD_IUR_CNT__W 4 +#define EC_OC_REG_TMD_IUR_CNT__M 0xF +#define EC_OC_REG_TMD_IUR_CNT_INIT 0x0 + + +#define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 +#define EC_OC_REG_AVR_ASH_CNT__W 4 +#define EC_OC_REG_AVR_ASH_CNT__M 0xF +#define EC_OC_REG_AVR_ASH_CNT_INIT 0x0 + + +#define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 +#define EC_OC_REG_AVR_BSH_CNT__W 4 +#define EC_OC_REG_AVR_BSH_CNT__M 0xF +#define EC_OC_REG_AVR_BSH_CNT_INIT 0x0 + + +#define EC_OC_REG_AVR_AVE_LOP__A 0x2150025 +#define EC_OC_REG_AVR_AVE_LOP__W 16 +#define EC_OC_REG_AVR_AVE_LOP__M 0xFFFF + +#define EC_OC_REG_AVR_AVE_HIP__A 0x2150026 +#define EC_OC_REG_AVR_AVE_HIP__W 5 +#define EC_OC_REG_AVR_AVE_HIP__M 0x1F + +#define EC_OC_REG_RCN_MODE__A 0x2150027 +#define EC_OC_REG_RCN_MODE__W 3 +#define EC_OC_REG_RCN_MODE__M 0x7 +#define EC_OC_REG_RCN_MODE_INIT 0x0 + +#define EC_OC_REG_RCN_MODE_MODE_0__B 0 +#define EC_OC_REG_RCN_MODE_MODE_0__W 1 +#define EC_OC_REG_RCN_MODE_MODE_0__M 0x1 +#define EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 +#define EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 + +#define EC_OC_REG_RCN_MODE_MODE_1__B 1 +#define EC_OC_REG_RCN_MODE_MODE_1__W 1 +#define EC_OC_REG_RCN_MODE_MODE_1__M 0x2 +#define EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 +#define EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 + +#define EC_OC_REG_RCN_MODE_MODE_2__B 2 +#define EC_OC_REG_RCN_MODE_MODE_2__W 1 +#define EC_OC_REG_RCN_MODE_MODE_2__M 0x4 +#define EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 +#define EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 + + +#define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 +#define EC_OC_REG_RCN_CRA_LOP__W 16 +#define EC_OC_REG_RCN_CRA_LOP__M 0xFFFF +#define EC_OC_REG_RCN_CRA_LOP_INIT 0x0 + + +#define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 +#define EC_OC_REG_RCN_CRA_HIP__W 8 +#define EC_OC_REG_RCN_CRA_HIP__M 0xFF +#define EC_OC_REG_RCN_CRA_HIP_INIT 0x0 + + +#define EC_OC_REG_RCN_CST_LOP__A 0x215002A +#define EC_OC_REG_RCN_CST_LOP__W 16 +#define EC_OC_REG_RCN_CST_LOP__M 0xFFFF +#define EC_OC_REG_RCN_CST_LOP_INIT 0x0 + + +#define EC_OC_REG_RCN_CST_HIP__A 0x215002B +#define EC_OC_REG_RCN_CST_HIP__W 8 +#define EC_OC_REG_RCN_CST_HIP__M 0xFF +#define EC_OC_REG_RCN_CST_HIP_INIT 0x0 + + +#define EC_OC_REG_RCN_SET_LVL__A 0x215002C +#define EC_OC_REG_RCN_SET_LVL__W 9 +#define EC_OC_REG_RCN_SET_LVL__M 0x1FF +#define EC_OC_REG_RCN_SET_LVL_INIT 0x0 + + +#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D +#define EC_OC_REG_RCN_GAI_LVL__W 4 +#define EC_OC_REG_RCN_GAI_LVL__M 0xF +#define EC_OC_REG_RCN_GAI_LVL_INIT 0x0 + + +#define EC_OC_REG_RCN_DRA_LOP__A 0x215002E +#define EC_OC_REG_RCN_DRA_LOP__W 16 +#define EC_OC_REG_RCN_DRA_LOP__M 0xFFFF + +#define EC_OC_REG_RCN_DRA_HIP__A 0x215002F +#define EC_OC_REG_RCN_DRA_HIP__W 8 +#define EC_OC_REG_RCN_DRA_HIP__M 0xFF + +#define EC_OC_REG_RCN_DOF_LOP__A 0x2150030 +#define EC_OC_REG_RCN_DOF_LOP__W 16 +#define EC_OC_REG_RCN_DOF_LOP__M 0xFFFF + +#define EC_OC_REG_RCN_DOF_HIP__A 0x2150031 +#define EC_OC_REG_RCN_DOF_HIP__W 8 +#define EC_OC_REG_RCN_DOF_HIP__M 0xFF + +#define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 +#define EC_OC_REG_RCN_CLP_LOP__W 16 +#define EC_OC_REG_RCN_CLP_LOP__M 0xFFFF +#define EC_OC_REG_RCN_CLP_LOP_INIT 0xFFFF + + +#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 +#define EC_OC_REG_RCN_CLP_HIP__W 8 +#define EC_OC_REG_RCN_CLP_HIP__M 0xFF +#define EC_OC_REG_RCN_CLP_HIP_INIT 0xFF + + +#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 +#define EC_OC_REG_RCN_MAP_LOP__W 16 +#define EC_OC_REG_RCN_MAP_LOP__M 0xFFFF + +#define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 +#define EC_OC_REG_RCN_MAP_HIP__W 8 +#define EC_OC_REG_RCN_MAP_HIP__M 0xFF + +#define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 +#define EC_OC_REG_OCR_MPG_UOS__W 12 +#define EC_OC_REG_OCR_MPG_UOS__M 0xFFF +#define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 +#define EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 +#define EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 +#define EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 +#define EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 +#define EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 +#define EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 +#define EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 +#define EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 +#define EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 +#define EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 +#define EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 +#define EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 +#define EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 + +#define EC_OC_REG_OCR_MPG_UOS_ERR__B 8 +#define EC_OC_REG_OCR_MPG_UOS_ERR__W 1 +#define EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 +#define EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 + +#define EC_OC_REG_OCR_MPG_UOS_STR__B 9 +#define EC_OC_REG_OCR_MPG_UOS_STR__W 1 +#define EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 +#define EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 + +#define EC_OC_REG_OCR_MPG_UOS_VAL__B 10 +#define EC_OC_REG_OCR_MPG_UOS_VAL__W 1 +#define EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 +#define EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 + +#define EC_OC_REG_OCR_MPG_UOS_CLK__B 11 +#define EC_OC_REG_OCR_MPG_UOS_CLK__W 1 +#define EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 +#define EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 + + +#define EC_OC_REG_OCR_MPG_WRI__A 0x2150037 +#define EC_OC_REG_OCR_MPG_WRI__W 12 +#define EC_OC_REG_OCR_MPG_WRI__M 0xFFF +#define EC_OC_REG_OCR_MPG_WRI_INIT 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 +#define EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 +#define EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 +#define EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 +#define EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 +#define EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 +#define EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 +#define EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 +#define EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 +#define EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 +#define EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 +#define EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 +#define EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 +#define EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 +#define EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 +#define EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 +#define EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 +#define EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 +#define EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 +#define EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 +#define EC_OC_REG_OCR_MPG_WRI_ERR__B 8 +#define EC_OC_REG_OCR_MPG_WRI_ERR__W 1 +#define EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 +#define EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 +#define EC_OC_REG_OCR_MPG_WRI_STR__B 9 +#define EC_OC_REG_OCR_MPG_WRI_STR__W 1 +#define EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 +#define EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 +#define EC_OC_REG_OCR_MPG_WRI_VAL__B 10 +#define EC_OC_REG_OCR_MPG_WRI_VAL__W 1 +#define EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 +#define EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 +#define EC_OC_REG_OCR_MPG_WRI_CLK__B 11 +#define EC_OC_REG_OCR_MPG_WRI_CLK__W 1 +#define EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 +#define EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 + + +#define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 +#define EC_OC_REG_OCR_MPG_USR_DAT__W 12 +#define EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF + +#define EC_OC_REG_OCR_MON_UOS__A 0x2150039 +#define EC_OC_REG_OCR_MON_UOS__W 12 +#define EC_OC_REG_OCR_MON_UOS__M 0xFFF +#define EC_OC_REG_OCR_MON_UOS_INIT 0x0 + +#define EC_OC_REG_OCR_MON_UOS_DAT_0__B 0 +#define EC_OC_REG_OCR_MON_UOS_DAT_0__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_0__M 0x1 +#define EC_OC_REG_OCR_MON_UOS_DAT_0_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1 + +#define EC_OC_REG_OCR_MON_UOS_DAT_1__B 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_1__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_1__M 0x2 +#define EC_OC_REG_OCR_MON_UOS_DAT_1_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2 + +#define EC_OC_REG_OCR_MON_UOS_DAT_2__B 2 +#define EC_OC_REG_OCR_MON_UOS_DAT_2__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_2__M 0x4 +#define EC_OC_REG_OCR_MON_UOS_DAT_2_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4 + +#define EC_OC_REG_OCR_MON_UOS_DAT_3__B 3 +#define EC_OC_REG_OCR_MON_UOS_DAT_3__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_3__M 0x8 +#define EC_OC_REG_OCR_MON_UOS_DAT_3_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8 + +#define EC_OC_REG_OCR_MON_UOS_DAT_4__B 4 +#define EC_OC_REG_OCR_MON_UOS_DAT_4__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_4__M 0x10 +#define EC_OC_REG_OCR_MON_UOS_DAT_4_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10 + +#define EC_OC_REG_OCR_MON_UOS_DAT_5__B 5 +#define EC_OC_REG_OCR_MON_UOS_DAT_5__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_5__M 0x20 +#define EC_OC_REG_OCR_MON_UOS_DAT_5_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20 + +#define EC_OC_REG_OCR_MON_UOS_DAT_6__B 6 +#define EC_OC_REG_OCR_MON_UOS_DAT_6__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_6__M 0x40 +#define EC_OC_REG_OCR_MON_UOS_DAT_6_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40 + +#define EC_OC_REG_OCR_MON_UOS_DAT_7__B 7 +#define EC_OC_REG_OCR_MON_UOS_DAT_7__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_7__M 0x80 +#define EC_OC_REG_OCR_MON_UOS_DAT_7_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80 + +#define EC_OC_REG_OCR_MON_UOS_DAT_8__B 8 +#define EC_OC_REG_OCR_MON_UOS_DAT_8__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_8__M 0x100 +#define EC_OC_REG_OCR_MON_UOS_DAT_8_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100 + +#define EC_OC_REG_OCR_MON_UOS_DAT_9__B 9 +#define EC_OC_REG_OCR_MON_UOS_DAT_9__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_9__M 0x200 +#define EC_OC_REG_OCR_MON_UOS_DAT_9_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200 + +#define EC_OC_REG_OCR_MON_UOS_VAL__B 10 +#define EC_OC_REG_OCR_MON_UOS_VAL__W 1 +#define EC_OC_REG_OCR_MON_UOS_VAL__M 0x400 +#define EC_OC_REG_OCR_MON_UOS_VAL_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400 + +#define EC_OC_REG_OCR_MON_UOS_CLK__B 11 +#define EC_OC_REG_OCR_MON_UOS_CLK__W 1 +#define EC_OC_REG_OCR_MON_UOS_CLK__M 0x800 +#define EC_OC_REG_OCR_MON_UOS_CLK_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 + + +#define EC_OC_REG_OCR_MON_WRI__A 0x215003A +#define EC_OC_REG_OCR_MON_WRI__W 12 +#define EC_OC_REG_OCR_MON_WRI__M 0xFFF +#define EC_OC_REG_OCR_MON_WRI_INIT 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_0__B 0 +#define EC_OC_REG_OCR_MON_WRI_DAT_0__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_0__M 0x1 +#define EC_OC_REG_OCR_MON_WRI_DAT_0_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_0_ENABLE 0x1 +#define EC_OC_REG_OCR_MON_WRI_DAT_1__B 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_1__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_1__M 0x2 +#define EC_OC_REG_OCR_MON_WRI_DAT_1_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_1_ENABLE 0x2 +#define EC_OC_REG_OCR_MON_WRI_DAT_2__B 2 +#define EC_OC_REG_OCR_MON_WRI_DAT_2__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_2__M 0x4 +#define EC_OC_REG_OCR_MON_WRI_DAT_2_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_2_ENABLE 0x4 +#define EC_OC_REG_OCR_MON_WRI_DAT_3__B 3 +#define EC_OC_REG_OCR_MON_WRI_DAT_3__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_3__M 0x8 +#define EC_OC_REG_OCR_MON_WRI_DAT_3_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_3_ENABLE 0x8 +#define EC_OC_REG_OCR_MON_WRI_DAT_4__B 4 +#define EC_OC_REG_OCR_MON_WRI_DAT_4__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_4__M 0x10 +#define EC_OC_REG_OCR_MON_WRI_DAT_4_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_4_ENABLE 0x10 +#define EC_OC_REG_OCR_MON_WRI_DAT_5__B 5 +#define EC_OC_REG_OCR_MON_WRI_DAT_5__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_5__M 0x20 +#define EC_OC_REG_OCR_MON_WRI_DAT_5_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_5_ENABLE 0x20 +#define EC_OC_REG_OCR_MON_WRI_DAT_6__B 6 +#define EC_OC_REG_OCR_MON_WRI_DAT_6__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_6__M 0x40 +#define EC_OC_REG_OCR_MON_WRI_DAT_6_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_6_ENABLE 0x40 +#define EC_OC_REG_OCR_MON_WRI_DAT_7__B 7 +#define EC_OC_REG_OCR_MON_WRI_DAT_7__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_7__M 0x80 +#define EC_OC_REG_OCR_MON_WRI_DAT_7_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_7_ENABLE 0x80 +#define EC_OC_REG_OCR_MON_WRI_DAT_8__B 8 +#define EC_OC_REG_OCR_MON_WRI_DAT_8__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_8__M 0x100 +#define EC_OC_REG_OCR_MON_WRI_DAT_8_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_8_ENABLE 0x100 +#define EC_OC_REG_OCR_MON_WRI_DAT_9__B 9 +#define EC_OC_REG_OCR_MON_WRI_DAT_9__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_9__M 0x200 +#define EC_OC_REG_OCR_MON_WRI_DAT_9_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_9_ENABLE 0x200 +#define EC_OC_REG_OCR_MON_WRI_VAL__B 10 +#define EC_OC_REG_OCR_MON_WRI_VAL__W 1 +#define EC_OC_REG_OCR_MON_WRI_VAL__M 0x400 +#define EC_OC_REG_OCR_MON_WRI_VAL_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_VAL_ENABLE 0x400 +#define EC_OC_REG_OCR_MON_WRI_CLK__B 11 +#define EC_OC_REG_OCR_MON_WRI_CLK__W 1 +#define EC_OC_REG_OCR_MON_WRI_CLK__M 0x800 +#define EC_OC_REG_OCR_MON_WRI_CLK_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_CLK_ENABLE 0x800 + + +#define EC_OC_REG_OCR_MON_USR_DAT__A 0x215003B +#define EC_OC_REG_OCR_MON_USR_DAT__W 12 +#define EC_OC_REG_OCR_MON_USR_DAT__M 0xFFF + +#define EC_OC_REG_OCR_MON_CNT__A 0x215003C +#define EC_OC_REG_OCR_MON_CNT__W 14 +#define EC_OC_REG_OCR_MON_CNT__M 0x3FFF +#define EC_OC_REG_OCR_MON_CNT_INIT 0x0 + + +#define EC_OC_REG_OCR_MON_RDX__A 0x215003D +#define EC_OC_REG_OCR_MON_RDX__W 1 +#define EC_OC_REG_OCR_MON_RDX__M 0x1 +#define EC_OC_REG_OCR_MON_RDX_INIT 0x0 + + +#define EC_OC_REG_OCR_MON_RD0__A 0x215003E +#define EC_OC_REG_OCR_MON_RD0__W 10 +#define EC_OC_REG_OCR_MON_RD0__M 0x3FF + +#define EC_OC_REG_OCR_MON_RD1__A 0x215003F +#define EC_OC_REG_OCR_MON_RD1__W 10 +#define EC_OC_REG_OCR_MON_RD1__M 0x3FF + +#define EC_OC_REG_OCR_MON_RD2__A 0x2150040 +#define EC_OC_REG_OCR_MON_RD2__W 10 +#define EC_OC_REG_OCR_MON_RD2__M 0x3FF + +#define EC_OC_REG_OCR_MON_RD3__A 0x2150041 +#define EC_OC_REG_OCR_MON_RD3__W 10 +#define EC_OC_REG_OCR_MON_RD3__M 0x3FF + +#define EC_OC_REG_OCR_MON_RD4__A 0x2150042 +#define EC_OC_REG_OCR_MON_RD4__W 10 +#define EC_OC_REG_OCR_MON_RD4__M 0x3FF + +#define EC_OC_REG_OCR_MON_RD5__A 0x2150043 +#define EC_OC_REG_OCR_MON_RD5__W 10 +#define EC_OC_REG_OCR_MON_RD5__M 0x3FF + +#define EC_OC_REG_OCR_INV_MON__A 0x2150044 +#define EC_OC_REG_OCR_INV_MON__W 12 +#define EC_OC_REG_OCR_INV_MON__M 0xFFF +#define EC_OC_REG_OCR_INV_MON_INIT 0x0 + + +#define EC_OC_REG_IPR_INV_MPG__A 0x2150045 +#define EC_OC_REG_IPR_INV_MPG__W 12 +#define EC_OC_REG_IPR_INV_MPG__M 0xFFF +#define EC_OC_REG_IPR_INV_MPG_INIT 0x0 + + +#define EC_OC_REG_IPR_MSR_SNC__A 0x2150046 +#define EC_OC_REG_IPR_MSR_SNC__W 6 +#define EC_OC_REG_IPR_MSR_SNC__M 0x3F +#define EC_OC_REG_IPR_MSR_SNC_INIT 0x0 + + + +#define EC_OC_RAM__A 0x2160000 + + + + + +#define CC_SID 0x1B + + + + + +#define CC_COMM_EXEC__A 0x2400000 +#define CC_COMM_EXEC__W 3 +#define CC_COMM_EXEC__M 0x7 +#define CC_COMM_EXEC_CTL__B 0 +#define CC_COMM_EXEC_CTL__W 3 +#define CC_COMM_EXEC_CTL__M 0x7 +#define CC_COMM_EXEC_CTL_STOP 0x0 +#define CC_COMM_EXEC_CTL_ACTIVE 0x1 +#define CC_COMM_EXEC_CTL_HOLD 0x2 +#define CC_COMM_EXEC_CTL_STEP 0x3 +#define CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define CC_COMM_STATE__A 0x2400001 +#define CC_COMM_STATE__W 16 +#define CC_COMM_STATE__M 0xFFFF +#define CC_COMM_MB__A 0x2400002 +#define CC_COMM_MB__W 16 +#define CC_COMM_MB__M 0xFFFF +#define CC_COMM_SERVICE0__A 0x2400003 +#define CC_COMM_SERVICE0__W 16 +#define CC_COMM_SERVICE0__M 0xFFFF +#define CC_COMM_SERVICE1__A 0x2400004 +#define CC_COMM_SERVICE1__W 16 +#define CC_COMM_SERVICE1__M 0xFFFF +#define CC_COMM_INT_STA__A 0x2400007 +#define CC_COMM_INT_STA__W 16 +#define CC_COMM_INT_STA__M 0xFFFF +#define CC_COMM_INT_MSK__A 0x2400008 +#define CC_COMM_INT_MSK__W 16 +#define CC_COMM_INT_MSK__M 0xFFFF + + + + + + + +#define CC_REG_COMM_EXEC__A 0x2410000 +#define CC_REG_COMM_EXEC__W 3 +#define CC_REG_COMM_EXEC__M 0x7 +#define CC_REG_COMM_EXEC_CTL__B 0 +#define CC_REG_COMM_EXEC_CTL__W 3 +#define CC_REG_COMM_EXEC_CTL__M 0x7 +#define CC_REG_COMM_EXEC_CTL_STOP 0x0 +#define CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define CC_REG_COMM_EXEC_CTL_HOLD 0x2 +#define CC_REG_COMM_EXEC_CTL_STEP 0x3 +#define CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define CC_REG_COMM_STATE__A 0x2410001 +#define CC_REG_COMM_STATE__W 16 +#define CC_REG_COMM_STATE__M 0xFFFF +#define CC_REG_COMM_MB__A 0x2410002 +#define CC_REG_COMM_MB__W 16 +#define CC_REG_COMM_MB__M 0xFFFF +#define CC_REG_COMM_SERVICE0__A 0x2410003 +#define CC_REG_COMM_SERVICE0__W 16 +#define CC_REG_COMM_SERVICE0__M 0xFFFF +#define CC_REG_COMM_SERVICE1__A 0x2410004 +#define CC_REG_COMM_SERVICE1__W 16 +#define CC_REG_COMM_SERVICE1__M 0xFFFF +#define CC_REG_COMM_INT_STA__A 0x2410007 +#define CC_REG_COMM_INT_STA__W 16 +#define CC_REG_COMM_INT_STA__M 0xFFFF +#define CC_REG_COMM_INT_MSK__A 0x2410008 +#define CC_REG_COMM_INT_MSK__W 16 +#define CC_REG_COMM_INT_MSK__M 0xFFFF + +#define CC_REG_OSC_MODE__A 0x2410010 +#define CC_REG_OSC_MODE__W 2 +#define CC_REG_OSC_MODE__M 0x3 +#define CC_REG_OSC_MODE_OHW 0x0 +#define CC_REG_OSC_MODE_M20 0x1 +#define CC_REG_OSC_MODE_M48 0x2 + + +#define CC_REG_PLL_MODE__A 0x2410011 +#define CC_REG_PLL_MODE__W 6 +#define CC_REG_PLL_MODE__M 0x3F +#define CC_REG_PLL_MODE_INIT 0xC +#define CC_REG_PLL_MODE_BYPASS__B 0 +#define CC_REG_PLL_MODE_BYPASS__W 2 +#define CC_REG_PLL_MODE_BYPASS__M 0x3 +#define CC_REG_PLL_MODE_BYPASS_OHW 0x0 +#define CC_REG_PLL_MODE_BYPASS_PLL 0x1 +#define CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 +#define CC_REG_PLL_MODE_PUMP__B 2 +#define CC_REG_PLL_MODE_PUMP__W 3 +#define CC_REG_PLL_MODE_PUMP__M 0x1C +#define CC_REG_PLL_MODE_PUMP_OFF 0x0 +#define CC_REG_PLL_MODE_PUMP_CUR_08 0x4 +#define CC_REG_PLL_MODE_PUMP_CUR_09 0x8 +#define CC_REG_PLL_MODE_PUMP_CUR_10 0xC +#define CC_REG_PLL_MODE_PUMP_CUR_11 0x10 +#define CC_REG_PLL_MODE_PUMP_CUR_12 0x14 +#define CC_REG_PLL_MODE_OUT_EN__B 5 +#define CC_REG_PLL_MODE_OUT_EN__W 1 +#define CC_REG_PLL_MODE_OUT_EN__M 0x20 +#define CC_REG_PLL_MODE_OUT_EN_OFF 0x0 +#define CC_REG_PLL_MODE_OUT_EN_ON 0x20 + + +#define CC_REG_REF_DIVIDE__A 0x2410012 +#define CC_REG_REF_DIVIDE__W 4 +#define CC_REG_REF_DIVIDE__M 0xF +#define CC_REG_REF_DIVIDE_INIT 0xA +#define CC_REG_REF_DIVIDE_OHW 0x0 +#define CC_REG_REF_DIVIDE_D01 0x1 +#define CC_REG_REF_DIVIDE_D02 0x2 +#define CC_REG_REF_DIVIDE_D03 0x3 +#define CC_REG_REF_DIVIDE_D04 0x4 +#define CC_REG_REF_DIVIDE_D05 0x5 +#define CC_REG_REF_DIVIDE_D06 0x6 +#define CC_REG_REF_DIVIDE_D07 0x7 +#define CC_REG_REF_DIVIDE_D08 0x8 +#define CC_REG_REF_DIVIDE_D09 0x9 +#define CC_REG_REF_DIVIDE_D10 0xA + + +#define CC_REG_REF_DELAY__A 0x2410013 +#define CC_REG_REF_DELAY__W 3 +#define CC_REG_REF_DELAY__M 0x7 +#define CC_REG_REF_DELAY_EDGE__B 0 +#define CC_REG_REF_DELAY_EDGE__W 1 +#define CC_REG_REF_DELAY_EDGE__M 0x1 +#define CC_REG_REF_DELAY_EDGE_POS 0x0 +#define CC_REG_REF_DELAY_EDGE_NEG 0x1 +#define CC_REG_REF_DELAY_DELAY__B 1 +#define CC_REG_REF_DELAY_DELAY__W 2 +#define CC_REG_REF_DELAY_DELAY__M 0x6 +#define CC_REG_REF_DELAY_DELAY_DEL_0 0x0 +#define CC_REG_REF_DELAY_DELAY_DEL_3 0x2 +#define CC_REG_REF_DELAY_DELAY_DEL_6 0x4 +#define CC_REG_REF_DELAY_DELAY_DEL_9 0x6 + + +#define CC_REG_CLK_DELAY__A 0x2410014 +#define CC_REG_CLK_DELAY__W 4 +#define CC_REG_CLK_DELAY__M 0xF +#define CC_REG_CLK_DELAY_OFF 0x0 + + +#define CC_REG_PWD_MODE__A 0x2410015 +#define CC_REG_PWD_MODE__W 2 +#define CC_REG_PWD_MODE__M 0x3 +#define CC_REG_PWD_MODE_UP 0x0 +#define CC_REG_PWD_MODE_DOWN_CLK 0x1 +#define CC_REG_PWD_MODE_DOWN_PLL 0x2 +#define CC_REG_PWD_MODE_DOWN_OSC 0x3 + + +#define CC_REG_SOFT_RST__A 0x2410016 +#define CC_REG_SOFT_RST__W 2 +#define CC_REG_SOFT_RST__M 0x3 +#define CC_REG_SOFT_RST_SYS__B 0 +#define CC_REG_SOFT_RST_SYS__W 1 +#define CC_REG_SOFT_RST_SYS__M 0x1 +#define CC_REG_SOFT_RST_OSC__B 1 +#define CC_REG_SOFT_RST_OSC__W 1 +#define CC_REG_SOFT_RST_OSC__M 0x2 + + +#define CC_REG_UPDATE__A 0x2410017 +#define CC_REG_UPDATE__W 16 +#define CC_REG_UPDATE__M 0xFFFF +#define CC_REG_UPDATE_KEY 0x3973 + + +#define CC_REG_PLL_LOCK__A 0x2410018 +#define CC_REG_PLL_LOCK__W 1 +#define CC_REG_PLL_LOCK__M 0x1 +#define CC_REG_PLL_LOCK_LOCK 0x1 + + +#define CC_REG_JTAGID_L__A 0x2410019 +#define CC_REG_JTAGID_L__W 16 +#define CC_REG_JTAGID_L__M 0xFFFF +#define CC_REG_JTAGID_L_INIT 0x0 + + +#define CC_REG_JTAGID_H__A 0x241001A +#define CC_REG_JTAGID_H__W 16 +#define CC_REG_JTAGID_H__M 0xFFFF +#define CC_REG_JTAGID_H_INIT 0x0 + + + + + +#define LC_SID 0x1C + + + + + +#define LC_COMM_EXEC__A 0x2800000 +#define LC_COMM_EXEC__W 3 +#define LC_COMM_EXEC__M 0x7 +#define LC_COMM_EXEC_CTL__B 0 +#define LC_COMM_EXEC_CTL__W 3 +#define LC_COMM_EXEC_CTL__M 0x7 +#define LC_COMM_EXEC_CTL_STOP 0x0 +#define LC_COMM_EXEC_CTL_ACTIVE 0x1 +#define LC_COMM_EXEC_CTL_HOLD 0x2 +#define LC_COMM_EXEC_CTL_STEP 0x3 +#define LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define LC_COMM_STATE__A 0x2800001 +#define LC_COMM_STATE__W 16 +#define LC_COMM_STATE__M 0xFFFF +#define LC_COMM_MB__A 0x2800002 +#define LC_COMM_MB__W 16 +#define LC_COMM_MB__M 0xFFFF +#define LC_COMM_SERVICE0__A 0x2800003 +#define LC_COMM_SERVICE0__W 16 +#define LC_COMM_SERVICE0__M 0xFFFF +#define LC_COMM_SERVICE1__A 0x2800004 +#define LC_COMM_SERVICE1__W 16 +#define LC_COMM_SERVICE1__M 0xFFFF +#define LC_COMM_INT_STA__A 0x2800007 +#define LC_COMM_INT_STA__W 16 +#define LC_COMM_INT_STA__M 0xFFFF +#define LC_COMM_INT_MSK__A 0x2800008 +#define LC_COMM_INT_MSK__W 16 +#define LC_COMM_INT_MSK__M 0xFFFF + + + + + + +#define LC_CT_REG_COMM_EXEC__A 0x2810000 +#define LC_CT_REG_COMM_EXEC__W 3 +#define LC_CT_REG_COMM_EXEC__M 0x7 +#define LC_CT_REG_COMM_EXEC_CTL__B 0 +#define LC_CT_REG_COMM_EXEC_CTL__W 3 +#define LC_CT_REG_COMM_EXEC_CTL__M 0x7 +#define LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define LC_CT_REG_COMM_STATE__A 0x2810001 +#define LC_CT_REG_COMM_STATE__W 10 +#define LC_CT_REG_COMM_STATE__M 0x3FF +#define LC_CT_REG_COMM_SERVICE0__A 0x2810003 +#define LC_CT_REG_COMM_SERVICE0__W 16 +#define LC_CT_REG_COMM_SERVICE0__M 0xFFFF +#define LC_CT_REG_COMM_SERVICE1__A 0x2810004 +#define LC_CT_REG_COMM_SERVICE1__W 16 +#define LC_CT_REG_COMM_SERVICE1__M 0xFFFF +#define LC_CT_REG_COMM_SERVICE1_LC__B 12 +#define LC_CT_REG_COMM_SERVICE1_LC__W 1 +#define LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 + + +#define LC_CT_REG_COMM_INT_STA__A 0x2810007 +#define LC_CT_REG_COMM_INT_STA__W 1 +#define LC_CT_REG_COMM_INT_STA__M 0x1 +#define LC_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define LC_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + + +#define LC_CT_REG_COMM_INT_MSK__A 0x2810008 +#define LC_CT_REG_COMM_INT_MSK__W 1 +#define LC_CT_REG_COMM_INT_MSK__M 0x1 +#define LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + + + + +#define LC_CT_REG_CTL_STK__AX 0x2810010 +#define LC_CT_REG_CTL_STK__XSZ 4 +#define LC_CT_REG_CTL_STK__W 10 +#define LC_CT_REG_CTL_STK__M 0x3FF + +#define LC_CT_REG_CTL_BPT_IDX__A 0x281001F +#define LC_CT_REG_CTL_BPT_IDX__W 1 +#define LC_CT_REG_CTL_BPT_IDX__M 0x1 + +#define LC_CT_REG_CTL_BPT__A 0x2810020 +#define LC_CT_REG_CTL_BPT__W 10 +#define LC_CT_REG_CTL_BPT__M 0x3FF + + + + + +#define LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 +#define LC_RA_RAM_PROC_DELAY_IF__W 16 +#define LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF +#define LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 +#define LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 +#define LC_RA_RAM_PROC_DELAY_FS__W 16 +#define LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF +#define LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 +#define LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 +#define LC_RA_RAM_LOCK_TH_CRMM__W 16 +#define LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF +#define LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 +#define LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 +#define LC_RA_RAM_LOCK_TH_SRMM__W 16 +#define LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF +#define LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 +#define LC_RA_RAM_LOCK_COUNT__A 0x282000A +#define LC_RA_RAM_LOCK_COUNT__W 16 +#define LC_RA_RAM_LOCK_COUNT__M 0xFFFF +#define LC_RA_RAM_CPRTOFS_NOM__A 0x282000B +#define LC_RA_RAM_CPRTOFS_NOM__W 16 +#define LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF +#define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C +#define LC_RA_RAM_IFINCR_NOM_L__W 16 +#define LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF +#define LC_RA_RAM_IFINCR_NOM_H__A 0x282000D +#define LC_RA_RAM_IFINCR_NOM_H__W 16 +#define LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF +#define LC_RA_RAM_FSINCR_NOM_L__A 0x282000E +#define LC_RA_RAM_FSINCR_NOM_L__W 16 +#define LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF +#define LC_RA_RAM_FSINCR_NOM_H__A 0x282000F +#define LC_RA_RAM_FSINCR_NOM_H__W 16 +#define LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF +#define LC_RA_RAM_MODE_2K__A 0x2820010 +#define LC_RA_RAM_MODE_2K__W 16 +#define LC_RA_RAM_MODE_2K__M 0xFFFF +#define LC_RA_RAM_MODE_GUARD__A 0x2820011 +#define LC_RA_RAM_MODE_GUARD__W 16 +#define LC_RA_RAM_MODE_GUARD__M 0xFFFF +#define LC_RA_RAM_MODE_GUARD_32 0x0 +#define LC_RA_RAM_MODE_GUARD_16 0x1 +#define LC_RA_RAM_MODE_GUARD_8 0x2 +#define LC_RA_RAM_MODE_GUARD_4 0x3 + +#define LC_RA_RAM_MODE_ADJUST__A 0x2820012 +#define LC_RA_RAM_MODE_ADJUST__W 16 +#define LC_RA_RAM_MODE_ADJUST__M 0xFFFF +#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 +#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 +#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 +#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 +#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 +#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 +#define LC_RA_RAM_MODE_ADJUST_SRMM__B 2 +#define LC_RA_RAM_MODE_ADJUST_SRMM__W 1 +#define LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 +#define LC_RA_RAM_MODE_ADJUST_PHASE__B 3 +#define LC_RA_RAM_MODE_ADJUST_PHASE__W 1 +#define LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 +#define LC_RA_RAM_MODE_ADJUST_DELAY__B 4 +#define LC_RA_RAM_MODE_ADJUST_DELAY__W 1 +#define LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 +#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 +#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 +#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 +#define LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 +#define LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 +#define LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 +#define LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 +#define LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 +#define LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 +#define LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 +#define LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 +#define LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 +#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 +#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 +#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 + +#define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A +#define LC_RA_RAM_FILTER_SYM_SET__W 16 +#define LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF +#define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 +#define LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B +#define LC_RA_RAM_FILTER_SYM_CUR__W 16 +#define LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF +#define LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 +#define LC_RA_RAM_MAX_ABS_EXP__A 0x282001D +#define LC_RA_RAM_MAX_ABS_EXP__W 16 +#define LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF +#define LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 +#define LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F +#define LC_RA_RAM_ACTUAL_CP_CRMM__W 16 +#define LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF +#define LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 +#define LC_RA_RAM_ACTUAL_CE_CRMM__W 16 +#define LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF +#define LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 +#define LC_RA_RAM_ACTUAL_CE_SRMM__W 16 +#define LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF +#define LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 +#define LC_RA_RAM_ACTUAL_PHASE__W 16 +#define LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF +#define LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 +#define LC_RA_RAM_ACTUAL_DELAY__W 16 +#define LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF +#define LC_RA_RAM_ADJUST_CRMM__A 0x2820024 +#define LC_RA_RAM_ADJUST_CRMM__W 16 +#define LC_RA_RAM_ADJUST_CRMM__M 0xFFFF +#define LC_RA_RAM_ADJUST_SRMM__A 0x2820025 +#define LC_RA_RAM_ADJUST_SRMM__W 16 +#define LC_RA_RAM_ADJUST_SRMM__M 0xFFFF +#define LC_RA_RAM_ADJUST_PHASE__A 0x2820026 +#define LC_RA_RAM_ADJUST_PHASE__W 16 +#define LC_RA_RAM_ADJUST_PHASE__M 0xFFFF +#define LC_RA_RAM_ADJUST_DELAY__A 0x2820027 +#define LC_RA_RAM_ADJUST_DELAY__W 16 +#define LC_RA_RAM_ADJUST_DELAY__M 0xFFFF + + + + + +#define LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 +#define LC_RA_RAM_PIPE_CP_PHASE_0__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 +#define LC_RA_RAM_PIPE_CP_PHASE_1__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A +#define LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B +#define LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C +#define LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D +#define LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF + + + +#define LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 +#define LC_RA_RAM_PIPE_CP_CRMM_0__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 +#define LC_RA_RAM_PIPE_CP_CRMM_1__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 +#define LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 +#define LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 +#define LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 +#define LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF + + + +#define LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 +#define LC_RA_RAM_PIPE_CP_SRMM_0__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 +#define LC_RA_RAM_PIPE_CP_SRMM_1__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A +#define LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B +#define LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C +#define LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D +#define LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF + + + + + +#define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 +#define LC_RA_RAM_FILTER_CRMM_A__W 16 +#define LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF +#define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 +#define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 +#define LC_RA_RAM_FILTER_CRMM_B__W 16 +#define LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF +#define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 +#define LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 +#define LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 +#define LC_RA_RAM_FILTER_CRMM_Z1__W 16 +#define LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF +#define LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 +#define LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 +#define LC_RA_RAM_FILTER_CRMM_Z2__W 16 +#define LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF +#define LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 +#define LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 +#define LC_RA_RAM_FILTER_CRMM_TMP__W 16 +#define LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF + + + +#define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 +#define LC_RA_RAM_FILTER_SRMM_A__W 16 +#define LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF +#define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 +#define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 +#define LC_RA_RAM_FILTER_SRMM_B__W 16 +#define LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF +#define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 +#define LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A +#define LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 +#define LC_RA_RAM_FILTER_SRMM_Z1__W 16 +#define LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF +#define LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C +#define LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 +#define LC_RA_RAM_FILTER_SRMM_Z2__W 16 +#define LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF +#define LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E +#define LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 +#define LC_RA_RAM_FILTER_SRMM_TMP__W 16 +#define LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF + + + +#define LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 +#define LC_RA_RAM_FILTER_PHASE_A__W 16 +#define LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF +#define LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 +#define LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 +#define LC_RA_RAM_FILTER_PHASE_B__W 16 +#define LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF +#define LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 +#define LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 +#define LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 +#define LC_RA_RAM_FILTER_PHASE_Z1__W 16 +#define LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF +#define LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 +#define LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 +#define LC_RA_RAM_FILTER_PHASE_Z2__W 16 +#define LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF +#define LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 +#define LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 +#define LC_RA_RAM_FILTER_PHASE_TMP__W 16 +#define LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF + + + +#define LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 +#define LC_RA_RAM_FILTER_DELAY_A__W 16 +#define LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF +#define LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 +#define LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 +#define LC_RA_RAM_FILTER_DELAY_B__W 16 +#define LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF +#define LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 +#define LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A +#define LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 +#define LC_RA_RAM_FILTER_DELAY_Z1__W 16 +#define LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF +#define LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C +#define LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 +#define LC_RA_RAM_FILTER_DELAY_Z2__W 16 +#define LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF +#define LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E +#define LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 +#define LC_RA_RAM_FILTER_DELAY_TMP__W 16 +#define LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF + + + + + + +#define LC_IF_RAM_TRP_BPT0__AX 0x2830000 +#define LC_IF_RAM_TRP_BPT0__XSZ 2 +#define LC_IF_RAM_TRP_BPT0__W 12 +#define LC_IF_RAM_TRP_BPT0__M 0xFFF + +#define LC_IF_RAM_TRP_STKU__AX 0x2830002 +#define LC_IF_RAM_TRP_STKU__XSZ 2 +#define LC_IF_RAM_TRP_STKU__W 12 +#define LC_IF_RAM_TRP_STKU__M 0xFFF + +#define LC_IF_RAM_TRP_WARM__AX 0x2830006 +#define LC_IF_RAM_TRP_WARM__XSZ 2 +#define LC_IF_RAM_TRP_WARM__W 12 +#define LC_IF_RAM_TRP_WARM__M 0xFFF + + + + + + + +#define B_HI_SID 0x10 + + + + + +#define B_HI_COMM_EXEC__A 0x400000 +#define B_HI_COMM_EXEC__W 3 +#define B_HI_COMM_EXEC__M 0x7 +#define B_HI_COMM_EXEC_CTL__B 0 +#define B_HI_COMM_EXEC_CTL__W 3 +#define B_HI_COMM_EXEC_CTL__M 0x7 +#define B_HI_COMM_EXEC_CTL_STOP 0x0 +#define B_HI_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_HI_COMM_EXEC_CTL_HOLD 0x2 +#define B_HI_COMM_EXEC_CTL_STEP 0x3 +#define B_HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_HI_COMM_STATE__A 0x400001 +#define B_HI_COMM_STATE__W 16 +#define B_HI_COMM_STATE__M 0xFFFF +#define B_HI_COMM_MB__A 0x400002 +#define B_HI_COMM_MB__W 16 +#define B_HI_COMM_MB__M 0xFFFF +#define B_HI_COMM_SERVICE0__A 0x400003 +#define B_HI_COMM_SERVICE0__W 16 +#define B_HI_COMM_SERVICE0__M 0xFFFF +#define B_HI_COMM_SERVICE1__A 0x400004 +#define B_HI_COMM_SERVICE1__W 16 +#define B_HI_COMM_SERVICE1__M 0xFFFF +#define B_HI_COMM_INT_STA__A 0x400007 +#define B_HI_COMM_INT_STA__W 16 +#define B_HI_COMM_INT_STA__M 0xFFFF +#define B_HI_COMM_INT_MSK__A 0x400008 +#define B_HI_COMM_INT_MSK__W 16 +#define B_HI_COMM_INT_MSK__M 0xFFFF + + + + + + +#define B_HI_CT_REG_COMM_EXEC__A 0x410000 +#define B_HI_CT_REG_COMM_EXEC__W 3 +#define B_HI_CT_REG_COMM_EXEC__M 0x7 +#define B_HI_CT_REG_COMM_EXEC_CTL__B 0 +#define B_HI_CT_REG_COMM_EXEC_CTL__W 3 +#define B_HI_CT_REG_COMM_EXEC_CTL__M 0x7 +#define B_HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define B_HI_CT_REG_COMM_STATE__A 0x410001 +#define B_HI_CT_REG_COMM_STATE__W 10 +#define B_HI_CT_REG_COMM_STATE__M 0x3FF +#define B_HI_CT_REG_COMM_SERVICE0__A 0x410003 +#define B_HI_CT_REG_COMM_SERVICE0__W 16 +#define B_HI_CT_REG_COMM_SERVICE0__M 0xFFFF +#define B_HI_CT_REG_COMM_SERVICE1__A 0x410004 +#define B_HI_CT_REG_COMM_SERVICE1__W 16 +#define B_HI_CT_REG_COMM_SERVICE1__M 0xFFFF +#define B_HI_CT_REG_COMM_SERVICE1_HI__B 0 +#define B_HI_CT_REG_COMM_SERVICE1_HI__W 1 +#define B_HI_CT_REG_COMM_SERVICE1_HI__M 0x1 + + +#define B_HI_CT_REG_COMM_INT_STA__A 0x410007 +#define B_HI_CT_REG_COMM_INT_STA__W 1 +#define B_HI_CT_REG_COMM_INT_STA__M 0x1 +#define B_HI_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define B_HI_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define B_HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + + +#define B_HI_CT_REG_COMM_INT_MSK__A 0x410008 +#define B_HI_CT_REG_COMM_INT_MSK__W 1 +#define B_HI_CT_REG_COMM_INT_MSK__M 0x1 +#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + + + + +#define B_HI_CT_REG_CTL_STK__AX 0x410010 +#define B_HI_CT_REG_CTL_STK__XSZ 4 +#define B_HI_CT_REG_CTL_STK__W 10 +#define B_HI_CT_REG_CTL_STK__M 0x3FF + +#define B_HI_CT_REG_CTL_BPT_IDX__A 0x41001F +#define B_HI_CT_REG_CTL_BPT_IDX__W 1 +#define B_HI_CT_REG_CTL_BPT_IDX__M 0x1 + +#define B_HI_CT_REG_CTL_BPT__A 0x410020 +#define B_HI_CT_REG_CTL_BPT__W 10 +#define B_HI_CT_REG_CTL_BPT__M 0x3FF + + + + + + +#define B_HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 +#define B_HI_RA_RAM_SLV0_FLG_SMM__W 1 +#define B_HI_RA_RAM_SLV0_FLG_SMM__M 0x1 +#define B_HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 +#define B_HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 + + +#define B_HI_RA_RAM_SLV0_DEV_ID__A 0x420011 +#define B_HI_RA_RAM_SLV0_DEV_ID__W 7 +#define B_HI_RA_RAM_SLV0_DEV_ID__M 0x7F + +#define B_HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 +#define B_HI_RA_RAM_SLV0_FLG_CRC__W 1 +#define B_HI_RA_RAM_SLV0_FLG_CRC__M 0x1 +#define B_HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 +#define B_HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 + + +#define B_HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 +#define B_HI_RA_RAM_SLV0_FLG_ACC__W 3 +#define B_HI_RA_RAM_SLV0_FLG_ACC__M 0x7 +#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 +#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 +#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 +#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 +#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 +#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 +#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 +#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 +#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 +#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 + + +#define B_HI_RA_RAM_SLV0_STATE__A 0x420014 +#define B_HI_RA_RAM_SLV0_STATE__W 1 +#define B_HI_RA_RAM_SLV0_STATE__M 0x1 +#define B_HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 +#define B_HI_RA_RAM_SLV0_STATE_DATA 0x1 + + +#define B_HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 +#define B_HI_RA_RAM_SLV0_BLK_BNK__W 12 +#define B_HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF +#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 +#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 +#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F +#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 +#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 +#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 + + +#define B_HI_RA_RAM_SLV0_ADDR__A 0x420016 +#define B_HI_RA_RAM_SLV0_ADDR__W 16 +#define B_HI_RA_RAM_SLV0_ADDR__M 0xFFFF + +#define B_HI_RA_RAM_SLV0_CRC__A 0x420017 +#define B_HI_RA_RAM_SLV0_CRC__W 16 +#define B_HI_RA_RAM_SLV0_CRC__M 0xFFFF + +#define B_HI_RA_RAM_SLV0_READBACK__A 0x420018 +#define B_HI_RA_RAM_SLV0_READBACK__W 16 +#define B_HI_RA_RAM_SLV0_READBACK__M 0xFFFF + + + + +#define B_HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 +#define B_HI_RA_RAM_SLV1_FLG_SMM__W 1 +#define B_HI_RA_RAM_SLV1_FLG_SMM__M 0x1 +#define B_HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 +#define B_HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 + + +#define B_HI_RA_RAM_SLV1_DEV_ID__A 0x420021 +#define B_HI_RA_RAM_SLV1_DEV_ID__W 7 +#define B_HI_RA_RAM_SLV1_DEV_ID__M 0x7F + +#define B_HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 +#define B_HI_RA_RAM_SLV1_FLG_CRC__W 1 +#define B_HI_RA_RAM_SLV1_FLG_CRC__M 0x1 +#define B_HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 +#define B_HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 + + +#define B_HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 +#define B_HI_RA_RAM_SLV1_FLG_ACC__W 3 +#define B_HI_RA_RAM_SLV1_FLG_ACC__M 0x7 +#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 +#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 +#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 +#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 +#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 +#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 +#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 +#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 +#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 +#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 + + +#define B_HI_RA_RAM_SLV1_STATE__A 0x420024 +#define B_HI_RA_RAM_SLV1_STATE__W 1 +#define B_HI_RA_RAM_SLV1_STATE__M 0x1 +#define B_HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 +#define B_HI_RA_RAM_SLV1_STATE_DATA 0x1 + + +#define B_HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 +#define B_HI_RA_RAM_SLV1_BLK_BNK__W 12 +#define B_HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF +#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 +#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 +#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F +#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 +#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 +#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 + + +#define B_HI_RA_RAM_SLV1_ADDR__A 0x420026 +#define B_HI_RA_RAM_SLV1_ADDR__W 16 +#define B_HI_RA_RAM_SLV1_ADDR__M 0xFFFF + +#define B_HI_RA_RAM_SLV1_CRC__A 0x420027 +#define B_HI_RA_RAM_SLV1_CRC__W 16 +#define B_HI_RA_RAM_SLV1_CRC__M 0xFFFF + +#define B_HI_RA_RAM_SLV1_READBACK__A 0x420028 +#define B_HI_RA_RAM_SLV1_READBACK__W 16 +#define B_HI_RA_RAM_SLV1_READBACK__M 0xFFFF + + + + +#define B_HI_RA_RAM_SRV_SEM__A 0x420030 +#define B_HI_RA_RAM_SRV_SEM__W 1 +#define B_HI_RA_RAM_SRV_SEM__M 0x1 +#define B_HI_RA_RAM_SRV_SEM_FREE 0x0 +#define B_HI_RA_RAM_SRV_SEM_CLAIMED 0x1 + + +#define B_HI_RA_RAM_SRV_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_RES__W 3 +#define B_HI_RA_RAM_SRV_RES__M 0x7 +#define B_HI_RA_RAM_SRV_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 +#define B_HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 +#define B_HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 +#define B_HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 + + +#define B_HI_RA_RAM_SRV_CMD__A 0x420032 +#define B_HI_RA_RAM_SRV_CMD__W 3 +#define B_HI_RA_RAM_SRV_CMD__M 0x7 +#define B_HI_RA_RAM_SRV_CMD_NULL 0x0 +#define B_HI_RA_RAM_SRV_CMD_UIO 0x1 +#define B_HI_RA_RAM_SRV_CMD_RESET 0x2 +#define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3 +#define B_HI_RA_RAM_SRV_CMD_COPY 0x4 +#define B_HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 +#define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 + + +#define B_HI_RA_RAM_SRV_PAR__AX 0x420033 +#define B_HI_RA_RAM_SRV_PAR__XSZ 5 +#define B_HI_RA_RAM_SRV_PAR__W 16 +#define B_HI_RA_RAM_SRV_PAR__M 0xFFFF + + + +#define B_HI_RA_RAM_SRV_NOP_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_NOP_RES__W 3 +#define B_HI_RA_RAM_SRV_NOP_RES__M 0x7 +#define B_HI_RA_RAM_SRV_NOP_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 + + + +#define B_HI_RA_RAM_SRV_UIO_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_UIO_RES__W 3 +#define B_HI_RA_RAM_SRV_UIO_RES__M 0x7 +#define B_HI_RA_RAM_SRV_UIO_RES_LO 0x0 +#define B_HI_RA_RAM_SRV_UIO_RES_HI 0x1 + +#define B_HI_RA_RAM_SRV_UIO_KEY__A 0x420033 +#define B_HI_RA_RAM_SRV_UIO_KEY__W 16 +#define B_HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF +#define B_HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 + +#define B_HI_RA_RAM_SRV_UIO_SEL__A 0x420034 +#define B_HI_RA_RAM_SRV_UIO_SEL__W 2 +#define B_HI_RA_RAM_SRV_UIO_SEL__M 0x3 +#define B_HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 +#define B_HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 + +#define B_HI_RA_RAM_SRV_UIO_SET__A 0x420035 +#define B_HI_RA_RAM_SRV_UIO_SET__W 2 +#define B_HI_RA_RAM_SRV_UIO_SET__M 0x3 +#define B_HI_RA_RAM_SRV_UIO_SET_OUT__B 0 +#define B_HI_RA_RAM_SRV_UIO_SET_OUT__W 1 +#define B_HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 +#define B_HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 +#define B_HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 +#define B_HI_RA_RAM_SRV_UIO_SET_DIR__B 1 +#define B_HI_RA_RAM_SRV_UIO_SET_DIR__W 1 +#define B_HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 +#define B_HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 +#define B_HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 + + + +#define B_HI_RA_RAM_SRV_RST_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_RST_RES__W 1 +#define B_HI_RA_RAM_SRV_RST_RES__M 0x1 +#define B_HI_RA_RAM_SRV_RST_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_RST_RES_ERROR 0x1 + +#define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033 +#define B_HI_RA_RAM_SRV_RST_KEY__W 16 +#define B_HI_RA_RAM_SRV_RST_KEY__M 0xFFFF +#define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 + + + +#define B_HI_RA_RAM_SRV_CFG_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_CFG_RES__W 1 +#define B_HI_RA_RAM_SRV_CFG_RES__M 0x1 +#define B_HI_RA_RAM_SRV_CFG_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 + +#define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033 +#define B_HI_RA_RAM_SRV_CFG_KEY__W 16 +#define B_HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF +#define B_HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 + + +#define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 +#define B_HI_RA_RAM_SRV_CFG_DIV__W 5 +#define B_HI_RA_RAM_SRV_CFG_DIV__M 0x1F + +#define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035 +#define B_HI_RA_RAM_SRV_CFG_BDL__W 6 +#define B_HI_RA_RAM_SRV_CFG_BDL__M 0x3F + +#define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036 +#define B_HI_RA_RAM_SRV_CFG_WUP__W 8 +#define B_HI_RA_RAM_SRV_CFG_WUP__M 0xFF + +#define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037 +#define B_HI_RA_RAM_SRV_CFG_ACT__W 4 +#define B_HI_RA_RAM_SRV_CFG_ACT__M 0xF +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 +#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 +#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 +#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 +#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 +#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 +#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 +#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 +#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 +#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 +#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 + + + +#define B_HI_RA_RAM_SRV_CPY_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_CPY_RES__W 1 +#define B_HI_RA_RAM_SRV_CPY_RES__M 0x1 +#define B_HI_RA_RAM_SRV_CPY_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 + + +#define B_HI_RA_RAM_SRV_CPY_SBB__A 0x420033 +#define B_HI_RA_RAM_SRV_CPY_SBB__W 12 +#define B_HI_RA_RAM_SRV_CPY_SBB__M 0xFFF +#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 +#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 +#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F +#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 +#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 +#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 + + +#define B_HI_RA_RAM_SRV_CPY_SAD__A 0x420034 +#define B_HI_RA_RAM_SRV_CPY_SAD__W 16 +#define B_HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF + +#define B_HI_RA_RAM_SRV_CPY_LEN__A 0x420035 +#define B_HI_RA_RAM_SRV_CPY_LEN__W 16 +#define B_HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF + +#define B_HI_RA_RAM_SRV_CPY_DBB__A 0x420033 +#define B_HI_RA_RAM_SRV_CPY_DBB__W 12 +#define B_HI_RA_RAM_SRV_CPY_DBB__M 0xFFF +#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 +#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 +#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F +#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 +#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 +#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 + + +#define B_HI_RA_RAM_SRV_CPY_DAD__A 0x420034 +#define B_HI_RA_RAM_SRV_CPY_DAD__W 16 +#define B_HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF + + + +#define B_HI_RA_RAM_SRV_TRM_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_TRM_RES__W 2 +#define B_HI_RA_RAM_SRV_TRM_RES__M 0x3 +#define B_HI_RA_RAM_SRV_TRM_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 +#define B_HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 + + +#define B_HI_RA_RAM_SRV_TRM_MST__A 0x420033 +#define B_HI_RA_RAM_SRV_TRM_MST__W 12 +#define B_HI_RA_RAM_SRV_TRM_MST__M 0xFFF + +#define B_HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 +#define B_HI_RA_RAM_SRV_TRM_SEQ__W 7 +#define B_HI_RA_RAM_SRV_TRM_SEQ__M 0x7F + +#define B_HI_RA_RAM_SRV_TRM_TRM__A 0x420035 +#define B_HI_RA_RAM_SRV_TRM_TRM__W 15 +#define B_HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF +#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 +#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 +#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF + + +#define B_HI_RA_RAM_SRV_TRM_DBB__A 0x420033 +#define B_HI_RA_RAM_SRV_TRM_DBB__W 12 +#define B_HI_RA_RAM_SRV_TRM_DBB__M 0xFFF +#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 +#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 +#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F +#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 +#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 +#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 + + +#define B_HI_RA_RAM_SRV_TRM_DAD__A 0x420034 +#define B_HI_RA_RAM_SRV_TRM_DAD__W 16 +#define B_HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF + + + + +#define B_HI_RA_RAM_USR_BEGIN__A 0x420040 +#define B_HI_RA_RAM_USR_BEGIN__W 16 +#define B_HI_RA_RAM_USR_BEGIN__M 0xFFFF + +#define B_HI_RA_RAM_USR_END__A 0x42007F +#define B_HI_RA_RAM_USR_END__W 16 +#define B_HI_RA_RAM_USR_END__M 0xFFFF + + + + + + +#define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 +#define B_HI_IF_RAM_TRP_BPT0__XSZ 2 +#define B_HI_IF_RAM_TRP_BPT0__W 12 +#define B_HI_IF_RAM_TRP_BPT0__M 0xFFF + +#define B_HI_IF_RAM_TRP_STKU__AX 0x430002 +#define B_HI_IF_RAM_TRP_STKU__XSZ 2 +#define B_HI_IF_RAM_TRP_STKU__W 12 +#define B_HI_IF_RAM_TRP_STKU__M 0xFFF + + + + +#define B_HI_IF_RAM_USR_BEGIN__A 0x430200 +#define B_HI_IF_RAM_USR_BEGIN__W 12 +#define B_HI_IF_RAM_USR_BEGIN__M 0xFFF + +#define B_HI_IF_RAM_USR_END__A 0x4303FF +#define B_HI_IF_RAM_USR_END__W 12 +#define B_HI_IF_RAM_USR_END__M 0xFFF + + + + + +#define B_SC_SID 0x11 + + + + + +#define B_SC_COMM_EXEC__A 0x800000 +#define B_SC_COMM_EXEC__W 3 +#define B_SC_COMM_EXEC__M 0x7 +#define B_SC_COMM_EXEC_CTL__B 0 +#define B_SC_COMM_EXEC_CTL__W 3 +#define B_SC_COMM_EXEC_CTL__M 0x7 +#define B_SC_COMM_EXEC_CTL_STOP 0x0 +#define B_SC_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_SC_COMM_EXEC_CTL_HOLD 0x2 +#define B_SC_COMM_EXEC_CTL_STEP 0x3 +#define B_SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_SC_COMM_STATE__A 0x800001 +#define B_SC_COMM_STATE__W 16 +#define B_SC_COMM_STATE__M 0xFFFF +#define B_SC_COMM_MB__A 0x800002 +#define B_SC_COMM_MB__W 16 +#define B_SC_COMM_MB__M 0xFFFF +#define B_SC_COMM_SERVICE0__A 0x800003 +#define B_SC_COMM_SERVICE0__W 16 +#define B_SC_COMM_SERVICE0__M 0xFFFF +#define B_SC_COMM_SERVICE1__A 0x800004 +#define B_SC_COMM_SERVICE1__W 16 +#define B_SC_COMM_SERVICE1__M 0xFFFF +#define B_SC_COMM_INT_STA__A 0x800007 +#define B_SC_COMM_INT_STA__W 16 +#define B_SC_COMM_INT_STA__M 0xFFFF +#define B_SC_COMM_INT_MSK__A 0x800008 +#define B_SC_COMM_INT_MSK__W 16 +#define B_SC_COMM_INT_MSK__M 0xFFFF + + + + + + +#define B_SC_CT_REG_COMM_EXEC__A 0x810000 +#define B_SC_CT_REG_COMM_EXEC__W 3 +#define B_SC_CT_REG_COMM_EXEC__M 0x7 +#define B_SC_CT_REG_COMM_EXEC_CTL__B 0 +#define B_SC_CT_REG_COMM_EXEC_CTL__W 3 +#define B_SC_CT_REG_COMM_EXEC_CTL__M 0x7 +#define B_SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define B_SC_CT_REG_COMM_STATE__A 0x810001 +#define B_SC_CT_REG_COMM_STATE__W 10 +#define B_SC_CT_REG_COMM_STATE__M 0x3FF +#define B_SC_CT_REG_COMM_SERVICE0__A 0x810003 +#define B_SC_CT_REG_COMM_SERVICE0__W 16 +#define B_SC_CT_REG_COMM_SERVICE0__M 0xFFFF +#define B_SC_CT_REG_COMM_SERVICE1__A 0x810004 +#define B_SC_CT_REG_COMM_SERVICE1__W 16 +#define B_SC_CT_REG_COMM_SERVICE1__M 0xFFFF +#define B_SC_CT_REG_COMM_SERVICE1_SC__B 1 +#define B_SC_CT_REG_COMM_SERVICE1_SC__W 1 +#define B_SC_CT_REG_COMM_SERVICE1_SC__M 0x2 + + +#define B_SC_CT_REG_COMM_INT_STA__A 0x810007 +#define B_SC_CT_REG_COMM_INT_STA__W 1 +#define B_SC_CT_REG_COMM_INT_STA__M 0x1 +#define B_SC_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define B_SC_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define B_SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + + +#define B_SC_CT_REG_COMM_INT_MSK__A 0x810008 +#define B_SC_CT_REG_COMM_INT_MSK__W 1 +#define B_SC_CT_REG_COMM_INT_MSK__M 0x1 +#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + + + + +#define B_SC_CT_REG_CTL_STK__AX 0x810010 +#define B_SC_CT_REG_CTL_STK__XSZ 4 +#define B_SC_CT_REG_CTL_STK__W 10 +#define B_SC_CT_REG_CTL_STK__M 0x3FF + +#define B_SC_CT_REG_CTL_BPT_IDX__A 0x81001F +#define B_SC_CT_REG_CTL_BPT_IDX__W 1 +#define B_SC_CT_REG_CTL_BPT_IDX__M 0x1 + +#define B_SC_CT_REG_CTL_BPT__A 0x810020 +#define B_SC_CT_REG_CTL_BPT__W 10 +#define B_SC_CT_REG_CTL_BPT__M 0x3FF + + + + + +#define B_SC_RA_RAM_PARAM0__A 0x820040 +#define B_SC_RA_RAM_PARAM0__W 16 +#define B_SC_RA_RAM_PARAM0__M 0xFFFF +#define B_SC_RA_RAM_PARAM1__A 0x820041 +#define B_SC_RA_RAM_PARAM1__W 16 +#define B_SC_RA_RAM_PARAM1__M 0xFFFF +#define B_SC_RA_RAM_CMD_ADDR__A 0x820042 +#define B_SC_RA_RAM_CMD_ADDR__W 16 +#define B_SC_RA_RAM_CMD_ADDR__M 0xFFFF +#define B_SC_RA_RAM_CMD__A 0x820043 +#define B_SC_RA_RAM_CMD__W 16 +#define B_SC_RA_RAM_CMD__M 0xFFFF +#define B_SC_RA_RAM_CMD_NULL 0x0 +#define B_SC_RA_RAM_CMD_PROC_START 0x1 +#define B_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 +#define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +#define B_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 +#define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 +#define B_SC_RA_RAM_CMD_USER_IO 0x6 +#define B_SC_RA_RAM_CMD_SET_TIMER 0x7 +#define B_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 +#define B_SC_RA_RAM_CMD_MAX 0x9 +#define B_SC_RA_RAM_CMDBLOCK__C 0x4 + +#define B_SC_RA_RAM_PROC_ACTIVATE__A 0x820044 +#define B_SC_RA_RAM_PROC_ACTIVATE__W 16 +#define B_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF +#define B_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF +#define B_SC_RA_RAM_PROC_TERMINATED__A 0x820045 +#define B_SC_RA_RAM_PROC_TERMINATED__W 16 +#define B_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF +#define B_SC_RA_RAM_SW_EVENT__A 0x820046 +#define B_SC_RA_RAM_SW_EVENT__W 14 +#define B_SC_RA_RAM_SW_EVENT__M 0x3FFF +#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 +#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 +#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 +#define B_SC_RA_RAM_SW_EVENT_RUN__B 1 +#define B_SC_RA_RAM_SW_EVENT_RUN__W 1 +#define B_SC_RA_RAM_SW_EVENT_RUN__M 0x2 +#define B_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 +#define B_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 +#define B_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 +#define B_SC_RA_RAM_SW_EVENT_FT_START__B 3 +#define B_SC_RA_RAM_SW_EVENT_FT_START__W 1 +#define B_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 +#define B_SC_RA_RAM_SW_EVENT_FI_START__B 4 +#define B_SC_RA_RAM_SW_EVENT_FI_START__W 1 +#define B_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 +#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 +#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 +#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 +#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 +#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 +#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 +#define B_SC_RA_RAM_SW_EVENT_CE_IR__B 7 +#define B_SC_RA_RAM_SW_EVENT_CE_IR__W 1 +#define B_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 +#define B_SC_RA_RAM_SW_EVENT_FE_FD__B 8 +#define B_SC_RA_RAM_SW_EVENT_FE_FD__W 1 +#define B_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 +#define B_SC_RA_RAM_SW_EVENT_FE_CF__B 9 +#define B_SC_RA_RAM_SW_EVENT_FE_CF__W 1 +#define B_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 +#define B_SC_RA_RAM_SW_EVENT_NF_READY__B 12 +#define B_SC_RA_RAM_SW_EVENT_NF_READY__W 1 +#define B_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 + +#define B_SC_RA_RAM_LOCKTRACK__A 0x820047 +#define B_SC_RA_RAM_LOCKTRACK__W 16 +#define B_SC_RA_RAM_LOCKTRACK__M 0xFFFF +#define B_SC_RA_RAM_LOCKTRACK_NULL 0x0 +#define B_SC_RA_RAM_LOCKTRACK_MIN 0x1 +#define B_SC_RA_RAM_LOCKTRACK_RESET 0x1 +#define B_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 +#define B_SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 +#define B_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 +#define B_SC_RA_RAM_LOCKTRACK_LC 0x5 +#define B_SC_RA_RAM_LOCKTRACK_P_ECHO 0x6 +#define B_SC_RA_RAM_LOCKTRACK_NE_INIT 0x7 +#define B_SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x8 +#define B_SC_RA_RAM_LOCKTRACK_TRACK 0x9 +#define B_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xA +#define B_SC_RA_RAM_LOCKTRACK_MAX 0xB + + + +#define B_SC_RA_RAM_OP_PARAM__A 0x820048 +#define B_SC_RA_RAM_OP_PARAM__W 13 +#define B_SC_RA_RAM_OP_PARAM__M 0x1FFF +#define B_SC_RA_RAM_OP_PARAM_MODE__B 0 +#define B_SC_RA_RAM_OP_PARAM_MODE__W 2 +#define B_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +#define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +#define B_SC_RA_RAM_OP_PARAM_GUARD__B 2 +#define B_SC_RA_RAM_OP_PARAM_GUARD__W 2 +#define B_SC_RA_RAM_OP_PARAM_GUARD__M 0xC +#define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 +#define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 +#define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 +#define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC +#define B_SC_RA_RAM_OP_PARAM_CONST__B 4 +#define B_SC_RA_RAM_OP_PARAM_CONST__W 2 +#define B_SC_RA_RAM_OP_PARAM_CONST__M 0x30 +#define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 +#define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +#define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +#define B_SC_RA_RAM_OP_PARAM_HIER__B 6 +#define B_SC_RA_RAM_OP_PARAM_HIER__W 3 +#define B_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 +#define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 +#define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 +#define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 +#define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 +#define B_SC_RA_RAM_OP_PARAM_RATE__B 9 +#define B_SC_RA_RAM_OP_PARAM_RATE__W 3 +#define B_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 +#define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 +#define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 +#define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 +#define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 +#define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 +#define B_SC_RA_RAM_OP_PARAM_PRIO__B 12 +#define B_SC_RA_RAM_OP_PARAM_PRIO__W 1 +#define B_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 +#define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 +#define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 + +#define B_SC_RA_RAM_OP_AUTO__A 0x820049 +#define B_SC_RA_RAM_OP_AUTO__W 6 +#define B_SC_RA_RAM_OP_AUTO__M 0x3F +#define B_SC_RA_RAM_OP_AUTO__PRE 0x1F +#define B_SC_RA_RAM_OP_AUTO_MODE__B 0 +#define B_SC_RA_RAM_OP_AUTO_MODE__W 1 +#define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1 +#define B_SC_RA_RAM_OP_AUTO_GUARD__B 1 +#define B_SC_RA_RAM_OP_AUTO_GUARD__W 1 +#define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 +#define B_SC_RA_RAM_OP_AUTO_CONST__B 2 +#define B_SC_RA_RAM_OP_AUTO_CONST__W 1 +#define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4 +#define B_SC_RA_RAM_OP_AUTO_HIER__B 3 +#define B_SC_RA_RAM_OP_AUTO_HIER__W 1 +#define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8 +#define B_SC_RA_RAM_OP_AUTO_RATE__B 4 +#define B_SC_RA_RAM_OP_AUTO_RATE__W 1 +#define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10 +#define B_SC_RA_RAM_OP_AUTO_PRIO__B 5 +#define B_SC_RA_RAM_OP_AUTO_PRIO__W 1 +#define B_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 + +#define B_SC_RA_RAM_PILOT_STATUS__A 0x82004A +#define B_SC_RA_RAM_PILOT_STATUS__W 16 +#define B_SC_RA_RAM_PILOT_STATUS__M 0xFFFF +#define B_SC_RA_RAM_PILOT_STATUS_OK 0x0 +#define B_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 +#define B_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 +#define B_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 + +#define B_SC_RA_RAM_LOCK__A 0x82004B +#define B_SC_RA_RAM_LOCK__W 4 +#define B_SC_RA_RAM_LOCK__M 0xF +#define B_SC_RA_RAM_LOCK_DEMOD__B 0 +#define B_SC_RA_RAM_LOCK_DEMOD__W 1 +#define B_SC_RA_RAM_LOCK_DEMOD__M 0x1 +#define B_SC_RA_RAM_LOCK_FEC__B 1 +#define B_SC_RA_RAM_LOCK_FEC__W 1 +#define B_SC_RA_RAM_LOCK_FEC__M 0x2 +#define B_SC_RA_RAM_LOCK_MPEG__B 2 +#define B_SC_RA_RAM_LOCK_MPEG__W 1 +#define B_SC_RA_RAM_LOCK_MPEG__M 0x4 +#define B_SC_RA_RAM_LOCK_NODVBT__B 3 +#define B_SC_RA_RAM_LOCK_NODVBT__W 1 +#define B_SC_RA_RAM_LOCK_NODVBT__M 0x8 + + + +#define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C +#define B_SC_RA_RAM_BE_OPT_ENA__W 5 +#define B_SC_RA_RAM_BE_OPT_ENA__M 0x1F +#define B_SC_RA_RAM_BE_OPT_ENA__PRE 0x1E +#define B_SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 +#define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 +#define B_SC_RA_RAM_BE_OPT_ENA_CSI_OPT 0x2 +#define B_SC_RA_RAM_BE_OPT_ENA_CAL_OPT 0x3 +#define B_SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 +#define B_SC_RA_RAM_BE_OPT_ENA_MAX 0x5 + +#define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D +#define B_SC_RA_RAM_BE_OPT_DELAY__W 16 +#define B_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF +#define B_SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 +#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E +#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 +#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF +#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 +#define B_SC_RA_RAM_ECHO_THRES__A 0x82004F +#define B_SC_RA_RAM_ECHO_THRES__W 16 +#define B_SC_RA_RAM_ECHO_THRES__M 0xFFFF +#define B_SC_RA_RAM_ECHO_THRES__PRE 0x2A +#define B_SC_RA_RAM_CONFIG__A 0x820050 +#define B_SC_RA_RAM_CONFIG__W 16 +#define B_SC_RA_RAM_CONFIG__M 0xFFFF +#define B_SC_RA_RAM_CONFIG__PRE 0x14 +#define B_SC_RA_RAM_CONFIG_ID__B 0 +#define B_SC_RA_RAM_CONFIG_ID__W 1 +#define B_SC_RA_RAM_CONFIG_ID__M 0x1 +#define B_SC_RA_RAM_CONFIG_ID_PRO 0x0 +#define B_SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 +#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 +#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 +#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 +#define B_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 +#define B_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 +#define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 +#define B_SC_RA_RAM_CONFIG_MIXMODE__B 3 +#define B_SC_RA_RAM_CONFIG_MIXMODE__W 1 +#define B_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 +#define B_SC_RA_RAM_CONFIG_FREQSCAN__B 4 +#define B_SC_RA_RAM_CONFIG_FREQSCAN__W 1 +#define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 +#define B_SC_RA_RAM_CONFIG_SLAVE__B 5 +#define B_SC_RA_RAM_CONFIG_SLAVE__W 1 +#define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20 +#define B_SC_RA_RAM_CONFIG_FAR_OFF__B 6 +#define B_SC_RA_RAM_CONFIG_FAR_OFF__W 1 +#define B_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 +#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 +#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 +#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 +#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 +#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 +#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 +#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 +#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 +#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 +#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 +#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 +#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 +#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 +#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 +#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 + +#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x820054 +#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 +#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF +#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 + + + + + +#define B_SC_RA_RAM_FR_2K_MAN_SH__A 0x820055 +#define B_SC_RA_RAM_FR_2K_MAN_SH__W 16 +#define B_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 +#define B_SC_RA_RAM_FR_2K_TAP_SH__A 0x820056 +#define B_SC_RA_RAM_FR_2K_TAP_SH__W 16 +#define B_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 +#define B_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x820057 +#define B_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 +#define B_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF +#define B_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 +#define B_SC_RA_RAM_FR_2K_LEAK_SH__A 0x820058 +#define B_SC_RA_RAM_FR_2K_LEAK_SH__W 16 +#define B_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 + + + +#define B_SC_RA_RAM_FR_8K_MAN_SH__A 0x820059 +#define B_SC_RA_RAM_FR_8K_MAN_SH__W 16 +#define B_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 +#define B_SC_RA_RAM_FR_8K_TAP_SH__A 0x82005A +#define B_SC_RA_RAM_FR_8K_TAP_SH__W 16 +#define B_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x4 +#define B_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x82005B +#define B_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 +#define B_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF +#define B_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 +#define B_SC_RA_RAM_FR_8K_LEAK_SH__A 0x82005C +#define B_SC_RA_RAM_FR_8K_LEAK_SH__W 16 +#define B_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x2 + + + +#define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D +#define B_SC_RA_RAM_CO_TD_CAL_2K__W 16 +#define B_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF +#define B_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB +#define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E +#define B_SC_RA_RAM_CO_TD_CAL_8K__W 16 +#define B_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF +#define B_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 +#define B_SC_RA_RAM_MOTION_OFFSET__A 0x82005F +#define B_SC_RA_RAM_MOTION_OFFSET__W 16 +#define B_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF +#define B_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 +#define B_SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 +#define B_SC_RA_RAM_STATE_PROC_STOP__XSZ 10 +#define B_SC_RA_RAM_STATE_PROC_STOP__W 16 +#define B_SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF +#define B_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE +#define B_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 +#define B_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_10__PRE 0xFFFE +#define B_SC_RA_RAM_STATE_PROC_START__AX 0x820070 +#define B_SC_RA_RAM_STATE_PROC_START__XSZ 10 +#define B_SC_RA_RAM_STATE_PROC_START__W 16 +#define B_SC_RA_RAM_STATE_PROC_START__M 0xFFFF +#define B_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 +#define B_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 +#define B_SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 +#define B_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 +#define B_SC_RA_RAM_STATE_PROC_START_5__PRE 0x100 +#define B_SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_START_7__PRE 0x40 +#define B_SC_RA_RAM_STATE_PROC_START_8__PRE 0x10 +#define B_SC_RA_RAM_STATE_PROC_START_9__PRE 0x30 +#define B_SC_RA_RAM_STATE_PROC_START_10__PRE 0x0 +#define B_SC_RA_RAM_IF_SAVE__AX 0x82008E +#define B_SC_RA_RAM_IF_SAVE__XSZ 2 +#define B_SC_RA_RAM_IF_SAVE__W 16 +#define B_SC_RA_RAM_IF_SAVE__M 0xFFFF +#define B_SC_RA_RAM_FR_THRES__A 0x82007D +#define B_SC_RA_RAM_FR_THRES__W 16 +#define B_SC_RA_RAM_FR_THRES__M 0xFFFF +#define B_SC_RA_RAM_FR_THRES__PRE 0x1A2C +#define B_SC_RA_RAM_STATUS__A 0x82007E +#define B_SC_RA_RAM_STATUS__W 16 +#define B_SC_RA_RAM_STATUS__M 0xFFFF +#define B_SC_RA_RAM_NF_BORDER_INIT__A 0x82007F +#define B_SC_RA_RAM_NF_BORDER_INIT__W 16 +#define B_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF +#define B_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 +#define B_SC_RA_RAM_TIMER__A 0x820080 +#define B_SC_RA_RAM_TIMER__W 16 +#define B_SC_RA_RAM_TIMER__M 0xFFFF +#define B_SC_RA_RAM_FI_OFFSET__A 0x820081 +#define B_SC_RA_RAM_FI_OFFSET__W 16 +#define B_SC_RA_RAM_FI_OFFSET__M 0xFFFF +#define B_SC_RA_RAM_FI_OFFSET__PRE 0x382 +#define B_SC_RA_RAM_ECHO_GUARD__A 0x820082 +#define B_SC_RA_RAM_ECHO_GUARD__W 16 +#define B_SC_RA_RAM_ECHO_GUARD__M 0xFFFF +#define B_SC_RA_RAM_ECHO_GUARD__PRE 0x18 +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__A 0x8200BA +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__W 16 +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__M 0xFFFF +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__PRE 0x3 +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__A 0x8200BB +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__W 16 +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__M 0xFFFF +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__PRE 0x0 + + + + + +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 + + + +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC + + + +#define B_SC_RA_RAM_IR_FREQ__A 0x8200D0 +#define B_SC_RA_RAM_IR_FREQ__W 16 +#define B_SC_RA_RAM_IR_FREQ__M 0xFFFF +#define B_SC_RA_RAM_IR_FREQ__PRE 0x0 + + + + + +#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 +#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 +#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 +#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 +#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 +#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 +#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 +#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 +#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 + + + +#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 +#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 +#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 +#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 +#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 +#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 +#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 +#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 +#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 + + + + + +#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 +#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 +#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 +#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 +#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 +#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 +#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 +#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 +#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 + + + +#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA +#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 +#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB +#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB +#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 +#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 +#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC +#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 +#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 + + + +#define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD +#define B_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 +#define B_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF +#define B_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 +#define B_SC_RA_RAM_ECHO_SHT_LIM__A 0x8200DE +#define B_SC_RA_RAM_ECHO_SHT_LIM__W 16 +#define B_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF +#define B_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x8200DF +#define B_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF +#define B_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0xCC0 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 + + + + + +#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 +#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 +#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 +#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 +#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 +#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 +#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 +#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 +#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 + + + +#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 +#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 +#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE +#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 +#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 +#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 +#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 +#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 +#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 + + + +#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 +#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 +#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF +#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 +#define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 +#define B_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 +#define B_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF +#define B_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C + + + +#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA +#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 +#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF +#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 +#define B_SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB +#define B_SC_RA_RAM_TPS_TIMEOUT__W 16 +#define B_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF +#define B_SC_RA_RAM_BAND__A 0x8200EC +#define B_SC_RA_RAM_BAND__W 16 +#define B_SC_RA_RAM_BAND__M 0xFFFF +#define B_SC_RA_RAM_BAND__PRE 0x0 +#define B_SC_RA_RAM_BAND_INTERVAL__B 0 +#define B_SC_RA_RAM_BAND_INTERVAL__W 4 +#define B_SC_RA_RAM_BAND_INTERVAL__M 0xF +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 + +#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED +#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 +#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF +#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 +#define B_SC_RA_RAM_REG__AX 0x8200F0 +#define B_SC_RA_RAM_REG__XSZ 2 +#define B_SC_RA_RAM_REG__W 16 +#define B_SC_RA_RAM_REG__M 0xFFFF +#define B_SC_RA_RAM_BREAK__A 0x8200F2 +#define B_SC_RA_RAM_BREAK__W 16 +#define B_SC_RA_RAM_BREAK__M 0xFFFF +#define B_SC_RA_RAM_BOOTCOUNT__A 0x8200F3 +#define B_SC_RA_RAM_BOOTCOUNT__W 16 +#define B_SC_RA_RAM_BOOTCOUNT__M 0xFFFF + + + +#define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 +#define B_SC_RA_RAM_LC_ABS_2K__W 16 +#define B_SC_RA_RAM_LC_ABS_2K__M 0xFFFF +#define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F +#define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5 +#define B_SC_RA_RAM_LC_ABS_8K__W 16 +#define B_SC_RA_RAM_LC_ABS_8K__M 0xFFFF +#define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F +#define B_SC_RA_RAM_NE_ERR_SELECT__A 0x8200F6 +#define B_SC_RA_RAM_NE_ERR_SELECT__W 16 +#define B_SC_RA_RAM_NE_ERR_SELECT__M 0xFFFF +#define B_SC_RA_RAM_NE_ERR_SELECT__PRE 0x19 +#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x8200F7 +#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 +#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF +#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 +#define B_SC_RA_RAM_RELOCK__A 0x8200FE +#define B_SC_RA_RAM_RELOCK__W 16 +#define B_SC_RA_RAM_RELOCK__M 0xFFFF +#define B_SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF +#define B_SC_RA_RAM_STACKUNDERFLOW__W 16 +#define B_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF + + + +#define B_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 +#define B_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 +#define B_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF +#define B_SC_RA_RAM_NF_PREPOST__A 0x820149 +#define B_SC_RA_RAM_NF_PREPOST__W 16 +#define B_SC_RA_RAM_NF_PREPOST__M 0xFFFF +#define B_SC_RA_RAM_NF_PREBORDER__A 0x82014A +#define B_SC_RA_RAM_NF_PREBORDER__W 16 +#define B_SC_RA_RAM_NF_PREBORDER__M 0xFFFF +#define B_SC_RA_RAM_NF_START__A 0x82014B +#define B_SC_RA_RAM_NF_START__W 16 +#define B_SC_RA_RAM_NF_START__M 0xFFFF +#define B_SC_RA_RAM_NF_MINISI__AX 0x82014C +#define B_SC_RA_RAM_NF_MINISI__XSZ 2 +#define B_SC_RA_RAM_NF_MINISI__W 16 +#define B_SC_RA_RAM_NF_MINISI__M 0xFFFF +#define B_SC_RA_RAM_NF_MAXECHO__A 0x82014E +#define B_SC_RA_RAM_NF_MAXECHO__W 16 +#define B_SC_RA_RAM_NF_MAXECHO__M 0xFFFF +#define B_SC_RA_RAM_NF_NRECHOES__A 0x82014F +#define B_SC_RA_RAM_NF_NRECHOES__W 16 +#define B_SC_RA_RAM_NF_NRECHOES__M 0xFFFF +#define B_SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 +#define B_SC_RA_RAM_NF_ECHOTABLE__XSZ 16 +#define B_SC_RA_RAM_NF_ECHOTABLE__W 16 +#define B_SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF + + + + + +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 + + + +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 + + + +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 + + + +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 + + + +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 + + + +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 + + + +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 + + + +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 +#define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE +#define B_SC_RA_RAM_DRIVER_VERSION__XSZ 2 +#define B_SC_RA_RAM_DRIVER_VERSION__W 16 +#define B_SC_RA_RAM_DRIVER_VERSION__M 0xFFFF +#define B_SC_RA_RAM_EVENT0_MIN 0x7 +#define B_SC_RA_RAM_EVENT0_FE_CU 0x7 +#define B_SC_RA_RAM_EVENT0_CE 0xA +#define B_SC_RA_RAM_EVENT0_EQ 0xE +#define B_SC_RA_RAM_EVENT0_MAX 0xF +#define B_SC_RA_RAM_PROC_LOCKTRACK 0x0 +#define B_SC_RA_RAM_PROC_MODE_GUARD 0x1 +#define B_SC_RA_RAM_PROC_PILOTS 0x2 +#define B_SC_RA_RAM_PROC_FESTART_ADJUST 0x3 +#define B_SC_RA_RAM_PROC_ECHO 0x4 +#define B_SC_RA_RAM_PROC_BE_OPT 0x5 +#define B_SC_RA_RAM_PROC_LOCK_MON 0x6 +#define B_SC_RA_RAM_PROC_EQ 0x7 +#define B_SC_RA_RAM_PROC_ECHO_DIVERSITY 0x8 +#define B_SC_RA_RAM_PROC_MAX 0x9 + + + + + + +#define B_SC_IF_RAM_TRP_RST__AX 0x830000 +#define B_SC_IF_RAM_TRP_RST__XSZ 2 +#define B_SC_IF_RAM_TRP_RST__W 12 +#define B_SC_IF_RAM_TRP_RST__M 0xFFF + +#define B_SC_IF_RAM_TRP_BPT0__AX 0x830002 +#define B_SC_IF_RAM_TRP_BPT0__XSZ 2 +#define B_SC_IF_RAM_TRP_BPT0__W 12 +#define B_SC_IF_RAM_TRP_BPT0__M 0xFFF + +#define B_SC_IF_RAM_TRP_STKU__AX 0x830004 +#define B_SC_IF_RAM_TRP_STKU__XSZ 2 +#define B_SC_IF_RAM_TRP_STKU__W 12 +#define B_SC_IF_RAM_TRP_STKU__M 0xFFF + + + + +#define B_SC_IF_RAM_VERSION_MA_MI__A 0x830FFE +#define B_SC_IF_RAM_VERSION_MA_MI__W 12 +#define B_SC_IF_RAM_VERSION_MA_MI__M 0xFFF + +#define B_SC_IF_RAM_VERSION_PATCH__A 0x830FFF +#define B_SC_IF_RAM_VERSION_PATCH__W 12 +#define B_SC_IF_RAM_VERSION_PATCH__M 0xFFF + + + + + + + + + +#define B_FE_COMM_EXEC__A 0xC00000 +#define B_FE_COMM_EXEC__W 3 +#define B_FE_COMM_EXEC__M 0x7 +#define B_FE_COMM_EXEC_CTL__B 0 +#define B_FE_COMM_EXEC_CTL__W 3 +#define B_FE_COMM_EXEC_CTL__M 0x7 +#define B_FE_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_COMM_EXEC_CTL_STEP 0x3 +#define B_FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_FE_COMM_STATE__A 0xC00001 +#define B_FE_COMM_STATE__W 16 +#define B_FE_COMM_STATE__M 0xFFFF +#define B_FE_COMM_MB__A 0xC00002 +#define B_FE_COMM_MB__W 16 +#define B_FE_COMM_MB__M 0xFFFF +#define B_FE_COMM_SERVICE0__A 0xC00003 +#define B_FE_COMM_SERVICE0__W 16 +#define B_FE_COMM_SERVICE0__M 0xFFFF +#define B_FE_COMM_SERVICE1__A 0xC00004 +#define B_FE_COMM_SERVICE1__W 16 +#define B_FE_COMM_SERVICE1__M 0xFFFF +#define B_FE_COMM_INT_STA__A 0xC00007 +#define B_FE_COMM_INT_STA__W 16 +#define B_FE_COMM_INT_STA__M 0xFFFF +#define B_FE_COMM_INT_MSK__A 0xC00008 +#define B_FE_COMM_INT_MSK__W 16 +#define B_FE_COMM_INT_MSK__M 0xFFFF + + + + + +#define B_FE_AD_SID 0x1 + + + + + + +#define B_FE_AD_REG_COMM_EXEC__A 0xC10000 +#define B_FE_AD_REG_COMM_EXEC__W 3 +#define B_FE_AD_REG_COMM_EXEC__M 0x7 +#define B_FE_AD_REG_COMM_EXEC_CTL__B 0 +#define B_FE_AD_REG_COMM_EXEC_CTL__W 3 +#define B_FE_AD_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define B_FE_AD_REG_COMM_MB__A 0xC10002 +#define B_FE_AD_REG_COMM_MB__W 2 +#define B_FE_AD_REG_COMM_MB__M 0x3 +#define B_FE_AD_REG_COMM_MB_CTR__B 0 +#define B_FE_AD_REG_COMM_MB_CTR__W 1 +#define B_FE_AD_REG_COMM_MB_CTR__M 0x1 +#define B_FE_AD_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_AD_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_AD_REG_COMM_MB_OBS__B 1 +#define B_FE_AD_REG_COMM_MB_OBS__W 1 +#define B_FE_AD_REG_COMM_MB_OBS__M 0x2 +#define B_FE_AD_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_AD_REG_COMM_MB_OBS_ON 0x2 + +#define B_FE_AD_REG_COMM_SERVICE0__A 0xC10003 +#define B_FE_AD_REG_COMM_SERVICE0__W 10 +#define B_FE_AD_REG_COMM_SERVICE0__M 0x3FF +#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 +#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 +#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 + +#define B_FE_AD_REG_COMM_SERVICE1__A 0xC10004 +#define B_FE_AD_REG_COMM_SERVICE1__W 11 +#define B_FE_AD_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_AD_REG_COMM_INT_STA__A 0xC10007 +#define B_FE_AD_REG_COMM_INT_STA__W 2 +#define B_FE_AD_REG_COMM_INT_STA__M 0x3 +#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 +#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 +#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 + + +#define B_FE_AD_REG_COMM_INT_MSK__A 0xC10008 +#define B_FE_AD_REG_COMM_INT_MSK__W 2 +#define B_FE_AD_REG_COMM_INT_MSK__M 0x3 +#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 +#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 +#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 + + +#define B_FE_AD_REG_CUR_SEL__A 0xC10010 +#define B_FE_AD_REG_CUR_SEL__W 2 +#define B_FE_AD_REG_CUR_SEL__M 0x3 +#define B_FE_AD_REG_CUR_SEL_INIT 0x2 + + +#define B_FE_AD_REG_OVERFLOW__A 0xC10011 +#define B_FE_AD_REG_OVERFLOW__W 1 +#define B_FE_AD_REG_OVERFLOW__M 0x1 +#define B_FE_AD_REG_OVERFLOW_INIT 0x0 + + +#define B_FE_AD_REG_FDB_IN__A 0xC10012 +#define B_FE_AD_REG_FDB_IN__W 1 +#define B_FE_AD_REG_FDB_IN__M 0x1 +#define B_FE_AD_REG_FDB_IN_INIT 0x0 + + +#define B_FE_AD_REG_PD__A 0xC10013 +#define B_FE_AD_REG_PD__W 1 +#define B_FE_AD_REG_PD__M 0x1 +#define B_FE_AD_REG_PD_INIT 0x1 + + +#define B_FE_AD_REG_INVEXT__A 0xC10014 +#define B_FE_AD_REG_INVEXT__W 1 +#define B_FE_AD_REG_INVEXT__M 0x1 +#define B_FE_AD_REG_INVEXT_INIT 0x0 + + +#define B_FE_AD_REG_CLKNEG__A 0xC10015 +#define B_FE_AD_REG_CLKNEG__W 1 +#define B_FE_AD_REG_CLKNEG__M 0x1 +#define B_FE_AD_REG_CLKNEG_INIT 0x0 + + +#define B_FE_AD_REG_MON_IN_MUX__A 0xC10016 +#define B_FE_AD_REG_MON_IN_MUX__W 2 +#define B_FE_AD_REG_MON_IN_MUX__M 0x3 +#define B_FE_AD_REG_MON_IN_MUX_INIT 0x0 + + +#define B_FE_AD_REG_MON_IN5__A 0xC10017 +#define B_FE_AD_REG_MON_IN5__W 10 +#define B_FE_AD_REG_MON_IN5__M 0x3FF +#define B_FE_AD_REG_MON_IN5_INIT 0x0 + + +#define B_FE_AD_REG_MON_IN4__A 0xC10018 +#define B_FE_AD_REG_MON_IN4__W 10 +#define B_FE_AD_REG_MON_IN4__M 0x3FF +#define B_FE_AD_REG_MON_IN4_INIT 0x0 + + +#define B_FE_AD_REG_MON_IN3__A 0xC10019 +#define B_FE_AD_REG_MON_IN3__W 10 +#define B_FE_AD_REG_MON_IN3__M 0x3FF +#define B_FE_AD_REG_MON_IN3_INIT 0x0 + + +#define B_FE_AD_REG_MON_IN2__A 0xC1001A +#define B_FE_AD_REG_MON_IN2__W 10 +#define B_FE_AD_REG_MON_IN2__M 0x3FF +#define B_FE_AD_REG_MON_IN2_INIT 0x0 + + +#define B_FE_AD_REG_MON_IN1__A 0xC1001B +#define B_FE_AD_REG_MON_IN1__W 10 +#define B_FE_AD_REG_MON_IN1__M 0x3FF +#define B_FE_AD_REG_MON_IN1_INIT 0x0 + + +#define B_FE_AD_REG_MON_IN0__A 0xC1001C +#define B_FE_AD_REG_MON_IN0__W 10 +#define B_FE_AD_REG_MON_IN0__M 0x3FF +#define B_FE_AD_REG_MON_IN0_INIT 0x0 + + +#define B_FE_AD_REG_MON_IN_VAL__A 0xC1001D +#define B_FE_AD_REG_MON_IN_VAL__W 1 +#define B_FE_AD_REG_MON_IN_VAL__M 0x1 +#define B_FE_AD_REG_MON_IN_VAL_INIT 0x0 + + +#define B_FE_AD_REG_CTR_CLK_O__A 0xC1001E +#define B_FE_AD_REG_CTR_CLK_O__W 1 +#define B_FE_AD_REG_CTR_CLK_O__M 0x1 +#define B_FE_AD_REG_CTR_CLK_O_INIT 0x0 + + +#define B_FE_AD_REG_CTR_CLK_E_O__A 0xC1001F +#define B_FE_AD_REG_CTR_CLK_E_O__W 1 +#define B_FE_AD_REG_CTR_CLK_E_O__M 0x1 +#define B_FE_AD_REG_CTR_CLK_E_O_INIT 0x1 + + +#define B_FE_AD_REG_CTR_VAL_O__A 0xC10020 +#define B_FE_AD_REG_CTR_VAL_O__W 1 +#define B_FE_AD_REG_CTR_VAL_O__M 0x1 +#define B_FE_AD_REG_CTR_VAL_O_INIT 0x0 + + +#define B_FE_AD_REG_CTR_VAL_E_O__A 0xC10021 +#define B_FE_AD_REG_CTR_VAL_E_O__W 1 +#define B_FE_AD_REG_CTR_VAL_E_O__M 0x1 +#define B_FE_AD_REG_CTR_VAL_E_O_INIT 0x1 + + +#define B_FE_AD_REG_CTR_DATA_O__A 0xC10022 +#define B_FE_AD_REG_CTR_DATA_O__W 10 +#define B_FE_AD_REG_CTR_DATA_O__M 0x3FF +#define B_FE_AD_REG_CTR_DATA_O_INIT 0x0 + + +#define B_FE_AD_REG_CTR_DATA_E_O__A 0xC10023 +#define B_FE_AD_REG_CTR_DATA_E_O__W 10 +#define B_FE_AD_REG_CTR_DATA_E_O__M 0x3FF +#define B_FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF + + + + + +#define B_FE_AG_SID 0x2 + + + + + + +#define B_FE_AG_REG_COMM_EXEC__A 0xC20000 +#define B_FE_AG_REG_COMM_EXEC__W 3 +#define B_FE_AG_REG_COMM_EXEC__M 0x7 +#define B_FE_AG_REG_COMM_EXEC_CTL__B 0 +#define B_FE_AG_REG_COMM_EXEC_CTL__W 3 +#define B_FE_AG_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_FE_AG_REG_COMM_STATE__A 0xC20001 +#define B_FE_AG_REG_COMM_STATE__W 4 +#define B_FE_AG_REG_COMM_STATE__M 0xF + +#define B_FE_AG_REG_COMM_MB__A 0xC20002 +#define B_FE_AG_REG_COMM_MB__W 4 +#define B_FE_AG_REG_COMM_MB__M 0xF +#define B_FE_AG_REG_COMM_MB_OBS__B 1 +#define B_FE_AG_REG_COMM_MB_OBS__W 1 +#define B_FE_AG_REG_COMM_MB_OBS__M 0x2 +#define B_FE_AG_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_AG_REG_COMM_MB_OBS_ON 0x2 +#define B_FE_AG_REG_COMM_MB_MUX__B 2 +#define B_FE_AG_REG_COMM_MB_MUX__W 2 +#define B_FE_AG_REG_COMM_MB_MUX__M 0xC +#define B_FE_AG_REG_COMM_MB_MUX_DAT 0x0 +#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD2 0x4 +#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD1 0x8 +#define B_FE_AG_REG_COMM_MB_MUX_DAT_IND_PD1 0xC + + +#define B_FE_AG_REG_COMM_SERVICE0__A 0xC20003 +#define B_FE_AG_REG_COMM_SERVICE0__W 10 +#define B_FE_AG_REG_COMM_SERVICE0__M 0x3FF + +#define B_FE_AG_REG_COMM_SERVICE1__A 0xC20004 +#define B_FE_AG_REG_COMM_SERVICE1__W 11 +#define B_FE_AG_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_AG_REG_COMM_INT_STA__A 0xC20007 +#define B_FE_AG_REG_COMM_INT_STA__W 8 +#define B_FE_AG_REG_COMM_INT_STA__M 0xFF +#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 +#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 +#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 +#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 +#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 +#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 +#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 +#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 +#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 +#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 +#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 +#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 +#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 +#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 + + +#define B_FE_AG_REG_COMM_INT_MSK__A 0xC20008 +#define B_FE_AG_REG_COMM_INT_MSK__W 8 +#define B_FE_AG_REG_COMM_INT_MSK__M 0xFF +#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 +#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 +#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 +#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 +#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 +#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 +#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 +#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 +#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 +#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 +#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 +#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 +#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 +#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 + + +#define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 +#define B_FE_AG_REG_AG_MODE_LOP__W 15 +#define B_FE_AG_REG_AG_MODE_LOP__M 0x7FFF +#define B_FE_AG_REG_AG_MODE_LOP_INIT 0x81E + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 + + +#define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 +#define B_FE_AG_REG_AG_MODE_HIP__W 5 +#define B_FE_AG_REG_AG_MODE_HIP__M 0x1F +#define B_FE_AG_REG_AG_MODE_HIP_INIT 0x0 + +#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 + +#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 + +#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__B 2 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__W 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__M 0x4 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH1 0x0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH2 0x4 + +#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__B 3 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__W 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8 + +#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__B 4 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__W 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__M 0x10 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH1 0x0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH2 0x10 + + +#define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 +#define B_FE_AG_REG_AG_PGA_MODE__W 3 +#define B_FE_AG_REG_AG_PGA_MODE__M 0x7 +#define B_FE_AG_REG_AG_PGA_MODE_INIT 0x3 +#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 +#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 + + +#define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 +#define B_FE_AG_REG_AG_AGC_SIO__W 2 +#define B_FE_AG_REG_AG_AGC_SIO__M 0x3 +#define B_FE_AG_REG_AG_AGC_SIO_INIT 0x3 + +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 + +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 + + +#define B_FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 +#define B_FE_AG_REG_AG_AGC_USR_DAT__W 2 +#define B_FE_AG_REG_AG_AGC_USR_DAT__M 0x3 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 + + +#define B_FE_AG_REG_AG_PWD__A 0xC20015 +#define B_FE_AG_REG_AG_PWD__W 5 +#define B_FE_AG_REG_AG_PWD__M 0x1F +#define B_FE_AG_REG_AG_PWD_INIT 0x6 + +#define B_FE_AG_REG_AG_PWD_PWD_PD1__B 0 +#define B_FE_AG_REG_AG_PWD_PWD_PD1__W 1 +#define B_FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 +#define B_FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 +#define B_FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 + +#define B_FE_AG_REG_AG_PWD_PWD_PD2__B 1 +#define B_FE_AG_REG_AG_PWD_PWD_PD2__W 1 +#define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 +#define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 +#define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 + +#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 + +#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 + +#define B_FE_AG_REG_AG_PWD_PWD_AAF__B 4 +#define B_FE_AG_REG_AG_PWD_PWD_AAF__W 1 +#define B_FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 +#define B_FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 +#define B_FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 + + +#define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 +#define B_FE_AG_REG_DCE_AUR_CNT__W 5 +#define B_FE_AG_REG_DCE_AUR_CNT__M 0x1F +#define B_FE_AG_REG_DCE_AUR_CNT_INIT 0x10 + + +#define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 +#define B_FE_AG_REG_DCE_RUR_CNT__W 5 +#define B_FE_AG_REG_DCE_RUR_CNT__M 0x1F +#define B_FE_AG_REG_DCE_RUR_CNT_INIT 0x0 + + +#define B_FE_AG_REG_DCE_AVE_DAT__A 0xC20018 +#define B_FE_AG_REG_DCE_AVE_DAT__W 10 +#define B_FE_AG_REG_DCE_AVE_DAT__M 0x3FF + +#define B_FE_AG_REG_DEC_AVE_WRI__A 0xC20019 +#define B_FE_AG_REG_DEC_AVE_WRI__W 10 +#define B_FE_AG_REG_DEC_AVE_WRI__M 0x3FF +#define B_FE_AG_REG_DEC_AVE_WRI_INIT 0x0 + + +#define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A +#define B_FE_AG_REG_ACE_AUR_CNT__W 5 +#define B_FE_AG_REG_ACE_AUR_CNT__M 0x1F +#define B_FE_AG_REG_ACE_AUR_CNT_INIT 0xE + + +#define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B +#define B_FE_AG_REG_ACE_RUR_CNT__W 5 +#define B_FE_AG_REG_ACE_RUR_CNT__M 0x1F +#define B_FE_AG_REG_ACE_RUR_CNT_INIT 0x0 + + +#define B_FE_AG_REG_ACE_AVE_DAT__A 0xC2001C +#define B_FE_AG_REG_ACE_AVE_DAT__W 10 +#define B_FE_AG_REG_ACE_AVE_DAT__M 0x3FF + +#define B_FE_AG_REG_AEC_AVE_INC__A 0xC2001D +#define B_FE_AG_REG_AEC_AVE_INC__W 10 +#define B_FE_AG_REG_AEC_AVE_INC__M 0x3FF +#define B_FE_AG_REG_AEC_AVE_INC_INIT 0x0 + + +#define B_FE_AG_REG_AEC_AVE_DAT__A 0xC2001E +#define B_FE_AG_REG_AEC_AVE_DAT__W 10 +#define B_FE_AG_REG_AEC_AVE_DAT__M 0x3FF + +#define B_FE_AG_REG_AEC_CLP_LVL__A 0xC2001F +#define B_FE_AG_REG_AEC_CLP_LVL__W 16 +#define B_FE_AG_REG_AEC_CLP_LVL__M 0xFFFF +#define B_FE_AG_REG_AEC_CLP_LVL_INIT 0x0 + + +#define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 +#define B_FE_AG_REG_CDR_RUR_CNT__W 5 +#define B_FE_AG_REG_CDR_RUR_CNT__M 0x1F +#define B_FE_AG_REG_CDR_RUR_CNT_INIT 0x10 + + +#define B_FE_AG_REG_CDR_CLP_DAT__A 0xC20021 +#define B_FE_AG_REG_CDR_CLP_DAT__W 16 +#define B_FE_AG_REG_CDR_CLP_DAT__M 0xFFFF + +#define B_FE_AG_REG_CDR_CLP_POS__A 0xC20022 +#define B_FE_AG_REG_CDR_CLP_POS__W 10 +#define B_FE_AG_REG_CDR_CLP_POS__M 0x3FF +#define B_FE_AG_REG_CDR_CLP_POS_INIT 0x16A + + +#define B_FE_AG_REG_CDR_CLP_NEG__A 0xC20023 +#define B_FE_AG_REG_CDR_CLP_NEG__W 10 +#define B_FE_AG_REG_CDR_CLP_NEG__M 0x3FF +#define B_FE_AG_REG_CDR_CLP_NEG_INIT 0x296 + + +#define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 +#define B_FE_AG_REG_EGC_RUR_CNT__W 5 +#define B_FE_AG_REG_EGC_RUR_CNT__M 0x1F +#define B_FE_AG_REG_EGC_RUR_CNT_INIT 0x0 + + +#define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 +#define B_FE_AG_REG_EGC_SET_LVL__W 9 +#define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF +#define B_FE_AG_REG_EGC_SET_LVL_INIT 0x46 + + +#define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 +#define B_FE_AG_REG_EGC_FLA_RGN__W 9 +#define B_FE_AG_REG_EGC_FLA_RGN__M 0x1FF +#define B_FE_AG_REG_EGC_FLA_RGN_INIT 0x4 + + +#define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 +#define B_FE_AG_REG_EGC_SLO_RGN__W 9 +#define B_FE_AG_REG_EGC_SLO_RGN__M 0x1FF +#define B_FE_AG_REG_EGC_SLO_RGN_INIT 0x1F + + +#define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 +#define B_FE_AG_REG_EGC_JMP_PSN__W 4 +#define B_FE_AG_REG_EGC_JMP_PSN__M 0xF +#define B_FE_AG_REG_EGC_JMP_PSN_INIT 0x0 + + +#define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 +#define B_FE_AG_REG_EGC_FLA_INC__W 16 +#define B_FE_AG_REG_EGC_FLA_INC__M 0xFFFF +#define B_FE_AG_REG_EGC_FLA_INC_INIT 0x0 + + +#define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A +#define B_FE_AG_REG_EGC_FLA_DEC__W 16 +#define B_FE_AG_REG_EGC_FLA_DEC__M 0xFFFF +#define B_FE_AG_REG_EGC_FLA_DEC_INIT 0x0 + + +#define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B +#define B_FE_AG_REG_EGC_SLO_INC__W 16 +#define B_FE_AG_REG_EGC_SLO_INC__M 0xFFFF +#define B_FE_AG_REG_EGC_SLO_INC_INIT 0x3 + + +#define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C +#define B_FE_AG_REG_EGC_SLO_DEC__W 16 +#define B_FE_AG_REG_EGC_SLO_DEC__M 0xFFFF +#define B_FE_AG_REG_EGC_SLO_DEC_INIT 0x3 + + +#define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D +#define B_FE_AG_REG_EGC_FAS_INC__W 16 +#define B_FE_AG_REG_EGC_FAS_INC__M 0xFFFF +#define B_FE_AG_REG_EGC_FAS_INC_INIT 0xE + + +#define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E +#define B_FE_AG_REG_EGC_FAS_DEC__W 16 +#define B_FE_AG_REG_EGC_FAS_DEC__M 0xFFFF +#define B_FE_AG_REG_EGC_FAS_DEC_INIT 0xE + + +#define B_FE_AG_REG_EGC_MAP_DAT__A 0xC2002F +#define B_FE_AG_REG_EGC_MAP_DAT__W 16 +#define B_FE_AG_REG_EGC_MAP_DAT__M 0xFFFF + +#define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030 +#define B_FE_AG_REG_PM1_AGC_WRI__W 11 +#define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF +#define B_FE_AG_REG_PM1_AGC_WRI_INIT 0x0 + + +#define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 +#define B_FE_AG_REG_GC1_AGC_RIC__W 16 +#define B_FE_AG_REG_GC1_AGC_RIC__M 0xFFFF +#define B_FE_AG_REG_GC1_AGC_RIC_INIT 0x64 + + +#define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 +#define B_FE_AG_REG_GC1_AGC_OFF__W 16 +#define B_FE_AG_REG_GC1_AGC_OFF__M 0xFFFF +#define B_FE_AG_REG_GC1_AGC_OFF_INIT 0xFEC8 + + +#define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 +#define B_FE_AG_REG_GC1_AGC_MAX__W 10 +#define B_FE_AG_REG_GC1_AGC_MAX__M 0x3FF +#define B_FE_AG_REG_GC1_AGC_MAX_INIT 0x1FF + + +#define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 +#define B_FE_AG_REG_GC1_AGC_MIN__W 10 +#define B_FE_AG_REG_GC1_AGC_MIN__M 0x3FF +#define B_FE_AG_REG_GC1_AGC_MIN_INIT 0x200 + + +#define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 +#define B_FE_AG_REG_GC1_AGC_DAT__W 10 +#define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF + +#define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036 +#define B_FE_AG_REG_PM2_AGC_WRI__W 11 +#define B_FE_AG_REG_PM2_AGC_WRI__M 0x7FF +#define B_FE_AG_REG_PM2_AGC_WRI_INIT 0x0 + + +#define B_FE_AG_REG_GC2_AGC_RIC__A 0xC20037 +#define B_FE_AG_REG_GC2_AGC_RIC__W 16 +#define B_FE_AG_REG_GC2_AGC_RIC__M 0xFFFF +#define B_FE_AG_REG_GC2_AGC_RIC_INIT 0x64 + + +#define B_FE_AG_REG_GC2_AGC_OFF__A 0xC20038 +#define B_FE_AG_REG_GC2_AGC_OFF__W 16 +#define B_FE_AG_REG_GC2_AGC_OFF__M 0xFFFF +#define B_FE_AG_REG_GC2_AGC_OFF_INIT 0xFEC8 + + +#define B_FE_AG_REG_GC2_AGC_MAX__A 0xC20039 +#define B_FE_AG_REG_GC2_AGC_MAX__W 10 +#define B_FE_AG_REG_GC2_AGC_MAX__M 0x3FF +#define B_FE_AG_REG_GC2_AGC_MAX_INIT 0x1FF + + +#define B_FE_AG_REG_GC2_AGC_MIN__A 0xC2003A +#define B_FE_AG_REG_GC2_AGC_MIN__W 10 +#define B_FE_AG_REG_GC2_AGC_MIN__M 0x3FF +#define B_FE_AG_REG_GC2_AGC_MIN_INIT 0x200 + + +#define B_FE_AG_REG_GC2_AGC_DAT__A 0xC2003B +#define B_FE_AG_REG_GC2_AGC_DAT__W 10 +#define B_FE_AG_REG_GC2_AGC_DAT__M 0x3FF + +#define B_FE_AG_REG_IND_WIN__A 0xC2003C +#define B_FE_AG_REG_IND_WIN__W 5 +#define B_FE_AG_REG_IND_WIN__M 0x1F +#define B_FE_AG_REG_IND_WIN_INIT 0x0 + + +#define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D +#define B_FE_AG_REG_IND_THD_LOL__W 6 +#define B_FE_AG_REG_IND_THD_LOL__M 0x3F +#define B_FE_AG_REG_IND_THD_LOL_INIT 0x5 + + +#define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E +#define B_FE_AG_REG_IND_THD_HIL__W 6 +#define B_FE_AG_REG_IND_THD_HIL__M 0x3F +#define B_FE_AG_REG_IND_THD_HIL_INIT 0xF + + +#define B_FE_AG_REG_IND_DEL__A 0xC2003F +#define B_FE_AG_REG_IND_DEL__W 7 +#define B_FE_AG_REG_IND_DEL__M 0x7F +#define B_FE_AG_REG_IND_DEL_INIT 0x32 + + +#define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 +#define B_FE_AG_REG_IND_PD1_WRI__W 6 +#define B_FE_AG_REG_IND_PD1_WRI__M 0x3F +#define B_FE_AG_REG_IND_PD1_WRI_INIT 0x1E + + +#define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 +#define B_FE_AG_REG_PDA_AUR_CNT__W 5 +#define B_FE_AG_REG_PDA_AUR_CNT__M 0x1F +#define B_FE_AG_REG_PDA_AUR_CNT_INIT 0x10 + + +#define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 +#define B_FE_AG_REG_PDA_RUR_CNT__W 5 +#define B_FE_AG_REG_PDA_RUR_CNT__M 0x1F +#define B_FE_AG_REG_PDA_RUR_CNT_INIT 0x0 + + +#define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 +#define B_FE_AG_REG_PDA_AVE_DAT__W 6 +#define B_FE_AG_REG_PDA_AVE_DAT__M 0x3F + +#define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044 +#define B_FE_AG_REG_PDC_RUR_CNT__W 5 +#define B_FE_AG_REG_PDC_RUR_CNT__M 0x1F +#define B_FE_AG_REG_PDC_RUR_CNT_INIT 0x0 + + +#define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 +#define B_FE_AG_REG_PDC_SET_LVL__W 6 +#define B_FE_AG_REG_PDC_SET_LVL__M 0x3F +#define B_FE_AG_REG_PDC_SET_LVL_INIT 0x10 + + +#define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 +#define B_FE_AG_REG_PDC_FLA_RGN__W 6 +#define B_FE_AG_REG_PDC_FLA_RGN__M 0x3F +#define B_FE_AG_REG_PDC_FLA_RGN_INIT 0x0 + + +#define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 +#define B_FE_AG_REG_PDC_JMP_PSN__W 3 +#define B_FE_AG_REG_PDC_JMP_PSN__M 0x7 +#define B_FE_AG_REG_PDC_JMP_PSN_INIT 0x0 + + +#define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 +#define B_FE_AG_REG_PDC_FLA_STP__W 16 +#define B_FE_AG_REG_PDC_FLA_STP__M 0xFFFF +#define B_FE_AG_REG_PDC_FLA_STP_INIT 0x0 + + +#define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 +#define B_FE_AG_REG_PDC_SLO_STP__W 16 +#define B_FE_AG_REG_PDC_SLO_STP__M 0xFFFF +#define B_FE_AG_REG_PDC_SLO_STP_INIT 0x1 + + +#define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A +#define B_FE_AG_REG_PDC_PD2_WRI__W 6 +#define B_FE_AG_REG_PDC_PD2_WRI__M 0x3F +#define B_FE_AG_REG_PDC_PD2_WRI_INIT 0x1F + + +#define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B +#define B_FE_AG_REG_PDC_MAP_DAT__W 6 +#define B_FE_AG_REG_PDC_MAP_DAT__M 0x3F + +#define B_FE_AG_REG_PDC_MAX__A 0xC2004C +#define B_FE_AG_REG_PDC_MAX__W 6 +#define B_FE_AG_REG_PDC_MAX__M 0x3F +#define B_FE_AG_REG_PDC_MAX_INIT 0x2 + + +#define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D +#define B_FE_AG_REG_TGA_AUR_CNT__W 5 +#define B_FE_AG_REG_TGA_AUR_CNT__M 0x1F +#define B_FE_AG_REG_TGA_AUR_CNT_INIT 0x10 + + +#define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E +#define B_FE_AG_REG_TGA_RUR_CNT__W 5 +#define B_FE_AG_REG_TGA_RUR_CNT__M 0x1F +#define B_FE_AG_REG_TGA_RUR_CNT_INIT 0x0 + + +#define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F +#define B_FE_AG_REG_TGA_AVE_DAT__W 6 +#define B_FE_AG_REG_TGA_AVE_DAT__M 0x3F + +#define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050 +#define B_FE_AG_REG_TGC_RUR_CNT__W 5 +#define B_FE_AG_REG_TGC_RUR_CNT__M 0x1F +#define B_FE_AG_REG_TGC_RUR_CNT_INIT 0x0 + + +#define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 +#define B_FE_AG_REG_TGC_SET_LVL__W 6 +#define B_FE_AG_REG_TGC_SET_LVL__M 0x3F +#define B_FE_AG_REG_TGC_SET_LVL_INIT 0x18 + + +#define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 +#define B_FE_AG_REG_TGC_FLA_RGN__W 6 +#define B_FE_AG_REG_TGC_FLA_RGN__M 0x3F +#define B_FE_AG_REG_TGC_FLA_RGN_INIT 0x0 + + +#define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 +#define B_FE_AG_REG_TGC_JMP_PSN__W 4 +#define B_FE_AG_REG_TGC_JMP_PSN__M 0xF +#define B_FE_AG_REG_TGC_JMP_PSN_INIT 0x0 + + +#define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 +#define B_FE_AG_REG_TGC_FLA_STP__W 16 +#define B_FE_AG_REG_TGC_FLA_STP__M 0xFFFF +#define B_FE_AG_REG_TGC_FLA_STP_INIT 0x0 + + +#define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 +#define B_FE_AG_REG_TGC_SLO_STP__W 16 +#define B_FE_AG_REG_TGC_SLO_STP__M 0xFFFF +#define B_FE_AG_REG_TGC_SLO_STP_INIT 0x1 + + +#define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 +#define B_FE_AG_REG_TGC_MAP_DAT__W 10 +#define B_FE_AG_REG_TGC_MAP_DAT__M 0x3FF + +#define B_FE_AG_REG_FGM_WRI__A 0xC20061 +#define B_FE_AG_REG_FGM_WRI__W 10 +#define B_FE_AG_REG_FGM_WRI__M 0x3FF +#define B_FE_AG_REG_FGM_WRI_INIT 0x80 + + +#define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 +#define B_FE_AG_REG_BGC_FGC_WRI__W 4 +#define B_FE_AG_REG_BGC_FGC_WRI__M 0xF +#define B_FE_AG_REG_BGC_FGC_WRI_INIT 0x0 + + +#define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 +#define B_FE_AG_REG_BGC_CGC_WRI__W 2 +#define B_FE_AG_REG_BGC_CGC_WRI__M 0x3 +#define B_FE_AG_REG_BGC_CGC_WRI_INIT 0x0 + + +#define B_FE_AG_REG_BGC_THD_LVL__A 0xC2006B +#define B_FE_AG_REG_BGC_THD_LVL__W 4 +#define B_FE_AG_REG_BGC_THD_LVL__M 0xF +#define B_FE_AG_REG_BGC_THD_LVL_INIT 0xF + + +#define B_FE_AG_REG_BGC_THD_INC__A 0xC2006C +#define B_FE_AG_REG_BGC_THD_INC__W 4 +#define B_FE_AG_REG_BGC_THD_INC__M 0xF +#define B_FE_AG_REG_BGC_THD_INC_INIT 0x8 + + +#define B_FE_AG_REG_BGC_DAT__A 0xC2006D +#define B_FE_AG_REG_BGC_DAT__W 4 +#define B_FE_AG_REG_BGC_DAT__M 0xF + +#define B_FE_AG_REG_IND_PD1_COM__A 0xC2006E +#define B_FE_AG_REG_IND_PD1_COM__W 6 +#define B_FE_AG_REG_IND_PD1_COM__M 0x3F +#define B_FE_AG_REG_IND_PD1_COM_INIT 0x7 + + +#define B_FE_AG_REG_AG_AGC_BUF__A 0xC2006F +#define B_FE_AG_REG_AG_AGC_BUF__W 2 +#define B_FE_AG_REG_AG_AGC_BUF__M 0x3 +#define B_FE_AG_REG_AG_AGC_BUF_INIT 0x3 + +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__B 0 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__W 1 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__M 0x1 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_SLOW 0x0 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_FAST 0x1 + +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__B 1 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__W 1 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__M 0x2 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_SLOW 0x0 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_FAST 0x2 + + +#define B_FE_AG_REG_PMX_SPE__A 0xC20070 +#define B_FE_AG_REG_PMX_SPE__W 3 +#define B_FE_AG_REG_PMX_SPE__M 0x7 +#define B_FE_AG_REG_PMX_SPE_INIT 0x1 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_1 0x0 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_2 0x1 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_3 0x2 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_4 0x3 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_5 0x4 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_6 0x5 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_7 0x6 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_8 0x7 + + + + + +#define B_FE_FS_SID 0x3 + + + + + + +#define B_FE_FS_REG_COMM_EXEC__A 0xC30000 +#define B_FE_FS_REG_COMM_EXEC__W 3 +#define B_FE_FS_REG_COMM_EXEC__M 0x7 +#define B_FE_FS_REG_COMM_EXEC_CTL__B 0 +#define B_FE_FS_REG_COMM_EXEC_CTL__W 3 +#define B_FE_FS_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_FE_FS_REG_COMM_STATE__A 0xC30001 +#define B_FE_FS_REG_COMM_STATE__W 4 +#define B_FE_FS_REG_COMM_STATE__M 0xF + +#define B_FE_FS_REG_COMM_MB__A 0xC30002 +#define B_FE_FS_REG_COMM_MB__W 3 +#define B_FE_FS_REG_COMM_MB__M 0x7 +#define B_FE_FS_REG_COMM_MB_CTR__B 0 +#define B_FE_FS_REG_COMM_MB_CTR__W 1 +#define B_FE_FS_REG_COMM_MB_CTR__M 0x1 +#define B_FE_FS_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_FS_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_FS_REG_COMM_MB_OBS__B 1 +#define B_FE_FS_REG_COMM_MB_OBS__W 1 +#define B_FE_FS_REG_COMM_MB_OBS__M 0x2 +#define B_FE_FS_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_FS_REG_COMM_MB_OBS_ON 0x2 +#define B_FE_FS_REG_COMM_MB_MUX__B 2 +#define B_FE_FS_REG_COMM_MB_MUX__W 1 +#define B_FE_FS_REG_COMM_MB_MUX__M 0x4 +#define B_FE_FS_REG_COMM_MB_MUX_REAL 0x0 +#define B_FE_FS_REG_COMM_MB_MUX_IMAG 0x4 + + +#define B_FE_FS_REG_COMM_SERVICE0__A 0xC30003 +#define B_FE_FS_REG_COMM_SERVICE0__W 10 +#define B_FE_FS_REG_COMM_SERVICE0__M 0x3FF + +#define B_FE_FS_REG_COMM_SERVICE1__A 0xC30004 +#define B_FE_FS_REG_COMM_SERVICE1__W 11 +#define B_FE_FS_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_FS_REG_COMM_ACT__A 0xC30005 +#define B_FE_FS_REG_COMM_ACT__W 2 +#define B_FE_FS_REG_COMM_ACT__M 0x3 + +#define B_FE_FS_REG_COMM_CNT__A 0xC30006 +#define B_FE_FS_REG_COMM_CNT__W 16 +#define B_FE_FS_REG_COMM_CNT__M 0xFFFF + +#define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010 +#define B_FE_FS_REG_ADD_INC_LOP__W 16 +#define B_FE_FS_REG_ADD_INC_LOP__M 0xFFFF +#define B_FE_FS_REG_ADD_INC_LOP_INIT 0x0 + + +#define B_FE_FS_REG_ADD_INC_HIP__A 0xC30011 +#define B_FE_FS_REG_ADD_INC_HIP__W 12 +#define B_FE_FS_REG_ADD_INC_HIP__M 0xFFF +#define B_FE_FS_REG_ADD_INC_HIP_INIT 0xC00 + + +#define B_FE_FS_REG_ADD_OFF__A 0xC30012 +#define B_FE_FS_REG_ADD_OFF__W 12 +#define B_FE_FS_REG_ADD_OFF__M 0xFFF +#define B_FE_FS_REG_ADD_OFF_INIT 0x0 + + +#define B_FE_FS_REG_ADD_OFF_VAL__A 0xC30013 +#define B_FE_FS_REG_ADD_OFF_VAL__W 1 +#define B_FE_FS_REG_ADD_OFF_VAL__M 0x1 +#define B_FE_FS_REG_ADD_OFF_VAL_INIT 0x0 + + + + + +#define B_FE_FD_SID 0x4 + + + + + + +#define B_FE_FD_REG_COMM_EXEC__A 0xC40000 +#define B_FE_FD_REG_COMM_EXEC__W 3 +#define B_FE_FD_REG_COMM_EXEC__M 0x7 +#define B_FE_FD_REG_COMM_EXEC_CTL__B 0 +#define B_FE_FD_REG_COMM_EXEC_CTL__W 3 +#define B_FE_FD_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define B_FE_FD_REG_COMM_MB__A 0xC40002 +#define B_FE_FD_REG_COMM_MB__W 3 +#define B_FE_FD_REG_COMM_MB__M 0x7 +#define B_FE_FD_REG_COMM_MB_CTR__B 0 +#define B_FE_FD_REG_COMM_MB_CTR__W 1 +#define B_FE_FD_REG_COMM_MB_CTR__M 0x1 +#define B_FE_FD_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_FD_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_FD_REG_COMM_MB_OBS__B 1 +#define B_FE_FD_REG_COMM_MB_OBS__W 1 +#define B_FE_FD_REG_COMM_MB_OBS__M 0x2 +#define B_FE_FD_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_FD_REG_COMM_MB_OBS_ON 0x2 + +#define B_FE_FD_REG_COMM_SERVICE0__A 0xC40003 +#define B_FE_FD_REG_COMM_SERVICE0__W 10 +#define B_FE_FD_REG_COMM_SERVICE0__M 0x3FF +#define B_FE_FD_REG_COMM_SERVICE1__A 0xC40004 +#define B_FE_FD_REG_COMM_SERVICE1__W 11 +#define B_FE_FD_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_FD_REG_COMM_INT_STA__A 0xC40007 +#define B_FE_FD_REG_COMM_INT_STA__W 1 +#define B_FE_FD_REG_COMM_INT_STA__M 0x1 +#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + + +#define B_FE_FD_REG_COMM_INT_MSK__A 0xC40008 +#define B_FE_FD_REG_COMM_INT_MSK__W 1 +#define B_FE_FD_REG_COMM_INT_MSK__M 0x1 +#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + + +#define B_FE_FD_REG_SCL__A 0xC40010 +#define B_FE_FD_REG_SCL__W 6 +#define B_FE_FD_REG_SCL__M 0x3F + +#define B_FE_FD_REG_MAX_LEV__A 0xC40011 +#define B_FE_FD_REG_MAX_LEV__W 3 +#define B_FE_FD_REG_MAX_LEV__M 0x7 + +#define B_FE_FD_REG_NR__A 0xC40012 +#define B_FE_FD_REG_NR__W 5 +#define B_FE_FD_REG_NR__M 0x1F + +#define B_FE_FD_REG_MEAS_SEL__A 0xC40013 +#define B_FE_FD_REG_MEAS_SEL__W 1 +#define B_FE_FD_REG_MEAS_SEL__M 0x1 + +#define B_FE_FD_REG_MEAS_VAL__A 0xC40014 +#define B_FE_FD_REG_MEAS_VAL__W 1 +#define B_FE_FD_REG_MEAS_VAL__M 0x1 + +#define B_FE_FD_REG_MAX__A 0xC40015 +#define B_FE_FD_REG_MAX__W 16 +#define B_FE_FD_REG_MAX__M 0xFFFF + + + + + +#define B_FE_IF_SID 0x5 + + + + + + +#define B_FE_IF_REG_COMM_EXEC__A 0xC50000 +#define B_FE_IF_REG_COMM_EXEC__W 3 +#define B_FE_IF_REG_COMM_EXEC__M 0x7 +#define B_FE_IF_REG_COMM_EXEC_CTL__B 0 +#define B_FE_IF_REG_COMM_EXEC_CTL__W 3 +#define B_FE_IF_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define B_FE_IF_REG_COMM_MB__A 0xC50002 +#define B_FE_IF_REG_COMM_MB__W 3 +#define B_FE_IF_REG_COMM_MB__M 0x7 +#define B_FE_IF_REG_COMM_MB_CTR__B 0 +#define B_FE_IF_REG_COMM_MB_CTR__W 1 +#define B_FE_IF_REG_COMM_MB_CTR__M 0x1 +#define B_FE_IF_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_IF_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_IF_REG_COMM_MB_OBS__B 1 +#define B_FE_IF_REG_COMM_MB_OBS__W 1 +#define B_FE_IF_REG_COMM_MB_OBS__M 0x2 +#define B_FE_IF_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_IF_REG_COMM_MB_OBS_ON 0x2 + + +#define B_FE_IF_REG_INCR0__A 0xC50010 +#define B_FE_IF_REG_INCR0__W 16 +#define B_FE_IF_REG_INCR0__M 0xFFFF +#define B_FE_IF_REG_INCR0_INIT 0x0 + + +#define B_FE_IF_REG_INCR1__A 0xC50011 +#define B_FE_IF_REG_INCR1__W 8 +#define B_FE_IF_REG_INCR1__M 0xFF +#define B_FE_IF_REG_INCR1_INIT 0x28 + + + + + +#define B_FE_CF_SID 0x6 + + + + + + +#define B_FE_CF_REG_COMM_EXEC__A 0xC60000 +#define B_FE_CF_REG_COMM_EXEC__W 3 +#define B_FE_CF_REG_COMM_EXEC__M 0x7 +#define B_FE_CF_REG_COMM_EXEC_CTL__B 0 +#define B_FE_CF_REG_COMM_EXEC_CTL__W 3 +#define B_FE_CF_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define B_FE_CF_REG_COMM_MB__A 0xC60002 +#define B_FE_CF_REG_COMM_MB__W 3 +#define B_FE_CF_REG_COMM_MB__M 0x7 +#define B_FE_CF_REG_COMM_MB_CTR__B 0 +#define B_FE_CF_REG_COMM_MB_CTR__W 1 +#define B_FE_CF_REG_COMM_MB_CTR__M 0x1 +#define B_FE_CF_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_CF_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_CF_REG_COMM_MB_OBS__B 1 +#define B_FE_CF_REG_COMM_MB_OBS__W 1 +#define B_FE_CF_REG_COMM_MB_OBS__M 0x2 +#define B_FE_CF_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_CF_REG_COMM_MB_OBS_ON 0x2 + +#define B_FE_CF_REG_COMM_SERVICE0__A 0xC60003 +#define B_FE_CF_REG_COMM_SERVICE0__W 10 +#define B_FE_CF_REG_COMM_SERVICE0__M 0x3FF +#define B_FE_CF_REG_COMM_SERVICE1__A 0xC60004 +#define B_FE_CF_REG_COMM_SERVICE1__W 11 +#define B_FE_CF_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_CF_REG_COMM_INT_STA__A 0xC60007 +#define B_FE_CF_REG_COMM_INT_STA__W 2 +#define B_FE_CF_REG_COMM_INT_STA__M 0x3 +#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + + +#define B_FE_CF_REG_COMM_INT_MSK__A 0xC60008 +#define B_FE_CF_REG_COMM_INT_MSK__W 2 +#define B_FE_CF_REG_COMM_INT_MSK__M 0x3 +#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + + +#define B_FE_CF_REG_SCL__A 0xC60010 +#define B_FE_CF_REG_SCL__W 9 +#define B_FE_CF_REG_SCL__M 0x1FF + +#define B_FE_CF_REG_MAX_LEV__A 0xC60011 +#define B_FE_CF_REG_MAX_LEV__W 3 +#define B_FE_CF_REG_MAX_LEV__M 0x7 + +#define B_FE_CF_REG_NR__A 0xC60012 +#define B_FE_CF_REG_NR__W 5 +#define B_FE_CF_REG_NR__M 0x1F + +#define B_FE_CF_REG_IMP_VAL__A 0xC60013 +#define B_FE_CF_REG_IMP_VAL__W 1 +#define B_FE_CF_REG_IMP_VAL__M 0x1 + +#define B_FE_CF_REG_MEAS_VAL__A 0xC60014 +#define B_FE_CF_REG_MEAS_VAL__W 1 +#define B_FE_CF_REG_MEAS_VAL__M 0x1 + +#define B_FE_CF_REG_MAX__A 0xC60015 +#define B_FE_CF_REG_MAX__W 16 +#define B_FE_CF_REG_MAX__M 0xFFFF + + + + + +#define B_FE_CU_SID 0x7 + + + + + + +#define B_FE_CU_REG_COMM_EXEC__A 0xC70000 +#define B_FE_CU_REG_COMM_EXEC__W 3 +#define B_FE_CU_REG_COMM_EXEC__M 0x7 +#define B_FE_CU_REG_COMM_EXEC_CTL__B 0 +#define B_FE_CU_REG_COMM_EXEC_CTL__W 3 +#define B_FE_CU_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_FE_CU_REG_COMM_STATE__A 0xC70001 +#define B_FE_CU_REG_COMM_STATE__W 4 +#define B_FE_CU_REG_COMM_STATE__M 0xF + +#define B_FE_CU_REG_COMM_MB__A 0xC70002 +#define B_FE_CU_REG_COMM_MB__W 3 +#define B_FE_CU_REG_COMM_MB__M 0x7 +#define B_FE_CU_REG_COMM_MB_CTR__B 0 +#define B_FE_CU_REG_COMM_MB_CTR__W 1 +#define B_FE_CU_REG_COMM_MB_CTR__M 0x1 +#define B_FE_CU_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_CU_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_CU_REG_COMM_MB_OBS__B 1 +#define B_FE_CU_REG_COMM_MB_OBS__W 1 +#define B_FE_CU_REG_COMM_MB_OBS__M 0x2 +#define B_FE_CU_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_CU_REG_COMM_MB_OBS_ON 0x2 +#define B_FE_CU_REG_COMM_MB_MUX__B 2 +#define B_FE_CU_REG_COMM_MB_MUX__W 1 +#define B_FE_CU_REG_COMM_MB_MUX__M 0x4 +#define B_FE_CU_REG_COMM_MB_MUX_REAL 0x0 +#define B_FE_CU_REG_COMM_MB_MUX_IMAG 0x4 + + +#define B_FE_CU_REG_COMM_SERVICE0__A 0xC70003 +#define B_FE_CU_REG_COMM_SERVICE0__W 10 +#define B_FE_CU_REG_COMM_SERVICE0__M 0x3FF + +#define B_FE_CU_REG_COMM_SERVICE1__A 0xC70004 +#define B_FE_CU_REG_COMM_SERVICE1__W 11 +#define B_FE_CU_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_CU_REG_COMM_ACT__A 0xC70005 +#define B_FE_CU_REG_COMM_ACT__W 2 +#define B_FE_CU_REG_COMM_ACT__M 0x3 + +#define B_FE_CU_REG_COMM_CNT__A 0xC70006 +#define B_FE_CU_REG_COMM_CNT__W 16 +#define B_FE_CU_REG_COMM_CNT__M 0xFFFF + +#define B_FE_CU_REG_COMM_INT_STA__A 0xC70007 +#define B_FE_CU_REG_COMM_INT_STA__W 4 +#define B_FE_CU_REG_COMM_INT_STA__M 0xF +#define B_FE_CU_REG_COMM_INT_STA_FE_START__B 0 +#define B_FE_CU_REG_COMM_INT_STA_FE_START__W 1 +#define B_FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 +#define B_FE_CU_REG_COMM_INT_STA_FT_START__B 1 +#define B_FE_CU_REG_COMM_INT_STA_FT_START__W 1 +#define B_FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 +#define B_FE_CU_REG_COMM_INT_STA_SB_START__B 2 +#define B_FE_CU_REG_COMM_INT_STA_SB_START__W 1 +#define B_FE_CU_REG_COMM_INT_STA_SB_START__M 0x4 +#define B_FE_CU_REG_COMM_INT_STA_NF_READY__B 3 +#define B_FE_CU_REG_COMM_INT_STA_NF_READY__W 1 +#define B_FE_CU_REG_COMM_INT_STA_NF_READY__M 0x8 + + +#define B_FE_CU_REG_COMM_INT_MSK__A 0xC70008 +#define B_FE_CU_REG_COMM_INT_MSK__W 4 +#define B_FE_CU_REG_COMM_INT_MSK__M 0xF +#define B_FE_CU_REG_COMM_INT_MSK_FE_START__B 0 +#define B_FE_CU_REG_COMM_INT_MSK_FE_START__W 1 +#define B_FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 +#define B_FE_CU_REG_COMM_INT_MSK_FT_START__B 1 +#define B_FE_CU_REG_COMM_INT_MSK_FT_START__W 1 +#define B_FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 +#define B_FE_CU_REG_COMM_INT_MSK_SB_START__B 2 +#define B_FE_CU_REG_COMM_INT_MSK_SB_START__W 1 +#define B_FE_CU_REG_COMM_INT_MSK_SB_START__M 0x4 +#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__B 3 +#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__W 1 +#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__M 0x8 + + +#define B_FE_CU_REG_MODE__A 0xC70010 +#define B_FE_CU_REG_MODE__W 5 +#define B_FE_CU_REG_MODE__M 0x1F +#define B_FE_CU_REG_MODE_INIT 0x0 + +#define B_FE_CU_REG_MODE_FFT__B 0 +#define B_FE_CU_REG_MODE_FFT__W 1 +#define B_FE_CU_REG_MODE_FFT__M 0x1 +#define B_FE_CU_REG_MODE_FFT_M8K 0x0 +#define B_FE_CU_REG_MODE_FFT_M2K 0x1 + +#define B_FE_CU_REG_MODE_COR__B 1 +#define B_FE_CU_REG_MODE_COR__W 1 +#define B_FE_CU_REG_MODE_COR__M 0x2 +#define B_FE_CU_REG_MODE_COR_OFF 0x0 +#define B_FE_CU_REG_MODE_COR_ON 0x2 + +#define B_FE_CU_REG_MODE_IFD__B 2 +#define B_FE_CU_REG_MODE_IFD__W 1 +#define B_FE_CU_REG_MODE_IFD__M 0x4 +#define B_FE_CU_REG_MODE_IFD_ENABLE 0x0 +#define B_FE_CU_REG_MODE_IFD_DISABLE 0x4 + +#define B_FE_CU_REG_MODE_SEL__B 3 +#define B_FE_CU_REG_MODE_SEL__W 1 +#define B_FE_CU_REG_MODE_SEL__M 0x8 +#define B_FE_CU_REG_MODE_SEL_COR 0x0 +#define B_FE_CU_REG_MODE_SEL_COR_NFC 0x8 + +#define B_FE_CU_REG_MODE_FES__B 4 +#define B_FE_CU_REG_MODE_FES__W 1 +#define B_FE_CU_REG_MODE_FES__M 0x10 +#define B_FE_CU_REG_MODE_FES_SEL_RST 0x0 +#define B_FE_CU_REG_MODE_FES_SEL_UPD 0x10 + + +#define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 +#define B_FE_CU_REG_FRM_CNT_RST__W 15 +#define B_FE_CU_REG_FRM_CNT_RST__M 0x7FFF +#define B_FE_CU_REG_FRM_CNT_RST_INIT 0x20FF + + +#define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 +#define B_FE_CU_REG_FRM_CNT_STR__W 15 +#define B_FE_CU_REG_FRM_CNT_STR__M 0x7FFF +#define B_FE_CU_REG_FRM_CNT_STR_INIT 0x1E + + +#define B_FE_CU_REG_FRM_SMP_CNT__A 0xC70013 +#define B_FE_CU_REG_FRM_SMP_CNT__W 15 +#define B_FE_CU_REG_FRM_SMP_CNT__M 0x7FFF + +#define B_FE_CU_REG_FRM_SMB_CNT__A 0xC70014 +#define B_FE_CU_REG_FRM_SMB_CNT__W 16 +#define B_FE_CU_REG_FRM_SMB_CNT__M 0xFFFF + +#define B_FE_CU_REG_CMP_MAX_DAT__A 0xC70015 +#define B_FE_CU_REG_CMP_MAX_DAT__W 12 +#define B_FE_CU_REG_CMP_MAX_DAT__M 0xFFF + +#define B_FE_CU_REG_CMP_MAX_ADR__A 0xC70016 +#define B_FE_CU_REG_CMP_MAX_ADR__W 10 +#define B_FE_CU_REG_CMP_MAX_ADR__M 0x3FF + +#define B_FE_CU_REG_BUF_NFC_DEL__A 0xC7001F +#define B_FE_CU_REG_BUF_NFC_DEL__W 14 +#define B_FE_CU_REG_BUF_NFC_DEL__M 0x3FFF +#define B_FE_CU_REG_BUF_NFC_DEL_INIT 0x0 + + +#define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 +#define B_FE_CU_REG_CTR_NFC_ICR__W 5 +#define B_FE_CU_REG_CTR_NFC_ICR__M 0x1F +#define B_FE_CU_REG_CTR_NFC_ICR_INIT 0x0 + + +#define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 +#define B_FE_CU_REG_CTR_NFC_OCR__W 15 +#define B_FE_CU_REG_CTR_NFC_OCR__M 0x7FFF +#define B_FE_CU_REG_CTR_NFC_OCR_INIT 0x61A8 + + +#define B_FE_CU_REG_CTR_NFC_CNT__A 0xC70022 +#define B_FE_CU_REG_CTR_NFC_CNT__W 15 +#define B_FE_CU_REG_CTR_NFC_CNT__M 0x7FFF + +#define B_FE_CU_REG_CTR_NFC_STS__A 0xC70023 +#define B_FE_CU_REG_CTR_NFC_STS__W 3 +#define B_FE_CU_REG_CTR_NFC_STS__M 0x7 +#define B_FE_CU_REG_CTR_NFC_STS_RUN 0x0 +#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_IMA 0x1 +#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_REA 0x2 +#define B_FE_CU_REG_CTR_NFC_STS_CNT_MAX 0x4 + + +#define B_FE_CU_REG_DIV_NFC_REA__A 0xC70024 +#define B_FE_CU_REG_DIV_NFC_REA__W 14 +#define B_FE_CU_REG_DIV_NFC_REA__M 0x3FFF + +#define B_FE_CU_REG_DIV_NFC_IMA__A 0xC70025 +#define B_FE_CU_REG_DIV_NFC_IMA__W 14 +#define B_FE_CU_REG_DIV_NFC_IMA__M 0x3FFF + +#define B_FE_CU_REG_FRM_CNT_UPD__A 0xC70026 +#define B_FE_CU_REG_FRM_CNT_UPD__W 15 +#define B_FE_CU_REG_FRM_CNT_UPD__M 0x7FFF +#define B_FE_CU_REG_FRM_CNT_UPD_INIT 0x20FF + + +#define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 +#define B_FE_CU_REG_DIV_NFC_CLP__W 2 +#define B_FE_CU_REG_DIV_NFC_CLP__M 0x3 +#define B_FE_CU_REG_DIV_NFC_CLP_INIT 0x1 +#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S11 0x0 +#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S12 0x1 +#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S13 0x2 +#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S14 0x3 + + + +#define B_FE_CU_BUF_RAM__A 0xC80000 + + + +#define B_FE_CU_CMP_RAM__A 0xC90000 + + + + + +#define B_FT_SID 0x8 + + + + + +#define B_FT_COMM_EXEC__A 0x1000000 +#define B_FT_COMM_EXEC__W 3 +#define B_FT_COMM_EXEC__M 0x7 +#define B_FT_COMM_EXEC_CTL__B 0 +#define B_FT_COMM_EXEC_CTL__W 3 +#define B_FT_COMM_EXEC_CTL__M 0x7 +#define B_FT_COMM_EXEC_CTL_STOP 0x0 +#define B_FT_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FT_COMM_EXEC_CTL_HOLD 0x2 +#define B_FT_COMM_EXEC_CTL_STEP 0x3 +#define B_FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_FT_COMM_STATE__A 0x1000001 +#define B_FT_COMM_STATE__W 16 +#define B_FT_COMM_STATE__M 0xFFFF +#define B_FT_COMM_MB__A 0x1000002 +#define B_FT_COMM_MB__W 16 +#define B_FT_COMM_MB__M 0xFFFF +#define B_FT_COMM_SERVICE0__A 0x1000003 +#define B_FT_COMM_SERVICE0__W 16 +#define B_FT_COMM_SERVICE0__M 0xFFFF +#define B_FT_COMM_SERVICE1__A 0x1000004 +#define B_FT_COMM_SERVICE1__W 16 +#define B_FT_COMM_SERVICE1__M 0xFFFF +#define B_FT_COMM_INT_STA__A 0x1000007 +#define B_FT_COMM_INT_STA__W 16 +#define B_FT_COMM_INT_STA__M 0xFFFF +#define B_FT_COMM_INT_MSK__A 0x1000008 +#define B_FT_COMM_INT_MSK__W 16 +#define B_FT_COMM_INT_MSK__M 0xFFFF + + + + + + +#define B_FT_REG_COMM_EXEC__A 0x1010000 +#define B_FT_REG_COMM_EXEC__W 3 +#define B_FT_REG_COMM_EXEC__M 0x7 +#define B_FT_REG_COMM_EXEC_CTL__B 0 +#define B_FT_REG_COMM_EXEC_CTL__W 3 +#define B_FT_REG_COMM_EXEC_CTL__M 0x7 +#define B_FT_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FT_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define B_FT_REG_COMM_MB__A 0x1010002 +#define B_FT_REG_COMM_MB__W 3 +#define B_FT_REG_COMM_MB__M 0x7 +#define B_FT_REG_COMM_MB_CTR__B 0 +#define B_FT_REG_COMM_MB_CTR__W 1 +#define B_FT_REG_COMM_MB_CTR__M 0x1 +#define B_FT_REG_COMM_MB_CTR_OFF 0x0 +#define B_FT_REG_COMM_MB_CTR_ON 0x1 +#define B_FT_REG_COMM_MB_OBS__B 1 +#define B_FT_REG_COMM_MB_OBS__W 1 +#define B_FT_REG_COMM_MB_OBS__M 0x2 +#define B_FT_REG_COMM_MB_OBS_OFF 0x0 +#define B_FT_REG_COMM_MB_OBS_ON 0x2 + + +#define B_FT_REG_MODE_2K__A 0x1010010 +#define B_FT_REG_MODE_2K__W 1 +#define B_FT_REG_MODE_2K__M 0x1 +#define B_FT_REG_MODE_2K_MODE_8K 0x0 +#define B_FT_REG_MODE_2K_MODE_2K 0x1 +#define B_FT_REG_MODE_2K_INIT 0x0 + + +#define B_FT_REG_NORM_OFF__A 0x1010016 +#define B_FT_REG_NORM_OFF__W 4 +#define B_FT_REG_NORM_OFF__M 0xF +#define B_FT_REG_NORM_OFF_INIT 0x2 + + + +#define B_FT_ST1_RAM__A 0x1020000 + + + +#define B_FT_ST2_RAM__A 0x1030000 + + + +#define B_FT_ST3_RAM__A 0x1040000 + + + +#define B_FT_ST5_RAM__A 0x1050000 + + + +#define B_FT_ST6_RAM__A 0x1060000 + + + +#define B_FT_ST8_RAM__A 0x1070000 + + + +#define B_FT_ST9_RAM__A 0x1080000 + + + + + +#define B_CP_SID 0x9 + + + + + +#define B_CP_COMM_EXEC__A 0x1400000 +#define B_CP_COMM_EXEC__W 3 +#define B_CP_COMM_EXEC__M 0x7 +#define B_CP_COMM_EXEC_CTL__B 0 +#define B_CP_COMM_EXEC_CTL__W 3 +#define B_CP_COMM_EXEC_CTL__M 0x7 +#define B_CP_COMM_EXEC_CTL_STOP 0x0 +#define B_CP_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CP_COMM_EXEC_CTL_HOLD 0x2 +#define B_CP_COMM_EXEC_CTL_STEP 0x3 +#define B_CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_CP_COMM_STATE__A 0x1400001 +#define B_CP_COMM_STATE__W 16 +#define B_CP_COMM_STATE__M 0xFFFF +#define B_CP_COMM_MB__A 0x1400002 +#define B_CP_COMM_MB__W 16 +#define B_CP_COMM_MB__M 0xFFFF +#define B_CP_COMM_SERVICE0__A 0x1400003 +#define B_CP_COMM_SERVICE0__W 16 +#define B_CP_COMM_SERVICE0__M 0xFFFF +#define B_CP_COMM_SERVICE1__A 0x1400004 +#define B_CP_COMM_SERVICE1__W 16 +#define B_CP_COMM_SERVICE1__M 0xFFFF +#define B_CP_COMM_INT_STA__A 0x1400007 +#define B_CP_COMM_INT_STA__W 16 +#define B_CP_COMM_INT_STA__M 0xFFFF +#define B_CP_COMM_INT_MSK__A 0x1400008 +#define B_CP_COMM_INT_MSK__W 16 +#define B_CP_COMM_INT_MSK__M 0xFFFF + + + + + + +#define B_CP_REG_COMM_EXEC__A 0x1410000 +#define B_CP_REG_COMM_EXEC__W 3 +#define B_CP_REG_COMM_EXEC__M 0x7 +#define B_CP_REG_COMM_EXEC_CTL__B 0 +#define B_CP_REG_COMM_EXEC_CTL__W 3 +#define B_CP_REG_COMM_EXEC_CTL__M 0x7 +#define B_CP_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CP_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_CP_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define B_CP_REG_COMM_MB__A 0x1410002 +#define B_CP_REG_COMM_MB__W 3 +#define B_CP_REG_COMM_MB__M 0x7 +#define B_CP_REG_COMM_MB_CTR__B 0 +#define B_CP_REG_COMM_MB_CTR__W 1 +#define B_CP_REG_COMM_MB_CTR__M 0x1 +#define B_CP_REG_COMM_MB_CTR_OFF 0x0 +#define B_CP_REG_COMM_MB_CTR_ON 0x1 +#define B_CP_REG_COMM_MB_OBS__B 1 +#define B_CP_REG_COMM_MB_OBS__W 1 +#define B_CP_REG_COMM_MB_OBS__M 0x2 +#define B_CP_REG_COMM_MB_OBS_OFF 0x0 +#define B_CP_REG_COMM_MB_OBS_ON 0x2 + +#define B_CP_REG_COMM_SERVICE0__A 0x1410003 +#define B_CP_REG_COMM_SERVICE0__W 10 +#define B_CP_REG_COMM_SERVICE0__M 0x3FF +#define B_CP_REG_COMM_SERVICE0_CP__B 9 +#define B_CP_REG_COMM_SERVICE0_CP__W 1 +#define B_CP_REG_COMM_SERVICE0_CP__M 0x200 + +#define B_CP_REG_COMM_SERVICE1__A 0x1410004 +#define B_CP_REG_COMM_SERVICE1__W 11 +#define B_CP_REG_COMM_SERVICE1__M 0x7FF + +#define B_CP_REG_COMM_INT_STA__A 0x1410007 +#define B_CP_REG_COMM_INT_STA__W 2 +#define B_CP_REG_COMM_INT_STA__M 0x3 +#define B_CP_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define B_CP_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define B_CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + + +#define B_CP_REG_COMM_INT_MSK__A 0x1410008 +#define B_CP_REG_COMM_INT_MSK__W 2 +#define B_CP_REG_COMM_INT_MSK__M 0x3 +#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + + +#define B_CP_REG_MODE_2K__A 0x1410010 +#define B_CP_REG_MODE_2K__W 1 +#define B_CP_REG_MODE_2K__M 0x1 +#define B_CP_REG_MODE_2K_INIT 0x0 + + +#define B_CP_REG_INTERVAL__A 0x1410011 +#define B_CP_REG_INTERVAL__W 4 +#define B_CP_REG_INTERVAL__M 0xF +#define B_CP_REG_INTERVAL_INIT 0x5 + + +#define B_CP_REG_DETECT_ENA__A 0x1410012 +#define B_CP_REG_DETECT_ENA__W 2 +#define B_CP_REG_DETECT_ENA__M 0x3 + +#define B_CP_REG_DETECT_ENA_SCATTERED__B 0 +#define B_CP_REG_DETECT_ENA_SCATTERED__W 1 +#define B_CP_REG_DETECT_ENA_SCATTERED__M 0x1 + +#define B_CP_REG_DETECT_ENA_CONTINUOUS__B 1 +#define B_CP_REG_DETECT_ENA_CONTINUOUS__W 1 +#define B_CP_REG_DETECT_ENA_CONTINUOUS__M 0x2 +#define B_CP_REG_DETECT_ENA_INIT 0x0 + + +#define B_CP_REG_BR_SMB_NR__A 0x1410021 +#define B_CP_REG_BR_SMB_NR__W 4 +#define B_CP_REG_BR_SMB_NR__M 0xF + +#define B_CP_REG_BR_SMB_NR_SMB__B 0 +#define B_CP_REG_BR_SMB_NR_SMB__W 2 +#define B_CP_REG_BR_SMB_NR_SMB__M 0x3 + +#define B_CP_REG_BR_SMB_NR_VAL__B 2 +#define B_CP_REG_BR_SMB_NR_VAL__W 1 +#define B_CP_REG_BR_SMB_NR_VAL__M 0x4 + +#define B_CP_REG_BR_SMB_NR_OFFSET__B 3 +#define B_CP_REG_BR_SMB_NR_OFFSET__W 1 +#define B_CP_REG_BR_SMB_NR_OFFSET__M 0x8 +#define B_CP_REG_BR_SMB_NR_INIT 0x0 + + +#define B_CP_REG_BR_CP_SMB_NR__A 0x1410022 +#define B_CP_REG_BR_CP_SMB_NR__W 2 +#define B_CP_REG_BR_CP_SMB_NR__M 0x3 +#define B_CP_REG_BR_CP_SMB_NR_INIT 0x0 + + +#define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 +#define B_CP_REG_BR_SPL_OFFSET__W 3 +#define B_CP_REG_BR_SPL_OFFSET__M 0x7 +#define B_CP_REG_BR_SPL_OFFSET_INIT 0x0 + + +#define B_CP_REG_BR_STR_DEL__A 0x1410024 +#define B_CP_REG_BR_STR_DEL__W 10 +#define B_CP_REG_BR_STR_DEL__M 0x3FF +#define B_CP_REG_BR_STR_DEL_INIT 0xA + + +#define B_CP_REG_BR_EXP_ADJ__A 0x1410025 +#define B_CP_REG_BR_EXP_ADJ__W 5 +#define B_CP_REG_BR_EXP_ADJ__M 0x1F +#define B_CP_REG_BR_EXP_ADJ_INIT 0x10 + + +#define B_CP_REG_RT_ANG_INC0__A 0x1410030 +#define B_CP_REG_RT_ANG_INC0__W 16 +#define B_CP_REG_RT_ANG_INC0__M 0xFFFF +#define B_CP_REG_RT_ANG_INC0_INIT 0x0 + + +#define B_CP_REG_RT_ANG_INC1__A 0x1410031 +#define B_CP_REG_RT_ANG_INC1__W 8 +#define B_CP_REG_RT_ANG_INC1__M 0xFF +#define B_CP_REG_RT_ANG_INC1_INIT 0x0 + + +#define B_CP_REG_RT_SPD_EXP_MARG__A 0x1410032 +#define B_CP_REG_RT_SPD_EXP_MARG__W 5 +#define B_CP_REG_RT_SPD_EXP_MARG__M 0x1F +#define B_CP_REG_RT_SPD_EXP_MARG_INIT 0x5 + + +#define B_CP_REG_RT_DETECT_TRH__A 0x1410033 +#define B_CP_REG_RT_DETECT_TRH__W 2 +#define B_CP_REG_RT_DETECT_TRH__M 0x3 +#define B_CP_REG_RT_DETECT_TRH_INIT 0x3 + + +#define B_CP_REG_RT_SPD_RELIABLE__A 0x1410034 +#define B_CP_REG_RT_SPD_RELIABLE__W 3 +#define B_CP_REG_RT_SPD_RELIABLE__M 0x7 +#define B_CP_REG_RT_SPD_RELIABLE_INIT 0x0 + + +#define B_CP_REG_RT_SPD_DIRECTION__A 0x1410035 +#define B_CP_REG_RT_SPD_DIRECTION__W 1 +#define B_CP_REG_RT_SPD_DIRECTION__M 0x1 +#define B_CP_REG_RT_SPD_DIRECTION_INIT 0x0 + + +#define B_CP_REG_RT_SPD_MOD__A 0x1410036 +#define B_CP_REG_RT_SPD_MOD__W 2 +#define B_CP_REG_RT_SPD_MOD__M 0x3 +#define B_CP_REG_RT_SPD_MOD_INIT 0x0 + + +#define B_CP_REG_RT_SPD_SMB__A 0x1410037 +#define B_CP_REG_RT_SPD_SMB__W 2 +#define B_CP_REG_RT_SPD_SMB__M 0x3 +#define B_CP_REG_RT_SPD_SMB_INIT 0x0 + + +#define B_CP_REG_RT_CPD_MODE__A 0x1410038 +#define B_CP_REG_RT_CPD_MODE__W 3 +#define B_CP_REG_RT_CPD_MODE__M 0x7 + +#define B_CP_REG_RT_CPD_MODE_MOD3__B 0 +#define B_CP_REG_RT_CPD_MODE_MOD3__W 2 +#define B_CP_REG_RT_CPD_MODE_MOD3__M 0x3 + +#define B_CP_REG_RT_CPD_MODE_ADD__B 2 +#define B_CP_REG_RT_CPD_MODE_ADD__W 1 +#define B_CP_REG_RT_CPD_MODE_ADD__M 0x4 +#define B_CP_REG_RT_CPD_MODE_INIT 0x0 + + +#define B_CP_REG_RT_CPD_RELIABLE__A 0x1410039 +#define B_CP_REG_RT_CPD_RELIABLE__W 3 +#define B_CP_REG_RT_CPD_RELIABLE__M 0x7 +#define B_CP_REG_RT_CPD_RELIABLE_INIT 0x0 + + +#define B_CP_REG_RT_CPD_BIN__A 0x141003A +#define B_CP_REG_RT_CPD_BIN__W 5 +#define B_CP_REG_RT_CPD_BIN__M 0x1F +#define B_CP_REG_RT_CPD_BIN_INIT 0x0 + + +#define B_CP_REG_RT_CPD_MAX__A 0x141003B +#define B_CP_REG_RT_CPD_MAX__W 4 +#define B_CP_REG_RT_CPD_MAX__M 0xF +#define B_CP_REG_RT_CPD_MAX_INIT 0x0 + + +#define B_CP_REG_RT_SUPR_VAL__A 0x141003C +#define B_CP_REG_RT_SUPR_VAL__W 2 +#define B_CP_REG_RT_SUPR_VAL__M 0x3 + +#define B_CP_REG_RT_SUPR_VAL_CE__B 0 +#define B_CP_REG_RT_SUPR_VAL_CE__W 1 +#define B_CP_REG_RT_SUPR_VAL_CE__M 0x1 + +#define B_CP_REG_RT_SUPR_VAL_DL__B 1 +#define B_CP_REG_RT_SUPR_VAL_DL__W 1 +#define B_CP_REG_RT_SUPR_VAL_DL__M 0x2 +#define B_CP_REG_RT_SUPR_VAL_INIT 0x0 + + +#define B_CP_REG_RT_EXP_AVE__A 0x141003D +#define B_CP_REG_RT_EXP_AVE__W 5 +#define B_CP_REG_RT_EXP_AVE__M 0x1F +#define B_CP_REG_RT_EXP_AVE_INIT 0x0 + + +#define B_CP_REG_RT_CPD_EXP_MARG__A 0x141003E +#define B_CP_REG_RT_CPD_EXP_MARG__W 5 +#define B_CP_REG_RT_CPD_EXP_MARG__M 0x1F +#define B_CP_REG_RT_CPD_EXP_MARG_INIT 0x3 + + +#define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 +#define B_CP_REG_AC_NEXP_OFFS__W 8 +#define B_CP_REG_AC_NEXP_OFFS__M 0xFF +#define B_CP_REG_AC_NEXP_OFFS_INIT 0x0 + + +#define B_CP_REG_AC_AVER_POW__A 0x1410041 +#define B_CP_REG_AC_AVER_POW__W 8 +#define B_CP_REG_AC_AVER_POW__M 0xFF +#define B_CP_REG_AC_AVER_POW_INIT 0x5F + + +#define B_CP_REG_AC_MAX_POW__A 0x1410042 +#define B_CP_REG_AC_MAX_POW__W 8 +#define B_CP_REG_AC_MAX_POW__M 0xFF +#define B_CP_REG_AC_MAX_POW_INIT 0x7A + + +#define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 +#define B_CP_REG_AC_WEIGHT_MAN__W 6 +#define B_CP_REG_AC_WEIGHT_MAN__M 0x3F +#define B_CP_REG_AC_WEIGHT_MAN_INIT 0x31 + + +#define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 +#define B_CP_REG_AC_WEIGHT_EXP__W 5 +#define B_CP_REG_AC_WEIGHT_EXP__M 0x1F +#define B_CP_REG_AC_WEIGHT_EXP_INIT 0x10 + + +#define B_CP_REG_AC_GAIN_MAN__A 0x1410045 +#define B_CP_REG_AC_GAIN_MAN__W 16 +#define B_CP_REG_AC_GAIN_MAN__M 0xFFFF +#define B_CP_REG_AC_GAIN_MAN_INIT 0x0 + + +#define B_CP_REG_AC_GAIN_EXP__A 0x1410046 +#define B_CP_REG_AC_GAIN_EXP__W 5 +#define B_CP_REG_AC_GAIN_EXP__M 0x1F +#define B_CP_REG_AC_GAIN_EXP_INIT 0x0 + + +#define B_CP_REG_AC_AMP_MODE__A 0x1410047 +#define B_CP_REG_AC_AMP_MODE__W 2 +#define B_CP_REG_AC_AMP_MODE__M 0x3 +#define B_CP_REG_AC_AMP_MODE_NEW 0x0 +#define B_CP_REG_AC_AMP_MODE_OLD 0x1 +#define B_CP_REG_AC_AMP_MODE_FIXED 0x2 +#define B_CP_REG_AC_AMP_MODE_INIT 0x2 + + +#define B_CP_REG_AC_AMP_FIX__A 0x1410048 +#define B_CP_REG_AC_AMP_FIX__W 14 +#define B_CP_REG_AC_AMP_FIX__M 0x3FFF +#define B_CP_REG_AC_AMP_FIX_INIT 0x1FF + + +#define B_CP_REG_AC_AMP_READ__A 0x1410049 +#define B_CP_REG_AC_AMP_READ__W 14 +#define B_CP_REG_AC_AMP_READ__M 0x3FFF +#define B_CP_REG_AC_AMP_READ_INIT 0x0 + + +#define B_CP_REG_AC_ANG_MODE__A 0x141004A +#define B_CP_REG_AC_ANG_MODE__W 2 +#define B_CP_REG_AC_ANG_MODE__M 0x3 +#define B_CP_REG_AC_ANG_MODE_NEW 0x0 +#define B_CP_REG_AC_ANG_MODE_OLD 0x1 +#define B_CP_REG_AC_ANG_MODE_NO_INT 0x2 +#define B_CP_REG_AC_ANG_MODE_OFFSET 0x3 +#define B_CP_REG_AC_ANG_MODE_INIT 0x3 + + +#define B_CP_REG_AC_ANG_OFFS__A 0x141004B +#define B_CP_REG_AC_ANG_OFFS__W 14 +#define B_CP_REG_AC_ANG_OFFS__M 0x3FFF +#define B_CP_REG_AC_ANG_OFFS_INIT 0x0 + + +#define B_CP_REG_AC_ANG_READ__A 0x141004C +#define B_CP_REG_AC_ANG_READ__W 16 +#define B_CP_REG_AC_ANG_READ__M 0xFFFF +#define B_CP_REG_AC_ANG_READ_INIT 0x0 + + +#define B_CP_REG_AC_ACCU_REAL0__A 0x1410060 +#define B_CP_REG_AC_ACCU_REAL0__W 8 +#define B_CP_REG_AC_ACCU_REAL0__M 0xFF +#define B_CP_REG_AC_ACCU_REAL0_INIT 0x0 + + +#define B_CP_REG_AC_ACCU_IMAG0__A 0x1410061 +#define B_CP_REG_AC_ACCU_IMAG0__W 8 +#define B_CP_REG_AC_ACCU_IMAG0__M 0xFF +#define B_CP_REG_AC_ACCU_IMAG0_INIT 0x0 + + +#define B_CP_REG_AC_ACCU_REAL1__A 0x1410062 +#define B_CP_REG_AC_ACCU_REAL1__W 8 +#define B_CP_REG_AC_ACCU_REAL1__M 0xFF +#define B_CP_REG_AC_ACCU_REAL1_INIT 0x0 + + +#define B_CP_REG_AC_ACCU_IMAG1__A 0x1410063 +#define B_CP_REG_AC_ACCU_IMAG1__W 8 +#define B_CP_REG_AC_ACCU_IMAG1__M 0xFF +#define B_CP_REG_AC_ACCU_IMAG1_INIT 0x0 + + +#define B_CP_REG_DL_MB_WR_ADDR__A 0x1410050 +#define B_CP_REG_DL_MB_WR_ADDR__W 15 +#define B_CP_REG_DL_MB_WR_ADDR__M 0x7FFF +#define B_CP_REG_DL_MB_WR_ADDR_INIT 0x0 + + +#define B_CP_REG_DL_MB_WR_CTR__A 0x1410051 +#define B_CP_REG_DL_MB_WR_CTR__W 5 +#define B_CP_REG_DL_MB_WR_CTR__M 0x1F + +#define B_CP_REG_DL_MB_WR_CTR_WORD__B 2 +#define B_CP_REG_DL_MB_WR_CTR_WORD__W 3 +#define B_CP_REG_DL_MB_WR_CTR_WORD__M 0x1C + +#define B_CP_REG_DL_MB_WR_CTR_OBS__B 1 +#define B_CP_REG_DL_MB_WR_CTR_OBS__W 1 +#define B_CP_REG_DL_MB_WR_CTR_OBS__M 0x2 + +#define B_CP_REG_DL_MB_WR_CTR_CTR__B 0 +#define B_CP_REG_DL_MB_WR_CTR_CTR__W 1 +#define B_CP_REG_DL_MB_WR_CTR_CTR__M 0x1 +#define B_CP_REG_DL_MB_WR_CTR_INIT 0x0 + + +#define B_CP_REG_DL_MB_RD_ADDR__A 0x1410052 +#define B_CP_REG_DL_MB_RD_ADDR__W 15 +#define B_CP_REG_DL_MB_RD_ADDR__M 0x7FFF +#define B_CP_REG_DL_MB_RD_ADDR_INIT 0x0 + + +#define B_CP_REG_DL_MB_RD_CTR__A 0x1410053 +#define B_CP_REG_DL_MB_RD_CTR__W 11 +#define B_CP_REG_DL_MB_RD_CTR__M 0x7FF + +#define B_CP_REG_DL_MB_RD_CTR_TEST__B 10 +#define B_CP_REG_DL_MB_RD_CTR_TEST__W 1 +#define B_CP_REG_DL_MB_RD_CTR_TEST__M 0x400 + +#define B_CP_REG_DL_MB_RD_CTR_OFFSET__B 8 +#define B_CP_REG_DL_MB_RD_CTR_OFFSET__W 2 +#define B_CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 + +#define B_CP_REG_DL_MB_RD_CTR_VALID__B 5 +#define B_CP_REG_DL_MB_RD_CTR_VALID__W 3 +#define B_CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 + +#define B_CP_REG_DL_MB_RD_CTR_WORD__B 2 +#define B_CP_REG_DL_MB_RD_CTR_WORD__W 3 +#define B_CP_REG_DL_MB_RD_CTR_WORD__M 0x1C + +#define B_CP_REG_DL_MB_RD_CTR_OBS__B 1 +#define B_CP_REG_DL_MB_RD_CTR_OBS__W 1 +#define B_CP_REG_DL_MB_RD_CTR_OBS__M 0x2 + +#define B_CP_REG_DL_MB_RD_CTR_CTR__B 0 +#define B_CP_REG_DL_MB_RD_CTR_CTR__W 1 +#define B_CP_REG_DL_MB_RD_CTR_CTR__M 0x1 +#define B_CP_REG_DL_MB_RD_CTR_INIT 0x0 + + + +#define B_CP_BR_BUF_RAM__A 0x1420000 + + + +#define B_CP_BR_CPL_RAM__A 0x1430000 + + + +#define B_CP_PB_DL0_RAM__A 0x1440000 + + + +#define B_CP_PB_DL1_RAM__A 0x1450000 + + + +#define B_CP_PB_DL2_RAM__A 0x1460000 + + + + + +#define B_CE_SID 0xA + + + + + +#define B_CE_COMM_EXEC__A 0x1800000 +#define B_CE_COMM_EXEC__W 3 +#define B_CE_COMM_EXEC__M 0x7 +#define B_CE_COMM_EXEC_CTL__B 0 +#define B_CE_COMM_EXEC_CTL__W 3 +#define B_CE_COMM_EXEC_CTL__M 0x7 +#define B_CE_COMM_EXEC_CTL_STOP 0x0 +#define B_CE_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CE_COMM_EXEC_CTL_HOLD 0x2 +#define B_CE_COMM_EXEC_CTL_STEP 0x3 +#define B_CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_CE_COMM_STATE__A 0x1800001 +#define B_CE_COMM_STATE__W 16 +#define B_CE_COMM_STATE__M 0xFFFF +#define B_CE_COMM_MB__A 0x1800002 +#define B_CE_COMM_MB__W 16 +#define B_CE_COMM_MB__M 0xFFFF +#define B_CE_COMM_SERVICE0__A 0x1800003 +#define B_CE_COMM_SERVICE0__W 16 +#define B_CE_COMM_SERVICE0__M 0xFFFF +#define B_CE_COMM_SERVICE1__A 0x1800004 +#define B_CE_COMM_SERVICE1__W 16 +#define B_CE_COMM_SERVICE1__M 0xFFFF +#define B_CE_COMM_INT_STA__A 0x1800007 +#define B_CE_COMM_INT_STA__W 16 +#define B_CE_COMM_INT_STA__M 0xFFFF +#define B_CE_COMM_INT_MSK__A 0x1800008 +#define B_CE_COMM_INT_MSK__W 16 +#define B_CE_COMM_INT_MSK__M 0xFFFF + + + + + + +#define B_CE_REG_COMM_EXEC__A 0x1810000 +#define B_CE_REG_COMM_EXEC__W 3 +#define B_CE_REG_COMM_EXEC__M 0x7 +#define B_CE_REG_COMM_EXEC_CTL__B 0 +#define B_CE_REG_COMM_EXEC_CTL__W 3 +#define B_CE_REG_COMM_EXEC_CTL__M 0x7 +#define B_CE_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CE_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_CE_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define B_CE_REG_COMM_MB__A 0x1810002 +#define B_CE_REG_COMM_MB__W 4 +#define B_CE_REG_COMM_MB__M 0xF +#define B_CE_REG_COMM_MB_CTR__B 0 +#define B_CE_REG_COMM_MB_CTR__W 1 +#define B_CE_REG_COMM_MB_CTR__M 0x1 +#define B_CE_REG_COMM_MB_CTR_OFF 0x0 +#define B_CE_REG_COMM_MB_CTR_ON 0x1 +#define B_CE_REG_COMM_MB_OBS__B 1 +#define B_CE_REG_COMM_MB_OBS__W 1 +#define B_CE_REG_COMM_MB_OBS__M 0x2 +#define B_CE_REG_COMM_MB_OBS_OFF 0x0 +#define B_CE_REG_COMM_MB_OBS_ON 0x2 +#define B_CE_REG_COMM_MB_OBS_SEL__B 2 +#define B_CE_REG_COMM_MB_OBS_SEL__W 2 +#define B_CE_REG_COMM_MB_OBS_SEL__M 0xC +#define B_CE_REG_COMM_MB_OBS_SEL_FI 0x0 +#define B_CE_REG_COMM_MB_OBS_SEL_TP 0x4 +#define B_CE_REG_COMM_MB_OBS_SEL_TI 0x8 +#define B_CE_REG_COMM_MB_OBS_SEL_FR 0x8 + +#define B_CE_REG_COMM_SERVICE0__A 0x1810003 +#define B_CE_REG_COMM_SERVICE0__W 10 +#define B_CE_REG_COMM_SERVICE0__M 0x3FF +#define B_CE_REG_COMM_SERVICE0_FT__B 8 +#define B_CE_REG_COMM_SERVICE0_FT__W 1 +#define B_CE_REG_COMM_SERVICE0_FT__M 0x100 + +#define B_CE_REG_COMM_SERVICE1__A 0x1810004 +#define B_CE_REG_COMM_SERVICE1__W 11 +#define B_CE_REG_COMM_SERVICE1__M 0x7FF + +#define B_CE_REG_COMM_INT_STA__A 0x1810007 +#define B_CE_REG_COMM_INT_STA__W 3 +#define B_CE_REG_COMM_INT_STA__M 0x7 +#define B_CE_REG_COMM_INT_STA_CE_PE__B 0 +#define B_CE_REG_COMM_INT_STA_CE_PE__W 1 +#define B_CE_REG_COMM_INT_STA_CE_PE__M 0x1 +#define B_CE_REG_COMM_INT_STA_CE_IR__B 1 +#define B_CE_REG_COMM_INT_STA_CE_IR__W 1 +#define B_CE_REG_COMM_INT_STA_CE_IR__M 0x2 +#define B_CE_REG_COMM_INT_STA_CE_FI__B 2 +#define B_CE_REG_COMM_INT_STA_CE_FI__W 1 +#define B_CE_REG_COMM_INT_STA_CE_FI__M 0x4 + + +#define B_CE_REG_COMM_INT_MSK__A 0x1810008 +#define B_CE_REG_COMM_INT_MSK__W 3 +#define B_CE_REG_COMM_INT_MSK__M 0x7 +#define B_CE_REG_COMM_INT_MSK_CE_PE__B 0 +#define B_CE_REG_COMM_INT_MSK_CE_PE__W 1 +#define B_CE_REG_COMM_INT_MSK_CE_PE__M 0x1 +#define B_CE_REG_COMM_INT_MSK_CE_IR__B 1 +#define B_CE_REG_COMM_INT_MSK_CE_IR__W 1 +#define B_CE_REG_COMM_INT_MSK_CE_IR__M 0x2 +#define B_CE_REG_COMM_INT_MSK_CE_FI__B 2 +#define B_CE_REG_COMM_INT_MSK_CE_FI__W 1 +#define B_CE_REG_COMM_INT_MSK_CE_FI__M 0x4 + + +#define B_CE_REG_2K__A 0x1810010 +#define B_CE_REG_2K__W 1 +#define B_CE_REG_2K__M 0x1 +#define B_CE_REG_2K_INIT 0x0 + + +#define B_CE_REG_TAPSET__A 0x1810011 +#define B_CE_REG_TAPSET__W 4 +#define B_CE_REG_TAPSET__M 0xF + + + +#define B_CE_REG_TAPSET_MOTION_INIT 0x0 + +#define B_CE_REG_TAPSET_MOTION_NO 0x0 + +#define B_CE_REG_TAPSET_MOTION_LOW 0x1 + +#define B_CE_REG_TAPSET_MOTION_HIGH 0x2 + +#define B_CE_REG_TAPSET_MOTION_HIGH2 0x4 + +#define B_CE_REG_TAPSET_MOTION_UNDEFINED 0x8 + + +#define B_CE_REG_AVG_POW__A 0x1810012 +#define B_CE_REG_AVG_POW__W 8 +#define B_CE_REG_AVG_POW__M 0xFF +#define B_CE_REG_AVG_POW_INIT 0x0 + + +#define B_CE_REG_MAX_POW__A 0x1810013 +#define B_CE_REG_MAX_POW__W 8 +#define B_CE_REG_MAX_POW__M 0xFF +#define B_CE_REG_MAX_POW_INIT 0x0 + + +#define B_CE_REG_ATT__A 0x1810014 +#define B_CE_REG_ATT__W 8 +#define B_CE_REG_ATT__M 0xFF +#define B_CE_REG_ATT_INIT 0x0 + + +#define B_CE_REG_NRED__A 0x1810015 +#define B_CE_REG_NRED__W 6 +#define B_CE_REG_NRED__M 0x3F +#define B_CE_REG_NRED_INIT 0x0 + + +#define B_CE_REG_PU_SIGN__A 0x1810020 +#define B_CE_REG_PU_SIGN__W 1 +#define B_CE_REG_PU_SIGN__M 0x1 +#define B_CE_REG_PU_SIGN_INIT 0x0 + + +#define B_CE_REG_PU_MIX__A 0x1810021 +#define B_CE_REG_PU_MIX__W 1 +#define B_CE_REG_PU_MIX__M 0x1 +#define B_CE_REG_PU_MIX_INIT 0x0 + + +#define B_CE_REG_PB_PILOT_REQ__A 0x1810030 +#define B_CE_REG_PB_PILOT_REQ__W 15 +#define B_CE_REG_PB_PILOT_REQ__M 0x7FFF +#define B_CE_REG_PB_PILOT_REQ_INIT 0x0 +#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 +#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 +#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 +#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 +#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 +#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF + + +#define B_CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 +#define B_CE_REG_PB_PILOT_REQ_VALID__W 1 +#define B_CE_REG_PB_PILOT_REQ_VALID__M 0x1 +#define B_CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 + + +#define B_CE_REG_PB_FREEZE__A 0x1810032 +#define B_CE_REG_PB_FREEZE__W 1 +#define B_CE_REG_PB_FREEZE__M 0x1 +#define B_CE_REG_PB_FREEZE_INIT 0x0 + + +#define B_CE_REG_PB_PILOT_EXP__A 0x1810038 +#define B_CE_REG_PB_PILOT_EXP__W 4 +#define B_CE_REG_PB_PILOT_EXP__M 0xF +#define B_CE_REG_PB_PILOT_EXP_INIT 0x0 + + +#define B_CE_REG_PB_PILOT_REAL__A 0x1810039 +#define B_CE_REG_PB_PILOT_REAL__W 10 +#define B_CE_REG_PB_PILOT_REAL__M 0x3FF +#define B_CE_REG_PB_PILOT_REAL_INIT 0x0 + + +#define B_CE_REG_PB_PILOT_IMAG__A 0x181003A +#define B_CE_REG_PB_PILOT_IMAG__W 10 +#define B_CE_REG_PB_PILOT_IMAG__M 0x3FF +#define B_CE_REG_PB_PILOT_IMAG_INIT 0x0 + + +#define B_CE_REG_PB_SMBNR__A 0x181003B +#define B_CE_REG_PB_SMBNR__W 5 +#define B_CE_REG_PB_SMBNR__M 0x1F +#define B_CE_REG_PB_SMBNR_INIT 0x0 + + +#define B_CE_REG_NE_PILOT_REQ__A 0x1810040 +#define B_CE_REG_NE_PILOT_REQ__W 12 +#define B_CE_REG_NE_PILOT_REQ__M 0xFFF +#define B_CE_REG_NE_PILOT_REQ_INIT 0x0 + + +#define B_CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 +#define B_CE_REG_NE_PILOT_REQ_VALID__W 2 +#define B_CE_REG_NE_PILOT_REQ_VALID__M 0x3 +#define B_CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 +#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 +#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 +#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 +#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 +#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 +#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 + + +#define B_CE_REG_NE_PILOT_DATA__A 0x1810042 +#define B_CE_REG_NE_PILOT_DATA__W 10 +#define B_CE_REG_NE_PILOT_DATA__M 0x3FF +#define B_CE_REG_NE_PILOT_DATA_INIT 0x0 + + +#define B_CE_REG_NE_ERR_SELECT__A 0x1810043 +#define B_CE_REG_NE_ERR_SELECT__W 5 +#define B_CE_REG_NE_ERR_SELECT__M 0x1F +#define B_CE_REG_NE_ERR_SELECT_INIT 0x7 + +#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__B 4 +#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__W 1 +#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__M 0x10 + +#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__B 3 +#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__W 1 +#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__M 0x8 + +#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 +#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 +#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 + +#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 +#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 +#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 + +#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 +#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 +#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 + + +#define B_CE_REG_NE_TD_CAL__A 0x1810044 +#define B_CE_REG_NE_TD_CAL__W 9 +#define B_CE_REG_NE_TD_CAL__M 0x1FF +#define B_CE_REG_NE_TD_CAL_INIT 0x1E8 + + +#define B_CE_REG_NE_FD_CAL__A 0x1810045 +#define B_CE_REG_NE_FD_CAL__W 9 +#define B_CE_REG_NE_FD_CAL__M 0x1FF +#define B_CE_REG_NE_FD_CAL_INIT 0x1D9 + + +#define B_CE_REG_NE_MIXAVG__A 0x1810046 +#define B_CE_REG_NE_MIXAVG__W 3 +#define B_CE_REG_NE_MIXAVG__M 0x7 +#define B_CE_REG_NE_MIXAVG_INIT 0x6 + + +#define B_CE_REG_NE_NUPD_OFS__A 0x1810047 +#define B_CE_REG_NE_NUPD_OFS__W 4 +#define B_CE_REG_NE_NUPD_OFS__M 0xF +#define B_CE_REG_NE_NUPD_OFS_INIT 0x4 + + +#define B_CE_REG_NE_TD_POW__A 0x1810048 +#define B_CE_REG_NE_TD_POW__W 15 +#define B_CE_REG_NE_TD_POW__M 0x7FFF +#define B_CE_REG_NE_TD_POW_INIT 0x0 + +#define B_CE_REG_NE_TD_POW_EXPONENT__B 10 +#define B_CE_REG_NE_TD_POW_EXPONENT__W 5 +#define B_CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 + +#define B_CE_REG_NE_TD_POW_MANTISSA__B 0 +#define B_CE_REG_NE_TD_POW_MANTISSA__W 10 +#define B_CE_REG_NE_TD_POW_MANTISSA__M 0x3FF + + +#define B_CE_REG_NE_FD_POW__A 0x1810049 +#define B_CE_REG_NE_FD_POW__W 15 +#define B_CE_REG_NE_FD_POW__M 0x7FFF +#define B_CE_REG_NE_FD_POW_INIT 0x0 + +#define B_CE_REG_NE_FD_POW_EXPONENT__B 10 +#define B_CE_REG_NE_FD_POW_EXPONENT__W 5 +#define B_CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 + +#define B_CE_REG_NE_FD_POW_MANTISSA__B 0 +#define B_CE_REG_NE_FD_POW_MANTISSA__W 10 +#define B_CE_REG_NE_FD_POW_MANTISSA__M 0x3FF + + +#define B_CE_REG_NE_NEXP_AVG__A 0x181004A +#define B_CE_REG_NE_NEXP_AVG__W 8 +#define B_CE_REG_NE_NEXP_AVG__M 0xFF +#define B_CE_REG_NE_NEXP_AVG_INIT 0x0 + + +#define B_CE_REG_NE_OFFSET__A 0x181004B +#define B_CE_REG_NE_OFFSET__W 9 +#define B_CE_REG_NE_OFFSET__M 0x1FF +#define B_CE_REG_NE_OFFSET_INIT 0x0 + + +#define B_CE_REG_NE_NUPD_TRH__A 0x181004C +#define B_CE_REG_NE_NUPD_TRH__W 5 +#define B_CE_REG_NE_NUPD_TRH__M 0x1F +#define B_CE_REG_NE_NUPD_TRH_INIT 0x14 + + +#define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 +#define B_CE_REG_PE_NEXP_OFFS__W 8 +#define B_CE_REG_PE_NEXP_OFFS__M 0xFF +#define B_CE_REG_PE_NEXP_OFFS_INIT 0x0 + + +#define B_CE_REG_PE_TIMESHIFT__A 0x1810051 +#define B_CE_REG_PE_TIMESHIFT__W 14 +#define B_CE_REG_PE_TIMESHIFT__M 0x3FFF +#define B_CE_REG_PE_TIMESHIFT_INIT 0x0 + + +#define B_CE_REG_PE_DIF_REAL_L__A 0x1810052 +#define B_CE_REG_PE_DIF_REAL_L__W 16 +#define B_CE_REG_PE_DIF_REAL_L__M 0xFFFF +#define B_CE_REG_PE_DIF_REAL_L_INIT 0x0 + + +#define B_CE_REG_PE_DIF_IMAG_L__A 0x1810053 +#define B_CE_REG_PE_DIF_IMAG_L__W 16 +#define B_CE_REG_PE_DIF_IMAG_L__M 0xFFFF +#define B_CE_REG_PE_DIF_IMAG_L_INIT 0x0 + + +#define B_CE_REG_PE_DIF_REAL_R__A 0x1810054 +#define B_CE_REG_PE_DIF_REAL_R__W 16 +#define B_CE_REG_PE_DIF_REAL_R__M 0xFFFF +#define B_CE_REG_PE_DIF_REAL_R_INIT 0x0 + + +#define B_CE_REG_PE_DIF_IMAG_R__A 0x1810055 +#define B_CE_REG_PE_DIF_IMAG_R__W 16 +#define B_CE_REG_PE_DIF_IMAG_R__M 0xFFFF +#define B_CE_REG_PE_DIF_IMAG_R_INIT 0x0 + + +#define B_CE_REG_PE_ABS_REAL_L__A 0x1810056 +#define B_CE_REG_PE_ABS_REAL_L__W 16 +#define B_CE_REG_PE_ABS_REAL_L__M 0xFFFF +#define B_CE_REG_PE_ABS_REAL_L_INIT 0x0 + + +#define B_CE_REG_PE_ABS_IMAG_L__A 0x1810057 +#define B_CE_REG_PE_ABS_IMAG_L__W 16 +#define B_CE_REG_PE_ABS_IMAG_L__M 0xFFFF +#define B_CE_REG_PE_ABS_IMAG_L_INIT 0x0 + + +#define B_CE_REG_PE_ABS_REAL_R__A 0x1810058 +#define B_CE_REG_PE_ABS_REAL_R__W 16 +#define B_CE_REG_PE_ABS_REAL_R__M 0xFFFF +#define B_CE_REG_PE_ABS_REAL_R_INIT 0x0 + + +#define B_CE_REG_PE_ABS_IMAG_R__A 0x1810059 +#define B_CE_REG_PE_ABS_IMAG_R__W 16 +#define B_CE_REG_PE_ABS_IMAG_R__M 0xFFFF +#define B_CE_REG_PE_ABS_IMAG_R_INIT 0x0 + + +#define B_CE_REG_PE_ABS_EXP_L__A 0x181005A +#define B_CE_REG_PE_ABS_EXP_L__W 5 +#define B_CE_REG_PE_ABS_EXP_L__M 0x1F +#define B_CE_REG_PE_ABS_EXP_L_INIT 0x0 + + +#define B_CE_REG_PE_ABS_EXP_R__A 0x181005B +#define B_CE_REG_PE_ABS_EXP_R__W 5 +#define B_CE_REG_PE_ABS_EXP_R__M 0x1F +#define B_CE_REG_PE_ABS_EXP_R_INIT 0x0 + + +#define B_CE_REG_TP_UPDATE_MODE__A 0x1810060 +#define B_CE_REG_TP_UPDATE_MODE__W 1 +#define B_CE_REG_TP_UPDATE_MODE__M 0x1 +#define B_CE_REG_TP_UPDATE_MODE_INIT 0x0 + + +#define B_CE_REG_TP_LMS_TAP_ON__A 0x1810061 +#define B_CE_REG_TP_LMS_TAP_ON__W 1 +#define B_CE_REG_TP_LMS_TAP_ON__M 0x1 + +#define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064 +#define B_CE_REG_TP_A0_TAP_NEW__W 10 +#define B_CE_REG_TP_A0_TAP_NEW__M 0x3FF + +#define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 +#define B_CE_REG_TP_A0_TAP_NEW_VALID__W 1 +#define B_CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 + +#define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 +#define B_CE_REG_TP_A0_MU_LMS_STEP__W 5 +#define B_CE_REG_TP_A0_MU_LMS_STEP__M 0x1F + +#define B_CE_REG_TP_A0_TAP_CURR__A 0x1810067 +#define B_CE_REG_TP_A0_TAP_CURR__W 10 +#define B_CE_REG_TP_A0_TAP_CURR__M 0x3FF + +#define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068 +#define B_CE_REG_TP_A1_TAP_NEW__W 10 +#define B_CE_REG_TP_A1_TAP_NEW__M 0x3FF + +#define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 +#define B_CE_REG_TP_A1_TAP_NEW_VALID__W 1 +#define B_CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 + +#define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A +#define B_CE_REG_TP_A1_MU_LMS_STEP__W 5 +#define B_CE_REG_TP_A1_MU_LMS_STEP__M 0x1F + +#define B_CE_REG_TP_A1_TAP_CURR__A 0x181006B +#define B_CE_REG_TP_A1_TAP_CURR__W 10 +#define B_CE_REG_TP_A1_TAP_CURR__M 0x3FF + +#define B_CE_REG_TP_DOPP_ENERGY__A 0x181006C +#define B_CE_REG_TP_DOPP_ENERGY__W 15 +#define B_CE_REG_TP_DOPP_ENERGY__M 0x7FFF +#define B_CE_REG_TP_DOPP_ENERGY_INIT 0x0 + +#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 +#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 +#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 + +#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 +#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 +#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF + + +#define B_CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D +#define B_CE_REG_TP_DOPP_DIFF_ENERGY__W 15 +#define B_CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 + +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 + +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF + + +#define B_CE_REG_TP_A0_TAP_ENERGY__A 0x181006E +#define B_CE_REG_TP_A0_TAP_ENERGY__W 15 +#define B_CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF +#define B_CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 + +#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 +#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 +#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 + +#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 +#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 +#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF + + +#define B_CE_REG_TP_A1_TAP_ENERGY__A 0x181006F +#define B_CE_REG_TP_A1_TAP_ENERGY__W 15 +#define B_CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF +#define B_CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 + +#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 +#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 +#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 + +#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 +#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 +#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF + + +#define B_CE_REG_TI_SYM_CNT__A 0x1810072 +#define B_CE_REG_TI_SYM_CNT__W 6 +#define B_CE_REG_TI_SYM_CNT__M 0x3F +#define B_CE_REG_TI_SYM_CNT_INIT 0x0 + + +#define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 +#define B_CE_REG_TI_PHN_ENABLE__W 1 +#define B_CE_REG_TI_PHN_ENABLE__M 0x1 +#define B_CE_REG_TI_PHN_ENABLE_INIT 0x0 + + +#define B_CE_REG_TI_SHIFT__A 0x1810074 +#define B_CE_REG_TI_SHIFT__W 2 +#define B_CE_REG_TI_SHIFT__M 0x3 +#define B_CE_REG_TI_SHIFT_INIT 0x0 + + +#define B_CE_REG_TI_SLOW__A 0x1810075 +#define B_CE_REG_TI_SLOW__W 1 +#define B_CE_REG_TI_SLOW__M 0x1 +#define B_CE_REG_TI_SLOW_INIT 0x0 + + +#define B_CE_REG_TI_MGAIN__A 0x1810076 +#define B_CE_REG_TI_MGAIN__W 8 +#define B_CE_REG_TI_MGAIN__M 0xFF +#define B_CE_REG_TI_MGAIN_INIT 0x0 + + +#define B_CE_REG_TI_ACCU1__A 0x1810077 +#define B_CE_REG_TI_ACCU1__W 8 +#define B_CE_REG_TI_ACCU1__M 0xFF +#define B_CE_REG_TI_ACCU1_INIT 0x0 + + +#define B_CE_REG_NI_PER_LEFT__A 0x18100B0 +#define B_CE_REG_NI_PER_LEFT__W 5 +#define B_CE_REG_NI_PER_LEFT__M 0x1F +#define B_CE_REG_NI_PER_LEFT_INIT 0xE + + +#define B_CE_REG_NI_PER_RIGHT__A 0x18100B1 +#define B_CE_REG_NI_PER_RIGHT__W 5 +#define B_CE_REG_NI_PER_RIGHT__M 0x1F +#define B_CE_REG_NI_PER_RIGHT_INIT 0x7 + + +#define B_CE_REG_NI_POS_LR__A 0x18100B2 +#define B_CE_REG_NI_POS_LR__W 9 +#define B_CE_REG_NI_POS_LR__M 0x1FF +#define B_CE_REG_NI_POS_LR_INIT 0xA0 + + +#define B_CE_REG_FI_SHT_INCR__A 0x1810090 +#define B_CE_REG_FI_SHT_INCR__W 7 +#define B_CE_REG_FI_SHT_INCR__M 0x7F +#define B_CE_REG_FI_SHT_INCR_INIT 0x9 + + +#define B_CE_REG_FI_EXP_NORM__A 0x1810091 +#define B_CE_REG_FI_EXP_NORM__W 4 +#define B_CE_REG_FI_EXP_NORM__M 0xF +#define B_CE_REG_FI_EXP_NORM_INIT 0x4 + + +#define B_CE_REG_FI_SUPR_VAL__A 0x1810092 +#define B_CE_REG_FI_SUPR_VAL__W 1 +#define B_CE_REG_FI_SUPR_VAL__M 0x1 +#define B_CE_REG_FI_SUPR_VAL_INIT 0x1 + + +#define B_CE_REG_IR_INPUTSEL__A 0x18100A0 +#define B_CE_REG_IR_INPUTSEL__W 1 +#define B_CE_REG_IR_INPUTSEL__M 0x1 +#define B_CE_REG_IR_INPUTSEL_INIT 0x0 + + +#define B_CE_REG_IR_STARTPOS__A 0x18100A1 +#define B_CE_REG_IR_STARTPOS__W 8 +#define B_CE_REG_IR_STARTPOS__M 0xFF +#define B_CE_REG_IR_STARTPOS_INIT 0x0 + + +#define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 +#define B_CE_REG_IR_NEXP_THRES__W 8 +#define B_CE_REG_IR_NEXP_THRES__M 0xFF +#define B_CE_REG_IR_NEXP_THRES_INIT 0x0 + + +#define B_CE_REG_IR_LENGTH__A 0x18100A3 +#define B_CE_REG_IR_LENGTH__W 4 +#define B_CE_REG_IR_LENGTH__M 0xF +#define B_CE_REG_IR_LENGTH_INIT 0x0 + + +#define B_CE_REG_IR_FREQ__A 0x18100A4 +#define B_CE_REG_IR_FREQ__W 11 +#define B_CE_REG_IR_FREQ__M 0x7FF +#define B_CE_REG_IR_FREQ_INIT 0x0 + + +#define B_CE_REG_IR_FREQINC__A 0x18100A5 +#define B_CE_REG_IR_FREQINC__W 11 +#define B_CE_REG_IR_FREQINC__M 0x7FF +#define B_CE_REG_IR_FREQINC_INIT 0x0 + + +#define B_CE_REG_IR_KAISINC__A 0x18100A6 +#define B_CE_REG_IR_KAISINC__W 15 +#define B_CE_REG_IR_KAISINC__M 0x7FFF +#define B_CE_REG_IR_KAISINC_INIT 0x0 + + +#define B_CE_REG_IR_CTL__A 0x18100A7 +#define B_CE_REG_IR_CTL__W 3 +#define B_CE_REG_IR_CTL__M 0x7 +#define B_CE_REG_IR_CTL_INIT 0x0 + + +#define B_CE_REG_IR_REAL__A 0x18100A8 +#define B_CE_REG_IR_REAL__W 16 +#define B_CE_REG_IR_REAL__M 0xFFFF +#define B_CE_REG_IR_REAL_INIT 0x0 + + +#define B_CE_REG_IR_IMAG__A 0x18100A9 +#define B_CE_REG_IR_IMAG__W 16 +#define B_CE_REG_IR_IMAG__M 0xFFFF +#define B_CE_REG_IR_IMAG_INIT 0x0 + + +#define B_CE_REG_IR_INDEX__A 0x18100AA +#define B_CE_REG_IR_INDEX__W 12 +#define B_CE_REG_IR_INDEX__M 0xFFF +#define B_CE_REG_IR_INDEX_INIT 0x0 + + + + +#define B_CE_REG_FR_COMM_EXEC__A 0x1820000 +#define B_CE_REG_FR_COMM_EXEC__W 1 +#define B_CE_REG_FR_COMM_EXEC__M 0x1 + +#define B_CE_REG_FR_TREAL00__A 0x1820010 +#define B_CE_REG_FR_TREAL00__W 11 +#define B_CE_REG_FR_TREAL00__M 0x7FF +#define B_CE_REG_FR_TREAL00_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG00__A 0x1820011 +#define B_CE_REG_FR_TIMAG00__W 11 +#define B_CE_REG_FR_TIMAG00__M 0x7FF +#define B_CE_REG_FR_TIMAG00_INIT 0x0 + + +#define B_CE_REG_FR_TREAL01__A 0x1820012 +#define B_CE_REG_FR_TREAL01__W 11 +#define B_CE_REG_FR_TREAL01__M 0x7FF +#define B_CE_REG_FR_TREAL01_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG01__A 0x1820013 +#define B_CE_REG_FR_TIMAG01__W 11 +#define B_CE_REG_FR_TIMAG01__M 0x7FF +#define B_CE_REG_FR_TIMAG01_INIT 0x0 + + +#define B_CE_REG_FR_TREAL02__A 0x1820014 +#define B_CE_REG_FR_TREAL02__W 11 +#define B_CE_REG_FR_TREAL02__M 0x7FF +#define B_CE_REG_FR_TREAL02_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG02__A 0x1820015 +#define B_CE_REG_FR_TIMAG02__W 11 +#define B_CE_REG_FR_TIMAG02__M 0x7FF +#define B_CE_REG_FR_TIMAG02_INIT 0x0 + + +#define B_CE_REG_FR_TREAL03__A 0x1820016 +#define B_CE_REG_FR_TREAL03__W 11 +#define B_CE_REG_FR_TREAL03__M 0x7FF +#define B_CE_REG_FR_TREAL03_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG03__A 0x1820017 +#define B_CE_REG_FR_TIMAG03__W 11 +#define B_CE_REG_FR_TIMAG03__M 0x7FF +#define B_CE_REG_FR_TIMAG03_INIT 0x0 + + +#define B_CE_REG_FR_TREAL04__A 0x1820018 +#define B_CE_REG_FR_TREAL04__W 11 +#define B_CE_REG_FR_TREAL04__M 0x7FF +#define B_CE_REG_FR_TREAL04_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG04__A 0x1820019 +#define B_CE_REG_FR_TIMAG04__W 11 +#define B_CE_REG_FR_TIMAG04__M 0x7FF +#define B_CE_REG_FR_TIMAG04_INIT 0x0 + + +#define B_CE_REG_FR_TREAL05__A 0x182001A +#define B_CE_REG_FR_TREAL05__W 11 +#define B_CE_REG_FR_TREAL05__M 0x7FF +#define B_CE_REG_FR_TREAL05_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG05__A 0x182001B +#define B_CE_REG_FR_TIMAG05__W 11 +#define B_CE_REG_FR_TIMAG05__M 0x7FF +#define B_CE_REG_FR_TIMAG05_INIT 0x0 + + +#define B_CE_REG_FR_TREAL06__A 0x182001C +#define B_CE_REG_FR_TREAL06__W 11 +#define B_CE_REG_FR_TREAL06__M 0x7FF +#define B_CE_REG_FR_TREAL06_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG06__A 0x182001D +#define B_CE_REG_FR_TIMAG06__W 11 +#define B_CE_REG_FR_TIMAG06__M 0x7FF +#define B_CE_REG_FR_TIMAG06_INIT 0x0 + + +#define B_CE_REG_FR_TREAL07__A 0x182001E +#define B_CE_REG_FR_TREAL07__W 11 +#define B_CE_REG_FR_TREAL07__M 0x7FF +#define B_CE_REG_FR_TREAL07_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG07__A 0x182001F +#define B_CE_REG_FR_TIMAG07__W 11 +#define B_CE_REG_FR_TIMAG07__M 0x7FF +#define B_CE_REG_FR_TIMAG07_INIT 0x0 + + +#define B_CE_REG_FR_TREAL08__A 0x1820020 +#define B_CE_REG_FR_TREAL08__W 11 +#define B_CE_REG_FR_TREAL08__M 0x7FF +#define B_CE_REG_FR_TREAL08_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG08__A 0x1820021 +#define B_CE_REG_FR_TIMAG08__W 11 +#define B_CE_REG_FR_TIMAG08__M 0x7FF +#define B_CE_REG_FR_TIMAG08_INIT 0x0 + + +#define B_CE_REG_FR_TREAL09__A 0x1820022 +#define B_CE_REG_FR_TREAL09__W 11 +#define B_CE_REG_FR_TREAL09__M 0x7FF +#define B_CE_REG_FR_TREAL09_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG09__A 0x1820023 +#define B_CE_REG_FR_TIMAG09__W 11 +#define B_CE_REG_FR_TIMAG09__M 0x7FF +#define B_CE_REG_FR_TIMAG09_INIT 0x0 + + +#define B_CE_REG_FR_TREAL10__A 0x1820024 +#define B_CE_REG_FR_TREAL10__W 11 +#define B_CE_REG_FR_TREAL10__M 0x7FF +#define B_CE_REG_FR_TREAL10_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG10__A 0x1820025 +#define B_CE_REG_FR_TIMAG10__W 11 +#define B_CE_REG_FR_TIMAG10__M 0x7FF +#define B_CE_REG_FR_TIMAG10_INIT 0x0 + + +#define B_CE_REG_FR_TREAL11__A 0x1820026 +#define B_CE_REG_FR_TREAL11__W 11 +#define B_CE_REG_FR_TREAL11__M 0x7FF +#define B_CE_REG_FR_TREAL11_INIT 0x52 + + +#define B_CE_REG_FR_TIMAG11__A 0x1820027 +#define B_CE_REG_FR_TIMAG11__W 11 +#define B_CE_REG_FR_TIMAG11__M 0x7FF +#define B_CE_REG_FR_TIMAG11_INIT 0x0 + + +#define B_CE_REG_FR_MID_TAP__A 0x1820028 +#define B_CE_REG_FR_MID_TAP__W 11 +#define B_CE_REG_FR_MID_TAP__M 0x7FF +#define B_CE_REG_FR_MID_TAP_INIT 0x51 + + +#define B_CE_REG_FR_SQS_G00__A 0x1820029 +#define B_CE_REG_FR_SQS_G00__W 8 +#define B_CE_REG_FR_SQS_G00__M 0xFF +#define B_CE_REG_FR_SQS_G00_INIT 0xB + + +#define B_CE_REG_FR_SQS_G01__A 0x182002A +#define B_CE_REG_FR_SQS_G01__W 8 +#define B_CE_REG_FR_SQS_G01__M 0xFF +#define B_CE_REG_FR_SQS_G01_INIT 0xB + + +#define B_CE_REG_FR_SQS_G02__A 0x182002B +#define B_CE_REG_FR_SQS_G02__W 8 +#define B_CE_REG_FR_SQS_G02__M 0xFF +#define B_CE_REG_FR_SQS_G02_INIT 0xB + + +#define B_CE_REG_FR_SQS_G03__A 0x182002C +#define B_CE_REG_FR_SQS_G03__W 8 +#define B_CE_REG_FR_SQS_G03__M 0xFF +#define B_CE_REG_FR_SQS_G03_INIT 0xB + + +#define B_CE_REG_FR_SQS_G04__A 0x182002D +#define B_CE_REG_FR_SQS_G04__W 8 +#define B_CE_REG_FR_SQS_G04__M 0xFF +#define B_CE_REG_FR_SQS_G04_INIT 0xB + + +#define B_CE_REG_FR_SQS_G05__A 0x182002E +#define B_CE_REG_FR_SQS_G05__W 8 +#define B_CE_REG_FR_SQS_G05__M 0xFF +#define B_CE_REG_FR_SQS_G05_INIT 0xB + + +#define B_CE_REG_FR_SQS_G06__A 0x182002F +#define B_CE_REG_FR_SQS_G06__W 8 +#define B_CE_REG_FR_SQS_G06__M 0xFF +#define B_CE_REG_FR_SQS_G06_INIT 0xB + + +#define B_CE_REG_FR_SQS_G07__A 0x1820030 +#define B_CE_REG_FR_SQS_G07__W 8 +#define B_CE_REG_FR_SQS_G07__M 0xFF +#define B_CE_REG_FR_SQS_G07_INIT 0xB + + +#define B_CE_REG_FR_SQS_G08__A 0x1820031 +#define B_CE_REG_FR_SQS_G08__W 8 +#define B_CE_REG_FR_SQS_G08__M 0xFF +#define B_CE_REG_FR_SQS_G08_INIT 0xB + + +#define B_CE_REG_FR_SQS_G09__A 0x1820032 +#define B_CE_REG_FR_SQS_G09__W 8 +#define B_CE_REG_FR_SQS_G09__M 0xFF +#define B_CE_REG_FR_SQS_G09_INIT 0xB + + +#define B_CE_REG_FR_SQS_G10__A 0x1820033 +#define B_CE_REG_FR_SQS_G10__W 8 +#define B_CE_REG_FR_SQS_G10__M 0xFF +#define B_CE_REG_FR_SQS_G10_INIT 0xB + + +#define B_CE_REG_FR_SQS_G11__A 0x1820034 +#define B_CE_REG_FR_SQS_G11__W 8 +#define B_CE_REG_FR_SQS_G11__M 0xFF +#define B_CE_REG_FR_SQS_G11_INIT 0xB + + +#define B_CE_REG_FR_SQS_G12__A 0x1820035 +#define B_CE_REG_FR_SQS_G12__W 8 +#define B_CE_REG_FR_SQS_G12__M 0xFF +#define B_CE_REG_FR_SQS_G12_INIT 0x5 + + +#define B_CE_REG_FR_RIO_G00__A 0x1820036 +#define B_CE_REG_FR_RIO_G00__W 9 +#define B_CE_REG_FR_RIO_G00__M 0x1FF +#define B_CE_REG_FR_RIO_G00_INIT 0x1FF + + +#define B_CE_REG_FR_RIO_G01__A 0x1820037 +#define B_CE_REG_FR_RIO_G01__W 9 +#define B_CE_REG_FR_RIO_G01__M 0x1FF +#define B_CE_REG_FR_RIO_G01_INIT 0x190 + + +#define B_CE_REG_FR_RIO_G02__A 0x1820038 +#define B_CE_REG_FR_RIO_G02__W 9 +#define B_CE_REG_FR_RIO_G02__M 0x1FF +#define B_CE_REG_FR_RIO_G02_INIT 0x10B + + +#define B_CE_REG_FR_RIO_G03__A 0x1820039 +#define B_CE_REG_FR_RIO_G03__W 9 +#define B_CE_REG_FR_RIO_G03__M 0x1FF +#define B_CE_REG_FR_RIO_G03_INIT 0xC8 + + +#define B_CE_REG_FR_RIO_G04__A 0x182003A +#define B_CE_REG_FR_RIO_G04__W 9 +#define B_CE_REG_FR_RIO_G04__M 0x1FF +#define B_CE_REG_FR_RIO_G04_INIT 0xA0 + + +#define B_CE_REG_FR_RIO_G05__A 0x182003B +#define B_CE_REG_FR_RIO_G05__W 9 +#define B_CE_REG_FR_RIO_G05__M 0x1FF +#define B_CE_REG_FR_RIO_G05_INIT 0x85 + + +#define B_CE_REG_FR_RIO_G06__A 0x182003C +#define B_CE_REG_FR_RIO_G06__W 9 +#define B_CE_REG_FR_RIO_G06__M 0x1FF +#define B_CE_REG_FR_RIO_G06_INIT 0x72 + + +#define B_CE_REG_FR_RIO_G07__A 0x182003D +#define B_CE_REG_FR_RIO_G07__W 9 +#define B_CE_REG_FR_RIO_G07__M 0x1FF +#define B_CE_REG_FR_RIO_G07_INIT 0x64 + + +#define B_CE_REG_FR_RIO_G08__A 0x182003E +#define B_CE_REG_FR_RIO_G08__W 9 +#define B_CE_REG_FR_RIO_G08__M 0x1FF +#define B_CE_REG_FR_RIO_G08_INIT 0x59 + + +#define B_CE_REG_FR_RIO_G09__A 0x182003F +#define B_CE_REG_FR_RIO_G09__W 9 +#define B_CE_REG_FR_RIO_G09__M 0x1FF +#define B_CE_REG_FR_RIO_G09_INIT 0x50 + + +#define B_CE_REG_FR_RIO_G10__A 0x1820040 +#define B_CE_REG_FR_RIO_G10__W 9 +#define B_CE_REG_FR_RIO_G10__M 0x1FF +#define B_CE_REG_FR_RIO_G10_INIT 0x49 + + +#define B_CE_REG_FR_MODE__A 0x1820041 +#define B_CE_REG_FR_MODE__W 9 +#define B_CE_REG_FR_MODE__M 0x1FF + +#define B_CE_REG_FR_MODE_UPDATE_ENABLE__B 0 +#define B_CE_REG_FR_MODE_UPDATE_ENABLE__W 1 +#define B_CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 + +#define B_CE_REG_FR_MODE_ERROR_SHIFT__B 1 +#define B_CE_REG_FR_MODE_ERROR_SHIFT__W 1 +#define B_CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 + +#define B_CE_REG_FR_MODE_NEXP_UPDATE__B 2 +#define B_CE_REG_FR_MODE_NEXP_UPDATE__W 1 +#define B_CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 + +#define B_CE_REG_FR_MODE_MANUAL_SHIFT__B 3 +#define B_CE_REG_FR_MODE_MANUAL_SHIFT__W 1 +#define B_CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 + +#define B_CE_REG_FR_MODE_SQUASH_MODE__B 4 +#define B_CE_REG_FR_MODE_SQUASH_MODE__W 1 +#define B_CE_REG_FR_MODE_SQUASH_MODE__M 0x10 + +#define B_CE_REG_FR_MODE_UPDATE_MODE__B 5 +#define B_CE_REG_FR_MODE_UPDATE_MODE__W 1 +#define B_CE_REG_FR_MODE_UPDATE_MODE__M 0x20 + +#define B_CE_REG_FR_MODE_MID_MODE__B 6 +#define B_CE_REG_FR_MODE_MID_MODE__W 1 +#define B_CE_REG_FR_MODE_MID_MODE__M 0x40 + +#define B_CE_REG_FR_MODE_NOISE_MODE__B 7 +#define B_CE_REG_FR_MODE_NOISE_MODE__W 1 +#define B_CE_REG_FR_MODE_NOISE_MODE__M 0x80 + +#define B_CE_REG_FR_MODE_NOTCH_MODE__B 8 +#define B_CE_REG_FR_MODE_NOTCH_MODE__W 1 +#define B_CE_REG_FR_MODE_NOTCH_MODE__M 0x100 +#define B_CE_REG_FR_MODE_INIT 0xDE + + +#define B_CE_REG_FR_SQS_TRH__A 0x1820042 +#define B_CE_REG_FR_SQS_TRH__W 8 +#define B_CE_REG_FR_SQS_TRH__M 0xFF +#define B_CE_REG_FR_SQS_TRH_INIT 0x80 + + +#define B_CE_REG_FR_RIO_GAIN__A 0x1820043 +#define B_CE_REG_FR_RIO_GAIN__W 3 +#define B_CE_REG_FR_RIO_GAIN__M 0x7 +#define B_CE_REG_FR_RIO_GAIN_INIT 0x2 + + +#define B_CE_REG_FR_BYPASS__A 0x1820044 +#define B_CE_REG_FR_BYPASS__W 10 +#define B_CE_REG_FR_BYPASS__M 0x3FF + +#define B_CE_REG_FR_BYPASS_RUN_IN__B 0 +#define B_CE_REG_FR_BYPASS_RUN_IN__W 4 +#define B_CE_REG_FR_BYPASS_RUN_IN__M 0xF + +#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 +#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 +#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 + +#define B_CE_REG_FR_BYPASS_TOTAL__B 9 +#define B_CE_REG_FR_BYPASS_TOTAL__W 1 +#define B_CE_REG_FR_BYPASS_TOTAL__M 0x200 +#define B_CE_REG_FR_BYPASS_INIT 0x13B + + +#define B_CE_REG_FR_PM_SET__A 0x1820045 +#define B_CE_REG_FR_PM_SET__W 4 +#define B_CE_REG_FR_PM_SET__M 0xF +#define B_CE_REG_FR_PM_SET_INIT 0x4 + + +#define B_CE_REG_FR_ERR_SH__A 0x1820046 +#define B_CE_REG_FR_ERR_SH__W 4 +#define B_CE_REG_FR_ERR_SH__M 0xF +#define B_CE_REG_FR_ERR_SH_INIT 0x4 + + +#define B_CE_REG_FR_MAN_SH__A 0x1820047 +#define B_CE_REG_FR_MAN_SH__W 4 +#define B_CE_REG_FR_MAN_SH__M 0xF +#define B_CE_REG_FR_MAN_SH_INIT 0x7 + + +#define B_CE_REG_FR_TAP_SH__A 0x1820048 +#define B_CE_REG_FR_TAP_SH__W 3 +#define B_CE_REG_FR_TAP_SH__M 0x7 +#define B_CE_REG_FR_TAP_SH_INIT 0x3 + + +#define B_CE_REG_FR_CLIP__A 0x1820049 +#define B_CE_REG_FR_CLIP__W 9 +#define B_CE_REG_FR_CLIP__M 0x1FF +#define B_CE_REG_FR_CLIP_INIT 0x49 + + +#define B_CE_REG_FR_LEAK_UPD__A 0x182004A +#define B_CE_REG_FR_LEAK_UPD__W 3 +#define B_CE_REG_FR_LEAK_UPD__M 0x7 +#define B_CE_REG_FR_LEAK_UPD_INIT 0x1 + + +#define B_CE_REG_FR_LEAK_SH__A 0x182004B +#define B_CE_REG_FR_LEAK_SH__W 3 +#define B_CE_REG_FR_LEAK_SH__M 0x7 +#define B_CE_REG_FR_LEAK_SH_INIT 0x1 + + + +#define B_CE_PB_RAM__A 0x1830000 + + + +#define B_CE_NE_RAM__A 0x1840000 + + + + + +#define B_EQ_SID 0xE + + + + + +#define B_EQ_COMM_EXEC__A 0x1C00000 +#define B_EQ_COMM_EXEC__W 3 +#define B_EQ_COMM_EXEC__M 0x7 +#define B_EQ_COMM_EXEC_CTL__B 0 +#define B_EQ_COMM_EXEC_CTL__W 3 +#define B_EQ_COMM_EXEC_CTL__M 0x7 +#define B_EQ_COMM_EXEC_CTL_STOP 0x0 +#define B_EQ_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EQ_COMM_EXEC_CTL_HOLD 0x2 +#define B_EQ_COMM_EXEC_CTL_STEP 0x3 +#define B_EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_EQ_COMM_STATE__A 0x1C00001 +#define B_EQ_COMM_STATE__W 16 +#define B_EQ_COMM_STATE__M 0xFFFF +#define B_EQ_COMM_MB__A 0x1C00002 +#define B_EQ_COMM_MB__W 16 +#define B_EQ_COMM_MB__M 0xFFFF +#define B_EQ_COMM_SERVICE0__A 0x1C00003 +#define B_EQ_COMM_SERVICE0__W 16 +#define B_EQ_COMM_SERVICE0__M 0xFFFF +#define B_EQ_COMM_SERVICE1__A 0x1C00004 +#define B_EQ_COMM_SERVICE1__W 16 +#define B_EQ_COMM_SERVICE1__M 0xFFFF +#define B_EQ_COMM_INT_STA__A 0x1C00007 +#define B_EQ_COMM_INT_STA__W 16 +#define B_EQ_COMM_INT_STA__M 0xFFFF +#define B_EQ_COMM_INT_MSK__A 0x1C00008 +#define B_EQ_COMM_INT_MSK__W 16 +#define B_EQ_COMM_INT_MSK__M 0xFFFF + + + + + + +#define B_EQ_REG_COMM_EXEC__A 0x1C10000 +#define B_EQ_REG_COMM_EXEC__W 3 +#define B_EQ_REG_COMM_EXEC__M 0x7 +#define B_EQ_REG_COMM_EXEC_CTL__B 0 +#define B_EQ_REG_COMM_EXEC_CTL__W 3 +#define B_EQ_REG_COMM_EXEC_CTL__M 0x7 +#define B_EQ_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EQ_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_EQ_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_EQ_REG_COMM_STATE__A 0x1C10001 +#define B_EQ_REG_COMM_STATE__W 4 +#define B_EQ_REG_COMM_STATE__M 0xF + +#define B_EQ_REG_COMM_MB__A 0x1C10002 +#define B_EQ_REG_COMM_MB__W 6 +#define B_EQ_REG_COMM_MB__M 0x3F +#define B_EQ_REG_COMM_MB_CTR__B 0 +#define B_EQ_REG_COMM_MB_CTR__W 1 +#define B_EQ_REG_COMM_MB_CTR__M 0x1 +#define B_EQ_REG_COMM_MB_CTR_OFF 0x0 +#define B_EQ_REG_COMM_MB_CTR_ON 0x1 +#define B_EQ_REG_COMM_MB_OBS__B 1 +#define B_EQ_REG_COMM_MB_OBS__W 1 +#define B_EQ_REG_COMM_MB_OBS__M 0x2 +#define B_EQ_REG_COMM_MB_OBS_OFF 0x0 +#define B_EQ_REG_COMM_MB_OBS_ON 0x2 +#define B_EQ_REG_COMM_MB_CTR_MUX__B 2 +#define B_EQ_REG_COMM_MB_CTR_MUX__W 2 +#define B_EQ_REG_COMM_MB_CTR_MUX__M 0xC +#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 +#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 +#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 +#define B_EQ_REG_COMM_MB_OBS_MUX__B 4 +#define B_EQ_REG_COMM_MB_OBS_MUX__W 2 +#define B_EQ_REG_COMM_MB_OBS_MUX__M 0x30 +#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 +#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 +#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 +#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 + + +#define B_EQ_REG_COMM_SERVICE0__A 0x1C10003 +#define B_EQ_REG_COMM_SERVICE0__W 10 +#define B_EQ_REG_COMM_SERVICE0__M 0x3FF + +#define B_EQ_REG_COMM_SERVICE1__A 0x1C10004 +#define B_EQ_REG_COMM_SERVICE1__W 11 +#define B_EQ_REG_COMM_SERVICE1__M 0x7FF + +#define B_EQ_REG_COMM_INT_STA__A 0x1C10007 +#define B_EQ_REG_COMM_INT_STA__W 2 +#define B_EQ_REG_COMM_INT_STA__M 0x3 +#define B_EQ_REG_COMM_INT_STA_TPS_RDY__B 0 +#define B_EQ_REG_COMM_INT_STA_TPS_RDY__W 1 +#define B_EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 +#define B_EQ_REG_COMM_INT_STA_ERR_RDY__B 1 +#define B_EQ_REG_COMM_INT_STA_ERR_RDY__W 1 +#define B_EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 + + +#define B_EQ_REG_COMM_INT_MSK__A 0x1C10008 +#define B_EQ_REG_COMM_INT_MSK__W 2 +#define B_EQ_REG_COMM_INT_MSK__M 0x3 +#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 +#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 +#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 +#define B_EQ_REG_COMM_INT_MSK_MER_RDY__B 1 +#define B_EQ_REG_COMM_INT_MSK_MER_RDY__W 1 +#define B_EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 + + +#define B_EQ_REG_IS_MODE__A 0x1C10014 +#define B_EQ_REG_IS_MODE__W 4 +#define B_EQ_REG_IS_MODE__M 0xF +#define B_EQ_REG_IS_MODE_INIT 0x0 + +#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 +#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 +#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 +#define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 +#define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 + +#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 +#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 +#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 +#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 +#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 + + +#define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 +#define B_EQ_REG_IS_GAIN_MAN__W 10 +#define B_EQ_REG_IS_GAIN_MAN__M 0x3FF +#define B_EQ_REG_IS_GAIN_MAN_INIT 0x114 + + +#define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 +#define B_EQ_REG_IS_GAIN_EXP__W 5 +#define B_EQ_REG_IS_GAIN_EXP__M 0x1F +#define B_EQ_REG_IS_GAIN_EXP_INIT 0x5 + + +#define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 +#define B_EQ_REG_IS_CLIP_EXP__W 5 +#define B_EQ_REG_IS_CLIP_EXP__M 0x1F +#define B_EQ_REG_IS_CLIP_EXP_INIT 0x10 + + +#define B_EQ_REG_DV_MODE__A 0x1C1001E +#define B_EQ_REG_DV_MODE__W 4 +#define B_EQ_REG_DV_MODE__M 0xF +#define B_EQ_REG_DV_MODE_INIT 0xF + +#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 + +#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 + +#define B_EQ_REG_DV_MODE_CLP_REA_ENA__B 2 +#define B_EQ_REG_DV_MODE_CLP_REA_ENA__W 1 +#define B_EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 +#define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 +#define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 + +#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 +#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 +#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 +#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 +#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 + + +#define B_EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F +#define B_EQ_REG_DV_POS_CLIP_DAT__W 16 +#define B_EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF + +#define B_EQ_REG_SN_MODE__A 0x1C10028 +#define B_EQ_REG_SN_MODE__W 8 +#define B_EQ_REG_SN_MODE__M 0xFF +#define B_EQ_REG_SN_MODE_INIT 0x18 + +#define B_EQ_REG_SN_MODE_MODE_0__B 0 +#define B_EQ_REG_SN_MODE_MODE_0__W 1 +#define B_EQ_REG_SN_MODE_MODE_0__M 0x1 +#define B_EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 + +#define B_EQ_REG_SN_MODE_MODE_1__B 1 +#define B_EQ_REG_SN_MODE_MODE_1__W 1 +#define B_EQ_REG_SN_MODE_MODE_1__M 0x2 +#define B_EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 + +#define B_EQ_REG_SN_MODE_MODE_2__B 2 +#define B_EQ_REG_SN_MODE_MODE_2__W 1 +#define B_EQ_REG_SN_MODE_MODE_2__M 0x4 +#define B_EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 + +#define B_EQ_REG_SN_MODE_MODE_3__B 3 +#define B_EQ_REG_SN_MODE_MODE_3__W 1 +#define B_EQ_REG_SN_MODE_MODE_3__M 0x8 +#define B_EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 + +#define B_EQ_REG_SN_MODE_MODE_4__B 4 +#define B_EQ_REG_SN_MODE_MODE_4__W 1 +#define B_EQ_REG_SN_MODE_MODE_4__M 0x10 +#define B_EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 + +#define B_EQ_REG_SN_MODE_MODE_5__B 5 +#define B_EQ_REG_SN_MODE_MODE_5__W 1 +#define B_EQ_REG_SN_MODE_MODE_5__M 0x20 +#define B_EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 + +#define B_EQ_REG_SN_MODE_MODE_6__B 6 +#define B_EQ_REG_SN_MODE_MODE_6__W 1 +#define B_EQ_REG_SN_MODE_MODE_6__M 0x40 +#define B_EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 +#define B_EQ_REG_SN_MODE_MODE_6_STATIC 0x40 + +#define B_EQ_REG_SN_MODE_MODE_7__B 7 +#define B_EQ_REG_SN_MODE_MODE_7__W 1 +#define B_EQ_REG_SN_MODE_MODE_7__M 0x80 +#define B_EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 +#define B_EQ_REG_SN_MODE_MODE_7_STATIC 0x80 + + +#define B_EQ_REG_SN_PFIX__A 0x1C10029 +#define B_EQ_REG_SN_PFIX__W 8 +#define B_EQ_REG_SN_PFIX__M 0xFF +#define B_EQ_REG_SN_PFIX_INIT 0x0 + + +#define B_EQ_REG_SN_CEGAIN__A 0x1C1002A +#define B_EQ_REG_SN_CEGAIN__W 8 +#define B_EQ_REG_SN_CEGAIN__M 0xFF +#define B_EQ_REG_SN_CEGAIN_INIT 0x30 + + +#define B_EQ_REG_SN_OFFSET__A 0x1C1002B +#define B_EQ_REG_SN_OFFSET__W 6 +#define B_EQ_REG_SN_OFFSET__M 0x3F +#define B_EQ_REG_SN_OFFSET_INIT 0x39 + + +#define B_EQ_REG_SN_NULLIFY__A 0x1C1002C +#define B_EQ_REG_SN_NULLIFY__W 6 +#define B_EQ_REG_SN_NULLIFY__M 0x3F +#define B_EQ_REG_SN_NULLIFY_INIT 0x0 + + +#define B_EQ_REG_SN_SQUASH__A 0x1C1002D +#define B_EQ_REG_SN_SQUASH__W 10 +#define B_EQ_REG_SN_SQUASH__M 0x3FF +#define B_EQ_REG_SN_SQUASH_INIT 0x7 + +#define B_EQ_REG_SN_SQUASH_MAN__B 0 +#define B_EQ_REG_SN_SQUASH_MAN__W 6 +#define B_EQ_REG_SN_SQUASH_MAN__M 0x3F + +#define B_EQ_REG_SN_SQUASH_EXP__B 6 +#define B_EQ_REG_SN_SQUASH_EXP__W 4 +#define B_EQ_REG_SN_SQUASH_EXP__M 0x3C0 + + + + +#define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 +#define B_EQ_REG_RC_SEL_CAR__W 8 +#define B_EQ_REG_RC_SEL_CAR__M 0xFF +#define B_EQ_REG_RC_SEL_CAR_INIT 0x2 +#define B_EQ_REG_RC_SEL_CAR_DIV__B 0 +#define B_EQ_REG_RC_SEL_CAR_DIV__W 1 +#define B_EQ_REG_RC_SEL_CAR_DIV__M 0x1 +#define B_EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 +#define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1 + +#define B_EQ_REG_RC_SEL_CAR_PASS__B 1 +#define B_EQ_REG_RC_SEL_CAR_PASS__W 2 +#define B_EQ_REG_RC_SEL_CAR_PASS__M 0x6 +#define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 +#define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 +#define B_EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 +#define B_EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 + +#define B_EQ_REG_RC_SEL_CAR_LOCAL__B 3 +#define B_EQ_REG_RC_SEL_CAR_LOCAL__W 2 +#define B_EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 +#define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 +#define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 +#define B_EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 +#define B_EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 + +#define B_EQ_REG_RC_SEL_CAR_MEAS__B 5 +#define B_EQ_REG_RC_SEL_CAR_MEAS__W 2 +#define B_EQ_REG_RC_SEL_CAR_MEAS__M 0x60 +#define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 +#define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 +#define B_EQ_REG_RC_SEL_CAR_MEAS_C_DRI 0x40 +#define B_EQ_REG_RC_SEL_CAR_MEAS_D_CC 0x60 + +#define B_EQ_REG_RC_SEL_CAR_FFTMODE__B 7 +#define B_EQ_REG_RC_SEL_CAR_FFTMODE__W 1 +#define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80 +#define B_EQ_REG_RC_SEL_CAR_FFTMODE_2K 0x0 +#define B_EQ_REG_RC_SEL_CAR_FFTMODE_8K 0x80 + + +#define B_EQ_REG_RC_STS__A 0x1C10033 +#define B_EQ_REG_RC_STS__W 14 +#define B_EQ_REG_RC_STS__M 0x3FFF + +#define B_EQ_REG_RC_STS_DIFF__B 0 +#define B_EQ_REG_RC_STS_DIFF__W 9 +#define B_EQ_REG_RC_STS_DIFF__M 0x1FF + +#define B_EQ_REG_RC_STS_FIRST__B 9 +#define B_EQ_REG_RC_STS_FIRST__W 1 +#define B_EQ_REG_RC_STS_FIRST__M 0x200 +#define B_EQ_REG_RC_STS_FIRST_A_CE 0x0 +#define B_EQ_REG_RC_STS_FIRST_B_DRI 0x200 + +#define B_EQ_REG_RC_STS_SELEC__B 10 +#define B_EQ_REG_RC_STS_SELEC__W 1 +#define B_EQ_REG_RC_STS_SELEC__M 0x400 +#define B_EQ_REG_RC_STS_SELEC_A_CE 0x0 +#define B_EQ_REG_RC_STS_SELEC_B_DRI 0x400 + +#define B_EQ_REG_RC_STS_OVERFLOW__B 11 +#define B_EQ_REG_RC_STS_OVERFLOW__W 1 +#define B_EQ_REG_RC_STS_OVERFLOW__M 0x800 +#define B_EQ_REG_RC_STS_OVERFLOW_NO 0x0 +#define B_EQ_REG_RC_STS_OVERFLOW_YES 0x800 + +#define B_EQ_REG_RC_STS_LOC_PRS__B 12 +#define B_EQ_REG_RC_STS_LOC_PRS__W 1 +#define B_EQ_REG_RC_STS_LOC_PRS__M 0x1000 +#define B_EQ_REG_RC_STS_LOC_PRS_NO 0x0 +#define B_EQ_REG_RC_STS_LOC_PRS_YES 0x1000 + +#define B_EQ_REG_RC_STS_DRI_PRS__B 13 +#define B_EQ_REG_RC_STS_DRI_PRS__W 1 +#define B_EQ_REG_RC_STS_DRI_PRS__M 0x2000 +#define B_EQ_REG_RC_STS_DRI_PRS_NO 0x0 +#define B_EQ_REG_RC_STS_DRI_PRS_YES 0x2000 + + +#define B_EQ_REG_OT_CONST__A 0x1C10046 +#define B_EQ_REG_OT_CONST__W 2 +#define B_EQ_REG_OT_CONST__M 0x3 +#define B_EQ_REG_OT_CONST_INIT 0x2 + + +#define B_EQ_REG_OT_ALPHA__A 0x1C10047 +#define B_EQ_REG_OT_ALPHA__W 2 +#define B_EQ_REG_OT_ALPHA__M 0x3 +#define B_EQ_REG_OT_ALPHA_INIT 0x0 + + +#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 +#define B_EQ_REG_OT_QNT_THRES0__W 5 +#define B_EQ_REG_OT_QNT_THRES0__M 0x1F +#define B_EQ_REG_OT_QNT_THRES0_INIT 0x1E + + +#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 +#define B_EQ_REG_OT_QNT_THRES1__W 5 +#define B_EQ_REG_OT_QNT_THRES1__M 0x1F +#define B_EQ_REG_OT_QNT_THRES1_INIT 0x1F + + +#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A +#define B_EQ_REG_OT_CSI_STEP__W 4 +#define B_EQ_REG_OT_CSI_STEP__M 0xF +#define B_EQ_REG_OT_CSI_STEP_INIT 0x5 + + +#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B +#define B_EQ_REG_OT_CSI_OFFSET__W 7 +#define B_EQ_REG_OT_CSI_OFFSET__M 0x7F +#define B_EQ_REG_OT_CSI_OFFSET_INIT 0x5 + + +#define B_EQ_REG_OT_CSI_GAIN__A 0x1C1004C +#define B_EQ_REG_OT_CSI_GAIN__W 8 +#define B_EQ_REG_OT_CSI_GAIN__M 0xFF +#define B_EQ_REG_OT_CSI_GAIN_INIT 0x2B + + +#define B_EQ_REG_OT_CSI_MEAN__A 0x1C1004D +#define B_EQ_REG_OT_CSI_MEAN__W 7 +#define B_EQ_REG_OT_CSI_MEAN__M 0x7F + +#define B_EQ_REG_OT_CSI_VARIANCE__A 0x1C1004E +#define B_EQ_REG_OT_CSI_VARIANCE__W 7 +#define B_EQ_REG_OT_CSI_VARIANCE__M 0x7F + + + + +#define B_EQ_REG_TD_TPS_INIT__A 0x1C10050 +#define B_EQ_REG_TD_TPS_INIT__W 1 +#define B_EQ_REG_TD_TPS_INIT__M 0x1 +#define B_EQ_REG_TD_TPS_INIT_INIT 0x0 +#define B_EQ_REG_TD_TPS_INIT_POS 0x0 +#define B_EQ_REG_TD_TPS_INIT_NEG 0x1 + + +#define B_EQ_REG_TD_TPS_SYNC__A 0x1C10051 +#define B_EQ_REG_TD_TPS_SYNC__W 16 +#define B_EQ_REG_TD_TPS_SYNC__M 0xFFFF +#define B_EQ_REG_TD_TPS_SYNC_INIT 0x0 +#define B_EQ_REG_TD_TPS_SYNC_ODD 0x35EE +#define B_EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 + + +#define B_EQ_REG_TD_TPS_LEN__A 0x1C10052 +#define B_EQ_REG_TD_TPS_LEN__W 6 +#define B_EQ_REG_TD_TPS_LEN__M 0x3F +#define B_EQ_REG_TD_TPS_LEN_INIT 0x0 +#define B_EQ_REG_TD_TPS_LEN_DEF 0x17 +#define B_EQ_REG_TD_TPS_LEN_ID_SUP 0x1F + + +#define B_EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 +#define B_EQ_REG_TD_TPS_FRM_NMB__W 2 +#define B_EQ_REG_TD_TPS_FRM_NMB__M 0x3 +#define B_EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 +#define B_EQ_REG_TD_TPS_FRM_NMB_1 0x0 +#define B_EQ_REG_TD_TPS_FRM_NMB_2 0x1 +#define B_EQ_REG_TD_TPS_FRM_NMB_3 0x2 +#define B_EQ_REG_TD_TPS_FRM_NMB_4 0x3 + + +#define B_EQ_REG_TD_TPS_CONST__A 0x1C10054 +#define B_EQ_REG_TD_TPS_CONST__W 2 +#define B_EQ_REG_TD_TPS_CONST__M 0x3 +#define B_EQ_REG_TD_TPS_CONST_INIT 0x0 +#define B_EQ_REG_TD_TPS_CONST_QPSK 0x0 +#define B_EQ_REG_TD_TPS_CONST_16QAM 0x1 +#define B_EQ_REG_TD_TPS_CONST_64QAM 0x2 + + +#define B_EQ_REG_TD_TPS_HINFO__A 0x1C10055 +#define B_EQ_REG_TD_TPS_HINFO__W 3 +#define B_EQ_REG_TD_TPS_HINFO__M 0x7 +#define B_EQ_REG_TD_TPS_HINFO_INIT 0x0 +#define B_EQ_REG_TD_TPS_HINFO_NH 0x0 +#define B_EQ_REG_TD_TPS_HINFO_H1 0x1 +#define B_EQ_REG_TD_TPS_HINFO_H2 0x2 +#define B_EQ_REG_TD_TPS_HINFO_H4 0x3 + + +#define B_EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 +#define B_EQ_REG_TD_TPS_CODE_HP__W 3 +#define B_EQ_REG_TD_TPS_CODE_HP__M 0x7 +#define B_EQ_REG_TD_TPS_CODE_HP_INIT 0x0 +#define B_EQ_REG_TD_TPS_CODE_HP_1_2 0x0 +#define B_EQ_REG_TD_TPS_CODE_HP_2_3 0x1 +#define B_EQ_REG_TD_TPS_CODE_HP_3_4 0x2 +#define B_EQ_REG_TD_TPS_CODE_HP_5_6 0x3 +#define B_EQ_REG_TD_TPS_CODE_HP_7_8 0x4 + + +#define B_EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 +#define B_EQ_REG_TD_TPS_CODE_LP__W 3 +#define B_EQ_REG_TD_TPS_CODE_LP__M 0x7 +#define B_EQ_REG_TD_TPS_CODE_LP_INIT 0x0 +#define B_EQ_REG_TD_TPS_CODE_LP_1_2 0x0 +#define B_EQ_REG_TD_TPS_CODE_LP_2_3 0x1 +#define B_EQ_REG_TD_TPS_CODE_LP_3_4 0x2 +#define B_EQ_REG_TD_TPS_CODE_LP_5_6 0x3 +#define B_EQ_REG_TD_TPS_CODE_LP_7_8 0x4 + + +#define B_EQ_REG_TD_TPS_GUARD__A 0x1C10058 +#define B_EQ_REG_TD_TPS_GUARD__W 2 +#define B_EQ_REG_TD_TPS_GUARD__M 0x3 +#define B_EQ_REG_TD_TPS_GUARD_INIT 0x0 +#define B_EQ_REG_TD_TPS_GUARD_32 0x0 +#define B_EQ_REG_TD_TPS_GUARD_16 0x1 +#define B_EQ_REG_TD_TPS_GUARD_08 0x2 +#define B_EQ_REG_TD_TPS_GUARD_04 0x3 + + +#define B_EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 +#define B_EQ_REG_TD_TPS_TR_MODE__W 2 +#define B_EQ_REG_TD_TPS_TR_MODE__M 0x3 +#define B_EQ_REG_TD_TPS_TR_MODE_INIT 0x0 +#define B_EQ_REG_TD_TPS_TR_MODE_2K 0x0 +#define B_EQ_REG_TD_TPS_TR_MODE_8K 0x1 + + +#define B_EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A +#define B_EQ_REG_TD_TPS_CELL_ID_HI__W 8 +#define B_EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF +#define B_EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 + + +#define B_EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B +#define B_EQ_REG_TD_TPS_CELL_ID_LO__W 8 +#define B_EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF +#define B_EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 + + +#define B_EQ_REG_TD_TPS_RSV__A 0x1C1005C +#define B_EQ_REG_TD_TPS_RSV__W 6 +#define B_EQ_REG_TD_TPS_RSV__M 0x3F +#define B_EQ_REG_TD_TPS_RSV_INIT 0x0 + + +#define B_EQ_REG_TD_TPS_BCH__A 0x1C1005D +#define B_EQ_REG_TD_TPS_BCH__W 14 +#define B_EQ_REG_TD_TPS_BCH__M 0x3FFF +#define B_EQ_REG_TD_TPS_BCH_INIT 0x0 + + +#define B_EQ_REG_TD_SQR_ERR_I__A 0x1C1005E +#define B_EQ_REG_TD_SQR_ERR_I__W 16 +#define B_EQ_REG_TD_SQR_ERR_I__M 0xFFFF +#define B_EQ_REG_TD_SQR_ERR_I_INIT 0x0 + + +#define B_EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F +#define B_EQ_REG_TD_SQR_ERR_Q__W 16 +#define B_EQ_REG_TD_SQR_ERR_Q__M 0xFFFF +#define B_EQ_REG_TD_SQR_ERR_Q_INIT 0x0 + + +#define B_EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 +#define B_EQ_REG_TD_SQR_ERR_EXP__W 4 +#define B_EQ_REG_TD_SQR_ERR_EXP__M 0xF +#define B_EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 + + +#define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 +#define B_EQ_REG_TD_REQ_SMB_CNT__W 16 +#define B_EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF +#define B_EQ_REG_TD_REQ_SMB_CNT_INIT 0x200 + + +#define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 +#define B_EQ_REG_TD_TPS_PWR_OFS__W 16 +#define B_EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF +#define B_EQ_REG_TD_TPS_PWR_OFS_INIT 0x19F + + + + + + + + + +#define B_EC_COMM_EXEC__A 0x2000000 +#define B_EC_COMM_EXEC__W 3 +#define B_EC_COMM_EXEC__M 0x7 +#define B_EC_COMM_EXEC_CTL__B 0 +#define B_EC_COMM_EXEC_CTL__W 3 +#define B_EC_COMM_EXEC_CTL__M 0x7 +#define B_EC_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_COMM_EXEC_CTL_HOLD 0x2 +#define B_EC_COMM_EXEC_CTL_STEP 0x3 +#define B_EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_EC_COMM_STATE__A 0x2000001 +#define B_EC_COMM_STATE__W 16 +#define B_EC_COMM_STATE__M 0xFFFF +#define B_EC_COMM_MB__A 0x2000002 +#define B_EC_COMM_MB__W 16 +#define B_EC_COMM_MB__M 0xFFFF +#define B_EC_COMM_SERVICE0__A 0x2000003 +#define B_EC_COMM_SERVICE0__W 16 +#define B_EC_COMM_SERVICE0__M 0xFFFF +#define B_EC_COMM_SERVICE1__A 0x2000004 +#define B_EC_COMM_SERVICE1__W 16 +#define B_EC_COMM_SERVICE1__M 0xFFFF +#define B_EC_COMM_INT_STA__A 0x2000007 +#define B_EC_COMM_INT_STA__W 16 +#define B_EC_COMM_INT_STA__M 0xFFFF +#define B_EC_COMM_INT_MSK__A 0x2000008 +#define B_EC_COMM_INT_MSK__W 16 +#define B_EC_COMM_INT_MSK__M 0xFFFF + + + + + +#define B_EC_SB_SID 0x16 + + + + + +#define B_EC_SB_REG_COMM_EXEC__A 0x2010000 +#define B_EC_SB_REG_COMM_EXEC__W 3 +#define B_EC_SB_REG_COMM_EXEC__M 0x7 +#define B_EC_SB_REG_COMM_EXEC_CTL__B 0 +#define B_EC_SB_REG_COMM_EXEC_CTL__W 3 +#define B_EC_SB_REG_COMM_EXEC_CTL__M 0x7 +#define B_EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define B_EC_SB_REG_COMM_STATE__A 0x2010001 +#define B_EC_SB_REG_COMM_STATE__W 4 +#define B_EC_SB_REG_COMM_STATE__M 0xF +#define B_EC_SB_REG_COMM_MB__A 0x2010002 +#define B_EC_SB_REG_COMM_MB__W 2 +#define B_EC_SB_REG_COMM_MB__M 0x3 +#define B_EC_SB_REG_COMM_MB_CTR__B 0 +#define B_EC_SB_REG_COMM_MB_CTR__W 1 +#define B_EC_SB_REG_COMM_MB_CTR__M 0x1 +#define B_EC_SB_REG_COMM_MB_CTR_OFF 0x0 +#define B_EC_SB_REG_COMM_MB_CTR_ON 0x1 +#define B_EC_SB_REG_COMM_MB_OBS__B 1 +#define B_EC_SB_REG_COMM_MB_OBS__W 1 +#define B_EC_SB_REG_COMM_MB_OBS__M 0x2 +#define B_EC_SB_REG_COMM_MB_OBS_OFF 0x0 +#define B_EC_SB_REG_COMM_MB_OBS_ON 0x2 + + +#define B_EC_SB_REG_TR_MODE__A 0x2010010 +#define B_EC_SB_REG_TR_MODE__W 1 +#define B_EC_SB_REG_TR_MODE__M 0x1 +#define B_EC_SB_REG_TR_MODE_INIT 0x0 +#define B_EC_SB_REG_TR_MODE_8K 0x0 +#define B_EC_SB_REG_TR_MODE_2K 0x1 + + +#define B_EC_SB_REG_CONST__A 0x2010011 +#define B_EC_SB_REG_CONST__W 2 +#define B_EC_SB_REG_CONST__M 0x3 +#define B_EC_SB_REG_CONST_INIT 0x2 +#define B_EC_SB_REG_CONST_QPSK 0x0 +#define B_EC_SB_REG_CONST_16QAM 0x1 +#define B_EC_SB_REG_CONST_64QAM 0x2 + + +#define B_EC_SB_REG_ALPHA__A 0x2010012 +#define B_EC_SB_REG_ALPHA__W 3 +#define B_EC_SB_REG_ALPHA__M 0x7 + +#define B_EC_SB_REG_ALPHA_INIT 0x0 + +#define B_EC_SB_REG_ALPHA_NH 0x0 + +#define B_EC_SB_REG_ALPHA_H1 0x1 + +#define B_EC_SB_REG_ALPHA_H2 0x2 + +#define B_EC_SB_REG_ALPHA_H4 0x3 + + +#define B_EC_SB_REG_PRIOR__A 0x2010013 +#define B_EC_SB_REG_PRIOR__W 1 +#define B_EC_SB_REG_PRIOR__M 0x1 +#define B_EC_SB_REG_PRIOR_INIT 0x0 +#define B_EC_SB_REG_PRIOR_HI 0x0 +#define B_EC_SB_REG_PRIOR_LO 0x1 + + +#define B_EC_SB_REG_CSI_HI__A 0x2010014 +#define B_EC_SB_REG_CSI_HI__W 5 +#define B_EC_SB_REG_CSI_HI__M 0x1F +#define B_EC_SB_REG_CSI_HI_INIT 0x1F +#define B_EC_SB_REG_CSI_HI_MAX 0x1F +#define B_EC_SB_REG_CSI_HI_MIN 0x0 +#define B_EC_SB_REG_CSI_HI_TAG 0x0 + + +#define B_EC_SB_REG_CSI_LO__A 0x2010015 +#define B_EC_SB_REG_CSI_LO__W 5 +#define B_EC_SB_REG_CSI_LO__M 0x1F +#define B_EC_SB_REG_CSI_LO_INIT 0x1E +#define B_EC_SB_REG_CSI_LO_MAX 0x1F +#define B_EC_SB_REG_CSI_LO_MIN 0x0 +#define B_EC_SB_REG_CSI_LO_TAG 0x0 + + +#define B_EC_SB_REG_SMB_TGL__A 0x2010016 +#define B_EC_SB_REG_SMB_TGL__W 1 +#define B_EC_SB_REG_SMB_TGL__M 0x1 +#define B_EC_SB_REG_SMB_TGL_OFF 0x0 +#define B_EC_SB_REG_SMB_TGL_ON 0x1 +#define B_EC_SB_REG_SMB_TGL_INIT 0x1 + + +#define B_EC_SB_REG_SNR_HI__A 0x2010017 +#define B_EC_SB_REG_SNR_HI__W 8 +#define B_EC_SB_REG_SNR_HI__M 0xFF +#define B_EC_SB_REG_SNR_HI_INIT 0x6E +#define B_EC_SB_REG_SNR_HI_MAX 0xFF +#define B_EC_SB_REG_SNR_HI_MIN 0x0 +#define B_EC_SB_REG_SNR_HI_TAG 0x0 + + +#define B_EC_SB_REG_SNR_MID__A 0x2010018 +#define B_EC_SB_REG_SNR_MID__W 8 +#define B_EC_SB_REG_SNR_MID__M 0xFF +#define B_EC_SB_REG_SNR_MID_INIT 0x6C +#define B_EC_SB_REG_SNR_MID_MAX 0xFF +#define B_EC_SB_REG_SNR_MID_MIN 0x0 +#define B_EC_SB_REG_SNR_MID_TAG 0x0 + + +#define B_EC_SB_REG_SNR_LO__A 0x2010019 +#define B_EC_SB_REG_SNR_LO__W 8 +#define B_EC_SB_REG_SNR_LO__M 0xFF +#define B_EC_SB_REG_SNR_LO_INIT 0x68 +#define B_EC_SB_REG_SNR_LO_MAX 0xFF +#define B_EC_SB_REG_SNR_LO_MIN 0x0 +#define B_EC_SB_REG_SNR_LO_TAG 0x0 + + +#define B_EC_SB_REG_SCALE_MSB__A 0x201001A +#define B_EC_SB_REG_SCALE_MSB__W 6 +#define B_EC_SB_REG_SCALE_MSB__M 0x3F +#define B_EC_SB_REG_SCALE_MSB_INIT 0x30 +#define B_EC_SB_REG_SCALE_MSB_MAX 0x3F + + +#define B_EC_SB_REG_SCALE_BIT2__A 0x201001B +#define B_EC_SB_REG_SCALE_BIT2__W 6 +#define B_EC_SB_REG_SCALE_BIT2__M 0x3F +#define B_EC_SB_REG_SCALE_BIT2_INIT 0xC +#define B_EC_SB_REG_SCALE_BIT2_MAX 0x3F + + +#define B_EC_SB_REG_SCALE_LSB__A 0x201001C +#define B_EC_SB_REG_SCALE_LSB__W 6 +#define B_EC_SB_REG_SCALE_LSB__M 0x3F +#define B_EC_SB_REG_SCALE_LSB_INIT 0x3 +#define B_EC_SB_REG_SCALE_LSB_MAX 0x3F + + +#define B_EC_SB_REG_CSI_OFS0__A 0x201001D +#define B_EC_SB_REG_CSI_OFS0__W 4 +#define B_EC_SB_REG_CSI_OFS0__M 0xF +#define B_EC_SB_REG_CSI_OFS0_INIT 0x4 + + +#define B_EC_SB_REG_CSI_OFS1__A 0x201001E +#define B_EC_SB_REG_CSI_OFS1__W 4 +#define B_EC_SB_REG_CSI_OFS1__M 0xF +#define B_EC_SB_REG_CSI_OFS1_INIT 0x1 + + +#define B_EC_SB_REG_CSI_OFS2__A 0x201001F +#define B_EC_SB_REG_CSI_OFS2__W 4 +#define B_EC_SB_REG_CSI_OFS2__M 0xF +#define B_EC_SB_REG_CSI_OFS2_INIT 0x2 + + +#define B_EC_SB_REG_MAX0__A 0x2010020 +#define B_EC_SB_REG_MAX0__W 6 +#define B_EC_SB_REG_MAX0__M 0x3F +#define B_EC_SB_REG_MAX0_INIT 0x3F + + +#define B_EC_SB_REG_MAX1__A 0x2010021 +#define B_EC_SB_REG_MAX1__W 6 +#define B_EC_SB_REG_MAX1__M 0x3F +#define B_EC_SB_REG_MAX1_INIT 0x3F + + +#define B_EC_SB_REG_MAX2__A 0x2010022 +#define B_EC_SB_REG_MAX2__W 6 +#define B_EC_SB_REG_MAX2__M 0x3F +#define B_EC_SB_REG_MAX2_INIT 0x3F + + +#define B_EC_SB_REG_CSI_DIS__A 0x2010023 +#define B_EC_SB_REG_CSI_DIS__W 1 +#define B_EC_SB_REG_CSI_DIS__M 0x1 +#define B_EC_SB_REG_CSI_DIS_INIT 0x0 + + + +#define B_EC_SB_SD_RAM__A 0x2020000 + + + +#define B_EC_SB_BD0_RAM__A 0x2030000 + + + +#define B_EC_SB_BD1_RAM__A 0x2040000 + + + + + +#define B_EC_VD_SID 0x17 + + + + + +#define B_EC_VD_REG_COMM_EXEC__A 0x2090000 +#define B_EC_VD_REG_COMM_EXEC__W 3 +#define B_EC_VD_REG_COMM_EXEC__M 0x7 +#define B_EC_VD_REG_COMM_EXEC_CTL__B 0 +#define B_EC_VD_REG_COMM_EXEC_CTL__W 3 +#define B_EC_VD_REG_COMM_EXEC_CTL__M 0x7 +#define B_EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define B_EC_VD_REG_COMM_STATE__A 0x2090001 +#define B_EC_VD_REG_COMM_STATE__W 4 +#define B_EC_VD_REG_COMM_STATE__M 0xF +#define B_EC_VD_REG_COMM_MB__A 0x2090002 +#define B_EC_VD_REG_COMM_MB__W 2 +#define B_EC_VD_REG_COMM_MB__M 0x3 +#define B_EC_VD_REG_COMM_MB_CTR__B 0 +#define B_EC_VD_REG_COMM_MB_CTR__W 1 +#define B_EC_VD_REG_COMM_MB_CTR__M 0x1 +#define B_EC_VD_REG_COMM_MB_CTR_OFF 0x0 +#define B_EC_VD_REG_COMM_MB_CTR_ON 0x1 +#define B_EC_VD_REG_COMM_MB_OBS__B 1 +#define B_EC_VD_REG_COMM_MB_OBS__W 1 +#define B_EC_VD_REG_COMM_MB_OBS__M 0x2 +#define B_EC_VD_REG_COMM_MB_OBS_OFF 0x0 +#define B_EC_VD_REG_COMM_MB_OBS_ON 0x2 + +#define B_EC_VD_REG_COMM_SERVICE0__A 0x2090003 +#define B_EC_VD_REG_COMM_SERVICE0__W 16 +#define B_EC_VD_REG_COMM_SERVICE0__M 0xFFFF +#define B_EC_VD_REG_COMM_SERVICE1__A 0x2090004 +#define B_EC_VD_REG_COMM_SERVICE1__W 16 +#define B_EC_VD_REG_COMM_SERVICE1__M 0xFFFF +#define B_EC_VD_REG_COMM_INT_STA__A 0x2090007 +#define B_EC_VD_REG_COMM_INT_STA__W 1 +#define B_EC_VD_REG_COMM_INT_STA__M 0x1 +#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 +#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 +#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 + +#define B_EC_VD_REG_COMM_INT_MSK__A 0x2090008 +#define B_EC_VD_REG_COMM_INT_MSK__W 1 +#define B_EC_VD_REG_COMM_INT_MSK__M 0x1 +#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 +#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 +#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 + + +#define B_EC_VD_REG_FORCE__A 0x2090010 +#define B_EC_VD_REG_FORCE__W 2 +#define B_EC_VD_REG_FORCE__M 0x3 +#define B_EC_VD_REG_FORCE_INIT 0x2 +#define B_EC_VD_REG_FORCE_FREE 0x0 +#define B_EC_VD_REG_FORCE_PROP 0x1 +#define B_EC_VD_REG_FORCE_FORCED 0x2 +#define B_EC_VD_REG_FORCE_FIXED 0x3 + + +#define B_EC_VD_REG_SET_CODERATE__A 0x2090011 +#define B_EC_VD_REG_SET_CODERATE__W 3 +#define B_EC_VD_REG_SET_CODERATE__M 0x7 +#define B_EC_VD_REG_SET_CODERATE_INIT 0x1 +#define B_EC_VD_REG_SET_CODERATE_C1_2 0x0 +#define B_EC_VD_REG_SET_CODERATE_C2_3 0x1 +#define B_EC_VD_REG_SET_CODERATE_C3_4 0x2 +#define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 +#define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 + + +#define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 +#define B_EC_VD_REG_REQ_SMB_CNT__W 16 +#define B_EC_VD_REG_REQ_SMB_CNT__M 0xFFFF +#define B_EC_VD_REG_REQ_SMB_CNT_INIT 0x1 + + +#define B_EC_VD_REG_REQ_BIT_CNT__A 0x2090013 +#define B_EC_VD_REG_REQ_BIT_CNT__W 16 +#define B_EC_VD_REG_REQ_BIT_CNT__M 0xFFFF +#define B_EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF + + +#define B_EC_VD_REG_RLK_ENA__A 0x2090014 +#define B_EC_VD_REG_RLK_ENA__W 1 +#define B_EC_VD_REG_RLK_ENA__M 0x1 +#define B_EC_VD_REG_RLK_ENA_INIT 0x1 +#define B_EC_VD_REG_RLK_ENA_OFF 0x0 +#define B_EC_VD_REG_RLK_ENA_ON 0x1 + + +#define B_EC_VD_REG_VAL__A 0x2090015 +#define B_EC_VD_REG_VAL__W 2 +#define B_EC_VD_REG_VAL__M 0x3 +#define B_EC_VD_REG_VAL_INIT 0x0 +#define B_EC_VD_REG_VAL_CODE 0x1 +#define B_EC_VD_REG_VAL_CNT 0x2 + + +#define B_EC_VD_REG_GET_CODERATE__A 0x2090016 +#define B_EC_VD_REG_GET_CODERATE__W 3 +#define B_EC_VD_REG_GET_CODERATE__M 0x7 +#define B_EC_VD_REG_GET_CODERATE_INIT 0x0 +#define B_EC_VD_REG_GET_CODERATE_C1_2 0x0 +#define B_EC_VD_REG_GET_CODERATE_C2_3 0x1 +#define B_EC_VD_REG_GET_CODERATE_C3_4 0x2 +#define B_EC_VD_REG_GET_CODERATE_C5_6 0x3 +#define B_EC_VD_REG_GET_CODERATE_C7_8 0x4 + + +#define B_EC_VD_REG_ERR_BIT_CNT__A 0x2090017 +#define B_EC_VD_REG_ERR_BIT_CNT__W 16 +#define B_EC_VD_REG_ERR_BIT_CNT__M 0xFFFF +#define B_EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF + + +#define B_EC_VD_REG_IN_BIT_CNT__A 0x2090018 +#define B_EC_VD_REG_IN_BIT_CNT__W 16 +#define B_EC_VD_REG_IN_BIT_CNT__M 0xFFFF +#define B_EC_VD_REG_IN_BIT_CNT_INIT 0x0 + + +#define B_EC_VD_REG_STS__A 0x2090019 +#define B_EC_VD_REG_STS__W 1 +#define B_EC_VD_REG_STS__M 0x1 +#define B_EC_VD_REG_STS_INIT 0x0 +#define B_EC_VD_REG_STS_NO_LOCK 0x0 +#define B_EC_VD_REG_STS_IN_LOCK 0x1 + + +#define B_EC_VD_REG_RLK_CNT__A 0x209001A +#define B_EC_VD_REG_RLK_CNT__W 16 +#define B_EC_VD_REG_RLK_CNT__M 0xFFFF +#define B_EC_VD_REG_RLK_CNT_INIT 0x0 + + + +#define B_EC_VD_TB0_RAM__A 0x20A0000 + + + +#define B_EC_VD_TB1_RAM__A 0x20B0000 + + + +#define B_EC_VD_TB2_RAM__A 0x20C0000 + + + +#define B_EC_VD_TB3_RAM__A 0x20D0000 + + + +#define B_EC_VD_RE_RAM__A 0x2100000 + + + + + +#define B_EC_OD_SID 0x18 + + + + + + +#define B_EC_OD_REG_COMM_EXEC__A 0x2110000 +#define B_EC_OD_REG_COMM_EXEC__W 3 +#define B_EC_OD_REG_COMM_EXEC__M 0x7 +#define B_EC_OD_REG_COMM_EXEC_CTL__B 0 +#define B_EC_OD_REG_COMM_EXEC_CTL__W 3 +#define B_EC_OD_REG_COMM_EXEC_CTL__M 0x7 +#define B_EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_EC_OD_REG_COMM_STATE__A 0x2110001 +#define B_EC_OD_REG_COMM_STATE__W 1 +#define B_EC_OD_REG_COMM_STATE__M 0x1 +#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__B 0 +#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__W 1 +#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__M 0x1 + + +#define B_EC_OD_REG_COMM_MB__A 0x2110002 +#define B_EC_OD_REG_COMM_MB__W 3 +#define B_EC_OD_REG_COMM_MB__M 0x7 +#define B_EC_OD_REG_COMM_MB_CTR__B 0 +#define B_EC_OD_REG_COMM_MB_CTR__W 1 +#define B_EC_OD_REG_COMM_MB_CTR__M 0x1 +#define B_EC_OD_REG_COMM_MB_CTR_OFF 0x0 +#define B_EC_OD_REG_COMM_MB_CTR_ON 0x1 +#define B_EC_OD_REG_COMM_MB_OBS__B 1 +#define B_EC_OD_REG_COMM_MB_OBS__W 1 +#define B_EC_OD_REG_COMM_MB_OBS__M 0x2 +#define B_EC_OD_REG_COMM_MB_OBS_OFF 0x0 +#define B_EC_OD_REG_COMM_MB_OBS_ON 0x2 + +#define B_EC_OD_REG_COMM_SERVICE0__A 0x2110003 +#define B_EC_OD_REG_COMM_SERVICE0__W 10 +#define B_EC_OD_REG_COMM_SERVICE0__M 0x3FF +#define B_EC_OD_REG_COMM_SERVICE1__A 0x2110004 +#define B_EC_OD_REG_COMM_SERVICE1__W 11 +#define B_EC_OD_REG_COMM_SERVICE1__M 0x7FF + +#define B_EC_OD_REG_COMM_ACTIVATE__A 0x2110005 +#define B_EC_OD_REG_COMM_ACTIVATE__W 2 +#define B_EC_OD_REG_COMM_ACTIVATE__M 0x3 + +#define B_EC_OD_REG_COMM_COUNT__A 0x2110006 +#define B_EC_OD_REG_COMM_COUNT__W 16 +#define B_EC_OD_REG_COMM_COUNT__M 0xFFFF + +#define B_EC_OD_REG_COMM_INT_STA__A 0x2110007 +#define B_EC_OD_REG_COMM_INT_STA__W 2 +#define B_EC_OD_REG_COMM_INT_STA__M 0x3 +#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 +#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 +#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 +#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 +#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 +#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 + + +#define B_EC_OD_REG_COMM_INT_MSK__A 0x2110008 +#define B_EC_OD_REG_COMM_INT_MSK__W 2 +#define B_EC_OD_REG_COMM_INT_MSK__M 0x3 +#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 +#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 +#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 +#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 +#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 +#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 + + +#define B_EC_OD_REG_SYNC__A 0x2110664 +#define B_EC_OD_REG_SYNC__W 12 +#define B_EC_OD_REG_SYNC__M 0xFFF +#define B_EC_OD_REG_SYNC_NR_SYNC__B 0 +#define B_EC_OD_REG_SYNC_NR_SYNC__W 5 +#define B_EC_OD_REG_SYNC_NR_SYNC__M 0x1F +#define B_EC_OD_REG_SYNC_IN_SYNC__B 5 +#define B_EC_OD_REG_SYNC_IN_SYNC__W 4 +#define B_EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 +#define B_EC_OD_REG_SYNC_OUT_SYNC__B 9 +#define B_EC_OD_REG_SYNC_OUT_SYNC__W 3 +#define B_EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 + + +#define B_EC_OD_REG_NOSYNC__A 0x2110004 +#define B_EC_OD_REG_NOSYNC__W 8 +#define B_EC_OD_REG_NOSYNC__M 0xFF + + + +#define B_EC_OD_DEINT_RAM__A 0x2120000 + + + + + +#define B_EC_RS_SID 0x19 + + + + + +#define B_EC_RS_REG_COMM_EXEC__A 0x2130000 +#define B_EC_RS_REG_COMM_EXEC__W 3 +#define B_EC_RS_REG_COMM_EXEC__M 0x7 +#define B_EC_RS_REG_COMM_EXEC_CTL__B 0 +#define B_EC_RS_REG_COMM_EXEC_CTL__W 3 +#define B_EC_RS_REG_COMM_EXEC_CTL__M 0x7 +#define B_EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define B_EC_RS_REG_COMM_STATE__A 0x2130001 +#define B_EC_RS_REG_COMM_STATE__W 4 +#define B_EC_RS_REG_COMM_STATE__M 0xF +#define B_EC_RS_REG_COMM_MB__A 0x2130002 +#define B_EC_RS_REG_COMM_MB__W 2 +#define B_EC_RS_REG_COMM_MB__M 0x3 +#define B_EC_RS_REG_COMM_MB_CTR__B 0 +#define B_EC_RS_REG_COMM_MB_CTR__W 1 +#define B_EC_RS_REG_COMM_MB_CTR__M 0x1 +#define B_EC_RS_REG_COMM_MB_CTR_OFF 0x0 +#define B_EC_RS_REG_COMM_MB_CTR_ON 0x1 +#define B_EC_RS_REG_COMM_MB_OBS__B 1 +#define B_EC_RS_REG_COMM_MB_OBS__W 1 +#define B_EC_RS_REG_COMM_MB_OBS__M 0x2 +#define B_EC_RS_REG_COMM_MB_OBS_OFF 0x0 +#define B_EC_RS_REG_COMM_MB_OBS_ON 0x2 + +#define B_EC_RS_REG_COMM_SERVICE0__A 0x2130003 +#define B_EC_RS_REG_COMM_SERVICE0__W 16 +#define B_EC_RS_REG_COMM_SERVICE0__M 0xFFFF +#define B_EC_RS_REG_COMM_SERVICE1__A 0x2130004 +#define B_EC_RS_REG_COMM_SERVICE1__W 16 +#define B_EC_RS_REG_COMM_SERVICE1__M 0xFFFF +#define B_EC_RS_REG_COMM_INT_STA__A 0x2130007 +#define B_EC_RS_REG_COMM_INT_STA__W 1 +#define B_EC_RS_REG_COMM_INT_STA__M 0x1 +#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 +#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 +#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 + +#define B_EC_RS_REG_COMM_INT_MSK__A 0x2130008 +#define B_EC_RS_REG_COMM_INT_MSK__W 1 +#define B_EC_RS_REG_COMM_INT_MSK__M 0x1 +#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 +#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 +#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 + + +#define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 +#define B_EC_RS_REG_REQ_PCK_CNT__W 16 +#define B_EC_RS_REG_REQ_PCK_CNT__M 0xFFFF +#define B_EC_RS_REG_REQ_PCK_CNT_INIT 0x200 + + +#define B_EC_RS_REG_VAL__A 0x2130011 +#define B_EC_RS_REG_VAL__W 1 +#define B_EC_RS_REG_VAL__M 0x1 +#define B_EC_RS_REG_VAL_INIT 0x0 +#define B_EC_RS_REG_VAL_PCK 0x1 + + +#define B_EC_RS_REG_ERR_PCK_CNT__A 0x2130012 +#define B_EC_RS_REG_ERR_PCK_CNT__W 16 +#define B_EC_RS_REG_ERR_PCK_CNT__M 0xFFFF +#define B_EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF + + +#define B_EC_RS_REG_ERR_SMB_CNT__A 0x2130013 +#define B_EC_RS_REG_ERR_SMB_CNT__W 16 +#define B_EC_RS_REG_ERR_SMB_CNT__M 0xFFFF +#define B_EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF + + +#define B_EC_RS_REG_ERR_BIT_CNT__A 0x2130014 +#define B_EC_RS_REG_ERR_BIT_CNT__W 16 +#define B_EC_RS_REG_ERR_BIT_CNT__M 0xFFFF +#define B_EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF + + +#define B_EC_RS_REG_IN_PCK_CNT__A 0x2130015 +#define B_EC_RS_REG_IN_PCK_CNT__W 16 +#define B_EC_RS_REG_IN_PCK_CNT__M 0xFFFF +#define B_EC_RS_REG_IN_PCK_CNT_INIT 0x0 + + + +#define B_EC_RS_EC_RAM__A 0x2140000 + + + + + +#define B_EC_OC_SID 0x1A + + + + + + +#define B_EC_OC_REG_COMM_EXEC__A 0x2150000 +#define B_EC_OC_REG_COMM_EXEC__W 3 +#define B_EC_OC_REG_COMM_EXEC__M 0x7 +#define B_EC_OC_REG_COMM_EXEC_CTL__B 0 +#define B_EC_OC_REG_COMM_EXEC_CTL__W 3 +#define B_EC_OC_REG_COMM_EXEC_CTL__M 0x7 +#define B_EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_EC_OC_REG_COMM_STATE__A 0x2150001 +#define B_EC_OC_REG_COMM_STATE__W 4 +#define B_EC_OC_REG_COMM_STATE__M 0xF + +#define B_EC_OC_REG_COMM_MB__A 0x2150002 +#define B_EC_OC_REG_COMM_MB__W 2 +#define B_EC_OC_REG_COMM_MB__M 0x3 +#define B_EC_OC_REG_COMM_MB_CTR__B 0 +#define B_EC_OC_REG_COMM_MB_CTR__W 1 +#define B_EC_OC_REG_COMM_MB_CTR__M 0x1 +#define B_EC_OC_REG_COMM_MB_CTR_OFF 0x0 +#define B_EC_OC_REG_COMM_MB_CTR_ON 0x1 +#define B_EC_OC_REG_COMM_MB_OBS__B 1 +#define B_EC_OC_REG_COMM_MB_OBS__W 1 +#define B_EC_OC_REG_COMM_MB_OBS__M 0x2 +#define B_EC_OC_REG_COMM_MB_OBS_OFF 0x0 +#define B_EC_OC_REG_COMM_MB_OBS_ON 0x2 + + +#define B_EC_OC_REG_COMM_SERVICE0__A 0x2150003 +#define B_EC_OC_REG_COMM_SERVICE0__W 10 +#define B_EC_OC_REG_COMM_SERVICE0__M 0x3FF + +#define B_EC_OC_REG_COMM_SERVICE1__A 0x2150004 +#define B_EC_OC_REG_COMM_SERVICE1__W 11 +#define B_EC_OC_REG_COMM_SERVICE1__M 0x7FF + +#define B_EC_OC_REG_COMM_INT_STA__A 0x2150007 +#define B_EC_OC_REG_COMM_INT_STA__W 6 +#define B_EC_OC_REG_COMM_INT_STA__M 0x3F +#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 +#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 +#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 +#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 +#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 +#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 +#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 +#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 +#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 +#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 +#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 +#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 +#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 +#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 +#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 + + +#define B_EC_OC_REG_COMM_INT_MSK__A 0x2150008 +#define B_EC_OC_REG_COMM_INT_MSK__W 6 +#define B_EC_OC_REG_COMM_INT_MSK__M 0x3F +#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 +#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 +#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 +#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 +#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 +#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 + + +#define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 +#define B_EC_OC_REG_OC_MODE_LOP__W 16 +#define B_EC_OC_REG_OC_MODE_LOP__M 0xFFFF +#define B_EC_OC_REG_OC_MODE_LOP_INIT 0x0 + +#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 +#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 +#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 + +#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 +#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 +#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 + +#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 +#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 +#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 + +#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 +#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 +#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 + +#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 +#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 +#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 + + +#define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 +#define B_EC_OC_REG_OC_MODE_HIP__W 15 +#define B_EC_OC_REG_OC_MODE_HIP__M 0x7FFF +#define B_EC_OC_REG_OC_MODE_HIP_INIT 0x5 + +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 + +#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 +#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 +#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 + +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 + +#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 +#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 +#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 + +#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 +#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 +#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 + +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 + +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 + +#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__B 14 +#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__M 0x4000 +#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_ZER 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_CLC 0x4000 + + +#define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 +#define B_EC_OC_REG_OC_MPG_SIO__W 12 +#define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF +#define B_EC_OC_REG_OC_MPG_SIO_INIT 0xFFF + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 + + +#define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 +#define B_EC_OC_REG_DTO_INC_LOP__W 16 +#define B_EC_OC_REG_DTO_INC_LOP__M 0xFFFF +#define B_EC_OC_REG_DTO_INC_LOP_INIT 0x0 + + +#define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 +#define B_EC_OC_REG_DTO_INC_HIP__W 8 +#define B_EC_OC_REG_DTO_INC_HIP__M 0xFF +#define B_EC_OC_REG_DTO_INC_HIP_INIT 0xC0 + + +#define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 +#define B_EC_OC_REG_SNC_ISC_LVL__W 12 +#define B_EC_OC_REG_SNC_ISC_LVL__M 0xFFF +#define B_EC_OC_REG_SNC_ISC_LVL_INIT 0x422 + +#define B_EC_OC_REG_SNC_ISC_LVL_ISC__B 0 +#define B_EC_OC_REG_SNC_ISC_LVL_ISC__W 4 +#define B_EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF + +#define B_EC_OC_REG_SNC_ISC_LVL_OSC__B 4 +#define B_EC_OC_REG_SNC_ISC_LVL_OSC__W 4 +#define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 + +#define B_EC_OC_REG_SNC_ISC_LVL_NSC__B 8 +#define B_EC_OC_REG_SNC_ISC_LVL_NSC__W 4 +#define B_EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 + + +#define B_EC_OC_REG_SNC_NSC_LVL__A 0x2150017 +#define B_EC_OC_REG_SNC_NSC_LVL__W 8 +#define B_EC_OC_REG_SNC_NSC_LVL__M 0xFF +#define B_EC_OC_REG_SNC_NSC_LVL_INIT 0x0 + + +#define B_EC_OC_REG_SNC_SNC_MODE__A 0x2150019 +#define B_EC_OC_REG_SNC_SNC_MODE__W 2 +#define B_EC_OC_REG_SNC_SNC_MODE__M 0x3 +#define B_EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 +#define B_EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 +#define B_EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 + + +#define B_EC_OC_REG_SNC_PCK_NMB__A 0x215001A +#define B_EC_OC_REG_SNC_PCK_NMB__W 16 +#define B_EC_OC_REG_SNC_PCK_NMB__M 0xFFFF + +#define B_EC_OC_REG_SNC_PCK_CNT__A 0x215001B +#define B_EC_OC_REG_SNC_PCK_CNT__W 16 +#define B_EC_OC_REG_SNC_PCK_CNT__M 0xFFFF + +#define B_EC_OC_REG_SNC_PCK_ERR__A 0x215001C +#define B_EC_OC_REG_SNC_PCK_ERR__W 16 +#define B_EC_OC_REG_SNC_PCK_ERR__M 0xFFFF + +#define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D +#define B_EC_OC_REG_TMD_TOP_MODE__W 2 +#define B_EC_OC_REG_TMD_TOP_MODE__M 0x3 +#define B_EC_OC_REG_TMD_TOP_MODE_INIT 0x3 +#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 +#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 +#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 +#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 + + +#define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E +#define B_EC_OC_REG_TMD_TOP_CNT__W 10 +#define B_EC_OC_REG_TMD_TOP_CNT__M 0x3FF +#define B_EC_OC_REG_TMD_TOP_CNT_INIT 0x1F4 + + +#define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F +#define B_EC_OC_REG_TMD_HIL_MAR__W 10 +#define B_EC_OC_REG_TMD_HIL_MAR__M 0x3FF +#define B_EC_OC_REG_TMD_HIL_MAR_INIT 0x3C0 + + +#define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 +#define B_EC_OC_REG_TMD_LOL_MAR__W 10 +#define B_EC_OC_REG_TMD_LOL_MAR__M 0x3FF +#define B_EC_OC_REG_TMD_LOL_MAR_INIT 0x40 + + +#define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 +#define B_EC_OC_REG_TMD_CUR_CNT__W 4 +#define B_EC_OC_REG_TMD_CUR_CNT__M 0xF +#define B_EC_OC_REG_TMD_CUR_CNT_INIT 0x3 + + +#define B_EC_OC_REG_TMD_IUR_CNT__A 0x2150022 +#define B_EC_OC_REG_TMD_IUR_CNT__W 4 +#define B_EC_OC_REG_TMD_IUR_CNT__M 0xF +#define B_EC_OC_REG_TMD_IUR_CNT_INIT 0x0 + + +#define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 +#define B_EC_OC_REG_AVR_ASH_CNT__W 4 +#define B_EC_OC_REG_AVR_ASH_CNT__M 0xF +#define B_EC_OC_REG_AVR_ASH_CNT_INIT 0x6 + + +#define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 +#define B_EC_OC_REG_AVR_BSH_CNT__W 4 +#define B_EC_OC_REG_AVR_BSH_CNT__M 0xF +#define B_EC_OC_REG_AVR_BSH_CNT_INIT 0x2 + + +#define B_EC_OC_REG_AVR_AVE_LOP__A 0x2150025 +#define B_EC_OC_REG_AVR_AVE_LOP__W 16 +#define B_EC_OC_REG_AVR_AVE_LOP__M 0xFFFF + +#define B_EC_OC_REG_AVR_AVE_HIP__A 0x2150026 +#define B_EC_OC_REG_AVR_AVE_HIP__W 5 +#define B_EC_OC_REG_AVR_AVE_HIP__M 0x1F + +#define B_EC_OC_REG_RCN_MODE__A 0x2150027 +#define B_EC_OC_REG_RCN_MODE__W 3 +#define B_EC_OC_REG_RCN_MODE__M 0x7 +#define B_EC_OC_REG_RCN_MODE_INIT 0x7 + +#define B_EC_OC_REG_RCN_MODE_MODE_0__B 0 +#define B_EC_OC_REG_RCN_MODE_MODE_0__W 1 +#define B_EC_OC_REG_RCN_MODE_MODE_0__M 0x1 +#define B_EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 +#define B_EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 + +#define B_EC_OC_REG_RCN_MODE_MODE_1__B 1 +#define B_EC_OC_REG_RCN_MODE_MODE_1__W 1 +#define B_EC_OC_REG_RCN_MODE_MODE_1__M 0x2 +#define B_EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 +#define B_EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 + +#define B_EC_OC_REG_RCN_MODE_MODE_2__B 2 +#define B_EC_OC_REG_RCN_MODE_MODE_2__W 1 +#define B_EC_OC_REG_RCN_MODE_MODE_2__M 0x4 +#define B_EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 +#define B_EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 + + +#define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 +#define B_EC_OC_REG_RCN_CRA_LOP__W 16 +#define B_EC_OC_REG_RCN_CRA_LOP__M 0xFFFF +#define B_EC_OC_REG_RCN_CRA_LOP_INIT 0x0 + + +#define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 +#define B_EC_OC_REG_RCN_CRA_HIP__W 8 +#define B_EC_OC_REG_RCN_CRA_HIP__M 0xFF +#define B_EC_OC_REG_RCN_CRA_HIP_INIT 0xC0 + + +#define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A +#define B_EC_OC_REG_RCN_CST_LOP__W 16 +#define B_EC_OC_REG_RCN_CST_LOP__M 0xFFFF +#define B_EC_OC_REG_RCN_CST_LOP_INIT 0x1000 + + +#define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B +#define B_EC_OC_REG_RCN_CST_HIP__W 8 +#define B_EC_OC_REG_RCN_CST_HIP__M 0xFF +#define B_EC_OC_REG_RCN_CST_HIP_INIT 0x0 + + +#define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C +#define B_EC_OC_REG_RCN_SET_LVL__W 9 +#define B_EC_OC_REG_RCN_SET_LVL__M 0x1FF +#define B_EC_OC_REG_RCN_SET_LVL_INIT 0x1FF + + +#define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D +#define B_EC_OC_REG_RCN_GAI_LVL__W 4 +#define B_EC_OC_REG_RCN_GAI_LVL__M 0xF +#define B_EC_OC_REG_RCN_GAI_LVL_INIT 0xA + + +#define B_EC_OC_REG_RCN_DRA_LOP__A 0x215002E +#define B_EC_OC_REG_RCN_DRA_LOP__W 16 +#define B_EC_OC_REG_RCN_DRA_LOP__M 0xFFFF + +#define B_EC_OC_REG_RCN_DRA_HIP__A 0x215002F +#define B_EC_OC_REG_RCN_DRA_HIP__W 8 +#define B_EC_OC_REG_RCN_DRA_HIP__M 0xFF + +#define B_EC_OC_REG_RCN_DOF_LOP__A 0x2150030 +#define B_EC_OC_REG_RCN_DOF_LOP__W 16 +#define B_EC_OC_REG_RCN_DOF_LOP__M 0xFFFF + +#define B_EC_OC_REG_RCN_DOF_HIP__A 0x2150031 +#define B_EC_OC_REG_RCN_DOF_HIP__W 8 +#define B_EC_OC_REG_RCN_DOF_HIP__M 0xFF + +#define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032 +#define B_EC_OC_REG_RCN_CLP_LOP__W 16 +#define B_EC_OC_REG_RCN_CLP_LOP__M 0xFFFF +#define B_EC_OC_REG_RCN_CLP_LOP_INIT 0x0 + + +#define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 +#define B_EC_OC_REG_RCN_CLP_HIP__W 8 +#define B_EC_OC_REG_RCN_CLP_HIP__M 0xFF +#define B_EC_OC_REG_RCN_CLP_HIP_INIT 0xC0 + + +#define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 +#define B_EC_OC_REG_RCN_MAP_LOP__W 16 +#define B_EC_OC_REG_RCN_MAP_LOP__M 0xFFFF + +#define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035 +#define B_EC_OC_REG_RCN_MAP_HIP__W 8 +#define B_EC_OC_REG_RCN_MAP_HIP__M 0xFF + +#define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036 +#define B_EC_OC_REG_OCR_MPG_UOS__W 12 +#define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF +#define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 + +#define B_EC_OC_REG_OCR_MPG_UOS_ERR__B 8 +#define B_EC_OC_REG_OCR_MPG_UOS_ERR__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 +#define B_EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 + +#define B_EC_OC_REG_OCR_MPG_UOS_STR__B 9 +#define B_EC_OC_REG_OCR_MPG_UOS_STR__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 +#define B_EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 + +#define B_EC_OC_REG_OCR_MPG_UOS_VAL__B 10 +#define B_EC_OC_REG_OCR_MPG_UOS_VAL__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 +#define B_EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 + +#define B_EC_OC_REG_OCR_MPG_UOS_CLK__B 11 +#define B_EC_OC_REG_OCR_MPG_UOS_CLK__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 +#define B_EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 + + +#define B_EC_OC_REG_OCR_MPG_WRI__A 0x2150037 +#define B_EC_OC_REG_OCR_MPG_WRI__W 12 +#define B_EC_OC_REG_OCR_MPG_WRI__M 0xFFF +#define B_EC_OC_REG_OCR_MPG_WRI_INIT 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 +#define B_EC_OC_REG_OCR_MPG_WRI_ERR__B 8 +#define B_EC_OC_REG_OCR_MPG_WRI_ERR__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 +#define B_EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 +#define B_EC_OC_REG_OCR_MPG_WRI_STR__B 9 +#define B_EC_OC_REG_OCR_MPG_WRI_STR__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 +#define B_EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 +#define B_EC_OC_REG_OCR_MPG_WRI_VAL__B 10 +#define B_EC_OC_REG_OCR_MPG_WRI_VAL__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 +#define B_EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 +#define B_EC_OC_REG_OCR_MPG_WRI_CLK__B 11 +#define B_EC_OC_REG_OCR_MPG_WRI_CLK__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 +#define B_EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 + + +#define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 +#define B_EC_OC_REG_OCR_MPG_USR_DAT__W 12 +#define B_EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF + +#define B_EC_OC_REG_OCR_MON_CNT__A 0x215003C +#define B_EC_OC_REG_OCR_MON_CNT__W 14 +#define B_EC_OC_REG_OCR_MON_CNT__M 0x3FFF +#define B_EC_OC_REG_OCR_MON_CNT_INIT 0x0 + + +#define B_EC_OC_REG_OCR_MON_RDX__A 0x215003D +#define B_EC_OC_REG_OCR_MON_RDX__W 1 +#define B_EC_OC_REG_OCR_MON_RDX__M 0x1 +#define B_EC_OC_REG_OCR_MON_RDX_INIT 0x0 + + +#define B_EC_OC_REG_OCR_MON_RD0__A 0x215003E +#define B_EC_OC_REG_OCR_MON_RD0__W 10 +#define B_EC_OC_REG_OCR_MON_RD0__M 0x3FF + +#define B_EC_OC_REG_OCR_MON_RD1__A 0x215003F +#define B_EC_OC_REG_OCR_MON_RD1__W 10 +#define B_EC_OC_REG_OCR_MON_RD1__M 0x3FF + +#define B_EC_OC_REG_OCR_MON_RD2__A 0x2150040 +#define B_EC_OC_REG_OCR_MON_RD2__W 10 +#define B_EC_OC_REG_OCR_MON_RD2__M 0x3FF + +#define B_EC_OC_REG_OCR_MON_RD3__A 0x2150041 +#define B_EC_OC_REG_OCR_MON_RD3__W 10 +#define B_EC_OC_REG_OCR_MON_RD3__M 0x3FF + +#define B_EC_OC_REG_OCR_MON_RD4__A 0x2150042 +#define B_EC_OC_REG_OCR_MON_RD4__W 10 +#define B_EC_OC_REG_OCR_MON_RD4__M 0x3FF + +#define B_EC_OC_REG_OCR_MON_RD5__A 0x2150043 +#define B_EC_OC_REG_OCR_MON_RD5__W 10 +#define B_EC_OC_REG_OCR_MON_RD5__M 0x3FF + +#define B_EC_OC_REG_OCR_INV_MON__A 0x2150044 +#define B_EC_OC_REG_OCR_INV_MON__W 12 +#define B_EC_OC_REG_OCR_INV_MON__M 0xFFF +#define B_EC_OC_REG_OCR_INV_MON_INIT 0x0 + + +#define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 +#define B_EC_OC_REG_IPR_INV_MPG__W 12 +#define B_EC_OC_REG_IPR_INV_MPG__M 0xFFF +#define B_EC_OC_REG_IPR_INV_MPG_INIT 0x0 + + +#define B_EC_OC_REG_IPR_MSR_SNC__A 0x2150046 +#define B_EC_OC_REG_IPR_MSR_SNC__W 6 +#define B_EC_OC_REG_IPR_MSR_SNC__M 0x3F +#define B_EC_OC_REG_IPR_MSR_SNC_INIT 0x0 + + +#define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 +#define B_EC_OC_REG_DTO_CLKMODE__W 2 +#define B_EC_OC_REG_DTO_CLKMODE__M 0x3 +#define B_EC_OC_REG_DTO_CLKMODE_INIT 0x2 + +#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__B 0 +#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__W 1 +#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__M 0x1 +#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_EVEN_ODD 0x0 +#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_ODD_EVEN 0x1 + +#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__B 1 +#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__W 1 +#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__M 0x2 +#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_SERIAL_MODE 0x0 +#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_PARALLEL_MODE 0x2 + + +#define B_EC_OC_REG_DTO_PER__A 0x2150048 +#define B_EC_OC_REG_DTO_PER__W 8 +#define B_EC_OC_REG_DTO_PER__M 0xFF +#define B_EC_OC_REG_DTO_PER_INIT 0x6 + + +#define B_EC_OC_REG_DTO_BUR__A 0x2150049 +#define B_EC_OC_REG_DTO_BUR__W 2 +#define B_EC_OC_REG_DTO_BUR__M 0x3 +#define B_EC_OC_REG_DTO_BUR_INIT 0x1 +#define B_EC_OC_REG_DTO_BUR_SELECT_1 0x0 +#define B_EC_OC_REG_DTO_BUR_SELECT_188 0x1 +#define B_EC_OC_REG_DTO_BUR_SELECT_204 0x2 +#define B_EC_OC_REG_DTO_BUR_SELECT_47 0x3 + + +#define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A +#define B_EC_OC_REG_RCR_CLKMODE__W 3 +#define B_EC_OC_REG_RCR_CLKMODE__M 0x7 +#define B_EC_OC_REG_RCR_CLKMODE_INIT 0x0 + +#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__B 0 +#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__W 1 +#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__M 0x1 +#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_FRACIONAL 0x0 +#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_RATIONAL 0x1 + +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__B 1 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__W 1 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__M 0x2 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_FRACTIONAL 0x0 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_RATIONAL 0x2 + +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__B 2 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__W 1 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__M 0x4 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FIFO 0x0 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FEEDBACKLOOP 0x4 + + + +#define B_EC_OC_RAM__A 0x2160000 + + + + + +#define B_CC_SID 0x1B + + + + + +#define B_CC_COMM_EXEC__A 0x2400000 +#define B_CC_COMM_EXEC__W 3 +#define B_CC_COMM_EXEC__M 0x7 +#define B_CC_COMM_EXEC_CTL__B 0 +#define B_CC_COMM_EXEC_CTL__W 3 +#define B_CC_COMM_EXEC_CTL__M 0x7 +#define B_CC_COMM_EXEC_CTL_STOP 0x0 +#define B_CC_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CC_COMM_EXEC_CTL_HOLD 0x2 +#define B_CC_COMM_EXEC_CTL_STEP 0x3 +#define B_CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_CC_COMM_STATE__A 0x2400001 +#define B_CC_COMM_STATE__W 16 +#define B_CC_COMM_STATE__M 0xFFFF +#define B_CC_COMM_MB__A 0x2400002 +#define B_CC_COMM_MB__W 16 +#define B_CC_COMM_MB__M 0xFFFF +#define B_CC_COMM_SERVICE0__A 0x2400003 +#define B_CC_COMM_SERVICE0__W 16 +#define B_CC_COMM_SERVICE0__M 0xFFFF +#define B_CC_COMM_SERVICE1__A 0x2400004 +#define B_CC_COMM_SERVICE1__W 16 +#define B_CC_COMM_SERVICE1__M 0xFFFF +#define B_CC_COMM_INT_STA__A 0x2400007 +#define B_CC_COMM_INT_STA__W 16 +#define B_CC_COMM_INT_STA__M 0xFFFF +#define B_CC_COMM_INT_MSK__A 0x2400008 +#define B_CC_COMM_INT_MSK__W 16 +#define B_CC_COMM_INT_MSK__M 0xFFFF + + + + + + + +#define B_CC_REG_COMM_EXEC__A 0x2410000 +#define B_CC_REG_COMM_EXEC__W 3 +#define B_CC_REG_COMM_EXEC__M 0x7 +#define B_CC_REG_COMM_EXEC_CTL__B 0 +#define B_CC_REG_COMM_EXEC_CTL__W 3 +#define B_CC_REG_COMM_EXEC_CTL__M 0x7 +#define B_CC_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CC_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_CC_REG_COMM_EXEC_CTL_STEP 0x3 +#define B_CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_CC_REG_COMM_STATE__A 0x2410001 +#define B_CC_REG_COMM_STATE__W 16 +#define B_CC_REG_COMM_STATE__M 0xFFFF +#define B_CC_REG_COMM_MB__A 0x2410002 +#define B_CC_REG_COMM_MB__W 16 +#define B_CC_REG_COMM_MB__M 0xFFFF +#define B_CC_REG_COMM_SERVICE0__A 0x2410003 +#define B_CC_REG_COMM_SERVICE0__W 16 +#define B_CC_REG_COMM_SERVICE0__M 0xFFFF +#define B_CC_REG_COMM_SERVICE1__A 0x2410004 +#define B_CC_REG_COMM_SERVICE1__W 16 +#define B_CC_REG_COMM_SERVICE1__M 0xFFFF +#define B_CC_REG_COMM_INT_STA__A 0x2410007 +#define B_CC_REG_COMM_INT_STA__W 16 +#define B_CC_REG_COMM_INT_STA__M 0xFFFF +#define B_CC_REG_COMM_INT_MSK__A 0x2410008 +#define B_CC_REG_COMM_INT_MSK__W 16 +#define B_CC_REG_COMM_INT_MSK__M 0xFFFF + +#define B_CC_REG_OSC_MODE__A 0x2410010 +#define B_CC_REG_OSC_MODE__W 2 +#define B_CC_REG_OSC_MODE__M 0x3 +#define B_CC_REG_OSC_MODE_OHW 0x0 +#define B_CC_REG_OSC_MODE_M20 0x1 +#define B_CC_REG_OSC_MODE_M48 0x2 + + +#define B_CC_REG_PLL_MODE__A 0x2410011 +#define B_CC_REG_PLL_MODE__W 6 +#define B_CC_REG_PLL_MODE__M 0x3F +#define B_CC_REG_PLL_MODE_INIT 0xC +#define B_CC_REG_PLL_MODE_BYPASS__B 0 +#define B_CC_REG_PLL_MODE_BYPASS__W 2 +#define B_CC_REG_PLL_MODE_BYPASS__M 0x3 +#define B_CC_REG_PLL_MODE_BYPASS_OHW 0x0 +#define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1 +#define B_CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 +#define B_CC_REG_PLL_MODE_PUMP__B 2 +#define B_CC_REG_PLL_MODE_PUMP__W 3 +#define B_CC_REG_PLL_MODE_PUMP__M 0x1C +#define B_CC_REG_PLL_MODE_PUMP_OFF 0x0 +#define B_CC_REG_PLL_MODE_PUMP_CUR_08 0x4 +#define B_CC_REG_PLL_MODE_PUMP_CUR_09 0x8 +#define B_CC_REG_PLL_MODE_PUMP_CUR_10 0xC +#define B_CC_REG_PLL_MODE_PUMP_CUR_11 0x10 +#define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14 +#define B_CC_REG_PLL_MODE_OUT_EN__B 5 +#define B_CC_REG_PLL_MODE_OUT_EN__W 1 +#define B_CC_REG_PLL_MODE_OUT_EN__M 0x20 +#define B_CC_REG_PLL_MODE_OUT_EN_OFF 0x0 +#define B_CC_REG_PLL_MODE_OUT_EN_ON 0x20 + + +#define B_CC_REG_REF_DIVIDE__A 0x2410012 +#define B_CC_REG_REF_DIVIDE__W 4 +#define B_CC_REG_REF_DIVIDE__M 0xF +#define B_CC_REG_REF_DIVIDE_INIT 0xA +#define B_CC_REG_REF_DIVIDE_OHW 0x0 +#define B_CC_REG_REF_DIVIDE_D01 0x1 +#define B_CC_REG_REF_DIVIDE_D02 0x2 +#define B_CC_REG_REF_DIVIDE_D03 0x3 +#define B_CC_REG_REF_DIVIDE_D04 0x4 +#define B_CC_REG_REF_DIVIDE_D05 0x5 +#define B_CC_REG_REF_DIVIDE_D06 0x6 +#define B_CC_REG_REF_DIVIDE_D07 0x7 +#define B_CC_REG_REF_DIVIDE_D08 0x8 +#define B_CC_REG_REF_DIVIDE_D09 0x9 +#define B_CC_REG_REF_DIVIDE_D10 0xA + + +#define B_CC_REG_REF_DELAY__A 0x2410013 +#define B_CC_REG_REF_DELAY__W 3 +#define B_CC_REG_REF_DELAY__M 0x7 +#define B_CC_REG_REF_DELAY_EDGE__B 0 +#define B_CC_REG_REF_DELAY_EDGE__W 1 +#define B_CC_REG_REF_DELAY_EDGE__M 0x1 +#define B_CC_REG_REF_DELAY_EDGE_POS 0x0 +#define B_CC_REG_REF_DELAY_EDGE_NEG 0x1 +#define B_CC_REG_REF_DELAY_DELAY__B 1 +#define B_CC_REG_REF_DELAY_DELAY__W 2 +#define B_CC_REG_REF_DELAY_DELAY__M 0x6 +#define B_CC_REG_REF_DELAY_DELAY_DEL_0 0x0 +#define B_CC_REG_REF_DELAY_DELAY_DEL_3 0x2 +#define B_CC_REG_REF_DELAY_DELAY_DEL_6 0x4 +#define B_CC_REG_REF_DELAY_DELAY_DEL_9 0x6 + + +#define B_CC_REG_CLK_DELAY__A 0x2410014 +#define B_CC_REG_CLK_DELAY__W 5 +#define B_CC_REG_CLK_DELAY__M 0x1F +#define B_CC_REG_CLK_DELAY_DELAY__B 0 +#define B_CC_REG_CLK_DELAY_DELAY__W 4 +#define B_CC_REG_CLK_DELAY_DELAY__M 0xF +#define B_CC_REG_CLK_DELAY_DELAY_DEL_00 0x0 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_05 0x1 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_10 0x2 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_15 0x3 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_20 0x4 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_25 0x5 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_30 0x6 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_35 0x7 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_40 0x8 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_45 0x9 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_50 0xA +#define B_CC_REG_CLK_DELAY_DELAY_DEL_55 0xB +#define B_CC_REG_CLK_DELAY_DELAY_DEL_60 0xC +#define B_CC_REG_CLK_DELAY_DELAY_DEL_65 0xD +#define B_CC_REG_CLK_DELAY_DELAY_DEL_70 0xE +#define B_CC_REG_CLK_DELAY_DELAY_DEL_75 0xF +#define B_CC_REG_CLK_DELAY_EDGE__B 4 +#define B_CC_REG_CLK_DELAY_EDGE__W 1 +#define B_CC_REG_CLK_DELAY_EDGE__M 0x10 +#define B_CC_REG_CLK_DELAY_EDGE_POS 0x0 +#define B_CC_REG_CLK_DELAY_EDGE_NEG 0x10 + + +#define B_CC_REG_PWD_MODE__A 0x2410015 +#define B_CC_REG_PWD_MODE__W 2 +#define B_CC_REG_PWD_MODE__M 0x3 +#define B_CC_REG_PWD_MODE_UP 0x0 +#define B_CC_REG_PWD_MODE_DOWN_CLK 0x1 +#define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 +#define B_CC_REG_PWD_MODE_DOWN_OSC 0x3 + + +#define B_CC_REG_SOFT_RST__A 0x2410016 +#define B_CC_REG_SOFT_RST__W 2 +#define B_CC_REG_SOFT_RST__M 0x3 +#define B_CC_REG_SOFT_RST_SYS__B 0 +#define B_CC_REG_SOFT_RST_SYS__W 1 +#define B_CC_REG_SOFT_RST_SYS__M 0x1 +#define B_CC_REG_SOFT_RST_OSC__B 1 +#define B_CC_REG_SOFT_RST_OSC__W 1 +#define B_CC_REG_SOFT_RST_OSC__M 0x2 + + +#define B_CC_REG_UPDATE__A 0x2410017 +#define B_CC_REG_UPDATE__W 16 +#define B_CC_REG_UPDATE__M 0xFFFF +#define B_CC_REG_UPDATE_KEY 0x3973 + + +#define B_CC_REG_PLL_LOCK__A 0x2410018 +#define B_CC_REG_PLL_LOCK__W 1 +#define B_CC_REG_PLL_LOCK__M 0x1 +#define B_CC_REG_PLL_LOCK_LOCK 0x1 + + +#define B_CC_REG_JTAGID_L__A 0x2410019 +#define B_CC_REG_JTAGID_L__W 16 +#define B_CC_REG_JTAGID_L__M 0xFFFF +#define B_CC_REG_JTAGID_L_INIT 0x0 + + +#define B_CC_REG_JTAGID_H__A 0x241001A +#define B_CC_REG_JTAGID_H__W 16 +#define B_CC_REG_JTAGID_H__M 0xFFFF +#define B_CC_REG_JTAGID_H_INIT 0x0 + + +#define B_CC_REG_DIVERSITY__A 0x241001B +#define B_CC_REG_DIVERSITY__W 1 +#define B_CC_REG_DIVERSITY__M 0x1 +#define B_CC_REG_DIVERSITY_INIT 0x0 + + +#define B_CC_REG_BACKUP3V__A 0x241001C +#define B_CC_REG_BACKUP3V__W 1 +#define B_CC_REG_BACKUP3V__M 0x1 +#define B_CC_REG_BACKUP3V_INIT 0x0 + + +#define B_CC_REG_DRV_IO__A 0x241001D +#define B_CC_REG_DRV_IO__W 3 +#define B_CC_REG_DRV_IO__M 0x7 +#define B_CC_REG_DRV_IO_INIT 0x2 + + +#define B_CC_REG_DRV_MPG__A 0x241001E +#define B_CC_REG_DRV_MPG__W 3 +#define B_CC_REG_DRV_MPG__M 0x7 +#define B_CC_REG_DRV_MPG_INIT 0x2 + + +#define B_CC_REG_DRV_I2C1__A 0x241001F +#define B_CC_REG_DRV_I2C1__W 3 +#define B_CC_REG_DRV_I2C1__M 0x7 +#define B_CC_REG_DRV_I2C1_INIT 0x2 + + +#define B_CC_REG_DRV_I2C2__A 0x2410020 +#define B_CC_REG_DRV_I2C2__W 1 +#define B_CC_REG_DRV_I2C2__M 0x1 +#define B_CC_REG_DRV_I2C2_INIT 0x0 + + + + + +#define B_LC_SID 0x1C + + + + + +#define B_LC_COMM_EXEC__A 0x2800000 +#define B_LC_COMM_EXEC__W 3 +#define B_LC_COMM_EXEC__M 0x7 +#define B_LC_COMM_EXEC_CTL__B 0 +#define B_LC_COMM_EXEC_CTL__W 3 +#define B_LC_COMM_EXEC_CTL__M 0x7 +#define B_LC_COMM_EXEC_CTL_STOP 0x0 +#define B_LC_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_LC_COMM_EXEC_CTL_HOLD 0x2 +#define B_LC_COMM_EXEC_CTL_STEP 0x3 +#define B_LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_LC_COMM_STATE__A 0x2800001 +#define B_LC_COMM_STATE__W 16 +#define B_LC_COMM_STATE__M 0xFFFF +#define B_LC_COMM_MB__A 0x2800002 +#define B_LC_COMM_MB__W 16 +#define B_LC_COMM_MB__M 0xFFFF +#define B_LC_COMM_SERVICE0__A 0x2800003 +#define B_LC_COMM_SERVICE0__W 16 +#define B_LC_COMM_SERVICE0__M 0xFFFF +#define B_LC_COMM_SERVICE1__A 0x2800004 +#define B_LC_COMM_SERVICE1__W 16 +#define B_LC_COMM_SERVICE1__M 0xFFFF +#define B_LC_COMM_INT_STA__A 0x2800007 +#define B_LC_COMM_INT_STA__W 16 +#define B_LC_COMM_INT_STA__M 0xFFFF +#define B_LC_COMM_INT_MSK__A 0x2800008 +#define B_LC_COMM_INT_MSK__W 16 +#define B_LC_COMM_INT_MSK__M 0xFFFF + + + + + + +#define B_LC_CT_REG_COMM_EXEC__A 0x2810000 +#define B_LC_CT_REG_COMM_EXEC__W 3 +#define B_LC_CT_REG_COMM_EXEC__M 0x7 +#define B_LC_CT_REG_COMM_EXEC_CTL__B 0 +#define B_LC_CT_REG_COMM_EXEC_CTL__W 3 +#define B_LC_CT_REG_COMM_EXEC_CTL__M 0x7 +#define B_LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 + + +#define B_LC_CT_REG_COMM_STATE__A 0x2810001 +#define B_LC_CT_REG_COMM_STATE__W 10 +#define B_LC_CT_REG_COMM_STATE__M 0x3FF +#define B_LC_CT_REG_COMM_SERVICE0__A 0x2810003 +#define B_LC_CT_REG_COMM_SERVICE0__W 16 +#define B_LC_CT_REG_COMM_SERVICE0__M 0xFFFF +#define B_LC_CT_REG_COMM_SERVICE1__A 0x2810004 +#define B_LC_CT_REG_COMM_SERVICE1__W 16 +#define B_LC_CT_REG_COMM_SERVICE1__M 0xFFFF +#define B_LC_CT_REG_COMM_SERVICE1_LC__B 12 +#define B_LC_CT_REG_COMM_SERVICE1_LC__W 1 +#define B_LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 + + +#define B_LC_CT_REG_COMM_INT_STA__A 0x2810007 +#define B_LC_CT_REG_COMM_INT_STA__W 1 +#define B_LC_CT_REG_COMM_INT_STA__M 0x1 +#define B_LC_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define B_LC_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define B_LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + + +#define B_LC_CT_REG_COMM_INT_MSK__A 0x2810008 +#define B_LC_CT_REG_COMM_INT_MSK__W 1 +#define B_LC_CT_REG_COMM_INT_MSK__M 0x1 +#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + + + + +#define B_LC_CT_REG_CTL_STK__AX 0x2810010 +#define B_LC_CT_REG_CTL_STK__XSZ 4 +#define B_LC_CT_REG_CTL_STK__W 10 +#define B_LC_CT_REG_CTL_STK__M 0x3FF + +#define B_LC_CT_REG_CTL_BPT_IDX__A 0x281001F +#define B_LC_CT_REG_CTL_BPT_IDX__W 1 +#define B_LC_CT_REG_CTL_BPT_IDX__M 0x1 + +#define B_LC_CT_REG_CTL_BPT__A 0x2810020 +#define B_LC_CT_REG_CTL_BPT__W 10 +#define B_LC_CT_REG_CTL_BPT__M 0x3FF + + + + + +#define B_LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 +#define B_LC_RA_RAM_PROC_DELAY_IF__W 16 +#define B_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF +#define B_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 +#define B_LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 +#define B_LC_RA_RAM_PROC_DELAY_FS__W 16 +#define B_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF +#define B_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 +#define B_LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 +#define B_LC_RA_RAM_LOCK_TH_CRMM__W 16 +#define B_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF +#define B_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 +#define B_LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 +#define B_LC_RA_RAM_LOCK_TH_SRMM__W 16 +#define B_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF +#define B_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 +#define B_LC_RA_RAM_LOCK_COUNT__A 0x282000A +#define B_LC_RA_RAM_LOCK_COUNT__W 16 +#define B_LC_RA_RAM_LOCK_COUNT__M 0xFFFF +#define B_LC_RA_RAM_CPRTOFS_NOM__A 0x282000B +#define B_LC_RA_RAM_CPRTOFS_NOM__W 16 +#define B_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF +#define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C +#define B_LC_RA_RAM_IFINCR_NOM_L__W 16 +#define B_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF +#define B_LC_RA_RAM_IFINCR_NOM_H__A 0x282000D +#define B_LC_RA_RAM_IFINCR_NOM_H__W 16 +#define B_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF +#define B_LC_RA_RAM_FSINCR_NOM_L__A 0x282000E +#define B_LC_RA_RAM_FSINCR_NOM_L__W 16 +#define B_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF +#define B_LC_RA_RAM_FSINCR_NOM_H__A 0x282000F +#define B_LC_RA_RAM_FSINCR_NOM_H__W 16 +#define B_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF +#define B_LC_RA_RAM_MODE_2K__A 0x2820010 +#define B_LC_RA_RAM_MODE_2K__W 16 +#define B_LC_RA_RAM_MODE_2K__M 0xFFFF +#define B_LC_RA_RAM_MODE_GUARD__A 0x2820011 +#define B_LC_RA_RAM_MODE_GUARD__W 16 +#define B_LC_RA_RAM_MODE_GUARD__M 0xFFFF +#define B_LC_RA_RAM_MODE_GUARD_32 0x0 +#define B_LC_RA_RAM_MODE_GUARD_16 0x1 +#define B_LC_RA_RAM_MODE_GUARD_8 0x2 +#define B_LC_RA_RAM_MODE_GUARD_4 0x3 + +#define B_LC_RA_RAM_MODE_ADJUST__A 0x2820012 +#define B_LC_RA_RAM_MODE_ADJUST__W 16 +#define B_LC_RA_RAM_MODE_ADJUST__M 0xFFFF +#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 +#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 +#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 +#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 +#define B_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 +#define B_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 +#define B_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 +#define B_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 +#define B_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 +#define B_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 +#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 +#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 +#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 +#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 +#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 +#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 +#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 +#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 +#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 +#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 + +#define B_LC_RA_RAM_RC_STS__A 0x2820014 +#define B_LC_RA_RAM_RC_STS__W 16 +#define B_LC_RA_RAM_RC_STS__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x2820018 +#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 +#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x2820019 +#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 +#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A +#define B_LC_RA_RAM_FILTER_SYM_SET__W 16 +#define B_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 +#define B_LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B +#define B_LC_RA_RAM_FILTER_SYM_CUR__W 16 +#define B_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 +#define B_LC_RA_RAM_DIVERSITY_DELAY__A 0x282001C +#define B_LC_RA_RAM_DIVERSITY_DELAY__W 16 +#define B_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF +#define B_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 +#define B_LC_RA_RAM_MAX_ABS_EXP__A 0x282001D +#define B_LC_RA_RAM_MAX_ABS_EXP__W 16 +#define B_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF +#define B_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 +#define B_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F +#define B_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 +#define B_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 +#define B_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 +#define B_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 +#define B_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 +#define B_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 +#define B_LC_RA_RAM_ACTUAL_PHASE__W 16 +#define B_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 +#define B_LC_RA_RAM_ACTUAL_DELAY__W 16 +#define B_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF +#define B_LC_RA_RAM_ADJUST_CRMM__A 0x2820024 +#define B_LC_RA_RAM_ADJUST_CRMM__W 16 +#define B_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF +#define B_LC_RA_RAM_ADJUST_SRMM__A 0x2820025 +#define B_LC_RA_RAM_ADJUST_SRMM__W 16 +#define B_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF +#define B_LC_RA_RAM_ADJUST_PHASE__A 0x2820026 +#define B_LC_RA_RAM_ADJUST_PHASE__W 16 +#define B_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF +#define B_LC_RA_RAM_ADJUST_DELAY__A 0x2820027 +#define B_LC_RA_RAM_ADJUST_DELAY__W 16 +#define B_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF + + + + + +#define B_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 +#define B_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 +#define B_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A +#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B +#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C +#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D +#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF + + + +#define B_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 +#define B_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 +#define B_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 +#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 +#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 +#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 +#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF + + + +#define B_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 +#define B_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 +#define B_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A +#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B +#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C +#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D +#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF + + + + + +#define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 +#define B_LC_RA_RAM_FILTER_CRMM_A__W 16 +#define B_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF +#define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 +#define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 +#define B_LC_RA_RAM_FILTER_CRMM_B__W 16 +#define B_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF +#define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 +#define B_LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 +#define B_LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 +#define B_LC_RA_RAM_FILTER_CRMM_Z1__W 16 +#define B_LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF +#define B_LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 +#define B_LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 +#define B_LC_RA_RAM_FILTER_CRMM_Z2__W 16 +#define B_LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF +#define B_LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 +#define B_LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 +#define B_LC_RA_RAM_FILTER_CRMM_TMP__W 16 +#define B_LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF + + + +#define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 +#define B_LC_RA_RAM_FILTER_SRMM_A__W 16 +#define B_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 +#define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 +#define B_LC_RA_RAM_FILTER_SRMM_B__W 16 +#define B_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 +#define B_LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A +#define B_LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 +#define B_LC_RA_RAM_FILTER_SRMM_Z1__W 16 +#define B_LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C +#define B_LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 +#define B_LC_RA_RAM_FILTER_SRMM_Z2__W 16 +#define B_LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E +#define B_LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 +#define B_LC_RA_RAM_FILTER_SRMM_TMP__W 16 +#define B_LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF + + + +#define B_LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 +#define B_LC_RA_RAM_FILTER_PHASE_A__W 16 +#define B_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF +#define B_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 +#define B_LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 +#define B_LC_RA_RAM_FILTER_PHASE_B__W 16 +#define B_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF +#define B_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 +#define B_LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 +#define B_LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 +#define B_LC_RA_RAM_FILTER_PHASE_Z1__W 16 +#define B_LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF +#define B_LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 +#define B_LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 +#define B_LC_RA_RAM_FILTER_PHASE_Z2__W 16 +#define B_LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF +#define B_LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 +#define B_LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 +#define B_LC_RA_RAM_FILTER_PHASE_TMP__W 16 +#define B_LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF + + + +#define B_LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 +#define B_LC_RA_RAM_FILTER_DELAY_A__W 16 +#define B_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF +#define B_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 +#define B_LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 +#define B_LC_RA_RAM_FILTER_DELAY_B__W 16 +#define B_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF +#define B_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 +#define B_LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A +#define B_LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 +#define B_LC_RA_RAM_FILTER_DELAY_Z1__W 16 +#define B_LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF +#define B_LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C +#define B_LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 +#define B_LC_RA_RAM_FILTER_DELAY_Z2__W 16 +#define B_LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF +#define B_LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E +#define B_LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 +#define B_LC_RA_RAM_FILTER_DELAY_TMP__W 16 +#define B_LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF + + + + + + +#define B_LC_IF_RAM_TRP_BPT0__AX 0x2830000 +#define B_LC_IF_RAM_TRP_BPT0__XSZ 2 +#define B_LC_IF_RAM_TRP_BPT0__W 12 +#define B_LC_IF_RAM_TRP_BPT0__M 0xFFF + +#define B_LC_IF_RAM_TRP_STKU__AX 0x2830002 +#define B_LC_IF_RAM_TRP_STKU__XSZ 2 +#define B_LC_IF_RAM_TRP_STKU__W 12 +#define B_LC_IF_RAM_TRP_STKU__M 0xFFF + +#define B_LC_IF_RAM_TRP_WARM__AX 0x2830006 +#define B_LC_IF_RAM_TRP_WARM__XSZ 2 +#define B_LC_IF_RAM_TRP_WARM__W 12 +#define B_LC_IF_RAM_TRP_WARM__M 0xFFF + +#ifdef __cplusplus +} +#endif + +#endif + + diff --git a/drivers/media/dvb/frontends/drxd_micro.h b/drivers/media/dvb/frontends/drxd_micro.h new file mode 100644 index 000000000000..237296d35e55 --- /dev/null +++ b/drivers/media/dvb/frontends/drxd_micro.h @@ -0,0 +1,1498 @@ +/*----------------------------------------------------------------------------- +* +* $(c) 2003-2007 Micronas GmbH. All rights reserved. +* +* This software and related documentation (the 'Software') are intellectual +* property owned by Micronas and are copyright of Micronas, unless specifically +* noted otherwise. +* +* Any use of the Software is permitted only pursuant to the terms of the +* license agreement, if any, which accompanies, is included with or applicable +* to the Software ('License Agreement') or upon express written consent of +* Micronas. Any copying, reproduction or redistribution of the Software in +* whole or in part by any means not in accordance with the License Agreement +* or as agreed in writing by Micronas is expressly prohibited. +* +* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE +* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE +* IS DELIVERED 'AS IS' AND MICRONAS HEREBY DISCLAIMS ALL WARRANTIES AND +* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES +* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT +* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL +* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY +* TO USE THE SOFTWARE. +* +* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, +* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, +* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS +* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE +* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM +* MICRONAS' NEGLIGENCE. $ +* +----------------------------------------------------------------------------*/ + + + +/* + Permission is granted by Micronas to distribute this file, either + in this form (hex-dump) or converted to a binary file, together + with the DRX397X Linux driver. +*/ + + +u8_t DRXD_A2_microcode[] = { +0x48, 0x4c, 0x00, 0x04, 0x00, 0x83, 0x00, 0x00, 0x10, 0x00, 0x00, 0x01, 0xe4, 0x47, 0xf6, 0x07, +0x11, 0x00, 0xf6, 0x07, 0x4a, 0x00, 0xf6, 0x07, 0x4c, 0x00, 0xf6, 0x07, 0xed, 0x07, 0xf6, 0x07, +0xf7, 0x07, 0xf6, 0x07, 0x9a, 0x04, 0xf6, 0x07, 0xf8, 0x04, 0x09, 0x00, 0xf6, 0x07, 0xe8, 0x04, +0xf7, 0x07, 0x13, 0x08, 0xc4, 0x07, 0x4b, 0x00, 0x00, 0x00, 0xc4, 0x07, 0xf3, 0x00, 0x0f, 0x04, +0x50, 0x00, 0x00, 0x06, 0xc4, 0x07, 0x20, 0x00, 0xfe, 0x01, 0xfd, 0x07, 0x21, 0x00, 0x02, 0x00, +0x02, 0x00, 0xc4, 0x07, 0x30, 0x00, 0xfe, 0x01, 0xfd, 0x07, 0x28, 0x00, 0x02, 0x00, 0x02, 0x00, +0xc4, 0x07, 0xc0, 0x00, 0xfe, 0x01, 0xfd, 0x07, 0x2f, 0x00, 0x02, 0x00, 0x02, 0x00, 0xc4, 0x07, +0x84, 0x00, 0x00, 0x00, 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0xb8, 0x0f, 0xde, 0x02, 0xb8, 0x0f, 0x02, 0x00, 0x40, 0x00, 0xc8, 0x07, +0x14, 0x00, 0xf9, 0x07, 0xbc, 0x03, 0x00, 0x00, 0x48, 0x00, 0xe2, 0x07, 0xc1, 0x00, 0xe3, 0x07, +0x12, 0x00, 0x60, 0x02, 0x55, 0x00, 0x08, 0x05, 0x3f, 0x00, 0x3f, 0x00, 0xf8, 0x0f, 0xc1, 0x03, +0xb8, 0x07, 0xc2, 0x07, 0x2e, 0x00, 0x2a, 0x04, 0xc2, 0x07, 0x68, 0x00, 0x00, 0x06, 0xc2, 0x07, +0x1a, 0x00, 0x6a, 0x04, 0x00, 0x06, 0xb8, 0x07, 0xc2, 0x07, 0x1a, 0x00, 0x6a, 0x04, 0x08, 0x06, +0x14, 0x00, 0xb8, 0x0f, 0x08, 0x04, 0x56, 0x00, 0x00, 0x05, 0xb8, 0x0f, 0x00, 0x06, 0xc2, 0x07, +0x68, 0x00, 0x08, 0x04, 0xd6, 0x02, 0x50, 0x00, 0x00, 0x05, 0x00, 0x0b, 0xb8, 0x07, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, +0x92, 0x00, 0x02, 0x82, 0x00, 0x00, 0x00, 0x80, 0x00, 0x01, 0x5b, 0x52, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe6, 0xff, 0xe3, 0xff, 0xc8, 0x00, 0x46, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0xe8, 0x03, 0x00, 0x00, 0xe8, 0x03, 0x10, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +u32_t DRXD_B1_microcode_length = (sizeof(DRXD_B1_microcode)); + -- cgit v1.2.3 From 949a12e3a87281e38d3520823e7e171bbe45b448 Mon Sep 17 00:00:00 2001 From: Devin Heitmueller <dheitmueller@kernellabs.com> Date: Sun, 13 Mar 2011 01:53:02 -0300 Subject: [media] drxd: add driver to Makefile and Kconfig Add the drxd to the Makefile and Kconfig Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/Kconfig | 11 +++++++++++ drivers/media/dvb/frontends/Makefile | 2 ++ 2 files changed, 13 insertions(+) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig index 83093d1f4f74..29ddeea2fffe 100644 --- a/drivers/media/dvb/frontends/Kconfig +++ b/drivers/media/dvb/frontends/Kconfig @@ -276,6 +276,17 @@ config DVB_DRX397XD download/extract them, and then copy them to /usr/lib/hotplug/firmware or /lib/firmware (depending on configuration of firmware hotplug). +config DVB_DRXD + tristate "Micronas DRXD driver" + depends on DVB_CORE && I2C + default m if DVB_FE_CUSTOMISE + help + A DVB-T tuner module. Say Y when you want to support this frontend. + + Note: this driver was based on vendor driver reference code (released + under the GPL) as opposed to the existing drx397xd driver, which + was written via reverse engineering. + config DVB_L64781 tristate "LSI L64781" depends on DVB_CORE && I2C diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile index 3b0c4bdc4b2b..fc08b6902a22 100644 --- a/drivers/media/dvb/frontends/Makefile +++ b/drivers/media/dvb/frontends/Makefile @@ -8,6 +8,7 @@ EXTRA_CFLAGS += -Idrivers/media/common/tuners/ stb0899-objs = stb0899_drv.o stb0899_algo.o stv0900-objs = stv0900_core.o stv0900_sw.o au8522-objs = au8522_dig.o au8522_decoder.o +drxd-objs = drxd_firm.o drxd_hard.o obj-$(CONFIG_DVB_PLL) += dvb-pll.o obj-$(CONFIG_DVB_STV0299) += stv0299.o @@ -37,6 +38,7 @@ obj-$(CONFIG_DVB_ZL10039) += zl10039.o obj-$(CONFIG_DVB_ZL10353) += zl10353.o obj-$(CONFIG_DVB_CX22702) += cx22702.o obj-$(CONFIG_DVB_DRX397XD) += drx397xD.o +obj-$(CONFIG_DVB_DRXD) += drxd.o obj-$(CONFIG_DVB_TDA10021) += tda10021.o obj-$(CONFIG_DVB_TDA10023) += tda10023.o obj-$(CONFIG_DVB_STV0297) += stv0297.o -- cgit v1.2.3 From ba96796544f3bfc53a3269f0cf65651e349f8033 Mon Sep 17 00:00:00 2001 From: Devin Heitmueller <dheitmueller@kernellabs.com> Date: Sun, 13 Mar 2011 01:54:02 -0300 Subject: [media] drxd: provide ability to control rs byte Provide the ability for the board configuration to specify whether to insert the RS byte into the TS interconnect to the bridge, while not required for the ngene in fact is required for the em28xx. Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd.h | 1 + drivers/media/dvb/frontends/drxd_hard.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h index 9b11dc835c44..81093b9b1568 100644 --- a/drivers/media/dvb/frontends/drxd.h +++ b/drivers/media/dvb/frontends/drxd.h @@ -38,6 +38,7 @@ struct drxd_config #define DRXD_PLL_MT3X0823 2 u32 clock; + u8 insert_rs_byte; u8 demod_address; u8 demoda_address; diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c index c4835b32e6d9..994195fe9fbb 100644 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -2449,7 +2449,7 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) state->tuner_mirrors=0; /* modify MPEG output attributes */ - state->insert_rs_byte = 0; + state->insert_rs_byte = state->config.insert_rs_byte; state->enable_parallel = (ulSerialMode != 1); /* Timing div, 250ns/Psys */ -- cgit v1.2.3 From 6b142b3c81e6e532dfad7256fcc7e75fded49245 Mon Sep 17 00:00:00 2001 From: Devin Heitmueller <dheitmueller@kernellabs.com> Date: Sun, 13 Mar 2011 02:02:01 -0300 Subject: [media] drxd: provide ability to disable the i2c gate control function If the tuner is not actually behind an i2c gate, using the i2c gate control function can wedge the i2c bus. Provide the ability to control on a per-board basis whether it should be used. Problem was noticed on the HVR-900 R2, where it resulted in the first tuning attempt succeeding, and then all subsequent attempts to access the xc3028 being treated as failures (including the call to sleep the tuner). Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd.h | 4 ++++ drivers/media/dvb/frontends/drxd_hard.c | 3 +++ drivers/media/video/em28xx/em28xx-dvb.c | 1 + 3 files changed, 8 insertions(+) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h index 81093b9b1568..b21c85315d76 100644 --- a/drivers/media/dvb/frontends/drxd.h +++ b/drivers/media/dvb/frontends/drxd.h @@ -44,6 +44,10 @@ struct drxd_config u8 demoda_address; u8 demod_revision; + /* If the tuner is not behind an i2c gate, be sure to flip this bit + or else the i2c bus could get wedged */ + u8 disable_i2c_gate_ctrl; + u32 IF; int (*pll_set) (void *priv, void *priv_params, u8 pll_addr, u8 demoda_addr, s32 *off); diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c index 994195fe9fbb..b8baafe3b54b 100644 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -2662,6 +2662,9 @@ int drxd_config_i2c(struct dvb_frontend *fe, int onoff) { struct drxd_state *state=fe->demodulator_priv; + if (state->config.disable_i2c_gate_ctrl == 1) + return 0; + return DRX_ConfigureI2CBridge(state, onoff); } diff --git a/drivers/media/video/em28xx/em28xx-dvb.c b/drivers/media/video/em28xx/em28xx-dvb.c index bdbdb1bd8ec9..f18e41f0bbc1 100644 --- a/drivers/media/video/em28xx/em28xx-dvb.c +++ b/drivers/media/video/em28xx/em28xx-dvb.c @@ -291,6 +291,7 @@ static struct drxd_config em28xx_drxd = { .demoda_address = 0x00, .pll_address = 0x00, .pll_type = DRXD_PLL_NONE, .clock = 12000, .insert_rs_byte = 1, .pll_set = NULL, .osc_deviation = NULL, .IF = 42800000, + .disable_i2c_gate_ctrl = 1, }; static int mt352_terratec_xs_init(struct dvb_frontend *fe) -- cgit v1.2.3 From 8f19f27e3e0e055aed877a07198cfbaf9d784105 Mon Sep 17 00:00:00 2001 From: Devin Heitmueller <dheitmueller@kernellabs.com> Date: Sun, 13 Mar 2011 02:11:07 -0300 Subject: [media] drxd: move firmware to binary blob Abstract out the firmware for the drx-d so that it can be loaded by the request_firmware() interface. The firmware licensing permits free redistribution, and can be found here: http://kernellabs.com/firmware/drxd Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd_firm.c | 2 - drivers/media/dvb/frontends/drxd_hard.c | 31 +- drivers/media/dvb/frontends/drxd_micro.h | 1498 ------------------------------ 3 files changed, 27 insertions(+), 1504 deletions(-) delete mode 100644 drivers/media/dvb/frontends/drxd_micro.h (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c index b27e928b94c1..b19a037e692e 100644 --- a/drivers/media/dvb/frontends/drxd_firm.c +++ b/drivers/media/dvb/frontends/drxd_firm.c @@ -939,5 +939,3 @@ u8_t DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */ WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 3500 - 50 ), END_OF_TABLE }; - -#include "drxd_micro.h" diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c index b8baafe3b54b..bdc004b65ea9 100644 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -35,6 +35,9 @@ #include "drxd.h" #include "drxd_firm.h" +#define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw" +#define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw" + #define CHK_ERROR(s) if( (status = s)<0 ) break #define CHUNK_SIZE 48 @@ -854,6 +857,26 @@ static int ReadIFAgc(struct drxd_state *state, u32 *pValue) return status; } +static int load_firmware(struct drxd_state *state, const char *fw_name) +{ + const struct firmware *fw; + + if (request_firmware(&fw, fw_name, state->dev) < 0) { + printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name); + return -EIO; + } + + state->microcode = kzalloc(fw->size, GFP_KERNEL); + if (state->microcode == NULL) { + printk(KERN_ERR "drxd: firmware load failure: nomemory\n"); + return -ENOMEM; + } + + memcpy(state->microcode, fw->data, fw->size); + state->microcode_length = fw->size; + return 0; +} + static int DownloadMicrocode(struct drxd_state *state, const u8 *pMCImage, u32 Length) { @@ -1450,8 +1473,8 @@ static int SetDeviceTypeId(struct drxd_state *state) state->m_InitCE = DRXD_InitCEA2; state->m_InitEQ = DRXD_InitEQA2; state->m_InitEC = DRXD_InitECA2; - state->microcode = DRXD_A2_microcode; - state->microcode_length = DRXD_A2_microcode_length; + if (load_firmware(state, DRX_FW_FILENAME_A2)) + return -EIO; } else { state->m_ResetCEFR = NULL; state->m_InitFE_1 = DRXD_InitFEB1_1; @@ -1460,8 +1483,8 @@ static int SetDeviceTypeId(struct drxd_state *state) state->m_InitCE = DRXD_InitCEB1; state->m_InitEQ = DRXD_InitEQB1; state->m_InitEC = DRXD_InitECB1; - state->microcode = DRXD_B1_microcode; - state->microcode_length = DRXD_B1_microcode_length; + if (load_firmware(state, DRX_FW_FILENAME_B1)) + return -EIO; } if (state->diversity) { state->m_InitDiversityFront = DRXD_InitDiversityFront; diff --git a/drivers/media/dvb/frontends/drxd_micro.h b/drivers/media/dvb/frontends/drxd_micro.h deleted file mode 100644 index 237296d35e55..000000000000 --- a/drivers/media/dvb/frontends/drxd_micro.h +++ /dev/null @@ -1,1498 +0,0 @@ -/*----------------------------------------------------------------------------- -* -* $(c) 2003-2007 Micronas GmbH. All rights reserved. -* -* This software and related documentation (the 'Software') are intellectual -* property owned by Micronas and are copyright of Micronas, unless specifically -* noted otherwise. -* -* Any use of the Software is permitted only pursuant to the terms of the -* license agreement, if any, which accompanies, is included with or applicable -* to the Software ('License Agreement') or upon express written consent of -* Micronas. Any copying, reproduction or redistribution of the Software in -* whole or in part by any means not in accordance with the License Agreement -* or as agreed in writing by Micronas is expressly prohibited. -* -* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE -* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE -* IS DELIVERED 'AS IS' AND MICRONAS HEREBY DISCLAIMS ALL WARRANTIES AND -* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES -* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT -* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL -* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY -* TO USE THE SOFTWARE. -* -* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL, -* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION, -* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS -* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE -* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM -* MICRONAS' NEGLIGENCE. $ -* -----------------------------------------------------------------------------*/ - - - -/* - Permission is granted by Micronas to distribute this file, either - in this form (hex-dump) or converted to a binary file, together - with the DRX397X Linux driver. -*/ - - -u8_t DRXD_A2_microcode[] = { -0x48, 0x4c, 0x00, 0x04, 0x00, 0x83, 0x00, 0x00, 0x10, 0x00, 0x00, 0x01, 0xe4, 0x47, 0xf6, 0x07, -0x11, 0x00, 0xf6, 0x07, 0x4a, 0x00, 0xf6, 0x07, 0x4c, 0x00, 0xf6, 0x07, 0xed, 0x07, 0xf6, 0x07, -0xf7, 0x07, 0xf6, 0x07, 0x9a, 0x04, 0xf6, 0x07, 0xf8, 0x04, 0x09, 0x00, 0xf6, 0x07, 0xe8, 0x04, -0xf7, 0x07, 0x13, 0x08, 0xc4, 0x07, 0x4b, 0x00, 0x00, 0x00, 0xc4, 0x07, 0xf3, 0x00, 0x0f, 0x04, -0x50, 0x00, 0x00, 0x06, 0xc4, 0x07, 0x20, 0x00, 0xfe, 0x01, 0xfd, 0x07, 0x21, 0x00, 0x02, 0x00, -0x02, 0x00, 0xc4, 0x07, 0x30, 0x00, 0xfe, 0x01, 0xfd, 0x07, 0x28, 0x00, 0x02, 0x00, 0x02, 0x00, -0xc4, 0x07, 0xc0, 0x00, 0xfe, 0x01, 0xfd, 0x07, 0x2f, 0x00, 0x02, 0x00, 0x02, 0x00, 0xc4, 0x07, -0x84, 0x00, 0x00, 0x00, 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0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00, -0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -u32_t DRXD_B1_microcode_length = (sizeof(DRXD_B1_microcode)); - -- cgit v1.2.3 From 6cacdd46e23826c0591238f5f11b1bfa6490797d Mon Sep 17 00:00:00 2001 From: Devin Heitmueller <dheitmueller@kernellabs.com> Date: Thu, 24 Mar 2011 13:44:01 -0300 Subject: [media] drxd: Run lindent across sources Take a first cleanup pass over the sources to bring them closer to the Linux coding style. Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd.h | 9 +- drivers/media/dvb/frontends/drxd_firm.c | 1576 ++++++++++---------- drivers/media/dvb/frontends/drxd_firm.h | 8 +- drivers/media/dvb/frontends/drxd_hard.c | 2111 +++++++++++++-------------- drivers/media/dvb/frontends/drxd_map_firm.h | 1810 +---------------------- 5 files changed, 1829 insertions(+), 3685 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h index b21c85315d76..d3d6c9246535 100644 --- a/drivers/media/dvb/frontends/drxd.h +++ b/drivers/media/dvb/frontends/drxd.h @@ -27,8 +27,7 @@ #include <linux/types.h> #include <linux/i2c.h> -struct drxd_config -{ +struct drxd_config { u8 index; u8 pll_address; @@ -49,9 +48,9 @@ struct drxd_config u8 disable_i2c_gate_ctrl; u32 IF; - int (*pll_set) (void *priv, void *priv_params, - u8 pll_addr, u8 demoda_addr, s32 *off); - s16 (*osc_deviation) (void *priv, s16 dev, int flag); + int (*pll_set) (void *priv, void *priv_params, + u8 pll_addr, u8 demoda_addr, s32 * off); + s16(*osc_deviation) (void *priv, s16 dev, int flag); }; extern diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c index b19a037e692e..9453929d0d1c 100644 --- a/drivers/media/dvb/frontends/drxd_firm.c +++ b/drivers/media/dvb/frontends/drxd_firm.c @@ -44,292 +44,294 @@ /* HI firmware patches */ #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A -#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */ - -u8_t DRXD_InitAtomicRead[] = -{ - WRBLOCK(HI_TR_FUNC_ADDR,HI_TR_FUNC_SIZE), - 0x26, 0x00, /* 0 -> ring.rdy; */ - 0x60, 0x04, /* r0rami.dt -> ring.xba; */ - 0x61, 0x04, /* r0rami.dt -> ring.xad; */ - 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */ - 0x40, 0x00, /* (long immediate) */ - 0x64, 0x04, /* r0rami.dt -> ring.len; */ - 0x65, 0x04, /* r0rami.dt -> ring.ctl; */ - 0x26, 0x00, /* 0 -> ring.rdy; */ - 0x38, 0x00, /* 0 -> jumps.ad; */ - END_OF_TABLE +#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */ + +u8_t DRXD_InitAtomicRead[] = { + WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE), + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x60, 0x04, /* r0rami.dt -> ring.xba; */ + 0x61, 0x04, /* r0rami.dt -> ring.xad; */ + 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */ + 0x40, 0x00, /* (long immediate) */ + 0x64, 0x04, /* r0rami.dt -> ring.len; */ + 0x65, 0x04, /* r0rami.dt -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x38, 0x00, /* 0 -> jumps.ad; */ + END_OF_TABLE }; /* Pins D0 and D1 of the parallel MPEG output can be used to set the I2C address of a device. */ #define HI_RST_FUNC_ADDR ( HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE) -#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */ +#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */ /* D0 Version */ -u8_t DRXD_HiI2cPatch_1[] = -{ - WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE), - 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */ - 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ - 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ - 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ - 0x23, 0x00, /* &data -> ring.iad; */ - 0x24, 0x00, /* 0 -> ring.len; */ - 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ - 0x26, 0x00, /* 0 -> ring.rdy; */ - 0x42, 0x00, /* &data+1 -> w0ram.ad; */ - 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ - 0x63, 0x00, /* &data+1 -> ring.iad; */ - 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ - 0x26, 0x00, /* 0 -> ring.rdy; */ - 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ - 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ - 0x26, 0x00, /* 0 -> ring.rdy; */ - 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ - 0x23, 0x00, /* &data -> ring.iad; */ - 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ - 0x26, 0x00, /* 0 -> ring.rdy; */ - 0x42, 0x00, /* &data+1 -> w0ram.ad; */ - 0x0F, 0x04, /* r0ram.dt -> and.op; */ - 0x1C, 0x06, /* reg0.dt -> and.tr; */ - 0xCF, 0x04, /* and.rs -> add.op; */ - 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ - 0xD0, 0x04, /* add.rs -> add.tr; */ - 0xC8, 0x04, /* add.rs -> reg0.dt; */ - 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ - 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ - 0x01, 0x00, /* 0 -> w0rami.dt; */ - 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ - 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ - 0x01, 0x00, /* 0 -> w0rami.dt; */ - 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ - 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ - 0x01, 0x00, /* 0 -> w0rami.dt; */ - 0x01, 0x00, /* 0 -> w0rami.dt; */ - 0x01, 0x00, /* 0 -> w0rami.dt; */ - 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ - 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ - 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ - 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ - 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ - - WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), - WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), - WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), - WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), - - /* Force quick and dirty reset */ - WR16(B_HI_CT_REG_COMM_STATE__A,0), - END_OF_TABLE +u8_t DRXD_HiI2cPatch_1[] = { + WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE), + 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */ + 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x24, 0x00, /* 0 -> ring.len; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ + 0x63, 0x00, /* &data+1 -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0x0F, 0x04, /* r0ram.dt -> and.op; */ + 0x1C, 0x06, /* reg0.dt -> and.tr; */ + 0xCF, 0x04, /* and.rs -> add.op; */ + 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ + 0xD0, 0x04, /* add.rs -> add.tr; */ + 0xC8, 0x04, /* add.rs -> reg0.dt; */ + 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ + 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ + + WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)), + (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)), + (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)), + (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)), + (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + + /* Force quick and dirty reset */ + WR16(B_HI_CT_REG_COMM_STATE__A, 0), + END_OF_TABLE }; /* D0,D1 Version */ -u8_t DRXD_HiI2cPatch_3[] = -{ - WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE), - 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */ - 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ - 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ - 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ - 0x23, 0x00, /* &data -> ring.iad; */ - 0x24, 0x00, /* 0 -> ring.len; */ - 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ - 0x26, 0x00, /* 0 -> ring.rdy; */ - 0x42, 0x00, /* &data+1 -> w0ram.ad; */ - 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ - 0x63, 0x00, /* &data+1 -> ring.iad; */ - 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ - 0x26, 0x00, /* 0 -> ring.rdy; */ - 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ - 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ - 0x26, 0x00, /* 0 -> ring.rdy; */ - 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ - 0x23, 0x00, /* &data -> ring.iad; */ - 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ - 0x26, 0x00, /* 0 -> ring.rdy; */ - 0x42, 0x00, /* &data+1 -> w0ram.ad; */ - 0x0F, 0x04, /* r0ram.dt -> and.op; */ - 0x1C, 0x06, /* reg0.dt -> and.tr; */ - 0xCF, 0x04, /* and.rs -> add.op; */ - 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ - 0xD0, 0x04, /* add.rs -> add.tr; */ - 0xC8, 0x04, /* add.rs -> reg0.dt; */ - 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ - 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ - 0x01, 0x00, /* 0 -> w0rami.dt; */ - 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ - 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ - 0x01, 0x00, /* 0 -> w0rami.dt; */ - 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ - 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ - 0x01, 0x00, /* 0 -> w0rami.dt; */ - 0x01, 0x00, /* 0 -> w0rami.dt; */ - 0x01, 0x00, /* 0 -> w0rami.dt; */ - 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ - 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ - 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ - 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ - 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ - - WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), - WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), - WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), - WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)), - - /* Force quick and dirty reset */ - WR16(B_HI_CT_REG_COMM_STATE__A,0), - END_OF_TABLE +u8_t DRXD_HiI2cPatch_3[] = { + WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE), + 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */ + 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x24, 0x00, /* 0 -> ring.len; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */ + 0x63, 0x00, /* &data+1 -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */ + 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */ + 0x23, 0x00, /* &data -> ring.iad; */ + 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */ + 0x26, 0x00, /* 0 -> ring.rdy; */ + 0x42, 0x00, /* &data+1 -> w0ram.ad; */ + 0x0F, 0x04, /* r0ram.dt -> and.op; */ + 0x1C, 0x06, /* reg0.dt -> and.tr; */ + 0xCF, 0x04, /* and.rs -> add.op; */ + 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */ + 0xD0, 0x04, /* add.rs -> add.tr; */ + 0xC8, 0x04, /* add.rs -> reg0.dt; */ + 0x60, 0x00, /* reg0.dt -> w0ram.dt; */ + 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x06, /* reg0.dt -> w0rami.dt; */ + 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x01, 0x00, /* 0 -> w0rami.dt; */ + 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */ + 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */ + 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ + + WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)), + (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)), + (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)), + (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)), + (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + + /* Force quick and dirty reset */ + WR16(B_HI_CT_REG_COMM_STATE__A, 0), + END_OF_TABLE }; -u8_t DRXD_ResetCEFR[] = -{ - WRBLOCK(CE_REG_FR_TREAL00__A, 57), - 0x52,0x00, /* CE_REG_FR_TREAL00__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG00__A */ - 0x52,0x00, /* CE_REG_FR_TREAL01__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG01__A */ - 0x52,0x00, /* CE_REG_FR_TREAL02__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG02__A */ - 0x52,0x00, /* CE_REG_FR_TREAL03__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG03__A */ - 0x52,0x00, /* CE_REG_FR_TREAL04__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG04__A */ - 0x52,0x00, /* CE_REG_FR_TREAL05__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG05__A */ - 0x52,0x00, /* CE_REG_FR_TREAL06__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG06__A */ - 0x52,0x00, /* CE_REG_FR_TREAL07__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG07__A */ - 0x52,0x00, /* CE_REG_FR_TREAL08__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG08__A */ - 0x52,0x00, /* CE_REG_FR_TREAL09__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG09__A */ - 0x52,0x00, /* CE_REG_FR_TREAL10__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG10__A */ - 0x52,0x00, /* CE_REG_FR_TREAL11__A */ - 0x00,0x00, /* CE_REG_FR_TIMAG11__A */ - - 0x52,0x00, /* CE_REG_FR_MID_TAP__A */ - - 0x0B,0x00, /* CE_REG_FR_SQS_G00__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G01__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G02__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G03__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G04__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G05__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G06__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G07__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G08__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G09__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G10__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G11__A */ - 0x0B,0x00, /* CE_REG_FR_SQS_G12__A */ - - 0xFF,0x01, /* CE_REG_FR_RIO_G00__A */ - 0x90,0x01, /* CE_REG_FR_RIO_G01__A */ - 0x0B,0x01, /* CE_REG_FR_RIO_G02__A */ - 0xC8,0x00, /* CE_REG_FR_RIO_G03__A */ - 0xA0,0x00, /* CE_REG_FR_RIO_G04__A */ - 0x85,0x00, /* CE_REG_FR_RIO_G05__A */ - 0x72,0x00, /* CE_REG_FR_RIO_G06__A */ - 0x64,0x00, /* CE_REG_FR_RIO_G07__A */ - 0x59,0x00, /* CE_REG_FR_RIO_G08__A */ - 0x50,0x00, /* CE_REG_FR_RIO_G09__A */ - 0x49,0x00, /* CE_REG_FR_RIO_G10__A */ - - 0x10,0x00, /* CE_REG_FR_MODE__A */ - 0x78,0x00, /* CE_REG_FR_SQS_TRH__A */ - 0x00,0x00, /* CE_REG_FR_RIO_GAIN__A */ - 0x00,0x02, /* CE_REG_FR_BYPASS__A */ - 0x0D,0x00, /* CE_REG_FR_PM_SET__A */ - 0x07,0x00, /* CE_REG_FR_ERR_SH__A */ - 0x04,0x00, /* CE_REG_FR_MAN_SH__A */ - 0x06,0x00, /* CE_REG_FR_TAP_SH__A */ - - END_OF_TABLE +u8_t DRXD_ResetCEFR[] = { + WRBLOCK(CE_REG_FR_TREAL00__A, 57), + 0x52, 0x00, /* CE_REG_FR_TREAL00__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG00__A */ + 0x52, 0x00, /* CE_REG_FR_TREAL01__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG01__A */ + 0x52, 0x00, /* CE_REG_FR_TREAL02__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG02__A */ + 0x52, 0x00, /* CE_REG_FR_TREAL03__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG03__A */ + 0x52, 0x00, /* CE_REG_FR_TREAL04__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG04__A */ + 0x52, 0x00, /* CE_REG_FR_TREAL05__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG05__A */ + 0x52, 0x00, /* CE_REG_FR_TREAL06__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG06__A */ + 0x52, 0x00, /* CE_REG_FR_TREAL07__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG07__A */ + 0x52, 0x00, /* CE_REG_FR_TREAL08__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG08__A */ + 0x52, 0x00, /* CE_REG_FR_TREAL09__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG09__A */ + 0x52, 0x00, /* CE_REG_FR_TREAL10__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG10__A */ + 0x52, 0x00, /* CE_REG_FR_TREAL11__A */ + 0x00, 0x00, /* CE_REG_FR_TIMAG11__A */ + + 0x52, 0x00, /* CE_REG_FR_MID_TAP__A */ + + 0x0B, 0x00, /* CE_REG_FR_SQS_G00__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G01__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G02__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G03__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G04__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G05__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G06__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G07__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G08__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G09__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G10__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G11__A */ + 0x0B, 0x00, /* CE_REG_FR_SQS_G12__A */ + + 0xFF, 0x01, /* CE_REG_FR_RIO_G00__A */ + 0x90, 0x01, /* CE_REG_FR_RIO_G01__A */ + 0x0B, 0x01, /* CE_REG_FR_RIO_G02__A */ + 0xC8, 0x00, /* CE_REG_FR_RIO_G03__A */ + 0xA0, 0x00, /* CE_REG_FR_RIO_G04__A */ + 0x85, 0x00, /* CE_REG_FR_RIO_G05__A */ + 0x72, 0x00, /* CE_REG_FR_RIO_G06__A */ + 0x64, 0x00, /* CE_REG_FR_RIO_G07__A */ + 0x59, 0x00, /* CE_REG_FR_RIO_G08__A */ + 0x50, 0x00, /* CE_REG_FR_RIO_G09__A */ + 0x49, 0x00, /* CE_REG_FR_RIO_G10__A */ + + 0x10, 0x00, /* CE_REG_FR_MODE__A */ + 0x78, 0x00, /* CE_REG_FR_SQS_TRH__A */ + 0x00, 0x00, /* CE_REG_FR_RIO_GAIN__A */ + 0x00, 0x02, /* CE_REG_FR_BYPASS__A */ + 0x0D, 0x00, /* CE_REG_FR_PM_SET__A */ + 0x07, 0x00, /* CE_REG_FR_ERR_SH__A */ + 0x04, 0x00, /* CE_REG_FR_MAN_SH__A */ + 0x06, 0x00, /* CE_REG_FR_TAP_SH__A */ + + END_OF_TABLE }; - -u8_t DRXD_InitFEA2_1[] = -{ - WRBLOCK(FE_AD_REG_PD__A , 3), - 0x00,0x00, /* FE_AD_REG_PD__A */ - 0x01,0x00, /* FE_AD_REG_INVEXT__A */ - 0x00,0x00, /* FE_AD_REG_CLKNEG__A */ - - WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A , 2), - 0x10,0x00, /* FE_AG_REG_DCE_AUR_CNT__A */ - 0x10,0x00, /* FE_AG_REG_DCE_RUR_CNT__A */ - - WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A , 2), - 0x0E,0x00, /* FE_AG_REG_ACE_AUR_CNT__A */ - 0x00,0x00, /* FE_AG_REG_ACE_RUR_CNT__A */ - - WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A , 5), - 0x04,0x00, /* FE_AG_REG_EGC_FLA_RGN__A */ - 0x1F,0x00, /* FE_AG_REG_EGC_SLO_RGN__A */ - 0x00,0x00, /* FE_AG_REG_EGC_JMP_PSN__A */ - 0x00,0x00, /* FE_AG_REG_EGC_FLA_INC__A */ - 0x00,0x00, /* FE_AG_REG_EGC_FLA_DEC__A */ - - WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A , 2), - 0xFF,0x01, /* FE_AG_REG_GC1_AGC_MAX__A */ - 0x00,0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */ - - WRBLOCK(FE_AG_REG_IND_WIN__A , 29), - 0x00,0x00, /* FE_AG_REG_IND_WIN__A */ - 0x05,0x00, /* FE_AG_REG_IND_THD_LOL__A */ - 0x0F,0x00, /* FE_AG_REG_IND_THD_HIL__A */ - 0x00,0x00, /* FE_AG_REG_IND_DEL__A don't care */ - 0x1E,0x00, /* FE_AG_REG_IND_PD1_WRI__A */ - 0x0C,0x00, /* FE_AG_REG_PDA_AUR_CNT__A */ - 0x00,0x00, /* FE_AG_REG_PDA_RUR_CNT__A */ - 0x00,0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */ - 0x00,0x00, /* FE_AG_REG_PDC_RUR_CNT__A */ - 0x01,0x00, /* FE_AG_REG_PDC_SET_LVL__A */ - 0x02,0x00, /* FE_AG_REG_PDC_FLA_RGN__A */ - 0x00,0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */ - 0xFF,0xFF, /* FE_AG_REG_PDC_FLA_STP__A */ - 0xFF,0xFF, /* FE_AG_REG_PDC_SLO_STP__A */ - 0x00,0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */ - 0x00,0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */ - 0x02,0x00, /* FE_AG_REG_PDC_MAX__A */ - 0x0C,0x00, /* FE_AG_REG_TGA_AUR_CNT__A */ - 0x00,0x00, /* FE_AG_REG_TGA_RUR_CNT__A */ - 0x00,0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */ - 0x00,0x00, /* FE_AG_REG_TGC_RUR_CNT__A */ - 0x22,0x00, /* FE_AG_REG_TGC_SET_LVL__A */ - 0x15,0x00, /* FE_AG_REG_TGC_FLA_RGN__A */ - 0x00,0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */ - 0x01,0x00, /* FE_AG_REG_TGC_FLA_STP__A */ - 0x0A,0x00, /* FE_AG_REG_TGC_SLO_STP__A */ - 0x00,0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */ - 0x10,0x00, /* FE_AG_REG_FGA_AUR_CNT__A */ - 0x10,0x00, /* FE_AG_REG_FGA_RUR_CNT__A */ - - WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A , 2), - 0x00,0x00, /* FE_AG_REG_BGC_FGC_WRI__A */ - 0x00,0x00, /* FE_AG_REG_BGC_CGC_WRI__A */ - - WRBLOCK(FE_FD_REG_SCL__A , 3), - 0x05,0x00, /* FE_FD_REG_SCL__A */ - 0x03,0x00, /* FE_FD_REG_MAX_LEV__A */ - 0x05,0x00, /* FE_FD_REG_NR__A */ - - WRBLOCK(FE_CF_REG_SCL__A , 5), - 0x16,0x00, /* FE_CF_REG_SCL__A */ - 0x04,0x00, /* FE_CF_REG_MAX_LEV__A */ - 0x06,0x00, /* FE_CF_REG_NR__A */ - 0x00,0x00, /* FE_CF_REG_IMP_VAL__A */ - 0x01,0x00, /* FE_CF_REG_MEAS_VAL__A */ - - WRBLOCK(FE_CU_REG_FRM_CNT_RST__A , 2), - 0x00,0x08, /* FE_CU_REG_FRM_CNT_RST__A */ - 0x00,0x00, /* FE_CU_REG_FRM_CNT_STR__A */ - - END_OF_TABLE +u8_t DRXD_InitFEA2_1[] = { + WRBLOCK(FE_AD_REG_PD__A, 3), + 0x00, 0x00, /* FE_AD_REG_PD__A */ + 0x01, 0x00, /* FE_AD_REG_INVEXT__A */ + 0x00, 0x00, /* FE_AD_REG_CLKNEG__A */ + + WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A, 2), + 0x10, 0x00, /* FE_AG_REG_DCE_AUR_CNT__A */ + 0x10, 0x00, /* FE_AG_REG_DCE_RUR_CNT__A */ + + WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A, 2), + 0x0E, 0x00, /* FE_AG_REG_ACE_AUR_CNT__A */ + 0x00, 0x00, /* FE_AG_REG_ACE_RUR_CNT__A */ + + WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A, 5), + 0x04, 0x00, /* FE_AG_REG_EGC_FLA_RGN__A */ + 0x1F, 0x00, /* FE_AG_REG_EGC_SLO_RGN__A */ + 0x00, 0x00, /* FE_AG_REG_EGC_JMP_PSN__A */ + 0x00, 0x00, /* FE_AG_REG_EGC_FLA_INC__A */ + 0x00, 0x00, /* FE_AG_REG_EGC_FLA_DEC__A */ + + WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A, 2), + 0xFF, 0x01, /* FE_AG_REG_GC1_AGC_MAX__A */ + 0x00, 0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */ + + WRBLOCK(FE_AG_REG_IND_WIN__A, 29), + 0x00, 0x00, /* FE_AG_REG_IND_WIN__A */ + 0x05, 0x00, /* FE_AG_REG_IND_THD_LOL__A */ + 0x0F, 0x00, /* FE_AG_REG_IND_THD_HIL__A */ + 0x00, 0x00, /* FE_AG_REG_IND_DEL__A don't care */ + 0x1E, 0x00, /* FE_AG_REG_IND_PD1_WRI__A */ + 0x0C, 0x00, /* FE_AG_REG_PDA_AUR_CNT__A */ + 0x00, 0x00, /* FE_AG_REG_PDA_RUR_CNT__A */ + 0x00, 0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */ + 0x00, 0x00, /* FE_AG_REG_PDC_RUR_CNT__A */ + 0x01, 0x00, /* FE_AG_REG_PDC_SET_LVL__A */ + 0x02, 0x00, /* FE_AG_REG_PDC_FLA_RGN__A */ + 0x00, 0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */ + 0xFF, 0xFF, /* FE_AG_REG_PDC_FLA_STP__A */ + 0xFF, 0xFF, /* FE_AG_REG_PDC_SLO_STP__A */ + 0x00, 0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */ + 0x00, 0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */ + 0x02, 0x00, /* FE_AG_REG_PDC_MAX__A */ + 0x0C, 0x00, /* FE_AG_REG_TGA_AUR_CNT__A */ + 0x00, 0x00, /* FE_AG_REG_TGA_RUR_CNT__A */ + 0x00, 0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */ + 0x00, 0x00, /* FE_AG_REG_TGC_RUR_CNT__A */ + 0x22, 0x00, /* FE_AG_REG_TGC_SET_LVL__A */ + 0x15, 0x00, /* FE_AG_REG_TGC_FLA_RGN__A */ + 0x00, 0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */ + 0x01, 0x00, /* FE_AG_REG_TGC_FLA_STP__A */ + 0x0A, 0x00, /* FE_AG_REG_TGC_SLO_STP__A */ + 0x00, 0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */ + 0x10, 0x00, /* FE_AG_REG_FGA_AUR_CNT__A */ + 0x10, 0x00, /* FE_AG_REG_FGA_RUR_CNT__A */ + + WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A, 2), + 0x00, 0x00, /* FE_AG_REG_BGC_FGC_WRI__A */ + 0x00, 0x00, /* FE_AG_REG_BGC_CGC_WRI__A */ + + WRBLOCK(FE_FD_REG_SCL__A, 3), + 0x05, 0x00, /* FE_FD_REG_SCL__A */ + 0x03, 0x00, /* FE_FD_REG_MAX_LEV__A */ + 0x05, 0x00, /* FE_FD_REG_NR__A */ + + WRBLOCK(FE_CF_REG_SCL__A, 5), + 0x16, 0x00, /* FE_CF_REG_SCL__A */ + 0x04, 0x00, /* FE_CF_REG_MAX_LEV__A */ + 0x06, 0x00, /* FE_CF_REG_NR__A */ + 0x00, 0x00, /* FE_CF_REG_IMP_VAL__A */ + 0x01, 0x00, /* FE_CF_REG_MEAS_VAL__A */ + + WRBLOCK(FE_CU_REG_FRM_CNT_RST__A, 2), + 0x00, 0x08, /* FE_CU_REG_FRM_CNT_RST__A */ + 0x00, 0x00, /* FE_CU_REG_FRM_CNT_STR__A */ + + END_OF_TABLE }; /* with PGA */ @@ -339,603 +341,589 @@ u8_t DRXD_InitFEA2_1[] = /* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/ /* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ -u8_t DRXD_InitFEA2_2[] = -{ - WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010), - WR16(FE_AG_REG_FGM_WRI__A , 48), - /* Activate measurement, activate scale */ - WR16(FE_FD_REG_MEAS_VAL__A , 0x0001), - - WR16(FE_CU_REG_COMM_EXEC__A, 0x0001), - WR16(FE_CF_REG_COMM_EXEC__A, 0x0001), - WR16(FE_IF_REG_COMM_EXEC__A, 0x0001), - WR16(FE_FD_REG_COMM_EXEC__A, 0x0001), - WR16(FE_FS_REG_COMM_EXEC__A, 0x0001), - WR16(FE_AD_REG_COMM_EXEC__A , 0x0001), - WR16(FE_AG_REG_COMM_EXEC__A , 0x0001), - WR16(FE_AG_REG_AG_MODE_LOP__A , 0x895E), - - END_OF_TABLE +u8_t DRXD_InitFEA2_2[] = { + WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010), + WR16(FE_AG_REG_FGM_WRI__A, 48), + /* Activate measurement, activate scale */ + WR16(FE_FD_REG_MEAS_VAL__A, 0x0001), + + WR16(FE_CU_REG_COMM_EXEC__A, 0x0001), + WR16(FE_CF_REG_COMM_EXEC__A, 0x0001), + WR16(FE_IF_REG_COMM_EXEC__A, 0x0001), + WR16(FE_FD_REG_COMM_EXEC__A, 0x0001), + WR16(FE_FS_REG_COMM_EXEC__A, 0x0001), + WR16(FE_AD_REG_COMM_EXEC__A, 0x0001), + WR16(FE_AG_REG_COMM_EXEC__A, 0x0001), + WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E), + + END_OF_TABLE }; -u8_t DRXD_InitFEB1_1[] = -{ - WR16(B_FE_AD_REG_PD__A ,0x0000 ), - WR16(B_FE_AD_REG_CLKNEG__A ,0x0000 ), - WR16(B_FE_AG_REG_BGC_FGC_WRI__A ,0x0000 ), - WR16(B_FE_AG_REG_BGC_CGC_WRI__A ,0x0000 ), - WR16(B_FE_AG_REG_AG_MODE_LOP__A ,0x000a ), - WR16(B_FE_AG_REG_IND_PD1_WRI__A ,35 ), - WR16(B_FE_AG_REG_IND_WIN__A ,0 ), - WR16(B_FE_AG_REG_IND_THD_LOL__A ,8 ), - WR16(B_FE_AG_REG_IND_THD_HIL__A ,8 ), - WR16(B_FE_CF_REG_IMP_VAL__A ,1 ), - WR16(B_FE_AG_REG_EGC_FLA_RGN__A ,7 ), - END_OF_TABLE +u8_t DRXD_InitFEB1_1[] = { + WR16(B_FE_AD_REG_PD__A, 0x0000), + WR16(B_FE_AD_REG_CLKNEG__A, 0x0000), + WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000), + WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000), + WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a), + WR16(B_FE_AG_REG_IND_PD1_WRI__A, 35), + WR16(B_FE_AG_REG_IND_WIN__A, 0), + WR16(B_FE_AG_REG_IND_THD_LOL__A, 8), + WR16(B_FE_AG_REG_IND_THD_HIL__A, 8), + WR16(B_FE_CF_REG_IMP_VAL__A, 1), + WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7), + END_OF_TABLE }; + /* with PGA */ /* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */ /* without PGA */ /* WR16(B_FE_AG_REG_AG_PGA_MODE__A , B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/ -/* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005*/ + /* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */ /* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ -u8_t DRXD_InitFEB1_2[] = -{ - WR16(B_FE_COMM_EXEC__A ,0x0001 ), - - /* RF-AGC setup */ - WR16(B_FE_AG_REG_PDA_AUR_CNT__A , 0x0C ), - WR16(B_FE_AG_REG_PDC_SET_LVL__A , 0x01 ), - WR16(B_FE_AG_REG_PDC_FLA_RGN__A , 0x02 ), - WR16(B_FE_AG_REG_PDC_FLA_STP__A , 0xFFFF ), - WR16(B_FE_AG_REG_PDC_SLO_STP__A , 0xFFFF ), - WR16(B_FE_AG_REG_PDC_MAX__A , 0x02 ), - WR16(B_FE_AG_REG_TGA_AUR_CNT__A , 0x0C ), - WR16(B_FE_AG_REG_TGC_SET_LVL__A , 0x22 ), - WR16(B_FE_AG_REG_TGC_FLA_RGN__A , 0x15 ), - WR16(B_FE_AG_REG_TGC_FLA_STP__A , 0x01 ), - WR16(B_FE_AG_REG_TGC_SLO_STP__A , 0x0A ), - - WR16(B_FE_CU_REG_DIV_NFC_CLP__A , 0 ), - WR16(B_FE_CU_REG_CTR_NFC_OCR__A , 25000 ), - WR16(B_FE_CU_REG_CTR_NFC_ICR__A , 1 ), - END_OF_TABLE +u8_t DRXD_InitFEB1_2[] = { + WR16(B_FE_COMM_EXEC__A, 0x0001), + + /* RF-AGC setup */ + WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C), + WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01), + WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02), + WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF), + WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF), + WR16(B_FE_AG_REG_PDC_MAX__A, 0x02), + WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C), + WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22), + WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15), + WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01), + WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A), + + WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0), + WR16(B_FE_CU_REG_CTR_NFC_OCR__A, 25000), + WR16(B_FE_CU_REG_CTR_NFC_ICR__A, 1), + END_OF_TABLE }; -u8_t DRXD_InitCPA2[] = -{ - WRBLOCK(CP_REG_BR_SPL_OFFSET__A , 2), - 0x07,0x00, /* CP_REG_BR_SPL_OFFSET__A */ - 0x0A,0x00, /* CP_REG_BR_STR_DEL__A */ - - WRBLOCK(CP_REG_RT_ANG_INC0__A , 4), - 0x00,0x00, /* CP_REG_RT_ANG_INC0__A */ - 0x00,0x00, /* CP_REG_RT_ANG_INC1__A */ - 0x03,0x00, /* CP_REG_RT_DETECT_ENA__A */ - 0x03,0x00, /* CP_REG_RT_DETECT_TRH__A */ - - WRBLOCK(CP_REG_AC_NEXP_OFFS__A , 5), - 0x32,0x00, /* CP_REG_AC_NEXP_OFFS__A */ - 0x62,0x00, /* CP_REG_AC_AVER_POW__A */ - 0x82,0x00, /* CP_REG_AC_MAX_POW__A */ - 0x26,0x00, /* CP_REG_AC_WEIGHT_MAN__A */ - 0x0F,0x00, /* CP_REG_AC_WEIGHT_EXP__A */ - - WRBLOCK(CP_REG_AC_AMP_MODE__A ,2), - 0x02,0x00, /* CP_REG_AC_AMP_MODE__A */ - 0x01,0x00, /* CP_REG_AC_AMP_FIX__A */ - - WR16(CP_REG_INTERVAL__A , 0x0005 ), - WR16(CP_REG_RT_EXP_MARG__A , 0x0004 ), - WR16(CP_REG_AC_ANG_MODE__A , 0x0003 ), - - WR16(CP_REG_COMM_EXEC__A , 0x0001 ), - END_OF_TABLE +u8_t DRXD_InitCPA2[] = { + WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2), + 0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */ + 0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */ + + WRBLOCK(CP_REG_RT_ANG_INC0__A, 4), + 0x00, 0x00, /* CP_REG_RT_ANG_INC0__A */ + 0x00, 0x00, /* CP_REG_RT_ANG_INC1__A */ + 0x03, 0x00, /* CP_REG_RT_DETECT_ENA__A */ + 0x03, 0x00, /* CP_REG_RT_DETECT_TRH__A */ + + WRBLOCK(CP_REG_AC_NEXP_OFFS__A, 5), + 0x32, 0x00, /* CP_REG_AC_NEXP_OFFS__A */ + 0x62, 0x00, /* CP_REG_AC_AVER_POW__A */ + 0x82, 0x00, /* CP_REG_AC_MAX_POW__A */ + 0x26, 0x00, /* CP_REG_AC_WEIGHT_MAN__A */ + 0x0F, 0x00, /* CP_REG_AC_WEIGHT_EXP__A */ + + WRBLOCK(CP_REG_AC_AMP_MODE__A, 2), + 0x02, 0x00, /* CP_REG_AC_AMP_MODE__A */ + 0x01, 0x00, /* CP_REG_AC_AMP_FIX__A */ + + WR16(CP_REG_INTERVAL__A, 0x0005), + WR16(CP_REG_RT_EXP_MARG__A, 0x0004), + WR16(CP_REG_AC_ANG_MODE__A, 0x0003), + + WR16(CP_REG_COMM_EXEC__A, 0x0001), + END_OF_TABLE }; -u8_t DRXD_InitCPB1[] = -{ - WR16(B_CP_REG_BR_SPL_OFFSET__A ,0x0008 ), - WR16(B_CP_COMM_EXEC__A ,0x0001 ), - END_OF_TABLE +u8_t DRXD_InitCPB1[] = { + WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008), + WR16(B_CP_COMM_EXEC__A, 0x0001), + END_OF_TABLE }; +u8_t DRXD_InitCEA2[] = { + WRBLOCK(CE_REG_AVG_POW__A, 4), + 0x62, 0x00, /* CE_REG_AVG_POW__A */ + 0x78, 0x00, /* CE_REG_MAX_POW__A */ + 0x62, 0x00, /* CE_REG_ATT__A */ + 0x17, 0x00, /* CE_REG_NRED__A */ -u8_t DRXD_InitCEA2[] = -{ - WRBLOCK(CE_REG_AVG_POW__A , 4), - 0x62,0x00, /* CE_REG_AVG_POW__A */ - 0x78,0x00, /* CE_REG_MAX_POW__A */ - 0x62,0x00, /* CE_REG_ATT__A */ - 0x17,0x00, /* CE_REG_NRED__A */ - - WRBLOCK(CE_REG_NE_ERR_SELECT__A , 2), - 0x07,0x00, /* CE_REG_NE_ERR_SELECT__A */ - 0xEB,0xFF, /* CE_REG_NE_TD_CAL__A */ + WRBLOCK(CE_REG_NE_ERR_SELECT__A, 2), + 0x07, 0x00, /* CE_REG_NE_ERR_SELECT__A */ + 0xEB, 0xFF, /* CE_REG_NE_TD_CAL__A */ - WRBLOCK(CE_REG_NE_MIXAVG__A , 2), - 0x06,0x00, /* CE_REG_NE_MIXAVG__A */ - 0x00,0x00, /* CE_REG_NE_NUPD_OFS__A */ + WRBLOCK(CE_REG_NE_MIXAVG__A, 2), + 0x06, 0x00, /* CE_REG_NE_MIXAVG__A */ + 0x00, 0x00, /* CE_REG_NE_NUPD_OFS__A */ - WRBLOCK(CE_REG_PE_NEXP_OFFS__A , 2), - 0x00,0x00, /* CE_REG_PE_NEXP_OFFS__A */ - 0x00,0x00, /* CE_REG_PE_TIMESHIFT__A */ + WRBLOCK(CE_REG_PE_NEXP_OFFS__A, 2), + 0x00, 0x00, /* CE_REG_PE_NEXP_OFFS__A */ + 0x00, 0x00, /* CE_REG_PE_TIMESHIFT__A */ - WRBLOCK(CE_REG_TP_A0_TAP_NEW__A , 3), - 0x00,0x01, /* CE_REG_TP_A0_TAP_NEW__A */ - 0x01,0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */ - 0x0E,0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */ + WRBLOCK(CE_REG_TP_A0_TAP_NEW__A, 3), + 0x00, 0x01, /* CE_REG_TP_A0_TAP_NEW__A */ + 0x01, 0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */ + 0x0E, 0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */ - WRBLOCK(CE_REG_TP_A1_TAP_NEW__A , 3), - 0x00,0x00, /* CE_REG_TP_A1_TAP_NEW__A */ - 0x01,0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */ - 0x0A,0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */ + WRBLOCK(CE_REG_TP_A1_TAP_NEW__A, 3), + 0x00, 0x00, /* CE_REG_TP_A1_TAP_NEW__A */ + 0x01, 0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */ + 0x0A, 0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */ - WRBLOCK(CE_REG_FI_SHT_INCR__A , 2), - 0x12,0x00, /* CE_REG_FI_SHT_INCR__A */ - 0x0C,0x00, /* CE_REG_FI_EXP_NORM__A */ + WRBLOCK(CE_REG_FI_SHT_INCR__A, 2), + 0x12, 0x00, /* CE_REG_FI_SHT_INCR__A */ + 0x0C, 0x00, /* CE_REG_FI_EXP_NORM__A */ - WRBLOCK(CE_REG_IR_INPUTSEL__A , 3), - 0x00,0x00, /* CE_REG_IR_INPUTSEL__A */ - 0x00,0x00, /* CE_REG_IR_STARTPOS__A */ - 0xFF,0x00, /* CE_REG_IR_NEXP_THRES__A */ + WRBLOCK(CE_REG_IR_INPUTSEL__A, 3), + 0x00, 0x00, /* CE_REG_IR_INPUTSEL__A */ + 0x00, 0x00, /* CE_REG_IR_STARTPOS__A */ + 0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */ + WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000), - WR16(CE_REG_TI_NEXP_OFFS__A ,0x0000), - - END_OF_TABLE + END_OF_TABLE }; -u8_t DRXD_InitCEB1[] = -{ - WR16(B_CE_REG_TI_PHN_ENABLE__A ,0x0001), - WR16(B_CE_REG_FR_PM_SET__A ,0x000D), +u8_t DRXD_InitCEB1[] = { + WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001), + WR16(B_CE_REG_FR_PM_SET__A, 0x000D), - END_OF_TABLE + END_OF_TABLE }; -u8_t DRXD_InitEQA2[] = -{ - WRBLOCK(EQ_REG_OT_QNT_THRES0__A , 4), - 0x1E,0x00, /* EQ_REG_OT_QNT_THRES0__A */ - 0x1F,0x00, /* EQ_REG_OT_QNT_THRES1__A */ - 0x06,0x00, /* EQ_REG_OT_CSI_STEP__A */ - 0x02,0x00, /* EQ_REG_OT_CSI_OFFSET__A */ - - WR16(EQ_REG_TD_REQ_SMB_CNT__A ,0x0200 ), - WR16(EQ_REG_IS_CLIP_EXP__A ,0x001F ), - WR16(EQ_REG_SN_OFFSET__A ,(u16_t)(-7) ), - WR16(EQ_REG_RC_SEL_CAR__A ,0x0002 ), - WR16(EQ_REG_COMM_EXEC__A ,0x0001 ), - END_OF_TABLE +u8_t DRXD_InitEQA2[] = { + WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4), + 0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */ + 0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */ + 0x06, 0x00, /* EQ_REG_OT_CSI_STEP__A */ + 0x02, 0x00, /* EQ_REG_OT_CSI_OFFSET__A */ + + WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200), + WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F), + WR16(EQ_REG_SN_OFFSET__A, (u16_t) (-7)), + WR16(EQ_REG_RC_SEL_CAR__A, 0x0002), + WR16(EQ_REG_COMM_EXEC__A, 0x0001), + END_OF_TABLE }; -u8_t DRXD_InitEQB1[] = -{ - WR16(B_EQ_REG_COMM_EXEC__A ,0x0001 ), - END_OF_TABLE +u8_t DRXD_InitEQB1[] = { + WR16(B_EQ_REG_COMM_EXEC__A, 0x0001), + END_OF_TABLE }; -u8_t DRXD_ResetECRAM[] = -{ - /* Reset packet sync bytes in EC_VD ram */ - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), - - /* Reset packet sync bytes in EC_RS ram */ - WR16(EC_RS_EC_RAM__A , 0x0000 ), - WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), - END_OF_TABLE +u8_t DRXD_ResetECRAM[] = { + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A, 0x0000), + WR16(EC_RS_EC_RAM__A + 204, 0x0000), + END_OF_TABLE }; -u8_t DRXD_InitECA2[] = -{ - WRBLOCK( EC_SB_REG_CSI_HI__A , 6), - 0x1F,0x00, /* EC_SB_REG_CSI_HI__A */ - 0x1E,0x00, /* EC_SB_REG_CSI_LO__A */ - 0x01,0x00, /* EC_SB_REG_SMB_TGL__A */ - 0x7F,0x00, /* EC_SB_REG_SNR_HI__A */ - 0x7F,0x00, /* EC_SB_REG_SNR_MID__A */ - 0x7F,0x00, /* EC_SB_REG_SNR_LO__A */ - - WRBLOCK( EC_RS_REG_REQ_PCK_CNT__A , 2), - 0x00,0x10, /* EC_RS_REG_REQ_PCK_CNT__A */ - DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */ - - WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5), - 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ - 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ - 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ - 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ - 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ - - WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2), - 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ - 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ - - WRBLOCK( EC_OC_REG_RCN_MODE__A , 7), - 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */ - 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ - 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ - 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */ - 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */ - 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */ - 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ - - WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2), - 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ - 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ - - WR16(EC_SB_REG_CSI_OFS__A , 0x0001 ), - WR16(EC_VD_REG_FORCE__A , 0x0002 ), - WR16(EC_VD_REG_REQ_SMB_CNT__A , 0x0001 ), - WR16(EC_VD_REG_RLK_ENA__A , 0x0001 ), - WR16(EC_OD_REG_SYNC__A , 0x0664 ), - WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ), - WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ), - /* Output zero on monitorbus pads, power saving */ - WR16(EC_OC_REG_OCR_MON_UOS__A , - ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | - EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | - EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ), - WR16(EC_OC_REG_OCR_MON_WRI__A, - EC_OC_REG_OCR_MON_WRI_INIT ), +u8_t DRXD_InitECA2[] = { + WRBLOCK(EC_SB_REG_CSI_HI__A, 6), + 0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */ + 0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */ + 0x01, 0x00, /* EC_SB_REG_SMB_TGL__A */ + 0x7F, 0x00, /* EC_SB_REG_SNR_HI__A */ + 0x7F, 0x00, /* EC_SB_REG_SNR_MID__A */ + 0x7F, 0x00, /* EC_SB_REG_SNR_LO__A */ + + WRBLOCK(EC_RS_REG_REQ_PCK_CNT__A, 2), + 0x00, 0x10, /* EC_RS_REG_REQ_PCK_CNT__A */ + DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */ + + WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5), + 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ + 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ + 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ + 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ + 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ + + WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2), + 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ + 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ + + WRBLOCK(EC_OC_REG_RCN_MODE__A, 7), + 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */ + 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ + 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ + 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */ + 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */ + 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */ + 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ + + WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2), + 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ + 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ + + WR16(EC_SB_REG_CSI_OFS__A, 0x0001), + WR16(EC_VD_REG_FORCE__A, 0x0002), + WR16(EC_VD_REG_REQ_SMB_CNT__A, 0x0001), + WR16(EC_VD_REG_RLK_ENA__A, 0x0001), + WR16(EC_OD_REG_SYNC__A, 0x0664), + WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000), + WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C), + /* Output zero on monitorbus pads, power saving */ + WR16(EC_OC_REG_OCR_MON_UOS__A, + (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | + EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | + EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)), + WR16(EC_OC_REG_OCR_MON_WRI__A, + EC_OC_REG_OCR_MON_WRI_INIT), /* CHK_ERROR(ResetECRAM(demod)); */ - /* Reset packet sync bytes in EC_VD ram */ - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), - - /* Reset packet sync bytes in EC_RS ram */ - WR16(EC_RS_EC_RAM__A , 0x0000 ), - WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), - - WR16(EC_SB_REG_COMM_EXEC__A , 0x0001 ), - WR16(EC_VD_REG_COMM_EXEC__A , 0x0001 ), - WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ), - WR16(EC_RS_REG_COMM_EXEC__A , 0x0001 ), - END_OF_TABLE + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A, 0x0000), + WR16(EC_RS_EC_RAM__A + 204, 0x0000), + + WR16(EC_SB_REG_COMM_EXEC__A, 0x0001), + WR16(EC_VD_REG_COMM_EXEC__A, 0x0001), + WR16(EC_OD_REG_COMM_EXEC__A, 0x0001), + WR16(EC_RS_REG_COMM_EXEC__A, 0x0001), + END_OF_TABLE }; -u8_t DRXD_InitECB1[] = -{ - WR16(B_EC_SB_REG_CSI_OFS0__A ,0x0001 ), - WR16(B_EC_SB_REG_CSI_OFS1__A ,0x0001 ), - WR16(B_EC_SB_REG_CSI_OFS2__A ,0x0001 ), - WR16(B_EC_SB_REG_CSI_LO__A ,0x000c ), - WR16(B_EC_SB_REG_CSI_HI__A ,0x0018 ), - WR16(B_EC_SB_REG_SNR_HI__A ,0x007f ), - WR16(B_EC_SB_REG_SNR_MID__A ,0x007f ), - WR16(B_EC_SB_REG_SNR_LO__A ,0x007f ), - - WR16(B_EC_OC_REG_DTO_CLKMODE__A ,0x0002 ), - WR16(B_EC_OC_REG_DTO_PER__A ,0x0006 ), - WR16(B_EC_OC_REG_DTO_BUR__A ,0x0001 ), - WR16(B_EC_OC_REG_RCR_CLKMODE__A ,0x0000 ), - WR16(B_EC_OC_REG_RCN_GAI_LVL__A ,0x000D ), - WR16(B_EC_OC_REG_OC_MPG_SIO__A ,0x0000 ), - - /* Needed because shadow registers do not have correct default value */ - WR16(B_EC_OC_REG_RCN_CST_LOP__A ,0x1000 ), - WR16(B_EC_OC_REG_RCN_CST_HIP__A ,0x0000 ), - WR16(B_EC_OC_REG_RCN_CRA_LOP__A ,0x0000 ), - WR16(B_EC_OC_REG_RCN_CRA_HIP__A ,0x00C0 ), - WR16(B_EC_OC_REG_RCN_CLP_LOP__A ,0x0000 ), - WR16(B_EC_OC_REG_RCN_CLP_HIP__A ,0x00C0 ), - WR16(B_EC_OC_REG_DTO_INC_LOP__A ,0x0000 ), - WR16(B_EC_OC_REG_DTO_INC_HIP__A ,0x00C0 ), - - WR16(B_EC_OD_REG_SYNC__A ,0x0664 ), - WR16(B_EC_RS_REG_REQ_PCK_CNT__A ,0x1000 ), +u8_t DRXD_InitECB1[] = { + WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001), + WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001), + WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001), + WR16(B_EC_SB_REG_CSI_LO__A, 0x000c), + WR16(B_EC_SB_REG_CSI_HI__A, 0x0018), + WR16(B_EC_SB_REG_SNR_HI__A, 0x007f), + WR16(B_EC_SB_REG_SNR_MID__A, 0x007f), + WR16(B_EC_SB_REG_SNR_LO__A, 0x007f), + + WR16(B_EC_OC_REG_DTO_CLKMODE__A, 0x0002), + WR16(B_EC_OC_REG_DTO_PER__A, 0x0006), + WR16(B_EC_OC_REG_DTO_BUR__A, 0x0001), + WR16(B_EC_OC_REG_RCR_CLKMODE__A, 0x0000), + WR16(B_EC_OC_REG_RCN_GAI_LVL__A, 0x000D), + WR16(B_EC_OC_REG_OC_MPG_SIO__A, 0x0000), + + /* Needed because shadow registers do not have correct default value */ + WR16(B_EC_OC_REG_RCN_CST_LOP__A, 0x1000), + WR16(B_EC_OC_REG_RCN_CST_HIP__A, 0x0000), + WR16(B_EC_OC_REG_RCN_CRA_LOP__A, 0x0000), + WR16(B_EC_OC_REG_RCN_CRA_HIP__A, 0x00C0), + WR16(B_EC_OC_REG_RCN_CLP_LOP__A, 0x0000), + WR16(B_EC_OC_REG_RCN_CLP_HIP__A, 0x00C0), + WR16(B_EC_OC_REG_DTO_INC_LOP__A, 0x0000), + WR16(B_EC_OC_REG_DTO_INC_HIP__A, 0x00C0), + + WR16(B_EC_OD_REG_SYNC__A, 0x0664), + WR16(B_EC_RS_REG_REQ_PCK_CNT__A, 0x1000), /* CHK_ERROR(ResetECRAM(demod)); */ - /* Reset packet sync bytes in EC_VD ram */ - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), - - /* Reset packet sync bytes in EC_RS ram */ - WR16(EC_RS_EC_RAM__A , 0x0000 ), - WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), - - WR16(B_EC_SB_REG_COMM_EXEC__A , 0x0001 ), - WR16(B_EC_VD_REG_COMM_EXEC__A , 0x0001 ), - WR16(B_EC_OD_REG_COMM_EXEC__A , 0x0001 ), - WR16(B_EC_RS_REG_COMM_EXEC__A , 0x0001 ), - END_OF_TABLE + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A, 0x0000), + WR16(EC_RS_EC_RAM__A + 204, 0x0000), + + WR16(B_EC_SB_REG_COMM_EXEC__A, 0x0001), + WR16(B_EC_VD_REG_COMM_EXEC__A, 0x0001), + WR16(B_EC_OD_REG_COMM_EXEC__A, 0x0001), + WR16(B_EC_RS_REG_COMM_EXEC__A, 0x0001), + END_OF_TABLE }; -u8_t DRXD_ResetECA2[] = -{ - - WR16(EC_OC_REG_COMM_EXEC__A , 0x0000 ), - WR16(EC_OD_REG_COMM_EXEC__A , 0x0000 ), - - WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5), - 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ - 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ - 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ - 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ - 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ - - WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2), - 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ - 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ - - WRBLOCK( EC_OC_REG_RCN_MODE__A , 7), - 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */ - 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ - 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ - 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */ - 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */ - 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */ - 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ - - WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2), - 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ - 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ - - WR16(EC_OD_REG_SYNC__A , 0x0664 ), - WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ), - WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ), - /* Output zero on monitorbus pads, power saving */ - WR16(EC_OC_REG_OCR_MON_UOS__A , - ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | - EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | - EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | - EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ), - WR16(EC_OC_REG_OCR_MON_WRI__A, - EC_OC_REG_OCR_MON_WRI_INIT ), +u8_t DRXD_ResetECA2[] = { + + WR16(EC_OC_REG_COMM_EXEC__A, 0x0000), + WR16(EC_OD_REG_COMM_EXEC__A, 0x0000), + + WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5), + 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */ + 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */ + 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */ + 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */ + 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */ + + WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2), + 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */ + 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */ + + WRBLOCK(EC_OC_REG_RCN_MODE__A, 7), + 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */ + 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */ + 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */ + 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */ + 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */ + 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */ + 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */ + + WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2), + 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */ + 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */ + + WR16(EC_OD_REG_SYNC__A, 0x0664), + WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000), + WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C), + /* Output zero on monitorbus pads, power saving */ + WR16(EC_OC_REG_OCR_MON_UOS__A, + (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE | + EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE | + EC_OC_REG_OCR_MON_UOS_VAL_ENABLE | + EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)), + WR16(EC_OC_REG_OCR_MON_WRI__A, + EC_OC_REG_OCR_MON_WRI_INIT), /* CHK_ERROR(ResetECRAM(demod)); */ - /* Reset packet sync bytes in EC_VD ram */ - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ), - WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ), - - /* Reset packet sync bytes in EC_RS ram */ - WR16(EC_RS_EC_RAM__A , 0x0000 ), - WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ), - - WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ), - END_OF_TABLE + /* Reset packet sync bytes in EC_VD ram */ + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000), + WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000), + + /* Reset packet sync bytes in EC_RS ram */ + WR16(EC_RS_EC_RAM__A, 0x0000), + WR16(EC_RS_EC_RAM__A + 204, 0x0000), + + WR16(EC_OD_REG_COMM_EXEC__A, 0x0001), + END_OF_TABLE }; -u8_t DRXD_InitSC[] = -{ - WR16(SC_COMM_EXEC__A, 0 ), - WR16(SC_COMM_STATE__A, 0 ), +u8_t DRXD_InitSC[] = { + WR16(SC_COMM_EXEC__A, 0), + WR16(SC_COMM_STATE__A, 0), #ifdef COMPILE_FOR_QT - WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100 ), + WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100), #endif - /* SC is not started, this is done in SetChannels() */ - END_OF_TABLE + /* SC is not started, this is done in SetChannels() */ + END_OF_TABLE }; /* Diversity settings */ -u8_t DRXD_InitDiversityFront[] = -{ - /* Start demod ********* RF in , diversity out *****************************/ - WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | - B_SC_RA_RAM_CONFIG_FREQSCAN__M ), - - WR16( B_SC_RA_RAM_LC_ABS_2K__A, 0x7), - WR16( B_SC_RA_RAM_LC_ABS_8K__A, 0x7), - WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ), - WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ), - WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ), - WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ), - WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ), - WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ), - - WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ), - WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ), - WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ), - WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ), - WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ), - WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ), - - WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7), - WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4), - WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7), - WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4), - WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500), - - WR16( B_CC_REG_DIVERSITY__A, 0x0001 ), - WR16( B_EC_OC_REG_OC_MODE_HIP__A, 0x0010 ), - WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | - B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | - B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ), - - - /* 0x2a ),*/ /* CE to PASS mux */ - - END_OF_TABLE +u8_t DRXD_InitDiversityFront[] = { + /* Start demod ********* RF in , diversity out **************************** */ + WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | + B_SC_RA_RAM_CONFIG_FREQSCAN__M), + + WR16(B_SC_RA_RAM_LC_ABS_2K__A, 0x7), + WR16(B_SC_RA_RAM_LC_ABS_8K__A, 0x7), + WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K), + WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)), + WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)), + WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K), + WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)), + WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)), + + WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K), + WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)), + WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)), + WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K), + WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)), + WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)), + + WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7), + WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4), + WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7), + WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4), + WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500), + + WR16(B_CC_REG_DIVERSITY__A, 0x0001), + WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010), + WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | + B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE), + + /* 0x2a ), *//* CE to PASS mux */ + + END_OF_TABLE }; -u8_t DRXD_InitDiversityEnd[] = -{ - /* End demod *********** combining RF in and diversity in, MPEG TS out *****/ - /* disable near/far; switch on timing slave mode */ - WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | - B_SC_RA_RAM_CONFIG_FREQSCAN__M | - B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M | - B_SC_RA_RAM_CONFIG_SLAVE__M | - B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M +u8_t DRXD_InitDiversityEnd[] = { + /* End demod *********** combining RF in and diversity in, MPEG TS out **** */ + /* disable near/far; switch on timing slave mode */ + WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | + B_SC_RA_RAM_CONFIG_FREQSCAN__M | + B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M | + B_SC_RA_RAM_CONFIG_SLAVE__M | + B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M /* MV from CtrlDiversity */ - ), + ), #ifdef DRXDDIV_SRMM_SLAVING - WR16( SC_RA_RAM_LC_ABS_2K__A, 0x3c7), - WR16( SC_RA_RAM_LC_ABS_8K__A, 0x3c7), + WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7), + WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7), #else - WR16( SC_RA_RAM_LC_ABS_2K__A, 0x7), - WR16( SC_RA_RAM_LC_ABS_8K__A, 0x7), + WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7), + WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7), #endif - WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ), - WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ), - WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ), - WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ), - WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ), - WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ), - - WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ), - WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ), - WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ), - WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ), - WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ), - WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ), - - WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7), - WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4), - WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7), - WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4), - WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500), - - WR16( B_CC_REG_DIVERSITY__A, 0x0001 ), - END_OF_TABLE + WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K), + WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)), + WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)), + WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K), + WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)), + WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)), + + WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K), + WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)), + WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)), + WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K), + WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)), + WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)), + + WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7), + WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4), + WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7), + WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4), + WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500), + + WR16(B_CC_REG_DIVERSITY__A, 0x0001), + END_OF_TABLE }; -u8_t DRXD_DisableDiversity[] = -{ - WR16( B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE), - WR16( B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE), - WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE ), - WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE ), - WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE ), - WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE ), - WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE ), - WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE ), - - WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE ), - WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE ), - WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE ), - WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE ), - WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE ), - WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE ), - - WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE), - WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE), - WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE), - WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE), - WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE), - - - WR16( B_CC_REG_DIVERSITY__A, 0x0000 ), - WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT ), /* combining disabled*/ - - END_OF_TABLE +u8_t DRXD_DisableDiversity[] = { + WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE), + WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE), + WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, + B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE), + WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, + B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE), + WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, + B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE), + WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, + B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE), + WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, + B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE), + WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, + B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE), + + WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, + B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE), + WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, + B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE), + WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, + B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE), + WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, + B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE), + WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, + B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE), + WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, + B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE), + + WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE), + WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE), + WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE), + WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE), + WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE), + + WR16(B_CC_REG_DIVERSITY__A, 0x0000), + WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */ + + END_OF_TABLE }; -u8_t DRXD_StartDiversityFront[] = -{ - /* Start demod, RF in and diversity out, no combining */ - WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ), - WR16( B_FE_AD_REG_FDB_IN__A, 0x0 ), - WR16( B_FE_AD_REG_INVEXT__A, 0x0 ), - WR16( B_EQ_REG_COMM_MB__A, 0x12 ), /* EQ to MB out */ - WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */ - B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | - B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ), - - WR16( SC_RA_RAM_ECHO_SHIFT_LIM__A, 2 ), - - END_OF_TABLE +u8_t DRXD_StartDiversityFront[] = { + /* Start demod, RF in and diversity out, no combining */ + WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), + WR16(B_FE_AD_REG_FDB_IN__A, 0x0), + WR16(B_FE_AD_REG_INVEXT__A, 0x0), + WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */ + WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */ + B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE), + + WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2), + + END_OF_TABLE }; -u8_t DRXD_StartDiversityEnd[] = -{ - /* End demod, combining RF in and diversity in, MPEG TS out */ - WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ), /* disable impulse noise cruncher */ - WR16( B_FE_AD_REG_INVEXT__A, 0x0 ), /* clock inversion (for sohard board) */ - WR16( B_CP_REG_BR_STR_DEL__A, 10 ), /* apperently no mb delay matching is best */ +u8_t DRXD_StartDiversityEnd[] = { + /* End demod, combining RF in and diversity in, MPEG TS out */ + WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */ + WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */ + WR16(B_CP_REG_BR_STR_DEL__A, 10), /* apperently no mb delay matching is best */ - WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */ - B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | - B_EQ_REG_RC_SEL_CAR_PASS_A_CC | - B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC ), + WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */ + B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | + B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC), - END_OF_TABLE + END_OF_TABLE }; -u8_t DRXD_DiversityDelay8MHZ[] = -{ - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 1000 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 800 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4800 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 4000 - 50 ), - END_OF_TABLE +u8_t DRXD_DiversityDelay8MHZ[] = { + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 800 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4800 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 4000 - 50), + END_OF_TABLE }; -u8_t DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */ +u8_t DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */ { - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 900 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 600 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4500 - 50 ), - WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 3500 - 50 ), - END_OF_TABLE + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 900 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 600 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4500 - 50), + WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 3500 - 50), + END_OF_TABLE }; diff --git a/drivers/media/dvb/frontends/drxd_firm.h b/drivers/media/dvb/frontends/drxd_firm.h index fa704cbf7664..367930a11426 100644 --- a/drivers/media/dvb/frontends/drxd_firm.h +++ b/drivers/media/dvb/frontends/drxd_firm.h @@ -40,7 +40,7 @@ typedef unsigned long u32_t; #define HI_I2C_DELAY 84 #define HI_I2C_BRIDGE_DELAY 750 -#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */ +#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */ #define EQ_TD_TPS_PWR_QPSK 0x016a #define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195 #define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195 @@ -65,7 +65,6 @@ typedef unsigned long u32_t; #define DRXD_SCAN_TIMEOUT (650) - #define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L) #define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L) #define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L) @@ -78,7 +77,6 @@ typedef unsigned long u32_t; #define DIFF_TARGET (4) #define DIFF_MARGIN (1) - extern u8_t DRXD_InitAtomicRead[]; extern u8_t DRXD_HiI2cPatch_1[]; extern u8_t DRXD_HiI2cPatch_3[]; @@ -95,7 +93,7 @@ extern u8_t DRXD_InitECA2[]; extern u8_t DRXD_ResetECA2[]; extern u8_t DRXD_ResetECRAM[]; -extern u8_t DRXD_A2_microcode[]; +extern u8_t DRXD_A2_microcode[]; extern u32_t DRXD_A2_microcode_length; extern u8_t DRXD_InitFEB1_1[]; @@ -114,7 +112,7 @@ extern u8_t DRXD_StartDiversityEnd[]; extern u8_t DRXD_DiversityDelay8MHZ[]; extern u8_t DRXD_DiversityDelay6MHZ[]; -extern u8_t DRXD_B1_microcode[]; +extern u8_t DRXD_B1_microcode[]; extern u32_t DRXD_B1_microcode_length; #endif diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c index bdc004b65ea9..ed6c529946dd 100644 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -62,7 +62,6 @@ #define DRX_LOCK_FEC 2 #define DRX_LOCK_DEMOD 4 - /****************************************************************************/ enum CSCDState { @@ -91,11 +90,11 @@ enum OperationMode { struct SCfgAgc { enum AGC_CTRL_MODE ctrlMode; - u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ - u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */ - u16 minOutputLevel;/* range [0, ... , 1023], 1/n of fullscale range */ - u16 maxOutputLevel;/* range [0, ... , 1023], 1/n of fullscale range */ - u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */ + u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ + u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */ + u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ + u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */ + u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */ u16 R1; u16 R2; @@ -112,7 +111,7 @@ struct SNoiseCal { enum app_env { APPENV_STATIC = 0, APPENV_PORTABLE = 1, - APPENV_MOBILE = 2 + APPENV_MOBILE = 2 }; enum EIFFilter { @@ -136,7 +135,7 @@ struct drxd_state { int init_done; struct semaphore mutex; - u8 chip_adr; + u8 chip_adr; u16 hi_cfg_timing_div; u16 hi_cfg_bridge_delay; u16 hi_cfg_wakeup_key; @@ -205,14 +204,13 @@ struct drxd_state { }; - /****************************************************************************/ /* I2C **********************************************************************/ /****************************************************************************/ -static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len) { - struct i2c_msg msg = { .addr=adr, .flags=0, .buf=data, .len=len }; + struct i2c_msg msg = {.addr = adr,.flags = 0,.buf = data,.len = len }; if (i2c_transfer(adap, &msg, 1) != 1) return -1; @@ -220,12 +218,13 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) } static int i2c_read(struct i2c_adapter *adap, - u8 adr, u8 *msg, int len, u8 *answ, int alen) + u8 adr, u8 * msg, int len, u8 * answ, int alen) { - struct i2c_msg msgs[2] = { { .addr=adr, .flags=0, - .buf=msg, .len=len }, - { .addr=adr, .flags=I2C_M_RD, - .buf=answ, .len=alen } }; + struct i2c_msg msgs[2] = { {.addr = adr,.flags = 0, + .buf = msg,.len = len}, + {.addr = adr,.flags = I2C_M_RD, + .buf = answ,.len = alen} + }; if (i2c_transfer(adap, msgs, 2) != 2) return -1; return 0; @@ -235,75 +234,81 @@ inline u32 MulDiv32(u32 a, u32 b, u32 c) { u64 tmp64; - tmp64=(u64)a*(u64)b; + tmp64 = (u64) a *(u64) b; do_div(tmp64, c); return (u32) tmp64; } -static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) +static int Read16(struct drxd_state *state, u32 reg, u16 * data, u8 flags) { - u8 adr=state->config.demod_address; - u8 mm1[4]={reg&0xff, (reg>>16)&0xff, - flags|((reg>>24)&0xff), (reg>>8)&0xff}; + u8 adr = state->config.demod_address; + u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, + flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff + }; u8 mm2[2]; - if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2)<0) + if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0) return -1; if (data) - *data=mm2[0]|(mm2[1]<<8); - return mm2[0]|(mm2[1]<<8); + *data = mm2[0] | (mm2[1] << 8); + return mm2[0] | (mm2[1] << 8); } -static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) +static int Read32(struct drxd_state *state, u32 reg, u32 * data, u8 flags) { - u8 adr=state->config.demod_address; - u8 mm1[4]={reg&0xff, (reg>>16)&0xff, - flags|((reg>>24)&0xff), (reg>>8)&0xff}; + u8 adr = state->config.demod_address; + u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, + flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff + }; u8 mm2[4]; - if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4)<0) + if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0) return -1; if (data) - *data=mm2[0]|(mm2[1]<<8)|(mm2[2]<<16)|(mm2[3]<<24); + *data = + mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24); return 0; } static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags) { - u8 adr=state->config.demod_address; - u8 mm[6]={ reg&0xff, (reg>>16)&0xff, - flags|((reg>>24)&0xff), (reg>>8)&0xff, - data&0xff, (data>>8)&0xff }; + u8 adr = state->config.demod_address; + u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff, + flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, + data & 0xff, (data >> 8) & 0xff + }; - if (i2c_write(state->i2c, adr, mm, 6)<0) + if (i2c_write(state->i2c, adr, mm, 6) < 0) return -1; return 0; } static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) { - u8 adr=state->config.demod_address; - u8 mm[8]={ reg&0xff, (reg>>16)&0xff, - flags|((reg>>24)&0xff), (reg>>8)&0xff, - data&0xff, (data>>8)&0xff, - (data>>16)&0xff, (data>>24)&0xff }; + u8 adr = state->config.demod_address; + u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff, + flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff, + data & 0xff, (data >> 8) & 0xff, + (data >> 16) & 0xff, (data >> 24) & 0xff + }; - if (i2c_write(state->i2c, adr, mm, 8)<0) + if (i2c_write(state->i2c, adr, mm, 8) < 0) return -1; return 0; } static int write_chunk(struct drxd_state *state, - u32 reg, u8 *data, u32 len, u8 flags) + u32 reg, u8 * data, u32 len, u8 flags) { - u8 adr=state->config.demod_address; - u8 mm[CHUNK_SIZE+4]={ reg&0xff, (reg>>16)&0xff, - flags|((reg>>24)&0xff), (reg>>8)&0xff }; + u8 adr = state->config.demod_address; + u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff, + flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff + }; int i; - for (i=0; i<len; i++) - mm[4+i]=data[i]; - if (i2c_write(state->i2c, adr, mm, 4+len)<0) { + for (i = 0; i < len; i++) + mm[4 + i] = data[i]; + if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { printk("error in write_chunk\n"); return -1; } @@ -311,12 +316,12 @@ static int write_chunk(struct drxd_state *state, } static int WriteBlock(struct drxd_state *state, - u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags) + u32 Address, u16 BlockSize, u8 * pBlock, u8 Flags) { - while(BlockSize > 0) { + while (BlockSize > 0) { u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize; - if (write_chunk(state, Address, pBlock, Chunk, Flags)<0) + if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0) return -1; pBlock += Chunk; Address += (Chunk >> 1); @@ -325,33 +330,32 @@ static int WriteBlock(struct drxd_state *state, return 0; } -static int WriteTable(struct drxd_state *state, u8 *pTable) +static int WriteTable(struct drxd_state *state, u8 * pTable) { int status = 0; - if( pTable == NULL ) + if (pTable == NULL) return 0; - while(!status) { + while (!status) { u16 Length; - u32 Address = pTable[0]|(pTable[1]<<8)| - (pTable[2]<<16)|(pTable[3]<<24); + u32 Address = pTable[0] | (pTable[1] << 8) | + (pTable[2] << 16) | (pTable[3] << 24); - if (Address==0xFFFFFFFF) + if (Address == 0xFFFFFFFF) break; pTable += sizeof(u32); - Length = pTable[0]|(pTable[1]<<8); + Length = pTable[0] | (pTable[1] << 8); pTable += sizeof(u16); if (!Length) break; - status = WriteBlock(state, Address, Length*2, pTable, 0); - pTable += (Length*2); + status = WriteBlock(state, Address, Length * 2, pTable, 0); + pTable += (Length * 2); } return status; } - /****************************************************************************/ /****************************************************************************/ /****************************************************************************/ @@ -375,32 +379,32 @@ static int InitCE(struct drxd_state *state) CHK_ERROR(WriteTable(state, state->m_InitCE)); if (state->operation_mode == OM_DVBT_Diversity_Front || - state->operation_mode == OM_DVBT_Diversity_End ) { + state->operation_mode == OM_DVBT_Diversity_End) { AppEnv = state->app_env_diversity; } - if ( AppEnv == APPENV_STATIC ) { - CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0000,0)); - } else if( AppEnv == APPENV_PORTABLE ) { - CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0001,0)); - } else if( AppEnv == APPENV_MOBILE && state->type_A ) { - CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0002,0)); - } else if( AppEnv == APPENV_MOBILE && !state->type_A ) { - CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0006,0)); + if (AppEnv == APPENV_STATIC) { + CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0000, 0)); + } else if (AppEnv == APPENV_PORTABLE) { + CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0001, 0)); + } else if (AppEnv == APPENV_MOBILE && state->type_A) { + CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0002, 0)); + } else if (AppEnv == APPENV_MOBILE && !state->type_A) { + CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0006, 0)); } /* start ce */ - CHK_ERROR(Write16(state,B_CE_REG_COMM_EXEC__A,0x0001,0)); - } while(0); + CHK_ERROR(Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0)); + } while (0); return status; } static int StopOC(struct drxd_state *state) { int status = 0; - u16 ocSyncLvl = 0; - u16 ocModeLop = state->m_EcOcRegOcModeLop; - u16 dtoIncLop = 0; - u16 dtoIncHip = 0; + u16 ocSyncLvl = 0; + u16 ocModeLop = state->m_EcOcRegOcModeLop; + u16 dtoIncLop = 0; + u16 dtoIncHip = 0; do { /* Store output configuration */ @@ -413,65 +417,65 @@ static int StopOC(struct drxd_state *state) /* Flush FIFO (byte-boundary) at fixed rate */ CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_LOP__A, - &dtoIncLop,0 )); + &dtoIncLop, 0)); CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_HIP__A, - &dtoIncHip,0 )); + &dtoIncHip, 0)); CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_LOP__A, - dtoIncLop,0 )); + dtoIncLop, 0)); CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_HIP__A, - dtoIncHip,0 )); + dtoIncHip, 0)); ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M); - ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC; + ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC; CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, - ocModeLop,0 )); + ocModeLop, 0)); CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, - EC_OC_REG_COMM_EXEC_CTL_HOLD,0 )); + EC_OC_REG_COMM_EXEC_CTL_HOLD, 0)); msleep(1); /* Output pins to '0' */ CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A, - EC_OC_REG_OCR_MPG_UOS__M,0 )); + EC_OC_REG_OCR_MPG_UOS__M, 0)); /* Force the OC out of sync */ ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M); CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A, - ocSyncLvl,0 )); + ocSyncLvl, 0)); ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M); - ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE; - ocModeLop |= 0x2; /* Magically-out-of-sync */ + ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE; + ocModeLop |= 0x2; /* Magically-out-of-sync */ CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, - ocModeLop,0 )); - CHK_ERROR(Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0,0 )); + ocModeLop, 0)); + CHK_ERROR(Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0)); CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, - EC_OC_REG_COMM_EXEC_CTL_ACTIVE,0 )); - } while(0); + EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0)); + } while (0); return status; } static int StartOC(struct drxd_state *state) { - int status=0; + int status = 0; do { /* Stop OC */ CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, - EC_OC_REG_COMM_EXEC_CTL_HOLD,0 )); + EC_OC_REG_COMM_EXEC_CTL_HOLD, 0)); /* Restore output configuration */ CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A, - state->m_EcOcRegSncSncLvl,0 )); + state->m_EcOcRegSncSncLvl, 0)); CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, - state->m_EcOcRegOcModeLop,0 )); + state->m_EcOcRegOcModeLop, 0)); /* Output pins active again */ CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A, - EC_OC_REG_OCR_MPG_UOS_INIT,0 )); + EC_OC_REG_OCR_MPG_UOS_INIT, 0)); /* Start OC */ CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, - EC_OC_REG_COMM_EXEC_CTL_ACTIVE,0 )); - } while(0); + EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0)); + } while (0); return status; } @@ -497,40 +501,39 @@ static int InitAtomicRead(struct drxd_state *state) static int CorrectSysClockDeviation(struct drxd_state *state); -static int DRX_GetLockStatus(struct drxd_state *state, u32 *pLockStatus) +static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus) { u16 ScRaRamLock = 0; - const u16 mpeg_lock_mask = ( SC_RA_RAM_LOCK_MPEG__M | - SC_RA_RAM_LOCK_FEC__M | - SC_RA_RAM_LOCK_DEMOD__M ); - const u16 fec_lock_mask = ( SC_RA_RAM_LOCK_FEC__M | - SC_RA_RAM_LOCK_DEMOD__M ); - const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M ; + const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M | + SC_RA_RAM_LOCK_FEC__M | + SC_RA_RAM_LOCK_DEMOD__M); + const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M | + SC_RA_RAM_LOCK_DEMOD__M); + const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M; int status; - *pLockStatus=0; + *pLockStatus = 0; - status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000 ); - if(status<0) { - printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n", - status); + status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); + if (status < 0) { + printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n", status); return status; } - if( state->drxd_state != DRXD_STARTED ) + if (state->drxd_state != DRXD_STARTED) return 0; - if ( (ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask ) { - *pLockStatus|=DRX_LOCK_MPEG; + if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) { + *pLockStatus |= DRX_LOCK_MPEG; CorrectSysClockDeviation(state); } - if ( (ScRaRamLock & fec_lock_mask) == fec_lock_mask ) - *pLockStatus|=DRX_LOCK_FEC; + if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) + *pLockStatus |= DRX_LOCK_FEC; - if ( (ScRaRamLock & demod_lock_mask) == demod_lock_mask ) - *pLockStatus|=DRX_LOCK_DEMOD; + if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) + *pLockStatus |= DRX_LOCK_DEMOD; return 0; } @@ -540,35 +543,33 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) { int status; - if( cfg->outputLevel > DRXD_FE_CTRL_MAX ) - return -1; + if (cfg->outputLevel > DRXD_FE_CTRL_MAX) + return -1; - if( cfg->ctrlMode == AGC_CTRL_USER ) { + if (cfg->ctrlMode == AGC_CTRL_USER) { do { u16 FeAgRegPm1AgcWri; u16 FeAgRegAgModeLop; - CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A, - &FeAgRegAgModeLop,0)); - FeAgRegAgModeLop &= - (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); - FeAgRegAgModeLop |= - FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC; - CHK_ERROR(Write16(state,FE_AG_REG_AG_MODE_LOP__A, - FeAgRegAgModeLop,0)); - - FeAgRegPm1AgcWri = (u16)(cfg->outputLevel & - FE_AG_REG_PM1_AGC_WRI__M); - CHK_ERROR(Write16(state,FE_AG_REG_PM1_AGC_WRI__A, - FeAgRegPm1AgcWri,0)); + CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, + &FeAgRegAgModeLop, 0)); + FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); + FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC; + CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, + FeAgRegAgModeLop, 0)); + + FeAgRegPm1AgcWri = (u16) (cfg->outputLevel & + FE_AG_REG_PM1_AGC_WRI__M); + CHK_ERROR(Write16(state, FE_AG_REG_PM1_AGC_WRI__A, + FeAgRegPm1AgcWri, 0)); } - while(0); - } else if( cfg->ctrlMode == AGC_CTRL_AUTO ) { - if ( ( (cfg->maxOutputLevel) < (cfg->minOutputLevel) ) || - ( (cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX ) || - ( (cfg->speed) > DRXD_FE_CTRL_MAX ) || - ( (cfg->settleLevel) > DRXD_FE_CTRL_MAX ) - ) + while (0); + } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { + if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) || + ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) || + ((cfg->speed) > DRXD_FE_CTRL_MAX) || + ((cfg->settleLevel) > DRXD_FE_CTRL_MAX) + ) return (-1); do { u16 FeAgRegAgModeLop; @@ -577,94 +578,95 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) /* == Mode == */ - CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A, - &FeAgRegAgModeLop,0)); - FeAgRegAgModeLop &= - (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); + CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, + &FeAgRegAgModeLop, 0)); + FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); FeAgRegAgModeLop |= - FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC; - CHK_ERROR(Write16(state,FE_AG_REG_AG_MODE_LOP__A, - FeAgRegAgModeLop,0)); + FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC; + CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, + FeAgRegAgModeLop, 0)); /* == Settle level == */ - FeAgRegEgcSetLvl = (u16)(( cfg->settleLevel >> 1 ) & - FE_AG_REG_EGC_SET_LVL__M ); - CHK_ERROR(Write16(state,FE_AG_REG_EGC_SET_LVL__A, - FeAgRegEgcSetLvl,0)); + FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) & + FE_AG_REG_EGC_SET_LVL__M); + CHK_ERROR(Write16(state, FE_AG_REG_EGC_SET_LVL__A, + FeAgRegEgcSetLvl, 0)); /* == Min/Max == */ - slope = (u16)(( cfg->maxOutputLevel - - cfg->minOutputLevel )/2); - offset = (u16)(( cfg->maxOutputLevel + - cfg->minOutputLevel )/2 - 511); + slope = (u16) ((cfg->maxOutputLevel - + cfg->minOutputLevel) / 2); + offset = (u16) ((cfg->maxOutputLevel + + cfg->minOutputLevel) / 2 - 511); - CHK_ERROR(Write16(state,FE_AG_REG_GC1_AGC_RIC__A, - slope,0)); - CHK_ERROR(Write16(state,FE_AG_REG_GC1_AGC_OFF__A, - offset,0)); + CHK_ERROR(Write16(state, FE_AG_REG_GC1_AGC_RIC__A, + slope, 0)); + CHK_ERROR(Write16(state, FE_AG_REG_GC1_AGC_OFF__A, + offset, 0)); /* == Speed == */ { const u16 maxRur = 8; - const u16 slowIncrDecLUT[]={ 3, 4, 4, 5, 6 }; - const u16 fastIncrDecLUT[]={ 14, 15, 15, 16, - 17, 18, 18, 19, - 20, 21, 22, 23, - 24, 26, 27, 28, - 29, 31}; - - u16 fineSteps = (DRXD_FE_CTRL_MAX+1)/ - (maxRur+1); - u16 fineSpeed = (u16)(cfg->speed - - ((cfg->speed/ - fineSteps)* + const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 }; + const u16 fastIncrDecLUT[] = { 14, 15, 15, 16, + 17, 18, 18, 19, + 20, 21, 22, 23, + 24, 26, 27, 28, + 29, 31 + }; + + u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) / + (maxRur + 1); + u16 fineSpeed = (u16) (cfg->speed - + ((cfg->speed / + fineSteps) * fineSteps)); - u16 invRurCount= (u16)(cfg->speed / - fineSteps); + u16 invRurCount = (u16) (cfg->speed / + fineSteps); u16 rurCount; - if ( invRurCount > maxRur ) - { - rurCount = 0; + if (invRurCount > maxRur) { + rurCount = 0; fineSpeed += fineSteps; } else { - rurCount = maxRur - invRurCount; + rurCount = maxRur - invRurCount; } /* - fastInc = default * - (2^(fineSpeed/fineSteps)) - => range[default...2*default> - slowInc = default * - (2^(fineSpeed/fineSteps)) - */ + fastInc = default * + (2^(fineSpeed/fineSteps)) + => range[default...2*default> + slowInc = default * + (2^(fineSpeed/fineSteps)) + */ { u16 fastIncrDec = - fastIncrDecLUT[fineSpeed/ - ((fineSteps/ - (14+1))+1) ]; - u16 slowIncrDec = slowIncrDecLUT[ - fineSpeed/(fineSteps/(3+1)) ]; + fastIncrDecLUT[fineSpeed / + ((fineSteps / + (14 + 1)) + 1)]; + u16 slowIncrDec = + slowIncrDecLUT[fineSpeed / + (fineSteps / + (3 + 1))]; CHK_ERROR(Write16(state, - FE_AG_REG_EGC_RUR_CNT__A, + FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0)); CHK_ERROR(Write16(state, - FE_AG_REG_EGC_FAS_INC__A, + FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0)); CHK_ERROR(Write16(state, - FE_AG_REG_EGC_FAS_DEC__A, + FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0)); CHK_ERROR(Write16(state, - FE_AG_REG_EGC_SLO_INC__A, + FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0)); CHK_ERROR(Write16(state, - FE_AG_REG_EGC_SLO_DEC__A, + FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0)); } } - } while(0); + } while (0); } else { /* No OFF mode for IF control */ @@ -673,90 +675,87 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) return status; } - static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) { int status = 0; - if( cfg->outputLevel > DRXD_FE_CTRL_MAX ) + if (cfg->outputLevel > DRXD_FE_CTRL_MAX) return -1; - if( cfg->ctrlMode == AGC_CTRL_USER ) { + if (cfg->ctrlMode == AGC_CTRL_USER) { do { - u16 AgModeLop=0; - u16 level = ( cfg->outputLevel ); + u16 AgModeLop = 0; + u16 level = (cfg->outputLevel); - if (level == DRXD_FE_CTRL_MAX ) + if (level == DRXD_FE_CTRL_MAX) level++; - CHK_ERROR( Write16(state,FE_AG_REG_PM2_AGC_WRI__A, - level, 0x0000 )); + CHK_ERROR(Write16(state, FE_AG_REG_PM2_AGC_WRI__A, + level, 0x0000)); /*==== Mode ====*/ /* Powerdown PD2, WRI source */ - state->m_FeAgRegAgPwd &= - ~(FE_AG_REG_AG_PWD_PWD_PD2__M); + state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); state->m_FeAgRegAgPwd |= - FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; - CHK_ERROR( Write16(state,FE_AG_REG_AG_PWD__A, - state->m_FeAgRegAgPwd,0x0000 )); - - CHK_ERROR( Read16(state,FE_AG_REG_AG_MODE_LOP__A, - &AgModeLop,0x0000 )); - AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M | - FE_AG_REG_AG_MODE_LOP_MODE_E__M)); - AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | - FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC ); - CHK_ERROR( Write16(state,FE_AG_REG_AG_MODE_LOP__A, - AgModeLop,0x0000 )); + FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; + CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A, + state->m_FeAgRegAgPwd, 0x0000)); + CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, + &AgModeLop, 0x0000)); + AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | + FE_AG_REG_AG_MODE_LOP_MODE_E__M)); + AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | + FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); + CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, + AgModeLop, 0x0000)); /* enable AGC2 pin */ { u16 FeAgRegAgAgcSio = 0; - CHK_ERROR( Read16(state, - FE_AG_REG_AG_AGC_SIO__A, - &FeAgRegAgAgcSio, 0x0000 )); + CHK_ERROR(Read16(state, + FE_AG_REG_AG_AGC_SIO__A, + &FeAgRegAgAgcSio, 0x0000)); FeAgRegAgAgcSio &= - ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); + ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); FeAgRegAgAgcSio |= - FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; - CHK_ERROR( Write16(state, - FE_AG_REG_AG_AGC_SIO__A, - FeAgRegAgAgcSio, 0x0000 )); + FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; + CHK_ERROR(Write16(state, + FE_AG_REG_AG_AGC_SIO__A, + FeAgRegAgAgcSio, 0x0000)); } - } while(0); - } else if( cfg->ctrlMode == AGC_CTRL_AUTO ) { - u16 AgModeLop=0; + } while (0); + } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { + u16 AgModeLop = 0; do { u16 level; /* Automatic control */ /* Powerup PD2, AGC2 as output, TGC source */ (state->m_FeAgRegAgPwd) &= - ~(FE_AG_REG_AG_PWD_PWD_PD2__M); + ~(FE_AG_REG_AG_PWD_PWD_PD2__M); (state->m_FeAgRegAgPwd) |= - FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; - CHK_ERROR(Write16(state,FE_AG_REG_AG_PWD__A, - (state->m_FeAgRegAgPwd),0x0000 )); - - CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A, - &AgModeLop,0x0000 )); - AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M | - FE_AG_REG_AG_MODE_LOP_MODE_E__M)); - AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | - FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC ); + FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; + CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A, + (state->m_FeAgRegAgPwd), 0x0000)); + + CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, + &AgModeLop, 0x0000)); + AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | + FE_AG_REG_AG_MODE_LOP_MODE_E__M)); + AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | + FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC); CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, - AgModeLop, 0x0000 )); + AgModeLop, 0x0000)); /* Settle level */ - level = ( (( cfg->settleLevel )>>4) & - FE_AG_REG_TGC_SET_LVL__M ); + level = (((cfg->settleLevel) >> 4) & + FE_AG_REG_TGC_SET_LVL__M); CHK_ERROR(Write16(state, FE_AG_REG_TGC_SET_LVL__A, - level,0x0000 )); + level, 0x0000)); /* Min/max: don't care */ @@ -765,91 +764,91 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) /* enable AGC2 pin */ { u16 FeAgRegAgAgcSio = 0; - CHK_ERROR( Read16(state, - FE_AG_REG_AG_AGC_SIO__A, - &FeAgRegAgAgcSio, 0x0000 )); + CHK_ERROR(Read16(state, + FE_AG_REG_AG_AGC_SIO__A, + &FeAgRegAgAgcSio, 0x0000)); FeAgRegAgAgcSio &= - ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); + ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); FeAgRegAgAgcSio |= - FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; - CHK_ERROR( Write16(state, - FE_AG_REG_AG_AGC_SIO__A, - FeAgRegAgAgcSio, 0x0000 )); + FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; + CHK_ERROR(Write16(state, + FE_AG_REG_AG_AGC_SIO__A, + FeAgRegAgAgcSio, 0x0000)); } - } while(0); + } while (0); } else { - u16 AgModeLop=0; + u16 AgModeLop = 0; do { /* No RF AGC control */ /* Powerdown PD2, AGC2 as output, WRI source */ (state->m_FeAgRegAgPwd) &= - ~(FE_AG_REG_AG_PWD_PWD_PD2__M); + ~(FE_AG_REG_AG_PWD_PWD_PD2__M); (state->m_FeAgRegAgPwd) |= - FE_AG_REG_AG_PWD_PWD_PD2_ENABLE; + FE_AG_REG_AG_PWD_PWD_PD2_ENABLE; CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A, - (state->m_FeAgRegAgPwd),0x0000 )); + (state->m_FeAgRegAgPwd), 0x0000)); CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, - &AgModeLop,0x0000 )); - AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M | - FE_AG_REG_AG_MODE_LOP_MODE_E__M)); - AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | - FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC ); + &AgModeLop, 0x0000)); + AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | + FE_AG_REG_AG_MODE_LOP_MODE_E__M)); + AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | + FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, - AgModeLop,0x0000 )); + AgModeLop, 0x0000)); /* set FeAgRegAgAgcSio AGC2 (RF) as input */ { u16 FeAgRegAgAgcSio = 0; - CHK_ERROR( Read16(state, - FE_AG_REG_AG_AGC_SIO__A, - &FeAgRegAgAgcSio, 0x0000 )); + CHK_ERROR(Read16(state, + FE_AG_REG_AG_AGC_SIO__A, + &FeAgRegAgAgcSio, 0x0000)); FeAgRegAgAgcSio &= - ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); + ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); FeAgRegAgAgcSio |= - FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT; - CHK_ERROR( Write16(state, - FE_AG_REG_AG_AGC_SIO__A, - FeAgRegAgAgcSio, 0x0000 )); + FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT; + CHK_ERROR(Write16(state, + FE_AG_REG_AG_AGC_SIO__A, + FeAgRegAgAgcSio, 0x0000)); } - } while(0); + } while (0); } return status; } -static int ReadIFAgc(struct drxd_state *state, u32 *pValue) +static int ReadIFAgc(struct drxd_state *state, u32 * pValue) { int status = 0; *pValue = 0; - if( state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF ) { + if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) { u16 Value; - status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A,&Value,0); + status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0); Value &= FE_AG_REG_GC1_AGC_DAT__M; - if(status>=0) { + if (status >= 0) { /* 3.3V - | - R1 - | + | + R1 + | Vin - R3 - * -- Vout - | - R2 - | - GND - */ + | + R2 + | + GND + */ u32 R1 = state->if_agc_cfg.R1; u32 R2 = state->if_agc_cfg.R2; u32 R3 = state->if_agc_cfg.R3; - u32 Vmax = (3300 * R2) / ( R1 + R2 ); - u32 Rpar = ( R2 * R3 ) / ( R3 + R2 ); - u32 Vmin = (3300 * Rpar ) / ( R1 + Rpar ); - u32 Vout = Vmin + (( Vmax - Vmin ) * Value) / 1024; + u32 Vmax = (3300 * R2) / (R1 + R2); + u32 Rpar = (R2 * R3) / (R3 + R2); + u32 Vmin = (3300 * Rpar) / (R1 + Rpar); + u32 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024; *pValue = Vout; } @@ -878,7 +877,7 @@ static int load_firmware(struct drxd_state *state, const char *fw_name) } static int DownloadMicrocode(struct drxd_state *state, - const u8 *pMCImage, u32 Length) + const u8 * pMCImage, u32 Length) { u8 *pSrc; u16 Flags; @@ -886,32 +885,38 @@ static int DownloadMicrocode(struct drxd_state *state, u16 nBlocks; u16 BlockSize; u16 BlockCRC; - u32 offset=0; - int i, status=0; + u32 offset = 0; + int i, status = 0; - pSrc=(u8 *) pMCImage; + pSrc = (u8 *) pMCImage; Flags = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); + pSrc += sizeof(u16); + offset += sizeof(u16); nBlocks = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); + pSrc += sizeof(u16); + offset += sizeof(u16); - for(i=0; i<nBlocks; i++ ) { - Address=(pSrc[0] << 24) | (pSrc[1] << 16) | - (pSrc[2] << 8) | pSrc[3]; - pSrc += sizeof(u32); offset += sizeof(u32); + for (i = 0; i < nBlocks; i++) { + Address = (pSrc[0] << 24) | (pSrc[1] << 16) | + (pSrc[2] << 8) | pSrc[3]; + pSrc += sizeof(u32); + offset += sizeof(u32); - BlockSize = ( (pSrc[0] << 8) | pSrc[1] ) * sizeof(u16); - pSrc += sizeof(u16); offset += sizeof(u16); + BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); + pSrc += sizeof(u16); + offset += sizeof(u16); Flags = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); + pSrc += sizeof(u16); + offset += sizeof(u16); BlockCRC = (pSrc[0] << 8) | pSrc[1]; - pSrc += sizeof(u16); offset += sizeof(u16); + pSrc += sizeof(u16); + offset += sizeof(u16); - status = WriteBlock(state,Address,BlockSize, - pSrc,DRX_I2C_CLEARCRC); - if (status<0) + status = WriteBlock(state, Address, BlockSize, + pSrc, DRX_I2C_CLEARCRC); + if (status < 0) break; pSrc += BlockSize; offset += BlockSize; @@ -920,51 +925,48 @@ static int DownloadMicrocode(struct drxd_state *state, return status; } -static int HI_Command(struct drxd_state *state, u16 cmd, u16 *pResult) +static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) { u32 nrRetries = 0; u16 waitCmd; int status; - if ((status=Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0))<0) + if ((status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0)) < 0) return status; do { - nrRetries+=1; - if (nrRetries>DRXD_MAX_RETRIES) { - status=-1; + nrRetries += 1; + if (nrRetries > DRXD_MAX_RETRIES) { + status = -1; break; }; - status=Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); - } while (waitCmd!=0); + status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0); + } while (waitCmd != 0); - if (status>=0) - status=Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); + if (status >= 0) + status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0); return status; } static int HI_CfgCommand(struct drxd_state *state) { - int status=0; + int status = 0; down(&state->mutex); - Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, - HI_RA_RAM_SRV_RST_KEY_ACT, 0); + Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); - Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, - state->hi_cfg_bridge_delay, 0); + Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0); Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0); - Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, - HI_RA_RAM_SRV_RST_KEY_ACT, 0); + Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); - if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)== + if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) == HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) - status=Write16(state, HI_RA_RAM_SRV_CMD__A, - HI_RA_RAM_SRV_CMD_CONFIG, 0); + status = Write16(state, HI_RA_RAM_SRV_CMD__A, + HI_RA_RAM_SRV_CMD_CONFIG, 0); else - status=HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0); + status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0); up(&state->mutex); return status; } @@ -974,7 +976,7 @@ static int InitHI(struct drxd_state *state) state->hi_cfg_wakeup_key = (state->chip_adr); /* port/bridge/power down ctrl */ state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON; - return HI_CfgCommand(state); + return HI_CfgCommand(state); } static int HI_ResetCommand(struct drxd_state *state) @@ -982,20 +984,19 @@ static int HI_ResetCommand(struct drxd_state *state) int status; down(&state->mutex); - status=Write16(state, HI_RA_RAM_SRV_RST_KEY__A, - HI_RA_RAM_SRV_RST_KEY_ACT, 0); - if (status==0) - status=HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0); + status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, + HI_RA_RAM_SRV_RST_KEY_ACT, 0); + if (status == 0) + status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0); up(&state->mutex); msleep(1); return status; } -static int DRX_ConfigureI2CBridge(struct drxd_state *state, - int bEnableBridge) +static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge) { state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M); - if ( bEnableBridge ) + if (bEnableBridge) state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON; else state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF; @@ -1010,13 +1011,13 @@ static int DRX_ConfigureI2CBridge(struct drxd_state *state, #if 0 static int AtomicReadBlock(struct drxd_state *state, - u32 Addr, u16 DataSize, u8 *pData, u8 Flags) + u32 Addr, u16 DataSize, u8 * pData, u8 Flags) { int status; - int i=0; + int i = 0; /* Parameter check */ - if ( (!pData) || ( (DataSize & 1)!=0 ) ) + if ((!pData) || ((DataSize & 1) != 0)) return -1; down(&state->mutex); @@ -1024,31 +1025,31 @@ static int AtomicReadBlock(struct drxd_state *state, do { /* Instruct HI to read n bytes */ /* TODO use proper names forthese egisters */ - CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_KEY__A, - (HI_TR_FUNC_ADDR & 0xFFFF), 0)); - CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_DIV__A, - (u16)(Addr >> 16), 0)); - CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_BDL__A, - (u16)(Addr & 0xFFFF), 0)); - CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_WUP__A, - (u16)((DataSize/2) - 1), 0)); - CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_ACT__A, - HI_TR_READ, 0)); - - CHK_ERROR( HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE,0)); - - } while(0); - - if (status>=0) { - for (i = 0; i < (DataSize/2); i += 1) { + CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, + (HI_TR_FUNC_ADDR & 0xFFFF), 0)); + CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, + (u16) (Addr >> 16), 0)); + CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, + (u16) (Addr & 0xFFFF), 0)); + CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, + (u16) ((DataSize / 2) - 1), 0)); + CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, + HI_TR_READ, 0)); + + CHK_ERROR(HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0)); + + } while (0); + + if (status >= 0) { + for (i = 0; i < (DataSize / 2); i += 1) { u16 word; status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i), &word, 0); - if( status<0) + if (status < 0) break; - pData[2*i] = (u8) (word & 0xFF); - pData[(2*i) + 1] = (u8) (word >> 8 ); + pData[2 * i] = (u8) (word & 0xFF); + pData[(2 * i) + 1] = (u8) (word >> 8); } } up(&state->mutex); @@ -1056,18 +1057,17 @@ static int AtomicReadBlock(struct drxd_state *state, } static int AtomicReadReg32(struct drxd_state *state, - u32 Addr, u32 *pData, u8 Flags) + u32 Addr, u32 * pData, u8 Flags) { - u8 buf[sizeof (u32)]; + u8 buf[sizeof(u32)]; int status; if (!pData) return -1; - status=AtomicReadBlock(state, Addr, sizeof (u32), buf, Flags); - *pData = (((u32) buf[0]) << 0) + - (((u32) buf[1]) << 8) + - (((u32) buf[2]) << 16) + - (((u32) buf[3]) << 24); + status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags); + *pData = (((u32) buf[0]) << 0) + + (((u32) buf[1]) << 8) + + (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24); return status; } #endif @@ -1095,7 +1095,7 @@ static int InitCC(struct drxd_state *state) { if (state->osc_clock_freq == 0 || state->osc_clock_freq > 20000 || - (state->osc_clock_freq % 4000 ) != 0 ) { + (state->osc_clock_freq % 4000) != 0) { printk("invalid osc frequency %d\n", state->osc_clock_freq); return -1; } @@ -1103,7 +1103,7 @@ static int InitCC(struct drxd_state *state) Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0); Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL | CC_REG_PLL_MODE_PUMP_CUR_12, 0); - Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq/4000, 0); + Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0); Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0); Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0); @@ -1114,19 +1114,18 @@ static int ResetECOD(struct drxd_state *state) { int status = 0; - if(state->type_A ) + if (state->type_A) status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0); else status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0); - if (!(status<0)) + if (!(status < 0)) status = WriteTable(state, state->m_ResetECRAM); - if (!(status<0)) + if (!(status < 0)) status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0); return status; } - /* Configure PGA switch */ static int SetCfgPga(struct drxd_state *state, int pgaSwitch) @@ -1135,28 +1134,28 @@ static int SetCfgPga(struct drxd_state *state, int pgaSwitch) u16 AgModeLop = 0; u16 AgModeHip = 0; do { - if ( pgaSwitch ) { + if (pgaSwitch) { /* PGA on */ /* fine gain */ CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000)); - AgModeLop&=(~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); - AgModeLop|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC; + AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); + AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC; CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000)); /* coarse gain */ CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000)); - AgModeHip&=(~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); - AgModeHip|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC ; + AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); + AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC; CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000)); /* enable fine and coarse gain, enable AAF, no ext resistor */ CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, - B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, + B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000)); } else { /* PGA off, bypass */ @@ -1164,71 +1163,73 @@ static int SetCfgPga(struct drxd_state *state, int pgaSwitch) /* fine gain */ CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000)); - AgModeLop&=(~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); - AgModeLop|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC ; + AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); + AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC; CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000)); /* coarse gain */ CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000)); - AgModeHip&=(~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); - AgModeHip|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC ; + AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); + AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC; CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000)); /* disable fine and coarse gain, enable AAF, no ext resistor */ CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, - B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, + B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000)); } } - while(0); + while (0); return status; } static int InitFE(struct drxd_state *state) { - int status; - - do - { - CHK_ERROR( WriteTable(state, state->m_InitFE_1)); + int status; - if( state->type_A ) { - status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, - FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0); - } else { - if (state->PGA) - status = SetCfgPga(state, 0); - else - status = - Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, - B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0); - } + do { + CHK_ERROR(WriteTable(state, state->m_InitFE_1)); - if (status<0) break; - CHK_ERROR( Write16( state, FE_AG_REG_AG_AGC_SIO__A, - state->m_FeAgRegAgAgcSio, 0x0000)); - CHK_ERROR( Write16( state, FE_AG_REG_AG_PWD__A,state->m_FeAgRegAgPwd, - 0x0000)); + if (state->type_A) { + status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, + FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, + 0); + } else { + if (state->PGA) + status = SetCfgPga(state, 0); + else + status = + Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, + B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, + 0); + } - CHK_ERROR( WriteTable(state, state->m_InitFE_2)); + if (status < 0) + break; + CHK_ERROR(Write16(state, FE_AG_REG_AG_AGC_SIO__A, + state->m_FeAgRegAgAgcSio, 0x0000)); + CHK_ERROR(Write16 + (state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, + 0x0000)); + CHK_ERROR(WriteTable(state, state->m_InitFE_2)); - } while(0); + } while (0); - return status; + return status; } static int InitFT(struct drxd_state *state) { /* - norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk - SC stuff - */ - return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000 ); + norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk + SC stuff + */ + return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000); } static int SC_WaitForReady(struct drxd_state *state) @@ -1236,10 +1237,9 @@ static int SC_WaitForReady(struct drxd_state *state) u16 curCmd; int i; - for(i = 0; i < DRXD_MAX_RETRIES; i += 1 ) - { - int status = Read16(state, SC_RA_RAM_CMD__A,&curCmd,0); - if (status==0 || curCmd == 0 ) + for (i = 0; i < DRXD_MAX_RETRIES; i += 1) { + int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0); + if (status == 0 || curCmd == 0) return status; } return -1; @@ -1247,79 +1247,75 @@ static int SC_WaitForReady(struct drxd_state *state) static int SC_SendCommand(struct drxd_state *state, u16 cmd) { - int status=0; + int status = 0; u16 errCode; - Write16(state, SC_RA_RAM_CMD__A,cmd,0); + Write16(state, SC_RA_RAM_CMD__A, cmd, 0); SC_WaitForReady(state); - Read16(state, SC_RA_RAM_CMD_ADDR__A,&errCode,0); + Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); - if( errCode == 0xFFFF ) - { - printk("Command Error\n"); - status = -1; + if (errCode == 0xFFFF) { + printk("Command Error\n"); + status = -1; } return status; } static int SC_ProcStartCommand(struct drxd_state *state, - u16 subCmd,u16 param0,u16 param1) + u16 subCmd, u16 param0, u16 param1) { - int status=0; + int status = 0; u16 scExec; down(&state->mutex); do { Read16(state, SC_COMM_EXEC__A, &scExec, 0); if (scExec != 1) { - status=-1; + status = -1; break; } SC_WaitForReady(state); - Write16(state, SC_RA_RAM_CMD_ADDR__A,subCmd,0); - Write16(state, SC_RA_RAM_PARAM1__A,param1,0); - Write16(state, SC_RA_RAM_PARAM0__A,param0,0); + Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); + Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); + Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); - } while(0); + } while (0); up(&state->mutex); return status; } - static int SC_SetPrefParamCommand(struct drxd_state *state, - u16 subCmd,u16 param0,u16 param1) + u16 subCmd, u16 param0, u16 param1) { int status; down(&state->mutex); do { - CHK_ERROR( SC_WaitForReady(state) ); - CHK_ERROR( Write16(state,SC_RA_RAM_CMD_ADDR__A,subCmd,0) ); - CHK_ERROR( Write16(state,SC_RA_RAM_PARAM1__A,param1,0) ); - CHK_ERROR( Write16(state,SC_RA_RAM_PARAM0__A,param0,0) ); - - CHK_ERROR( SC_SendCommand(state, - SC_RA_RAM_CMD_SET_PREF_PARAM) ); - } while(0); + CHK_ERROR(SC_WaitForReady(state)); + CHK_ERROR(Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0)); + CHK_ERROR(Write16(state, SC_RA_RAM_PARAM1__A, param1, 0)); + CHK_ERROR(Write16(state, SC_RA_RAM_PARAM0__A, param0, 0)); + + CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM)); + } while (0); up(&state->mutex); return status; } #if 0 -static int SC_GetOpParamCommand(struct drxd_state *state, u16 *result) +static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result) { - int status=0; + int status = 0; down(&state->mutex); do { - CHK_ERROR( SC_WaitForReady(state) ); - CHK_ERROR( SC_SendCommand(state, - SC_RA_RAM_CMD_GET_OP_PARAM) ); - CHK_ERROR( Read16(state, SC_RA_RAM_PARAM0__A,result, 0 ) ); - } while(0); + CHK_ERROR(SC_WaitForReady(state)); + CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM)); + CHK_ERROR(Read16(state, SC_RA_RAM_PARAM0__A, result, 0)); + } while (0); up(&state->mutex); return status; } @@ -1333,45 +1329,38 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) u16 EcOcRegIprInvMpg = 0; u16 EcOcRegOcModeLop = 0; u16 EcOcRegOcModeHip = 0; - u16 EcOcRegOcMpgSio = 0; + u16 EcOcRegOcMpgSio = 0; /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, - &EcOcRegOcModeLop, 0));*/ + &EcOcRegOcModeLop, 0)); */ - if( state->operation_mode == OM_DVBT_Diversity_Front ) - { - if ( bEnableOutput ) - { + if (state->operation_mode == OM_DVBT_Diversity_Front) { + if (bEnableOutput) { EcOcRegOcModeHip |= - B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR; - } - else + B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR; + } else EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; EcOcRegOcModeLop |= - EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; - } - else - { + EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; + } else { EcOcRegOcModeLop = state->m_EcOcRegOcModeLop; if (bEnableOutput) - EcOcRegOcMpgSio &= - (~(EC_OC_REG_OC_MPG_SIO__M)); + EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M)); else EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M; /* Don't Insert RS Byte */ - if( state->insert_rs_byte ) - { + if (state->insert_rs_byte) { EcOcRegOcModeLop &= - (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M)); + (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M)); EcOcRegOcModeHip &= - (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); + (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); EcOcRegOcModeHip |= EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE; } else { EcOcRegOcModeLop |= - EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; + EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE; EcOcRegOcModeHip &= (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M); EcOcRegOcModeHip |= @@ -1379,7 +1368,7 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) } /* Mode = Parallel */ - if( state->enable_parallel ) + if (state->enable_parallel) EcOcRegOcModeLop &= (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M)); else @@ -1407,114 +1396,114 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) EcOcRegIprInvMpg &= (~(0x0800)); /* EcOcRegOcModeLop =0x05; */ - CHK_ERROR( Write16(state, EC_OC_REG_IPR_INV_MPG__A, - EcOcRegIprInvMpg, 0)); - CHK_ERROR( Write16(state, EC_OC_REG_OC_MODE_LOP__A, - EcOcRegOcModeLop, 0) ); - CHK_ERROR( Write16(state, EC_OC_REG_OC_MODE_HIP__A, - EcOcRegOcModeHip, 0x0000 ) ); - CHK_ERROR( Write16(state, EC_OC_REG_OC_MPG_SIO__A, - EcOcRegOcMpgSio, 0) ); - } while(0); + CHK_ERROR(Write16(state, EC_OC_REG_IPR_INV_MPG__A, + EcOcRegIprInvMpg, 0)); + CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, + EcOcRegOcModeLop, 0)); + CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_HIP__A, + EcOcRegOcModeHip, 0x0000)); + CHK_ERROR(Write16(state, EC_OC_REG_OC_MPG_SIO__A, + EcOcRegOcMpgSio, 0)); + } while (0); return status; } static int SetDeviceTypeId(struct drxd_state *state) { - int status = 0; - u16 deviceId = 0 ; - - do { - CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); - /* TODO: why twice? */ - CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); - printk( "drxd: deviceId = %04x\n",deviceId); - - state->type_A = 0; - state->PGA = 0; - state->diversity = 0; - if (deviceId == 0) { /* on A2 only 3975 available */ - state->type_A = 1; - printk("DRX3975D-A2\n"); - } else { - deviceId >>= 12; - printk("DRX397%dD-B1\n",deviceId); - switch(deviceId) { - case 4: - state->diversity = 1; - case 3: - case 7: - state->PGA = 1; - break; - case 6: - state->diversity = 1; - case 5: - case 8: - break; - default: - status = -1; - break; - } - } - } while(0); - - if (status<0) - return status; - - /* Init Table selection */ - state->m_InitAtomicRead = DRXD_InitAtomicRead; - state->m_InitSC = DRXD_InitSC; - state->m_ResetECRAM = DRXD_ResetECRAM; - if (state->type_A) { - state->m_ResetCEFR = DRXD_ResetCEFR; - state->m_InitFE_1 = DRXD_InitFEA2_1; - state->m_InitFE_2 = DRXD_InitFEA2_2; - state->m_InitCP = DRXD_InitCPA2; - state->m_InitCE = DRXD_InitCEA2; - state->m_InitEQ = DRXD_InitEQA2; - state->m_InitEC = DRXD_InitECA2; - if (load_firmware(state, DRX_FW_FILENAME_A2)) - return -EIO; - } else { - state->m_ResetCEFR = NULL; - state->m_InitFE_1 = DRXD_InitFEB1_1; - state->m_InitFE_2 = DRXD_InitFEB1_2; - state->m_InitCP = DRXD_InitCPB1; - state->m_InitCE = DRXD_InitCEB1; - state->m_InitEQ = DRXD_InitEQB1; - state->m_InitEC = DRXD_InitECB1; - if (load_firmware(state, DRX_FW_FILENAME_B1)) - return -EIO; - } - if (state->diversity) { - state->m_InitDiversityFront = DRXD_InitDiversityFront; - state->m_InitDiversityEnd = DRXD_InitDiversityEnd; - state->m_DisableDiversity = DRXD_DisableDiversity; - state->m_StartDiversityFront = DRXD_StartDiversityFront; - state->m_StartDiversityEnd = DRXD_StartDiversityEnd; - state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; - state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; - } else { - state->m_InitDiversityFront = NULL; - state->m_InitDiversityEnd = NULL; - state->m_DisableDiversity = NULL; - state->m_StartDiversityFront = NULL; - state->m_StartDiversityEnd = NULL; - state->m_DiversityDelay8MHZ = NULL; - state->m_DiversityDelay6MHZ = NULL; - } - - return status; + int status = 0; + u16 deviceId = 0; + + do { + CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); + /* TODO: why twice? */ + CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); + printk("drxd: deviceId = %04x\n", deviceId); + + state->type_A = 0; + state->PGA = 0; + state->diversity = 0; + if (deviceId == 0) { /* on A2 only 3975 available */ + state->type_A = 1; + printk("DRX3975D-A2\n"); + } else { + deviceId >>= 12; + printk("DRX397%dD-B1\n", deviceId); + switch (deviceId) { + case 4: + state->diversity = 1; + case 3: + case 7: + state->PGA = 1; + break; + case 6: + state->diversity = 1; + case 5: + case 8: + break; + default: + status = -1; + break; + } + } + } while (0); + + if (status < 0) + return status; + + /* Init Table selection */ + state->m_InitAtomicRead = DRXD_InitAtomicRead; + state->m_InitSC = DRXD_InitSC; + state->m_ResetECRAM = DRXD_ResetECRAM; + if (state->type_A) { + state->m_ResetCEFR = DRXD_ResetCEFR; + state->m_InitFE_1 = DRXD_InitFEA2_1; + state->m_InitFE_2 = DRXD_InitFEA2_2; + state->m_InitCP = DRXD_InitCPA2; + state->m_InitCE = DRXD_InitCEA2; + state->m_InitEQ = DRXD_InitEQA2; + state->m_InitEC = DRXD_InitECA2; + if (load_firmware(state, DRX_FW_FILENAME_A2)) + return -EIO; + } else { + state->m_ResetCEFR = NULL; + state->m_InitFE_1 = DRXD_InitFEB1_1; + state->m_InitFE_2 = DRXD_InitFEB1_2; + state->m_InitCP = DRXD_InitCPB1; + state->m_InitCE = DRXD_InitCEB1; + state->m_InitEQ = DRXD_InitEQB1; + state->m_InitEC = DRXD_InitECB1; + if (load_firmware(state, DRX_FW_FILENAME_B1)) + return -EIO; + } + if (state->diversity) { + state->m_InitDiversityFront = DRXD_InitDiversityFront; + state->m_InitDiversityEnd = DRXD_InitDiversityEnd; + state->m_DisableDiversity = DRXD_DisableDiversity; + state->m_StartDiversityFront = DRXD_StartDiversityFront; + state->m_StartDiversityEnd = DRXD_StartDiversityEnd; + state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ; + state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ; + } else { + state->m_InitDiversityFront = NULL; + state->m_InitDiversityEnd = NULL; + state->m_DisableDiversity = NULL; + state->m_StartDiversityFront = NULL; + state->m_StartDiversityEnd = NULL; + state->m_DiversityDelay8MHZ = NULL; + state->m_DiversityDelay6MHZ = NULL; + } + + return status; } static int CorrectSysClockDeviation(struct drxd_state *state) { int status; - s32 incr = 0; - s32 nomincr = 0; - u32 bandwidth=0; - u32 sysClockInHz=0; - u32 sysClockFreq=0; /* in kHz */ + s32 incr = 0; + s32 nomincr = 0; + u32 bandwidth = 0; + u32 sysClockInHz = 0; + u32 sysClockFreq = 0; /* in kHz */ s16 oscClockDeviation; s16 Diff; @@ -1523,79 +1512,75 @@ static int CorrectSysClockDeviation(struct drxd_state *state) /* These accesses should be AtomicReadReg32, but that causes trouble (at least for diversity */ - CHK_ERROR( Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, - ((u32 *)&nomincr),0 )); - CHK_ERROR( Read32(state, FE_IF_REG_INCR0__A, - (u32 *) &incr,0 )); - - if( state->type_A ) { - if( (nomincr - incr < -500) || - (nomincr - incr > 500 ) ) + CHK_ERROR(Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, + ((u32 *) & nomincr), 0)); + CHK_ERROR(Read32(state, FE_IF_REG_INCR0__A, (u32 *) & incr, 0)); + + if (state->type_A) { + if ((nomincr - incr < -500) || (nomincr - incr > 500)) break; } else { - if( (nomincr - incr < -2000 ) || - (nomincr - incr > 2000 ) ) + if ((nomincr - incr < -2000) || (nomincr - incr > 2000)) break; } - switch( state->param.u.ofdm.bandwidth ) - { - case BANDWIDTH_8_MHZ : + switch (state->param.u.ofdm.bandwidth) { + case BANDWIDTH_8_MHZ: bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ; break; - case BANDWIDTH_7_MHZ : + case BANDWIDTH_7_MHZ: bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; break; - case BANDWIDTH_6_MHZ : + case BANDWIDTH_6_MHZ: bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; break; - default : + default: return -1; break; } /* Compute new sysclock value sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */ - incr += (1<<23); - sysClockInHz = MulDiv32(incr,bandwidth,1<<21); - sysClockFreq= (u32)(sysClockInHz/1000); + incr += (1 << 23); + sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21); + sysClockFreq = (u32) (sysClockInHz / 1000); /* rounding */ - if ( ( sysClockInHz%1000 ) > 500 ) - { + if ((sysClockInHz % 1000) > 500) { sysClockFreq++; } /* Compute clock deviation in ppm */ - oscClockDeviation = (u16) ( - (((s32)(sysClockFreq) - - (s32)(state->expected_sys_clock_freq))* - 1000000L)/(s32)(state->expected_sys_clock_freq) ); + oscClockDeviation = (u16) ((((s32) (sysClockFreq) - + (s32) + (state->expected_sys_clock_freq)) * + 1000000L) / + (s32) + (state->expected_sys_clock_freq)); Diff = oscClockDeviation - state->osc_clock_deviation; - /*printk("sysclockdiff=%d\n", Diff);*/ - if( Diff >= -200 && Diff <= 200 ) { + /*printk("sysclockdiff=%d\n", Diff); */ + if (Diff >= -200 && Diff <= 200) { state->sys_clock_freq = (u16) sysClockFreq; - if( oscClockDeviation != - state->osc_clock_deviation ) { + if (oscClockDeviation != state->osc_clock_deviation) { if (state->config.osc_deviation) { - state->config.osc_deviation( - state->priv, - oscClockDeviation, 1); - state->osc_clock_deviation= - oscClockDeviation; + state->config.osc_deviation(state->priv, + oscClockDeviation, + 1); + state->osc_clock_deviation = + oscClockDeviation; } } /* switch OFF SRMM scan in SC */ - CHK_ERROR( Write16( state, - SC_RA_RAM_SAMPLE_RATE_COUNT__A, - DRXD_OSCDEV_DONT_SCAN,0)); + CHK_ERROR(Write16(state, + SC_RA_RAM_SAMPLE_RATE_COUNT__A, + DRXD_OSCDEV_DONT_SCAN, 0)); /* overrule FE_IF internal value for proper re-locking */ - CHK_ERROR( Write16( state, SC_RA_RAM_IF_SAVE__AX, - state->current_fe_if_incr, 0)); + CHK_ERROR(Write16(state, SC_RA_RAM_IF_SAVE__AX, + state->current_fe_if_incr, 0)); state->cscd_state = CSCD_SAVED; } - } while(0); + } while (0); return (status); } @@ -1604,60 +1589,58 @@ static int DRX_Stop(struct drxd_state *state) { int status; - if( state->drxd_state != DRXD_STARTED ) + if (state->drxd_state != DRXD_STARTED) return 0; do { - if (state->cscd_state != CSCD_SAVED ) { + if (state->cscd_state != CSCD_SAVED) { u32 lock; - CHK_ERROR( DRX_GetLockStatus(state, &lock)); + CHK_ERROR(DRX_GetLockStatus(state, &lock)); } CHK_ERROR(StopOC(state)); state->drxd_state = DRXD_STOPPED; - CHK_ERROR( ConfigureMPEGOutput(state, 0) ); + CHK_ERROR(ConfigureMPEGOutput(state, 0)); - if(state->type_A ) { + if (state->type_A) { /* Stop relevant processors off the device */ - CHK_ERROR( Write16(state, EC_OD_REG_COMM_EXEC__A, - 0x0000, 0x0000)); + CHK_ERROR(Write16(state, EC_OD_REG_COMM_EXEC__A, + 0x0000, 0x0000)); - CHK_ERROR( Write16(state, SC_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0 )); - CHK_ERROR( Write16(state, LC_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0 )); + CHK_ERROR(Write16(state, SC_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0)); + CHK_ERROR(Write16(state, LC_COMM_EXEC__A, + SC_COMM_EXEC_CTL_STOP, 0)); } else { /* Stop all processors except HI & CC & FE */ CHK_ERROR(Write16(state, B_SC_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0 )); + SC_COMM_EXEC_CTL_STOP, 0)); CHK_ERROR(Write16(state, B_LC_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0 )); + SC_COMM_EXEC_CTL_STOP, 0)); CHK_ERROR(Write16(state, B_FT_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0 )); + SC_COMM_EXEC_CTL_STOP, 0)); CHK_ERROR(Write16(state, B_CP_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0 )); + SC_COMM_EXEC_CTL_STOP, 0)); CHK_ERROR(Write16(state, B_CE_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0 )); + SC_COMM_EXEC_CTL_STOP, 0)); CHK_ERROR(Write16(state, B_EQ_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0 )); + SC_COMM_EXEC_CTL_STOP, 0)); CHK_ERROR(Write16(state, - EC_OD_REG_COMM_EXEC__A, - 0x0000, 0 )); + EC_OD_REG_COMM_EXEC__A, 0x0000, 0)); } - } while(0); + } while (0); return status; } - int SetOperationMode(struct drxd_state *state, int oMode) { int status; @@ -1678,15 +1661,12 @@ int SetOperationMode(struct drxd_state *state, int oMode) break; } - switch(oMode) - { + switch (oMode) { case OM_DVBT_Diversity_Front: - status = WriteTable(state, - state->m_InitDiversityFront); + status = WriteTable(state, state->m_InitDiversityFront); break; case OM_DVBT_Diversity_End: - status = WriteTable(state, - state->m_InitDiversityEnd); + status = WriteTable(state, state->m_InitDiversityEnd); break; case OM_Default: /* We need to check how to @@ -1695,58 +1675,52 @@ int SetOperationMode(struct drxd_state *state, int oMode) status = WriteTable(state, state->m_DisableDiversity); break; } - } while(0); + } while (0); if (!status) state->operation_mode = oMode; return status; } - - static int StartDiversity(struct drxd_state *state) { - int status=0; + int status = 0; u16 rcControl; do { if (state->operation_mode == OM_DVBT_Diversity_Front) { CHK_ERROR(WriteTable(state, state->m_StartDiversityFront)); - } else if( state->operation_mode == OM_DVBT_Diversity_End ) { + } else if (state->operation_mode == OM_DVBT_Diversity_End) { CHK_ERROR(WriteTable(state, state->m_StartDiversityEnd)); - if( state->param.u.ofdm.bandwidth == - BANDWIDTH_8_MHZ ) { - CHK_ERROR( - WriteTable(state, - state-> - m_DiversityDelay8MHZ)); + if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { + CHK_ERROR(WriteTable(state, + state-> + m_DiversityDelay8MHZ)); } else { - CHK_ERROR( - WriteTable(state, - state-> - m_DiversityDelay6MHZ)); + CHK_ERROR(WriteTable(state, + state-> + m_DiversityDelay6MHZ)); } CHK_ERROR(Read16(state, B_EQ_REG_RC_SEL_CAR__A, - &rcControl,0)); + &rcControl, 0)); rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M); rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON | - /* combining enabled */ - B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | - B_EQ_REG_RC_SEL_CAR_PASS_A_CC | - B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC; + /* combining enabled */ + B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | + B_EQ_REG_RC_SEL_CAR_PASS_A_CC | + B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC; CHK_ERROR(Write16(state, B_EQ_REG_RC_SEL_CAR__A, - rcControl,0)); + rcControl, 0)); } - } while(0); + } while (0); return status; } - static int SetFrequencyShift(struct drxd_state *state, u32 offsetFreq, int channelMirrored) { @@ -1763,60 +1737,55 @@ static int SetFrequencyShift(struct drxd_state *state, */ /* Compute register value, unsigned computation */ - state->fe_fs_add_incr = MulDiv32( state->intermediate_freq + + state->fe_fs_add_incr = MulDiv32(state->intermediate_freq + offsetFreq, - 1<<28, state->sys_clock_freq); + 1 << 28, state->sys_clock_freq); /* Remove integer part */ state->fe_fs_add_incr &= 0x0FFFFFFFL; - if (negativeShift) - { - state->fe_fs_add_incr = ((1<<28) - state->fe_fs_add_incr); + if (negativeShift) { + state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); } /* Save the frequency shift without tunerOffset compensation for CtrlGetChannel. */ - state->org_fe_fs_add_incr = MulDiv32( state->intermediate_freq, - 1<<28, state->sys_clock_freq); + state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq, + 1 << 28, state->sys_clock_freq); /* Remove integer part */ state->org_fe_fs_add_incr &= 0x0FFFFFFFL; if (negativeShift) - state->org_fe_fs_add_incr = ((1L<<28) - + state->org_fe_fs_add_incr = ((1L << 28) - state->org_fe_fs_add_incr); return Write32(state, FE_FS_REG_ADD_INC_LOP__A, state->fe_fs_add_incr, 0); } -static int SetCfgNoiseCalibration (struct drxd_state *state, - struct SNoiseCal* noiseCal ) +static int SetCfgNoiseCalibration(struct drxd_state *state, + struct SNoiseCal *noiseCal) { u16 beOptEna; - int status=0; + int status = 0; do { - CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A, - &beOptEna, 0)); - if (noiseCal->cpOpt) - { + CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0)); + if (noiseCal->cpOpt) { beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); } else { beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); CHK_ERROR(Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0)); } - CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A, - beOptEna, 0)); + CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0)); - if( !state->type_A ) - { - CHK_ERROR(Write16( state, - B_SC_RA_RAM_CO_TD_CAL_2K__A, - noiseCal->tdCal2k,0)); - CHK_ERROR(Write16( state, - B_SC_RA_RAM_CO_TD_CAL_8K__A, - noiseCal->tdCal8k,0)); + if (!state->type_A) { + CHK_ERROR(Write16(state, + B_SC_RA_RAM_CO_TD_CAL_2K__A, + noiseCal->tdCal2k, 0)); + CHK_ERROR(Write16(state, + B_SC_RA_RAM_CO_TD_CAL_8K__A, + noiseCal->tdCal8k, 0)); } - } while(0); + } while (0); return status; } @@ -1826,84 +1795,83 @@ static int DRX_Start(struct drxd_state *state, s32 off) struct dvb_ofdm_parameters *p = &state->param.u.ofdm; int status; - u16 transmissionParams = 0; - u16 operationMode = 0; - u16 qpskTdTpsPwr = 0; - u16 qam16TdTpsPwr = 0; - u16 qam64TdTpsPwr = 0; - u32 feIfIncr = 0; - u32 bandwidth = 0; + u16 transmissionParams = 0; + u16 operationMode = 0; + u16 qpskTdTpsPwr = 0; + u16 qam16TdTpsPwr = 0; + u16 qam64TdTpsPwr = 0; + u32 feIfIncr = 0; + u32 bandwidth = 0; int mirrorFreqSpect; - u16 qpskSnCeGain = 0; - u16 qam16SnCeGain = 0; - u16 qam64SnCeGain = 0; - u16 qpskIsGainMan = 0; - u16 qam16IsGainMan = 0; - u16 qam64IsGainMan = 0; - u16 qpskIsGainExp = 0; - u16 qam16IsGainExp = 0; - u16 qam64IsGainExp = 0; - u16 bandwidthParam = 0; - - if (off<0) - off=(off-500)/1000; + u16 qpskSnCeGain = 0; + u16 qam16SnCeGain = 0; + u16 qam64SnCeGain = 0; + u16 qpskIsGainMan = 0; + u16 qam16IsGainMan = 0; + u16 qam64IsGainMan = 0; + u16 qpskIsGainExp = 0; + u16 qam16IsGainExp = 0; + u16 qam64IsGainExp = 0; + u16 bandwidthParam = 0; + + if (off < 0) + off = (off - 500) / 1000; else - off=(off+500)/1000; + off = (off + 500) / 1000; do { if (state->drxd_state != DRXD_STOPPED) return -1; - CHK_ERROR( ResetECOD(state) ); + CHK_ERROR(ResetECOD(state)); if (state->type_A) { - CHK_ERROR( InitSC(state) ); + CHK_ERROR(InitSC(state)); } else { - CHK_ERROR( InitFT(state) ); - CHK_ERROR( InitCP(state) ); - CHK_ERROR( InitCE(state) ); - CHK_ERROR( InitEQ(state) ); - CHK_ERROR( InitSC(state) ); + CHK_ERROR(InitFT(state)); + CHK_ERROR(InitCP(state)); + CHK_ERROR(InitCE(state)); + CHK_ERROR(InitEQ(state)); + CHK_ERROR(InitSC(state)); } /* Restore current IF & RF AGC settings */ - CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg )); - CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg )); + CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg)); + CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg)); - mirrorFreqSpect=( state->param.inversion==INVERSION_ON); + mirrorFreqSpect = (state->param.inversion == INVERSION_ON); switch (p->transmission_mode) { - default: /* Not set, detect it automatically */ + default: /* Not set, detect it automatically */ operationMode |= SC_RA_RAM_OP_AUTO_MODE__M; /* fall through , try first guess DRX_FFTMODE_8K */ - case TRANSMISSION_MODE_8K : + case TRANSMISSION_MODE_8K: transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K; if (state->type_A) { - CHK_ERROR( Write16(state, - EC_SB_REG_TR_MODE__A, - EC_SB_REG_TR_MODE_8K, - 0x0000 )); - qpskSnCeGain = 99; + CHK_ERROR(Write16(state, + EC_SB_REG_TR_MODE__A, + EC_SB_REG_TR_MODE_8K, + 0x0000)); + qpskSnCeGain = 99; qam16SnCeGain = 83; qam64SnCeGain = 67; } break; - case TRANSMISSION_MODE_2K : + case TRANSMISSION_MODE_2K: transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K; if (state->type_A) { - CHK_ERROR( Write16(state, - EC_SB_REG_TR_MODE__A, - EC_SB_REG_TR_MODE_2K, - 0x0000 )); - qpskSnCeGain = 97; + CHK_ERROR(Write16(state, + EC_SB_REG_TR_MODE__A, + EC_SB_REG_TR_MODE_2K, + 0x0000)); + qpskSnCeGain = 97; qam16SnCeGain = 71; qam64SnCeGain = 65; } break; } - switch( p->guard_interval ) - { + switch (p->guard_interval) { case GUARD_INTERVAL_1_4: transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; break; @@ -1916,95 +1884,94 @@ static int DRX_Start(struct drxd_state *state, s32 off) case GUARD_INTERVAL_1_32: transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32; break; - default: /* Not set, detect it automatically */ + default: /* Not set, detect it automatically */ operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M; /* try first guess 1/4 */ transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4; break; } - switch( p->hierarchy_information ) - { + switch (p->hierarchy_information) { case HIERARCHY_1: transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1; if (state->type_A) { - CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, - 0x0001, 0x0000 ) ); - CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, - 0x0001, 0x0000 ) ); + CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, + 0x0001, 0x0000)); + CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, + 0x0001, 0x0000)); - qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; + qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1; qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1; - qpskIsGainMan = - SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; + qpskIsGainMan = + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; qam16IsGainMan = - SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; + SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; qam64IsGainMan = - SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; + SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; - qpskIsGainExp = - SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; + qpskIsGainExp = + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; qam16IsGainExp = - SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; + SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; qam64IsGainExp = - SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; + SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; } break; case HIERARCHY_2: transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2; if (state->type_A) { - CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, - 0x0002, 0x0000 ) ); - CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, - 0x0002, 0x0000 ) ); + CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, + 0x0002, 0x0000)); + CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, + 0x0002, 0x0000)); - qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; + qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2; qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2; qpskIsGainMan = - SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; qam16IsGainMan = - SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE; + SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE; qam64IsGainMan = - SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE; + SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE; - qpskIsGainExp = - SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; + qpskIsGainExp = + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; qam16IsGainExp = - SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE; + SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE; qam64IsGainExp = - SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE; + SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE; } break; case HIERARCHY_4: transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4; if (state->type_A) { - CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, - 0x0003, 0x0000 )); - CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, - 0x0003, 0x0000 ) ); + CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, + 0x0003, 0x0000)); + CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, + 0x0003, 0x0000)); - qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; + qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4; qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4; - qpskIsGainMan = - SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; + qpskIsGainMan = + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE; qam16IsGainMan = - SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE; + SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE; qam64IsGainMan = - SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE; + SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE; - qpskIsGainExp = - SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; + qpskIsGainExp = + SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE; qam16IsGainExp = - SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE; + SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE; qam64IsGainExp = - SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE; + SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE; } break; case HIERARCHY_AUTO: @@ -2013,34 +1980,34 @@ static int DRX_Start(struct drxd_state *state, s32 off) operationMode |= SC_RA_RAM_OP_AUTO_HIER__M; transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO; if (state->type_A) { - CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A, - 0x0000, 0x0000 ) ); - CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A, - 0x0000, 0x0000 ) ); + CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, + 0x0000, 0x0000)); + CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, + 0x0000, 0x0000)); - qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK; + qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK; qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN; qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN; - qpskIsGainMan = - SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE; + qpskIsGainMan = + SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE; qam16IsGainMan = - SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; + SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE; qam64IsGainMan = - SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; + SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE; - qpskIsGainExp = - SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE; + qpskIsGainExp = + SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE; qam16IsGainExp = - SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; + SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE; qam64IsGainExp = - SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; + SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE; } break; } - CHK_ERROR( status ); + CHK_ERROR(status); - switch( p->constellation ) { + switch (p->constellation) { default: operationMode |= SC_RA_RAM_OP_AUTO_CONST__M; /* fall through , try first guess @@ -2049,60 +2016,60 @@ static int DRX_Start(struct drxd_state *state, s32 off) transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64; if (state->type_A) { CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, - 0x0002, 0x0000 ) ); + 0x0002, 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, - 0x0000) ); + 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_SCALE_MSB__A, - 0x0020, 0x0000 ) ); + 0x0020, 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_SCALE_BIT2__A, - 0x0008, 0x0000 ) ); + 0x0008, 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_SCALE_LSB__A, - 0x0002, 0x0000 ) ); + 0x0002, 0x0000)); CHK_ERROR(Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, - qam64TdTpsPwr, 0x0000 ) ); - CHK_ERROR( Write16(state,EQ_REG_SN_CEGAIN__A, - qam64SnCeGain, 0x0000 )); - CHK_ERROR( Write16(state,EQ_REG_IS_GAIN_MAN__A, - qam64IsGainMan, 0x0000 )); - CHK_ERROR( Write16(state,EQ_REG_IS_GAIN_EXP__A, - qam64IsGainExp, 0x0000 )); + qam64TdTpsPwr, 0x0000)); + CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A, + qam64SnCeGain, 0x0000)); + CHK_ERROR(Write16(state, EQ_REG_IS_GAIN_MAN__A, + qam64IsGainMan, 0x0000)); + CHK_ERROR(Write16(state, EQ_REG_IS_GAIN_EXP__A, + qam64IsGainExp, 0x0000)); } break; - case QPSK : + case QPSK: transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK; if (state->type_A) { CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, - 0x0000, 0x0000 ) ); + 0x0000, 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, - 0x0000) ); + 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_SCALE_MSB__A, - 0x0010, 0x0000 ) ); + 0x0010, 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_SCALE_BIT2__A, - 0x0000, 0x0000 ) ); + 0x0000, 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_SCALE_LSB__A, - 0x0000, 0x0000 ) ); + 0x0000, 0x0000)); CHK_ERROR(Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, - qpskTdTpsPwr, 0x0000 ) ); - CHK_ERROR( Write16(state, EQ_REG_SN_CEGAIN__A, - qpskSnCeGain, 0x0000 )); - CHK_ERROR( Write16(state, - EQ_REG_IS_GAIN_MAN__A, - qpskIsGainMan, 0x0000 )); - CHK_ERROR( Write16(state, - EQ_REG_IS_GAIN_EXP__A, - qpskIsGainExp, 0x0000 )); + qpskTdTpsPwr, 0x0000)); + CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A, + qpskSnCeGain, 0x0000)); + CHK_ERROR(Write16(state, + EQ_REG_IS_GAIN_MAN__A, + qpskIsGainMan, 0x0000)); + CHK_ERROR(Write16(state, + EQ_REG_IS_GAIN_EXP__A, + qpskIsGainExp, 0x0000)); } break; @@ -2110,104 +2077,103 @@ static int DRX_Start(struct drxd_state *state, s32 off) transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16; if (state->type_A) { CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, - 0x0001, 0x0000 ) ); + 0x0001, 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, - 0x0000) ); + 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_SCALE_MSB__A, - 0x0010, 0x0000 ) ); + 0x0010, 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_SCALE_BIT2__A, - 0x0004, 0x0000 ) ); + 0x0004, 0x0000)); CHK_ERROR(Write16(state, EC_SB_REG_SCALE_LSB__A, - 0x0000, 0x0000 ) ); + 0x0000, 0x0000)); CHK_ERROR(Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, - qam16TdTpsPwr, 0x0000 ) ); - CHK_ERROR( Write16(state, EQ_REG_SN_CEGAIN__A, - qam16SnCeGain, 0x0000 )); - CHK_ERROR( Write16(state, - EQ_REG_IS_GAIN_MAN__A, - qam16IsGainMan, 0x0000 )); - CHK_ERROR( Write16(state, - EQ_REG_IS_GAIN_EXP__A, - qam16IsGainExp, 0x0000 )); + qam16TdTpsPwr, 0x0000)); + CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A, + qam16SnCeGain, 0x0000)); + CHK_ERROR(Write16(state, + EQ_REG_IS_GAIN_MAN__A, + qam16IsGainMan, 0x0000)); + CHK_ERROR(Write16(state, + EQ_REG_IS_GAIN_EXP__A, + qam16IsGainExp, 0x0000)); } break; } - CHK_ERROR( status ); + CHK_ERROR(status); switch (DRX_CHANNEL_HIGH) { default: case DRX_CHANNEL_AUTO: case DRX_CHANNEL_LOW: transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO; - CHK_ERROR( Write16(state, EC_SB_REG_PRIOR__A, - EC_SB_REG_PRIOR_LO, 0x0000 )); + CHK_ERROR(Write16(state, EC_SB_REG_PRIOR__A, + EC_SB_REG_PRIOR_LO, 0x0000)); break; case DRX_CHANNEL_HIGH: transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI; - CHK_ERROR( Write16(state, EC_SB_REG_PRIOR__A, - EC_SB_REG_PRIOR_HI, 0x0000 )); + CHK_ERROR(Write16(state, EC_SB_REG_PRIOR__A, + EC_SB_REG_PRIOR_HI, 0x0000)); break; } - switch( p->code_rate_HP ) - { + switch (p->code_rate_HP) { case FEC_1_2: transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2; if (state->type_A) { - CHK_ERROR( Write16(state, - EC_VD_REG_SET_CODERATE__A, - EC_VD_REG_SET_CODERATE_C1_2, - 0x0000 ) ); + CHK_ERROR(Write16(state, + EC_VD_REG_SET_CODERATE__A, + EC_VD_REG_SET_CODERATE_C1_2, + 0x0000)); } break; default: operationMode |= SC_RA_RAM_OP_AUTO_RATE__M; - case FEC_2_3 : + case FEC_2_3: transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3; if (state->type_A) { - CHK_ERROR( Write16(state, - EC_VD_REG_SET_CODERATE__A, - EC_VD_REG_SET_CODERATE_C2_3, - 0x0000 ) ); + CHK_ERROR(Write16(state, + EC_VD_REG_SET_CODERATE__A, + EC_VD_REG_SET_CODERATE_C2_3, + 0x0000)); } break; - case FEC_3_4 : + case FEC_3_4: transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4; if (state->type_A) { - CHK_ERROR( Write16(state, - EC_VD_REG_SET_CODERATE__A, - EC_VD_REG_SET_CODERATE_C3_4, - 0x0000 ) ); + CHK_ERROR(Write16(state, + EC_VD_REG_SET_CODERATE__A, + EC_VD_REG_SET_CODERATE_C3_4, + 0x0000)); } break; - case FEC_5_6 : + case FEC_5_6: transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6; if (state->type_A) { - CHK_ERROR( Write16(state, - EC_VD_REG_SET_CODERATE__A, - EC_VD_REG_SET_CODERATE_C5_6, - 0x0000 ) ); + CHK_ERROR(Write16(state, + EC_VD_REG_SET_CODERATE__A, + EC_VD_REG_SET_CODERATE_C5_6, + 0x0000)); } break; - case FEC_7_8 : + case FEC_7_8: transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8; if (state->type_A) { - CHK_ERROR( Write16(state, - EC_VD_REG_SET_CODERATE__A, - EC_VD_REG_SET_CODERATE_C7_8, - 0x0000 ) ); + CHK_ERROR(Write16(state, + EC_VD_REG_SET_CODERATE__A, + EC_VD_REG_SET_CODERATE_C7_8, + 0x0000)); } break; } - CHK_ERROR( status ); + CHK_ERROR(status); /* First determine real bandwidth (Hz) */ /* Also set delay for impulse noise cruncher (only A2) */ @@ -2216,8 +2182,7 @@ static int DRX_Start(struct drxd_state *state, s32 off) by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC functions */ - switch( p->bandwidth ) - { + switch (p->bandwidth) { case BANDWIDTH_AUTO: case BANDWIDTH_8_MHZ: /* (64/7)*(8/8)*1000000 */ @@ -2225,27 +2190,27 @@ static int DRX_Start(struct drxd_state *state, s32 off) bandwidthParam = 0; status = Write16(state, - FE_AG_REG_IND_DEL__A , 50 , 0x0000 ); + FE_AG_REG_IND_DEL__A, 50, 0x0000); break; case BANDWIDTH_7_MHZ: /* (64/7)*(7/8)*1000000 */ bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ; - bandwidthParam =0x4807; /*binary:0100 1000 0000 0111 */ + bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */ status = Write16(state, - FE_AG_REG_IND_DEL__A , 59 , 0x0000 ); + FE_AG_REG_IND_DEL__A, 59, 0x0000); break; case BANDWIDTH_6_MHZ: /* (64/7)*(6/8)*1000000 */ bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ; - bandwidthParam =0x0F07; /*binary: 0000 1111 0000 0111*/ + bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */ status = Write16(state, - FE_AG_REG_IND_DEL__A , 71 , 0x0000 ); + FE_AG_REG_IND_DEL__A, 71, 0x0000); break; } - CHK_ERROR( status ); + CHK_ERROR(status); - CHK_ERROR( Write16(state, - SC_RA_RAM_BAND__A, bandwidthParam, 0x0000)); + CHK_ERROR(Write16(state, + SC_RA_RAM_BAND__A, bandwidthParam, 0x0000)); { u16 sc_config; @@ -2254,45 +2219,43 @@ static int DRX_Start(struct drxd_state *state, s32 off) /* enable SLAVE mode in 2k 1/32 to prevent timing change glitches */ - if ( (p->transmission_mode==TRANSMISSION_MODE_2K) && - (p->guard_interval==GUARD_INTERVAL_1_32) ) { + if ((p->transmission_mode == TRANSMISSION_MODE_2K) && + (p->guard_interval == GUARD_INTERVAL_1_32)) { /* enable slave */ sc_config |= SC_RA_RAM_CONFIG_SLAVE__M; } else { /* disable slave */ sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M; } - CHK_ERROR( Write16(state, - SC_RA_RAM_CONFIG__A, sc_config,0 )); + CHK_ERROR(Write16(state, + SC_RA_RAM_CONFIG__A, sc_config, 0)); } - CHK_ERROR( SetCfgNoiseCalibration(state, &state->noise_cal)); + CHK_ERROR(SetCfgNoiseCalibration(state, &state->noise_cal)); - if (state->cscd_state == CSCD_INIT ) - { + if (state->cscd_state == CSCD_INIT) { /* switch on SRMM scan in SC */ - CHK_ERROR( Write16(state, - SC_RA_RAM_SAMPLE_RATE_COUNT__A, - DRXD_OSCDEV_DO_SCAN, 0x0000 )); + CHK_ERROR(Write16(state, + SC_RA_RAM_SAMPLE_RATE_COUNT__A, + DRXD_OSCDEV_DO_SCAN, 0x0000)); /* CHK_ERROR( Write16( SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP , 0x0000 ));*/ state->cscd_state = CSCD_SET; } - /* Now compute FE_IF_REG_INCR */ /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) => - ((SysFreq / BandWidth) * (2^21) ) - (2^23)*/ - feIfIncr = MulDiv32(state->sys_clock_freq*1000, - ( 1ULL<< 21 ), bandwidth) - (1<<23) ; - CHK_ERROR( Write16(state, - FE_IF_REG_INCR0__A, - (u16)(feIfIncr & FE_IF_REG_INCR0__M ), - 0x0000) ); - CHK_ERROR( Write16(state, - FE_IF_REG_INCR1__A, - (u16)((feIfIncr >> FE_IF_REG_INCR0__W) & - FE_IF_REG_INCR1__M ), 0x0000) ); + ((SysFreq / BandWidth) * (2^21) ) - (2^23) */ + feIfIncr = MulDiv32(state->sys_clock_freq * 1000, + (1ULL << 21), bandwidth) - (1 << 23); + CHK_ERROR(Write16(state, + FE_IF_REG_INCR0__A, + (u16) (feIfIncr & FE_IF_REG_INCR0__M), + 0x0000)); + CHK_ERROR(Write16(state, + FE_IF_REG_INCR1__A, + (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & + FE_IF_REG_INCR1__M), 0x0000)); /* Bandwidth setting done */ /* Mirror & frequency offset */ @@ -2301,34 +2264,34 @@ static int DRX_Start(struct drxd_state *state, s32 off) /* Start SC, write channel settings to SC */ /* Enable SC after setting all other parameters */ - CHK_ERROR( Write16(state, SC_COMM_STATE__A, 0, 0x0000)); - CHK_ERROR( Write16(state, SC_COMM_EXEC__A, 1, 0x0000)); + CHK_ERROR(Write16(state, SC_COMM_STATE__A, 0, 0x0000)); + CHK_ERROR(Write16(state, SC_COMM_EXEC__A, 1, 0x0000)); /* Write SC parameter registers, operation mode */ #if 1 - operationMode =( SC_RA_RAM_OP_AUTO_MODE__M | - SC_RA_RAM_OP_AUTO_GUARD__M | - SC_RA_RAM_OP_AUTO_CONST__M | - SC_RA_RAM_OP_AUTO_HIER__M | - SC_RA_RAM_OP_AUTO_RATE__M ); + operationMode = (SC_RA_RAM_OP_AUTO_MODE__M | + SC_RA_RAM_OP_AUTO_GUARD__M | + SC_RA_RAM_OP_AUTO_CONST__M | + SC_RA_RAM_OP_AUTO_HIER__M | + SC_RA_RAM_OP_AUTO_RATE__M); #endif - CHK_ERROR( SC_SetPrefParamCommand(state, 0x0000, - transmissionParams, - operationMode) ); + CHK_ERROR(SC_SetPrefParamCommand(state, 0x0000, + transmissionParams, + operationMode)); /* Start correct processes to get in lock */ - CHK_ERROR( SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, - SC_RA_RAM_SW_EVENT_RUN_NMASK__M, - SC_RA_RAM_LOCKTRACK_MIN) ); + CHK_ERROR(SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, + SC_RA_RAM_SW_EVENT_RUN_NMASK__M, + SC_RA_RAM_LOCKTRACK_MIN)); - CHK_ERROR( StartOC(state) ); + CHK_ERROR(StartOC(state)); - if( state->operation_mode != OM_Default ) { + if (state->operation_mode != OM_Default) { CHK_ERROR(StartDiversity(state)); } state->drxd_state = DRXD_STARTED; - } while(0); + } while (0); return status; } @@ -2336,140 +2299,136 @@ static int DRX_Start(struct drxd_state *state, s32 off) static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) { u32 ulRfAgcOutputLevel = 0xffffffff; - u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */ - u32 ulRfAgcMinLevel = 0; /* Currently unused */ - u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */ - u32 ulRfAgcSpeed = 0; /* Currently unused */ - u32 ulRfAgcMode = 0;/*2; Off */ - u32 ulRfAgcR1 = 820; + u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */ + u32 ulRfAgcMinLevel = 0; /* Currently unused */ + u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */ + u32 ulRfAgcSpeed = 0; /* Currently unused */ + u32 ulRfAgcMode = 0; /*2; Off */ + u32 ulRfAgcR1 = 820; u32 ulRfAgcR2 = 2200; - u32 ulRfAgcR3 = 150; - u32 ulIfAgcMode = 0; /* Auto */ + u32 ulRfAgcR3 = 150; + u32 ulIfAgcMode = 0; /* Auto */ u32 ulIfAgcOutputLevel = 0xffffffff; u32 ulIfAgcSettleLevel = 0xffffffff; u32 ulIfAgcMinLevel = 0xffffffff; u32 ulIfAgcMaxLevel = 0xffffffff; u32 ulIfAgcSpeed = 0xffffffff; - u32 ulIfAgcR1 = 820; + u32 ulIfAgcR1 = 820; u32 ulIfAgcR2 = 2200; - u32 ulIfAgcR3 = 150; + u32 ulIfAgcR3 = 150; u32 ulClock = state->config.clock; u32 ulSerialMode = 0; - u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */ + u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */ u32 ulHiI2cDelay = HI_I2C_DELAY; u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY; u32 ulHiI2cPatch = 0; - u32 ulEnvironment = APPENV_PORTABLE; + u32 ulEnvironment = APPENV_PORTABLE; u32 ulEnvironmentDiversity = APPENV_MOBILE; u32 ulIFFilter = IFFILTER_SAW; - state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; + state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; state->if_agc_cfg.outputLevel = 0; state->if_agc_cfg.settleLevel = 140; state->if_agc_cfg.minOutputLevel = 0; state->if_agc_cfg.maxOutputLevel = 1023; state->if_agc_cfg.speed = 904; - if( ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX ) - { - state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; - state->if_agc_cfg.outputLevel = (u16)(ulIfAgcOutputLevel); + if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) { + state->if_agc_cfg.ctrlMode = AGC_CTRL_USER; + state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel); } - if( ulIfAgcMode == 0 && + if (ulIfAgcMode == 0 && ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX && ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX && ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX && - ulIfAgcSpeed <= DRXD_FE_CTRL_MAX - ) - { - state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; - state->if_agc_cfg.settleLevel = (u16)(ulIfAgcSettleLevel); - state->if_agc_cfg.minOutputLevel = (u16)(ulIfAgcMinLevel); - state->if_agc_cfg.maxOutputLevel = (u16)(ulIfAgcMaxLevel); - state->if_agc_cfg.speed = (u16)(ulIfAgcSpeed); + ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) { + state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO; + state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel); + state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel); + state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel); + state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed); } - state->if_agc_cfg.R1 = (u16)(ulIfAgcR1); - state->if_agc_cfg.R2 = (u16)(ulIfAgcR2); - state->if_agc_cfg.R3 = (u16)(ulIfAgcR3); + state->if_agc_cfg.R1 = (u16) (ulIfAgcR1); + state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); + state->if_agc_cfg.R3 = (u16) (ulIfAgcR3); - state->rf_agc_cfg.R1 = (u16)(ulRfAgcR1); - state->rf_agc_cfg.R2 = (u16)(ulRfAgcR2); - state->rf_agc_cfg.R3 = (u16)(ulRfAgcR3); + state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1); + state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); + state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3); - state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; + state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; /* rest of the RFAgcCfg structure currently unused */ - if (ulRfAgcMode==1 && ulRfAgcOutputLevel<=DRXD_FE_CTRL_MAX) { - state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; - state->rf_agc_cfg.outputLevel = (u16)(ulRfAgcOutputLevel); + if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) { + state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER; + state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel); } - if( ulRfAgcMode == 0 && + if (ulRfAgcMode == 0 && ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX && ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX && ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX && - ulRfAgcSpeed <= DRXD_FE_CTRL_MAX - ) - { - state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; - state->rf_agc_cfg.settleLevel = (u16)(ulRfAgcSettleLevel); - state->rf_agc_cfg.minOutputLevel = (u16)(ulRfAgcMinLevel); - state->rf_agc_cfg.maxOutputLevel = (u16)(ulRfAgcMaxLevel); - state->rf_agc_cfg.speed = (u16)(ulRfAgcSpeed); + ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) { + state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO; + state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel); + state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel); + state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel); + state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); } - if( ulRfAgcMode == 2 ) - { - state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; + if (ulRfAgcMode == 2) { + state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; } if (ulEnvironment <= 2) - state->app_env_default = (enum app_env) - (ulEnvironment); + state->app_env_default = (enum app_env) + (ulEnvironment); if (ulEnvironmentDiversity <= 2) state->app_env_diversity = (enum app_env) - (ulEnvironmentDiversity); + (ulEnvironmentDiversity); - if( ulIFFilter == IFFILTER_DISCRETE ) - { + if (ulIFFilter == IFFILTER_DISCRETE) { /* discrete filter */ - state->noise_cal.cpOpt = 0; - state->noise_cal.cpNexpOfs = 40; - state->noise_cal.tdCal2k = -40; - state->noise_cal.tdCal8k = -24; + state->noise_cal.cpOpt = 0; + state->noise_cal.cpNexpOfs = 40; + state->noise_cal.tdCal2k = -40; + state->noise_cal.tdCal8k = -24; } else { /* SAW filter */ - state->noise_cal.cpOpt = 1; - state->noise_cal.cpNexpOfs = 0; - state->noise_cal.tdCal2k = -21; - state->noise_cal.tdCal8k = -24; + state->noise_cal.cpOpt = 1; + state->noise_cal.cpNexpOfs = 0; + state->noise_cal.tdCal2k = -21; + state->noise_cal.tdCal8k = -24; } - state->m_EcOcRegOcModeLop = (u16)(ulEcOcRegOcModeLop); - - state->chip_adr = (state->config.demod_address<<1)|1; - switch( ulHiI2cPatch ) - { - case 1 : state->m_HiI2cPatch = DRXD_HiI2cPatch_1; break; - case 3 : state->m_HiI2cPatch = DRXD_HiI2cPatch_3; break; + state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop); + + state->chip_adr = (state->config.demod_address << 1) | 1; + switch (ulHiI2cPatch) { + case 1: + state->m_HiI2cPatch = DRXD_HiI2cPatch_1; + break; + case 3: + state->m_HiI2cPatch = DRXD_HiI2cPatch_3; + break; default: state->m_HiI2cPatch = NULL; } /* modify tuner and clock attributes */ - state->intermediate_freq = (u16)(IntermediateFrequency/1000); + state->intermediate_freq = (u16) (IntermediateFrequency / 1000); /* expected system clock frequency in kHz */ state->expected_sys_clock_freq = 48000; /* real system clock frequency in kHz */ state->sys_clock_freq = 48000; - state->osc_clock_freq = (u16) ulClock; + state->osc_clock_freq = (u16) ulClock; state->osc_clock_deviation = 0; state->cscd_state = CSCD_INIT; state->drxd_state = DRXD_UNINITIALIZED; - state->PGA=0; - state->type_A=0; - state->tuner_mirrors=0; + state->PGA = 0; + state->type_A = 0; + state->tuner_mirrors = 0; /* modify MPEG output attributes */ state->insert_rs_byte = state->config.insert_rs_byte; @@ -2478,12 +2437,12 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) /* Timing div, 250ns/Psys */ /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */ - state->hi_cfg_timing_div = (u16)((state->sys_clock_freq/1000)* - ulHiI2cDelay)/1000 ; + state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) * + ulHiI2cDelay) / 1000; /* Bridge delay, uses oscilator clock */ /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */ - state->hi_cfg_bridge_delay = (u16)((state->osc_clock_freq/1000) * - ulHiI2cBridgeDelay)/1000 ; + state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) * + ulHiI2cBridgeDelay) / 1000; state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */ @@ -2491,9 +2450,9 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) return 0; } -int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) +int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size) { - int status=0; + int status = 0; u32 driverVersion; if (state->init_done) @@ -2504,10 +2463,10 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) do { state->operation_mode = OM_Default; - CHK_ERROR( SetDeviceTypeId(state) ); + CHK_ERROR(SetDeviceTypeId(state)); /* Apply I2c address patch to B1 */ - if( !state->type_A && state->m_HiI2cPatch != NULL ) + if (!state->type_A && state->m_HiI2cPatch != NULL) CHK_ERROR(WriteTable(state, state->m_HiI2cPatch)); if (state->type_A) { @@ -2516,7 +2475,7 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) CHK_ERROR(Write16(state, 0x43012D, 0x047f, 0)); } - CHK_ERROR( HI_ResetCommand(state)); + CHK_ERROR(HI_ResetCommand(state)); CHK_ERROR(StopAllProcessors(state)); CHK_ERROR(InitCC(state)); @@ -2525,29 +2484,27 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) if (state->config.osc_deviation) state->osc_clock_deviation = - state->config.osc_deviation(state->priv, - 0, 0); + state->config.osc_deviation(state->priv, 0, 0); { /* Handle clock deviation */ s32 devB; - s32 devA = (s32)(state->osc_clock_deviation) * - (s32)(state->expected_sys_clock_freq); + s32 devA = (s32) (state->osc_clock_deviation) * + (s32) (state->expected_sys_clock_freq); /* deviation in kHz */ - s32 deviation = ( devA /(1000000L)); + s32 deviation = (devA / (1000000L)); /* rounding, signed */ - if ( devA > 0 ) - devB=(2); + if (devA > 0) + devB = (2); else - devB=(-2); - if ( (devB*(devA%1000000L)>1000000L ) ) - { + devB = (-2); + if ((devB * (devA % 1000000L) > 1000000L)) { /* add +1 or -1 */ - deviation += (devB/2); + deviation += (devB / 2); } - state->sys_clock_freq=(u16)((state-> - expected_sys_clock_freq)+ - deviation); + state->sys_clock_freq = + (u16) ((state->expected_sys_clock_freq) + + deviation); } CHK_ERROR(InitHI(state)); CHK_ERROR(InitAtomicRead(state)); @@ -2565,7 +2522,7 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) if (state->PGA) { state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; - SetCfgPga(state, 0); /* PGA = 0 dB */ + SetCfgPga(state, 0); /* PGA = 0 dB */ } else { state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER; } @@ -2587,39 +2544,37 @@ int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size) CHK_ERROR(Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0)); CHK_ERROR(Write16(state, LC_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0 )); - + SC_COMM_EXEC_CTL_STOP, 0)); - driverVersion = (((VERSION_MAJOR/10) << 4) + - (VERSION_MAJOR%10)) << 24; - driverVersion += (((VERSION_MINOR/10) << 4) + - (VERSION_MINOR%10)) << 16; - driverVersion += ((VERSION_PATCH/1000)<<12) + - ((VERSION_PATCH/100)<<8) + - ((VERSION_PATCH/10 )<< 4) + - (VERSION_PATCH%10 ); + driverVersion = (((VERSION_MAJOR / 10) << 4) + + (VERSION_MAJOR % 10)) << 24; + driverVersion += (((VERSION_MINOR / 10) << 4) + + (VERSION_MINOR % 10)) << 16; + driverVersion += ((VERSION_PATCH / 1000) << 12) + + ((VERSION_PATCH / 100) << 8) + + ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10); CHK_ERROR(Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, - driverVersion,0 )); + driverVersion, 0)); - CHK_ERROR( StopOC(state) ); + CHK_ERROR(StopOC(state)); state->drxd_state = DRXD_STOPPED; - state->init_done=1; - status=0; + state->init_done = 1; + status = 0; } while (0); return status; } -int DRXD_status(struct drxd_state *state, u32 *pLockStatus) +int DRXD_status(struct drxd_state *state, u32 * pLockStatus) { DRX_GetLockStatus(state, pLockStatus); - /*if (*pLockStatus&DRX_LOCK_MPEG)*/ - if (*pLockStatus&DRX_LOCK_FEC) { + /*if (*pLockStatus&DRX_LOCK_MPEG) */ + if (*pLockStatus & DRX_LOCK_FEC) { ConfigureMPEGOutput(state, 1); /* Get status again, in case we have MPEG lock now */ - /*DRX_GetLockStatus(state, pLockStatus);*/ + /*DRX_GetLockStatus(state, pLockStatus); */ } return 0; @@ -2629,61 +2584,59 @@ int DRXD_status(struct drxd_state *state, u32 *pLockStatus) /****************************************************************************/ /****************************************************************************/ -static int drxd_read_signal_strength(struct dvb_frontend *fe, - u16 *strength) +static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength) { struct drxd_state *state = fe->demodulator_priv; u32 value; int res; - res=ReadIFAgc(state, &value); - if (res<0) - *strength=0; + res = ReadIFAgc(state, &value); + if (res < 0) + *strength = 0; else - *strength=0xffff-(value<<4); + *strength = 0xffff - (value << 4); return 0; } - -static int drxd_read_status(struct dvb_frontend *fe, fe_status_t *status) +static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status) { struct drxd_state *state = fe->demodulator_priv; u32 lock; DRXD_status(state, &lock); - *status=0; + *status = 0; /* No MPEG lock in V255 firmware, bug ? */ #if 1 - if (lock&DRX_LOCK_MPEG) - *status|=FE_HAS_LOCK; + if (lock & DRX_LOCK_MPEG) + *status |= FE_HAS_LOCK; #else - if (lock&DRX_LOCK_FEC) - *status|=FE_HAS_LOCK; + if (lock & DRX_LOCK_FEC) + *status |= FE_HAS_LOCK; #endif - if (lock&DRX_LOCK_FEC) - *status|=FE_HAS_VITERBI|FE_HAS_SYNC; - if (lock&DRX_LOCK_DEMOD) - *status|=FE_HAS_CARRIER|FE_HAS_SIGNAL; + if (lock & DRX_LOCK_FEC) + *status |= FE_HAS_VITERBI | FE_HAS_SYNC; + if (lock & DRX_LOCK_DEMOD) + *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; return 0; } static int drxd_init(struct dvb_frontend *fe) { - struct drxd_state *state=fe->demodulator_priv; - int err=0; + struct drxd_state *state = fe->demodulator_priv; + int err = 0; /* if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */ - return DRXD_init(state, 0, 0); + return DRXD_init(state, 0, 0); - err=DRXD_init(state, state->fw->data, state->fw->size); + err = DRXD_init(state, state->fw->data, state->fw->size); release_firmware(state->fw); return err; } int drxd_config_i2c(struct dvb_frontend *fe, int onoff) { - struct drxd_state *state=fe->demodulator_priv; + struct drxd_state *state = fe->demodulator_priv; if (state->config.disable_i2c_gate_ctrl == 1) return 0; @@ -2692,58 +2645,58 @@ int drxd_config_i2c(struct dvb_frontend *fe, int onoff) } static int drxd_get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings *sets) + struct dvb_frontend_tune_settings *sets) { - sets->min_delay_ms=10000; - sets->max_drift=0; - sets->step_size=0; + sets->min_delay_ms = 10000; + sets->max_drift = 0; + sets->step_size = 0; return 0; } -static int drxd_read_ber(struct dvb_frontend *fe, u32 *ber) +static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber) { *ber = 0; return 0; } -static int drxd_read_snr(struct dvb_frontend *fe, u16 *snr) +static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr) { - *snr=0; + *snr = 0; return 0; } -static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) { - *ucblocks=0; + *ucblocks = 0; return 0; } -static int drxd_sleep(struct dvb_frontend* fe) +static int drxd_sleep(struct dvb_frontend *fe) { - struct drxd_state *state=fe->demodulator_priv; + struct drxd_state *state = fe->demodulator_priv; ConfigureMPEGOutput(state, 0); return 0; } static int drxd_get_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *param) + struct dvb_frontend_parameters *param) { return 0; } -static int drxd_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) +static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) { return drxd_config_i2c(fe, enable); } static int drxd_set_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *param) + struct dvb_frontend_parameters *param) { - struct drxd_state *state=fe->demodulator_priv; - s32 off=0; + struct drxd_state *state = fe->demodulator_priv; + s32 off = 0; - state->param=*param; + state->param = *param; DRX_Stop(state); if (fe->ops.tuner_ops.set_params) { @@ -2756,8 +2709,7 @@ static int drxd_set_frontend(struct dvb_frontend *fe, if (state->config.pll_set && state->config.pll_set(state->priv, param, state->config.pll_address, - state->config.demoda_address, - &off)<0) { + state->config.demoda_address, &off) < 0) { printk("Error in pll_set\n"); return -1; } @@ -2767,7 +2719,6 @@ static int drxd_set_frontend(struct dvb_frontend *fe, return DRX_Start(state, off); } - static void drxd_release(struct dvb_frontend *fe) { struct drxd_state *state = fe->demodulator_priv; @@ -2778,22 +2729,20 @@ static void drxd_release(struct dvb_frontend *fe) static struct dvb_frontend_ops drxd_ops = { .info = { - .name = "Micronas DRXD DVB-T", - .type = FE_OFDM, - .frequency_min = 47125000, - .frequency_max = 855250000, - .frequency_stepsize = 166667, - .frequency_tolerance = 0, - .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | - FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | - FE_CAN_FEC_AUTO | - FE_CAN_QAM_16 | FE_CAN_QAM_64 | - FE_CAN_QAM_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | - FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | - FE_CAN_MUTE_TS - }, + .name = "Micronas DRXD DVB-T", + .type = FE_OFDM, + .frequency_min = 47125000, + .frequency_max = 855250000, + .frequency_stepsize = 166667, + .frequency_tolerance = 0, + .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | + FE_CAN_FEC_AUTO | + FE_CAN_QAM_16 | FE_CAN_QAM_64 | + FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | + FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS}, .release = drxd_release, .init = drxd_init, @@ -2817,29 +2766,29 @@ struct dvb_frontend *drxd_attach(const struct drxd_config *config, { struct drxd_state *state = NULL; - state=kmalloc(sizeof(struct drxd_state), GFP_KERNEL); + state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL); if (!state) return NULL; memset(state, 0, sizeof(*state)); memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops)); - state->dev=dev; - state->config=*config; - state->i2c=i2c; - state->priv=priv; + state->dev = dev; + state->config = *config; + state->i2c = i2c; + state->priv = priv; sema_init(&state->mutex, 1); - if (Read16(state, 0, 0, 0)<0) + if (Read16(state, 0, 0, 0) < 0) goto error; #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) - state->frontend.ops=&state->ops; + state->frontend.ops = &state->ops; #else memcpy(&state->frontend.ops, &drxd_ops, sizeof(struct dvb_frontend_ops)); #endif - state->frontend.demodulator_priv=state; + state->frontend.demodulator_priv = state; ConfigureMPEGOutput(state, 0); return &state->frontend; diff --git a/drivers/media/dvb/frontends/drxd_map_firm.h b/drivers/media/dvb/frontends/drxd_map_firm.h index 3523cfee7479..c9fbb459b20f 100644 --- a/drivers/media/dvb/frontends/drxd_map_firm.h +++ b/drivers/media/dvb/frontends/drxd_map_firm.h @@ -24,16 +24,8 @@ #ifndef __DRX3973D_MAP__H__ #define __DRX3973D_MAP__H__ -#ifdef __cplusplus -extern "C" { -#endif - #define HI_SID 0x10 - - - - #define HI_COMM_EXEC__A 0x400000 #define HI_COMM_EXEC__W 3 #define HI_COMM_EXEC__M 0x7 @@ -66,11 +58,6 @@ extern "C" { #define HI_COMM_INT_MSK__W 16 #define HI_COMM_INT_MSK__M 0xFFFF - - - - - #define HI_CT_REG_COMM_EXEC__A 0x410000 #define HI_CT_REG_COMM_EXEC__W 3 #define HI_CT_REG_COMM_EXEC__M 0x7 @@ -82,7 +69,6 @@ extern "C" { #define HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 #define HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 - #define HI_CT_REG_COMM_STATE__A 0x410001 #define HI_CT_REG_COMM_STATE__W 10 #define HI_CT_REG_COMM_STATE__M 0x3FF @@ -96,7 +82,6 @@ extern "C" { #define HI_CT_REG_COMM_SERVICE1_HI__W 1 #define HI_CT_REG_COMM_SERVICE1_HI__M 0x1 - #define HI_CT_REG_COMM_INT_STA__A 0x410007 #define HI_CT_REG_COMM_INT_STA__W 1 #define HI_CT_REG_COMM_INT_STA__M 0x1 @@ -104,7 +89,6 @@ extern "C" { #define HI_CT_REG_COMM_INT_STA_REQUEST__W 1 #define HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - #define HI_CT_REG_COMM_INT_MSK__A 0x410008 #define HI_CT_REG_COMM_INT_MSK__W 1 #define HI_CT_REG_COMM_INT_MSK__M 0x1 @@ -112,9 +96,6 @@ extern "C" { #define HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 #define HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - - - #define HI_CT_REG_CTL_STK__AX 0x410010 #define HI_CT_REG_CTL_STK__XSZ 4 #define HI_CT_REG_CTL_STK__W 10 @@ -128,18 +109,12 @@ extern "C" { #define HI_CT_REG_CTL_BPT__W 10 #define HI_CT_REG_CTL_BPT__M 0x3FF - - - - - #define HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 #define HI_RA_RAM_SLV0_FLG_SMM__W 1 #define HI_RA_RAM_SLV0_FLG_SMM__M 0x1 #define HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 #define HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 - #define HI_RA_RAM_SLV0_DEV_ID__A 0x420011 #define HI_RA_RAM_SLV0_DEV_ID__W 7 #define HI_RA_RAM_SLV0_DEV_ID__M 0x7F @@ -150,7 +125,6 @@ extern "C" { #define HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 #define HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 - #define HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 #define HI_RA_RAM_SLV0_FLG_ACC__W 3 #define HI_RA_RAM_SLV0_FLG_ACC__M 0x7 @@ -165,14 +139,12 @@ extern "C" { #define HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 #define HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 - #define HI_RA_RAM_SLV0_STATE__A 0x420014 #define HI_RA_RAM_SLV0_STATE__W 1 #define HI_RA_RAM_SLV0_STATE__M 0x1 #define HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 #define HI_RA_RAM_SLV0_STATE_DATA 0x1 - #define HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 #define HI_RA_RAM_SLV0_BLK_BNK__W 12 #define HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF @@ -183,7 +155,6 @@ extern "C" { #define HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 #define HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 - #define HI_RA_RAM_SLV0_ADDR__A 0x420016 #define HI_RA_RAM_SLV0_ADDR__W 16 #define HI_RA_RAM_SLV0_ADDR__M 0xFFFF @@ -196,16 +167,12 @@ extern "C" { #define HI_RA_RAM_SLV0_READBACK__W 16 #define HI_RA_RAM_SLV0_READBACK__M 0xFFFF - - - #define HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 #define HI_RA_RAM_SLV1_FLG_SMM__W 1 #define HI_RA_RAM_SLV1_FLG_SMM__M 0x1 #define HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 #define HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 - #define HI_RA_RAM_SLV1_DEV_ID__A 0x420021 #define HI_RA_RAM_SLV1_DEV_ID__W 7 #define HI_RA_RAM_SLV1_DEV_ID__M 0x7F @@ -216,7 +183,6 @@ extern "C" { #define HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 #define HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 - #define HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 #define HI_RA_RAM_SLV1_FLG_ACC__W 3 #define HI_RA_RAM_SLV1_FLG_ACC__M 0x7 @@ -231,14 +197,12 @@ extern "C" { #define HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 #define HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 - #define HI_RA_RAM_SLV1_STATE__A 0x420024 #define HI_RA_RAM_SLV1_STATE__W 1 #define HI_RA_RAM_SLV1_STATE__M 0x1 #define HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 #define HI_RA_RAM_SLV1_STATE_DATA 0x1 - #define HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 #define HI_RA_RAM_SLV1_BLK_BNK__W 12 #define HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF @@ -249,7 +213,6 @@ extern "C" { #define HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 #define HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 - #define HI_RA_RAM_SLV1_ADDR__A 0x420026 #define HI_RA_RAM_SLV1_ADDR__W 16 #define HI_RA_RAM_SLV1_ADDR__M 0xFFFF @@ -262,16 +225,12 @@ extern "C" { #define HI_RA_RAM_SLV1_READBACK__W 16 #define HI_RA_RAM_SLV1_READBACK__M 0xFFFF - - - #define HI_RA_RAM_SRV_SEM__A 0x420030 #define HI_RA_RAM_SRV_SEM__W 1 #define HI_RA_RAM_SRV_SEM__M 0x1 #define HI_RA_RAM_SRV_SEM_FREE 0x0 #define HI_RA_RAM_SRV_SEM_CLAIMED 0x1 - #define HI_RA_RAM_SRV_RES__A 0x420031 #define HI_RA_RAM_SRV_RES__W 3 #define HI_RA_RAM_SRV_RES__M 0x7 @@ -281,7 +240,6 @@ extern "C" { #define HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 #define HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 - #define HI_RA_RAM_SRV_CMD__A 0x420032 #define HI_RA_RAM_SRV_CMD__W 3 #define HI_RA_RAM_SRV_CMD__M 0x7 @@ -293,22 +251,17 @@ extern "C" { #define HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 - #define HI_RA_RAM_SRV_PAR__AX 0x420033 #define HI_RA_RAM_SRV_PAR__XSZ 5 #define HI_RA_RAM_SRV_PAR__W 16 #define HI_RA_RAM_SRV_PAR__M 0xFFFF - - #define HI_RA_RAM_SRV_NOP_RES__A 0x420031 #define HI_RA_RAM_SRV_NOP_RES__W 3 #define HI_RA_RAM_SRV_NOP_RES__M 0x7 #define HI_RA_RAM_SRV_NOP_RES_OK 0x0 #define HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 - - #define HI_RA_RAM_SRV_UIO_RES__A 0x420031 #define HI_RA_RAM_SRV_UIO_RES__W 3 #define HI_RA_RAM_SRV_UIO_RES__M 0x7 @@ -340,8 +293,6 @@ extern "C" { #define HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 #define HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 - - #define HI_RA_RAM_SRV_RST_RES__A 0x420031 #define HI_RA_RAM_SRV_RST_RES__W 1 #define HI_RA_RAM_SRV_RST_RES__M 0x1 @@ -353,8 +304,6 @@ extern "C" { #define HI_RA_RAM_SRV_RST_KEY__M 0xFFFF #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 - - #define HI_RA_RAM_SRV_CFG_RES__A 0x420031 #define HI_RA_RAM_SRV_CFG_RES__W 1 #define HI_RA_RAM_SRV_CFG_RES__M 0x1 @@ -366,7 +315,6 @@ extern "C" { #define HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF #define HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 - #define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 #define HI_RA_RAM_SRV_CFG_DIV__W 5 #define HI_RA_RAM_SRV_CFG_DIV__M 0x1F @@ -403,15 +351,12 @@ extern "C" { #define HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 #define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 - - #define HI_RA_RAM_SRV_CPY_RES__A 0x420031 #define HI_RA_RAM_SRV_CPY_RES__W 1 #define HI_RA_RAM_SRV_CPY_RES__M 0x1 #define HI_RA_RAM_SRV_CPY_RES_OK 0x0 #define HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 - #define HI_RA_RAM_SRV_CPY_SBB__A 0x420033 #define HI_RA_RAM_SRV_CPY_SBB__W 12 #define HI_RA_RAM_SRV_CPY_SBB__M 0xFFF @@ -422,7 +367,6 @@ extern "C" { #define HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 #define HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 - #define HI_RA_RAM_SRV_CPY_SAD__A 0x420034 #define HI_RA_RAM_SRV_CPY_SAD__W 16 #define HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF @@ -441,13 +385,10 @@ extern "C" { #define HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 #define HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 - #define HI_RA_RAM_SRV_CPY_DAD__A 0x420034 #define HI_RA_RAM_SRV_CPY_DAD__W 16 #define HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF - - #define HI_RA_RAM_SRV_TRM_RES__A 0x420031 #define HI_RA_RAM_SRV_TRM_RES__W 2 #define HI_RA_RAM_SRV_TRM_RES__M 0x3 @@ -455,7 +396,6 @@ extern "C" { #define HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 #define HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 - #define HI_RA_RAM_SRV_TRM_MST__A 0x420033 #define HI_RA_RAM_SRV_TRM_MST__W 12 #define HI_RA_RAM_SRV_TRM_MST__M 0xFFF @@ -471,7 +411,6 @@ extern "C" { #define HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 #define HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF - #define HI_RA_RAM_SRV_TRM_DBB__A 0x420033 #define HI_RA_RAM_SRV_TRM_DBB__W 12 #define HI_RA_RAM_SRV_TRM_DBB__M 0xFFF @@ -482,14 +421,10 @@ extern "C" { #define HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 #define HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 - #define HI_RA_RAM_SRV_TRM_DAD__A 0x420034 #define HI_RA_RAM_SRV_TRM_DAD__W 16 #define HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF - - - #define HI_RA_RAM_USR_BEGIN__A 0x420040 #define HI_RA_RAM_USR_BEGIN__W 16 #define HI_RA_RAM_USR_BEGIN__M 0xFFFF @@ -498,11 +433,6 @@ extern "C" { #define HI_RA_RAM_USR_END__W 16 #define HI_RA_RAM_USR_END__M 0xFFFF - - - - - #define HI_IF_RAM_TRP_BPT0__AX 0x430000 #define HI_IF_RAM_TRP_BPT0__XSZ 2 #define HI_IF_RAM_TRP_BPT0__W 12 @@ -513,9 +443,6 @@ extern "C" { #define HI_IF_RAM_TRP_STKU__W 12 #define HI_IF_RAM_TRP_STKU__M 0xFFF - - - #define HI_IF_RAM_USR_BEGIN__A 0x430200 #define HI_IF_RAM_USR_BEGIN__W 12 #define HI_IF_RAM_USR_BEGIN__M 0xFFF @@ -524,16 +451,8 @@ extern "C" { #define HI_IF_RAM_USR_END__W 12 #define HI_IF_RAM_USR_END__M 0xFFF - - - - #define SC_SID 0x11 - - - - #define SC_COMM_EXEC__A 0x800000 #define SC_COMM_EXEC__W 3 #define SC_COMM_EXEC__M 0x7 @@ -566,11 +485,6 @@ extern "C" { #define SC_COMM_INT_MSK__W 16 #define SC_COMM_INT_MSK__M 0xFFFF - - - - - #define SC_CT_REG_COMM_EXEC__A 0x810000 #define SC_CT_REG_COMM_EXEC__W 3 #define SC_CT_REG_COMM_EXEC__M 0x7 @@ -582,7 +496,6 @@ extern "C" { #define SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 #define SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - #define SC_CT_REG_COMM_STATE__A 0x810001 #define SC_CT_REG_COMM_STATE__W 10 #define SC_CT_REG_COMM_STATE__M 0x3FF @@ -596,7 +509,6 @@ extern "C" { #define SC_CT_REG_COMM_SERVICE1_SC__W 1 #define SC_CT_REG_COMM_SERVICE1_SC__M 0x2 - #define SC_CT_REG_COMM_INT_STA__A 0x810007 #define SC_CT_REG_COMM_INT_STA__W 1 #define SC_CT_REG_COMM_INT_STA__M 0x1 @@ -604,7 +516,6 @@ extern "C" { #define SC_CT_REG_COMM_INT_STA_REQUEST__W 1 #define SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - #define SC_CT_REG_COMM_INT_MSK__A 0x810008 #define SC_CT_REG_COMM_INT_MSK__W 1 #define SC_CT_REG_COMM_INT_MSK__M 0x1 @@ -612,9 +523,6 @@ extern "C" { #define SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 #define SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - - - #define SC_CT_REG_CTL_STK__AX 0x810010 #define SC_CT_REG_CTL_STK__XSZ 4 #define SC_CT_REG_CTL_STK__W 10 @@ -628,10 +536,6 @@ extern "C" { #define SC_CT_REG_CTL_BPT__W 10 #define SC_CT_REG_CTL_BPT__M 0x3FF - - - - #define SC_RA_RAM_PARAM0__A 0x820040 #define SC_RA_RAM_PARAM0__W 16 #define SC_RA_RAM_PARAM0__M 0xFFFF @@ -722,8 +626,6 @@ extern "C" { #define SC_RA_RAM_LOCKTRACK_SR_SCANNING 0xC #define SC_RA_RAM_LOCKTRACK_MAX 0xD - - #define SC_RA_RAM_OP_PARAM__A 0x820048 #define SC_RA_RAM_OP_PARAM__W 13 #define SC_RA_RAM_OP_PARAM__M 0x1FFF @@ -812,8 +714,6 @@ extern "C" { #define SC_RA_RAM_LOCK_NODVBT__W 1 #define SC_RA_RAM_LOCK_NODVBT__M 0x8 - - #define SC_RA_RAM_BE_OPT_ENA__A 0x82004C #define SC_RA_RAM_BE_OPT_ENA__W 5 #define SC_RA_RAM_BE_OPT_ENA__M 0x1F @@ -873,8 +773,6 @@ extern "C" { #define SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 #define SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 - - #define SC_RA_RAM_PILOT_THRES_SPD__A 0x820051 #define SC_RA_RAM_PILOT_THRES_SPD__W 16 #define SC_RA_RAM_PILOT_THRES_SPD__M 0xFFFF @@ -888,8 +786,6 @@ extern "C" { #define SC_RA_RAM_PILOT_THRES_FREQSCAN__M 0xFFFF #define SC_RA_RAM_PILOT_THRES_FREQSCAN__PRE 0x406 - - #define SC_RA_RAM_CO_THRES_8K__A 0x820055 #define SC_RA_RAM_CO_THRES_8K__W 16 #define SC_RA_RAM_CO_THRES_8K__M 0xFFFF @@ -991,17 +887,11 @@ extern "C" { #define SC_RA_RAM_ECHO_GUARD__M 0xFFFF #define SC_RA_RAM_ECHO_GUARD__PRE 0x18 - - #define SC_RA_RAM_IR_FREQ__A 0x8200D0 #define SC_RA_RAM_IR_FREQ__W 16 #define SC_RA_RAM_IR_FREQ__M 0xFFFF #define SC_RA_RAM_IR_FREQ__PRE 0x0 - - - - #define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 #define SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 #define SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF @@ -1015,8 +905,6 @@ extern "C" { #define SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF #define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 - - #define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 #define SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 #define SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF @@ -1030,10 +918,6 @@ extern "C" { #define SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF #define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 - - - - #define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 #define SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 #define SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF @@ -1047,8 +931,6 @@ extern "C" { #define SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF #define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 - - #define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA #define SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 #define SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF @@ -1062,8 +944,6 @@ extern "C" { #define SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF #define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 - - #define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD #define SC_RA_RAM_ECHO_SHIFT_LIM__W 16 #define SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF @@ -1077,10 +957,6 @@ extern "C" { #define SC_RA_RAM_ECHO_FILTER__M 0xFFFF #define SC_RA_RAM_ECHO_FILTER__PRE 0x2 - - - - #define SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 #define SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 #define SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF @@ -1094,8 +970,6 @@ extern "C" { #define SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF #define SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 - - #define SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 #define SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 #define SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF @@ -1109,8 +983,6 @@ extern "C" { #define SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF #define SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 - - #define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 #define SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 #define SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF @@ -1120,8 +992,6 @@ extern "C" { #define SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF #define SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x113 - - #define SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA #define SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 #define SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF @@ -1176,8 +1046,6 @@ extern "C" { #define SC_RA_RAM_BOOTCOUNT__W 16 #define SC_RA_RAM_BOOTCOUNT__M 0xFFFF - - #define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 #define SC_RA_RAM_LC_ABS_2K__W 16 #define SC_RA_RAM_LC_ABS_2K__M 0xFFFF @@ -1187,10 +1055,6 @@ extern "C" { #define SC_RA_RAM_LC_ABS_8K__M 0xFFFF #define SC_RA_RAM_LC_ABS_8K__PRE 0x1F - - - - #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__A 0x8200F6 #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__W 16 #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__M 0xFFFF @@ -1200,8 +1064,6 @@ extern "C" { #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__M 0xFFFF #define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__PRE 0x0 - - #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__A 0x8200F8 #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__W 16 #define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__M 0xFFFF @@ -1217,8 +1079,6 @@ extern "C" { #define SC_RA_RAM_STACKUNDERFLOW__W 16 #define SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF - - #define SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 #define SC_RA_RAM_NF_MAXECHOTOKEN__W 16 #define SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF @@ -1246,10 +1106,6 @@ extern "C" { #define SC_RA_RAM_NF_ECHOTABLE__W 16 #define SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF - - - - #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF @@ -1259,8 +1115,6 @@ extern "C" { #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 - - #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF @@ -1270,8 +1124,6 @@ extern "C" { #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 - - #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF @@ -1281,8 +1133,6 @@ extern "C" { #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 - - #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF @@ -1292,8 +1142,6 @@ extern "C" { #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 - - #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF @@ -1303,8 +1151,6 @@ extern "C" { #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 - - #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF @@ -1314,8 +1160,6 @@ extern "C" { #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 - - #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF @@ -1325,8 +1169,6 @@ extern "C" { #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 - - #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF @@ -1357,11 +1199,6 @@ extern "C" { #define SC_RA_RAM_PROC_EQ 0x7 #define SC_RA_RAM_PROC_MAX 0x8 - - - - - #define SC_IF_RAM_TRP_RST__AX 0x830000 #define SC_IF_RAM_TRP_RST__XSZ 2 #define SC_IF_RAM_TRP_RST__W 12 @@ -1377,9 +1214,6 @@ extern "C" { #define SC_IF_RAM_TRP_STKU__W 12 #define SC_IF_RAM_TRP_STKU__M 0xFFF - - - #define SC_IF_RAM_VERSION_MA_MI__A 0x830FFE #define SC_IF_RAM_VERSION_MA_MI__W 12 #define SC_IF_RAM_VERSION_MA_MI__M 0xFFF @@ -1388,14 +1222,6 @@ extern "C" { #define SC_IF_RAM_VERSION_PATCH__W 12 #define SC_IF_RAM_VERSION_PATCH__M 0xFFF - - - - - - - - #define FE_COMM_EXEC__A 0xC00000 #define FE_COMM_EXEC__W 3 #define FE_COMM_EXEC__M 0x7 @@ -1428,17 +1254,8 @@ extern "C" { #define FE_COMM_INT_MSK__W 16 #define FE_COMM_INT_MSK__M 0xFFFF - - - - #define FE_AD_SID 0x1 - - - - - #define FE_AD_REG_COMM_EXEC__A 0xC10000 #define FE_AD_REG_COMM_EXEC__W 3 #define FE_AD_REG_COMM_EXEC__M 0x7 @@ -1450,7 +1267,6 @@ extern "C" { #define FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 #define FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 - #define FE_AD_REG_COMM_MB__A 0xC10002 #define FE_AD_REG_COMM_MB__W 2 #define FE_AD_REG_COMM_MB__M 0x3 @@ -1483,7 +1299,6 @@ extern "C" { #define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 #define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 - #define FE_AD_REG_COMM_INT_MSK__A 0xC10008 #define FE_AD_REG_COMM_INT_MSK__W 2 #define FE_AD_REG_COMM_INT_MSK__M 0x3 @@ -1491,137 +1306,108 @@ extern "C" { #define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 #define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 - #define FE_AD_REG_CUR_SEL__A 0xC10010 #define FE_AD_REG_CUR_SEL__W 2 #define FE_AD_REG_CUR_SEL__M 0x3 #define FE_AD_REG_CUR_SEL_INIT 0x2 - #define FE_AD_REG_OVERFLOW__A 0xC10011 #define FE_AD_REG_OVERFLOW__W 1 #define FE_AD_REG_OVERFLOW__M 0x1 #define FE_AD_REG_OVERFLOW_INIT 0x0 - #define FE_AD_REG_FDB_IN__A 0xC10012 #define FE_AD_REG_FDB_IN__W 1 #define FE_AD_REG_FDB_IN__M 0x1 #define FE_AD_REG_FDB_IN_INIT 0x0 - #define FE_AD_REG_PD__A 0xC10013 #define FE_AD_REG_PD__W 1 #define FE_AD_REG_PD__M 0x1 #define FE_AD_REG_PD_INIT 0x1 - #define FE_AD_REG_INVEXT__A 0xC10014 #define FE_AD_REG_INVEXT__W 1 #define FE_AD_REG_INVEXT__M 0x1 #define FE_AD_REG_INVEXT_INIT 0x0 - #define FE_AD_REG_CLKNEG__A 0xC10015 #define FE_AD_REG_CLKNEG__W 1 #define FE_AD_REG_CLKNEG__M 0x1 #define FE_AD_REG_CLKNEG_INIT 0x0 - #define FE_AD_REG_MON_IN_MUX__A 0xC10016 #define FE_AD_REG_MON_IN_MUX__W 2 #define FE_AD_REG_MON_IN_MUX__M 0x3 #define FE_AD_REG_MON_IN_MUX_INIT 0x0 - #define FE_AD_REG_MON_IN5__A 0xC10017 #define FE_AD_REG_MON_IN5__W 10 #define FE_AD_REG_MON_IN5__M 0x3FF #define FE_AD_REG_MON_IN5_INIT 0x0 - #define FE_AD_REG_MON_IN4__A 0xC10018 #define FE_AD_REG_MON_IN4__W 10 #define FE_AD_REG_MON_IN4__M 0x3FF #define FE_AD_REG_MON_IN4_INIT 0x0 - #define FE_AD_REG_MON_IN3__A 0xC10019 #define FE_AD_REG_MON_IN3__W 10 #define FE_AD_REG_MON_IN3__M 0x3FF #define FE_AD_REG_MON_IN3_INIT 0x0 - #define FE_AD_REG_MON_IN2__A 0xC1001A #define FE_AD_REG_MON_IN2__W 10 #define FE_AD_REG_MON_IN2__M 0x3FF #define FE_AD_REG_MON_IN2_INIT 0x0 - #define FE_AD_REG_MON_IN1__A 0xC1001B #define FE_AD_REG_MON_IN1__W 10 #define FE_AD_REG_MON_IN1__M 0x3FF #define FE_AD_REG_MON_IN1_INIT 0x0 - #define FE_AD_REG_MON_IN0__A 0xC1001C #define FE_AD_REG_MON_IN0__W 10 #define FE_AD_REG_MON_IN0__M 0x3FF #define FE_AD_REG_MON_IN0_INIT 0x0 - #define FE_AD_REG_MON_IN_VAL__A 0xC1001D #define FE_AD_REG_MON_IN_VAL__W 1 #define FE_AD_REG_MON_IN_VAL__M 0x1 #define FE_AD_REG_MON_IN_VAL_INIT 0x0 - #define FE_AD_REG_CTR_CLK_O__A 0xC1001E #define FE_AD_REG_CTR_CLK_O__W 1 #define FE_AD_REG_CTR_CLK_O__M 0x1 #define FE_AD_REG_CTR_CLK_O_INIT 0x0 - #define FE_AD_REG_CTR_CLK_E_O__A 0xC1001F #define FE_AD_REG_CTR_CLK_E_O__W 1 #define FE_AD_REG_CTR_CLK_E_O__M 0x1 #define FE_AD_REG_CTR_CLK_E_O_INIT 0x1 - #define FE_AD_REG_CTR_VAL_O__A 0xC10020 #define FE_AD_REG_CTR_VAL_O__W 1 #define FE_AD_REG_CTR_VAL_O__M 0x1 #define FE_AD_REG_CTR_VAL_O_INIT 0x0 - #define FE_AD_REG_CTR_VAL_E_O__A 0xC10021 #define FE_AD_REG_CTR_VAL_E_O__W 1 #define FE_AD_REG_CTR_VAL_E_O__M 0x1 #define FE_AD_REG_CTR_VAL_E_O_INIT 0x1 - #define FE_AD_REG_CTR_DATA_O__A 0xC10022 #define FE_AD_REG_CTR_DATA_O__W 10 #define FE_AD_REG_CTR_DATA_O__M 0x3FF #define FE_AD_REG_CTR_DATA_O_INIT 0x0 - #define FE_AD_REG_CTR_DATA_E_O__A 0xC10023 #define FE_AD_REG_CTR_DATA_E_O__W 10 #define FE_AD_REG_CTR_DATA_E_O__M 0x3FF #define FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF - - - - #define FE_AG_SID 0x2 - - - - - #define FE_AG_REG_COMM_EXEC__A 0xC20000 #define FE_AG_REG_COMM_EXEC__W 3 #define FE_AG_REG_COMM_EXEC__M 0x7 @@ -1651,7 +1437,6 @@ extern "C" { #define FE_AG_REG_COMM_MB_OBS_OFF 0x0 #define FE_AG_REG_COMM_MB_OBS_ON 0x2 - #define FE_AG_REG_COMM_SERVICE0__A 0xC20003 #define FE_AG_REG_COMM_SERVICE0__W 10 #define FE_AG_REG_COMM_SERVICE0__M 0x3FF @@ -1688,7 +1473,6 @@ extern "C" { #define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 #define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 - #define FE_AG_REG_COMM_INT_MSK__A 0xC20008 #define FE_AG_REG_COMM_INT_MSK__W 8 #define FE_AG_REG_COMM_INT_MSK__M 0xFF @@ -1717,7 +1501,6 @@ extern "C" { #define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 #define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 - #define FE_AG_REG_AG_MODE_LOP__A 0xC20010 #define FE_AG_REG_AG_MODE_LOP__W 16 #define FE_AG_REG_AG_MODE_LOP__M 0xFFFF @@ -1819,7 +1602,6 @@ extern "C" { #define FE_AG_REG_AG_MODE_LOP_MODE_F_DISABLE 0x0 #define FE_AG_REG_AG_MODE_LOP_MODE_F_ENABLE 0x8000 - #define FE_AG_REG_AG_MODE_HIP__A 0xC20011 #define FE_AG_REG_AG_MODE_HIP__W 2 #define FE_AG_REG_AG_MODE_HIP__M 0x3 @@ -1837,7 +1619,6 @@ extern "C" { #define FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 #define FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 - #define FE_AG_REG_AG_PGA_MODE__A 0xC20012 #define FE_AG_REG_AG_PGA_MODE__W 3 #define FE_AG_REG_AG_PGA_MODE__M 0x7 @@ -1851,7 +1632,6 @@ extern "C" { #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 #define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 - #define FE_AG_REG_AG_AGC_SIO__A 0xC20013 #define FE_AG_REG_AG_AGC_SIO__W 2 #define FE_AG_REG_AG_AGC_SIO__M 0x3 @@ -1869,7 +1649,6 @@ extern "C" { #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 - #define FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 #define FE_AG_REG_AG_AGC_USR_DAT__W 2 #define FE_AG_REG_AG_AGC_USR_DAT__M 0x3 @@ -1880,7 +1659,6 @@ extern "C" { #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 #define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 - #define FE_AG_REG_AG_PWD__A 0xC20015 #define FE_AG_REG_AG_PWD__W 5 #define FE_AG_REG_AG_PWD__M 0x1F @@ -1916,19 +1694,16 @@ extern "C" { #define FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 #define FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 - #define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 #define FE_AG_REG_DCE_AUR_CNT__W 5 #define FE_AG_REG_DCE_AUR_CNT__M 0x1F #define FE_AG_REG_DCE_AUR_CNT_INIT 0x0 - #define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 #define FE_AG_REG_DCE_RUR_CNT__W 5 #define FE_AG_REG_DCE_RUR_CNT__M 0x1F #define FE_AG_REG_DCE_RUR_CNT_INIT 0x0 - #define FE_AG_REG_DCE_AVE_DAT__A 0xC20018 #define FE_AG_REG_DCE_AVE_DAT__W 10 #define FE_AG_REG_DCE_AVE_DAT__M 0x3FF @@ -1938,19 +1713,16 @@ extern "C" { #define FE_AG_REG_DEC_AVE_WRI__M 0x3FF #define FE_AG_REG_DEC_AVE_WRI_INIT 0x0 - #define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A #define FE_AG_REG_ACE_AUR_CNT__W 5 #define FE_AG_REG_ACE_AUR_CNT__M 0x1F #define FE_AG_REG_ACE_AUR_CNT_INIT 0x0 - #define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B #define FE_AG_REG_ACE_RUR_CNT__W 5 #define FE_AG_REG_ACE_RUR_CNT__M 0x1F #define FE_AG_REG_ACE_RUR_CNT_INIT 0x0 - #define FE_AG_REG_ACE_AVE_DAT__A 0xC2001C #define FE_AG_REG_ACE_AVE_DAT__W 10 #define FE_AG_REG_ACE_AVE_DAT__M 0x3FF @@ -1960,7 +1732,6 @@ extern "C" { #define FE_AG_REG_AEC_AVE_INC__M 0x3FF #define FE_AG_REG_AEC_AVE_INC_INIT 0x0 - #define FE_AG_REG_AEC_AVE_DAT__A 0xC2001E #define FE_AG_REG_AEC_AVE_DAT__W 10 #define FE_AG_REG_AEC_AVE_DAT__M 0x3FF @@ -1970,13 +1741,11 @@ extern "C" { #define FE_AG_REG_AEC_CLP_LVL__M 0xFFFF #define FE_AG_REG_AEC_CLP_LVL_INIT 0x0 - #define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 #define FE_AG_REG_CDR_RUR_CNT__W 5 #define FE_AG_REG_CDR_RUR_CNT__M 0x1F #define FE_AG_REG_CDR_RUR_CNT_INIT 0x0 - #define FE_AG_REG_CDR_CLP_DAT__A 0xC20021 #define FE_AG_REG_CDR_CLP_DAT__W 16 #define FE_AG_REG_CDR_CLP_DAT__M 0xFFFF @@ -1986,79 +1755,66 @@ extern "C" { #define FE_AG_REG_CDR_CLP_POS__M 0x3FF #define FE_AG_REG_CDR_CLP_POS_INIT 0x0 - #define FE_AG_REG_CDR_CLP_NEG__A 0xC20023 #define FE_AG_REG_CDR_CLP_NEG__W 10 #define FE_AG_REG_CDR_CLP_NEG__M 0x3FF #define FE_AG_REG_CDR_CLP_NEG_INIT 0x0 - #define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 #define FE_AG_REG_EGC_RUR_CNT__W 5 #define FE_AG_REG_EGC_RUR_CNT__M 0x1F #define FE_AG_REG_EGC_RUR_CNT_INIT 0x0 - #define FE_AG_REG_EGC_SET_LVL__A 0xC20025 #define FE_AG_REG_EGC_SET_LVL__W 9 #define FE_AG_REG_EGC_SET_LVL__M 0x1FF #define FE_AG_REG_EGC_SET_LVL_INIT 0x0 - #define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 #define FE_AG_REG_EGC_FLA_RGN__W 9 #define FE_AG_REG_EGC_FLA_RGN__M 0x1FF #define FE_AG_REG_EGC_FLA_RGN_INIT 0x0 - #define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 #define FE_AG_REG_EGC_SLO_RGN__W 9 #define FE_AG_REG_EGC_SLO_RGN__M 0x1FF #define FE_AG_REG_EGC_SLO_RGN_INIT 0x0 - #define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 #define FE_AG_REG_EGC_JMP_PSN__W 4 #define FE_AG_REG_EGC_JMP_PSN__M 0xF #define FE_AG_REG_EGC_JMP_PSN_INIT 0x0 - #define FE_AG_REG_EGC_FLA_INC__A 0xC20029 #define FE_AG_REG_EGC_FLA_INC__W 16 #define FE_AG_REG_EGC_FLA_INC__M 0xFFFF #define FE_AG_REG_EGC_FLA_INC_INIT 0x0 - #define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A #define FE_AG_REG_EGC_FLA_DEC__W 16 #define FE_AG_REG_EGC_FLA_DEC__M 0xFFFF #define FE_AG_REG_EGC_FLA_DEC_INIT 0x0 - #define FE_AG_REG_EGC_SLO_INC__A 0xC2002B #define FE_AG_REG_EGC_SLO_INC__W 16 #define FE_AG_REG_EGC_SLO_INC__M 0xFFFF #define FE_AG_REG_EGC_SLO_INC_INIT 0x0 - #define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C #define FE_AG_REG_EGC_SLO_DEC__W 16 #define FE_AG_REG_EGC_SLO_DEC__M 0xFFFF #define FE_AG_REG_EGC_SLO_DEC_INIT 0x0 - #define FE_AG_REG_EGC_FAS_INC__A 0xC2002D #define FE_AG_REG_EGC_FAS_INC__W 16 #define FE_AG_REG_EGC_FAS_INC__M 0xFFFF #define FE_AG_REG_EGC_FAS_INC_INIT 0x0 - #define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E #define FE_AG_REG_EGC_FAS_DEC__W 16 #define FE_AG_REG_EGC_FAS_DEC__M 0xFFFF #define FE_AG_REG_EGC_FAS_DEC_INIT 0x0 - #define FE_AG_REG_EGC_MAP_DAT__A 0xC2002F #define FE_AG_REG_EGC_MAP_DAT__W 16 #define FE_AG_REG_EGC_MAP_DAT__M 0xFFFF @@ -2068,31 +1824,26 @@ extern "C" { #define FE_AG_REG_PM1_AGC_WRI__M 0x7FF #define FE_AG_REG_PM1_AGC_WRI_INIT 0x0 - #define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 #define FE_AG_REG_GC1_AGC_RIC__W 16 #define FE_AG_REG_GC1_AGC_RIC__M 0xFFFF #define FE_AG_REG_GC1_AGC_RIC_INIT 0x0 - #define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 #define FE_AG_REG_GC1_AGC_OFF__W 16 #define FE_AG_REG_GC1_AGC_OFF__M 0xFFFF #define FE_AG_REG_GC1_AGC_OFF_INIT 0x0 - #define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 #define FE_AG_REG_GC1_AGC_MAX__W 10 #define FE_AG_REG_GC1_AGC_MAX__M 0x3FF #define FE_AG_REG_GC1_AGC_MAX_INIT 0x0 - #define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 #define FE_AG_REG_GC1_AGC_MIN__W 10 #define FE_AG_REG_GC1_AGC_MIN__M 0x3FF #define FE_AG_REG_GC1_AGC_MIN_INIT 0x0 - #define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 #define FE_AG_REG_GC1_AGC_DAT__W 10 #define FE_AG_REG_GC1_AGC_DAT__M 0x3FF @@ -2102,31 +1853,26 @@ extern "C" { #define FE_AG_REG_PM2_AGC_WRI__M 0x7FF #define FE_AG_REG_PM2_AGC_WRI_INIT 0x0 - #define FE_AG_REG_GC2_AGC_RIC__A 0xC20037 #define FE_AG_REG_GC2_AGC_RIC__W 16 #define FE_AG_REG_GC2_AGC_RIC__M 0xFFFF #define FE_AG_REG_GC2_AGC_RIC_INIT 0x0 - #define FE_AG_REG_GC2_AGC_OFF__A 0xC20038 #define FE_AG_REG_GC2_AGC_OFF__W 16 #define FE_AG_REG_GC2_AGC_OFF__M 0xFFFF #define FE_AG_REG_GC2_AGC_OFF_INIT 0x0 - #define FE_AG_REG_GC2_AGC_MAX__A 0xC20039 #define FE_AG_REG_GC2_AGC_MAX__W 10 #define FE_AG_REG_GC2_AGC_MAX__M 0x3FF #define FE_AG_REG_GC2_AGC_MAX_INIT 0x0 - #define FE_AG_REG_GC2_AGC_MIN__A 0xC2003A #define FE_AG_REG_GC2_AGC_MIN__W 10 #define FE_AG_REG_GC2_AGC_MIN__M 0x3FF #define FE_AG_REG_GC2_AGC_MIN_INIT 0x0 - #define FE_AG_REG_GC2_AGC_DAT__A 0xC2003B #define FE_AG_REG_GC2_AGC_DAT__W 10 #define FE_AG_REG_GC2_AGC_DAT__M 0x3FF @@ -2136,43 +1882,36 @@ extern "C" { #define FE_AG_REG_IND_WIN__M 0x1F #define FE_AG_REG_IND_WIN_INIT 0x0 - #define FE_AG_REG_IND_THD_LOL__A 0xC2003D #define FE_AG_REG_IND_THD_LOL__W 6 #define FE_AG_REG_IND_THD_LOL__M 0x3F #define FE_AG_REG_IND_THD_LOL_INIT 0x0 - #define FE_AG_REG_IND_THD_HIL__A 0xC2003E #define FE_AG_REG_IND_THD_HIL__W 6 #define FE_AG_REG_IND_THD_HIL__M 0x3F #define FE_AG_REG_IND_THD_HIL_INIT 0x0 - #define FE_AG_REG_IND_DEL__A 0xC2003F #define FE_AG_REG_IND_DEL__W 7 #define FE_AG_REG_IND_DEL__M 0x7F #define FE_AG_REG_IND_DEL_INIT 0x0 - #define FE_AG_REG_IND_PD1_WRI__A 0xC20040 #define FE_AG_REG_IND_PD1_WRI__W 6 #define FE_AG_REG_IND_PD1_WRI__M 0x3F #define FE_AG_REG_IND_PD1_WRI_INIT 0x1F - #define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 #define FE_AG_REG_PDA_AUR_CNT__W 5 #define FE_AG_REG_PDA_AUR_CNT__M 0x1F #define FE_AG_REG_PDA_AUR_CNT_INIT 0x0 - #define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 #define FE_AG_REG_PDA_RUR_CNT__W 5 #define FE_AG_REG_PDA_RUR_CNT__M 0x1F #define FE_AG_REG_PDA_RUR_CNT_INIT 0x0 - #define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 #define FE_AG_REG_PDA_AVE_DAT__W 6 #define FE_AG_REG_PDA_AVE_DAT__M 0x3F @@ -2182,43 +1921,36 @@ extern "C" { #define FE_AG_REG_PDC_RUR_CNT__M 0x1F #define FE_AG_REG_PDC_RUR_CNT_INIT 0x0 - #define FE_AG_REG_PDC_SET_LVL__A 0xC20045 #define FE_AG_REG_PDC_SET_LVL__W 6 #define FE_AG_REG_PDC_SET_LVL__M 0x3F #define FE_AG_REG_PDC_SET_LVL_INIT 0x10 - #define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 #define FE_AG_REG_PDC_FLA_RGN__W 6 #define FE_AG_REG_PDC_FLA_RGN__M 0x3F #define FE_AG_REG_PDC_FLA_RGN_INIT 0x0 - #define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 #define FE_AG_REG_PDC_JMP_PSN__W 3 #define FE_AG_REG_PDC_JMP_PSN__M 0x7 #define FE_AG_REG_PDC_JMP_PSN_INIT 0x0 - #define FE_AG_REG_PDC_FLA_STP__A 0xC20048 #define FE_AG_REG_PDC_FLA_STP__W 16 #define FE_AG_REG_PDC_FLA_STP__M 0xFFFF #define FE_AG_REG_PDC_FLA_STP_INIT 0x0 - #define FE_AG_REG_PDC_SLO_STP__A 0xC20049 #define FE_AG_REG_PDC_SLO_STP__W 16 #define FE_AG_REG_PDC_SLO_STP__M 0xFFFF #define FE_AG_REG_PDC_SLO_STP_INIT 0x0 - #define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A #define FE_AG_REG_PDC_PD2_WRI__W 6 #define FE_AG_REG_PDC_PD2_WRI__M 0x3F #define FE_AG_REG_PDC_PD2_WRI_INIT 0x0 - #define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B #define FE_AG_REG_PDC_MAP_DAT__W 6 #define FE_AG_REG_PDC_MAP_DAT__M 0x3F @@ -2228,19 +1960,16 @@ extern "C" { #define FE_AG_REG_PDC_MAX__M 0x3F #define FE_AG_REG_PDC_MAX_INIT 0x2 - #define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D #define FE_AG_REG_TGA_AUR_CNT__W 5 #define FE_AG_REG_TGA_AUR_CNT__M 0x1F #define FE_AG_REG_TGA_AUR_CNT_INIT 0x0 - #define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E #define FE_AG_REG_TGA_RUR_CNT__W 5 #define FE_AG_REG_TGA_RUR_CNT__M 0x1F #define FE_AG_REG_TGA_RUR_CNT_INIT 0x0 - #define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F #define FE_AG_REG_TGA_AVE_DAT__W 6 #define FE_AG_REG_TGA_AVE_DAT__M 0x3F @@ -2250,37 +1979,31 @@ extern "C" { #define FE_AG_REG_TGC_RUR_CNT__M 0x1F #define FE_AG_REG_TGC_RUR_CNT_INIT 0x0 - #define FE_AG_REG_TGC_SET_LVL__A 0xC20051 #define FE_AG_REG_TGC_SET_LVL__W 6 #define FE_AG_REG_TGC_SET_LVL__M 0x3F #define FE_AG_REG_TGC_SET_LVL_INIT 0x0 - #define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 #define FE_AG_REG_TGC_FLA_RGN__W 6 #define FE_AG_REG_TGC_FLA_RGN__M 0x3F #define FE_AG_REG_TGC_FLA_RGN_INIT 0x0 - #define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 #define FE_AG_REG_TGC_JMP_PSN__W 4 #define FE_AG_REG_TGC_JMP_PSN__M 0xF #define FE_AG_REG_TGC_JMP_PSN_INIT 0x0 - #define FE_AG_REG_TGC_FLA_STP__A 0xC20054 #define FE_AG_REG_TGC_FLA_STP__W 16 #define FE_AG_REG_TGC_FLA_STP__M 0xFFFF #define FE_AG_REG_TGC_FLA_STP_INIT 0x0 - #define FE_AG_REG_TGC_SLO_STP__A 0xC20055 #define FE_AG_REG_TGC_SLO_STP__W 16 #define FE_AG_REG_TGC_SLO_STP__M 0xFFFF #define FE_AG_REG_TGC_SLO_STP_INIT 0x0 - #define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 #define FE_AG_REG_TGC_MAP_DAT__W 10 #define FE_AG_REG_TGC_MAP_DAT__M 0x3FF @@ -2290,13 +2013,11 @@ extern "C" { #define FE_AG_REG_FGA_AUR_CNT__M 0x1F #define FE_AG_REG_FGA_AUR_CNT_INIT 0x0 - #define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 #define FE_AG_REG_FGA_RUR_CNT__W 5 #define FE_AG_REG_FGA_RUR_CNT__M 0x1F #define FE_AG_REG_FGA_RUR_CNT_INIT 0x0 - #define FE_AG_REG_FGA_AVE_DAT__A 0xC20059 #define FE_AG_REG_FGA_AVE_DAT__W 10 #define FE_AG_REG_FGA_AVE_DAT__M 0x3FF @@ -2306,37 +2027,31 @@ extern "C" { #define FE_AG_REG_FGC_RUR_CNT__M 0x1F #define FE_AG_REG_FGC_RUR_CNT_INIT 0x0 - #define FE_AG_REG_FGC_SET_LVL__A 0xC2005B #define FE_AG_REG_FGC_SET_LVL__W 9 #define FE_AG_REG_FGC_SET_LVL__M 0x1FF #define FE_AG_REG_FGC_SET_LVL_INIT 0x0 - #define FE_AG_REG_FGC_FLA_RGN__A 0xC2005C #define FE_AG_REG_FGC_FLA_RGN__W 9 #define FE_AG_REG_FGC_FLA_RGN__M 0x1FF #define FE_AG_REG_FGC_FLA_RGN_INIT 0x0 - #define FE_AG_REG_FGC_JMP_PSN__A 0xC2005D #define FE_AG_REG_FGC_JMP_PSN__W 4 #define FE_AG_REG_FGC_JMP_PSN__M 0xF #define FE_AG_REG_FGC_JMP_PSN_INIT 0x0 - #define FE_AG_REG_FGC_FLA_STP__A 0xC2005E #define FE_AG_REG_FGC_FLA_STP__W 16 #define FE_AG_REG_FGC_FLA_STP__M 0xFFFF #define FE_AG_REG_FGC_FLA_STP_INIT 0x0 - #define FE_AG_REG_FGC_SLO_STP__A 0xC2005F #define FE_AG_REG_FGC_SLO_STP__W 16 #define FE_AG_REG_FGC_SLO_STP__M 0xFFFF #define FE_AG_REG_FGC_SLO_STP_INIT 0x0 - #define FE_AG_REG_FGC_MAP_DAT__A 0xC20060 #define FE_AG_REG_FGC_MAP_DAT__W 10 #define FE_AG_REG_FGC_MAP_DAT__M 0x3FF @@ -2346,70 +2061,52 @@ extern "C" { #define FE_AG_REG_FGM_WRI__M 0x3FF #define FE_AG_REG_FGM_WRI_INIT 0x20 - #define FE_AG_REG_BGC_RUR_CNT__A 0xC20062 #define FE_AG_REG_BGC_RUR_CNT__W 5 #define FE_AG_REG_BGC_RUR_CNT__M 0x1F #define FE_AG_REG_BGC_RUR_CNT_INIT 0x0 - #define FE_AG_REG_BGC_SET_LVL__A 0xC20063 #define FE_AG_REG_BGC_SET_LVL__W 9 #define FE_AG_REG_BGC_SET_LVL__M 0x1FF #define FE_AG_REG_BGC_SET_LVL_INIT 0x0 - #define FE_AG_REG_BGC_FLA_RGN__A 0xC20064 #define FE_AG_REG_BGC_FLA_RGN__W 9 #define FE_AG_REG_BGC_FLA_RGN__M 0x1FF #define FE_AG_REG_BGC_FLA_RGN_INIT 0x0 - #define FE_AG_REG_BGC_JMP_PSN__A 0xC20065 #define FE_AG_REG_BGC_JMP_PSN__W 4 #define FE_AG_REG_BGC_JMP_PSN__M 0xF #define FE_AG_REG_BGC_JMP_PSN_INIT 0x0 - #define FE_AG_REG_BGC_FLA_STP__A 0xC20066 #define FE_AG_REG_BGC_FLA_STP__W 16 #define FE_AG_REG_BGC_FLA_STP__M 0xFFFF #define FE_AG_REG_BGC_FLA_STP_INIT 0x0 - #define FE_AG_REG_BGC_SLO_STP__A 0xC20067 #define FE_AG_REG_BGC_SLO_STP__W 16 #define FE_AG_REG_BGC_SLO_STP__M 0xFFFF #define FE_AG_REG_BGC_SLO_STP_INIT 0x0 - #define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 #define FE_AG_REG_BGC_FGC_WRI__W 4 #define FE_AG_REG_BGC_FGC_WRI__M 0xF #define FE_AG_REG_BGC_FGC_WRI_INIT 0x7 - #define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 #define FE_AG_REG_BGC_CGC_WRI__W 2 #define FE_AG_REG_BGC_CGC_WRI__M 0x3 #define FE_AG_REG_BGC_CGC_WRI_INIT 0x1 - #define FE_AG_REG_BGC_FGC_DAT__A 0xC2006A #define FE_AG_REG_BGC_FGC_DAT__W 4 #define FE_AG_REG_BGC_FGC_DAT__M 0xF - - - - #define FE_FS_SID 0x3 - - - - - #define FE_FS_REG_COMM_EXEC__A 0xC30000 #define FE_FS_REG_COMM_EXEC__W 3 #define FE_FS_REG_COMM_EXEC__M 0x7 @@ -2444,7 +2141,6 @@ extern "C" { #define FE_FS_REG_COMM_MB_MUX_REAL 0x0 #define FE_FS_REG_COMM_MB_MUX_IMAG 0x4 - #define FE_FS_REG_COMM_SERVICE0__A 0xC30003 #define FE_FS_REG_COMM_SERVICE0__W 10 #define FE_FS_REG_COMM_SERVICE0__M 0x3FF @@ -2466,35 +2162,23 @@ extern "C" { #define FE_FS_REG_ADD_INC_LOP__M 0xFFFF #define FE_FS_REG_ADD_INC_LOP_INIT 0x0 - #define FE_FS_REG_ADD_INC_HIP__A 0xC30011 #define FE_FS_REG_ADD_INC_HIP__W 12 #define FE_FS_REG_ADD_INC_HIP__M 0xFFF #define FE_FS_REG_ADD_INC_HIP_INIT 0x0 - #define FE_FS_REG_ADD_OFF__A 0xC30012 #define FE_FS_REG_ADD_OFF__W 12 #define FE_FS_REG_ADD_OFF__M 0xFFF #define FE_FS_REG_ADD_OFF_INIT 0x0 - #define FE_FS_REG_ADD_OFF_VAL__A 0xC30013 #define FE_FS_REG_ADD_OFF_VAL__W 1 #define FE_FS_REG_ADD_OFF_VAL__M 0x1 #define FE_FS_REG_ADD_OFF_VAL_INIT 0x0 - - - - #define FE_FD_SID 0x4 - - - - - #define FE_FD_REG_COMM_EXEC__A 0xC40000 #define FE_FD_REG_COMM_EXEC__W 3 #define FE_FD_REG_COMM_EXEC__M 0x7 @@ -2506,7 +2190,6 @@ extern "C" { #define FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 #define FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 - #define FE_FD_REG_COMM_MB__A 0xC40002 #define FE_FD_REG_COMM_MB__W 3 #define FE_FD_REG_COMM_MB__M 0x7 @@ -2535,7 +2218,6 @@ extern "C" { #define FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 #define FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - #define FE_FD_REG_COMM_INT_MSK__A 0xC40008 #define FE_FD_REG_COMM_INT_MSK__W 1 #define FE_FD_REG_COMM_INT_MSK__M 0x1 @@ -2543,7 +2225,6 @@ extern "C" { #define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 #define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - #define FE_FD_REG_SCL__A 0xC40010 #define FE_FD_REG_SCL__W 6 #define FE_FD_REG_SCL__M 0x3F @@ -2572,17 +2253,8 @@ extern "C" { #define FE_FD_REG_POWER__W 10 #define FE_FD_REG_POWER__M 0x3FF - - - - #define FE_IF_SID 0x5 - - - - - #define FE_IF_REG_COMM_EXEC__A 0xC50000 #define FE_IF_REG_COMM_EXEC__W 3 #define FE_IF_REG_COMM_EXEC__M 0x7 @@ -2594,7 +2266,6 @@ extern "C" { #define FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 #define FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 - #define FE_IF_REG_COMM_MB__A 0xC50002 #define FE_IF_REG_COMM_MB__W 3 #define FE_IF_REG_COMM_MB__M 0x7 @@ -2609,29 +2280,18 @@ extern "C" { #define FE_IF_REG_COMM_MB_OBS_OFF 0x0 #define FE_IF_REG_COMM_MB_OBS_ON 0x2 - #define FE_IF_REG_INCR0__A 0xC50010 #define FE_IF_REG_INCR0__W 16 #define FE_IF_REG_INCR0__M 0xFFFF #define FE_IF_REG_INCR0_INIT 0x0 - #define FE_IF_REG_INCR1__A 0xC50011 #define FE_IF_REG_INCR1__W 8 #define FE_IF_REG_INCR1__M 0xFF #define FE_IF_REG_INCR1_INIT 0x28 - - - - #define FE_CF_SID 0x6 - - - - - #define FE_CF_REG_COMM_EXEC__A 0xC60000 #define FE_CF_REG_COMM_EXEC__W 3 #define FE_CF_REG_COMM_EXEC__M 0x7 @@ -2643,7 +2303,6 @@ extern "C" { #define FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 #define FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 - #define FE_CF_REG_COMM_MB__A 0xC60002 #define FE_CF_REG_COMM_MB__W 3 #define FE_CF_REG_COMM_MB__M 0x7 @@ -2672,7 +2331,6 @@ extern "C" { #define FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 #define FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - #define FE_CF_REG_COMM_INT_MSK__A 0xC60008 #define FE_CF_REG_COMM_INT_MSK__W 2 #define FE_CF_REG_COMM_INT_MSK__M 0x3 @@ -2680,7 +2338,6 @@ extern "C" { #define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 #define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - #define FE_CF_REG_SCL__A 0xC60010 #define FE_CF_REG_SCL__W 9 #define FE_CF_REG_SCL__M 0x1FF @@ -2709,17 +2366,8 @@ extern "C" { #define FE_CF_REG_POWER__W 10 #define FE_CF_REG_POWER__M 0x3FF - - - - #define FE_CU_SID 0x7 - - - - - #define FE_CU_REG_COMM_EXEC__A 0xC70000 #define FE_CU_REG_COMM_EXEC__W 3 #define FE_CU_REG_COMM_EXEC__M 0x7 @@ -2754,7 +2402,6 @@ extern "C" { #define FE_CU_REG_COMM_MB_MUX_REAL 0x0 #define FE_CU_REG_COMM_MB_MUX_IMAG 0x4 - #define FE_CU_REG_COMM_SERVICE0__A 0xC70003 #define FE_CU_REG_COMM_SERVICE0__W 10 #define FE_CU_REG_COMM_SERVICE0__M 0x3FF @@ -2781,7 +2428,6 @@ extern "C" { #define FE_CU_REG_COMM_INT_STA_FT_START__W 1 #define FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 - #define FE_CU_REG_COMM_INT_MSK__A 0xC70008 #define FE_CU_REG_COMM_INT_MSK__W 2 #define FE_CU_REG_COMM_INT_MSK__M 0x3 @@ -2792,7 +2438,6 @@ extern "C" { #define FE_CU_REG_COMM_INT_MSK_FT_START__W 1 #define FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 - #define FE_CU_REG_MODE__A 0xC70010 #define FE_CU_REG_MODE__W 3 #define FE_CU_REG_MODE__M 0x7 @@ -2816,19 +2461,16 @@ extern "C" { #define FE_CU_REG_MODE_IFD_ENABLE 0x0 #define FE_CU_REG_MODE_IFD_DISABLE 0x4 - #define FE_CU_REG_FRM_CNT_RST__A 0xC70011 #define FE_CU_REG_FRM_CNT_RST__W 15 #define FE_CU_REG_FRM_CNT_RST__M 0x7FFF #define FE_CU_REG_FRM_CNT_RST_INIT 0x0 - #define FE_CU_REG_FRM_CNT_STR__A 0xC70012 #define FE_CU_REG_FRM_CNT_STR__W 15 #define FE_CU_REG_FRM_CNT_STR__M 0x7FFF #define FE_CU_REG_FRM_CNT_STR_INIT 0x0 - #define FE_CU_REG_FRM_SMP_CNT__A 0xC70013 #define FE_CU_REG_FRM_SMP_CNT__W 15 #define FE_CU_REG_FRM_SMP_CNT__M 0x7FFF @@ -2850,25 +2492,21 @@ extern "C" { #define FE_CU_REG_CTR_NF1_WLO__M 0x7FFF #define FE_CU_REG_CTR_NF1_WLO_INIT 0x0 - #define FE_CU_REG_CTR_NF1_WHI__A 0xC70018 #define FE_CU_REG_CTR_NF1_WHI__W 15 #define FE_CU_REG_CTR_NF1_WHI__M 0x7FFF #define FE_CU_REG_CTR_NF1_WHI_INIT 0x0 - #define FE_CU_REG_CTR_NF2_WLO__A 0xC70019 #define FE_CU_REG_CTR_NF2_WLO__W 15 #define FE_CU_REG_CTR_NF2_WLO__M 0x7FFF #define FE_CU_REG_CTR_NF2_WLO_INIT 0x0 - #define FE_CU_REG_CTR_NF2_WHI__A 0xC7001A #define FE_CU_REG_CTR_NF2_WHI__W 15 #define FE_CU_REG_CTR_NF2_WHI__M 0x7FFF #define FE_CU_REG_CTR_NF2_WHI_INIT 0x0 - #define FE_CU_REG_DIV_NF1_REA__A 0xC7001B #define FE_CU_REG_DIV_NF1_REA__W 12 #define FE_CU_REG_DIV_NF1_REA__M 0xFFF @@ -2885,24 +2523,12 @@ extern "C" { #define FE_CU_REG_DIV_NF2_IMA__W 12 #define FE_CU_REG_DIV_NF2_IMA__M 0xFFF - - #define FE_CU_BUF_RAM__A 0xC80000 - - #define FE_CU_CMP_RAM__A 0xC90000 - - - - #define FT_SID 0x8 - - - - #define FT_COMM_EXEC__A 0x1000000 #define FT_COMM_EXEC__W 3 #define FT_COMM_EXEC__M 0x7 @@ -2935,11 +2561,6 @@ extern "C" { #define FT_COMM_INT_MSK__W 16 #define FT_COMM_INT_MSK__M 0xFFFF - - - - - #define FT_REG_COMM_EXEC__A 0x1010000 #define FT_REG_COMM_EXEC__W 3 #define FT_REG_COMM_EXEC__M 0x7 @@ -2951,7 +2572,6 @@ extern "C" { #define FT_REG_COMM_EXEC_CTL_HOLD 0x2 #define FT_REG_COMM_EXEC_CTL_STEP 0x3 - #define FT_REG_COMM_MB__A 0x1010002 #define FT_REG_COMM_MB__W 3 #define FT_REG_COMM_MB__M 0x7 @@ -2984,7 +2604,6 @@ extern "C" { #define FT_REG_COMM_INT_STA_NEW_MEAS__W 1 #define FT_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - #define FT_REG_COMM_INT_MSK__A 0x1010008 #define FT_REG_COMM_INT_MSK__W 2 #define FT_REG_COMM_INT_MSK__M 0x3 @@ -2992,7 +2611,6 @@ extern "C" { #define FT_REG_COMM_INT_MSK_NEW_MEAS__W 1 #define FT_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - #define FT_REG_MODE_2K__A 0x1010010 #define FT_REG_MODE_2K__W 1 #define FT_REG_MODE_2K__M 0x1 @@ -3000,7 +2618,6 @@ extern "C" { #define FT_REG_MODE_2K_MODE_2K 0x1 #define FT_REG_MODE_2K_INIT 0x0 - #define FT_REG_BUS_MOD__A 0x1010011 #define FT_REG_BUS_MOD__W 1 #define FT_REG_BUS_MOD__M 0x1 @@ -3008,74 +2625,47 @@ extern "C" { #define FT_REG_BUS_MOD_PILOT 0x1 #define FT_REG_BUS_MOD_INIT 0x0 - #define FT_REG_BUS_REAL__A 0x1010012 #define FT_REG_BUS_REAL__W 10 #define FT_REG_BUS_REAL__M 0x3FF #define FT_REG_BUS_REAL_INIT 0x0 - #define FT_REG_BUS_IMAG__A 0x1010013 #define FT_REG_BUS_IMAG__W 10 #define FT_REG_BUS_IMAG__M 0x3FF #define FT_REG_BUS_IMAG_INIT 0x0 - #define FT_REG_BUS_VAL__A 0x1010014 #define FT_REG_BUS_VAL__W 1 #define FT_REG_BUS_VAL__M 0x1 #define FT_REG_BUS_VAL_INIT 0x0 - #define FT_REG_PEAK__A 0x1010015 #define FT_REG_PEAK__W 11 #define FT_REG_PEAK__M 0x7FF #define FT_REG_PEAK_INIT 0x0 - #define FT_REG_NORM_OFF__A 0x1010016 #define FT_REG_NORM_OFF__W 4 #define FT_REG_NORM_OFF__M 0xF #define FT_REG_NORM_OFF_INIT 0x2 - - #define FT_ST1_RAM__A 0x1020000 - - #define FT_ST2_RAM__A 0x1030000 - - #define FT_ST3_RAM__A 0x1040000 - - #define FT_ST5_RAM__A 0x1050000 - - #define FT_ST6_RAM__A 0x1060000 - - #define FT_ST8_RAM__A 0x1070000 - - #define FT_ST9_RAM__A 0x1080000 - - - - #define CP_SID 0x9 - - - - #define CP_COMM_EXEC__A 0x1400000 #define CP_COMM_EXEC__W 3 #define CP_COMM_EXEC__M 0x7 @@ -3108,11 +2698,6 @@ extern "C" { #define CP_COMM_INT_MSK__W 16 #define CP_COMM_INT_MSK__M 0xFFFF - - - - - #define CP_REG_COMM_EXEC__A 0x1410000 #define CP_REG_COMM_EXEC__W 3 #define CP_REG_COMM_EXEC__M 0x7 @@ -3124,7 +2709,6 @@ extern "C" { #define CP_REG_COMM_EXEC_CTL_HOLD 0x2 #define CP_REG_COMM_EXEC_CTL_STEP 0x3 - #define CP_REG_COMM_MB__A 0x1410002 #define CP_REG_COMM_MB__W 3 #define CP_REG_COMM_MB__M 0x7 @@ -3157,7 +2741,6 @@ extern "C" { #define CP_REG_COMM_INT_STA_NEW_MEAS__W 1 #define CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - #define CP_REG_COMM_INT_MSK__A 0x1410008 #define CP_REG_COMM_INT_MSK__W 2 #define CP_REG_COMM_INT_MSK__M 0x3 @@ -3165,55 +2748,46 @@ extern "C" { #define CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 #define CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - #define CP_REG_MODE_2K__A 0x1410010 #define CP_REG_MODE_2K__W 1 #define CP_REG_MODE_2K__M 0x1 #define CP_REG_MODE_2K_INIT 0x0 - #define CP_REG_INTERVAL__A 0x1410011 #define CP_REG_INTERVAL__W 4 #define CP_REG_INTERVAL__M 0xF #define CP_REG_INTERVAL_INIT 0x5 - #define CP_REG_SKIP_START0__A 0x1410012 #define CP_REG_SKIP_START0__W 13 #define CP_REG_SKIP_START0__M 0x1FFF #define CP_REG_SKIP_START0_INIT 0x0 - #define CP_REG_SKIP_STOP0__A 0x1410013 #define CP_REG_SKIP_STOP0__W 13 #define CP_REG_SKIP_STOP0__M 0x1FFF #define CP_REG_SKIP_STOP0_INIT 0x0 - #define CP_REG_SKIP_START1__A 0x1410014 #define CP_REG_SKIP_START1__W 13 #define CP_REG_SKIP_START1__M 0x1FFF #define CP_REG_SKIP_START1_INIT 0x0 - #define CP_REG_SKIP_STOP1__A 0x1410015 #define CP_REG_SKIP_STOP1__W 13 #define CP_REG_SKIP_STOP1__M 0x1FFF #define CP_REG_SKIP_STOP1_INIT 0x0 - #define CP_REG_SKIP_START2__A 0x1410016 #define CP_REG_SKIP_START2__W 13 #define CP_REG_SKIP_START2__M 0x1FFF #define CP_REG_SKIP_START2_INIT 0x0 - #define CP_REG_SKIP_STOP2__A 0x1410017 #define CP_REG_SKIP_STOP2__W 13 #define CP_REG_SKIP_STOP2__M 0x1FFF #define CP_REG_SKIP_STOP2_INIT 0x0 - #define CP_REG_SKIP_ENA__A 0x1410018 #define CP_REG_SKIP_ENA__W 3 #define CP_REG_SKIP_ENA__M 0x7 @@ -3231,13 +2805,11 @@ extern "C" { #define CP_REG_SKIP_ENA_CPD__M 0x4 #define CP_REG_SKIP_ENA_INIT 0x0 - #define CP_REG_BR_MODE_MIX__A 0x1410020 #define CP_REG_BR_MODE_MIX__W 1 #define CP_REG_BR_MODE_MIX__M 0x1 #define CP_REG_BR_MODE_MIX_INIT 0x0 - #define CP_REG_BR_SMB_NR__A 0x1410021 #define CP_REG_BR_SMB_NR__W 3 #define CP_REG_BR_SMB_NR__M 0x7 @@ -3251,37 +2823,31 @@ extern "C" { #define CP_REG_BR_SMB_NR_VAL__M 0x4 #define CP_REG_BR_SMB_NR_INIT 0x0 - #define CP_REG_BR_CP_SMB_NR__A 0x1410022 #define CP_REG_BR_CP_SMB_NR__W 2 #define CP_REG_BR_CP_SMB_NR__M 0x3 #define CP_REG_BR_CP_SMB_NR_INIT 0x0 - #define CP_REG_BR_SPL_OFFSET__A 0x1410023 #define CP_REG_BR_SPL_OFFSET__W 3 #define CP_REG_BR_SPL_OFFSET__M 0x7 #define CP_REG_BR_SPL_OFFSET_INIT 0x0 - #define CP_REG_BR_STR_DEL__A 0x1410024 #define CP_REG_BR_STR_DEL__W 10 #define CP_REG_BR_STR_DEL__M 0x3FF #define CP_REG_BR_STR_DEL_INIT 0xA - #define CP_REG_RT_ANG_INC0__A 0x1410030 #define CP_REG_RT_ANG_INC0__W 16 #define CP_REG_RT_ANG_INC0__M 0xFFFF #define CP_REG_RT_ANG_INC0_INIT 0x0 - #define CP_REG_RT_ANG_INC1__A 0x1410031 #define CP_REG_RT_ANG_INC1__W 8 #define CP_REG_RT_ANG_INC1__M 0xFF #define CP_REG_RT_ANG_INC1_INIT 0x0 - #define CP_REG_RT_DETECT_ENA__A 0x1410032 #define CP_REG_RT_DETECT_ENA__W 2 #define CP_REG_RT_DETECT_ENA__M 0x3 @@ -3295,37 +2861,31 @@ extern "C" { #define CP_REG_RT_DETECT_ENA_CONTINUOUS__M 0x2 #define CP_REG_RT_DETECT_ENA_INIT 0x0 - #define CP_REG_RT_DETECT_TRH__A 0x1410033 #define CP_REG_RT_DETECT_TRH__W 2 #define CP_REG_RT_DETECT_TRH__M 0x3 #define CP_REG_RT_DETECT_TRH_INIT 0x3 - #define CP_REG_RT_SPD_RELIABLE__A 0x1410034 #define CP_REG_RT_SPD_RELIABLE__W 3 #define CP_REG_RT_SPD_RELIABLE__M 0x7 #define CP_REG_RT_SPD_RELIABLE_INIT 0x0 - #define CP_REG_RT_SPD_DIRECTION__A 0x1410035 #define CP_REG_RT_SPD_DIRECTION__W 1 #define CP_REG_RT_SPD_DIRECTION__M 0x1 #define CP_REG_RT_SPD_DIRECTION_INIT 0x0 - #define CP_REG_RT_SPD_MOD__A 0x1410036 #define CP_REG_RT_SPD_MOD__W 2 #define CP_REG_RT_SPD_MOD__M 0x3 #define CP_REG_RT_SPD_MOD_INIT 0x0 - #define CP_REG_RT_SPD_SMB__A 0x1410037 #define CP_REG_RT_SPD_SMB__W 2 #define CP_REG_RT_SPD_SMB__M 0x3 #define CP_REG_RT_SPD_SMB_INIT 0x0 - #define CP_REG_RT_CPD_MODE__A 0x1410038 #define CP_REG_RT_CPD_MODE__W 3 #define CP_REG_RT_CPD_MODE__M 0x7 @@ -3339,25 +2899,21 @@ extern "C" { #define CP_REG_RT_CPD_MODE_ADD__M 0x4 #define CP_REG_RT_CPD_MODE_INIT 0x0 - #define CP_REG_RT_CPD_RELIABLE__A 0x1410039 #define CP_REG_RT_CPD_RELIABLE__W 3 #define CP_REG_RT_CPD_RELIABLE__M 0x7 #define CP_REG_RT_CPD_RELIABLE_INIT 0x0 - #define CP_REG_RT_CPD_BIN__A 0x141003A #define CP_REG_RT_CPD_BIN__W 5 #define CP_REG_RT_CPD_BIN__M 0x1F #define CP_REG_RT_CPD_BIN_INIT 0x0 - #define CP_REG_RT_CPD_MAX__A 0x141003B #define CP_REG_RT_CPD_MAX__W 4 #define CP_REG_RT_CPD_MAX__M 0xF #define CP_REG_RT_CPD_MAX_INIT 0x0 - #define CP_REG_RT_SUPR_VAL__A 0x141003C #define CP_REG_RT_SUPR_VAL__W 2 #define CP_REG_RT_SUPR_VAL__M 0x3 @@ -3371,61 +2927,51 @@ extern "C" { #define CP_REG_RT_SUPR_VAL_DL__M 0x2 #define CP_REG_RT_SUPR_VAL_INIT 0x0 - #define CP_REG_RT_EXP_AVE__A 0x141003D #define CP_REG_RT_EXP_AVE__W 5 #define CP_REG_RT_EXP_AVE__M 0x1F #define CP_REG_RT_EXP_AVE_INIT 0x0 - #define CP_REG_RT_EXP_MARG__A 0x141003E #define CP_REG_RT_EXP_MARG__W 5 #define CP_REG_RT_EXP_MARG__M 0x1F #define CP_REG_RT_EXP_MARG_INIT 0x0 - #define CP_REG_AC_NEXP_OFFS__A 0x1410040 #define CP_REG_AC_NEXP_OFFS__W 8 #define CP_REG_AC_NEXP_OFFS__M 0xFF #define CP_REG_AC_NEXP_OFFS_INIT 0x0 - #define CP_REG_AC_AVER_POW__A 0x1410041 #define CP_REG_AC_AVER_POW__W 8 #define CP_REG_AC_AVER_POW__M 0xFF #define CP_REG_AC_AVER_POW_INIT 0x5F - #define CP_REG_AC_MAX_POW__A 0x1410042 #define CP_REG_AC_MAX_POW__W 8 #define CP_REG_AC_MAX_POW__M 0xFF #define CP_REG_AC_MAX_POW_INIT 0x7A - #define CP_REG_AC_WEIGHT_MAN__A 0x1410043 #define CP_REG_AC_WEIGHT_MAN__W 6 #define CP_REG_AC_WEIGHT_MAN__M 0x3F #define CP_REG_AC_WEIGHT_MAN_INIT 0x31 - #define CP_REG_AC_WEIGHT_EXP__A 0x1410044 #define CP_REG_AC_WEIGHT_EXP__W 5 #define CP_REG_AC_WEIGHT_EXP__M 0x1F #define CP_REG_AC_WEIGHT_EXP_INIT 0x10 - #define CP_REG_AC_GAIN_MAN__A 0x1410045 #define CP_REG_AC_GAIN_MAN__W 16 #define CP_REG_AC_GAIN_MAN__M 0xFFFF #define CP_REG_AC_GAIN_MAN_INIT 0x0 - #define CP_REG_AC_GAIN_EXP__A 0x1410046 #define CP_REG_AC_GAIN_EXP__W 5 #define CP_REG_AC_GAIN_EXP__M 0x1F #define CP_REG_AC_GAIN_EXP_INIT 0x0 - #define CP_REG_AC_AMP_MODE__A 0x1410047 #define CP_REG_AC_AMP_MODE__W 2 #define CP_REG_AC_AMP_MODE__M 0x3 @@ -3434,19 +2980,16 @@ extern "C" { #define CP_REG_AC_AMP_MODE_FIXED 0x2 #define CP_REG_AC_AMP_MODE_INIT 0x2 - #define CP_REG_AC_AMP_FIX__A 0x1410048 #define CP_REG_AC_AMP_FIX__W 14 #define CP_REG_AC_AMP_FIX__M 0x3FFF #define CP_REG_AC_AMP_FIX_INIT 0x1FF - #define CP_REG_AC_AMP_READ__A 0x1410049 #define CP_REG_AC_AMP_READ__W 14 #define CP_REG_AC_AMP_READ__M 0x3FFF #define CP_REG_AC_AMP_READ_INIT 0x0 - #define CP_REG_AC_ANG_MODE__A 0x141004A #define CP_REG_AC_ANG_MODE__W 2 #define CP_REG_AC_ANG_MODE__M 0x3 @@ -3456,25 +2999,21 @@ extern "C" { #define CP_REG_AC_ANG_MODE_OFFSET 0x3 #define CP_REG_AC_ANG_MODE_INIT 0x3 - #define CP_REG_AC_ANG_OFFS__A 0x141004B #define CP_REG_AC_ANG_OFFS__W 14 #define CP_REG_AC_ANG_OFFS__M 0x3FFF #define CP_REG_AC_ANG_OFFS_INIT 0x0 - #define CP_REG_AC_ANG_READ__A 0x141004C #define CP_REG_AC_ANG_READ__W 16 #define CP_REG_AC_ANG_READ__M 0xFFFF #define CP_REG_AC_ANG_READ_INIT 0x0 - #define CP_REG_DL_MB_WR_ADDR__A 0x1410050 #define CP_REG_DL_MB_WR_ADDR__W 15 #define CP_REG_DL_MB_WR_ADDR__M 0x7FFF #define CP_REG_DL_MB_WR_ADDR_INIT 0x0 - #define CP_REG_DL_MB_WR_CTR__A 0x1410051 #define CP_REG_DL_MB_WR_CTR__W 5 #define CP_REG_DL_MB_WR_CTR__M 0x1F @@ -3492,13 +3031,11 @@ extern "C" { #define CP_REG_DL_MB_WR_CTR_CTR__M 0x1 #define CP_REG_DL_MB_WR_CTR_INIT 0x0 - #define CP_REG_DL_MB_RD_ADDR__A 0x1410052 #define CP_REG_DL_MB_RD_ADDR__W 15 #define CP_REG_DL_MB_RD_ADDR__M 0x7FFF #define CP_REG_DL_MB_RD_ADDR_INIT 0x0 - #define CP_REG_DL_MB_RD_CTR__A 0x1410053 #define CP_REG_DL_MB_RD_CTR__W 11 #define CP_REG_DL_MB_RD_CTR__M 0x7FF @@ -3528,36 +3065,18 @@ extern "C" { #define CP_REG_DL_MB_RD_CTR_CTR__M 0x1 #define CP_REG_DL_MB_RD_CTR_INIT 0x0 - - #define CP_BR_BUF_RAM__A 0x1420000 - - #define CP_BR_CPL_RAM__A 0x1430000 - - #define CP_PB_DL0_RAM__A 0x1440000 - - #define CP_PB_DL1_RAM__A 0x1450000 - - #define CP_PB_DL2_RAM__A 0x1460000 - - - - #define CE_SID 0xA - - - - #define CE_COMM_EXEC__A 0x1800000 #define CE_COMM_EXEC__W 3 #define CE_COMM_EXEC__M 0x7 @@ -3590,11 +3109,6 @@ extern "C" { #define CE_COMM_INT_MSK__W 16 #define CE_COMM_INT_MSK__M 0xFFFF - - - - - #define CE_REG_COMM_EXEC__A 0x1810000 #define CE_REG_COMM_EXEC__W 3 #define CE_REG_COMM_EXEC__M 0x7 @@ -3606,7 +3120,6 @@ extern "C" { #define CE_REG_COMM_EXEC_CTL_HOLD 0x2 #define CE_REG_COMM_EXEC_CTL_STEP 0x3 - #define CE_REG_COMM_MB__A 0x1810002 #define CE_REG_COMM_MB__W 4 #define CE_REG_COMM_MB__M 0xF @@ -3652,7 +3165,6 @@ extern "C" { #define CE_REG_COMM_INT_STA_CE_FI__W 1 #define CE_REG_COMM_INT_STA_CE_FI__M 0x4 - #define CE_REG_COMM_INT_MSK__A 0x1810008 #define CE_REG_COMM_INT_MSK__W 3 #define CE_REG_COMM_INT_MSK__M 0x7 @@ -3666,19 +3178,15 @@ extern "C" { #define CE_REG_COMM_INT_MSK_CE_FI__W 1 #define CE_REG_COMM_INT_MSK_CE_FI__M 0x4 - #define CE_REG_2K__A 0x1810010 #define CE_REG_2K__W 1 #define CE_REG_2K__M 0x1 #define CE_REG_2K_INIT 0x0 - #define CE_REG_TAPSET__A 0x1810011 #define CE_REG_TAPSET__W 2 #define CE_REG_TAPSET__M 0x3 - - #define CE_REG_TAPSET_MOTION_INIT 0x0 #define CE_REG_TAPSET_MOTION_NO 0x0 @@ -3689,43 +3197,36 @@ extern "C" { #define CE_REG_TAPSET_MOTION_UNDEFINED 0x3 - #define CE_REG_AVG_POW__A 0x1810012 #define CE_REG_AVG_POW__W 8 #define CE_REG_AVG_POW__M 0xFF #define CE_REG_AVG_POW_INIT 0x0 - #define CE_REG_MAX_POW__A 0x1810013 #define CE_REG_MAX_POW__W 8 #define CE_REG_MAX_POW__M 0xFF #define CE_REG_MAX_POW_INIT 0x0 - #define CE_REG_ATT__A 0x1810014 #define CE_REG_ATT__W 8 #define CE_REG_ATT__M 0xFF #define CE_REG_ATT_INIT 0x0 - #define CE_REG_NRED__A 0x1810015 #define CE_REG_NRED__W 6 #define CE_REG_NRED__M 0x3F #define CE_REG_NRED_INIT 0x0 - #define CE_REG_PU_SIGN__A 0x1810020 #define CE_REG_PU_SIGN__W 1 #define CE_REG_PU_SIGN__M 0x1 #define CE_REG_PU_SIGN_INIT 0x0 - #define CE_REG_PU_MIX__A 0x1810021 #define CE_REG_PU_MIX__W 7 #define CE_REG_PU_MIX__M 0x7F #define CE_REG_PU_MIX_INIT 0x0 - #define CE_REG_PB_PILOT_REQ__A 0x1810030 #define CE_REG_PB_PILOT_REQ__W 15 #define CE_REG_PB_PILOT_REQ__M 0x7FFF @@ -3737,49 +3238,41 @@ extern "C" { #define CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 #define CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF - #define CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 #define CE_REG_PB_PILOT_REQ_VALID__W 1 #define CE_REG_PB_PILOT_REQ_VALID__M 0x1 #define CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 - #define CE_REG_PB_FREEZE__A 0x1810032 #define CE_REG_PB_FREEZE__W 1 #define CE_REG_PB_FREEZE__M 0x1 #define CE_REG_PB_FREEZE_INIT 0x0 - #define CE_REG_PB_PILOT_EXP__A 0x1810038 #define CE_REG_PB_PILOT_EXP__W 4 #define CE_REG_PB_PILOT_EXP__M 0xF #define CE_REG_PB_PILOT_EXP_INIT 0x0 - #define CE_REG_PB_PILOT_REAL__A 0x1810039 #define CE_REG_PB_PILOT_REAL__W 10 #define CE_REG_PB_PILOT_REAL__M 0x3FF #define CE_REG_PB_PILOT_REAL_INIT 0x0 - #define CE_REG_PB_PILOT_IMAG__A 0x181003A #define CE_REG_PB_PILOT_IMAG__W 10 #define CE_REG_PB_PILOT_IMAG__M 0x3FF #define CE_REG_PB_PILOT_IMAG_INIT 0x0 - #define CE_REG_PB_SMBNR__A 0x181003B #define CE_REG_PB_SMBNR__W 5 #define CE_REG_PB_SMBNR__M 0x1F #define CE_REG_PB_SMBNR_INIT 0x0 - #define CE_REG_NE_PILOT_REQ__A 0x1810040 #define CE_REG_NE_PILOT_REQ__W 12 #define CE_REG_NE_PILOT_REQ__M 0xFFF #define CE_REG_NE_PILOT_REQ_INIT 0x0 - #define CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 #define CE_REG_NE_PILOT_REQ_VALID__W 2 #define CE_REG_NE_PILOT_REQ_VALID__M 0x3 @@ -3791,13 +3284,11 @@ extern "C" { #define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 #define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 - #define CE_REG_NE_PILOT_DATA__A 0x1810042 #define CE_REG_NE_PILOT_DATA__W 10 #define CE_REG_NE_PILOT_DATA__M 0x3FF #define CE_REG_NE_PILOT_DATA_INIT 0x0 - #define CE_REG_NE_ERR_SELECT__A 0x1810043 #define CE_REG_NE_ERR_SELECT__W 3 #define CE_REG_NE_ERR_SELECT__M 0x7 @@ -3815,31 +3306,26 @@ extern "C" { #define CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 #define CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 - #define CE_REG_NE_TD_CAL__A 0x1810044 #define CE_REG_NE_TD_CAL__W 9 #define CE_REG_NE_TD_CAL__M 0x1FF #define CE_REG_NE_TD_CAL_INIT 0x0 - #define CE_REG_NE_FD_CAL__A 0x1810045 #define CE_REG_NE_FD_CAL__W 9 #define CE_REG_NE_FD_CAL__M 0x1FF #define CE_REG_NE_FD_CAL_INIT 0x0 - #define CE_REG_NE_MIXAVG__A 0x1810046 #define CE_REG_NE_MIXAVG__W 3 #define CE_REG_NE_MIXAVG__M 0x7 #define CE_REG_NE_MIXAVG_INIT 0x0 - #define CE_REG_NE_NUPD_OFS__A 0x1810047 #define CE_REG_NE_NUPD_OFS__W 7 #define CE_REG_NE_NUPD_OFS__M 0x7F #define CE_REG_NE_NUPD_OFS_INIT 0x0 - #define CE_REG_NE_TD_POW__A 0x1810048 #define CE_REG_NE_TD_POW__W 15 #define CE_REG_NE_TD_POW__M 0x7FFF @@ -3853,7 +3339,6 @@ extern "C" { #define CE_REG_NE_TD_POW_MANTISSA__W 10 #define CE_REG_NE_TD_POW_MANTISSA__M 0x3FF - #define CE_REG_NE_FD_POW__A 0x1810049 #define CE_REG_NE_FD_POW__W 15 #define CE_REG_NE_FD_POW__M 0x7FFF @@ -3867,97 +3352,81 @@ extern "C" { #define CE_REG_NE_FD_POW_MANTISSA__W 10 #define CE_REG_NE_FD_POW_MANTISSA__M 0x3FF - #define CE_REG_NE_NEXP_AVG__A 0x181004A #define CE_REG_NE_NEXP_AVG__W 8 #define CE_REG_NE_NEXP_AVG__M 0xFF #define CE_REG_NE_NEXP_AVG_INIT 0x0 - #define CE_REG_NE_OFFSET__A 0x181004B #define CE_REG_NE_OFFSET__W 9 #define CE_REG_NE_OFFSET__M 0x1FF #define CE_REG_NE_OFFSET_INIT 0x0 - #define CE_REG_PE_NEXP_OFFS__A 0x1810050 #define CE_REG_PE_NEXP_OFFS__W 8 #define CE_REG_PE_NEXP_OFFS__M 0xFF #define CE_REG_PE_NEXP_OFFS_INIT 0x0 - #define CE_REG_PE_TIMESHIFT__A 0x1810051 #define CE_REG_PE_TIMESHIFT__W 14 #define CE_REG_PE_TIMESHIFT__M 0x3FFF #define CE_REG_PE_TIMESHIFT_INIT 0x0 - #define CE_REG_PE_DIF_REAL_L__A 0x1810052 #define CE_REG_PE_DIF_REAL_L__W 16 #define CE_REG_PE_DIF_REAL_L__M 0xFFFF #define CE_REG_PE_DIF_REAL_L_INIT 0x0 - #define CE_REG_PE_DIF_IMAG_L__A 0x1810053 #define CE_REG_PE_DIF_IMAG_L__W 16 #define CE_REG_PE_DIF_IMAG_L__M 0xFFFF #define CE_REG_PE_DIF_IMAG_L_INIT 0x0 - #define CE_REG_PE_DIF_REAL_R__A 0x1810054 #define CE_REG_PE_DIF_REAL_R__W 16 #define CE_REG_PE_DIF_REAL_R__M 0xFFFF #define CE_REG_PE_DIF_REAL_R_INIT 0x0 - #define CE_REG_PE_DIF_IMAG_R__A 0x1810055 #define CE_REG_PE_DIF_IMAG_R__W 16 #define CE_REG_PE_DIF_IMAG_R__M 0xFFFF #define CE_REG_PE_DIF_IMAG_R_INIT 0x0 - #define CE_REG_PE_ABS_REAL_L__A 0x1810056 #define CE_REG_PE_ABS_REAL_L__W 16 #define CE_REG_PE_ABS_REAL_L__M 0xFFFF #define CE_REG_PE_ABS_REAL_L_INIT 0x0 - #define CE_REG_PE_ABS_IMAG_L__A 0x1810057 #define CE_REG_PE_ABS_IMAG_L__W 16 #define CE_REG_PE_ABS_IMAG_L__M 0xFFFF #define CE_REG_PE_ABS_IMAG_L_INIT 0x0 - #define CE_REG_PE_ABS_REAL_R__A 0x1810058 #define CE_REG_PE_ABS_REAL_R__W 16 #define CE_REG_PE_ABS_REAL_R__M 0xFFFF #define CE_REG_PE_ABS_REAL_R_INIT 0x0 - #define CE_REG_PE_ABS_IMAG_R__A 0x1810059 #define CE_REG_PE_ABS_IMAG_R__W 16 #define CE_REG_PE_ABS_IMAG_R__M 0xFFFF #define CE_REG_PE_ABS_IMAG_R_INIT 0x0 - #define CE_REG_PE_ABS_EXP_L__A 0x181005A #define CE_REG_PE_ABS_EXP_L__W 5 #define CE_REG_PE_ABS_EXP_L__M 0x1F #define CE_REG_PE_ABS_EXP_L_INIT 0x0 - #define CE_REG_PE_ABS_EXP_R__A 0x181005B #define CE_REG_PE_ABS_EXP_R__W 5 #define CE_REG_PE_ABS_EXP_R__M 0x1F #define CE_REG_PE_ABS_EXP_R_INIT 0x0 - #define CE_REG_TP_UPDATE_MODE__A 0x1810060 #define CE_REG_TP_UPDATE_MODE__W 1 #define CE_REG_TP_UPDATE_MODE__M 0x1 #define CE_REG_TP_UPDATE_MODE_INIT 0x0 - #define CE_REG_TP_LMS_TAP_ON__A 0x1810061 #define CE_REG_TP_LMS_TAP_ON__W 1 #define CE_REG_TP_LMS_TAP_ON__M 0x1 @@ -4007,7 +3476,6 @@ extern "C" { #define CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 #define CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF - #define CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D #define CE_REG_TP_DOPP_DIFF_ENERGY__W 15 #define CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF @@ -4021,7 +3489,6 @@ extern "C" { #define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 #define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF - #define CE_REG_TP_A0_TAP_ENERGY__A 0x181006E #define CE_REG_TP_A0_TAP_ENERGY__W 15 #define CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF @@ -4035,7 +3502,6 @@ extern "C" { #define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 #define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF - #define CE_REG_TP_A1_TAP_ENERGY__A 0x181006F #define CE_REG_TP_A1_TAP_ENERGY__W 15 #define CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF @@ -4049,399 +3515,331 @@ extern "C" { #define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 #define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF - #define CE_REG_TI_NEXP_OFFS__A 0x1810070 #define CE_REG_TI_NEXP_OFFS__W 8 #define CE_REG_TI_NEXP_OFFS__M 0xFF #define CE_REG_TI_NEXP_OFFS_INIT 0x0 - #define CE_REG_TI_PEAK__A 0x1810071 #define CE_REG_TI_PEAK__W 8 #define CE_REG_TI_PEAK__M 0xFF #define CE_REG_TI_PEAK_INIT 0x0 - #define CE_REG_FI_SHT_INCR__A 0x1810090 #define CE_REG_FI_SHT_INCR__W 7 #define CE_REG_FI_SHT_INCR__M 0x7F #define CE_REG_FI_SHT_INCR_INIT 0x9 - #define CE_REG_FI_EXP_NORM__A 0x1810091 #define CE_REG_FI_EXP_NORM__W 4 #define CE_REG_FI_EXP_NORM__M 0xF #define CE_REG_FI_EXP_NORM_INIT 0x4 - #define CE_REG_FI_SUPR_VAL__A 0x1810092 #define CE_REG_FI_SUPR_VAL__W 1 #define CE_REG_FI_SUPR_VAL__M 0x1 #define CE_REG_FI_SUPR_VAL_INIT 0x1 - #define CE_REG_IR_INPUTSEL__A 0x18100A0 #define CE_REG_IR_INPUTSEL__W 1 #define CE_REG_IR_INPUTSEL__M 0x1 #define CE_REG_IR_INPUTSEL_INIT 0x0 - #define CE_REG_IR_STARTPOS__A 0x18100A1 #define CE_REG_IR_STARTPOS__W 8 #define CE_REG_IR_STARTPOS__M 0xFF #define CE_REG_IR_STARTPOS_INIT 0x0 - #define CE_REG_IR_NEXP_THRES__A 0x18100A2 #define CE_REG_IR_NEXP_THRES__W 8 #define CE_REG_IR_NEXP_THRES__M 0xFF #define CE_REG_IR_NEXP_THRES_INIT 0x0 - #define CE_REG_IR_LENGTH__A 0x18100A3 #define CE_REG_IR_LENGTH__W 4 #define CE_REG_IR_LENGTH__M 0xF #define CE_REG_IR_LENGTH_INIT 0x0 - #define CE_REG_IR_FREQ__A 0x18100A4 #define CE_REG_IR_FREQ__W 11 #define CE_REG_IR_FREQ__M 0x7FF #define CE_REG_IR_FREQ_INIT 0x0 - #define CE_REG_IR_FREQINC__A 0x18100A5 #define CE_REG_IR_FREQINC__W 11 #define CE_REG_IR_FREQINC__M 0x7FF #define CE_REG_IR_FREQINC_INIT 0x0 - #define CE_REG_IR_KAISINC__A 0x18100A6 #define CE_REG_IR_KAISINC__W 15 #define CE_REG_IR_KAISINC__M 0x7FFF #define CE_REG_IR_KAISINC_INIT 0x0 - #define CE_REG_IR_CTL__A 0x18100A7 #define CE_REG_IR_CTL__W 3 #define CE_REG_IR_CTL__M 0x7 #define CE_REG_IR_CTL_INIT 0x0 - #define CE_REG_IR_REAL__A 0x18100A8 #define CE_REG_IR_REAL__W 16 #define CE_REG_IR_REAL__M 0xFFFF #define CE_REG_IR_REAL_INIT 0x0 - #define CE_REG_IR_IMAG__A 0x18100A9 #define CE_REG_IR_IMAG__W 16 #define CE_REG_IR_IMAG__M 0xFFFF #define CE_REG_IR_IMAG_INIT 0x0 - #define CE_REG_IR_INDEX__A 0x18100AA #define CE_REG_IR_INDEX__W 12 #define CE_REG_IR_INDEX__M 0xFFF #define CE_REG_IR_INDEX_INIT 0x0 - - - #define CE_REG_FR_TREAL00__A 0x1820010 #define CE_REG_FR_TREAL00__W 11 #define CE_REG_FR_TREAL00__M 0x7FF #define CE_REG_FR_TREAL00_INIT 0x52 - #define CE_REG_FR_TIMAG00__A 0x1820011 #define CE_REG_FR_TIMAG00__W 11 #define CE_REG_FR_TIMAG00__M 0x7FF #define CE_REG_FR_TIMAG00_INIT 0x0 - #define CE_REG_FR_TREAL01__A 0x1820012 #define CE_REG_FR_TREAL01__W 11 #define CE_REG_FR_TREAL01__M 0x7FF #define CE_REG_FR_TREAL01_INIT 0x52 - #define CE_REG_FR_TIMAG01__A 0x1820013 #define CE_REG_FR_TIMAG01__W 11 #define CE_REG_FR_TIMAG01__M 0x7FF #define CE_REG_FR_TIMAG01_INIT 0x0 - #define CE_REG_FR_TREAL02__A 0x1820014 #define CE_REG_FR_TREAL02__W 11 #define CE_REG_FR_TREAL02__M 0x7FF #define CE_REG_FR_TREAL02_INIT 0x52 - #define CE_REG_FR_TIMAG02__A 0x1820015 #define CE_REG_FR_TIMAG02__W 11 #define CE_REG_FR_TIMAG02__M 0x7FF #define CE_REG_FR_TIMAG02_INIT 0x0 - #define CE_REG_FR_TREAL03__A 0x1820016 #define CE_REG_FR_TREAL03__W 11 #define CE_REG_FR_TREAL03__M 0x7FF #define CE_REG_FR_TREAL03_INIT 0x52 - #define CE_REG_FR_TIMAG03__A 0x1820017 #define CE_REG_FR_TIMAG03__W 11 #define CE_REG_FR_TIMAG03__M 0x7FF #define CE_REG_FR_TIMAG03_INIT 0x0 - #define CE_REG_FR_TREAL04__A 0x1820018 #define CE_REG_FR_TREAL04__W 11 #define CE_REG_FR_TREAL04__M 0x7FF #define CE_REG_FR_TREAL04_INIT 0x52 - #define CE_REG_FR_TIMAG04__A 0x1820019 #define CE_REG_FR_TIMAG04__W 11 #define CE_REG_FR_TIMAG04__M 0x7FF #define CE_REG_FR_TIMAG04_INIT 0x0 - #define CE_REG_FR_TREAL05__A 0x182001A #define CE_REG_FR_TREAL05__W 11 #define CE_REG_FR_TREAL05__M 0x7FF #define CE_REG_FR_TREAL05_INIT 0x52 - #define CE_REG_FR_TIMAG05__A 0x182001B #define CE_REG_FR_TIMAG05__W 11 #define CE_REG_FR_TIMAG05__M 0x7FF #define CE_REG_FR_TIMAG05_INIT 0x0 - #define CE_REG_FR_TREAL06__A 0x182001C #define CE_REG_FR_TREAL06__W 11 #define CE_REG_FR_TREAL06__M 0x7FF #define CE_REG_FR_TREAL06_INIT 0x52 - #define CE_REG_FR_TIMAG06__A 0x182001D #define CE_REG_FR_TIMAG06__W 11 #define CE_REG_FR_TIMAG06__M 0x7FF #define CE_REG_FR_TIMAG06_INIT 0x0 - #define CE_REG_FR_TREAL07__A 0x182001E #define CE_REG_FR_TREAL07__W 11 #define CE_REG_FR_TREAL07__M 0x7FF #define CE_REG_FR_TREAL07_INIT 0x52 - #define CE_REG_FR_TIMAG07__A 0x182001F #define CE_REG_FR_TIMAG07__W 11 #define CE_REG_FR_TIMAG07__M 0x7FF #define CE_REG_FR_TIMAG07_INIT 0x0 - #define CE_REG_FR_TREAL08__A 0x1820020 #define CE_REG_FR_TREAL08__W 11 #define CE_REG_FR_TREAL08__M 0x7FF #define CE_REG_FR_TREAL08_INIT 0x52 - #define CE_REG_FR_TIMAG08__A 0x1820021 #define CE_REG_FR_TIMAG08__W 11 #define CE_REG_FR_TIMAG08__M 0x7FF #define CE_REG_FR_TIMAG08_INIT 0x0 - #define CE_REG_FR_TREAL09__A 0x1820022 #define CE_REG_FR_TREAL09__W 11 #define CE_REG_FR_TREAL09__M 0x7FF #define CE_REG_FR_TREAL09_INIT 0x52 - #define CE_REG_FR_TIMAG09__A 0x1820023 #define CE_REG_FR_TIMAG09__W 11 #define CE_REG_FR_TIMAG09__M 0x7FF #define CE_REG_FR_TIMAG09_INIT 0x0 - #define CE_REG_FR_TREAL10__A 0x1820024 #define CE_REG_FR_TREAL10__W 11 #define CE_REG_FR_TREAL10__M 0x7FF #define CE_REG_FR_TREAL10_INIT 0x52 - #define CE_REG_FR_TIMAG10__A 0x1820025 #define CE_REG_FR_TIMAG10__W 11 #define CE_REG_FR_TIMAG10__M 0x7FF #define CE_REG_FR_TIMAG10_INIT 0x0 - #define CE_REG_FR_TREAL11__A 0x1820026 #define CE_REG_FR_TREAL11__W 11 #define CE_REG_FR_TREAL11__M 0x7FF #define CE_REG_FR_TREAL11_INIT 0x52 - #define CE_REG_FR_TIMAG11__A 0x1820027 #define CE_REG_FR_TIMAG11__W 11 #define CE_REG_FR_TIMAG11__M 0x7FF #define CE_REG_FR_TIMAG11_INIT 0x0 - #define CE_REG_FR_MID_TAP__A 0x1820028 #define CE_REG_FR_MID_TAP__W 11 #define CE_REG_FR_MID_TAP__M 0x7FF #define CE_REG_FR_MID_TAP_INIT 0x51 - #define CE_REG_FR_SQS_G00__A 0x1820029 #define CE_REG_FR_SQS_G00__W 8 #define CE_REG_FR_SQS_G00__M 0xFF #define CE_REG_FR_SQS_G00_INIT 0xB - #define CE_REG_FR_SQS_G01__A 0x182002A #define CE_REG_FR_SQS_G01__W 8 #define CE_REG_FR_SQS_G01__M 0xFF #define CE_REG_FR_SQS_G01_INIT 0xB - #define CE_REG_FR_SQS_G02__A 0x182002B #define CE_REG_FR_SQS_G02__W 8 #define CE_REG_FR_SQS_G02__M 0xFF #define CE_REG_FR_SQS_G02_INIT 0xB - #define CE_REG_FR_SQS_G03__A 0x182002C #define CE_REG_FR_SQS_G03__W 8 #define CE_REG_FR_SQS_G03__M 0xFF #define CE_REG_FR_SQS_G03_INIT 0xB - #define CE_REG_FR_SQS_G04__A 0x182002D #define CE_REG_FR_SQS_G04__W 8 #define CE_REG_FR_SQS_G04__M 0xFF #define CE_REG_FR_SQS_G04_INIT 0xB - #define CE_REG_FR_SQS_G05__A 0x182002E #define CE_REG_FR_SQS_G05__W 8 #define CE_REG_FR_SQS_G05__M 0xFF #define CE_REG_FR_SQS_G05_INIT 0xB - #define CE_REG_FR_SQS_G06__A 0x182002F #define CE_REG_FR_SQS_G06__W 8 #define CE_REG_FR_SQS_G06__M 0xFF #define CE_REG_FR_SQS_G06_INIT 0xB - #define CE_REG_FR_SQS_G07__A 0x1820030 #define CE_REG_FR_SQS_G07__W 8 #define CE_REG_FR_SQS_G07__M 0xFF #define CE_REG_FR_SQS_G07_INIT 0xB - #define CE_REG_FR_SQS_G08__A 0x1820031 #define CE_REG_FR_SQS_G08__W 8 #define CE_REG_FR_SQS_G08__M 0xFF #define CE_REG_FR_SQS_G08_INIT 0xB - #define CE_REG_FR_SQS_G09__A 0x1820032 #define CE_REG_FR_SQS_G09__W 8 #define CE_REG_FR_SQS_G09__M 0xFF #define CE_REG_FR_SQS_G09_INIT 0xB - #define CE_REG_FR_SQS_G10__A 0x1820033 #define CE_REG_FR_SQS_G10__W 8 #define CE_REG_FR_SQS_G10__M 0xFF #define CE_REG_FR_SQS_G10_INIT 0xB - #define CE_REG_FR_SQS_G11__A 0x1820034 #define CE_REG_FR_SQS_G11__W 8 #define CE_REG_FR_SQS_G11__M 0xFF #define CE_REG_FR_SQS_G11_INIT 0xB - #define CE_REG_FR_SQS_G12__A 0x1820035 #define CE_REG_FR_SQS_G12__W 8 #define CE_REG_FR_SQS_G12__M 0xFF #define CE_REG_FR_SQS_G12_INIT 0x5 - #define CE_REG_FR_RIO_G00__A 0x1820036 #define CE_REG_FR_RIO_G00__W 9 #define CE_REG_FR_RIO_G00__M 0x1FF #define CE_REG_FR_RIO_G00_INIT 0x1FF - #define CE_REG_FR_RIO_G01__A 0x1820037 #define CE_REG_FR_RIO_G01__W 9 #define CE_REG_FR_RIO_G01__M 0x1FF #define CE_REG_FR_RIO_G01_INIT 0x190 - #define CE_REG_FR_RIO_G02__A 0x1820038 #define CE_REG_FR_RIO_G02__W 9 #define CE_REG_FR_RIO_G02__M 0x1FF #define CE_REG_FR_RIO_G02_INIT 0x10B - #define CE_REG_FR_RIO_G03__A 0x1820039 #define CE_REG_FR_RIO_G03__W 9 #define CE_REG_FR_RIO_G03__M 0x1FF #define CE_REG_FR_RIO_G03_INIT 0xC8 - #define CE_REG_FR_RIO_G04__A 0x182003A #define CE_REG_FR_RIO_G04__W 9 #define CE_REG_FR_RIO_G04__M 0x1FF #define CE_REG_FR_RIO_G04_INIT 0xA0 - #define CE_REG_FR_RIO_G05__A 0x182003B #define CE_REG_FR_RIO_G05__W 9 #define CE_REG_FR_RIO_G05__M 0x1FF #define CE_REG_FR_RIO_G05_INIT 0x85 - #define CE_REG_FR_RIO_G06__A 0x182003C #define CE_REG_FR_RIO_G06__W 9 #define CE_REG_FR_RIO_G06__M 0x1FF #define CE_REG_FR_RIO_G06_INIT 0x72 - #define CE_REG_FR_RIO_G07__A 0x182003D #define CE_REG_FR_RIO_G07__W 9 #define CE_REG_FR_RIO_G07__M 0x1FF #define CE_REG_FR_RIO_G07_INIT 0x64 - #define CE_REG_FR_RIO_G08__A 0x182003E #define CE_REG_FR_RIO_G08__W 9 #define CE_REG_FR_RIO_G08__M 0x1FF #define CE_REG_FR_RIO_G08_INIT 0x59 - #define CE_REG_FR_RIO_G09__A 0x182003F #define CE_REG_FR_RIO_G09__W 9 #define CE_REG_FR_RIO_G09__M 0x1FF #define CE_REG_FR_RIO_G09_INIT 0x50 - #define CE_REG_FR_RIO_G10__A 0x1820040 #define CE_REG_FR_RIO_G10__W 9 #define CE_REG_FR_RIO_G10__M 0x1FF #define CE_REG_FR_RIO_G10_INIT 0x49 - #define CE_REG_FR_MODE__A 0x1820041 #define CE_REG_FR_MODE__W 6 #define CE_REG_FR_MODE__M 0x3F @@ -4471,19 +3869,16 @@ extern "C" { #define CE_REG_FR_MODE_UPDATE_MODE__M 0x20 #define CE_REG_FR_MODE_INIT 0x3E - #define CE_REG_FR_SQS_TRH__A 0x1820042 #define CE_REG_FR_SQS_TRH__W 8 #define CE_REG_FR_SQS_TRH__M 0xFF #define CE_REG_FR_SQS_TRH_INIT 0x80 - #define CE_REG_FR_RIO_GAIN__A 0x1820043 #define CE_REG_FR_RIO_GAIN__W 3 #define CE_REG_FR_RIO_GAIN__M 0x7 #define CE_REG_FR_RIO_GAIN_INIT 0x2 - #define CE_REG_FR_BYPASS__A 0x1820044 #define CE_REG_FR_BYPASS__W 10 #define CE_REG_FR_BYPASS__M 0x3FF @@ -4501,54 +3896,37 @@ extern "C" { #define CE_REG_FR_BYPASS_TOTAL__M 0x200 #define CE_REG_FR_BYPASS_INIT 0x13B - #define CE_REG_FR_PM_SET__A 0x1820045 #define CE_REG_FR_PM_SET__W 4 #define CE_REG_FR_PM_SET__M 0xF #define CE_REG_FR_PM_SET_INIT 0x4 - #define CE_REG_FR_ERR_SH__A 0x1820046 #define CE_REG_FR_ERR_SH__W 4 #define CE_REG_FR_ERR_SH__M 0xF #define CE_REG_FR_ERR_SH_INIT 0x4 - #define CE_REG_FR_MAN_SH__A 0x1820047 #define CE_REG_FR_MAN_SH__W 4 #define CE_REG_FR_MAN_SH__M 0xF #define CE_REG_FR_MAN_SH_INIT 0x7 - #define CE_REG_FR_TAP_SH__A 0x1820048 #define CE_REG_FR_TAP_SH__W 3 #define CE_REG_FR_TAP_SH__M 0x7 #define CE_REG_FR_TAP_SH_INIT 0x3 - #define CE_REG_FR_CLIP__A 0x1820049 #define CE_REG_FR_CLIP__W 9 #define CE_REG_FR_CLIP__M 0x1FF #define CE_REG_FR_CLIP_INIT 0x49 - - #define CE_PB_RAM__A 0x1830000 - - #define CE_NE_RAM__A 0x1840000 - - - - #define EQ_SID 0xE - - - - #define EQ_COMM_EXEC__A 0x1C00000 #define EQ_COMM_EXEC__W 3 #define EQ_COMM_EXEC__M 0x7 @@ -4581,11 +3959,6 @@ extern "C" { #define EQ_COMM_INT_MSK__W 16 #define EQ_COMM_INT_MSK__M 0xFFFF - - - - - #define EQ_REG_COMM_EXEC__A 0x1C10000 #define EQ_REG_COMM_EXEC__W 3 #define EQ_REG_COMM_EXEC__M 0x7 @@ -4628,7 +4001,6 @@ extern "C" { #define EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 #define EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 - #define EQ_REG_COMM_SERVICE0__A 0x1C10003 #define EQ_REG_COMM_SERVICE0__W 10 #define EQ_REG_COMM_SERVICE0__M 0x3FF @@ -4647,7 +4019,6 @@ extern "C" { #define EQ_REG_COMM_INT_STA_ERR_RDY__W 1 #define EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 - #define EQ_REG_COMM_INT_MSK__A 0x1C10008 #define EQ_REG_COMM_INT_MSK__W 2 #define EQ_REG_COMM_INT_MSK__M 0x3 @@ -4658,7 +4029,6 @@ extern "C" { #define EQ_REG_COMM_INT_MSK_MER_RDY__W 1 #define EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 - #define EQ_REG_IS_MODE__A 0x1C10014 #define EQ_REG_IS_MODE__W 4 #define EQ_REG_IS_MODE__M 0xF @@ -4676,25 +4046,21 @@ extern "C" { #define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 #define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 - #define EQ_REG_IS_GAIN_MAN__A 0x1C10015 #define EQ_REG_IS_GAIN_MAN__W 10 #define EQ_REG_IS_GAIN_MAN__M 0x3FF #define EQ_REG_IS_GAIN_MAN_INIT 0x0 - #define EQ_REG_IS_GAIN_EXP__A 0x1C10016 #define EQ_REG_IS_GAIN_EXP__W 5 #define EQ_REG_IS_GAIN_EXP__M 0x1F #define EQ_REG_IS_GAIN_EXP_INIT 0x0 - #define EQ_REG_IS_CLIP_EXP__A 0x1C10017 #define EQ_REG_IS_CLIP_EXP__W 5 #define EQ_REG_IS_CLIP_EXP__M 0x1F #define EQ_REG_IS_CLIP_EXP_INIT 0x0 - #define EQ_REG_DV_MODE__A 0x1C1001E #define EQ_REG_DV_MODE__W 4 #define EQ_REG_DV_MODE__M 0xF @@ -4724,7 +4090,6 @@ extern "C" { #define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 #define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 - #define EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F #define EQ_REG_DV_POS_CLIP_DAT__W 16 #define EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF @@ -4782,31 +4147,26 @@ extern "C" { #define EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 #define EQ_REG_SN_MODE_MODE_7_STATIC 0x80 - #define EQ_REG_SN_PFIX__A 0x1C10029 #define EQ_REG_SN_PFIX__W 8 #define EQ_REG_SN_PFIX__M 0xFF #define EQ_REG_SN_PFIX_INIT 0x0 - #define EQ_REG_SN_CEGAIN__A 0x1C1002A #define EQ_REG_SN_CEGAIN__W 8 #define EQ_REG_SN_CEGAIN__M 0xFF #define EQ_REG_SN_CEGAIN_INIT 0x0 - #define EQ_REG_SN_OFFSET__A 0x1C1002B #define EQ_REG_SN_OFFSET__W 6 #define EQ_REG_SN_OFFSET__M 0x3F #define EQ_REG_SN_OFFSET_INIT 0x0 - #define EQ_REG_SN_NULLIFY__A 0x1C1002C #define EQ_REG_SN_NULLIFY__W 6 #define EQ_REG_SN_NULLIFY__M 0x3F #define EQ_REG_SN_NULLIFY_INIT 0x0 - #define EQ_REG_SN_SQUASH__A 0x1C1002D #define EQ_REG_SN_SQUASH__W 10 #define EQ_REG_SN_SQUASH__M 0x3FF @@ -4820,9 +4180,6 @@ extern "C" { #define EQ_REG_SN_SQUASH_EXP__W 4 #define EQ_REG_SN_SQUASH_EXP__M 0x3C0 - - - #define EQ_REG_RC_SEL_CAR__A 0x1C10032 #define EQ_REG_RC_SEL_CAR__W 6 #define EQ_REG_RC_SEL_CAR__M 0x3F @@ -4855,7 +4212,6 @@ extern "C" { #define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 #define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 - #define EQ_REG_RC_STS__A 0x1C10033 #define EQ_REG_RC_STS__W 12 #define EQ_REG_RC_STS__M 0xFFF @@ -4882,45 +4238,36 @@ extern "C" { #define EQ_REG_RC_STS_OVERFLOW_NO 0x0 #define EQ_REG_RC_STS_OVERFLOW_YES 0x800 - #define EQ_REG_OT_CONST__A 0x1C10046 #define EQ_REG_OT_CONST__W 2 #define EQ_REG_OT_CONST__M 0x3 #define EQ_REG_OT_CONST_INIT 0x0 - #define EQ_REG_OT_ALPHA__A 0x1C10047 #define EQ_REG_OT_ALPHA__W 2 #define EQ_REG_OT_ALPHA__M 0x3 #define EQ_REG_OT_ALPHA_INIT 0x0 - #define EQ_REG_OT_QNT_THRES0__A 0x1C10048 #define EQ_REG_OT_QNT_THRES0__W 5 #define EQ_REG_OT_QNT_THRES0__M 0x1F #define EQ_REG_OT_QNT_THRES0_INIT 0x0 - #define EQ_REG_OT_QNT_THRES1__A 0x1C10049 #define EQ_REG_OT_QNT_THRES1__W 5 #define EQ_REG_OT_QNT_THRES1__M 0x1F #define EQ_REG_OT_QNT_THRES1_INIT 0x0 - #define EQ_REG_OT_CSI_STEP__A 0x1C1004A #define EQ_REG_OT_CSI_STEP__W 4 #define EQ_REG_OT_CSI_STEP__M 0xF #define EQ_REG_OT_CSI_STEP_INIT 0x0 - #define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B #define EQ_REG_OT_CSI_OFFSET__W 7 #define EQ_REG_OT_CSI_OFFSET__M 0x7F #define EQ_REG_OT_CSI_OFFSET_INIT 0x0 - - - #define EQ_REG_TD_TPS_INIT__A 0x1C10050 #define EQ_REG_TD_TPS_INIT__W 1 #define EQ_REG_TD_TPS_INIT__M 0x1 @@ -4928,7 +4275,6 @@ extern "C" { #define EQ_REG_TD_TPS_INIT_POS 0x0 #define EQ_REG_TD_TPS_INIT_NEG 0x1 - #define EQ_REG_TD_TPS_SYNC__A 0x1C10051 #define EQ_REG_TD_TPS_SYNC__W 16 #define EQ_REG_TD_TPS_SYNC__M 0xFFFF @@ -4936,7 +4282,6 @@ extern "C" { #define EQ_REG_TD_TPS_SYNC_ODD 0x35EE #define EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 - #define EQ_REG_TD_TPS_LEN__A 0x1C10052 #define EQ_REG_TD_TPS_LEN__W 6 #define EQ_REG_TD_TPS_LEN__M 0x3F @@ -4944,7 +4289,6 @@ extern "C" { #define EQ_REG_TD_TPS_LEN_DEF 0x17 #define EQ_REG_TD_TPS_LEN_ID_SUP 0x1F - #define EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 #define EQ_REG_TD_TPS_FRM_NMB__W 2 #define EQ_REG_TD_TPS_FRM_NMB__M 0x3 @@ -4954,7 +4298,6 @@ extern "C" { #define EQ_REG_TD_TPS_FRM_NMB_3 0x2 #define EQ_REG_TD_TPS_FRM_NMB_4 0x3 - #define EQ_REG_TD_TPS_CONST__A 0x1C10054 #define EQ_REG_TD_TPS_CONST__W 2 #define EQ_REG_TD_TPS_CONST__M 0x3 @@ -4963,7 +4306,6 @@ extern "C" { #define EQ_REG_TD_TPS_CONST_16QAM 0x1 #define EQ_REG_TD_TPS_CONST_64QAM 0x2 - #define EQ_REG_TD_TPS_HINFO__A 0x1C10055 #define EQ_REG_TD_TPS_HINFO__W 3 #define EQ_REG_TD_TPS_HINFO__M 0x7 @@ -4973,7 +4315,6 @@ extern "C" { #define EQ_REG_TD_TPS_HINFO_H2 0x2 #define EQ_REG_TD_TPS_HINFO_H4 0x3 - #define EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 #define EQ_REG_TD_TPS_CODE_HP__W 3 #define EQ_REG_TD_TPS_CODE_HP__M 0x7 @@ -4984,7 +4325,6 @@ extern "C" { #define EQ_REG_TD_TPS_CODE_HP_5_6 0x3 #define EQ_REG_TD_TPS_CODE_HP_7_8 0x4 - #define EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 #define EQ_REG_TD_TPS_CODE_LP__W 3 #define EQ_REG_TD_TPS_CODE_LP__M 0x7 @@ -4995,7 +4335,6 @@ extern "C" { #define EQ_REG_TD_TPS_CODE_LP_5_6 0x3 #define EQ_REG_TD_TPS_CODE_LP_7_8 0x4 - #define EQ_REG_TD_TPS_GUARD__A 0x1C10058 #define EQ_REG_TD_TPS_GUARD__W 2 #define EQ_REG_TD_TPS_GUARD__M 0x3 @@ -5005,7 +4344,6 @@ extern "C" { #define EQ_REG_TD_TPS_GUARD_08 0x2 #define EQ_REG_TD_TPS_GUARD_04 0x3 - #define EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 #define EQ_REG_TD_TPS_TR_MODE__W 2 #define EQ_REG_TD_TPS_TR_MODE__M 0x3 @@ -5013,68 +4351,51 @@ extern "C" { #define EQ_REG_TD_TPS_TR_MODE_2K 0x0 #define EQ_REG_TD_TPS_TR_MODE_8K 0x1 - #define EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A #define EQ_REG_TD_TPS_CELL_ID_HI__W 8 #define EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF #define EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 - #define EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B #define EQ_REG_TD_TPS_CELL_ID_LO__W 8 #define EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF #define EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 - #define EQ_REG_TD_TPS_RSV__A 0x1C1005C #define EQ_REG_TD_TPS_RSV__W 6 #define EQ_REG_TD_TPS_RSV__M 0x3F #define EQ_REG_TD_TPS_RSV_INIT 0x0 - #define EQ_REG_TD_TPS_BCH__A 0x1C1005D #define EQ_REG_TD_TPS_BCH__W 14 #define EQ_REG_TD_TPS_BCH__M 0x3FFF #define EQ_REG_TD_TPS_BCH_INIT 0x0 - #define EQ_REG_TD_SQR_ERR_I__A 0x1C1005E #define EQ_REG_TD_SQR_ERR_I__W 16 #define EQ_REG_TD_SQR_ERR_I__M 0xFFFF #define EQ_REG_TD_SQR_ERR_I_INIT 0x0 - #define EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F #define EQ_REG_TD_SQR_ERR_Q__W 16 #define EQ_REG_TD_SQR_ERR_Q__M 0xFFFF #define EQ_REG_TD_SQR_ERR_Q_INIT 0x0 - #define EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 #define EQ_REG_TD_SQR_ERR_EXP__W 4 #define EQ_REG_TD_SQR_ERR_EXP__M 0xF #define EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 - #define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 #define EQ_REG_TD_REQ_SMB_CNT__W 16 #define EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF #define EQ_REG_TD_REQ_SMB_CNT_INIT 0x0 - #define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 #define EQ_REG_TD_TPS_PWR_OFS__W 16 #define EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF #define EQ_REG_TD_TPS_PWR_OFS_INIT 0x0 - - - - - - - - #define EC_COMM_EXEC__A 0x2000000 #define EC_COMM_EXEC__W 3 #define EC_COMM_EXEC__M 0x7 @@ -5107,16 +4428,8 @@ extern "C" { #define EC_COMM_INT_MSK__W 16 #define EC_COMM_INT_MSK__M 0xFFFF - - - - #define EC_SB_SID 0x16 - - - - #define EC_SB_REG_COMM_EXEC__A 0x2010000 #define EC_SB_REG_COMM_EXEC__W 3 #define EC_SB_REG_COMM_EXEC__M 0x7 @@ -5144,7 +4457,6 @@ extern "C" { #define EC_SB_REG_COMM_MB_OBS_OFF 0x0 #define EC_SB_REG_COMM_MB_OBS_ON 0x2 - #define EC_SB_REG_TR_MODE__A 0x2010010 #define EC_SB_REG_TR_MODE__W 1 #define EC_SB_REG_TR_MODE__M 0x1 @@ -5152,7 +4464,6 @@ extern "C" { #define EC_SB_REG_TR_MODE_8K 0x0 #define EC_SB_REG_TR_MODE_2K 0x1 - #define EC_SB_REG_CONST__A 0x2010011 #define EC_SB_REG_CONST__W 2 #define EC_SB_REG_CONST__M 0x3 @@ -5161,7 +4472,6 @@ extern "C" { #define EC_SB_REG_CONST_16QAM 0x1 #define EC_SB_REG_CONST_64QAM 0x2 - #define EC_SB_REG_ALPHA__A 0x2010012 #define EC_SB_REG_ALPHA__W 3 #define EC_SB_REG_ALPHA__M 0x7 @@ -5176,7 +4486,6 @@ extern "C" { #define EC_SB_REG_ALPHA_H4 0x3 - #define EC_SB_REG_PRIOR__A 0x2010013 #define EC_SB_REG_PRIOR__W 1 #define EC_SB_REG_PRIOR__M 0x1 @@ -5184,7 +4493,6 @@ extern "C" { #define EC_SB_REG_PRIOR_HI 0x0 #define EC_SB_REG_PRIOR_LO 0x1 - #define EC_SB_REG_CSI_HI__A 0x2010014 #define EC_SB_REG_CSI_HI__W 5 #define EC_SB_REG_CSI_HI__M 0x1F @@ -5193,7 +4501,6 @@ extern "C" { #define EC_SB_REG_CSI_HI_MIN 0x0 #define EC_SB_REG_CSI_HI_TAG 0x0 - #define EC_SB_REG_CSI_LO__A 0x2010015 #define EC_SB_REG_CSI_LO__W 5 #define EC_SB_REG_CSI_LO__M 0x1F @@ -5202,14 +4509,12 @@ extern "C" { #define EC_SB_REG_CSI_LO_MIN 0x0 #define EC_SB_REG_CSI_LO_TAG 0x0 - #define EC_SB_REG_SMB_TGL__A 0x2010016 #define EC_SB_REG_SMB_TGL__W 1 #define EC_SB_REG_SMB_TGL__M 0x1 #define EC_SB_REG_SMB_TGL_OFF 0x0 #define EC_SB_REG_SMB_TGL_ON 0x1 - #define EC_SB_REG_SNR_HI__A 0x2010017 #define EC_SB_REG_SNR_HI__W 8 #define EC_SB_REG_SNR_HI__M 0xFF @@ -5218,7 +4523,6 @@ extern "C" { #define EC_SB_REG_SNR_HI_MIN 0x0 #define EC_SB_REG_SNR_HI_TAG 0x0 - #define EC_SB_REG_SNR_MID__A 0x2010018 #define EC_SB_REG_SNR_MID__W 8 #define EC_SB_REG_SNR_MID__M 0xFF @@ -5227,7 +4531,6 @@ extern "C" { #define EC_SB_REG_SNR_MID_MIN 0x0 #define EC_SB_REG_SNR_MID_TAG 0x0 - #define EC_SB_REG_SNR_LO__A 0x2010019 #define EC_SB_REG_SNR_LO__W 8 #define EC_SB_REG_SNR_LO__M 0xFF @@ -5236,28 +4539,24 @@ extern "C" { #define EC_SB_REG_SNR_LO_MIN 0x0 #define EC_SB_REG_SNR_LO_TAG 0x0 - #define EC_SB_REG_SCALE_MSB__A 0x201001A #define EC_SB_REG_SCALE_MSB__W 6 #define EC_SB_REG_SCALE_MSB__M 0x3F #define EC_SB_REG_SCALE_MSB_INIT 0x30 #define EC_SB_REG_SCALE_MSB_MAX 0x3F - #define EC_SB_REG_SCALE_BIT2__A 0x201001B #define EC_SB_REG_SCALE_BIT2__W 6 #define EC_SB_REG_SCALE_BIT2__M 0x3F #define EC_SB_REG_SCALE_BIT2_INIT 0x20 #define EC_SB_REG_SCALE_BIT2_MAX 0x3F - #define EC_SB_REG_SCALE_LSB__A 0x201001C #define EC_SB_REG_SCALE_LSB__W 6 #define EC_SB_REG_SCALE_LSB__M 0x3F #define EC_SB_REG_SCALE_LSB_INIT 0x10 #define EC_SB_REG_SCALE_LSB_MAX 0x3F - #define EC_SB_REG_CSI_OFS__A 0x201001D #define EC_SB_REG_CSI_OFS__W 4 #define EC_SB_REG_CSI_OFS__M 0xF @@ -5271,28 +4570,14 @@ extern "C" { #define EC_SB_REG_CSI_OFS_DIS_ENA 0x0 #define EC_SB_REG_CSI_OFS_DIS_DIS 0x8 - - #define EC_SB_SD_RAM__A 0x2020000 - - #define EC_SB_BD0_RAM__A 0x2030000 - - #define EC_SB_BD1_RAM__A 0x2040000 - - - - #define EC_VD_SID 0x17 - - - - #define EC_VD_REG_COMM_EXEC__A 0x2090000 #define EC_VD_REG_COMM_EXEC__W 3 #define EC_VD_REG_COMM_EXEC__M 0x7 @@ -5340,7 +4625,6 @@ extern "C" { #define EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 #define EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 - #define EC_VD_REG_FORCE__A 0x2090010 #define EC_VD_REG_FORCE__W 2 #define EC_VD_REG_FORCE__M 0x3 @@ -5350,7 +4634,6 @@ extern "C" { #define EC_VD_REG_FORCE_FORCED 0x2 #define EC_VD_REG_FORCE_FIXED 0x3 - #define EC_VD_REG_SET_CODERATE__A 0x2090011 #define EC_VD_REG_SET_CODERATE__W 3 #define EC_VD_REG_SET_CODERATE__M 0x7 @@ -5361,19 +4644,16 @@ extern "C" { #define EC_VD_REG_SET_CODERATE_C5_6 0x3 #define EC_VD_REG_SET_CODERATE_C7_8 0x4 - #define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 #define EC_VD_REG_REQ_SMB_CNT__W 16 #define EC_VD_REG_REQ_SMB_CNT__M 0xFFFF #define EC_VD_REG_REQ_SMB_CNT_INIT 0x0 - #define EC_VD_REG_REQ_BIT_CNT__A 0x2090013 #define EC_VD_REG_REQ_BIT_CNT__W 16 #define EC_VD_REG_REQ_BIT_CNT__M 0xFFFF #define EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF - #define EC_VD_REG_RLK_ENA__A 0x2090014 #define EC_VD_REG_RLK_ENA__W 1 #define EC_VD_REG_RLK_ENA__M 0x1 @@ -5381,7 +4661,6 @@ extern "C" { #define EC_VD_REG_RLK_ENA_OFF 0x0 #define EC_VD_REG_RLK_ENA_ON 0x1 - #define EC_VD_REG_VAL__A 0x2090015 #define EC_VD_REG_VAL__W 2 #define EC_VD_REG_VAL__M 0x3 @@ -5389,7 +4668,6 @@ extern "C" { #define EC_VD_REG_VAL_CODE 0x1 #define EC_VD_REG_VAL_CNT 0x2 - #define EC_VD_REG_GET_CODERATE__A 0x2090016 #define EC_VD_REG_GET_CODERATE__W 3 #define EC_VD_REG_GET_CODERATE__M 0x7 @@ -5400,19 +4678,16 @@ extern "C" { #define EC_VD_REG_GET_CODERATE_C5_6 0x3 #define EC_VD_REG_GET_CODERATE_C7_8 0x4 - #define EC_VD_REG_ERR_BIT_CNT__A 0x2090017 #define EC_VD_REG_ERR_BIT_CNT__W 16 #define EC_VD_REG_ERR_BIT_CNT__M 0xFFFF #define EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF - #define EC_VD_REG_IN_BIT_CNT__A 0x2090018 #define EC_VD_REG_IN_BIT_CNT__W 16 #define EC_VD_REG_IN_BIT_CNT__M 0xFFFF #define EC_VD_REG_IN_BIT_CNT_INIT 0x0 - #define EC_VD_REG_STS__A 0x2090019 #define EC_VD_REG_STS__W 1 #define EC_VD_REG_STS__M 0x1 @@ -5420,43 +4695,23 @@ extern "C" { #define EC_VD_REG_STS_NO_LOCK 0x0 #define EC_VD_REG_STS_IN_LOCK 0x1 - #define EC_VD_REG_RLK_CNT__A 0x209001A #define EC_VD_REG_RLK_CNT__W 16 #define EC_VD_REG_RLK_CNT__M 0xFFFF #define EC_VD_REG_RLK_CNT_INIT 0x0 - - #define EC_VD_TB0_RAM__A 0x20A0000 - - #define EC_VD_TB1_RAM__A 0x20B0000 - - #define EC_VD_TB2_RAM__A 0x20C0000 - - #define EC_VD_TB3_RAM__A 0x20D0000 - - #define EC_VD_RE_RAM__A 0x2100000 - - - - #define EC_OD_SID 0x18 - - - - - #define EC_OD_REG_COMM_EXEC__A 0x2110000 #define EC_OD_REG_COMM_EXEC__W 3 #define EC_OD_REG_COMM_EXEC__M 0x7 @@ -5468,7 +4723,6 @@ extern "C" { #define EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 #define EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 - #define EC_OD_REG_COMM_MB__A 0x2110002 #define EC_OD_REG_COMM_MB__W 3 #define EC_OD_REG_COMM_MB__M 0x7 @@ -5508,7 +4762,6 @@ extern "C" { #define EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 #define EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 - #define EC_OD_REG_COMM_INT_MSK__A 0x2110008 #define EC_OD_REG_COMM_INT_MSK__W 2 #define EC_OD_REG_COMM_INT_MSK__M 0x3 @@ -5519,7 +4772,6 @@ extern "C" { #define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 #define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 - #define EC_OD_REG_SYNC__A 0x2110010 #define EC_OD_REG_SYNC__W 12 #define EC_OD_REG_SYNC__M 0xFFF @@ -5533,25 +4785,14 @@ extern "C" { #define EC_OD_REG_SYNC_OUT_SYNC__W 3 #define EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 - #define EC_OD_REG_NOSYNC__A 0x2110011 #define EC_OD_REG_NOSYNC__W 8 #define EC_OD_REG_NOSYNC__M 0xFF - - #define EC_OD_DEINT_RAM__A 0x2120000 - - - - #define EC_RS_SID 0x19 - - - - #define EC_RS_REG_COMM_EXEC__A 0x2130000 #define EC_RS_REG_COMM_EXEC__W 3 #define EC_RS_REG_COMM_EXEC__M 0x7 @@ -5599,58 +4840,41 @@ extern "C" { #define EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 #define EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 - #define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 #define EC_RS_REG_REQ_PCK_CNT__W 16 #define EC_RS_REG_REQ_PCK_CNT__M 0xFFFF #define EC_RS_REG_REQ_PCK_CNT_INIT 0xFF - #define EC_RS_REG_VAL__A 0x2130011 #define EC_RS_REG_VAL__W 1 #define EC_RS_REG_VAL__M 0x1 #define EC_RS_REG_VAL_INIT 0x0 #define EC_RS_REG_VAL_PCK 0x1 - #define EC_RS_REG_ERR_PCK_CNT__A 0x2130012 #define EC_RS_REG_ERR_PCK_CNT__W 16 #define EC_RS_REG_ERR_PCK_CNT__M 0xFFFF #define EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF - #define EC_RS_REG_ERR_SMB_CNT__A 0x2130013 #define EC_RS_REG_ERR_SMB_CNT__W 16 #define EC_RS_REG_ERR_SMB_CNT__M 0xFFFF #define EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF - #define EC_RS_REG_ERR_BIT_CNT__A 0x2130014 #define EC_RS_REG_ERR_BIT_CNT__W 16 #define EC_RS_REG_ERR_BIT_CNT__M 0xFFFF #define EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF - #define EC_RS_REG_IN_PCK_CNT__A 0x2130015 #define EC_RS_REG_IN_PCK_CNT__W 16 #define EC_RS_REG_IN_PCK_CNT__M 0xFFFF #define EC_RS_REG_IN_PCK_CNT_INIT 0x0 - - #define EC_RS_EC_RAM__A 0x2140000 - - - - #define EC_OC_SID 0x1A - - - - - #define EC_OC_REG_COMM_EXEC__A 0x2150000 #define EC_OC_REG_COMM_EXEC__W 3 #define EC_OC_REG_COMM_EXEC__M 0x7 @@ -5680,7 +4904,6 @@ extern "C" { #define EC_OC_REG_COMM_MB_OBS_OFF 0x0 #define EC_OC_REG_COMM_MB_OBS_ON 0x2 - #define EC_OC_REG_COMM_SERVICE0__A 0x2150003 #define EC_OC_REG_COMM_SERVICE0__W 10 #define EC_OC_REG_COMM_SERVICE0__M 0x3FF @@ -5711,7 +4934,6 @@ extern "C" { #define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 #define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 - #define EC_OC_REG_COMM_INT_MSK__A 0x2150008 #define EC_OC_REG_COMM_INT_MSK__W 6 #define EC_OC_REG_COMM_INT_MSK__M 0x3F @@ -5734,7 +4956,6 @@ extern "C" { #define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 #define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 - #define EC_OC_REG_OC_MODE_LOP__A 0x2150010 #define EC_OC_REG_OC_MODE_LOP__W 16 #define EC_OC_REG_OC_MODE_LOP__M 0xFFFF @@ -5824,7 +5045,6 @@ extern "C" { #define EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 #define EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 - #define EC_OC_REG_OC_MODE_HIP__A 0x2150011 #define EC_OC_REG_OC_MODE_HIP__W 14 #define EC_OC_REG_OC_MODE_HIP__M 0x3FFF @@ -5914,7 +5134,6 @@ extern "C" { #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 #define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 - #define EC_OC_REG_OC_MPG_SIO__A 0x2150012 #define EC_OC_REG_OC_MPG_SIO__W 12 #define EC_OC_REG_OC_MPG_SIO__M 0xFFF @@ -5992,7 +5211,6 @@ extern "C" { #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 #define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 - #define EC_OC_REG_OC_MON_SIO__A 0x2150013 #define EC_OC_REG_OC_MON_SIO__W 12 #define EC_OC_REG_OC_MON_SIO__M 0xFFF @@ -6070,19 +5288,16 @@ extern "C" { #define EC_OC_REG_OC_MON_SIO_MON_SIO_11_OUTPUT 0x0 #define EC_OC_REG_OC_MON_SIO_MON_SIO_11_INPUT 0x800 - #define EC_OC_REG_DTO_INC_LOP__A 0x2150014 #define EC_OC_REG_DTO_INC_LOP__W 16 #define EC_OC_REG_DTO_INC_LOP__M 0xFFFF #define EC_OC_REG_DTO_INC_LOP_INIT 0x0 - #define EC_OC_REG_DTO_INC_HIP__A 0x2150015 #define EC_OC_REG_DTO_INC_HIP__W 8 #define EC_OC_REG_DTO_INC_HIP__M 0xFF #define EC_OC_REG_DTO_INC_HIP_INIT 0x0 - #define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 #define EC_OC_REG_SNC_ISC_LVL__W 12 #define EC_OC_REG_SNC_ISC_LVL__M 0xFFF @@ -6100,13 +5315,11 @@ extern "C" { #define EC_OC_REG_SNC_ISC_LVL_NSC__W 4 #define EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 - #define EC_OC_REG_SNC_NSC_LVL__A 0x2150017 #define EC_OC_REG_SNC_NSC_LVL__W 8 #define EC_OC_REG_SNC_NSC_LVL__M 0xFF #define EC_OC_REG_SNC_NSC_LVL_INIT 0x0 - #define EC_OC_REG_SNC_SNC_MODE__A 0x2150019 #define EC_OC_REG_SNC_SNC_MODE__W 2 #define EC_OC_REG_SNC_SNC_MODE__M 0x3 @@ -6114,7 +5327,6 @@ extern "C" { #define EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 #define EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 - #define EC_OC_REG_SNC_PCK_NMB__A 0x215001A #define EC_OC_REG_SNC_PCK_NMB__W 16 #define EC_OC_REG_SNC_PCK_NMB__M 0xFFFF @@ -6136,49 +5348,41 @@ extern "C" { #define EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 #define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 - #define EC_OC_REG_TMD_TOP_CNT__A 0x215001E #define EC_OC_REG_TMD_TOP_CNT__W 10 #define EC_OC_REG_TMD_TOP_CNT__M 0x3FF #define EC_OC_REG_TMD_TOP_CNT_INIT 0x0 - #define EC_OC_REG_TMD_HIL_MAR__A 0x215001F #define EC_OC_REG_TMD_HIL_MAR__W 10 #define EC_OC_REG_TMD_HIL_MAR__M 0x3FF #define EC_OC_REG_TMD_HIL_MAR_INIT 0x0 - #define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 #define EC_OC_REG_TMD_LOL_MAR__W 10 #define EC_OC_REG_TMD_LOL_MAR__M 0x3FF #define EC_OC_REG_TMD_LOL_MAR_INIT 0x0 - #define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 #define EC_OC_REG_TMD_CUR_CNT__W 4 #define EC_OC_REG_TMD_CUR_CNT__M 0xF #define EC_OC_REG_TMD_CUR_CNT_INIT 0x0 - #define EC_OC_REG_TMD_IUR_CNT__A 0x2150022 #define EC_OC_REG_TMD_IUR_CNT__W 4 #define EC_OC_REG_TMD_IUR_CNT__M 0xF #define EC_OC_REG_TMD_IUR_CNT_INIT 0x0 - #define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 #define EC_OC_REG_AVR_ASH_CNT__W 4 #define EC_OC_REG_AVR_ASH_CNT__M 0xF #define EC_OC_REG_AVR_ASH_CNT_INIT 0x0 - #define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 #define EC_OC_REG_AVR_BSH_CNT__W 4 #define EC_OC_REG_AVR_BSH_CNT__M 0xF #define EC_OC_REG_AVR_BSH_CNT_INIT 0x0 - #define EC_OC_REG_AVR_AVE_LOP__A 0x2150025 #define EC_OC_REG_AVR_AVE_LOP__W 16 #define EC_OC_REG_AVR_AVE_LOP__M 0xFFFF @@ -6210,43 +5414,36 @@ extern "C" { #define EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 #define EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 - #define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 #define EC_OC_REG_RCN_CRA_LOP__W 16 #define EC_OC_REG_RCN_CRA_LOP__M 0xFFFF #define EC_OC_REG_RCN_CRA_LOP_INIT 0x0 - #define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 #define EC_OC_REG_RCN_CRA_HIP__W 8 #define EC_OC_REG_RCN_CRA_HIP__M 0xFF #define EC_OC_REG_RCN_CRA_HIP_INIT 0x0 - #define EC_OC_REG_RCN_CST_LOP__A 0x215002A #define EC_OC_REG_RCN_CST_LOP__W 16 #define EC_OC_REG_RCN_CST_LOP__M 0xFFFF #define EC_OC_REG_RCN_CST_LOP_INIT 0x0 - #define EC_OC_REG_RCN_CST_HIP__A 0x215002B #define EC_OC_REG_RCN_CST_HIP__W 8 #define EC_OC_REG_RCN_CST_HIP__M 0xFF #define EC_OC_REG_RCN_CST_HIP_INIT 0x0 - #define EC_OC_REG_RCN_SET_LVL__A 0x215002C #define EC_OC_REG_RCN_SET_LVL__W 9 #define EC_OC_REG_RCN_SET_LVL__M 0x1FF #define EC_OC_REG_RCN_SET_LVL_INIT 0x0 - #define EC_OC_REG_RCN_GAI_LVL__A 0x215002D #define EC_OC_REG_RCN_GAI_LVL__W 4 #define EC_OC_REG_RCN_GAI_LVL__M 0xF #define EC_OC_REG_RCN_GAI_LVL_INIT 0x0 - #define EC_OC_REG_RCN_DRA_LOP__A 0x215002E #define EC_OC_REG_RCN_DRA_LOP__W 16 #define EC_OC_REG_RCN_DRA_LOP__M 0xFFFF @@ -6268,13 +5465,11 @@ extern "C" { #define EC_OC_REG_RCN_CLP_LOP__M 0xFFFF #define EC_OC_REG_RCN_CLP_LOP_INIT 0xFFFF - #define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 #define EC_OC_REG_RCN_CLP_HIP__W 8 #define EC_OC_REG_RCN_CLP_HIP__M 0xFF #define EC_OC_REG_RCN_CLP_HIP_INIT 0xFF - #define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 #define EC_OC_REG_RCN_MAP_LOP__W 16 #define EC_OC_REG_RCN_MAP_LOP__M 0xFFFF @@ -6360,7 +5555,6 @@ extern "C" { #define EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 #define EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 - #define EC_OC_REG_OCR_MPG_WRI__A 0x2150037 #define EC_OC_REG_OCR_MPG_WRI__W 12 #define EC_OC_REG_OCR_MPG_WRI__M 0xFFF @@ -6426,7 +5620,6 @@ extern "C" { #define EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 #define EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 - #define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 #define EC_OC_REG_OCR_MPG_USR_DAT__W 12 #define EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF @@ -6508,7 +5701,6 @@ extern "C" { #define EC_OC_REG_OCR_MON_UOS_CLK_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 - #define EC_OC_REG_OCR_MON_WRI__A 0x215003A #define EC_OC_REG_OCR_MON_WRI__W 12 #define EC_OC_REG_OCR_MON_WRI__M 0xFFF @@ -6574,7 +5766,6 @@ extern "C" { #define EC_OC_REG_OCR_MON_WRI_CLK_DISABLE 0x0 #define EC_OC_REG_OCR_MON_WRI_CLK_ENABLE 0x800 - #define EC_OC_REG_OCR_MON_USR_DAT__A 0x215003B #define EC_OC_REG_OCR_MON_USR_DAT__W 12 #define EC_OC_REG_OCR_MON_USR_DAT__M 0xFFF @@ -6584,13 +5775,11 @@ extern "C" { #define EC_OC_REG_OCR_MON_CNT__M 0x3FFF #define EC_OC_REG_OCR_MON_CNT_INIT 0x0 - #define EC_OC_REG_OCR_MON_RDX__A 0x215003D #define EC_OC_REG_OCR_MON_RDX__W 1 #define EC_OC_REG_OCR_MON_RDX__M 0x1 #define EC_OC_REG_OCR_MON_RDX_INIT 0x0 - #define EC_OC_REG_OCR_MON_RD0__A 0x215003E #define EC_OC_REG_OCR_MON_RD0__W 10 #define EC_OC_REG_OCR_MON_RD0__M 0x3FF @@ -6620,32 +5809,20 @@ extern "C" { #define EC_OC_REG_OCR_INV_MON__M 0xFFF #define EC_OC_REG_OCR_INV_MON_INIT 0x0 - #define EC_OC_REG_IPR_INV_MPG__A 0x2150045 #define EC_OC_REG_IPR_INV_MPG__W 12 #define EC_OC_REG_IPR_INV_MPG__M 0xFFF #define EC_OC_REG_IPR_INV_MPG_INIT 0x0 - #define EC_OC_REG_IPR_MSR_SNC__A 0x2150046 #define EC_OC_REG_IPR_MSR_SNC__W 6 #define EC_OC_REG_IPR_MSR_SNC__M 0x3F #define EC_OC_REG_IPR_MSR_SNC_INIT 0x0 - - #define EC_OC_RAM__A 0x2160000 - - - - #define CC_SID 0x1B - - - - #define CC_COMM_EXEC__A 0x2400000 #define CC_COMM_EXEC__W 3 #define CC_COMM_EXEC__M 0x7 @@ -6678,12 +5855,6 @@ extern "C" { #define CC_COMM_INT_MSK__W 16 #define CC_COMM_INT_MSK__M 0xFFFF - - - - - - #define CC_REG_COMM_EXEC__A 0x2410000 #define CC_REG_COMM_EXEC__W 3 #define CC_REG_COMM_EXEC__M 0x7 @@ -6723,7 +5894,6 @@ extern "C" { #define CC_REG_OSC_MODE_M20 0x1 #define CC_REG_OSC_MODE_M48 0x2 - #define CC_REG_PLL_MODE__A 0x2410011 #define CC_REG_PLL_MODE__W 6 #define CC_REG_PLL_MODE__M 0x3F @@ -6749,7 +5919,6 @@ extern "C" { #define CC_REG_PLL_MODE_OUT_EN_OFF 0x0 #define CC_REG_PLL_MODE_OUT_EN_ON 0x20 - #define CC_REG_REF_DIVIDE__A 0x2410012 #define CC_REG_REF_DIVIDE__W 4 #define CC_REG_REF_DIVIDE__M 0xF @@ -6766,7 +5935,6 @@ extern "C" { #define CC_REG_REF_DIVIDE_D09 0x9 #define CC_REG_REF_DIVIDE_D10 0xA - #define CC_REG_REF_DELAY__A 0x2410013 #define CC_REG_REF_DELAY__W 3 #define CC_REG_REF_DELAY__M 0x7 @@ -6783,13 +5951,11 @@ extern "C" { #define CC_REG_REF_DELAY_DELAY_DEL_6 0x4 #define CC_REG_REF_DELAY_DELAY_DEL_9 0x6 - #define CC_REG_CLK_DELAY__A 0x2410014 #define CC_REG_CLK_DELAY__W 4 #define CC_REG_CLK_DELAY__M 0xF #define CC_REG_CLK_DELAY_OFF 0x0 - #define CC_REG_PWD_MODE__A 0x2410015 #define CC_REG_PWD_MODE__W 2 #define CC_REG_PWD_MODE__M 0x3 @@ -6798,7 +5964,6 @@ extern "C" { #define CC_REG_PWD_MODE_DOWN_PLL 0x2 #define CC_REG_PWD_MODE_DOWN_OSC 0x3 - #define CC_REG_SOFT_RST__A 0x2410016 #define CC_REG_SOFT_RST__W 2 #define CC_REG_SOFT_RST__M 0x3 @@ -6809,40 +5974,28 @@ extern "C" { #define CC_REG_SOFT_RST_OSC__W 1 #define CC_REG_SOFT_RST_OSC__M 0x2 - #define CC_REG_UPDATE__A 0x2410017 #define CC_REG_UPDATE__W 16 #define CC_REG_UPDATE__M 0xFFFF #define CC_REG_UPDATE_KEY 0x3973 - #define CC_REG_PLL_LOCK__A 0x2410018 #define CC_REG_PLL_LOCK__W 1 #define CC_REG_PLL_LOCK__M 0x1 #define CC_REG_PLL_LOCK_LOCK 0x1 - #define CC_REG_JTAGID_L__A 0x2410019 #define CC_REG_JTAGID_L__W 16 #define CC_REG_JTAGID_L__M 0xFFFF #define CC_REG_JTAGID_L_INIT 0x0 - #define CC_REG_JTAGID_H__A 0x241001A #define CC_REG_JTAGID_H__W 16 #define CC_REG_JTAGID_H__M 0xFFFF #define CC_REG_JTAGID_H_INIT 0x0 - - - - #define LC_SID 0x1C - - - - #define LC_COMM_EXEC__A 0x2800000 #define LC_COMM_EXEC__W 3 #define LC_COMM_EXEC__M 0x7 @@ -6875,11 +6028,6 @@ extern "C" { #define LC_COMM_INT_MSK__W 16 #define LC_COMM_INT_MSK__M 0xFFFF - - - - - #define LC_CT_REG_COMM_EXEC__A 0x2810000 #define LC_CT_REG_COMM_EXEC__W 3 #define LC_CT_REG_COMM_EXEC__M 0x7 @@ -6891,7 +6039,6 @@ extern "C" { #define LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 #define LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - #define LC_CT_REG_COMM_STATE__A 0x2810001 #define LC_CT_REG_COMM_STATE__W 10 #define LC_CT_REG_COMM_STATE__M 0x3FF @@ -6905,7 +6052,6 @@ extern "C" { #define LC_CT_REG_COMM_SERVICE1_LC__W 1 #define LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 - #define LC_CT_REG_COMM_INT_STA__A 0x2810007 #define LC_CT_REG_COMM_INT_STA__W 1 #define LC_CT_REG_COMM_INT_STA__M 0x1 @@ -6913,7 +6059,6 @@ extern "C" { #define LC_CT_REG_COMM_INT_STA_REQUEST__W 1 #define LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - #define LC_CT_REG_COMM_INT_MSK__A 0x2810008 #define LC_CT_REG_COMM_INT_MSK__W 1 #define LC_CT_REG_COMM_INT_MSK__M 0x1 @@ -6921,9 +6066,6 @@ extern "C" { #define LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 #define LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - - - #define LC_CT_REG_CTL_STK__AX 0x2810010 #define LC_CT_REG_CTL_STK__XSZ 4 #define LC_CT_REG_CTL_STK__W 10 @@ -6937,10 +6079,6 @@ extern "C" { #define LC_CT_REG_CTL_BPT__W 10 #define LC_CT_REG_CTL_BPT__M 0x3FF - - - - #define LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 #define LC_RA_RAM_PROC_DELAY_IF__W 16 #define LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF @@ -7060,10 +6198,6 @@ extern "C" { #define LC_RA_RAM_ADJUST_DELAY__W 16 #define LC_RA_RAM_ADJUST_DELAY__M 0xFFFF - - - - #define LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 #define LC_RA_RAM_PIPE_CP_PHASE_0__W 16 #define LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF @@ -7083,8 +6217,6 @@ extern "C" { #define LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 #define LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF - - #define LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 #define LC_RA_RAM_PIPE_CP_CRMM_0__W 16 #define LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF @@ -7104,8 +6236,6 @@ extern "C" { #define LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 #define LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF - - #define LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 #define LC_RA_RAM_PIPE_CP_SRMM_0__W 16 #define LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF @@ -7125,10 +6255,6 @@ extern "C" { #define LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 #define LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF - - - - #define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 #define LC_RA_RAM_FILTER_CRMM_A__W 16 #define LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF @@ -7150,8 +6276,6 @@ extern "C" { #define LC_RA_RAM_FILTER_CRMM_TMP__W 16 #define LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF - - #define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 #define LC_RA_RAM_FILTER_SRMM_A__W 16 #define LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF @@ -7173,8 +6297,6 @@ extern "C" { #define LC_RA_RAM_FILTER_SRMM_TMP__W 16 #define LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF - - #define LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 #define LC_RA_RAM_FILTER_PHASE_A__W 16 #define LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF @@ -7196,8 +6318,6 @@ extern "C" { #define LC_RA_RAM_FILTER_PHASE_TMP__W 16 #define LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF - - #define LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 #define LC_RA_RAM_FILTER_DELAY_A__W 16 #define LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF @@ -7219,11 +6339,6 @@ extern "C" { #define LC_RA_RAM_FILTER_DELAY_TMP__W 16 #define LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF - - - - - #define LC_IF_RAM_TRP_BPT0__AX 0x2830000 #define LC_IF_RAM_TRP_BPT0__XSZ 2 #define LC_IF_RAM_TRP_BPT0__W 12 @@ -7239,18 +6354,8 @@ extern "C" { #define LC_IF_RAM_TRP_WARM__W 12 #define LC_IF_RAM_TRP_WARM__M 0xFFF - - - - - - #define B_HI_SID 0x10 - - - - #define B_HI_COMM_EXEC__A 0x400000 #define B_HI_COMM_EXEC__W 3 #define B_HI_COMM_EXEC__M 0x7 @@ -7283,11 +6388,6 @@ extern "C" { #define B_HI_COMM_INT_MSK__W 16 #define B_HI_COMM_INT_MSK__M 0xFFFF - - - - - #define B_HI_CT_REG_COMM_EXEC__A 0x410000 #define B_HI_CT_REG_COMM_EXEC__W 3 #define B_HI_CT_REG_COMM_EXEC__M 0x7 @@ -7299,7 +6399,6 @@ extern "C" { #define B_HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 #define B_HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 - #define B_HI_CT_REG_COMM_STATE__A 0x410001 #define B_HI_CT_REG_COMM_STATE__W 10 #define B_HI_CT_REG_COMM_STATE__M 0x3FF @@ -7313,7 +6412,6 @@ extern "C" { #define B_HI_CT_REG_COMM_SERVICE1_HI__W 1 #define B_HI_CT_REG_COMM_SERVICE1_HI__M 0x1 - #define B_HI_CT_REG_COMM_INT_STA__A 0x410007 #define B_HI_CT_REG_COMM_INT_STA__W 1 #define B_HI_CT_REG_COMM_INT_STA__M 0x1 @@ -7321,7 +6419,6 @@ extern "C" { #define B_HI_CT_REG_COMM_INT_STA_REQUEST__W 1 #define B_HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - #define B_HI_CT_REG_COMM_INT_MSK__A 0x410008 #define B_HI_CT_REG_COMM_INT_MSK__W 1 #define B_HI_CT_REG_COMM_INT_MSK__M 0x1 @@ -7329,9 +6426,6 @@ extern "C" { #define B_HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 #define B_HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - - - #define B_HI_CT_REG_CTL_STK__AX 0x410010 #define B_HI_CT_REG_CTL_STK__XSZ 4 #define B_HI_CT_REG_CTL_STK__W 10 @@ -7345,18 +6439,12 @@ extern "C" { #define B_HI_CT_REG_CTL_BPT__W 10 #define B_HI_CT_REG_CTL_BPT__M 0x3FF - - - - - #define B_HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 #define B_HI_RA_RAM_SLV0_FLG_SMM__W 1 #define B_HI_RA_RAM_SLV0_FLG_SMM__M 0x1 #define B_HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 #define B_HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 - #define B_HI_RA_RAM_SLV0_DEV_ID__A 0x420011 #define B_HI_RA_RAM_SLV0_DEV_ID__W 7 #define B_HI_RA_RAM_SLV0_DEV_ID__M 0x7F @@ -7367,7 +6455,6 @@ extern "C" { #define B_HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 #define B_HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 - #define B_HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 #define B_HI_RA_RAM_SLV0_FLG_ACC__W 3 #define B_HI_RA_RAM_SLV0_FLG_ACC__M 0x7 @@ -7382,14 +6469,12 @@ extern "C" { #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 #define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 - #define B_HI_RA_RAM_SLV0_STATE__A 0x420014 #define B_HI_RA_RAM_SLV0_STATE__W 1 #define B_HI_RA_RAM_SLV0_STATE__M 0x1 #define B_HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 #define B_HI_RA_RAM_SLV0_STATE_DATA 0x1 - #define B_HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 #define B_HI_RA_RAM_SLV0_BLK_BNK__W 12 #define B_HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF @@ -7400,7 +6485,6 @@ extern "C" { #define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 #define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 - #define B_HI_RA_RAM_SLV0_ADDR__A 0x420016 #define B_HI_RA_RAM_SLV0_ADDR__W 16 #define B_HI_RA_RAM_SLV0_ADDR__M 0xFFFF @@ -7413,16 +6497,12 @@ extern "C" { #define B_HI_RA_RAM_SLV0_READBACK__W 16 #define B_HI_RA_RAM_SLV0_READBACK__M 0xFFFF - - - #define B_HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 #define B_HI_RA_RAM_SLV1_FLG_SMM__W 1 #define B_HI_RA_RAM_SLV1_FLG_SMM__M 0x1 #define B_HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 #define B_HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 - #define B_HI_RA_RAM_SLV1_DEV_ID__A 0x420021 #define B_HI_RA_RAM_SLV1_DEV_ID__W 7 #define B_HI_RA_RAM_SLV1_DEV_ID__M 0x7F @@ -7433,7 +6513,6 @@ extern "C" { #define B_HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 #define B_HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 - #define B_HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 #define B_HI_RA_RAM_SLV1_FLG_ACC__W 3 #define B_HI_RA_RAM_SLV1_FLG_ACC__M 0x7 @@ -7448,14 +6527,12 @@ extern "C" { #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 #define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 - #define B_HI_RA_RAM_SLV1_STATE__A 0x420024 #define B_HI_RA_RAM_SLV1_STATE__W 1 #define B_HI_RA_RAM_SLV1_STATE__M 0x1 #define B_HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 #define B_HI_RA_RAM_SLV1_STATE_DATA 0x1 - #define B_HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 #define B_HI_RA_RAM_SLV1_BLK_BNK__W 12 #define B_HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF @@ -7466,7 +6543,6 @@ extern "C" { #define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 #define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 - #define B_HI_RA_RAM_SLV1_ADDR__A 0x420026 #define B_HI_RA_RAM_SLV1_ADDR__W 16 #define B_HI_RA_RAM_SLV1_ADDR__M 0xFFFF @@ -7479,16 +6555,12 @@ extern "C" { #define B_HI_RA_RAM_SLV1_READBACK__W 16 #define B_HI_RA_RAM_SLV1_READBACK__M 0xFFFF - - - #define B_HI_RA_RAM_SRV_SEM__A 0x420030 #define B_HI_RA_RAM_SRV_SEM__W 1 #define B_HI_RA_RAM_SRV_SEM__M 0x1 #define B_HI_RA_RAM_SRV_SEM_FREE 0x0 #define B_HI_RA_RAM_SRV_SEM_CLAIMED 0x1 - #define B_HI_RA_RAM_SRV_RES__A 0x420031 #define B_HI_RA_RAM_SRV_RES__W 3 #define B_HI_RA_RAM_SRV_RES__M 0x7 @@ -7498,7 +6570,6 @@ extern "C" { #define B_HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 #define B_HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 - #define B_HI_RA_RAM_SRV_CMD__A 0x420032 #define B_HI_RA_RAM_SRV_CMD__W 3 #define B_HI_RA_RAM_SRV_CMD__M 0x7 @@ -7510,22 +6581,17 @@ extern "C" { #define B_HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 #define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 - #define B_HI_RA_RAM_SRV_PAR__AX 0x420033 #define B_HI_RA_RAM_SRV_PAR__XSZ 5 #define B_HI_RA_RAM_SRV_PAR__W 16 #define B_HI_RA_RAM_SRV_PAR__M 0xFFFF - - #define B_HI_RA_RAM_SRV_NOP_RES__A 0x420031 #define B_HI_RA_RAM_SRV_NOP_RES__W 3 #define B_HI_RA_RAM_SRV_NOP_RES__M 0x7 #define B_HI_RA_RAM_SRV_NOP_RES_OK 0x0 #define B_HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 - - #define B_HI_RA_RAM_SRV_UIO_RES__A 0x420031 #define B_HI_RA_RAM_SRV_UIO_RES__W 3 #define B_HI_RA_RAM_SRV_UIO_RES__M 0x7 @@ -7557,8 +6623,6 @@ extern "C" { #define B_HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 #define B_HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 - - #define B_HI_RA_RAM_SRV_RST_RES__A 0x420031 #define B_HI_RA_RAM_SRV_RST_RES__W 1 #define B_HI_RA_RAM_SRV_RST_RES__M 0x1 @@ -7570,8 +6634,6 @@ extern "C" { #define B_HI_RA_RAM_SRV_RST_KEY__M 0xFFFF #define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 - - #define B_HI_RA_RAM_SRV_CFG_RES__A 0x420031 #define B_HI_RA_RAM_SRV_CFG_RES__W 1 #define B_HI_RA_RAM_SRV_CFG_RES__M 0x1 @@ -7583,7 +6645,6 @@ extern "C" { #define B_HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF #define B_HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 - #define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 #define B_HI_RA_RAM_SRV_CFG_DIV__W 5 #define B_HI_RA_RAM_SRV_CFG_DIV__M 0x1F @@ -7620,15 +6681,12 @@ extern "C" { #define B_HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 #define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 - - #define B_HI_RA_RAM_SRV_CPY_RES__A 0x420031 #define B_HI_RA_RAM_SRV_CPY_RES__W 1 #define B_HI_RA_RAM_SRV_CPY_RES__M 0x1 #define B_HI_RA_RAM_SRV_CPY_RES_OK 0x0 #define B_HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 - #define B_HI_RA_RAM_SRV_CPY_SBB__A 0x420033 #define B_HI_RA_RAM_SRV_CPY_SBB__W 12 #define B_HI_RA_RAM_SRV_CPY_SBB__M 0xFFF @@ -7639,7 +6697,6 @@ extern "C" { #define B_HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 #define B_HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 - #define B_HI_RA_RAM_SRV_CPY_SAD__A 0x420034 #define B_HI_RA_RAM_SRV_CPY_SAD__W 16 #define B_HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF @@ -7658,13 +6715,10 @@ extern "C" { #define B_HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 #define B_HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 - #define B_HI_RA_RAM_SRV_CPY_DAD__A 0x420034 #define B_HI_RA_RAM_SRV_CPY_DAD__W 16 #define B_HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF - - #define B_HI_RA_RAM_SRV_TRM_RES__A 0x420031 #define B_HI_RA_RAM_SRV_TRM_RES__W 2 #define B_HI_RA_RAM_SRV_TRM_RES__M 0x3 @@ -7672,7 +6726,6 @@ extern "C" { #define B_HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 #define B_HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 - #define B_HI_RA_RAM_SRV_TRM_MST__A 0x420033 #define B_HI_RA_RAM_SRV_TRM_MST__W 12 #define B_HI_RA_RAM_SRV_TRM_MST__M 0xFFF @@ -7688,7 +6741,6 @@ extern "C" { #define B_HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 #define B_HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF - #define B_HI_RA_RAM_SRV_TRM_DBB__A 0x420033 #define B_HI_RA_RAM_SRV_TRM_DBB__W 12 #define B_HI_RA_RAM_SRV_TRM_DBB__M 0xFFF @@ -7699,14 +6751,10 @@ extern "C" { #define B_HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 #define B_HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 - #define B_HI_RA_RAM_SRV_TRM_DAD__A 0x420034 #define B_HI_RA_RAM_SRV_TRM_DAD__W 16 #define B_HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF - - - #define B_HI_RA_RAM_USR_BEGIN__A 0x420040 #define B_HI_RA_RAM_USR_BEGIN__W 16 #define B_HI_RA_RAM_USR_BEGIN__M 0xFFFF @@ -7715,11 +6763,6 @@ extern "C" { #define B_HI_RA_RAM_USR_END__W 16 #define B_HI_RA_RAM_USR_END__M 0xFFFF - - - - - #define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 #define B_HI_IF_RAM_TRP_BPT0__XSZ 2 #define B_HI_IF_RAM_TRP_BPT0__W 12 @@ -7730,9 +6773,6 @@ extern "C" { #define B_HI_IF_RAM_TRP_STKU__W 12 #define B_HI_IF_RAM_TRP_STKU__M 0xFFF - - - #define B_HI_IF_RAM_USR_BEGIN__A 0x430200 #define B_HI_IF_RAM_USR_BEGIN__W 12 #define B_HI_IF_RAM_USR_BEGIN__M 0xFFF @@ -7741,16 +6781,8 @@ extern "C" { #define B_HI_IF_RAM_USR_END__W 12 #define B_HI_IF_RAM_USR_END__M 0xFFF - - - - #define B_SC_SID 0x11 - - - - #define B_SC_COMM_EXEC__A 0x800000 #define B_SC_COMM_EXEC__W 3 #define B_SC_COMM_EXEC__M 0x7 @@ -7783,11 +6815,6 @@ extern "C" { #define B_SC_COMM_INT_MSK__W 16 #define B_SC_COMM_INT_MSK__M 0xFFFF - - - - - #define B_SC_CT_REG_COMM_EXEC__A 0x810000 #define B_SC_CT_REG_COMM_EXEC__W 3 #define B_SC_CT_REG_COMM_EXEC__M 0x7 @@ -7799,7 +6826,6 @@ extern "C" { #define B_SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 #define B_SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - #define B_SC_CT_REG_COMM_STATE__A 0x810001 #define B_SC_CT_REG_COMM_STATE__W 10 #define B_SC_CT_REG_COMM_STATE__M 0x3FF @@ -7813,7 +6839,6 @@ extern "C" { #define B_SC_CT_REG_COMM_SERVICE1_SC__W 1 #define B_SC_CT_REG_COMM_SERVICE1_SC__M 0x2 - #define B_SC_CT_REG_COMM_INT_STA__A 0x810007 #define B_SC_CT_REG_COMM_INT_STA__W 1 #define B_SC_CT_REG_COMM_INT_STA__M 0x1 @@ -7821,7 +6846,6 @@ extern "C" { #define B_SC_CT_REG_COMM_INT_STA_REQUEST__W 1 #define B_SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - #define B_SC_CT_REG_COMM_INT_MSK__A 0x810008 #define B_SC_CT_REG_COMM_INT_MSK__W 1 #define B_SC_CT_REG_COMM_INT_MSK__M 0x1 @@ -7829,9 +6853,6 @@ extern "C" { #define B_SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 #define B_SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - - - #define B_SC_CT_REG_CTL_STK__AX 0x810010 #define B_SC_CT_REG_CTL_STK__XSZ 4 #define B_SC_CT_REG_CTL_STK__W 10 @@ -7845,10 +6866,6 @@ extern "C" { #define B_SC_CT_REG_CTL_BPT__W 10 #define B_SC_CT_REG_CTL_BPT__M 0x3FF - - - - #define B_SC_RA_RAM_PARAM0__A 0x820040 #define B_SC_RA_RAM_PARAM0__W 16 #define B_SC_RA_RAM_PARAM0__M 0xFFFF @@ -7934,8 +6951,6 @@ extern "C" { #define B_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xA #define B_SC_RA_RAM_LOCKTRACK_MAX 0xB - - #define B_SC_RA_RAM_OP_PARAM__A 0x820048 #define B_SC_RA_RAM_OP_PARAM__W 13 #define B_SC_RA_RAM_OP_PARAM__M 0x1FFF @@ -8025,8 +7040,6 @@ extern "C" { #define B_SC_RA_RAM_LOCK_NODVBT__W 1 #define B_SC_RA_RAM_LOCK_NODVBT__M 0x8 - - #define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C #define B_SC_RA_RAM_BE_OPT_ENA__W 5 #define B_SC_RA_RAM_BE_OPT_ENA__M 0x1F @@ -8098,10 +7111,6 @@ extern "C" { #define B_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF #define B_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 - - - - #define B_SC_RA_RAM_FR_2K_MAN_SH__A 0x820055 #define B_SC_RA_RAM_FR_2K_MAN_SH__W 16 #define B_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF @@ -8119,8 +7128,6 @@ extern "C" { #define B_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF #define B_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 - - #define B_SC_RA_RAM_FR_8K_MAN_SH__A 0x820059 #define B_SC_RA_RAM_FR_8K_MAN_SH__W 16 #define B_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF @@ -8138,8 +7145,6 @@ extern "C" { #define B_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF #define B_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x2 - - #define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D #define B_SC_RA_RAM_CO_TD_CAL_2K__W 16 #define B_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF @@ -8215,10 +7220,6 @@ extern "C" { #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__M 0xFFFF #define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__PRE 0x0 - - - - #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF @@ -8236,8 +7237,6 @@ extern "C" { #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 - - #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF @@ -8255,17 +7254,11 @@ extern "C" { #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC - - #define B_SC_RA_RAM_IR_FREQ__A 0x8200D0 #define B_SC_RA_RAM_IR_FREQ__W 16 #define B_SC_RA_RAM_IR_FREQ__M 0xFFFF #define B_SC_RA_RAM_IR_FREQ__PRE 0x0 - - - - #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF @@ -8279,8 +7272,6 @@ extern "C" { #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 - - #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF @@ -8294,10 +7285,6 @@ extern "C" { #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 - - - - #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF @@ -8311,8 +7298,6 @@ extern "C" { #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 - - #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF @@ -8326,8 +7311,6 @@ extern "C" { #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 - - #define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD #define B_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 #define B_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF @@ -8347,10 +7330,6 @@ extern "C" { #define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 #define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 - - - - #define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 #define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 #define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF @@ -8364,8 +7343,6 @@ extern "C" { #define B_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF #define B_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 - - #define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 #define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 #define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF @@ -8379,8 +7356,6 @@ extern "C" { #define B_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF #define B_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 - - #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF @@ -8390,8 +7365,6 @@ extern "C" { #define B_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF #define B_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C - - #define B_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA #define B_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 #define B_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF @@ -8446,8 +7419,6 @@ extern "C" { #define B_SC_RA_RAM_BOOTCOUNT__W 16 #define B_SC_RA_RAM_BOOTCOUNT__M 0xFFFF - - #define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 #define B_SC_RA_RAM_LC_ABS_2K__W 16 #define B_SC_RA_RAM_LC_ABS_2K__M 0xFFFF @@ -8471,8 +7442,6 @@ extern "C" { #define B_SC_RA_RAM_STACKUNDERFLOW__W 16 #define B_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF - - #define B_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 #define B_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 #define B_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF @@ -8500,10 +7469,6 @@ extern "C" { #define B_SC_RA_RAM_NF_ECHOTABLE__W 16 #define B_SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF - - - - #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF @@ -8513,8 +7478,6 @@ extern "C" { #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 - - #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF @@ -8522,9 +7485,7 @@ extern "C" { #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 - - +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 @@ -8535,8 +7496,6 @@ extern "C" { #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 - - #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF @@ -8546,8 +7505,6 @@ extern "C" { #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 - - #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF @@ -8557,8 +7514,6 @@ extern "C" { #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 - - #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF @@ -8568,8 +7523,6 @@ extern "C" { #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 - - #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF @@ -8579,8 +7532,6 @@ extern "C" { #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 - - #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF @@ -8609,11 +7560,6 @@ extern "C" { #define B_SC_RA_RAM_PROC_ECHO_DIVERSITY 0x8 #define B_SC_RA_RAM_PROC_MAX 0x9 - - - - - #define B_SC_IF_RAM_TRP_RST__AX 0x830000 #define B_SC_IF_RAM_TRP_RST__XSZ 2 #define B_SC_IF_RAM_TRP_RST__W 12 @@ -8629,9 +7575,6 @@ extern "C" { #define B_SC_IF_RAM_TRP_STKU__W 12 #define B_SC_IF_RAM_TRP_STKU__M 0xFFF - - - #define B_SC_IF_RAM_VERSION_MA_MI__A 0x830FFE #define B_SC_IF_RAM_VERSION_MA_MI__W 12 #define B_SC_IF_RAM_VERSION_MA_MI__M 0xFFF @@ -8640,14 +7583,6 @@ extern "C" { #define B_SC_IF_RAM_VERSION_PATCH__W 12 #define B_SC_IF_RAM_VERSION_PATCH__M 0xFFF - - - - - - - - #define B_FE_COMM_EXEC__A 0xC00000 #define B_FE_COMM_EXEC__W 3 #define B_FE_COMM_EXEC__M 0x7 @@ -8680,17 +7615,8 @@ extern "C" { #define B_FE_COMM_INT_MSK__W 16 #define B_FE_COMM_INT_MSK__M 0xFFFF - - - - #define B_FE_AD_SID 0x1 - - - - - #define B_FE_AD_REG_COMM_EXEC__A 0xC10000 #define B_FE_AD_REG_COMM_EXEC__W 3 #define B_FE_AD_REG_COMM_EXEC__M 0x7 @@ -8702,7 +7628,6 @@ extern "C" { #define B_FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 #define B_FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 - #define B_FE_AD_REG_COMM_MB__A 0xC10002 #define B_FE_AD_REG_COMM_MB__W 2 #define B_FE_AD_REG_COMM_MB__M 0x3 @@ -8735,7 +7660,6 @@ extern "C" { #define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 #define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 - #define B_FE_AD_REG_COMM_INT_MSK__A 0xC10008 #define B_FE_AD_REG_COMM_INT_MSK__W 2 #define B_FE_AD_REG_COMM_INT_MSK__M 0x3 @@ -8743,137 +7667,108 @@ extern "C" { #define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 #define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 - #define B_FE_AD_REG_CUR_SEL__A 0xC10010 #define B_FE_AD_REG_CUR_SEL__W 2 #define B_FE_AD_REG_CUR_SEL__M 0x3 #define B_FE_AD_REG_CUR_SEL_INIT 0x2 - #define B_FE_AD_REG_OVERFLOW__A 0xC10011 #define B_FE_AD_REG_OVERFLOW__W 1 #define B_FE_AD_REG_OVERFLOW__M 0x1 #define B_FE_AD_REG_OVERFLOW_INIT 0x0 - #define B_FE_AD_REG_FDB_IN__A 0xC10012 #define B_FE_AD_REG_FDB_IN__W 1 #define B_FE_AD_REG_FDB_IN__M 0x1 #define B_FE_AD_REG_FDB_IN_INIT 0x0 - #define B_FE_AD_REG_PD__A 0xC10013 #define B_FE_AD_REG_PD__W 1 #define B_FE_AD_REG_PD__M 0x1 #define B_FE_AD_REG_PD_INIT 0x1 - #define B_FE_AD_REG_INVEXT__A 0xC10014 #define B_FE_AD_REG_INVEXT__W 1 #define B_FE_AD_REG_INVEXT__M 0x1 #define B_FE_AD_REG_INVEXT_INIT 0x0 - #define B_FE_AD_REG_CLKNEG__A 0xC10015 #define B_FE_AD_REG_CLKNEG__W 1 #define B_FE_AD_REG_CLKNEG__M 0x1 #define B_FE_AD_REG_CLKNEG_INIT 0x0 - #define B_FE_AD_REG_MON_IN_MUX__A 0xC10016 #define B_FE_AD_REG_MON_IN_MUX__W 2 #define B_FE_AD_REG_MON_IN_MUX__M 0x3 #define B_FE_AD_REG_MON_IN_MUX_INIT 0x0 - #define B_FE_AD_REG_MON_IN5__A 0xC10017 #define B_FE_AD_REG_MON_IN5__W 10 #define B_FE_AD_REG_MON_IN5__M 0x3FF #define B_FE_AD_REG_MON_IN5_INIT 0x0 - #define B_FE_AD_REG_MON_IN4__A 0xC10018 #define B_FE_AD_REG_MON_IN4__W 10 #define B_FE_AD_REG_MON_IN4__M 0x3FF #define B_FE_AD_REG_MON_IN4_INIT 0x0 - #define B_FE_AD_REG_MON_IN3__A 0xC10019 #define B_FE_AD_REG_MON_IN3__W 10 #define B_FE_AD_REG_MON_IN3__M 0x3FF #define B_FE_AD_REG_MON_IN3_INIT 0x0 - #define B_FE_AD_REG_MON_IN2__A 0xC1001A #define B_FE_AD_REG_MON_IN2__W 10 #define B_FE_AD_REG_MON_IN2__M 0x3FF #define B_FE_AD_REG_MON_IN2_INIT 0x0 - #define B_FE_AD_REG_MON_IN1__A 0xC1001B #define B_FE_AD_REG_MON_IN1__W 10 #define B_FE_AD_REG_MON_IN1__M 0x3FF #define B_FE_AD_REG_MON_IN1_INIT 0x0 - #define B_FE_AD_REG_MON_IN0__A 0xC1001C #define B_FE_AD_REG_MON_IN0__W 10 #define B_FE_AD_REG_MON_IN0__M 0x3FF #define B_FE_AD_REG_MON_IN0_INIT 0x0 - #define B_FE_AD_REG_MON_IN_VAL__A 0xC1001D #define B_FE_AD_REG_MON_IN_VAL__W 1 #define B_FE_AD_REG_MON_IN_VAL__M 0x1 #define B_FE_AD_REG_MON_IN_VAL_INIT 0x0 - #define B_FE_AD_REG_CTR_CLK_O__A 0xC1001E #define B_FE_AD_REG_CTR_CLK_O__W 1 #define B_FE_AD_REG_CTR_CLK_O__M 0x1 #define B_FE_AD_REG_CTR_CLK_O_INIT 0x0 - #define B_FE_AD_REG_CTR_CLK_E_O__A 0xC1001F #define B_FE_AD_REG_CTR_CLK_E_O__W 1 #define B_FE_AD_REG_CTR_CLK_E_O__M 0x1 #define B_FE_AD_REG_CTR_CLK_E_O_INIT 0x1 - #define B_FE_AD_REG_CTR_VAL_O__A 0xC10020 #define B_FE_AD_REG_CTR_VAL_O__W 1 #define B_FE_AD_REG_CTR_VAL_O__M 0x1 #define B_FE_AD_REG_CTR_VAL_O_INIT 0x0 - #define B_FE_AD_REG_CTR_VAL_E_O__A 0xC10021 #define B_FE_AD_REG_CTR_VAL_E_O__W 1 #define B_FE_AD_REG_CTR_VAL_E_O__M 0x1 #define B_FE_AD_REG_CTR_VAL_E_O_INIT 0x1 - #define B_FE_AD_REG_CTR_DATA_O__A 0xC10022 #define B_FE_AD_REG_CTR_DATA_O__W 10 #define B_FE_AD_REG_CTR_DATA_O__M 0x3FF #define B_FE_AD_REG_CTR_DATA_O_INIT 0x0 - #define B_FE_AD_REG_CTR_DATA_E_O__A 0xC10023 #define B_FE_AD_REG_CTR_DATA_E_O__W 10 #define B_FE_AD_REG_CTR_DATA_E_O__M 0x3FF #define B_FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF - - - - #define B_FE_AG_SID 0x2 - - - - - #define B_FE_AG_REG_COMM_EXEC__A 0xC20000 #define B_FE_AG_REG_COMM_EXEC__W 3 #define B_FE_AG_REG_COMM_EXEC__M 0x7 @@ -8905,7 +7800,6 @@ extern "C" { #define B_FE_AG_REG_COMM_MB_MUX_DAT_PD1 0x8 #define B_FE_AG_REG_COMM_MB_MUX_DAT_IND_PD1 0xC - #define B_FE_AG_REG_COMM_SERVICE0__A 0xC20003 #define B_FE_AG_REG_COMM_SERVICE0__W 10 #define B_FE_AG_REG_COMM_SERVICE0__M 0x3FF @@ -8939,7 +7833,6 @@ extern "C" { #define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 #define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 - #define B_FE_AG_REG_COMM_INT_MSK__A 0xC20008 #define B_FE_AG_REG_COMM_INT_MSK__W 8 #define B_FE_AG_REG_COMM_INT_MSK__M 0xFF @@ -8965,7 +7858,6 @@ extern "C" { #define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 #define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 - #define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 #define B_FE_AG_REG_AG_MODE_LOP__W 15 #define B_FE_AG_REG_AG_MODE_LOP__M 0x7FFF @@ -9055,7 +7947,6 @@ extern "C" { #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 - #define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 #define B_FE_AG_REG_AG_MODE_HIP__W 5 #define B_FE_AG_REG_AG_MODE_HIP__M 0x1F @@ -9091,7 +7982,6 @@ extern "C" { #define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH1 0x0 #define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH2 0x10 - #define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 #define B_FE_AG_REG_AG_PGA_MODE__W 3 #define B_FE_AG_REG_AG_PGA_MODE__M 0x7 @@ -9105,7 +7995,6 @@ extern "C" { #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 - #define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 #define B_FE_AG_REG_AG_AGC_SIO__W 2 #define B_FE_AG_REG_AG_AGC_SIO__M 0x3 @@ -9123,7 +8012,6 @@ extern "C" { #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 - #define B_FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 #define B_FE_AG_REG_AG_AGC_USR_DAT__W 2 #define B_FE_AG_REG_AG_AGC_USR_DAT__M 0x3 @@ -9134,7 +8022,6 @@ extern "C" { #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 #define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 - #define B_FE_AG_REG_AG_PWD__A 0xC20015 #define B_FE_AG_REG_AG_PWD__W 5 #define B_FE_AG_REG_AG_PWD__M 0x1F @@ -9170,19 +8057,16 @@ extern "C" { #define B_FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 #define B_FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 - #define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 #define B_FE_AG_REG_DCE_AUR_CNT__W 5 #define B_FE_AG_REG_DCE_AUR_CNT__M 0x1F #define B_FE_AG_REG_DCE_AUR_CNT_INIT 0x10 - #define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 #define B_FE_AG_REG_DCE_RUR_CNT__W 5 #define B_FE_AG_REG_DCE_RUR_CNT__M 0x1F #define B_FE_AG_REG_DCE_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_DCE_AVE_DAT__A 0xC20018 #define B_FE_AG_REG_DCE_AVE_DAT__W 10 #define B_FE_AG_REG_DCE_AVE_DAT__M 0x3FF @@ -9192,19 +8076,16 @@ extern "C" { #define B_FE_AG_REG_DEC_AVE_WRI__M 0x3FF #define B_FE_AG_REG_DEC_AVE_WRI_INIT 0x0 - #define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A #define B_FE_AG_REG_ACE_AUR_CNT__W 5 #define B_FE_AG_REG_ACE_AUR_CNT__M 0x1F #define B_FE_AG_REG_ACE_AUR_CNT_INIT 0xE - #define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B #define B_FE_AG_REG_ACE_RUR_CNT__W 5 #define B_FE_AG_REG_ACE_RUR_CNT__M 0x1F #define B_FE_AG_REG_ACE_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_ACE_AVE_DAT__A 0xC2001C #define B_FE_AG_REG_ACE_AVE_DAT__W 10 #define B_FE_AG_REG_ACE_AVE_DAT__M 0x3FF @@ -9214,7 +8095,6 @@ extern "C" { #define B_FE_AG_REG_AEC_AVE_INC__M 0x3FF #define B_FE_AG_REG_AEC_AVE_INC_INIT 0x0 - #define B_FE_AG_REG_AEC_AVE_DAT__A 0xC2001E #define B_FE_AG_REG_AEC_AVE_DAT__W 10 #define B_FE_AG_REG_AEC_AVE_DAT__M 0x3FF @@ -9224,13 +8104,11 @@ extern "C" { #define B_FE_AG_REG_AEC_CLP_LVL__M 0xFFFF #define B_FE_AG_REG_AEC_CLP_LVL_INIT 0x0 - #define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 #define B_FE_AG_REG_CDR_RUR_CNT__W 5 #define B_FE_AG_REG_CDR_RUR_CNT__M 0x1F #define B_FE_AG_REG_CDR_RUR_CNT_INIT 0x10 - #define B_FE_AG_REG_CDR_CLP_DAT__A 0xC20021 #define B_FE_AG_REG_CDR_CLP_DAT__W 16 #define B_FE_AG_REG_CDR_CLP_DAT__M 0xFFFF @@ -9240,79 +8118,66 @@ extern "C" { #define B_FE_AG_REG_CDR_CLP_POS__M 0x3FF #define B_FE_AG_REG_CDR_CLP_POS_INIT 0x16A - #define B_FE_AG_REG_CDR_CLP_NEG__A 0xC20023 #define B_FE_AG_REG_CDR_CLP_NEG__W 10 #define B_FE_AG_REG_CDR_CLP_NEG__M 0x3FF #define B_FE_AG_REG_CDR_CLP_NEG_INIT 0x296 - #define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 #define B_FE_AG_REG_EGC_RUR_CNT__W 5 #define B_FE_AG_REG_EGC_RUR_CNT__M 0x1F #define B_FE_AG_REG_EGC_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 #define B_FE_AG_REG_EGC_SET_LVL__W 9 #define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF #define B_FE_AG_REG_EGC_SET_LVL_INIT 0x46 - #define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 #define B_FE_AG_REG_EGC_FLA_RGN__W 9 #define B_FE_AG_REG_EGC_FLA_RGN__M 0x1FF #define B_FE_AG_REG_EGC_FLA_RGN_INIT 0x4 - #define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 #define B_FE_AG_REG_EGC_SLO_RGN__W 9 #define B_FE_AG_REG_EGC_SLO_RGN__M 0x1FF #define B_FE_AG_REG_EGC_SLO_RGN_INIT 0x1F - #define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 #define B_FE_AG_REG_EGC_JMP_PSN__W 4 #define B_FE_AG_REG_EGC_JMP_PSN__M 0xF #define B_FE_AG_REG_EGC_JMP_PSN_INIT 0x0 - #define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 #define B_FE_AG_REG_EGC_FLA_INC__W 16 #define B_FE_AG_REG_EGC_FLA_INC__M 0xFFFF #define B_FE_AG_REG_EGC_FLA_INC_INIT 0x0 - #define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A #define B_FE_AG_REG_EGC_FLA_DEC__W 16 #define B_FE_AG_REG_EGC_FLA_DEC__M 0xFFFF #define B_FE_AG_REG_EGC_FLA_DEC_INIT 0x0 - #define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B #define B_FE_AG_REG_EGC_SLO_INC__W 16 #define B_FE_AG_REG_EGC_SLO_INC__M 0xFFFF #define B_FE_AG_REG_EGC_SLO_INC_INIT 0x3 - #define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C #define B_FE_AG_REG_EGC_SLO_DEC__W 16 #define B_FE_AG_REG_EGC_SLO_DEC__M 0xFFFF #define B_FE_AG_REG_EGC_SLO_DEC_INIT 0x3 - #define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D #define B_FE_AG_REG_EGC_FAS_INC__W 16 #define B_FE_AG_REG_EGC_FAS_INC__M 0xFFFF #define B_FE_AG_REG_EGC_FAS_INC_INIT 0xE - #define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E #define B_FE_AG_REG_EGC_FAS_DEC__W 16 #define B_FE_AG_REG_EGC_FAS_DEC__M 0xFFFF #define B_FE_AG_REG_EGC_FAS_DEC_INIT 0xE - #define B_FE_AG_REG_EGC_MAP_DAT__A 0xC2002F #define B_FE_AG_REG_EGC_MAP_DAT__W 16 #define B_FE_AG_REG_EGC_MAP_DAT__M 0xFFFF @@ -9322,31 +8187,26 @@ extern "C" { #define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF #define B_FE_AG_REG_PM1_AGC_WRI_INIT 0x0 - #define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 #define B_FE_AG_REG_GC1_AGC_RIC__W 16 #define B_FE_AG_REG_GC1_AGC_RIC__M 0xFFFF #define B_FE_AG_REG_GC1_AGC_RIC_INIT 0x64 - #define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 #define B_FE_AG_REG_GC1_AGC_OFF__W 16 #define B_FE_AG_REG_GC1_AGC_OFF__M 0xFFFF #define B_FE_AG_REG_GC1_AGC_OFF_INIT 0xFEC8 - #define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 #define B_FE_AG_REG_GC1_AGC_MAX__W 10 #define B_FE_AG_REG_GC1_AGC_MAX__M 0x3FF #define B_FE_AG_REG_GC1_AGC_MAX_INIT 0x1FF - #define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 #define B_FE_AG_REG_GC1_AGC_MIN__W 10 #define B_FE_AG_REG_GC1_AGC_MIN__M 0x3FF #define B_FE_AG_REG_GC1_AGC_MIN_INIT 0x200 - #define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 #define B_FE_AG_REG_GC1_AGC_DAT__W 10 #define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF @@ -9356,31 +8216,26 @@ extern "C" { #define B_FE_AG_REG_PM2_AGC_WRI__M 0x7FF #define B_FE_AG_REG_PM2_AGC_WRI_INIT 0x0 - #define B_FE_AG_REG_GC2_AGC_RIC__A 0xC20037 #define B_FE_AG_REG_GC2_AGC_RIC__W 16 #define B_FE_AG_REG_GC2_AGC_RIC__M 0xFFFF #define B_FE_AG_REG_GC2_AGC_RIC_INIT 0x64 - #define B_FE_AG_REG_GC2_AGC_OFF__A 0xC20038 #define B_FE_AG_REG_GC2_AGC_OFF__W 16 #define B_FE_AG_REG_GC2_AGC_OFF__M 0xFFFF #define B_FE_AG_REG_GC2_AGC_OFF_INIT 0xFEC8 - #define B_FE_AG_REG_GC2_AGC_MAX__A 0xC20039 #define B_FE_AG_REG_GC2_AGC_MAX__W 10 #define B_FE_AG_REG_GC2_AGC_MAX__M 0x3FF #define B_FE_AG_REG_GC2_AGC_MAX_INIT 0x1FF - #define B_FE_AG_REG_GC2_AGC_MIN__A 0xC2003A #define B_FE_AG_REG_GC2_AGC_MIN__W 10 #define B_FE_AG_REG_GC2_AGC_MIN__M 0x3FF #define B_FE_AG_REG_GC2_AGC_MIN_INIT 0x200 - #define B_FE_AG_REG_GC2_AGC_DAT__A 0xC2003B #define B_FE_AG_REG_GC2_AGC_DAT__W 10 #define B_FE_AG_REG_GC2_AGC_DAT__M 0x3FF @@ -9390,43 +8245,36 @@ extern "C" { #define B_FE_AG_REG_IND_WIN__M 0x1F #define B_FE_AG_REG_IND_WIN_INIT 0x0 - #define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D #define B_FE_AG_REG_IND_THD_LOL__W 6 #define B_FE_AG_REG_IND_THD_LOL__M 0x3F #define B_FE_AG_REG_IND_THD_LOL_INIT 0x5 - #define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E #define B_FE_AG_REG_IND_THD_HIL__W 6 #define B_FE_AG_REG_IND_THD_HIL__M 0x3F #define B_FE_AG_REG_IND_THD_HIL_INIT 0xF - #define B_FE_AG_REG_IND_DEL__A 0xC2003F #define B_FE_AG_REG_IND_DEL__W 7 #define B_FE_AG_REG_IND_DEL__M 0x7F #define B_FE_AG_REG_IND_DEL_INIT 0x32 - #define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 #define B_FE_AG_REG_IND_PD1_WRI__W 6 #define B_FE_AG_REG_IND_PD1_WRI__M 0x3F #define B_FE_AG_REG_IND_PD1_WRI_INIT 0x1E - #define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 #define B_FE_AG_REG_PDA_AUR_CNT__W 5 #define B_FE_AG_REG_PDA_AUR_CNT__M 0x1F #define B_FE_AG_REG_PDA_AUR_CNT_INIT 0x10 - #define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 #define B_FE_AG_REG_PDA_RUR_CNT__W 5 #define B_FE_AG_REG_PDA_RUR_CNT__M 0x1F #define B_FE_AG_REG_PDA_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 #define B_FE_AG_REG_PDA_AVE_DAT__W 6 #define B_FE_AG_REG_PDA_AVE_DAT__M 0x3F @@ -9436,43 +8284,36 @@ extern "C" { #define B_FE_AG_REG_PDC_RUR_CNT__M 0x1F #define B_FE_AG_REG_PDC_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 #define B_FE_AG_REG_PDC_SET_LVL__W 6 #define B_FE_AG_REG_PDC_SET_LVL__M 0x3F #define B_FE_AG_REG_PDC_SET_LVL_INIT 0x10 - #define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 #define B_FE_AG_REG_PDC_FLA_RGN__W 6 #define B_FE_AG_REG_PDC_FLA_RGN__M 0x3F #define B_FE_AG_REG_PDC_FLA_RGN_INIT 0x0 - #define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 #define B_FE_AG_REG_PDC_JMP_PSN__W 3 #define B_FE_AG_REG_PDC_JMP_PSN__M 0x7 #define B_FE_AG_REG_PDC_JMP_PSN_INIT 0x0 - #define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 #define B_FE_AG_REG_PDC_FLA_STP__W 16 #define B_FE_AG_REG_PDC_FLA_STP__M 0xFFFF #define B_FE_AG_REG_PDC_FLA_STP_INIT 0x0 - #define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 #define B_FE_AG_REG_PDC_SLO_STP__W 16 #define B_FE_AG_REG_PDC_SLO_STP__M 0xFFFF #define B_FE_AG_REG_PDC_SLO_STP_INIT 0x1 - #define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A #define B_FE_AG_REG_PDC_PD2_WRI__W 6 #define B_FE_AG_REG_PDC_PD2_WRI__M 0x3F #define B_FE_AG_REG_PDC_PD2_WRI_INIT 0x1F - #define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B #define B_FE_AG_REG_PDC_MAP_DAT__W 6 #define B_FE_AG_REG_PDC_MAP_DAT__M 0x3F @@ -9482,19 +8323,16 @@ extern "C" { #define B_FE_AG_REG_PDC_MAX__M 0x3F #define B_FE_AG_REG_PDC_MAX_INIT 0x2 - #define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D #define B_FE_AG_REG_TGA_AUR_CNT__W 5 #define B_FE_AG_REG_TGA_AUR_CNT__M 0x1F #define B_FE_AG_REG_TGA_AUR_CNT_INIT 0x10 - #define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E #define B_FE_AG_REG_TGA_RUR_CNT__W 5 #define B_FE_AG_REG_TGA_RUR_CNT__M 0x1F #define B_FE_AG_REG_TGA_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F #define B_FE_AG_REG_TGA_AVE_DAT__W 6 #define B_FE_AG_REG_TGA_AVE_DAT__M 0x3F @@ -9504,37 +8342,31 @@ extern "C" { #define B_FE_AG_REG_TGC_RUR_CNT__M 0x1F #define B_FE_AG_REG_TGC_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 #define B_FE_AG_REG_TGC_SET_LVL__W 6 #define B_FE_AG_REG_TGC_SET_LVL__M 0x3F #define B_FE_AG_REG_TGC_SET_LVL_INIT 0x18 - #define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 #define B_FE_AG_REG_TGC_FLA_RGN__W 6 #define B_FE_AG_REG_TGC_FLA_RGN__M 0x3F #define B_FE_AG_REG_TGC_FLA_RGN_INIT 0x0 - #define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 #define B_FE_AG_REG_TGC_JMP_PSN__W 4 #define B_FE_AG_REG_TGC_JMP_PSN__M 0xF #define B_FE_AG_REG_TGC_JMP_PSN_INIT 0x0 - #define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 #define B_FE_AG_REG_TGC_FLA_STP__W 16 #define B_FE_AG_REG_TGC_FLA_STP__M 0xFFFF #define B_FE_AG_REG_TGC_FLA_STP_INIT 0x0 - #define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 #define B_FE_AG_REG_TGC_SLO_STP__W 16 #define B_FE_AG_REG_TGC_SLO_STP__M 0xFFFF #define B_FE_AG_REG_TGC_SLO_STP_INIT 0x1 - #define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 #define B_FE_AG_REG_TGC_MAP_DAT__W 10 #define B_FE_AG_REG_TGC_MAP_DAT__M 0x3FF @@ -9544,31 +8376,26 @@ extern "C" { #define B_FE_AG_REG_FGM_WRI__M 0x3FF #define B_FE_AG_REG_FGM_WRI_INIT 0x80 - #define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 #define B_FE_AG_REG_BGC_FGC_WRI__W 4 #define B_FE_AG_REG_BGC_FGC_WRI__M 0xF #define B_FE_AG_REG_BGC_FGC_WRI_INIT 0x0 - #define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 #define B_FE_AG_REG_BGC_CGC_WRI__W 2 #define B_FE_AG_REG_BGC_CGC_WRI__M 0x3 #define B_FE_AG_REG_BGC_CGC_WRI_INIT 0x0 - #define B_FE_AG_REG_BGC_THD_LVL__A 0xC2006B #define B_FE_AG_REG_BGC_THD_LVL__W 4 #define B_FE_AG_REG_BGC_THD_LVL__M 0xF #define B_FE_AG_REG_BGC_THD_LVL_INIT 0xF - #define B_FE_AG_REG_BGC_THD_INC__A 0xC2006C #define B_FE_AG_REG_BGC_THD_INC__W 4 #define B_FE_AG_REG_BGC_THD_INC__M 0xF #define B_FE_AG_REG_BGC_THD_INC_INIT 0x8 - #define B_FE_AG_REG_BGC_DAT__A 0xC2006D #define B_FE_AG_REG_BGC_DAT__W 4 #define B_FE_AG_REG_BGC_DAT__M 0xF @@ -9578,7 +8405,6 @@ extern "C" { #define B_FE_AG_REG_IND_PD1_COM__M 0x3F #define B_FE_AG_REG_IND_PD1_COM_INIT 0x7 - #define B_FE_AG_REG_AG_AGC_BUF__A 0xC2006F #define B_FE_AG_REG_AG_AGC_BUF__W 2 #define B_FE_AG_REG_AG_AGC_BUF__M 0x3 @@ -9596,7 +8422,6 @@ extern "C" { #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_SLOW 0x0 #define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_FAST 0x2 - #define B_FE_AG_REG_PMX_SPE__A 0xC20070 #define B_FE_AG_REG_PMX_SPE__W 3 #define B_FE_AG_REG_PMX_SPE__M 0x7 @@ -9610,17 +8435,8 @@ extern "C" { #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_7 0x6 #define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_8 0x7 - - - - #define B_FE_FS_SID 0x3 - - - - - #define B_FE_FS_REG_COMM_EXEC__A 0xC30000 #define B_FE_FS_REG_COMM_EXEC__W 3 #define B_FE_FS_REG_COMM_EXEC__M 0x7 @@ -9655,7 +8471,6 @@ extern "C" { #define B_FE_FS_REG_COMM_MB_MUX_REAL 0x0 #define B_FE_FS_REG_COMM_MB_MUX_IMAG 0x4 - #define B_FE_FS_REG_COMM_SERVICE0__A 0xC30003 #define B_FE_FS_REG_COMM_SERVICE0__W 10 #define B_FE_FS_REG_COMM_SERVICE0__M 0x3FF @@ -9677,35 +8492,23 @@ extern "C" { #define B_FE_FS_REG_ADD_INC_LOP__M 0xFFFF #define B_FE_FS_REG_ADD_INC_LOP_INIT 0x0 - #define B_FE_FS_REG_ADD_INC_HIP__A 0xC30011 #define B_FE_FS_REG_ADD_INC_HIP__W 12 #define B_FE_FS_REG_ADD_INC_HIP__M 0xFFF #define B_FE_FS_REG_ADD_INC_HIP_INIT 0xC00 - #define B_FE_FS_REG_ADD_OFF__A 0xC30012 #define B_FE_FS_REG_ADD_OFF__W 12 #define B_FE_FS_REG_ADD_OFF__M 0xFFF #define B_FE_FS_REG_ADD_OFF_INIT 0x0 - #define B_FE_FS_REG_ADD_OFF_VAL__A 0xC30013 #define B_FE_FS_REG_ADD_OFF_VAL__W 1 #define B_FE_FS_REG_ADD_OFF_VAL__M 0x1 #define B_FE_FS_REG_ADD_OFF_VAL_INIT 0x0 - - - - #define B_FE_FD_SID 0x4 - - - - - #define B_FE_FD_REG_COMM_EXEC__A 0xC40000 #define B_FE_FD_REG_COMM_EXEC__W 3 #define B_FE_FD_REG_COMM_EXEC__M 0x7 @@ -9717,7 +8520,6 @@ extern "C" { #define B_FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 #define B_FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 - #define B_FE_FD_REG_COMM_MB__A 0xC40002 #define B_FE_FD_REG_COMM_MB__W 3 #define B_FE_FD_REG_COMM_MB__M 0x7 @@ -9746,7 +8548,6 @@ extern "C" { #define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 #define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - #define B_FE_FD_REG_COMM_INT_MSK__A 0xC40008 #define B_FE_FD_REG_COMM_INT_MSK__W 1 #define B_FE_FD_REG_COMM_INT_MSK__M 0x1 @@ -9754,7 +8555,6 @@ extern "C" { #define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 #define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - #define B_FE_FD_REG_SCL__A 0xC40010 #define B_FE_FD_REG_SCL__W 6 #define B_FE_FD_REG_SCL__M 0x3F @@ -9779,17 +8579,8 @@ extern "C" { #define B_FE_FD_REG_MAX__W 16 #define B_FE_FD_REG_MAX__M 0xFFFF - - - - #define B_FE_IF_SID 0x5 - - - - - #define B_FE_IF_REG_COMM_EXEC__A 0xC50000 #define B_FE_IF_REG_COMM_EXEC__W 3 #define B_FE_IF_REG_COMM_EXEC__M 0x7 @@ -9801,7 +8592,6 @@ extern "C" { #define B_FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 #define B_FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 - #define B_FE_IF_REG_COMM_MB__A 0xC50002 #define B_FE_IF_REG_COMM_MB__W 3 #define B_FE_IF_REG_COMM_MB__M 0x7 @@ -9816,29 +8606,18 @@ extern "C" { #define B_FE_IF_REG_COMM_MB_OBS_OFF 0x0 #define B_FE_IF_REG_COMM_MB_OBS_ON 0x2 - #define B_FE_IF_REG_INCR0__A 0xC50010 #define B_FE_IF_REG_INCR0__W 16 #define B_FE_IF_REG_INCR0__M 0xFFFF #define B_FE_IF_REG_INCR0_INIT 0x0 - #define B_FE_IF_REG_INCR1__A 0xC50011 #define B_FE_IF_REG_INCR1__W 8 #define B_FE_IF_REG_INCR1__M 0xFF #define B_FE_IF_REG_INCR1_INIT 0x28 - - - - #define B_FE_CF_SID 0x6 - - - - - #define B_FE_CF_REG_COMM_EXEC__A 0xC60000 #define B_FE_CF_REG_COMM_EXEC__W 3 #define B_FE_CF_REG_COMM_EXEC__M 0x7 @@ -9850,7 +8629,6 @@ extern "C" { #define B_FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 #define B_FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 - #define B_FE_CF_REG_COMM_MB__A 0xC60002 #define B_FE_CF_REG_COMM_MB__W 3 #define B_FE_CF_REG_COMM_MB__M 0x7 @@ -9879,7 +8657,6 @@ extern "C" { #define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 #define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - #define B_FE_CF_REG_COMM_INT_MSK__A 0xC60008 #define B_FE_CF_REG_COMM_INT_MSK__W 2 #define B_FE_CF_REG_COMM_INT_MSK__M 0x3 @@ -9887,7 +8664,6 @@ extern "C" { #define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 #define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - #define B_FE_CF_REG_SCL__A 0xC60010 #define B_FE_CF_REG_SCL__W 9 #define B_FE_CF_REG_SCL__M 0x1FF @@ -9912,17 +8688,8 @@ extern "C" { #define B_FE_CF_REG_MAX__W 16 #define B_FE_CF_REG_MAX__M 0xFFFF - - - - #define B_FE_CU_SID 0x7 - - - - - #define B_FE_CU_REG_COMM_EXEC__A 0xC70000 #define B_FE_CU_REG_COMM_EXEC__W 3 #define B_FE_CU_REG_COMM_EXEC__M 0x7 @@ -9957,7 +8724,6 @@ extern "C" { #define B_FE_CU_REG_COMM_MB_MUX_REAL 0x0 #define B_FE_CU_REG_COMM_MB_MUX_IMAG 0x4 - #define B_FE_CU_REG_COMM_SERVICE0__A 0xC70003 #define B_FE_CU_REG_COMM_SERVICE0__W 10 #define B_FE_CU_REG_COMM_SERVICE0__M 0x3FF @@ -9990,7 +8756,6 @@ extern "C" { #define B_FE_CU_REG_COMM_INT_STA_NF_READY__W 1 #define B_FE_CU_REG_COMM_INT_STA_NF_READY__M 0x8 - #define B_FE_CU_REG_COMM_INT_MSK__A 0xC70008 #define B_FE_CU_REG_COMM_INT_MSK__W 4 #define B_FE_CU_REG_COMM_INT_MSK__M 0xF @@ -10007,7 +8772,6 @@ extern "C" { #define B_FE_CU_REG_COMM_INT_MSK_NF_READY__W 1 #define B_FE_CU_REG_COMM_INT_MSK_NF_READY__M 0x8 - #define B_FE_CU_REG_MODE__A 0xC70010 #define B_FE_CU_REG_MODE__W 5 #define B_FE_CU_REG_MODE__M 0x1F @@ -10043,19 +8807,16 @@ extern "C" { #define B_FE_CU_REG_MODE_FES_SEL_RST 0x0 #define B_FE_CU_REG_MODE_FES_SEL_UPD 0x10 - #define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 #define B_FE_CU_REG_FRM_CNT_RST__W 15 #define B_FE_CU_REG_FRM_CNT_RST__M 0x7FFF #define B_FE_CU_REG_FRM_CNT_RST_INIT 0x20FF - #define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 #define B_FE_CU_REG_FRM_CNT_STR__W 15 #define B_FE_CU_REG_FRM_CNT_STR__M 0x7FFF #define B_FE_CU_REG_FRM_CNT_STR_INIT 0x1E - #define B_FE_CU_REG_FRM_SMP_CNT__A 0xC70013 #define B_FE_CU_REG_FRM_SMP_CNT__W 15 #define B_FE_CU_REG_FRM_SMP_CNT__M 0x7FFF @@ -10077,19 +8838,16 @@ extern "C" { #define B_FE_CU_REG_BUF_NFC_DEL__M 0x3FFF #define B_FE_CU_REG_BUF_NFC_DEL_INIT 0x0 - #define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 #define B_FE_CU_REG_CTR_NFC_ICR__W 5 #define B_FE_CU_REG_CTR_NFC_ICR__M 0x1F #define B_FE_CU_REG_CTR_NFC_ICR_INIT 0x0 - #define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 #define B_FE_CU_REG_CTR_NFC_OCR__W 15 #define B_FE_CU_REG_CTR_NFC_OCR__M 0x7FFF #define B_FE_CU_REG_CTR_NFC_OCR_INIT 0x61A8 - #define B_FE_CU_REG_CTR_NFC_CNT__A 0xC70022 #define B_FE_CU_REG_CTR_NFC_CNT__W 15 #define B_FE_CU_REG_CTR_NFC_CNT__M 0x7FFF @@ -10102,7 +8860,6 @@ extern "C" { #define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_REA 0x2 #define B_FE_CU_REG_CTR_NFC_STS_CNT_MAX 0x4 - #define B_FE_CU_REG_DIV_NFC_REA__A 0xC70024 #define B_FE_CU_REG_DIV_NFC_REA__W 14 #define B_FE_CU_REG_DIV_NFC_REA__M 0x3FFF @@ -10116,7 +8873,6 @@ extern "C" { #define B_FE_CU_REG_FRM_CNT_UPD__M 0x7FFF #define B_FE_CU_REG_FRM_CNT_UPD_INIT 0x20FF - #define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 #define B_FE_CU_REG_DIV_NFC_CLP__W 2 #define B_FE_CU_REG_DIV_NFC_CLP__M 0x3 @@ -10126,24 +8882,12 @@ extern "C" { #define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S13 0x2 #define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S14 0x3 - - #define B_FE_CU_BUF_RAM__A 0xC80000 - - #define B_FE_CU_CMP_RAM__A 0xC90000 - - - - #define B_FT_SID 0x8 - - - - #define B_FT_COMM_EXEC__A 0x1000000 #define B_FT_COMM_EXEC__W 3 #define B_FT_COMM_EXEC__M 0x7 @@ -10176,11 +8920,6 @@ extern "C" { #define B_FT_COMM_INT_MSK__W 16 #define B_FT_COMM_INT_MSK__M 0xFFFF - - - - - #define B_FT_REG_COMM_EXEC__A 0x1010000 #define B_FT_REG_COMM_EXEC__W 3 #define B_FT_REG_COMM_EXEC__M 0x7 @@ -10192,7 +8931,6 @@ extern "C" { #define B_FT_REG_COMM_EXEC_CTL_HOLD 0x2 #define B_FT_REG_COMM_EXEC_CTL_STEP 0x3 - #define B_FT_REG_COMM_MB__A 0x1010002 #define B_FT_REG_COMM_MB__W 3 #define B_FT_REG_COMM_MB__M 0x7 @@ -10207,7 +8945,6 @@ extern "C" { #define B_FT_REG_COMM_MB_OBS_OFF 0x0 #define B_FT_REG_COMM_MB_OBS_ON 0x2 - #define B_FT_REG_MODE_2K__A 0x1010010 #define B_FT_REG_MODE_2K__W 1 #define B_FT_REG_MODE_2K__M 0x1 @@ -10215,49 +8952,26 @@ extern "C" { #define B_FT_REG_MODE_2K_MODE_2K 0x1 #define B_FT_REG_MODE_2K_INIT 0x0 - #define B_FT_REG_NORM_OFF__A 0x1010016 #define B_FT_REG_NORM_OFF__W 4 #define B_FT_REG_NORM_OFF__M 0xF -#define B_FT_REG_NORM_OFF_INIT 0x2 - - - -#define B_FT_ST1_RAM__A 0x1020000 - - - -#define B_FT_ST2_RAM__A 0x1030000 - - - -#define B_FT_ST3_RAM__A 0x1040000 - - - -#define B_FT_ST5_RAM__A 0x1050000 - - - -#define B_FT_ST6_RAM__A 0x1060000 - - - -#define B_FT_ST8_RAM__A 0x1070000 - - - -#define B_FT_ST9_RAM__A 0x1080000 - +#define B_FT_REG_NORM_OFF_INIT 0x2 +#define B_FT_ST1_RAM__A 0x1020000 +#define B_FT_ST2_RAM__A 0x1030000 +#define B_FT_ST3_RAM__A 0x1040000 -#define B_CP_SID 0x9 +#define B_FT_ST5_RAM__A 0x1050000 +#define B_FT_ST6_RAM__A 0x1060000 +#define B_FT_ST8_RAM__A 0x1070000 +#define B_FT_ST9_RAM__A 0x1080000 +#define B_CP_SID 0x9 #define B_CP_COMM_EXEC__A 0x1400000 #define B_CP_COMM_EXEC__W 3 @@ -10291,11 +9005,6 @@ extern "C" { #define B_CP_COMM_INT_MSK__W 16 #define B_CP_COMM_INT_MSK__M 0xFFFF - - - - - #define B_CP_REG_COMM_EXEC__A 0x1410000 #define B_CP_REG_COMM_EXEC__W 3 #define B_CP_REG_COMM_EXEC__M 0x7 @@ -10307,7 +9016,6 @@ extern "C" { #define B_CP_REG_COMM_EXEC_CTL_HOLD 0x2 #define B_CP_REG_COMM_EXEC_CTL_STEP 0x3 - #define B_CP_REG_COMM_MB__A 0x1410002 #define B_CP_REG_COMM_MB__W 3 #define B_CP_REG_COMM_MB__M 0x7 @@ -10340,7 +9048,6 @@ extern "C" { #define B_CP_REG_COMM_INT_STA_NEW_MEAS__W 1 #define B_CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - #define B_CP_REG_COMM_INT_MSK__A 0x1410008 #define B_CP_REG_COMM_INT_MSK__W 2 #define B_CP_REG_COMM_INT_MSK__M 0x3 @@ -10348,19 +9055,16 @@ extern "C" { #define B_CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 #define B_CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - #define B_CP_REG_MODE_2K__A 0x1410010 #define B_CP_REG_MODE_2K__W 1 #define B_CP_REG_MODE_2K__M 0x1 #define B_CP_REG_MODE_2K_INIT 0x0 - #define B_CP_REG_INTERVAL__A 0x1410011 #define B_CP_REG_INTERVAL__W 4 #define B_CP_REG_INTERVAL__M 0xF #define B_CP_REG_INTERVAL_INIT 0x5 - #define B_CP_REG_DETECT_ENA__A 0x1410012 #define B_CP_REG_DETECT_ENA__W 2 #define B_CP_REG_DETECT_ENA__M 0x3 @@ -10374,7 +9078,6 @@ extern "C" { #define B_CP_REG_DETECT_ENA_CONTINUOUS__M 0x2 #define B_CP_REG_DETECT_ENA_INIT 0x0 - #define B_CP_REG_BR_SMB_NR__A 0x1410021 #define B_CP_REG_BR_SMB_NR__W 4 #define B_CP_REG_BR_SMB_NR__M 0xF @@ -10392,79 +9095,66 @@ extern "C" { #define B_CP_REG_BR_SMB_NR_OFFSET__M 0x8 #define B_CP_REG_BR_SMB_NR_INIT 0x0 - #define B_CP_REG_BR_CP_SMB_NR__A 0x1410022 #define B_CP_REG_BR_CP_SMB_NR__W 2 #define B_CP_REG_BR_CP_SMB_NR__M 0x3 #define B_CP_REG_BR_CP_SMB_NR_INIT 0x0 - #define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 #define B_CP_REG_BR_SPL_OFFSET__W 3 #define B_CP_REG_BR_SPL_OFFSET__M 0x7 #define B_CP_REG_BR_SPL_OFFSET_INIT 0x0 - #define B_CP_REG_BR_STR_DEL__A 0x1410024 #define B_CP_REG_BR_STR_DEL__W 10 #define B_CP_REG_BR_STR_DEL__M 0x3FF #define B_CP_REG_BR_STR_DEL_INIT 0xA - #define B_CP_REG_BR_EXP_ADJ__A 0x1410025 #define B_CP_REG_BR_EXP_ADJ__W 5 #define B_CP_REG_BR_EXP_ADJ__M 0x1F #define B_CP_REG_BR_EXP_ADJ_INIT 0x10 - #define B_CP_REG_RT_ANG_INC0__A 0x1410030 #define B_CP_REG_RT_ANG_INC0__W 16 #define B_CP_REG_RT_ANG_INC0__M 0xFFFF #define B_CP_REG_RT_ANG_INC0_INIT 0x0 - #define B_CP_REG_RT_ANG_INC1__A 0x1410031 #define B_CP_REG_RT_ANG_INC1__W 8 #define B_CP_REG_RT_ANG_INC1__M 0xFF #define B_CP_REG_RT_ANG_INC1_INIT 0x0 - #define B_CP_REG_RT_SPD_EXP_MARG__A 0x1410032 #define B_CP_REG_RT_SPD_EXP_MARG__W 5 #define B_CP_REG_RT_SPD_EXP_MARG__M 0x1F #define B_CP_REG_RT_SPD_EXP_MARG_INIT 0x5 - #define B_CP_REG_RT_DETECT_TRH__A 0x1410033 #define B_CP_REG_RT_DETECT_TRH__W 2 #define B_CP_REG_RT_DETECT_TRH__M 0x3 #define B_CP_REG_RT_DETECT_TRH_INIT 0x3 - #define B_CP_REG_RT_SPD_RELIABLE__A 0x1410034 #define B_CP_REG_RT_SPD_RELIABLE__W 3 #define B_CP_REG_RT_SPD_RELIABLE__M 0x7 #define B_CP_REG_RT_SPD_RELIABLE_INIT 0x0 - #define B_CP_REG_RT_SPD_DIRECTION__A 0x1410035 #define B_CP_REG_RT_SPD_DIRECTION__W 1 #define B_CP_REG_RT_SPD_DIRECTION__M 0x1 #define B_CP_REG_RT_SPD_DIRECTION_INIT 0x0 - #define B_CP_REG_RT_SPD_MOD__A 0x1410036 #define B_CP_REG_RT_SPD_MOD__W 2 #define B_CP_REG_RT_SPD_MOD__M 0x3 #define B_CP_REG_RT_SPD_MOD_INIT 0x0 - #define B_CP_REG_RT_SPD_SMB__A 0x1410037 #define B_CP_REG_RT_SPD_SMB__W 2 #define B_CP_REG_RT_SPD_SMB__M 0x3 #define B_CP_REG_RT_SPD_SMB_INIT 0x0 - #define B_CP_REG_RT_CPD_MODE__A 0x1410038 #define B_CP_REG_RT_CPD_MODE__W 3 #define B_CP_REG_RT_CPD_MODE__M 0x7 @@ -10478,25 +9168,21 @@ extern "C" { #define B_CP_REG_RT_CPD_MODE_ADD__M 0x4 #define B_CP_REG_RT_CPD_MODE_INIT 0x0 - #define B_CP_REG_RT_CPD_RELIABLE__A 0x1410039 #define B_CP_REG_RT_CPD_RELIABLE__W 3 #define B_CP_REG_RT_CPD_RELIABLE__M 0x7 #define B_CP_REG_RT_CPD_RELIABLE_INIT 0x0 - #define B_CP_REG_RT_CPD_BIN__A 0x141003A #define B_CP_REG_RT_CPD_BIN__W 5 #define B_CP_REG_RT_CPD_BIN__M 0x1F #define B_CP_REG_RT_CPD_BIN_INIT 0x0 - #define B_CP_REG_RT_CPD_MAX__A 0x141003B #define B_CP_REG_RT_CPD_MAX__W 4 #define B_CP_REG_RT_CPD_MAX__M 0xF #define B_CP_REG_RT_CPD_MAX_INIT 0x0 - #define B_CP_REG_RT_SUPR_VAL__A 0x141003C #define B_CP_REG_RT_SUPR_VAL__W 2 #define B_CP_REG_RT_SUPR_VAL__M 0x3 @@ -10510,61 +9196,51 @@ extern "C" { #define B_CP_REG_RT_SUPR_VAL_DL__M 0x2 #define B_CP_REG_RT_SUPR_VAL_INIT 0x0 - #define B_CP_REG_RT_EXP_AVE__A 0x141003D #define B_CP_REG_RT_EXP_AVE__W 5 #define B_CP_REG_RT_EXP_AVE__M 0x1F #define B_CP_REG_RT_EXP_AVE_INIT 0x0 - #define B_CP_REG_RT_CPD_EXP_MARG__A 0x141003E #define B_CP_REG_RT_CPD_EXP_MARG__W 5 #define B_CP_REG_RT_CPD_EXP_MARG__M 0x1F #define B_CP_REG_RT_CPD_EXP_MARG_INIT 0x3 - #define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 #define B_CP_REG_AC_NEXP_OFFS__W 8 #define B_CP_REG_AC_NEXP_OFFS__M 0xFF #define B_CP_REG_AC_NEXP_OFFS_INIT 0x0 - #define B_CP_REG_AC_AVER_POW__A 0x1410041 #define B_CP_REG_AC_AVER_POW__W 8 #define B_CP_REG_AC_AVER_POW__M 0xFF #define B_CP_REG_AC_AVER_POW_INIT 0x5F - #define B_CP_REG_AC_MAX_POW__A 0x1410042 #define B_CP_REG_AC_MAX_POW__W 8 #define B_CP_REG_AC_MAX_POW__M 0xFF #define B_CP_REG_AC_MAX_POW_INIT 0x7A - #define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 #define B_CP_REG_AC_WEIGHT_MAN__W 6 #define B_CP_REG_AC_WEIGHT_MAN__M 0x3F #define B_CP_REG_AC_WEIGHT_MAN_INIT 0x31 - #define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 #define B_CP_REG_AC_WEIGHT_EXP__W 5 #define B_CP_REG_AC_WEIGHT_EXP__M 0x1F #define B_CP_REG_AC_WEIGHT_EXP_INIT 0x10 - #define B_CP_REG_AC_GAIN_MAN__A 0x1410045 #define B_CP_REG_AC_GAIN_MAN__W 16 #define B_CP_REG_AC_GAIN_MAN__M 0xFFFF #define B_CP_REG_AC_GAIN_MAN_INIT 0x0 - #define B_CP_REG_AC_GAIN_EXP__A 0x1410046 #define B_CP_REG_AC_GAIN_EXP__W 5 #define B_CP_REG_AC_GAIN_EXP__M 0x1F #define B_CP_REG_AC_GAIN_EXP_INIT 0x0 - #define B_CP_REG_AC_AMP_MODE__A 0x1410047 #define B_CP_REG_AC_AMP_MODE__W 2 #define B_CP_REG_AC_AMP_MODE__M 0x3 @@ -10573,19 +9249,16 @@ extern "C" { #define B_CP_REG_AC_AMP_MODE_FIXED 0x2 #define B_CP_REG_AC_AMP_MODE_INIT 0x2 - #define B_CP_REG_AC_AMP_FIX__A 0x1410048 #define B_CP_REG_AC_AMP_FIX__W 14 #define B_CP_REG_AC_AMP_FIX__M 0x3FFF #define B_CP_REG_AC_AMP_FIX_INIT 0x1FF - #define B_CP_REG_AC_AMP_READ__A 0x1410049 #define B_CP_REG_AC_AMP_READ__W 14 #define B_CP_REG_AC_AMP_READ__M 0x3FFF #define B_CP_REG_AC_AMP_READ_INIT 0x0 - #define B_CP_REG_AC_ANG_MODE__A 0x141004A #define B_CP_REG_AC_ANG_MODE__W 2 #define B_CP_REG_AC_ANG_MODE__M 0x3 @@ -10595,49 +9268,41 @@ extern "C" { #define B_CP_REG_AC_ANG_MODE_OFFSET 0x3 #define B_CP_REG_AC_ANG_MODE_INIT 0x3 - #define B_CP_REG_AC_ANG_OFFS__A 0x141004B #define B_CP_REG_AC_ANG_OFFS__W 14 #define B_CP_REG_AC_ANG_OFFS__M 0x3FFF #define B_CP_REG_AC_ANG_OFFS_INIT 0x0 - #define B_CP_REG_AC_ANG_READ__A 0x141004C #define B_CP_REG_AC_ANG_READ__W 16 #define B_CP_REG_AC_ANG_READ__M 0xFFFF #define B_CP_REG_AC_ANG_READ_INIT 0x0 - #define B_CP_REG_AC_ACCU_REAL0__A 0x1410060 #define B_CP_REG_AC_ACCU_REAL0__W 8 #define B_CP_REG_AC_ACCU_REAL0__M 0xFF #define B_CP_REG_AC_ACCU_REAL0_INIT 0x0 - #define B_CP_REG_AC_ACCU_IMAG0__A 0x1410061 #define B_CP_REG_AC_ACCU_IMAG0__W 8 #define B_CP_REG_AC_ACCU_IMAG0__M 0xFF #define B_CP_REG_AC_ACCU_IMAG0_INIT 0x0 - #define B_CP_REG_AC_ACCU_REAL1__A 0x1410062 #define B_CP_REG_AC_ACCU_REAL1__W 8 #define B_CP_REG_AC_ACCU_REAL1__M 0xFF #define B_CP_REG_AC_ACCU_REAL1_INIT 0x0 - #define B_CP_REG_AC_ACCU_IMAG1__A 0x1410063 #define B_CP_REG_AC_ACCU_IMAG1__W 8 #define B_CP_REG_AC_ACCU_IMAG1__M 0xFF #define B_CP_REG_AC_ACCU_IMAG1_INIT 0x0 - #define B_CP_REG_DL_MB_WR_ADDR__A 0x1410050 #define B_CP_REG_DL_MB_WR_ADDR__W 15 #define B_CP_REG_DL_MB_WR_ADDR__M 0x7FFF #define B_CP_REG_DL_MB_WR_ADDR_INIT 0x0 - #define B_CP_REG_DL_MB_WR_CTR__A 0x1410051 #define B_CP_REG_DL_MB_WR_CTR__W 5 #define B_CP_REG_DL_MB_WR_CTR__M 0x1F @@ -10655,13 +9320,11 @@ extern "C" { #define B_CP_REG_DL_MB_WR_CTR_CTR__M 0x1 #define B_CP_REG_DL_MB_WR_CTR_INIT 0x0 - #define B_CP_REG_DL_MB_RD_ADDR__A 0x1410052 #define B_CP_REG_DL_MB_RD_ADDR__W 15 #define B_CP_REG_DL_MB_RD_ADDR__M 0x7FFF #define B_CP_REG_DL_MB_RD_ADDR_INIT 0x0 - #define B_CP_REG_DL_MB_RD_CTR__A 0x1410053 #define B_CP_REG_DL_MB_RD_CTR__W 11 #define B_CP_REG_DL_MB_RD_CTR__M 0x7FF @@ -10691,36 +9354,18 @@ extern "C" { #define B_CP_REG_DL_MB_RD_CTR_CTR__M 0x1 #define B_CP_REG_DL_MB_RD_CTR_INIT 0x0 - - #define B_CP_BR_BUF_RAM__A 0x1420000 - - #define B_CP_BR_CPL_RAM__A 0x1430000 - - #define B_CP_PB_DL0_RAM__A 0x1440000 - - #define B_CP_PB_DL1_RAM__A 0x1450000 - - #define B_CP_PB_DL2_RAM__A 0x1460000 - - - - #define B_CE_SID 0xA - - - - #define B_CE_COMM_EXEC__A 0x1800000 #define B_CE_COMM_EXEC__W 3 #define B_CE_COMM_EXEC__M 0x7 @@ -10753,11 +9398,6 @@ extern "C" { #define B_CE_COMM_INT_MSK__W 16 #define B_CE_COMM_INT_MSK__M 0xFFFF - - - - - #define B_CE_REG_COMM_EXEC__A 0x1810000 #define B_CE_REG_COMM_EXEC__W 3 #define B_CE_REG_COMM_EXEC__M 0x7 @@ -10769,7 +9409,6 @@ extern "C" { #define B_CE_REG_COMM_EXEC_CTL_HOLD 0x2 #define B_CE_REG_COMM_EXEC_CTL_STEP 0x3 - #define B_CE_REG_COMM_MB__A 0x1810002 #define B_CE_REG_COMM_MB__W 4 #define B_CE_REG_COMM_MB__M 0xF @@ -10815,7 +9454,6 @@ extern "C" { #define B_CE_REG_COMM_INT_STA_CE_FI__W 1 #define B_CE_REG_COMM_INT_STA_CE_FI__M 0x4 - #define B_CE_REG_COMM_INT_MSK__A 0x1810008 #define B_CE_REG_COMM_INT_MSK__W 3 #define B_CE_REG_COMM_INT_MSK__M 0x7 @@ -10829,19 +9467,15 @@ extern "C" { #define B_CE_REG_COMM_INT_MSK_CE_FI__W 1 #define B_CE_REG_COMM_INT_MSK_CE_FI__M 0x4 - #define B_CE_REG_2K__A 0x1810010 #define B_CE_REG_2K__W 1 #define B_CE_REG_2K__M 0x1 #define B_CE_REG_2K_INIT 0x0 - #define B_CE_REG_TAPSET__A 0x1810011 #define B_CE_REG_TAPSET__W 4 #define B_CE_REG_TAPSET__M 0xF - - #define B_CE_REG_TAPSET_MOTION_INIT 0x0 #define B_CE_REG_TAPSET_MOTION_NO 0x0 @@ -10854,43 +9488,36 @@ extern "C" { #define B_CE_REG_TAPSET_MOTION_UNDEFINED 0x8 - #define B_CE_REG_AVG_POW__A 0x1810012 #define B_CE_REG_AVG_POW__W 8 #define B_CE_REG_AVG_POW__M 0xFF #define B_CE_REG_AVG_POW_INIT 0x0 - #define B_CE_REG_MAX_POW__A 0x1810013 #define B_CE_REG_MAX_POW__W 8 #define B_CE_REG_MAX_POW__M 0xFF #define B_CE_REG_MAX_POW_INIT 0x0 - #define B_CE_REG_ATT__A 0x1810014 #define B_CE_REG_ATT__W 8 #define B_CE_REG_ATT__M 0xFF #define B_CE_REG_ATT_INIT 0x0 - #define B_CE_REG_NRED__A 0x1810015 #define B_CE_REG_NRED__W 6 #define B_CE_REG_NRED__M 0x3F #define B_CE_REG_NRED_INIT 0x0 - #define B_CE_REG_PU_SIGN__A 0x1810020 #define B_CE_REG_PU_SIGN__W 1 #define B_CE_REG_PU_SIGN__M 0x1 #define B_CE_REG_PU_SIGN_INIT 0x0 - #define B_CE_REG_PU_MIX__A 0x1810021 #define B_CE_REG_PU_MIX__W 1 #define B_CE_REG_PU_MIX__M 0x1 #define B_CE_REG_PU_MIX_INIT 0x0 - #define B_CE_REG_PB_PILOT_REQ__A 0x1810030 #define B_CE_REG_PB_PILOT_REQ__W 15 #define B_CE_REG_PB_PILOT_REQ__M 0x7FFF @@ -10902,49 +9529,41 @@ extern "C" { #define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 #define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF - #define B_CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 #define B_CE_REG_PB_PILOT_REQ_VALID__W 1 #define B_CE_REG_PB_PILOT_REQ_VALID__M 0x1 #define B_CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 - #define B_CE_REG_PB_FREEZE__A 0x1810032 #define B_CE_REG_PB_FREEZE__W 1 #define B_CE_REG_PB_FREEZE__M 0x1 #define B_CE_REG_PB_FREEZE_INIT 0x0 - #define B_CE_REG_PB_PILOT_EXP__A 0x1810038 #define B_CE_REG_PB_PILOT_EXP__W 4 #define B_CE_REG_PB_PILOT_EXP__M 0xF #define B_CE_REG_PB_PILOT_EXP_INIT 0x0 - #define B_CE_REG_PB_PILOT_REAL__A 0x1810039 #define B_CE_REG_PB_PILOT_REAL__W 10 #define B_CE_REG_PB_PILOT_REAL__M 0x3FF #define B_CE_REG_PB_PILOT_REAL_INIT 0x0 - #define B_CE_REG_PB_PILOT_IMAG__A 0x181003A #define B_CE_REG_PB_PILOT_IMAG__W 10 #define B_CE_REG_PB_PILOT_IMAG__M 0x3FF #define B_CE_REG_PB_PILOT_IMAG_INIT 0x0 - #define B_CE_REG_PB_SMBNR__A 0x181003B #define B_CE_REG_PB_SMBNR__W 5 #define B_CE_REG_PB_SMBNR__M 0x1F #define B_CE_REG_PB_SMBNR_INIT 0x0 - #define B_CE_REG_NE_PILOT_REQ__A 0x1810040 #define B_CE_REG_NE_PILOT_REQ__W 12 #define B_CE_REG_NE_PILOT_REQ__M 0xFFF #define B_CE_REG_NE_PILOT_REQ_INIT 0x0 - #define B_CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 #define B_CE_REG_NE_PILOT_REQ_VALID__W 2 #define B_CE_REG_NE_PILOT_REQ_VALID__M 0x3 @@ -10956,13 +9575,11 @@ extern "C" { #define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 #define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 - #define B_CE_REG_NE_PILOT_DATA__A 0x1810042 #define B_CE_REG_NE_PILOT_DATA__W 10 #define B_CE_REG_NE_PILOT_DATA__M 0x3FF #define B_CE_REG_NE_PILOT_DATA_INIT 0x0 - #define B_CE_REG_NE_ERR_SELECT__A 0x1810043 #define B_CE_REG_NE_ERR_SELECT__W 5 #define B_CE_REG_NE_ERR_SELECT__M 0x1F @@ -10988,31 +9605,26 @@ extern "C" { #define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 #define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 - #define B_CE_REG_NE_TD_CAL__A 0x1810044 #define B_CE_REG_NE_TD_CAL__W 9 #define B_CE_REG_NE_TD_CAL__M 0x1FF #define B_CE_REG_NE_TD_CAL_INIT 0x1E8 - #define B_CE_REG_NE_FD_CAL__A 0x1810045 #define B_CE_REG_NE_FD_CAL__W 9 #define B_CE_REG_NE_FD_CAL__M 0x1FF #define B_CE_REG_NE_FD_CAL_INIT 0x1D9 - #define B_CE_REG_NE_MIXAVG__A 0x1810046 #define B_CE_REG_NE_MIXAVG__W 3 #define B_CE_REG_NE_MIXAVG__M 0x7 #define B_CE_REG_NE_MIXAVG_INIT 0x6 - #define B_CE_REG_NE_NUPD_OFS__A 0x1810047 #define B_CE_REG_NE_NUPD_OFS__W 4 #define B_CE_REG_NE_NUPD_OFS__M 0xF #define B_CE_REG_NE_NUPD_OFS_INIT 0x4 - #define B_CE_REG_NE_TD_POW__A 0x1810048 #define B_CE_REG_NE_TD_POW__W 15 #define B_CE_REG_NE_TD_POW__M 0x7FFF @@ -11026,7 +9638,6 @@ extern "C" { #define B_CE_REG_NE_TD_POW_MANTISSA__W 10 #define B_CE_REG_NE_TD_POW_MANTISSA__M 0x3FF - #define B_CE_REG_NE_FD_POW__A 0x1810049 #define B_CE_REG_NE_FD_POW__W 15 #define B_CE_REG_NE_FD_POW__M 0x7FFF @@ -11040,103 +9651,86 @@ extern "C" { #define B_CE_REG_NE_FD_POW_MANTISSA__W 10 #define B_CE_REG_NE_FD_POW_MANTISSA__M 0x3FF - #define B_CE_REG_NE_NEXP_AVG__A 0x181004A #define B_CE_REG_NE_NEXP_AVG__W 8 #define B_CE_REG_NE_NEXP_AVG__M 0xFF #define B_CE_REG_NE_NEXP_AVG_INIT 0x0 - #define B_CE_REG_NE_OFFSET__A 0x181004B #define B_CE_REG_NE_OFFSET__W 9 #define B_CE_REG_NE_OFFSET__M 0x1FF #define B_CE_REG_NE_OFFSET_INIT 0x0 - #define B_CE_REG_NE_NUPD_TRH__A 0x181004C #define B_CE_REG_NE_NUPD_TRH__W 5 #define B_CE_REG_NE_NUPD_TRH__M 0x1F #define B_CE_REG_NE_NUPD_TRH_INIT 0x14 - #define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 #define B_CE_REG_PE_NEXP_OFFS__W 8 #define B_CE_REG_PE_NEXP_OFFS__M 0xFF #define B_CE_REG_PE_NEXP_OFFS_INIT 0x0 - #define B_CE_REG_PE_TIMESHIFT__A 0x1810051 #define B_CE_REG_PE_TIMESHIFT__W 14 #define B_CE_REG_PE_TIMESHIFT__M 0x3FFF #define B_CE_REG_PE_TIMESHIFT_INIT 0x0 - #define B_CE_REG_PE_DIF_REAL_L__A 0x1810052 #define B_CE_REG_PE_DIF_REAL_L__W 16 #define B_CE_REG_PE_DIF_REAL_L__M 0xFFFF #define B_CE_REG_PE_DIF_REAL_L_INIT 0x0 - #define B_CE_REG_PE_DIF_IMAG_L__A 0x1810053 #define B_CE_REG_PE_DIF_IMAG_L__W 16 #define B_CE_REG_PE_DIF_IMAG_L__M 0xFFFF #define B_CE_REG_PE_DIF_IMAG_L_INIT 0x0 - #define B_CE_REG_PE_DIF_REAL_R__A 0x1810054 #define B_CE_REG_PE_DIF_REAL_R__W 16 #define B_CE_REG_PE_DIF_REAL_R__M 0xFFFF #define B_CE_REG_PE_DIF_REAL_R_INIT 0x0 - #define B_CE_REG_PE_DIF_IMAG_R__A 0x1810055 #define B_CE_REG_PE_DIF_IMAG_R__W 16 #define B_CE_REG_PE_DIF_IMAG_R__M 0xFFFF #define B_CE_REG_PE_DIF_IMAG_R_INIT 0x0 - #define B_CE_REG_PE_ABS_REAL_L__A 0x1810056 #define B_CE_REG_PE_ABS_REAL_L__W 16 #define B_CE_REG_PE_ABS_REAL_L__M 0xFFFF #define B_CE_REG_PE_ABS_REAL_L_INIT 0x0 - #define B_CE_REG_PE_ABS_IMAG_L__A 0x1810057 #define B_CE_REG_PE_ABS_IMAG_L__W 16 #define B_CE_REG_PE_ABS_IMAG_L__M 0xFFFF #define B_CE_REG_PE_ABS_IMAG_L_INIT 0x0 - #define B_CE_REG_PE_ABS_REAL_R__A 0x1810058 #define B_CE_REG_PE_ABS_REAL_R__W 16 #define B_CE_REG_PE_ABS_REAL_R__M 0xFFFF #define B_CE_REG_PE_ABS_REAL_R_INIT 0x0 - #define B_CE_REG_PE_ABS_IMAG_R__A 0x1810059 #define B_CE_REG_PE_ABS_IMAG_R__W 16 #define B_CE_REG_PE_ABS_IMAG_R__M 0xFFFF #define B_CE_REG_PE_ABS_IMAG_R_INIT 0x0 - #define B_CE_REG_PE_ABS_EXP_L__A 0x181005A #define B_CE_REG_PE_ABS_EXP_L__W 5 #define B_CE_REG_PE_ABS_EXP_L__M 0x1F #define B_CE_REG_PE_ABS_EXP_L_INIT 0x0 - #define B_CE_REG_PE_ABS_EXP_R__A 0x181005B #define B_CE_REG_PE_ABS_EXP_R__W 5 #define B_CE_REG_PE_ABS_EXP_R__M 0x1F #define B_CE_REG_PE_ABS_EXP_R_INIT 0x0 - #define B_CE_REG_TP_UPDATE_MODE__A 0x1810060 #define B_CE_REG_TP_UPDATE_MODE__W 1 #define B_CE_REG_TP_UPDATE_MODE__M 0x1 #define B_CE_REG_TP_UPDATE_MODE_INIT 0x0 - #define B_CE_REG_TP_LMS_TAP_ON__A 0x1810061 #define B_CE_REG_TP_LMS_TAP_ON__W 1 #define B_CE_REG_TP_LMS_TAP_ON__M 0x1 @@ -11186,7 +9780,6 @@ extern "C" { #define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 #define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF - #define B_CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D #define B_CE_REG_TP_DOPP_DIFF_ENERGY__W 15 #define B_CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF @@ -11200,7 +9793,6 @@ extern "C" { #define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 #define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF - #define B_CE_REG_TP_A0_TAP_ENERGY__A 0x181006E #define B_CE_REG_TP_A0_TAP_ENERGY__W 15 #define B_CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF @@ -11214,7 +9806,6 @@ extern "C" { #define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 #define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF - #define B_CE_REG_TP_A1_TAP_ENERGY__A 0x181006F #define B_CE_REG_TP_A1_TAP_ENERGY__W 15 #define B_CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF @@ -11228,147 +9819,121 @@ extern "C" { #define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 #define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF - #define B_CE_REG_TI_SYM_CNT__A 0x1810072 #define B_CE_REG_TI_SYM_CNT__W 6 #define B_CE_REG_TI_SYM_CNT__M 0x3F #define B_CE_REG_TI_SYM_CNT_INIT 0x0 - #define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 #define B_CE_REG_TI_PHN_ENABLE__W 1 #define B_CE_REG_TI_PHN_ENABLE__M 0x1 #define B_CE_REG_TI_PHN_ENABLE_INIT 0x0 - #define B_CE_REG_TI_SHIFT__A 0x1810074 #define B_CE_REG_TI_SHIFT__W 2 #define B_CE_REG_TI_SHIFT__M 0x3 #define B_CE_REG_TI_SHIFT_INIT 0x0 - #define B_CE_REG_TI_SLOW__A 0x1810075 #define B_CE_REG_TI_SLOW__W 1 #define B_CE_REG_TI_SLOW__M 0x1 #define B_CE_REG_TI_SLOW_INIT 0x0 - #define B_CE_REG_TI_MGAIN__A 0x1810076 #define B_CE_REG_TI_MGAIN__W 8 #define B_CE_REG_TI_MGAIN__M 0xFF #define B_CE_REG_TI_MGAIN_INIT 0x0 - #define B_CE_REG_TI_ACCU1__A 0x1810077 #define B_CE_REG_TI_ACCU1__W 8 #define B_CE_REG_TI_ACCU1__M 0xFF #define B_CE_REG_TI_ACCU1_INIT 0x0 - #define B_CE_REG_NI_PER_LEFT__A 0x18100B0 #define B_CE_REG_NI_PER_LEFT__W 5 #define B_CE_REG_NI_PER_LEFT__M 0x1F #define B_CE_REG_NI_PER_LEFT_INIT 0xE - #define B_CE_REG_NI_PER_RIGHT__A 0x18100B1 #define B_CE_REG_NI_PER_RIGHT__W 5 #define B_CE_REG_NI_PER_RIGHT__M 0x1F #define B_CE_REG_NI_PER_RIGHT_INIT 0x7 - #define B_CE_REG_NI_POS_LR__A 0x18100B2 #define B_CE_REG_NI_POS_LR__W 9 #define B_CE_REG_NI_POS_LR__M 0x1FF #define B_CE_REG_NI_POS_LR_INIT 0xA0 - #define B_CE_REG_FI_SHT_INCR__A 0x1810090 #define B_CE_REG_FI_SHT_INCR__W 7 #define B_CE_REG_FI_SHT_INCR__M 0x7F #define B_CE_REG_FI_SHT_INCR_INIT 0x9 - #define B_CE_REG_FI_EXP_NORM__A 0x1810091 #define B_CE_REG_FI_EXP_NORM__W 4 #define B_CE_REG_FI_EXP_NORM__M 0xF #define B_CE_REG_FI_EXP_NORM_INIT 0x4 - #define B_CE_REG_FI_SUPR_VAL__A 0x1810092 #define B_CE_REG_FI_SUPR_VAL__W 1 #define B_CE_REG_FI_SUPR_VAL__M 0x1 #define B_CE_REG_FI_SUPR_VAL_INIT 0x1 - #define B_CE_REG_IR_INPUTSEL__A 0x18100A0 #define B_CE_REG_IR_INPUTSEL__W 1 #define B_CE_REG_IR_INPUTSEL__M 0x1 #define B_CE_REG_IR_INPUTSEL_INIT 0x0 - #define B_CE_REG_IR_STARTPOS__A 0x18100A1 #define B_CE_REG_IR_STARTPOS__W 8 #define B_CE_REG_IR_STARTPOS__M 0xFF #define B_CE_REG_IR_STARTPOS_INIT 0x0 - #define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 #define B_CE_REG_IR_NEXP_THRES__W 8 #define B_CE_REG_IR_NEXP_THRES__M 0xFF #define B_CE_REG_IR_NEXP_THRES_INIT 0x0 - #define B_CE_REG_IR_LENGTH__A 0x18100A3 #define B_CE_REG_IR_LENGTH__W 4 #define B_CE_REG_IR_LENGTH__M 0xF #define B_CE_REG_IR_LENGTH_INIT 0x0 - #define B_CE_REG_IR_FREQ__A 0x18100A4 #define B_CE_REG_IR_FREQ__W 11 #define B_CE_REG_IR_FREQ__M 0x7FF #define B_CE_REG_IR_FREQ_INIT 0x0 - #define B_CE_REG_IR_FREQINC__A 0x18100A5 #define B_CE_REG_IR_FREQINC__W 11 #define B_CE_REG_IR_FREQINC__M 0x7FF #define B_CE_REG_IR_FREQINC_INIT 0x0 - #define B_CE_REG_IR_KAISINC__A 0x18100A6 #define B_CE_REG_IR_KAISINC__W 15 #define B_CE_REG_IR_KAISINC__M 0x7FFF #define B_CE_REG_IR_KAISINC_INIT 0x0 - #define B_CE_REG_IR_CTL__A 0x18100A7 #define B_CE_REG_IR_CTL__W 3 #define B_CE_REG_IR_CTL__M 0x7 #define B_CE_REG_IR_CTL_INIT 0x0 - #define B_CE_REG_IR_REAL__A 0x18100A8 #define B_CE_REG_IR_REAL__W 16 #define B_CE_REG_IR_REAL__M 0xFFFF #define B_CE_REG_IR_REAL_INIT 0x0 - #define B_CE_REG_IR_IMAG__A 0x18100A9 #define B_CE_REG_IR_IMAG__W 16 #define B_CE_REG_IR_IMAG__M 0xFFFF #define B_CE_REG_IR_IMAG_INIT 0x0 - #define B_CE_REG_IR_INDEX__A 0x18100AA #define B_CE_REG_IR_INDEX__W 12 #define B_CE_REG_IR_INDEX__M 0xFFF #define B_CE_REG_IR_INDEX_INIT 0x0 - - - #define B_CE_REG_FR_COMM_EXEC__A 0x1820000 #define B_CE_REG_FR_COMM_EXEC__W 1 #define B_CE_REG_FR_COMM_EXEC__M 0x1 @@ -11378,295 +9943,246 @@ extern "C" { #define B_CE_REG_FR_TREAL00__M 0x7FF #define B_CE_REG_FR_TREAL00_INIT 0x52 - #define B_CE_REG_FR_TIMAG00__A 0x1820011 #define B_CE_REG_FR_TIMAG00__W 11 #define B_CE_REG_FR_TIMAG00__M 0x7FF #define B_CE_REG_FR_TIMAG00_INIT 0x0 - #define B_CE_REG_FR_TREAL01__A 0x1820012 #define B_CE_REG_FR_TREAL01__W 11 #define B_CE_REG_FR_TREAL01__M 0x7FF #define B_CE_REG_FR_TREAL01_INIT 0x52 - #define B_CE_REG_FR_TIMAG01__A 0x1820013 #define B_CE_REG_FR_TIMAG01__W 11 #define B_CE_REG_FR_TIMAG01__M 0x7FF #define B_CE_REG_FR_TIMAG01_INIT 0x0 - #define B_CE_REG_FR_TREAL02__A 0x1820014 #define B_CE_REG_FR_TREAL02__W 11 #define B_CE_REG_FR_TREAL02__M 0x7FF #define B_CE_REG_FR_TREAL02_INIT 0x52 - #define B_CE_REG_FR_TIMAG02__A 0x1820015 #define B_CE_REG_FR_TIMAG02__W 11 #define B_CE_REG_FR_TIMAG02__M 0x7FF #define B_CE_REG_FR_TIMAG02_INIT 0x0 - #define B_CE_REG_FR_TREAL03__A 0x1820016 #define B_CE_REG_FR_TREAL03__W 11 #define B_CE_REG_FR_TREAL03__M 0x7FF #define B_CE_REG_FR_TREAL03_INIT 0x52 - #define B_CE_REG_FR_TIMAG03__A 0x1820017 #define B_CE_REG_FR_TIMAG03__W 11 #define B_CE_REG_FR_TIMAG03__M 0x7FF #define B_CE_REG_FR_TIMAG03_INIT 0x0 - #define B_CE_REG_FR_TREAL04__A 0x1820018 #define B_CE_REG_FR_TREAL04__W 11 #define B_CE_REG_FR_TREAL04__M 0x7FF #define B_CE_REG_FR_TREAL04_INIT 0x52 - #define B_CE_REG_FR_TIMAG04__A 0x1820019 #define B_CE_REG_FR_TIMAG04__W 11 #define B_CE_REG_FR_TIMAG04__M 0x7FF #define B_CE_REG_FR_TIMAG04_INIT 0x0 - #define B_CE_REG_FR_TREAL05__A 0x182001A #define B_CE_REG_FR_TREAL05__W 11 #define B_CE_REG_FR_TREAL05__M 0x7FF #define B_CE_REG_FR_TREAL05_INIT 0x52 - #define B_CE_REG_FR_TIMAG05__A 0x182001B #define B_CE_REG_FR_TIMAG05__W 11 #define B_CE_REG_FR_TIMAG05__M 0x7FF #define B_CE_REG_FR_TIMAG05_INIT 0x0 - #define B_CE_REG_FR_TREAL06__A 0x182001C #define B_CE_REG_FR_TREAL06__W 11 #define B_CE_REG_FR_TREAL06__M 0x7FF #define B_CE_REG_FR_TREAL06_INIT 0x52 - #define B_CE_REG_FR_TIMAG06__A 0x182001D #define B_CE_REG_FR_TIMAG06__W 11 #define B_CE_REG_FR_TIMAG06__M 0x7FF #define B_CE_REG_FR_TIMAG06_INIT 0x0 - #define B_CE_REG_FR_TREAL07__A 0x182001E #define B_CE_REG_FR_TREAL07__W 11 #define B_CE_REG_FR_TREAL07__M 0x7FF #define B_CE_REG_FR_TREAL07_INIT 0x52 - #define B_CE_REG_FR_TIMAG07__A 0x182001F #define B_CE_REG_FR_TIMAG07__W 11 #define B_CE_REG_FR_TIMAG07__M 0x7FF #define B_CE_REG_FR_TIMAG07_INIT 0x0 - #define B_CE_REG_FR_TREAL08__A 0x1820020 #define B_CE_REG_FR_TREAL08__W 11 #define B_CE_REG_FR_TREAL08__M 0x7FF #define B_CE_REG_FR_TREAL08_INIT 0x52 - #define B_CE_REG_FR_TIMAG08__A 0x1820021 #define B_CE_REG_FR_TIMAG08__W 11 #define B_CE_REG_FR_TIMAG08__M 0x7FF #define B_CE_REG_FR_TIMAG08_INIT 0x0 - #define B_CE_REG_FR_TREAL09__A 0x1820022 #define B_CE_REG_FR_TREAL09__W 11 #define B_CE_REG_FR_TREAL09__M 0x7FF #define B_CE_REG_FR_TREAL09_INIT 0x52 - #define B_CE_REG_FR_TIMAG09__A 0x1820023 #define B_CE_REG_FR_TIMAG09__W 11 #define B_CE_REG_FR_TIMAG09__M 0x7FF #define B_CE_REG_FR_TIMAG09_INIT 0x0 - #define B_CE_REG_FR_TREAL10__A 0x1820024 #define B_CE_REG_FR_TREAL10__W 11 #define B_CE_REG_FR_TREAL10__M 0x7FF #define B_CE_REG_FR_TREAL10_INIT 0x52 - #define B_CE_REG_FR_TIMAG10__A 0x1820025 #define B_CE_REG_FR_TIMAG10__W 11 #define B_CE_REG_FR_TIMAG10__M 0x7FF #define B_CE_REG_FR_TIMAG10_INIT 0x0 - #define B_CE_REG_FR_TREAL11__A 0x1820026 #define B_CE_REG_FR_TREAL11__W 11 #define B_CE_REG_FR_TREAL11__M 0x7FF #define B_CE_REG_FR_TREAL11_INIT 0x52 - #define B_CE_REG_FR_TIMAG11__A 0x1820027 #define B_CE_REG_FR_TIMAG11__W 11 #define B_CE_REG_FR_TIMAG11__M 0x7FF #define B_CE_REG_FR_TIMAG11_INIT 0x0 - #define B_CE_REG_FR_MID_TAP__A 0x1820028 #define B_CE_REG_FR_MID_TAP__W 11 #define B_CE_REG_FR_MID_TAP__M 0x7FF #define B_CE_REG_FR_MID_TAP_INIT 0x51 - #define B_CE_REG_FR_SQS_G00__A 0x1820029 #define B_CE_REG_FR_SQS_G00__W 8 #define B_CE_REG_FR_SQS_G00__M 0xFF #define B_CE_REG_FR_SQS_G00_INIT 0xB - #define B_CE_REG_FR_SQS_G01__A 0x182002A #define B_CE_REG_FR_SQS_G01__W 8 #define B_CE_REG_FR_SQS_G01__M 0xFF #define B_CE_REG_FR_SQS_G01_INIT 0xB - #define B_CE_REG_FR_SQS_G02__A 0x182002B #define B_CE_REG_FR_SQS_G02__W 8 #define B_CE_REG_FR_SQS_G02__M 0xFF #define B_CE_REG_FR_SQS_G02_INIT 0xB - #define B_CE_REG_FR_SQS_G03__A 0x182002C #define B_CE_REG_FR_SQS_G03__W 8 #define B_CE_REG_FR_SQS_G03__M 0xFF #define B_CE_REG_FR_SQS_G03_INIT 0xB - #define B_CE_REG_FR_SQS_G04__A 0x182002D #define B_CE_REG_FR_SQS_G04__W 8 #define B_CE_REG_FR_SQS_G04__M 0xFF #define B_CE_REG_FR_SQS_G04_INIT 0xB - #define B_CE_REG_FR_SQS_G05__A 0x182002E #define B_CE_REG_FR_SQS_G05__W 8 #define B_CE_REG_FR_SQS_G05__M 0xFF #define B_CE_REG_FR_SQS_G05_INIT 0xB - #define B_CE_REG_FR_SQS_G06__A 0x182002F #define B_CE_REG_FR_SQS_G06__W 8 #define B_CE_REG_FR_SQS_G06__M 0xFF #define B_CE_REG_FR_SQS_G06_INIT 0xB - #define B_CE_REG_FR_SQS_G07__A 0x1820030 #define B_CE_REG_FR_SQS_G07__W 8 #define B_CE_REG_FR_SQS_G07__M 0xFF #define B_CE_REG_FR_SQS_G07_INIT 0xB - #define B_CE_REG_FR_SQS_G08__A 0x1820031 #define B_CE_REG_FR_SQS_G08__W 8 #define B_CE_REG_FR_SQS_G08__M 0xFF #define B_CE_REG_FR_SQS_G08_INIT 0xB - #define B_CE_REG_FR_SQS_G09__A 0x1820032 #define B_CE_REG_FR_SQS_G09__W 8 #define B_CE_REG_FR_SQS_G09__M 0xFF #define B_CE_REG_FR_SQS_G09_INIT 0xB - #define B_CE_REG_FR_SQS_G10__A 0x1820033 #define B_CE_REG_FR_SQS_G10__W 8 #define B_CE_REG_FR_SQS_G10__M 0xFF #define B_CE_REG_FR_SQS_G10_INIT 0xB - #define B_CE_REG_FR_SQS_G11__A 0x1820034 #define B_CE_REG_FR_SQS_G11__W 8 #define B_CE_REG_FR_SQS_G11__M 0xFF #define B_CE_REG_FR_SQS_G11_INIT 0xB - #define B_CE_REG_FR_SQS_G12__A 0x1820035 #define B_CE_REG_FR_SQS_G12__W 8 #define B_CE_REG_FR_SQS_G12__M 0xFF #define B_CE_REG_FR_SQS_G12_INIT 0x5 - #define B_CE_REG_FR_RIO_G00__A 0x1820036 #define B_CE_REG_FR_RIO_G00__W 9 #define B_CE_REG_FR_RIO_G00__M 0x1FF #define B_CE_REG_FR_RIO_G00_INIT 0x1FF - #define B_CE_REG_FR_RIO_G01__A 0x1820037 #define B_CE_REG_FR_RIO_G01__W 9 #define B_CE_REG_FR_RIO_G01__M 0x1FF #define B_CE_REG_FR_RIO_G01_INIT 0x190 - #define B_CE_REG_FR_RIO_G02__A 0x1820038 #define B_CE_REG_FR_RIO_G02__W 9 #define B_CE_REG_FR_RIO_G02__M 0x1FF #define B_CE_REG_FR_RIO_G02_INIT 0x10B - #define B_CE_REG_FR_RIO_G03__A 0x1820039 #define B_CE_REG_FR_RIO_G03__W 9 #define B_CE_REG_FR_RIO_G03__M 0x1FF #define B_CE_REG_FR_RIO_G03_INIT 0xC8 - #define B_CE_REG_FR_RIO_G04__A 0x182003A #define B_CE_REG_FR_RIO_G04__W 9 #define B_CE_REG_FR_RIO_G04__M 0x1FF #define B_CE_REG_FR_RIO_G04_INIT 0xA0 - #define B_CE_REG_FR_RIO_G05__A 0x182003B #define B_CE_REG_FR_RIO_G05__W 9 #define B_CE_REG_FR_RIO_G05__M 0x1FF #define B_CE_REG_FR_RIO_G05_INIT 0x85 - #define B_CE_REG_FR_RIO_G06__A 0x182003C #define B_CE_REG_FR_RIO_G06__W 9 #define B_CE_REG_FR_RIO_G06__M 0x1FF #define B_CE_REG_FR_RIO_G06_INIT 0x72 - #define B_CE_REG_FR_RIO_G07__A 0x182003D #define B_CE_REG_FR_RIO_G07__W 9 #define B_CE_REG_FR_RIO_G07__M 0x1FF #define B_CE_REG_FR_RIO_G07_INIT 0x64 - #define B_CE_REG_FR_RIO_G08__A 0x182003E #define B_CE_REG_FR_RIO_G08__W 9 #define B_CE_REG_FR_RIO_G08__M 0x1FF #define B_CE_REG_FR_RIO_G08_INIT 0x59 - #define B_CE_REG_FR_RIO_G09__A 0x182003F #define B_CE_REG_FR_RIO_G09__W 9 #define B_CE_REG_FR_RIO_G09__M 0x1FF #define B_CE_REG_FR_RIO_G09_INIT 0x50 - #define B_CE_REG_FR_RIO_G10__A 0x1820040 #define B_CE_REG_FR_RIO_G10__W 9 #define B_CE_REG_FR_RIO_G10__M 0x1FF #define B_CE_REG_FR_RIO_G10_INIT 0x49 - #define B_CE_REG_FR_MODE__A 0x1820041 #define B_CE_REG_FR_MODE__W 9 #define B_CE_REG_FR_MODE__M 0x1FF @@ -11708,19 +10224,16 @@ extern "C" { #define B_CE_REG_FR_MODE_NOTCH_MODE__M 0x100 #define B_CE_REG_FR_MODE_INIT 0xDE - #define B_CE_REG_FR_SQS_TRH__A 0x1820042 #define B_CE_REG_FR_SQS_TRH__W 8 #define B_CE_REG_FR_SQS_TRH__M 0xFF #define B_CE_REG_FR_SQS_TRH_INIT 0x80 - #define B_CE_REG_FR_RIO_GAIN__A 0x1820043 #define B_CE_REG_FR_RIO_GAIN__W 3 #define B_CE_REG_FR_RIO_GAIN__M 0x7 #define B_CE_REG_FR_RIO_GAIN_INIT 0x2 - #define B_CE_REG_FR_BYPASS__A 0x1820044 #define B_CE_REG_FR_BYPASS__W 10 #define B_CE_REG_FR_BYPASS__M 0x3FF @@ -11738,66 +10251,47 @@ extern "C" { #define B_CE_REG_FR_BYPASS_TOTAL__M 0x200 #define B_CE_REG_FR_BYPASS_INIT 0x13B - #define B_CE_REG_FR_PM_SET__A 0x1820045 #define B_CE_REG_FR_PM_SET__W 4 #define B_CE_REG_FR_PM_SET__M 0xF #define B_CE_REG_FR_PM_SET_INIT 0x4 - #define B_CE_REG_FR_ERR_SH__A 0x1820046 #define B_CE_REG_FR_ERR_SH__W 4 #define B_CE_REG_FR_ERR_SH__M 0xF #define B_CE_REG_FR_ERR_SH_INIT 0x4 - #define B_CE_REG_FR_MAN_SH__A 0x1820047 #define B_CE_REG_FR_MAN_SH__W 4 #define B_CE_REG_FR_MAN_SH__M 0xF #define B_CE_REG_FR_MAN_SH_INIT 0x7 - #define B_CE_REG_FR_TAP_SH__A 0x1820048 #define B_CE_REG_FR_TAP_SH__W 3 #define B_CE_REG_FR_TAP_SH__M 0x7 #define B_CE_REG_FR_TAP_SH_INIT 0x3 - #define B_CE_REG_FR_CLIP__A 0x1820049 #define B_CE_REG_FR_CLIP__W 9 #define B_CE_REG_FR_CLIP__M 0x1FF #define B_CE_REG_FR_CLIP_INIT 0x49 - #define B_CE_REG_FR_LEAK_UPD__A 0x182004A #define B_CE_REG_FR_LEAK_UPD__W 3 #define B_CE_REG_FR_LEAK_UPD__M 0x7 #define B_CE_REG_FR_LEAK_UPD_INIT 0x1 - #define B_CE_REG_FR_LEAK_SH__A 0x182004B #define B_CE_REG_FR_LEAK_SH__W 3 #define B_CE_REG_FR_LEAK_SH__M 0x7 #define B_CE_REG_FR_LEAK_SH_INIT 0x1 - - #define B_CE_PB_RAM__A 0x1830000 - - #define B_CE_NE_RAM__A 0x1840000 - - - - #define B_EQ_SID 0xE - - - - #define B_EQ_COMM_EXEC__A 0x1C00000 #define B_EQ_COMM_EXEC__W 3 #define B_EQ_COMM_EXEC__M 0x7 @@ -11830,11 +10324,6 @@ extern "C" { #define B_EQ_COMM_INT_MSK__W 16 #define B_EQ_COMM_INT_MSK__M 0xFFFF - - - - - #define B_EQ_REG_COMM_EXEC__A 0x1C10000 #define B_EQ_REG_COMM_EXEC__W 3 #define B_EQ_REG_COMM_EXEC__M 0x7 @@ -11877,7 +10366,6 @@ extern "C" { #define B_EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 #define B_EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 - #define B_EQ_REG_COMM_SERVICE0__A 0x1C10003 #define B_EQ_REG_COMM_SERVICE0__W 10 #define B_EQ_REG_COMM_SERVICE0__M 0x3FF @@ -11896,7 +10384,6 @@ extern "C" { #define B_EQ_REG_COMM_INT_STA_ERR_RDY__W 1 #define B_EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 - #define B_EQ_REG_COMM_INT_MSK__A 0x1C10008 #define B_EQ_REG_COMM_INT_MSK__W 2 #define B_EQ_REG_COMM_INT_MSK__M 0x3 @@ -11907,7 +10394,6 @@ extern "C" { #define B_EQ_REG_COMM_INT_MSK_MER_RDY__W 1 #define B_EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 - #define B_EQ_REG_IS_MODE__A 0x1C10014 #define B_EQ_REG_IS_MODE__W 4 #define B_EQ_REG_IS_MODE__M 0xF @@ -11925,25 +10411,21 @@ extern "C" { #define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 #define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 - #define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 #define B_EQ_REG_IS_GAIN_MAN__W 10 #define B_EQ_REG_IS_GAIN_MAN__M 0x3FF #define B_EQ_REG_IS_GAIN_MAN_INIT 0x114 - #define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 #define B_EQ_REG_IS_GAIN_EXP__W 5 #define B_EQ_REG_IS_GAIN_EXP__M 0x1F #define B_EQ_REG_IS_GAIN_EXP_INIT 0x5 - #define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 #define B_EQ_REG_IS_CLIP_EXP__W 5 #define B_EQ_REG_IS_CLIP_EXP__M 0x1F #define B_EQ_REG_IS_CLIP_EXP_INIT 0x10 - #define B_EQ_REG_DV_MODE__A 0x1C1001E #define B_EQ_REG_DV_MODE__W 4 #define B_EQ_REG_DV_MODE__M 0xF @@ -11973,7 +10455,6 @@ extern "C" { #define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 #define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 - #define B_EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F #define B_EQ_REG_DV_POS_CLIP_DAT__W 16 #define B_EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF @@ -12031,31 +10512,26 @@ extern "C" { #define B_EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 #define B_EQ_REG_SN_MODE_MODE_7_STATIC 0x80 - #define B_EQ_REG_SN_PFIX__A 0x1C10029 #define B_EQ_REG_SN_PFIX__W 8 #define B_EQ_REG_SN_PFIX__M 0xFF #define B_EQ_REG_SN_PFIX_INIT 0x0 - #define B_EQ_REG_SN_CEGAIN__A 0x1C1002A #define B_EQ_REG_SN_CEGAIN__W 8 #define B_EQ_REG_SN_CEGAIN__M 0xFF #define B_EQ_REG_SN_CEGAIN_INIT 0x30 - #define B_EQ_REG_SN_OFFSET__A 0x1C1002B #define B_EQ_REG_SN_OFFSET__W 6 #define B_EQ_REG_SN_OFFSET__M 0x3F #define B_EQ_REG_SN_OFFSET_INIT 0x39 - #define B_EQ_REG_SN_NULLIFY__A 0x1C1002C #define B_EQ_REG_SN_NULLIFY__W 6 #define B_EQ_REG_SN_NULLIFY__M 0x3F #define B_EQ_REG_SN_NULLIFY_INIT 0x0 - #define B_EQ_REG_SN_SQUASH__A 0x1C1002D #define B_EQ_REG_SN_SQUASH__W 10 #define B_EQ_REG_SN_SQUASH__M 0x3FF @@ -12069,9 +10545,6 @@ extern "C" { #define B_EQ_REG_SN_SQUASH_EXP__W 4 #define B_EQ_REG_SN_SQUASH_EXP__M 0x3C0 - - - #define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 #define B_EQ_REG_RC_SEL_CAR__W 8 #define B_EQ_REG_RC_SEL_CAR__M 0xFF @@ -12112,7 +10585,6 @@ extern "C" { #define B_EQ_REG_RC_SEL_CAR_FFTMODE_2K 0x0 #define B_EQ_REG_RC_SEL_CAR_FFTMODE_8K 0x80 - #define B_EQ_REG_RC_STS__A 0x1C10033 #define B_EQ_REG_RC_STS__W 14 #define B_EQ_REG_RC_STS__M 0x3FFF @@ -12151,49 +10623,41 @@ extern "C" { #define B_EQ_REG_RC_STS_DRI_PRS_NO 0x0 #define B_EQ_REG_RC_STS_DRI_PRS_YES 0x2000 - #define B_EQ_REG_OT_CONST__A 0x1C10046 #define B_EQ_REG_OT_CONST__W 2 #define B_EQ_REG_OT_CONST__M 0x3 #define B_EQ_REG_OT_CONST_INIT 0x2 - #define B_EQ_REG_OT_ALPHA__A 0x1C10047 #define B_EQ_REG_OT_ALPHA__W 2 #define B_EQ_REG_OT_ALPHA__M 0x3 #define B_EQ_REG_OT_ALPHA_INIT 0x0 - #define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 #define B_EQ_REG_OT_QNT_THRES0__W 5 #define B_EQ_REG_OT_QNT_THRES0__M 0x1F #define B_EQ_REG_OT_QNT_THRES0_INIT 0x1E - #define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 #define B_EQ_REG_OT_QNT_THRES1__W 5 #define B_EQ_REG_OT_QNT_THRES1__M 0x1F #define B_EQ_REG_OT_QNT_THRES1_INIT 0x1F - #define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A #define B_EQ_REG_OT_CSI_STEP__W 4 #define B_EQ_REG_OT_CSI_STEP__M 0xF #define B_EQ_REG_OT_CSI_STEP_INIT 0x5 - #define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B #define B_EQ_REG_OT_CSI_OFFSET__W 7 #define B_EQ_REG_OT_CSI_OFFSET__M 0x7F #define B_EQ_REG_OT_CSI_OFFSET_INIT 0x5 - #define B_EQ_REG_OT_CSI_GAIN__A 0x1C1004C #define B_EQ_REG_OT_CSI_GAIN__W 8 #define B_EQ_REG_OT_CSI_GAIN__M 0xFF #define B_EQ_REG_OT_CSI_GAIN_INIT 0x2B - #define B_EQ_REG_OT_CSI_MEAN__A 0x1C1004D #define B_EQ_REG_OT_CSI_MEAN__W 7 #define B_EQ_REG_OT_CSI_MEAN__M 0x7F @@ -12202,9 +10666,6 @@ extern "C" { #define B_EQ_REG_OT_CSI_VARIANCE__W 7 #define B_EQ_REG_OT_CSI_VARIANCE__M 0x7F - - - #define B_EQ_REG_TD_TPS_INIT__A 0x1C10050 #define B_EQ_REG_TD_TPS_INIT__W 1 #define B_EQ_REG_TD_TPS_INIT__M 0x1 @@ -12212,7 +10673,6 @@ extern "C" { #define B_EQ_REG_TD_TPS_INIT_POS 0x0 #define B_EQ_REG_TD_TPS_INIT_NEG 0x1 - #define B_EQ_REG_TD_TPS_SYNC__A 0x1C10051 #define B_EQ_REG_TD_TPS_SYNC__W 16 #define B_EQ_REG_TD_TPS_SYNC__M 0xFFFF @@ -12220,7 +10680,6 @@ extern "C" { #define B_EQ_REG_TD_TPS_SYNC_ODD 0x35EE #define B_EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 - #define B_EQ_REG_TD_TPS_LEN__A 0x1C10052 #define B_EQ_REG_TD_TPS_LEN__W 6 #define B_EQ_REG_TD_TPS_LEN__M 0x3F @@ -12228,7 +10687,6 @@ extern "C" { #define B_EQ_REG_TD_TPS_LEN_DEF 0x17 #define B_EQ_REG_TD_TPS_LEN_ID_SUP 0x1F - #define B_EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 #define B_EQ_REG_TD_TPS_FRM_NMB__W 2 #define B_EQ_REG_TD_TPS_FRM_NMB__M 0x3 @@ -12238,7 +10696,6 @@ extern "C" { #define B_EQ_REG_TD_TPS_FRM_NMB_3 0x2 #define B_EQ_REG_TD_TPS_FRM_NMB_4 0x3 - #define B_EQ_REG_TD_TPS_CONST__A 0x1C10054 #define B_EQ_REG_TD_TPS_CONST__W 2 #define B_EQ_REG_TD_TPS_CONST__M 0x3 @@ -12247,7 +10704,6 @@ extern "C" { #define B_EQ_REG_TD_TPS_CONST_16QAM 0x1 #define B_EQ_REG_TD_TPS_CONST_64QAM 0x2 - #define B_EQ_REG_TD_TPS_HINFO__A 0x1C10055 #define B_EQ_REG_TD_TPS_HINFO__W 3 #define B_EQ_REG_TD_TPS_HINFO__M 0x7 @@ -12257,7 +10713,6 @@ extern "C" { #define B_EQ_REG_TD_TPS_HINFO_H2 0x2 #define B_EQ_REG_TD_TPS_HINFO_H4 0x3 - #define B_EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 #define B_EQ_REG_TD_TPS_CODE_HP__W 3 #define B_EQ_REG_TD_TPS_CODE_HP__M 0x7 @@ -12268,7 +10723,6 @@ extern "C" { #define B_EQ_REG_TD_TPS_CODE_HP_5_6 0x3 #define B_EQ_REG_TD_TPS_CODE_HP_7_8 0x4 - #define B_EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 #define B_EQ_REG_TD_TPS_CODE_LP__W 3 #define B_EQ_REG_TD_TPS_CODE_LP__M 0x7 @@ -12279,7 +10733,6 @@ extern "C" { #define B_EQ_REG_TD_TPS_CODE_LP_5_6 0x3 #define B_EQ_REG_TD_TPS_CODE_LP_7_8 0x4 - #define B_EQ_REG_TD_TPS_GUARD__A 0x1C10058 #define B_EQ_REG_TD_TPS_GUARD__W 2 #define B_EQ_REG_TD_TPS_GUARD__M 0x3 @@ -12289,7 +10742,6 @@ extern "C" { #define B_EQ_REG_TD_TPS_GUARD_08 0x2 #define B_EQ_REG_TD_TPS_GUARD_04 0x3 - #define B_EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 #define B_EQ_REG_TD_TPS_TR_MODE__W 2 #define B_EQ_REG_TD_TPS_TR_MODE__M 0x3 @@ -12297,68 +10749,51 @@ extern "C" { #define B_EQ_REG_TD_TPS_TR_MODE_2K 0x0 #define B_EQ_REG_TD_TPS_TR_MODE_8K 0x1 - #define B_EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A #define B_EQ_REG_TD_TPS_CELL_ID_HI__W 8 #define B_EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF #define B_EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 - #define B_EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B #define B_EQ_REG_TD_TPS_CELL_ID_LO__W 8 #define B_EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF #define B_EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 - #define B_EQ_REG_TD_TPS_RSV__A 0x1C1005C #define B_EQ_REG_TD_TPS_RSV__W 6 #define B_EQ_REG_TD_TPS_RSV__M 0x3F #define B_EQ_REG_TD_TPS_RSV_INIT 0x0 - #define B_EQ_REG_TD_TPS_BCH__A 0x1C1005D #define B_EQ_REG_TD_TPS_BCH__W 14 #define B_EQ_REG_TD_TPS_BCH__M 0x3FFF #define B_EQ_REG_TD_TPS_BCH_INIT 0x0 - #define B_EQ_REG_TD_SQR_ERR_I__A 0x1C1005E #define B_EQ_REG_TD_SQR_ERR_I__W 16 #define B_EQ_REG_TD_SQR_ERR_I__M 0xFFFF #define B_EQ_REG_TD_SQR_ERR_I_INIT 0x0 - #define B_EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F #define B_EQ_REG_TD_SQR_ERR_Q__W 16 #define B_EQ_REG_TD_SQR_ERR_Q__M 0xFFFF #define B_EQ_REG_TD_SQR_ERR_Q_INIT 0x0 - #define B_EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 #define B_EQ_REG_TD_SQR_ERR_EXP__W 4 #define B_EQ_REG_TD_SQR_ERR_EXP__M 0xF #define B_EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 - #define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 #define B_EQ_REG_TD_REQ_SMB_CNT__W 16 #define B_EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF #define B_EQ_REG_TD_REQ_SMB_CNT_INIT 0x200 - #define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 #define B_EQ_REG_TD_TPS_PWR_OFS__W 16 #define B_EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF #define B_EQ_REG_TD_TPS_PWR_OFS_INIT 0x19F - - - - - - - - #define B_EC_COMM_EXEC__A 0x2000000 #define B_EC_COMM_EXEC__W 3 #define B_EC_COMM_EXEC__M 0x7 @@ -12391,16 +10826,8 @@ extern "C" { #define B_EC_COMM_INT_MSK__W 16 #define B_EC_COMM_INT_MSK__M 0xFFFF - - - - #define B_EC_SB_SID 0x16 - - - - #define B_EC_SB_REG_COMM_EXEC__A 0x2010000 #define B_EC_SB_REG_COMM_EXEC__W 3 #define B_EC_SB_REG_COMM_EXEC__M 0x7 @@ -12428,7 +10855,6 @@ extern "C" { #define B_EC_SB_REG_COMM_MB_OBS_OFF 0x0 #define B_EC_SB_REG_COMM_MB_OBS_ON 0x2 - #define B_EC_SB_REG_TR_MODE__A 0x2010010 #define B_EC_SB_REG_TR_MODE__W 1 #define B_EC_SB_REG_TR_MODE__M 0x1 @@ -12436,7 +10862,6 @@ extern "C" { #define B_EC_SB_REG_TR_MODE_8K 0x0 #define B_EC_SB_REG_TR_MODE_2K 0x1 - #define B_EC_SB_REG_CONST__A 0x2010011 #define B_EC_SB_REG_CONST__W 2 #define B_EC_SB_REG_CONST__M 0x3 @@ -12445,7 +10870,6 @@ extern "C" { #define B_EC_SB_REG_CONST_16QAM 0x1 #define B_EC_SB_REG_CONST_64QAM 0x2 - #define B_EC_SB_REG_ALPHA__A 0x2010012 #define B_EC_SB_REG_ALPHA__W 3 #define B_EC_SB_REG_ALPHA__M 0x7 @@ -12460,7 +10884,6 @@ extern "C" { #define B_EC_SB_REG_ALPHA_H4 0x3 - #define B_EC_SB_REG_PRIOR__A 0x2010013 #define B_EC_SB_REG_PRIOR__W 1 #define B_EC_SB_REG_PRIOR__M 0x1 @@ -12468,7 +10891,6 @@ extern "C" { #define B_EC_SB_REG_PRIOR_HI 0x0 #define B_EC_SB_REG_PRIOR_LO 0x1 - #define B_EC_SB_REG_CSI_HI__A 0x2010014 #define B_EC_SB_REG_CSI_HI__W 5 #define B_EC_SB_REG_CSI_HI__M 0x1F @@ -12477,7 +10899,6 @@ extern "C" { #define B_EC_SB_REG_CSI_HI_MIN 0x0 #define B_EC_SB_REG_CSI_HI_TAG 0x0 - #define B_EC_SB_REG_CSI_LO__A 0x2010015 #define B_EC_SB_REG_CSI_LO__W 5 #define B_EC_SB_REG_CSI_LO__M 0x1F @@ -12486,7 +10907,6 @@ extern "C" { #define B_EC_SB_REG_CSI_LO_MIN 0x0 #define B_EC_SB_REG_CSI_LO_TAG 0x0 - #define B_EC_SB_REG_SMB_TGL__A 0x2010016 #define B_EC_SB_REG_SMB_TGL__W 1 #define B_EC_SB_REG_SMB_TGL__M 0x1 @@ -12494,7 +10914,6 @@ extern "C" { #define B_EC_SB_REG_SMB_TGL_ON 0x1 #define B_EC_SB_REG_SMB_TGL_INIT 0x1 - #define B_EC_SB_REG_SNR_HI__A 0x2010017 #define B_EC_SB_REG_SNR_HI__W 8 #define B_EC_SB_REG_SNR_HI__M 0xFF @@ -12503,7 +10922,6 @@ extern "C" { #define B_EC_SB_REG_SNR_HI_MIN 0x0 #define B_EC_SB_REG_SNR_HI_TAG 0x0 - #define B_EC_SB_REG_SNR_MID__A 0x2010018 #define B_EC_SB_REG_SNR_MID__W 8 #define B_EC_SB_REG_SNR_MID__M 0xFF @@ -12512,7 +10930,6 @@ extern "C" { #define B_EC_SB_REG_SNR_MID_MIN 0x0 #define B_EC_SB_REG_SNR_MID_TAG 0x0 - #define B_EC_SB_REG_SNR_LO__A 0x2010019 #define B_EC_SB_REG_SNR_LO__W 8 #define B_EC_SB_REG_SNR_LO__M 0xFF @@ -12521,91 +10938,67 @@ extern "C" { #define B_EC_SB_REG_SNR_LO_MIN 0x0 #define B_EC_SB_REG_SNR_LO_TAG 0x0 - #define B_EC_SB_REG_SCALE_MSB__A 0x201001A #define B_EC_SB_REG_SCALE_MSB__W 6 #define B_EC_SB_REG_SCALE_MSB__M 0x3F #define B_EC_SB_REG_SCALE_MSB_INIT 0x30 #define B_EC_SB_REG_SCALE_MSB_MAX 0x3F - #define B_EC_SB_REG_SCALE_BIT2__A 0x201001B #define B_EC_SB_REG_SCALE_BIT2__W 6 #define B_EC_SB_REG_SCALE_BIT2__M 0x3F #define B_EC_SB_REG_SCALE_BIT2_INIT 0xC #define B_EC_SB_REG_SCALE_BIT2_MAX 0x3F - #define B_EC_SB_REG_SCALE_LSB__A 0x201001C #define B_EC_SB_REG_SCALE_LSB__W 6 #define B_EC_SB_REG_SCALE_LSB__M 0x3F #define B_EC_SB_REG_SCALE_LSB_INIT 0x3 #define B_EC_SB_REG_SCALE_LSB_MAX 0x3F - #define B_EC_SB_REG_CSI_OFS0__A 0x201001D #define B_EC_SB_REG_CSI_OFS0__W 4 #define B_EC_SB_REG_CSI_OFS0__M 0xF #define B_EC_SB_REG_CSI_OFS0_INIT 0x4 - #define B_EC_SB_REG_CSI_OFS1__A 0x201001E #define B_EC_SB_REG_CSI_OFS1__W 4 #define B_EC_SB_REG_CSI_OFS1__M 0xF #define B_EC_SB_REG_CSI_OFS1_INIT 0x1 - #define B_EC_SB_REG_CSI_OFS2__A 0x201001F #define B_EC_SB_REG_CSI_OFS2__W 4 #define B_EC_SB_REG_CSI_OFS2__M 0xF #define B_EC_SB_REG_CSI_OFS2_INIT 0x2 - #define B_EC_SB_REG_MAX0__A 0x2010020 #define B_EC_SB_REG_MAX0__W 6 #define B_EC_SB_REG_MAX0__M 0x3F #define B_EC_SB_REG_MAX0_INIT 0x3F - #define B_EC_SB_REG_MAX1__A 0x2010021 #define B_EC_SB_REG_MAX1__W 6 #define B_EC_SB_REG_MAX1__M 0x3F #define B_EC_SB_REG_MAX1_INIT 0x3F - #define B_EC_SB_REG_MAX2__A 0x2010022 #define B_EC_SB_REG_MAX2__W 6 #define B_EC_SB_REG_MAX2__M 0x3F #define B_EC_SB_REG_MAX2_INIT 0x3F - #define B_EC_SB_REG_CSI_DIS__A 0x2010023 #define B_EC_SB_REG_CSI_DIS__W 1 #define B_EC_SB_REG_CSI_DIS__M 0x1 #define B_EC_SB_REG_CSI_DIS_INIT 0x0 - - #define B_EC_SB_SD_RAM__A 0x2020000 - - #define B_EC_SB_BD0_RAM__A 0x2030000 - - #define B_EC_SB_BD1_RAM__A 0x2040000 - - - - #define B_EC_VD_SID 0x17 - - - - #define B_EC_VD_REG_COMM_EXEC__A 0x2090000 #define B_EC_VD_REG_COMM_EXEC__W 3 #define B_EC_VD_REG_COMM_EXEC__M 0x7 @@ -12653,7 +11046,6 @@ extern "C" { #define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 #define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 - #define B_EC_VD_REG_FORCE__A 0x2090010 #define B_EC_VD_REG_FORCE__W 2 #define B_EC_VD_REG_FORCE__M 0x3 @@ -12663,7 +11055,6 @@ extern "C" { #define B_EC_VD_REG_FORCE_FORCED 0x2 #define B_EC_VD_REG_FORCE_FIXED 0x3 - #define B_EC_VD_REG_SET_CODERATE__A 0x2090011 #define B_EC_VD_REG_SET_CODERATE__W 3 #define B_EC_VD_REG_SET_CODERATE__M 0x7 @@ -12674,19 +11065,16 @@ extern "C" { #define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 #define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 - #define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 #define B_EC_VD_REG_REQ_SMB_CNT__W 16 #define B_EC_VD_REG_REQ_SMB_CNT__M 0xFFFF #define B_EC_VD_REG_REQ_SMB_CNT_INIT 0x1 - #define B_EC_VD_REG_REQ_BIT_CNT__A 0x2090013 #define B_EC_VD_REG_REQ_BIT_CNT__W 16 #define B_EC_VD_REG_REQ_BIT_CNT__M 0xFFFF #define B_EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF - #define B_EC_VD_REG_RLK_ENA__A 0x2090014 #define B_EC_VD_REG_RLK_ENA__W 1 #define B_EC_VD_REG_RLK_ENA__M 0x1 @@ -12694,7 +11082,6 @@ extern "C" { #define B_EC_VD_REG_RLK_ENA_OFF 0x0 #define B_EC_VD_REG_RLK_ENA_ON 0x1 - #define B_EC_VD_REG_VAL__A 0x2090015 #define B_EC_VD_REG_VAL__W 2 #define B_EC_VD_REG_VAL__M 0x3 @@ -12702,7 +11089,6 @@ extern "C" { #define B_EC_VD_REG_VAL_CODE 0x1 #define B_EC_VD_REG_VAL_CNT 0x2 - #define B_EC_VD_REG_GET_CODERATE__A 0x2090016 #define B_EC_VD_REG_GET_CODERATE__W 3 #define B_EC_VD_REG_GET_CODERATE__M 0x7 @@ -12713,19 +11099,16 @@ extern "C" { #define B_EC_VD_REG_GET_CODERATE_C5_6 0x3 #define B_EC_VD_REG_GET_CODERATE_C7_8 0x4 - #define B_EC_VD_REG_ERR_BIT_CNT__A 0x2090017 #define B_EC_VD_REG_ERR_BIT_CNT__W 16 #define B_EC_VD_REG_ERR_BIT_CNT__M 0xFFFF #define B_EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF - #define B_EC_VD_REG_IN_BIT_CNT__A 0x2090018 #define B_EC_VD_REG_IN_BIT_CNT__W 16 #define B_EC_VD_REG_IN_BIT_CNT__M 0xFFFF #define B_EC_VD_REG_IN_BIT_CNT_INIT 0x0 - #define B_EC_VD_REG_STS__A 0x2090019 #define B_EC_VD_REG_STS__W 1 #define B_EC_VD_REG_STS__M 0x1 @@ -12733,43 +11116,23 @@ extern "C" { #define B_EC_VD_REG_STS_NO_LOCK 0x0 #define B_EC_VD_REG_STS_IN_LOCK 0x1 - #define B_EC_VD_REG_RLK_CNT__A 0x209001A #define B_EC_VD_REG_RLK_CNT__W 16 #define B_EC_VD_REG_RLK_CNT__M 0xFFFF #define B_EC_VD_REG_RLK_CNT_INIT 0x0 - - #define B_EC_VD_TB0_RAM__A 0x20A0000 - - #define B_EC_VD_TB1_RAM__A 0x20B0000 - - #define B_EC_VD_TB2_RAM__A 0x20C0000 - - #define B_EC_VD_TB3_RAM__A 0x20D0000 - - #define B_EC_VD_RE_RAM__A 0x2100000 - - - - #define B_EC_OD_SID 0x18 - - - - - #define B_EC_OD_REG_COMM_EXEC__A 0x2110000 #define B_EC_OD_REG_COMM_EXEC__W 3 #define B_EC_OD_REG_COMM_EXEC__M 0x7 @@ -12788,7 +11151,6 @@ extern "C" { #define B_EC_OD_REG_COMM_STATE_DI_LOCKED__W 1 #define B_EC_OD_REG_COMM_STATE_DI_LOCKED__M 0x1 - #define B_EC_OD_REG_COMM_MB__A 0x2110002 #define B_EC_OD_REG_COMM_MB__W 3 #define B_EC_OD_REG_COMM_MB__M 0x7 @@ -12828,7 +11190,6 @@ extern "C" { #define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 #define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 - #define B_EC_OD_REG_COMM_INT_MSK__A 0x2110008 #define B_EC_OD_REG_COMM_INT_MSK__W 2 #define B_EC_OD_REG_COMM_INT_MSK__M 0x3 @@ -12839,7 +11200,6 @@ extern "C" { #define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 #define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 - #define B_EC_OD_REG_SYNC__A 0x2110664 #define B_EC_OD_REG_SYNC__W 12 #define B_EC_OD_REG_SYNC__M 0xFFF @@ -12853,25 +11213,14 @@ extern "C" { #define B_EC_OD_REG_SYNC_OUT_SYNC__W 3 #define B_EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 - #define B_EC_OD_REG_NOSYNC__A 0x2110004 #define B_EC_OD_REG_NOSYNC__W 8 #define B_EC_OD_REG_NOSYNC__M 0xFF - - #define B_EC_OD_DEINT_RAM__A 0x2120000 - - - - #define B_EC_RS_SID 0x19 - - - - #define B_EC_RS_REG_COMM_EXEC__A 0x2130000 #define B_EC_RS_REG_COMM_EXEC__W 3 #define B_EC_RS_REG_COMM_EXEC__M 0x7 @@ -12919,58 +11268,41 @@ extern "C" { #define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 #define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 - #define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 #define B_EC_RS_REG_REQ_PCK_CNT__W 16 #define B_EC_RS_REG_REQ_PCK_CNT__M 0xFFFF #define B_EC_RS_REG_REQ_PCK_CNT_INIT 0x200 - #define B_EC_RS_REG_VAL__A 0x2130011 #define B_EC_RS_REG_VAL__W 1 #define B_EC_RS_REG_VAL__M 0x1 #define B_EC_RS_REG_VAL_INIT 0x0 #define B_EC_RS_REG_VAL_PCK 0x1 - #define B_EC_RS_REG_ERR_PCK_CNT__A 0x2130012 #define B_EC_RS_REG_ERR_PCK_CNT__W 16 #define B_EC_RS_REG_ERR_PCK_CNT__M 0xFFFF #define B_EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF - #define B_EC_RS_REG_ERR_SMB_CNT__A 0x2130013 #define B_EC_RS_REG_ERR_SMB_CNT__W 16 #define B_EC_RS_REG_ERR_SMB_CNT__M 0xFFFF #define B_EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF - #define B_EC_RS_REG_ERR_BIT_CNT__A 0x2130014 #define B_EC_RS_REG_ERR_BIT_CNT__W 16 #define B_EC_RS_REG_ERR_BIT_CNT__M 0xFFFF #define B_EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF - #define B_EC_RS_REG_IN_PCK_CNT__A 0x2130015 #define B_EC_RS_REG_IN_PCK_CNT__W 16 #define B_EC_RS_REG_IN_PCK_CNT__M 0xFFFF #define B_EC_RS_REG_IN_PCK_CNT_INIT 0x0 - - #define B_EC_RS_EC_RAM__A 0x2140000 - - - - #define B_EC_OC_SID 0x1A - - - - - #define B_EC_OC_REG_COMM_EXEC__A 0x2150000 #define B_EC_OC_REG_COMM_EXEC__W 3 #define B_EC_OC_REG_COMM_EXEC__M 0x7 @@ -13000,7 +11332,6 @@ extern "C" { #define B_EC_OC_REG_COMM_MB_OBS_OFF 0x0 #define B_EC_OC_REG_COMM_MB_OBS_ON 0x2 - #define B_EC_OC_REG_COMM_SERVICE0__A 0x2150003 #define B_EC_OC_REG_COMM_SERVICE0__W 10 #define B_EC_OC_REG_COMM_SERVICE0__M 0x3FF @@ -13031,7 +11362,6 @@ extern "C" { #define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 #define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 - #define B_EC_OC_REG_COMM_INT_MSK__A 0x2150008 #define B_EC_OC_REG_COMM_INT_MSK__W 6 #define B_EC_OC_REG_COMM_INT_MSK__M 0x3F @@ -13054,7 +11384,6 @@ extern "C" { #define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 #define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 - #define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 #define B_EC_OC_REG_OC_MODE_LOP__W 16 #define B_EC_OC_REG_OC_MODE_LOP__M 0xFFFF @@ -13144,7 +11473,6 @@ extern "C" { #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 #define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 - #define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 #define B_EC_OC_REG_OC_MODE_HIP__W 15 #define B_EC_OC_REG_OC_MODE_HIP__M 0x7FFF @@ -13240,7 +11568,6 @@ extern "C" { #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_ZER 0x0 #define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_CLC 0x4000 - #define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 #define B_EC_OC_REG_OC_MPG_SIO__W 12 #define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF @@ -13318,19 +11645,16 @@ extern "C" { #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 #define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 - #define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 #define B_EC_OC_REG_DTO_INC_LOP__W 16 #define B_EC_OC_REG_DTO_INC_LOP__M 0xFFFF #define B_EC_OC_REG_DTO_INC_LOP_INIT 0x0 - #define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 #define B_EC_OC_REG_DTO_INC_HIP__W 8 #define B_EC_OC_REG_DTO_INC_HIP__M 0xFF #define B_EC_OC_REG_DTO_INC_HIP_INIT 0xC0 - #define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 #define B_EC_OC_REG_SNC_ISC_LVL__W 12 #define B_EC_OC_REG_SNC_ISC_LVL__M 0xFFF @@ -13348,13 +11672,11 @@ extern "C" { #define B_EC_OC_REG_SNC_ISC_LVL_NSC__W 4 #define B_EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 - #define B_EC_OC_REG_SNC_NSC_LVL__A 0x2150017 #define B_EC_OC_REG_SNC_NSC_LVL__W 8 #define B_EC_OC_REG_SNC_NSC_LVL__M 0xFF #define B_EC_OC_REG_SNC_NSC_LVL_INIT 0x0 - #define B_EC_OC_REG_SNC_SNC_MODE__A 0x2150019 #define B_EC_OC_REG_SNC_SNC_MODE__W 2 #define B_EC_OC_REG_SNC_SNC_MODE__M 0x3 @@ -13362,7 +11684,6 @@ extern "C" { #define B_EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 #define B_EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 - #define B_EC_OC_REG_SNC_PCK_NMB__A 0x215001A #define B_EC_OC_REG_SNC_PCK_NMB__W 16 #define B_EC_OC_REG_SNC_PCK_NMB__M 0xFFFF @@ -13384,49 +11705,41 @@ extern "C" { #define B_EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 #define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 - #define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E #define B_EC_OC_REG_TMD_TOP_CNT__W 10 #define B_EC_OC_REG_TMD_TOP_CNT__M 0x3FF #define B_EC_OC_REG_TMD_TOP_CNT_INIT 0x1F4 - #define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F #define B_EC_OC_REG_TMD_HIL_MAR__W 10 #define B_EC_OC_REG_TMD_HIL_MAR__M 0x3FF #define B_EC_OC_REG_TMD_HIL_MAR_INIT 0x3C0 - #define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 #define B_EC_OC_REG_TMD_LOL_MAR__W 10 #define B_EC_OC_REG_TMD_LOL_MAR__M 0x3FF #define B_EC_OC_REG_TMD_LOL_MAR_INIT 0x40 - #define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 #define B_EC_OC_REG_TMD_CUR_CNT__W 4 #define B_EC_OC_REG_TMD_CUR_CNT__M 0xF #define B_EC_OC_REG_TMD_CUR_CNT_INIT 0x3 - #define B_EC_OC_REG_TMD_IUR_CNT__A 0x2150022 #define B_EC_OC_REG_TMD_IUR_CNT__W 4 #define B_EC_OC_REG_TMD_IUR_CNT__M 0xF #define B_EC_OC_REG_TMD_IUR_CNT_INIT 0x0 - #define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 #define B_EC_OC_REG_AVR_ASH_CNT__W 4 #define B_EC_OC_REG_AVR_ASH_CNT__M 0xF #define B_EC_OC_REG_AVR_ASH_CNT_INIT 0x6 - #define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 #define B_EC_OC_REG_AVR_BSH_CNT__W 4 #define B_EC_OC_REG_AVR_BSH_CNT__M 0xF #define B_EC_OC_REG_AVR_BSH_CNT_INIT 0x2 - #define B_EC_OC_REG_AVR_AVE_LOP__A 0x2150025 #define B_EC_OC_REG_AVR_AVE_LOP__W 16 #define B_EC_OC_REG_AVR_AVE_LOP__M 0xFFFF @@ -13458,43 +11771,36 @@ extern "C" { #define B_EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 #define B_EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 - #define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 #define B_EC_OC_REG_RCN_CRA_LOP__W 16 #define B_EC_OC_REG_RCN_CRA_LOP__M 0xFFFF #define B_EC_OC_REG_RCN_CRA_LOP_INIT 0x0 - #define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 #define B_EC_OC_REG_RCN_CRA_HIP__W 8 #define B_EC_OC_REG_RCN_CRA_HIP__M 0xFF #define B_EC_OC_REG_RCN_CRA_HIP_INIT 0xC0 - #define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A #define B_EC_OC_REG_RCN_CST_LOP__W 16 #define B_EC_OC_REG_RCN_CST_LOP__M 0xFFFF #define B_EC_OC_REG_RCN_CST_LOP_INIT 0x1000 - #define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B #define B_EC_OC_REG_RCN_CST_HIP__W 8 #define B_EC_OC_REG_RCN_CST_HIP__M 0xFF #define B_EC_OC_REG_RCN_CST_HIP_INIT 0x0 - #define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C #define B_EC_OC_REG_RCN_SET_LVL__W 9 #define B_EC_OC_REG_RCN_SET_LVL__M 0x1FF #define B_EC_OC_REG_RCN_SET_LVL_INIT 0x1FF - #define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D #define B_EC_OC_REG_RCN_GAI_LVL__W 4 #define B_EC_OC_REG_RCN_GAI_LVL__M 0xF #define B_EC_OC_REG_RCN_GAI_LVL_INIT 0xA - #define B_EC_OC_REG_RCN_DRA_LOP__A 0x215002E #define B_EC_OC_REG_RCN_DRA_LOP__W 16 #define B_EC_OC_REG_RCN_DRA_LOP__M 0xFFFF @@ -13516,13 +11822,11 @@ extern "C" { #define B_EC_OC_REG_RCN_CLP_LOP__M 0xFFFF #define B_EC_OC_REG_RCN_CLP_LOP_INIT 0x0 - #define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 #define B_EC_OC_REG_RCN_CLP_HIP__W 8 #define B_EC_OC_REG_RCN_CLP_HIP__M 0xFF #define B_EC_OC_REG_RCN_CLP_HIP_INIT 0xC0 - #define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 #define B_EC_OC_REG_RCN_MAP_LOP__W 16 #define B_EC_OC_REG_RCN_MAP_LOP__M 0xFFFF @@ -13608,7 +11912,6 @@ extern "C" { #define B_EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 #define B_EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 - #define B_EC_OC_REG_OCR_MPG_WRI__A 0x2150037 #define B_EC_OC_REG_OCR_MPG_WRI__W 12 #define B_EC_OC_REG_OCR_MPG_WRI__M 0xFFF @@ -13674,7 +11977,6 @@ extern "C" { #define B_EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 #define B_EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 - #define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 #define B_EC_OC_REG_OCR_MPG_USR_DAT__W 12 #define B_EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF @@ -13684,13 +11986,11 @@ extern "C" { #define B_EC_OC_REG_OCR_MON_CNT__M 0x3FFF #define B_EC_OC_REG_OCR_MON_CNT_INIT 0x0 - #define B_EC_OC_REG_OCR_MON_RDX__A 0x215003D #define B_EC_OC_REG_OCR_MON_RDX__W 1 #define B_EC_OC_REG_OCR_MON_RDX__M 0x1 #define B_EC_OC_REG_OCR_MON_RDX_INIT 0x0 - #define B_EC_OC_REG_OCR_MON_RD0__A 0x215003E #define B_EC_OC_REG_OCR_MON_RD0__W 10 #define B_EC_OC_REG_OCR_MON_RD0__M 0x3FF @@ -13720,19 +12020,16 @@ extern "C" { #define B_EC_OC_REG_OCR_INV_MON__M 0xFFF #define B_EC_OC_REG_OCR_INV_MON_INIT 0x0 - #define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 #define B_EC_OC_REG_IPR_INV_MPG__W 12 #define B_EC_OC_REG_IPR_INV_MPG__M 0xFFF #define B_EC_OC_REG_IPR_INV_MPG_INIT 0x0 - #define B_EC_OC_REG_IPR_MSR_SNC__A 0x2150046 #define B_EC_OC_REG_IPR_MSR_SNC__W 6 #define B_EC_OC_REG_IPR_MSR_SNC__M 0x3F #define B_EC_OC_REG_IPR_MSR_SNC_INIT 0x0 - #define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 #define B_EC_OC_REG_DTO_CLKMODE__W 2 #define B_EC_OC_REG_DTO_CLKMODE__M 0x3 @@ -13750,13 +12047,11 @@ extern "C" { #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_SERIAL_MODE 0x0 #define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_PARALLEL_MODE 0x2 - #define B_EC_OC_REG_DTO_PER__A 0x2150048 #define B_EC_OC_REG_DTO_PER__W 8 #define B_EC_OC_REG_DTO_PER__M 0xFF #define B_EC_OC_REG_DTO_PER_INIT 0x6 - #define B_EC_OC_REG_DTO_BUR__A 0x2150049 #define B_EC_OC_REG_DTO_BUR__W 2 #define B_EC_OC_REG_DTO_BUR__M 0x3 @@ -13766,7 +12061,6 @@ extern "C" { #define B_EC_OC_REG_DTO_BUR_SELECT_204 0x2 #define B_EC_OC_REG_DTO_BUR_SELECT_47 0x3 - #define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A #define B_EC_OC_REG_RCR_CLKMODE__W 3 #define B_EC_OC_REG_RCR_CLKMODE__M 0x7 @@ -13790,20 +12084,10 @@ extern "C" { #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FIFO 0x0 #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FEEDBACKLOOP 0x4 - - #define B_EC_OC_RAM__A 0x2160000 - - - - #define B_CC_SID 0x1B - - - - #define B_CC_COMM_EXEC__A 0x2400000 #define B_CC_COMM_EXEC__W 3 #define B_CC_COMM_EXEC__M 0x7 @@ -13836,12 +12120,6 @@ extern "C" { #define B_CC_COMM_INT_MSK__W 16 #define B_CC_COMM_INT_MSK__M 0xFFFF - - - - - - #define B_CC_REG_COMM_EXEC__A 0x2410000 #define B_CC_REG_COMM_EXEC__W 3 #define B_CC_REG_COMM_EXEC__M 0x7 @@ -13881,7 +12159,6 @@ extern "C" { #define B_CC_REG_OSC_MODE_M20 0x1 #define B_CC_REG_OSC_MODE_M48 0x2 - #define B_CC_REG_PLL_MODE__A 0x2410011 #define B_CC_REG_PLL_MODE__W 6 #define B_CC_REG_PLL_MODE__M 0x3F @@ -13907,7 +12184,6 @@ extern "C" { #define B_CC_REG_PLL_MODE_OUT_EN_OFF 0x0 #define B_CC_REG_PLL_MODE_OUT_EN_ON 0x20 - #define B_CC_REG_REF_DIVIDE__A 0x2410012 #define B_CC_REG_REF_DIVIDE__W 4 #define B_CC_REG_REF_DIVIDE__M 0xF @@ -13924,7 +12200,6 @@ extern "C" { #define B_CC_REG_REF_DIVIDE_D09 0x9 #define B_CC_REG_REF_DIVIDE_D10 0xA - #define B_CC_REG_REF_DELAY__A 0x2410013 #define B_CC_REG_REF_DELAY__W 3 #define B_CC_REG_REF_DELAY__M 0x7 @@ -13941,7 +12216,6 @@ extern "C" { #define B_CC_REG_REF_DELAY_DELAY_DEL_6 0x4 #define B_CC_REG_REF_DELAY_DELAY_DEL_9 0x6 - #define B_CC_REG_CLK_DELAY__A 0x2410014 #define B_CC_REG_CLK_DELAY__W 5 #define B_CC_REG_CLK_DELAY__M 0x1F @@ -13970,7 +12244,6 @@ extern "C" { #define B_CC_REG_CLK_DELAY_EDGE_POS 0x0 #define B_CC_REG_CLK_DELAY_EDGE_NEG 0x10 - #define B_CC_REG_PWD_MODE__A 0x2410015 #define B_CC_REG_PWD_MODE__W 2 #define B_CC_REG_PWD_MODE__M 0x3 @@ -13979,7 +12252,6 @@ extern "C" { #define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 #define B_CC_REG_PWD_MODE_DOWN_OSC 0x3 - #define B_CC_REG_SOFT_RST__A 0x2410016 #define B_CC_REG_SOFT_RST__W 2 #define B_CC_REG_SOFT_RST__M 0x3 @@ -13990,76 +12262,58 @@ extern "C" { #define B_CC_REG_SOFT_RST_OSC__W 1 #define B_CC_REG_SOFT_RST_OSC__M 0x2 - #define B_CC_REG_UPDATE__A 0x2410017 #define B_CC_REG_UPDATE__W 16 #define B_CC_REG_UPDATE__M 0xFFFF #define B_CC_REG_UPDATE_KEY 0x3973 - #define B_CC_REG_PLL_LOCK__A 0x2410018 #define B_CC_REG_PLL_LOCK__W 1 #define B_CC_REG_PLL_LOCK__M 0x1 #define B_CC_REG_PLL_LOCK_LOCK 0x1 - #define B_CC_REG_JTAGID_L__A 0x2410019 #define B_CC_REG_JTAGID_L__W 16 #define B_CC_REG_JTAGID_L__M 0xFFFF #define B_CC_REG_JTAGID_L_INIT 0x0 - #define B_CC_REG_JTAGID_H__A 0x241001A #define B_CC_REG_JTAGID_H__W 16 #define B_CC_REG_JTAGID_H__M 0xFFFF #define B_CC_REG_JTAGID_H_INIT 0x0 - #define B_CC_REG_DIVERSITY__A 0x241001B #define B_CC_REG_DIVERSITY__W 1 #define B_CC_REG_DIVERSITY__M 0x1 #define B_CC_REG_DIVERSITY_INIT 0x0 - #define B_CC_REG_BACKUP3V__A 0x241001C #define B_CC_REG_BACKUP3V__W 1 #define B_CC_REG_BACKUP3V__M 0x1 #define B_CC_REG_BACKUP3V_INIT 0x0 - #define B_CC_REG_DRV_IO__A 0x241001D #define B_CC_REG_DRV_IO__W 3 #define B_CC_REG_DRV_IO__M 0x7 #define B_CC_REG_DRV_IO_INIT 0x2 - #define B_CC_REG_DRV_MPG__A 0x241001E #define B_CC_REG_DRV_MPG__W 3 #define B_CC_REG_DRV_MPG__M 0x7 #define B_CC_REG_DRV_MPG_INIT 0x2 - #define B_CC_REG_DRV_I2C1__A 0x241001F #define B_CC_REG_DRV_I2C1__W 3 #define B_CC_REG_DRV_I2C1__M 0x7 #define B_CC_REG_DRV_I2C1_INIT 0x2 - #define B_CC_REG_DRV_I2C2__A 0x2410020 #define B_CC_REG_DRV_I2C2__W 1 #define B_CC_REG_DRV_I2C2__M 0x1 #define B_CC_REG_DRV_I2C2_INIT 0x0 - - - - #define B_LC_SID 0x1C - - - - #define B_LC_COMM_EXEC__A 0x2800000 #define B_LC_COMM_EXEC__W 3 #define B_LC_COMM_EXEC__M 0x7 @@ -14092,11 +12346,6 @@ extern "C" { #define B_LC_COMM_INT_MSK__W 16 #define B_LC_COMM_INT_MSK__M 0xFFFF - - - - - #define B_LC_CT_REG_COMM_EXEC__A 0x2810000 #define B_LC_CT_REG_COMM_EXEC__W 3 #define B_LC_CT_REG_COMM_EXEC__M 0x7 @@ -14108,7 +12357,6 @@ extern "C" { #define B_LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 #define B_LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - #define B_LC_CT_REG_COMM_STATE__A 0x2810001 #define B_LC_CT_REG_COMM_STATE__W 10 #define B_LC_CT_REG_COMM_STATE__M 0x3FF @@ -14122,7 +12370,6 @@ extern "C" { #define B_LC_CT_REG_COMM_SERVICE1_LC__W 1 #define B_LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 - #define B_LC_CT_REG_COMM_INT_STA__A 0x2810007 #define B_LC_CT_REG_COMM_INT_STA__W 1 #define B_LC_CT_REG_COMM_INT_STA__M 0x1 @@ -14130,7 +12377,6 @@ extern "C" { #define B_LC_CT_REG_COMM_INT_STA_REQUEST__W 1 #define B_LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - #define B_LC_CT_REG_COMM_INT_MSK__A 0x2810008 #define B_LC_CT_REG_COMM_INT_MSK__W 1 #define B_LC_CT_REG_COMM_INT_MSK__M 0x1 @@ -14138,9 +12384,6 @@ extern "C" { #define B_LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 #define B_LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - - - #define B_LC_CT_REG_CTL_STK__AX 0x2810010 #define B_LC_CT_REG_CTL_STK__XSZ 4 #define B_LC_CT_REG_CTL_STK__W 10 @@ -14154,10 +12397,6 @@ extern "C" { #define B_LC_CT_REG_CTL_BPT__W 10 #define B_LC_CT_REG_CTL_BPT__M 0x3FF - - - - #define B_LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 #define B_LC_RA_RAM_PROC_DELAY_IF__W 16 #define B_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF @@ -14296,10 +12535,6 @@ extern "C" { #define B_LC_RA_RAM_ADJUST_DELAY__W 16 #define B_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF - - - - #define B_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 #define B_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 #define B_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF @@ -14319,8 +12554,6 @@ extern "C" { #define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 #define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF - - #define B_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 #define B_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 #define B_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF @@ -14340,8 +12573,6 @@ extern "C" { #define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 #define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF - - #define B_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 #define B_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 #define B_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF @@ -14361,10 +12592,6 @@ extern "C" { #define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 #define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF - - - - #define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 #define B_LC_RA_RAM_FILTER_CRMM_A__W 16 #define B_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF @@ -14386,8 +12613,6 @@ extern "C" { #define B_LC_RA_RAM_FILTER_CRMM_TMP__W 16 #define B_LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF - - #define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 #define B_LC_RA_RAM_FILTER_SRMM_A__W 16 #define B_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF @@ -14409,8 +12634,6 @@ extern "C" { #define B_LC_RA_RAM_FILTER_SRMM_TMP__W 16 #define B_LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF - - #define B_LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 #define B_LC_RA_RAM_FILTER_PHASE_A__W 16 #define B_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF @@ -14432,8 +12655,6 @@ extern "C" { #define B_LC_RA_RAM_FILTER_PHASE_TMP__W 16 #define B_LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF - - #define B_LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 #define B_LC_RA_RAM_FILTER_DELAY_A__W 16 #define B_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF @@ -14455,11 +12676,6 @@ extern "C" { #define B_LC_RA_RAM_FILTER_DELAY_TMP__W 16 #define B_LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF - - - - - #define B_LC_IF_RAM_TRP_BPT0__AX 0x2830000 #define B_LC_IF_RAM_TRP_BPT0__XSZ 2 #define B_LC_IF_RAM_TRP_BPT0__W 12 @@ -14475,10 +12691,4 @@ extern "C" { #define B_LC_IF_RAM_TRP_WARM__W 12 #define B_LC_IF_RAM_TRP_WARM__M 0xFFF -#ifdef __cplusplus -} #endif - -#endif - - -- cgit v1.2.3 From be9297d130835082587ef95cc83825871146e840 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab <mchehab@redhat.com> Date: Fri, 25 Mar 2011 09:42:26 -0300 Subject: [media] drxd_map_firm.h: make checkpatch.pl happier s/(define\s+[^\s]+)\s........../\1/ Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd_map_firm.h | 25322 +++++++++++++------------- 1 file changed, 12661 insertions(+), 12661 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd_map_firm.h b/drivers/media/dvb/frontends/drxd_map_firm.h index c9fbb459b20f..160323a4f932 100644 --- a/drivers/media/dvb/frontends/drxd_map_firm.h +++ b/drivers/media/dvb/frontends/drxd_map_firm.h @@ -24,12671 +24,12671 @@ #ifndef __DRX3973D_MAP__H__ #define __DRX3973D_MAP__H__ -#define HI_SID 0x10 - -#define HI_COMM_EXEC__A 0x400000 -#define HI_COMM_EXEC__W 3 -#define HI_COMM_EXEC__M 0x7 -#define HI_COMM_EXEC_CTL__B 0 -#define HI_COMM_EXEC_CTL__W 3 -#define HI_COMM_EXEC_CTL__M 0x7 -#define HI_COMM_EXEC_CTL_STOP 0x0 -#define HI_COMM_EXEC_CTL_ACTIVE 0x1 -#define HI_COMM_EXEC_CTL_HOLD 0x2 -#define HI_COMM_EXEC_CTL_STEP 0x3 -#define HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define HI_COMM_STATE__A 0x400001 -#define HI_COMM_STATE__W 16 -#define HI_COMM_STATE__M 0xFFFF -#define HI_COMM_MB__A 0x400002 -#define HI_COMM_MB__W 16 -#define HI_COMM_MB__M 0xFFFF -#define HI_COMM_SERVICE0__A 0x400003 -#define HI_COMM_SERVICE0__W 16 -#define HI_COMM_SERVICE0__M 0xFFFF -#define HI_COMM_SERVICE1__A 0x400004 -#define HI_COMM_SERVICE1__W 16 -#define HI_COMM_SERVICE1__M 0xFFFF -#define HI_COMM_INT_STA__A 0x400007 -#define HI_COMM_INT_STA__W 16 -#define HI_COMM_INT_STA__M 0xFFFF -#define HI_COMM_INT_MSK__A 0x400008 -#define HI_COMM_INT_MSK__W 16 -#define HI_COMM_INT_MSK__M 0xFFFF - -#define HI_CT_REG_COMM_EXEC__A 0x410000 -#define HI_CT_REG_COMM_EXEC__W 3 -#define HI_CT_REG_COMM_EXEC__M 0x7 -#define HI_CT_REG_COMM_EXEC_CTL__B 0 -#define HI_CT_REG_COMM_EXEC_CTL__W 3 -#define HI_CT_REG_COMM_EXEC_CTL__M 0x7 -#define HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define HI_CT_REG_COMM_STATE__A 0x410001 -#define HI_CT_REG_COMM_STATE__W 10 -#define HI_CT_REG_COMM_STATE__M 0x3FF -#define HI_CT_REG_COMM_SERVICE0__A 0x410003 -#define HI_CT_REG_COMM_SERVICE0__W 16 -#define HI_CT_REG_COMM_SERVICE0__M 0xFFFF -#define HI_CT_REG_COMM_SERVICE1__A 0x410004 -#define HI_CT_REG_COMM_SERVICE1__W 16 -#define HI_CT_REG_COMM_SERVICE1__M 0xFFFF -#define HI_CT_REG_COMM_SERVICE1_HI__B 0 -#define HI_CT_REG_COMM_SERVICE1_HI__W 1 -#define HI_CT_REG_COMM_SERVICE1_HI__M 0x1 - -#define HI_CT_REG_COMM_INT_STA__A 0x410007 -#define HI_CT_REG_COMM_INT_STA__W 1 -#define HI_CT_REG_COMM_INT_STA__M 0x1 -#define HI_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define HI_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define HI_CT_REG_COMM_INT_MSK__A 0x410008 -#define HI_CT_REG_COMM_INT_MSK__W 1 -#define HI_CT_REG_COMM_INT_MSK__M 0x1 -#define HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define HI_CT_REG_CTL_STK__AX 0x410010 -#define HI_CT_REG_CTL_STK__XSZ 4 -#define HI_CT_REG_CTL_STK__W 10 -#define HI_CT_REG_CTL_STK__M 0x3FF - -#define HI_CT_REG_CTL_BPT_IDX__A 0x41001F -#define HI_CT_REG_CTL_BPT_IDX__W 1 -#define HI_CT_REG_CTL_BPT_IDX__M 0x1 - -#define HI_CT_REG_CTL_BPT__A 0x410020 -#define HI_CT_REG_CTL_BPT__W 10 -#define HI_CT_REG_CTL_BPT__M 0x3FF - -#define HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 -#define HI_RA_RAM_SLV0_FLG_SMM__W 1 -#define HI_RA_RAM_SLV0_FLG_SMM__M 0x1 -#define HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 -#define HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 - -#define HI_RA_RAM_SLV0_DEV_ID__A 0x420011 -#define HI_RA_RAM_SLV0_DEV_ID__W 7 -#define HI_RA_RAM_SLV0_DEV_ID__M 0x7F - -#define HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 -#define HI_RA_RAM_SLV0_FLG_CRC__W 1 -#define HI_RA_RAM_SLV0_FLG_CRC__M 0x1 -#define HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 -#define HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 - -#define HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 -#define HI_RA_RAM_SLV0_FLG_ACC__W 3 -#define HI_RA_RAM_SLV0_FLG_ACC__M 0x7 -#define HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 -#define HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 -#define HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 -#define HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 -#define HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 -#define HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 -#define HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 -#define HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 -#define HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 -#define HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 - -#define HI_RA_RAM_SLV0_STATE__A 0x420014 -#define HI_RA_RAM_SLV0_STATE__W 1 -#define HI_RA_RAM_SLV0_STATE__M 0x1 -#define HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 -#define HI_RA_RAM_SLV0_STATE_DATA 0x1 - -#define HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 -#define HI_RA_RAM_SLV0_BLK_BNK__W 12 -#define HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF -#define HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 -#define HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 -#define HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F -#define HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 -#define HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 -#define HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 - -#define HI_RA_RAM_SLV0_ADDR__A 0x420016 -#define HI_RA_RAM_SLV0_ADDR__W 16 -#define HI_RA_RAM_SLV0_ADDR__M 0xFFFF - -#define HI_RA_RAM_SLV0_CRC__A 0x420017 -#define HI_RA_RAM_SLV0_CRC__W 16 -#define HI_RA_RAM_SLV0_CRC__M 0xFFFF - -#define HI_RA_RAM_SLV0_READBACK__A 0x420018 -#define HI_RA_RAM_SLV0_READBACK__W 16 -#define HI_RA_RAM_SLV0_READBACK__M 0xFFFF - -#define HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 -#define HI_RA_RAM_SLV1_FLG_SMM__W 1 -#define HI_RA_RAM_SLV1_FLG_SMM__M 0x1 -#define HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 -#define HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 - -#define HI_RA_RAM_SLV1_DEV_ID__A 0x420021 -#define HI_RA_RAM_SLV1_DEV_ID__W 7 -#define HI_RA_RAM_SLV1_DEV_ID__M 0x7F - -#define HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 -#define HI_RA_RAM_SLV1_FLG_CRC__W 1 -#define HI_RA_RAM_SLV1_FLG_CRC__M 0x1 -#define HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 -#define HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 - -#define HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 -#define HI_RA_RAM_SLV1_FLG_ACC__W 3 -#define HI_RA_RAM_SLV1_FLG_ACC__M 0x7 -#define HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 -#define HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 -#define HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 -#define HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 -#define HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 -#define HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 -#define HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 -#define HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 -#define HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 -#define HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 - -#define HI_RA_RAM_SLV1_STATE__A 0x420024 -#define HI_RA_RAM_SLV1_STATE__W 1 -#define HI_RA_RAM_SLV1_STATE__M 0x1 -#define HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 -#define HI_RA_RAM_SLV1_STATE_DATA 0x1 - -#define HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 -#define HI_RA_RAM_SLV1_BLK_BNK__W 12 -#define HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF -#define HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 -#define HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 -#define HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F -#define HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 -#define HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 -#define HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 - -#define HI_RA_RAM_SLV1_ADDR__A 0x420026 -#define HI_RA_RAM_SLV1_ADDR__W 16 -#define HI_RA_RAM_SLV1_ADDR__M 0xFFFF - -#define HI_RA_RAM_SLV1_CRC__A 0x420027 -#define HI_RA_RAM_SLV1_CRC__W 16 -#define HI_RA_RAM_SLV1_CRC__M 0xFFFF - -#define HI_RA_RAM_SLV1_READBACK__A 0x420028 -#define HI_RA_RAM_SLV1_READBACK__W 16 -#define HI_RA_RAM_SLV1_READBACK__M 0xFFFF - -#define HI_RA_RAM_SRV_SEM__A 0x420030 -#define HI_RA_RAM_SRV_SEM__W 1 -#define HI_RA_RAM_SRV_SEM__M 0x1 -#define HI_RA_RAM_SRV_SEM_FREE 0x0 -#define HI_RA_RAM_SRV_SEM_CLAIMED 0x1 - -#define HI_RA_RAM_SRV_RES__A 0x420031 -#define HI_RA_RAM_SRV_RES__W 3 -#define HI_RA_RAM_SRV_RES__M 0x7 -#define HI_RA_RAM_SRV_RES_OK 0x0 -#define HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 -#define HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 -#define HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 -#define HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 - -#define HI_RA_RAM_SRV_CMD__A 0x420032 -#define HI_RA_RAM_SRV_CMD__W 3 -#define HI_RA_RAM_SRV_CMD__M 0x7 -#define HI_RA_RAM_SRV_CMD_NULL 0x0 -#define HI_RA_RAM_SRV_CMD_UIO 0x1 -#define HI_RA_RAM_SRV_CMD_RESET 0x2 -#define HI_RA_RAM_SRV_CMD_CONFIG 0x3 -#define HI_RA_RAM_SRV_CMD_COPY 0x4 -#define HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 -#define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 - -#define HI_RA_RAM_SRV_PAR__AX 0x420033 -#define HI_RA_RAM_SRV_PAR__XSZ 5 -#define HI_RA_RAM_SRV_PAR__W 16 -#define HI_RA_RAM_SRV_PAR__M 0xFFFF - -#define HI_RA_RAM_SRV_NOP_RES__A 0x420031 -#define HI_RA_RAM_SRV_NOP_RES__W 3 -#define HI_RA_RAM_SRV_NOP_RES__M 0x7 -#define HI_RA_RAM_SRV_NOP_RES_OK 0x0 -#define HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 - -#define HI_RA_RAM_SRV_UIO_RES__A 0x420031 -#define HI_RA_RAM_SRV_UIO_RES__W 3 -#define HI_RA_RAM_SRV_UIO_RES__M 0x7 -#define HI_RA_RAM_SRV_UIO_RES_LO 0x0 -#define HI_RA_RAM_SRV_UIO_RES_HI 0x1 - -#define HI_RA_RAM_SRV_UIO_KEY__A 0x420033 -#define HI_RA_RAM_SRV_UIO_KEY__W 16 -#define HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF -#define HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 - -#define HI_RA_RAM_SRV_UIO_SEL__A 0x420034 -#define HI_RA_RAM_SRV_UIO_SEL__W 2 -#define HI_RA_RAM_SRV_UIO_SEL__M 0x3 -#define HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 -#define HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 - -#define HI_RA_RAM_SRV_UIO_SET__A 0x420035 -#define HI_RA_RAM_SRV_UIO_SET__W 2 -#define HI_RA_RAM_SRV_UIO_SET__M 0x3 -#define HI_RA_RAM_SRV_UIO_SET_OUT__B 0 -#define HI_RA_RAM_SRV_UIO_SET_OUT__W 1 -#define HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 -#define HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 -#define HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 -#define HI_RA_RAM_SRV_UIO_SET_DIR__B 1 -#define HI_RA_RAM_SRV_UIO_SET_DIR__W 1 -#define HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 -#define HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 -#define HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 - -#define HI_RA_RAM_SRV_RST_RES__A 0x420031 -#define HI_RA_RAM_SRV_RST_RES__W 1 -#define HI_RA_RAM_SRV_RST_RES__M 0x1 -#define HI_RA_RAM_SRV_RST_RES_OK 0x0 -#define HI_RA_RAM_SRV_RST_RES_ERROR 0x1 - -#define HI_RA_RAM_SRV_RST_KEY__A 0x420033 -#define HI_RA_RAM_SRV_RST_KEY__W 16 -#define HI_RA_RAM_SRV_RST_KEY__M 0xFFFF -#define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 - -#define HI_RA_RAM_SRV_CFG_RES__A 0x420031 -#define HI_RA_RAM_SRV_CFG_RES__W 1 -#define HI_RA_RAM_SRV_CFG_RES__M 0x1 -#define HI_RA_RAM_SRV_CFG_RES_OK 0x0 -#define HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 - -#define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 -#define HI_RA_RAM_SRV_CFG_KEY__W 16 -#define HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF -#define HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 - -#define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 -#define HI_RA_RAM_SRV_CFG_DIV__W 5 -#define HI_RA_RAM_SRV_CFG_DIV__M 0x1F - -#define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 -#define HI_RA_RAM_SRV_CFG_BDL__W 6 -#define HI_RA_RAM_SRV_CFG_BDL__M 0x3F - -#define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 -#define HI_RA_RAM_SRV_CFG_WUP__W 8 -#define HI_RA_RAM_SRV_CFG_WUP__M 0xFF - -#define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 -#define HI_RA_RAM_SRV_CFG_ACT__W 4 -#define HI_RA_RAM_SRV_CFG_ACT__M 0xF -#define HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 -#define HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 -#define HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 -#define HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 -#define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 -#define HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 -#define HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 -#define HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 -#define HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 -#define HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 -#define HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 -#define HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 -#define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 -#define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 -#define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 -#define HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 -#define HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 -#define HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 -#define HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 -#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 - -#define HI_RA_RAM_SRV_CPY_RES__A 0x420031 -#define HI_RA_RAM_SRV_CPY_RES__W 1 -#define HI_RA_RAM_SRV_CPY_RES__M 0x1 -#define HI_RA_RAM_SRV_CPY_RES_OK 0x0 -#define HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 - -#define HI_RA_RAM_SRV_CPY_SBB__A 0x420033 -#define HI_RA_RAM_SRV_CPY_SBB__W 12 -#define HI_RA_RAM_SRV_CPY_SBB__M 0xFFF -#define HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 -#define HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 -#define HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F -#define HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 -#define HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 -#define HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 - -#define HI_RA_RAM_SRV_CPY_SAD__A 0x420034 -#define HI_RA_RAM_SRV_CPY_SAD__W 16 -#define HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF - -#define HI_RA_RAM_SRV_CPY_LEN__A 0x420035 -#define HI_RA_RAM_SRV_CPY_LEN__W 16 -#define HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF - -#define HI_RA_RAM_SRV_CPY_DBB__A 0x420033 -#define HI_RA_RAM_SRV_CPY_DBB__W 12 -#define HI_RA_RAM_SRV_CPY_DBB__M 0xFFF -#define HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 -#define HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 -#define HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F -#define HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 -#define HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 -#define HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 - -#define HI_RA_RAM_SRV_CPY_DAD__A 0x420034 -#define HI_RA_RAM_SRV_CPY_DAD__W 16 -#define HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF - -#define HI_RA_RAM_SRV_TRM_RES__A 0x420031 -#define HI_RA_RAM_SRV_TRM_RES__W 2 -#define HI_RA_RAM_SRV_TRM_RES__M 0x3 -#define HI_RA_RAM_SRV_TRM_RES_OK 0x0 -#define HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 -#define HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 - -#define HI_RA_RAM_SRV_TRM_MST__A 0x420033 -#define HI_RA_RAM_SRV_TRM_MST__W 12 -#define HI_RA_RAM_SRV_TRM_MST__M 0xFFF - -#define HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 -#define HI_RA_RAM_SRV_TRM_SEQ__W 7 -#define HI_RA_RAM_SRV_TRM_SEQ__M 0x7F - -#define HI_RA_RAM_SRV_TRM_TRM__A 0x420035 -#define HI_RA_RAM_SRV_TRM_TRM__W 15 -#define HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF -#define HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 -#define HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 -#define HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF - -#define HI_RA_RAM_SRV_TRM_DBB__A 0x420033 -#define HI_RA_RAM_SRV_TRM_DBB__W 12 -#define HI_RA_RAM_SRV_TRM_DBB__M 0xFFF -#define HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 -#define HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 -#define HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F -#define HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 -#define HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 -#define HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 - -#define HI_RA_RAM_SRV_TRM_DAD__A 0x420034 -#define HI_RA_RAM_SRV_TRM_DAD__W 16 -#define HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF - -#define HI_RA_RAM_USR_BEGIN__A 0x420040 -#define HI_RA_RAM_USR_BEGIN__W 16 -#define HI_RA_RAM_USR_BEGIN__M 0xFFFF - -#define HI_RA_RAM_USR_END__A 0x42007F -#define HI_RA_RAM_USR_END__W 16 -#define HI_RA_RAM_USR_END__M 0xFFFF - -#define HI_IF_RAM_TRP_BPT0__AX 0x430000 -#define HI_IF_RAM_TRP_BPT0__XSZ 2 -#define HI_IF_RAM_TRP_BPT0__W 12 -#define HI_IF_RAM_TRP_BPT0__M 0xFFF - -#define HI_IF_RAM_TRP_STKU__AX 0x430002 -#define HI_IF_RAM_TRP_STKU__XSZ 2 -#define HI_IF_RAM_TRP_STKU__W 12 -#define HI_IF_RAM_TRP_STKU__M 0xFFF - -#define HI_IF_RAM_USR_BEGIN__A 0x430200 -#define HI_IF_RAM_USR_BEGIN__W 12 -#define HI_IF_RAM_USR_BEGIN__M 0xFFF - -#define HI_IF_RAM_USR_END__A 0x4303FF -#define HI_IF_RAM_USR_END__W 12 -#define HI_IF_RAM_USR_END__M 0xFFF - -#define SC_SID 0x11 - -#define SC_COMM_EXEC__A 0x800000 -#define SC_COMM_EXEC__W 3 -#define SC_COMM_EXEC__M 0x7 -#define SC_COMM_EXEC_CTL__B 0 -#define SC_COMM_EXEC_CTL__W 3 -#define SC_COMM_EXEC_CTL__M 0x7 -#define SC_COMM_EXEC_CTL_STOP 0x0 -#define SC_COMM_EXEC_CTL_ACTIVE 0x1 -#define SC_COMM_EXEC_CTL_HOLD 0x2 -#define SC_COMM_EXEC_CTL_STEP 0x3 -#define SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define SC_COMM_STATE__A 0x800001 -#define SC_COMM_STATE__W 16 -#define SC_COMM_STATE__M 0xFFFF -#define SC_COMM_MB__A 0x800002 -#define SC_COMM_MB__W 16 -#define SC_COMM_MB__M 0xFFFF -#define SC_COMM_SERVICE0__A 0x800003 -#define SC_COMM_SERVICE0__W 16 -#define SC_COMM_SERVICE0__M 0xFFFF -#define SC_COMM_SERVICE1__A 0x800004 -#define SC_COMM_SERVICE1__W 16 -#define SC_COMM_SERVICE1__M 0xFFFF -#define SC_COMM_INT_STA__A 0x800007 -#define SC_COMM_INT_STA__W 16 -#define SC_COMM_INT_STA__M 0xFFFF -#define SC_COMM_INT_MSK__A 0x800008 -#define SC_COMM_INT_MSK__W 16 -#define SC_COMM_INT_MSK__M 0xFFFF - -#define SC_CT_REG_COMM_EXEC__A 0x810000 -#define SC_CT_REG_COMM_EXEC__W 3 -#define SC_CT_REG_COMM_EXEC__M 0x7 -#define SC_CT_REG_COMM_EXEC_CTL__B 0 -#define SC_CT_REG_COMM_EXEC_CTL__W 3 -#define SC_CT_REG_COMM_EXEC_CTL__M 0x7 -#define SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define SC_CT_REG_COMM_STATE__A 0x810001 -#define SC_CT_REG_COMM_STATE__W 10 -#define SC_CT_REG_COMM_STATE__M 0x3FF -#define SC_CT_REG_COMM_SERVICE0__A 0x810003 -#define SC_CT_REG_COMM_SERVICE0__W 16 -#define SC_CT_REG_COMM_SERVICE0__M 0xFFFF -#define SC_CT_REG_COMM_SERVICE1__A 0x810004 -#define SC_CT_REG_COMM_SERVICE1__W 16 -#define SC_CT_REG_COMM_SERVICE1__M 0xFFFF -#define SC_CT_REG_COMM_SERVICE1_SC__B 1 -#define SC_CT_REG_COMM_SERVICE1_SC__W 1 -#define SC_CT_REG_COMM_SERVICE1_SC__M 0x2 - -#define SC_CT_REG_COMM_INT_STA__A 0x810007 -#define SC_CT_REG_COMM_INT_STA__W 1 -#define SC_CT_REG_COMM_INT_STA__M 0x1 -#define SC_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define SC_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define SC_CT_REG_COMM_INT_MSK__A 0x810008 -#define SC_CT_REG_COMM_INT_MSK__W 1 -#define SC_CT_REG_COMM_INT_MSK__M 0x1 -#define SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define SC_CT_REG_CTL_STK__AX 0x810010 -#define SC_CT_REG_CTL_STK__XSZ 4 -#define SC_CT_REG_CTL_STK__W 10 -#define SC_CT_REG_CTL_STK__M 0x3FF - -#define SC_CT_REG_CTL_BPT_IDX__A 0x81001F -#define SC_CT_REG_CTL_BPT_IDX__W 1 -#define SC_CT_REG_CTL_BPT_IDX__M 0x1 - -#define SC_CT_REG_CTL_BPT__A 0x810020 -#define SC_CT_REG_CTL_BPT__W 10 -#define SC_CT_REG_CTL_BPT__M 0x3FF - -#define SC_RA_RAM_PARAM0__A 0x820040 -#define SC_RA_RAM_PARAM0__W 16 -#define SC_RA_RAM_PARAM0__M 0xFFFF -#define SC_RA_RAM_PARAM1__A 0x820041 -#define SC_RA_RAM_PARAM1__W 16 -#define SC_RA_RAM_PARAM1__M 0xFFFF -#define SC_RA_RAM_CMD_ADDR__A 0x820042 -#define SC_RA_RAM_CMD_ADDR__W 16 -#define SC_RA_RAM_CMD_ADDR__M 0xFFFF -#define SC_RA_RAM_CMD__A 0x820043 -#define SC_RA_RAM_CMD__W 16 -#define SC_RA_RAM_CMD__M 0xFFFF -#define SC_RA_RAM_CMD_NULL 0x0 -#define SC_RA_RAM_CMD_PROC_START 0x1 -#define SC_RA_RAM_CMD_PROC_TRIGGER 0x2 -#define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 -#define SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 -#define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 -#define SC_RA_RAM_CMD_USER_IO 0x6 -#define SC_RA_RAM_CMD_SET_TIMER 0x7 -#define SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 -#define SC_RA_RAM_CMD_MAX 0x8 -#define SC_RA_RAM_CMDBLOCK__C 0x4 - -#define SC_RA_RAM_PROC_ACTIVATE__A 0x820044 -#define SC_RA_RAM_PROC_ACTIVATE__W 16 -#define SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF -#define SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF -#define SC_RA_RAM_PROC_TERMINATED__A 0x820045 -#define SC_RA_RAM_PROC_TERMINATED__W 16 -#define SC_RA_RAM_PROC_TERMINATED__M 0xFFFF -#define SC_RA_RAM_SW_EVENT__A 0x820046 -#define SC_RA_RAM_SW_EVENT__W 14 -#define SC_RA_RAM_SW_EVENT__M 0x3FFF -#define SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 -#define SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 -#define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 -#define SC_RA_RAM_SW_EVENT_RUN__B 1 -#define SC_RA_RAM_SW_EVENT_RUN__W 1 -#define SC_RA_RAM_SW_EVENT_RUN__M 0x2 -#define SC_RA_RAM_SW_EVENT_TERMINATE__B 2 -#define SC_RA_RAM_SW_EVENT_TERMINATE__W 1 -#define SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 -#define SC_RA_RAM_SW_EVENT_FT_START__B 3 -#define SC_RA_RAM_SW_EVENT_FT_START__W 1 -#define SC_RA_RAM_SW_EVENT_FT_START__M 0x8 -#define SC_RA_RAM_SW_EVENT_FI_START__B 4 -#define SC_RA_RAM_SW_EVENT_FI_START__W 1 -#define SC_RA_RAM_SW_EVENT_FI_START__M 0x10 -#define SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 -#define SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 -#define SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 -#define SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 -#define SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 -#define SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 -#define SC_RA_RAM_SW_EVENT_CE_IR__B 7 -#define SC_RA_RAM_SW_EVENT_CE_IR__W 1 -#define SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 -#define SC_RA_RAM_SW_EVENT_FE_FD__B 8 -#define SC_RA_RAM_SW_EVENT_FE_FD__W 1 -#define SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 -#define SC_RA_RAM_SW_EVENT_FE_CF__B 9 -#define SC_RA_RAM_SW_EVENT_FE_CF__W 1 -#define SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__B 10 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__W 1 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__M 0x400 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__B 11 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__W 1 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__M 0x800 - -#define SC_RA_RAM_LOCKTRACK__A 0x820047 -#define SC_RA_RAM_LOCKTRACK__W 16 -#define SC_RA_RAM_LOCKTRACK__M 0xFFFF -#define SC_RA_RAM_LOCKTRACK_NULL 0x0 -#define SC_RA_RAM_LOCKTRACK_MIN 0x1 -#define SC_RA_RAM_LOCKTRACK_RESET 0x1 -#define SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 -#define SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 -#define SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 -#define SC_RA_RAM_LOCKTRACK_P_DETECT_MIRROR 0x5 -#define SC_RA_RAM_LOCKTRACK_LC 0x6 -#define SC_RA_RAM_LOCKTRACK_P_ECHO 0x7 -#define SC_RA_RAM_LOCKTRACK_NE_INIT 0x8 -#define SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x9 -#define SC_RA_RAM_LOCKTRACK_TRACK 0xA -#define SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xB -#define SC_RA_RAM_LOCKTRACK_SR_SCANNING 0xC -#define SC_RA_RAM_LOCKTRACK_MAX 0xD - -#define SC_RA_RAM_OP_PARAM__A 0x820048 -#define SC_RA_RAM_OP_PARAM__W 13 -#define SC_RA_RAM_OP_PARAM__M 0x1FFF -#define SC_RA_RAM_OP_PARAM_MODE__B 0 -#define SC_RA_RAM_OP_PARAM_MODE__W 2 -#define SC_RA_RAM_OP_PARAM_MODE__M 0x3 -#define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 -#define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 -#define SC_RA_RAM_OP_PARAM_GUARD__B 2 -#define SC_RA_RAM_OP_PARAM_GUARD__W 2 -#define SC_RA_RAM_OP_PARAM_GUARD__M 0xC -#define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 -#define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 -#define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 -#define SC_RA_RAM_OP_PARAM_GUARD_4 0xC -#define SC_RA_RAM_OP_PARAM_CONST__B 4 -#define SC_RA_RAM_OP_PARAM_CONST__W 2 -#define SC_RA_RAM_OP_PARAM_CONST__M 0x30 -#define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 -#define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 -#define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 -#define SC_RA_RAM_OP_PARAM_HIER__B 6 -#define SC_RA_RAM_OP_PARAM_HIER__W 3 -#define SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 -#define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 -#define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 -#define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 -#define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 -#define SC_RA_RAM_OP_PARAM_RATE__B 9 -#define SC_RA_RAM_OP_PARAM_RATE__W 3 -#define SC_RA_RAM_OP_PARAM_RATE__M 0xE00 -#define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 -#define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 -#define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 -#define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 -#define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 -#define SC_RA_RAM_OP_PARAM_PRIO__B 12 -#define SC_RA_RAM_OP_PARAM_PRIO__W 1 -#define SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 -#define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 -#define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 - -#define SC_RA_RAM_OP_AUTO__A 0x820049 -#define SC_RA_RAM_OP_AUTO__W 6 -#define SC_RA_RAM_OP_AUTO__M 0x3F -#define SC_RA_RAM_OP_AUTO__PRE 0x1F -#define SC_RA_RAM_OP_AUTO_MODE__B 0 -#define SC_RA_RAM_OP_AUTO_MODE__W 1 -#define SC_RA_RAM_OP_AUTO_MODE__M 0x1 -#define SC_RA_RAM_OP_AUTO_GUARD__B 1 -#define SC_RA_RAM_OP_AUTO_GUARD__W 1 -#define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 -#define SC_RA_RAM_OP_AUTO_CONST__B 2 -#define SC_RA_RAM_OP_AUTO_CONST__W 1 -#define SC_RA_RAM_OP_AUTO_CONST__M 0x4 -#define SC_RA_RAM_OP_AUTO_HIER__B 3 -#define SC_RA_RAM_OP_AUTO_HIER__W 1 -#define SC_RA_RAM_OP_AUTO_HIER__M 0x8 -#define SC_RA_RAM_OP_AUTO_RATE__B 4 -#define SC_RA_RAM_OP_AUTO_RATE__W 1 -#define SC_RA_RAM_OP_AUTO_RATE__M 0x10 -#define SC_RA_RAM_OP_AUTO_PRIO__B 5 -#define SC_RA_RAM_OP_AUTO_PRIO__W 1 -#define SC_RA_RAM_OP_AUTO_PRIO__M 0x20 - -#define SC_RA_RAM_PILOT_STATUS__A 0x82004A -#define SC_RA_RAM_PILOT_STATUS__W 16 -#define SC_RA_RAM_PILOT_STATUS__M 0xFFFF -#define SC_RA_RAM_PILOT_STATUS_OK 0x0 -#define SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 -#define SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 - -#define SC_RA_RAM_LOCK__A 0x82004B -#define SC_RA_RAM_LOCK__W 4 -#define SC_RA_RAM_LOCK__M 0xF -#define SC_RA_RAM_LOCK_DEMOD__B 0 -#define SC_RA_RAM_LOCK_DEMOD__W 1 -#define SC_RA_RAM_LOCK_DEMOD__M 0x1 -#define SC_RA_RAM_LOCK_FEC__B 1 -#define SC_RA_RAM_LOCK_FEC__W 1 -#define SC_RA_RAM_LOCK_FEC__M 0x2 -#define SC_RA_RAM_LOCK_MPEG__B 2 -#define SC_RA_RAM_LOCK_MPEG__W 1 -#define SC_RA_RAM_LOCK_MPEG__M 0x4 -#define SC_RA_RAM_LOCK_NODVBT__B 3 -#define SC_RA_RAM_LOCK_NODVBT__W 1 -#define SC_RA_RAM_LOCK_NODVBT__M 0x8 - -#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C -#define SC_RA_RAM_BE_OPT_ENA__W 5 -#define SC_RA_RAM_BE_OPT_ENA__M 0x1F -#define SC_RA_RAM_BE_OPT_ENA__PRE 0x14 -#define SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 -#define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 -#define SC_RA_RAM_BE_OPT_ENA_COCHANNEL 0x2 -#define SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 -#define SC_RA_RAM_BE_OPT_ENA_MAX 0x5 - -#define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D -#define SC_RA_RAM_BE_OPT_DELAY__W 16 -#define SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF -#define SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 -#define SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E -#define SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 -#define SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF -#define SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 -#define SC_RA_RAM_ECHO_THRES__A 0x82004F -#define SC_RA_RAM_ECHO_THRES__W 16 -#define SC_RA_RAM_ECHO_THRES__M 0xFFFF -#define SC_RA_RAM_ECHO_THRES__PRE 0x2A -#define SC_RA_RAM_CONFIG__A 0x820050 -#define SC_RA_RAM_CONFIG__W 16 -#define SC_RA_RAM_CONFIG__M 0xFFFF -#define SC_RA_RAM_CONFIG__PRE 0x54 -#define SC_RA_RAM_CONFIG_ID__B 0 -#define SC_RA_RAM_CONFIG_ID__W 1 -#define SC_RA_RAM_CONFIG_ID__M 0x1 -#define SC_RA_RAM_CONFIG_ID_PRO 0x0 -#define SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 -#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 -#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 -#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 -#define SC_RA_RAM_CONFIG_FR_ENABLE__B 2 -#define SC_RA_RAM_CONFIG_FR_ENABLE__W 1 -#define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 -#define SC_RA_RAM_CONFIG_MIXMODE__B 3 -#define SC_RA_RAM_CONFIG_MIXMODE__W 1 -#define SC_RA_RAM_CONFIG_MIXMODE__M 0x8 -#define SC_RA_RAM_CONFIG_FREQSCAN__B 4 -#define SC_RA_RAM_CONFIG_FREQSCAN__W 1 -#define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 -#define SC_RA_RAM_CONFIG_SLAVE__B 5 -#define SC_RA_RAM_CONFIG_SLAVE__W 1 -#define SC_RA_RAM_CONFIG_SLAVE__M 0x20 -#define SC_RA_RAM_CONFIG_FAR_OFF__B 6 -#define SC_RA_RAM_CONFIG_FAR_OFF__W 1 -#define SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 -#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 -#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 -#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 -#define SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 -#define SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 -#define SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 -#define SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 -#define SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 -#define SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 - -#define SC_RA_RAM_PILOT_THRES_SPD__A 0x820051 -#define SC_RA_RAM_PILOT_THRES_SPD__W 16 -#define SC_RA_RAM_PILOT_THRES_SPD__M 0xFFFF -#define SC_RA_RAM_PILOT_THRES_SPD__PRE 0x4 -#define SC_RA_RAM_PILOT_THRES_CPD__A 0x820052 -#define SC_RA_RAM_PILOT_THRES_CPD__W 16 -#define SC_RA_RAM_PILOT_THRES_CPD__M 0xFFFF -#define SC_RA_RAM_PILOT_THRES_CPD__PRE 0x4 -#define SC_RA_RAM_PILOT_THRES_FREQSCAN__A 0x820053 -#define SC_RA_RAM_PILOT_THRES_FREQSCAN__W 16 -#define SC_RA_RAM_PILOT_THRES_FREQSCAN__M 0xFFFF -#define SC_RA_RAM_PILOT_THRES_FREQSCAN__PRE 0x406 - -#define SC_RA_RAM_CO_THRES_8K__A 0x820055 -#define SC_RA_RAM_CO_THRES_8K__W 16 -#define SC_RA_RAM_CO_THRES_8K__M 0xFFFF -#define SC_RA_RAM_CO_THRES_8K__PRE 0x10E -#define SC_RA_RAM_CO_THRES_2K__A 0x820056 -#define SC_RA_RAM_CO_THRES_2K__W 16 -#define SC_RA_RAM_CO_THRES_2K__M 0xFFFF -#define SC_RA_RAM_CO_THRES_2K__PRE 0x208 -#define SC_RA_RAM_CO_LEVEL__A 0x820057 -#define SC_RA_RAM_CO_LEVEL__W 16 -#define SC_RA_RAM_CO_LEVEL__M 0xFFFF -#define SC_RA_RAM_CO_DETECT__A 0x820058 -#define SC_RA_RAM_CO_DETECT__W 16 -#define SC_RA_RAM_CO_DETECT__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__A 0x820059 -#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__PRE 0xFFDB -#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__A 0x82005A -#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__PRE 0xFFEB -#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__A 0x82005B -#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__PRE 0xFFFB -#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__A 0x82005C -#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__PRE 0xFFDD -#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__A 0x82005D -#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__PRE 0xFFED -#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__A 0x82005E -#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__PRE 0xFFFD -#define SC_RA_RAM_MOTION_OFFSET__A 0x82005F -#define SC_RA_RAM_MOTION_OFFSET__W 16 -#define SC_RA_RAM_MOTION_OFFSET__M 0xFFFF -#define SC_RA_RAM_MOTION_OFFSET__PRE 0x2 -#define SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 -#define SC_RA_RAM_STATE_PROC_STOP__XSZ 12 -#define SC_RA_RAM_STATE_PROC_STOP__W 16 -#define SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF -#define SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE -#define SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 -#define SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_10__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_11__PRE 0xFFFE -#define SC_RA_RAM_STATE_PROC_STOP_12__PRE 0xFFFE -#define SC_RA_RAM_STATE_PROC_START__AX 0x820070 -#define SC_RA_RAM_STATE_PROC_START__XSZ 12 -#define SC_RA_RAM_STATE_PROC_START__W 16 -#define SC_RA_RAM_STATE_PROC_START__M 0xFFFF -#define SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 -#define SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 -#define SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 -#define SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 -#define SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 -#define SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_START_7__PRE 0x10 -#define SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_START_9__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_START_10__PRE 0x30 -#define SC_RA_RAM_STATE_PROC_START_11__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_START_12__PRE 0x0 -#define SC_RA_RAM_IF_SAVE__AX 0x82008E -#define SC_RA_RAM_IF_SAVE__XSZ 2 -#define SC_RA_RAM_IF_SAVE__W 16 -#define SC_RA_RAM_IF_SAVE__M 0xFFFF -#define SC_RA_RAM_FR_THRES__A 0x82007D -#define SC_RA_RAM_FR_THRES__W 16 -#define SC_RA_RAM_FR_THRES__M 0xFFFF -#define SC_RA_RAM_FR_THRES__PRE 0x1A2C -#define SC_RA_RAM_STATUS__A 0x82007E -#define SC_RA_RAM_STATUS__W 16 -#define SC_RA_RAM_STATUS__M 0xFFFF -#define SC_RA_RAM_NF_BORDER_INIT__A 0x82007F -#define SC_RA_RAM_NF_BORDER_INIT__W 16 -#define SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF -#define SC_RA_RAM_NF_BORDER_INIT__PRE 0x500 -#define SC_RA_RAM_TIMER__A 0x820080 -#define SC_RA_RAM_TIMER__W 16 -#define SC_RA_RAM_TIMER__M 0xFFFF -#define SC_RA_RAM_FI_OFFSET__A 0x820081 -#define SC_RA_RAM_FI_OFFSET__W 16 -#define SC_RA_RAM_FI_OFFSET__M 0xFFFF -#define SC_RA_RAM_FI_OFFSET__PRE 0x382 -#define SC_RA_RAM_ECHO_GUARD__A 0x820082 -#define SC_RA_RAM_ECHO_GUARD__W 16 -#define SC_RA_RAM_ECHO_GUARD__M 0xFFFF -#define SC_RA_RAM_ECHO_GUARD__PRE 0x18 - -#define SC_RA_RAM_IR_FREQ__A 0x8200D0 -#define SC_RA_RAM_IR_FREQ__W 16 -#define SC_RA_RAM_IR_FREQ__M 0xFFFF -#define SC_RA_RAM_IR_FREQ__PRE 0x0 - -#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 -#define SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 -#define SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF -#define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 -#define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 -#define SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 -#define SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF -#define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 -#define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 -#define SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 -#define SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF -#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 - -#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 -#define SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 -#define SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF -#define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 -#define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 -#define SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 -#define SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF -#define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 -#define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 -#define SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 -#define SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF -#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 - -#define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 -#define SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 -#define SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF -#define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 -#define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 -#define SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 -#define SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF -#define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 -#define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 -#define SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 -#define SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF -#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 - -#define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA -#define SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 -#define SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF -#define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB -#define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB -#define SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 -#define SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF -#define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 -#define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC -#define SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 -#define SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF -#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 - -#define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD -#define SC_RA_RAM_ECHO_SHIFT_LIM__W 16 -#define SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF -#define SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0xFFFF -#define SC_RA_RAM_ECHO_AGE__A 0x8200DE -#define SC_RA_RAM_ECHO_AGE__W 16 -#define SC_RA_RAM_ECHO_AGE__M 0xFFFF -#define SC_RA_RAM_ECHO_AGE__PRE 0xFFFF -#define SC_RA_RAM_ECHO_FILTER__A 0x8200DF -#define SC_RA_RAM_ECHO_FILTER__W 16 -#define SC_RA_RAM_ECHO_FILTER__M 0xFFFF -#define SC_RA_RAM_ECHO_FILTER__PRE 0x2 - -#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 -#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 -#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF -#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 -#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 -#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 -#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF -#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 -#define SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 -#define SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 -#define SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF -#define SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 - -#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 -#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 -#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF -#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE -#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 -#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 -#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF -#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 -#define SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 -#define SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 -#define SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF -#define SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 - -#define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 -#define SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 -#define SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF -#define SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x10 -#define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 -#define SC_RA_RAM_SAMPLE_RATE_STEP__W 16 -#define SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF -#define SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x113 - -#define SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA -#define SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 -#define SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF -#define SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 -#define SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB -#define SC_RA_RAM_TPS_TIMEOUT__W 16 -#define SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF -#define SC_RA_RAM_BAND__A 0x8200EC -#define SC_RA_RAM_BAND__W 16 -#define SC_RA_RAM_BAND__M 0xFFFF -#define SC_RA_RAM_BAND__PRE 0x0 -#define SC_RA_RAM_BAND_INTERVAL__B 0 -#define SC_RA_RAM_BAND_INTERVAL__W 4 -#define SC_RA_RAM_BAND_INTERVAL__M 0xF -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 - -#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED -#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 -#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF -#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 -#define SC_RA_RAM_REG__AX 0x8200F0 -#define SC_RA_RAM_REG__XSZ 2 -#define SC_RA_RAM_REG__W 16 -#define SC_RA_RAM_REG__M 0xFFFF -#define SC_RA_RAM_BREAK__A 0x8200F2 -#define SC_RA_RAM_BREAK__W 16 -#define SC_RA_RAM_BREAK__M 0xFFFF -#define SC_RA_RAM_BOOTCOUNT__A 0x8200F3 -#define SC_RA_RAM_BOOTCOUNT__W 16 -#define SC_RA_RAM_BOOTCOUNT__M 0xFFFF - -#define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 -#define SC_RA_RAM_LC_ABS_2K__W 16 -#define SC_RA_RAM_LC_ABS_2K__M 0xFFFF -#define SC_RA_RAM_LC_ABS_2K__PRE 0x1F -#define SC_RA_RAM_LC_ABS_8K__A 0x8200F5 -#define SC_RA_RAM_LC_ABS_8K__W 16 -#define SC_RA_RAM_LC_ABS_8K__M 0xFFFF -#define SC_RA_RAM_LC_ABS_8K__PRE 0x1F - -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__A 0x8200F6 -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__W 16 -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__M 0xFFFF -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__PRE 0x1 -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__A 0x8200F7 -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__W 16 -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__M 0xFFFF -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__PRE 0x0 - -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__A 0x8200F8 -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__W 16 -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__M 0xFFFF -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__PRE 0x3 -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__A 0x8200F9 -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__W 16 -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__M 0xFFFF -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__PRE 0x2 -#define SC_RA_RAM_RELOCK__A 0x8200FE -#define SC_RA_RAM_RELOCK__W 16 -#define SC_RA_RAM_RELOCK__M 0xFFFF -#define SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF -#define SC_RA_RAM_STACKUNDERFLOW__W 16 -#define SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF - -#define SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 -#define SC_RA_RAM_NF_MAXECHOTOKEN__W 16 -#define SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF -#define SC_RA_RAM_NF_PREPOST__A 0x820149 -#define SC_RA_RAM_NF_PREPOST__W 16 -#define SC_RA_RAM_NF_PREPOST__M 0xFFFF -#define SC_RA_RAM_NF_PREBORDER__A 0x82014A -#define SC_RA_RAM_NF_PREBORDER__W 16 -#define SC_RA_RAM_NF_PREBORDER__M 0xFFFF -#define SC_RA_RAM_NF_START__A 0x82014B -#define SC_RA_RAM_NF_START__W 16 -#define SC_RA_RAM_NF_START__M 0xFFFF -#define SC_RA_RAM_NF_MINISI__AX 0x82014C -#define SC_RA_RAM_NF_MINISI__XSZ 2 -#define SC_RA_RAM_NF_MINISI__W 16 -#define SC_RA_RAM_NF_MINISI__M 0xFFFF -#define SC_RA_RAM_NF_MAXECHO__A 0x82014E -#define SC_RA_RAM_NF_MAXECHO__W 16 -#define SC_RA_RAM_NF_MAXECHO__M 0xFFFF -#define SC_RA_RAM_NF_NRECHOES__A 0x82014F -#define SC_RA_RAM_NF_NRECHOES__W 16 -#define SC_RA_RAM_NF_NRECHOES__M 0xFFFF -#define SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 -#define SC_RA_RAM_NF_ECHOTABLE__XSZ 16 -#define SC_RA_RAM_NF_ECHOTABLE__W 16 -#define SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF - -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6 -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 - -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 - -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 - -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 - -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 - -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 - -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 - -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5 -#define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE -#define SC_RA_RAM_DRIVER_VERSION__XSZ 2 -#define SC_RA_RAM_DRIVER_VERSION__W 16 -#define SC_RA_RAM_DRIVER_VERSION__M 0xFFFF -#define SC_RA_RAM_EVENT0_MIN 0x7 -#define SC_RA_RAM_EVENT0_FE_CU 0x7 -#define SC_RA_RAM_EVENT0_CE 0xA -#define SC_RA_RAM_EVENT0_EQ 0xE -#define SC_RA_RAM_EVENT0_MAX 0xF -#define SC_RA_RAM_EVENT1_MIN 0x8 -#define SC_RA_RAM_EVENT1_EC_OD 0x8 -#define SC_RA_RAM_EVENT1_LC 0xC -#define SC_RA_RAM_EVENT1_MAX 0xD -#define SC_RA_RAM_PROC_LOCKTRACK 0x0 -#define SC_RA_RAM_PROC_MODE_GUARD 0x1 -#define SC_RA_RAM_PROC_PILOTS 0x2 -#define SC_RA_RAM_PROC_FESTART_ADJUST 0x3 -#define SC_RA_RAM_PROC_ECHO 0x4 -#define SC_RA_RAM_PROC_BE_OPT 0x5 -#define SC_RA_RAM_PROC_EQ 0x7 -#define SC_RA_RAM_PROC_MAX 0x8 - -#define SC_IF_RAM_TRP_RST__AX 0x830000 -#define SC_IF_RAM_TRP_RST__XSZ 2 -#define SC_IF_RAM_TRP_RST__W 12 -#define SC_IF_RAM_TRP_RST__M 0xFFF - -#define SC_IF_RAM_TRP_BPT0__AX 0x830002 -#define SC_IF_RAM_TRP_BPT0__XSZ 2 -#define SC_IF_RAM_TRP_BPT0__W 12 -#define SC_IF_RAM_TRP_BPT0__M 0xFFF - -#define SC_IF_RAM_TRP_STKU__AX 0x830004 -#define SC_IF_RAM_TRP_STKU__XSZ 2 -#define SC_IF_RAM_TRP_STKU__W 12 -#define SC_IF_RAM_TRP_STKU__M 0xFFF - -#define SC_IF_RAM_VERSION_MA_MI__A 0x830FFE -#define SC_IF_RAM_VERSION_MA_MI__W 12 -#define SC_IF_RAM_VERSION_MA_MI__M 0xFFF - -#define SC_IF_RAM_VERSION_PATCH__A 0x830FFF -#define SC_IF_RAM_VERSION_PATCH__W 12 -#define SC_IF_RAM_VERSION_PATCH__M 0xFFF - -#define FE_COMM_EXEC__A 0xC00000 -#define FE_COMM_EXEC__W 3 -#define FE_COMM_EXEC__M 0x7 -#define FE_COMM_EXEC_CTL__B 0 -#define FE_COMM_EXEC_CTL__W 3 -#define FE_COMM_EXEC_CTL__M 0x7 -#define FE_COMM_EXEC_CTL_STOP 0x0 -#define FE_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_COMM_EXEC_CTL_HOLD 0x2 -#define FE_COMM_EXEC_CTL_STEP 0x3 -#define FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define FE_COMM_STATE__A 0xC00001 -#define FE_COMM_STATE__W 16 -#define FE_COMM_STATE__M 0xFFFF -#define FE_COMM_MB__A 0xC00002 -#define FE_COMM_MB__W 16 -#define FE_COMM_MB__M 0xFFFF -#define FE_COMM_SERVICE0__A 0xC00003 -#define FE_COMM_SERVICE0__W 16 -#define FE_COMM_SERVICE0__M 0xFFFF -#define FE_COMM_SERVICE1__A 0xC00004 -#define FE_COMM_SERVICE1__W 16 -#define FE_COMM_SERVICE1__M 0xFFFF -#define FE_COMM_INT_STA__A 0xC00007 -#define FE_COMM_INT_STA__W 16 -#define FE_COMM_INT_STA__M 0xFFFF -#define FE_COMM_INT_MSK__A 0xC00008 -#define FE_COMM_INT_MSK__W 16 -#define FE_COMM_INT_MSK__M 0xFFFF - -#define FE_AD_SID 0x1 - -#define FE_AD_REG_COMM_EXEC__A 0xC10000 -#define FE_AD_REG_COMM_EXEC__W 3 -#define FE_AD_REG_COMM_EXEC__M 0x7 -#define FE_AD_REG_COMM_EXEC_CTL__B 0 -#define FE_AD_REG_COMM_EXEC_CTL__W 3 -#define FE_AD_REG_COMM_EXEC_CTL__M 0x7 -#define FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_AD_REG_COMM_MB__A 0xC10002 -#define FE_AD_REG_COMM_MB__W 2 -#define FE_AD_REG_COMM_MB__M 0x3 -#define FE_AD_REG_COMM_MB_CTR__B 0 -#define FE_AD_REG_COMM_MB_CTR__W 1 -#define FE_AD_REG_COMM_MB_CTR__M 0x1 -#define FE_AD_REG_COMM_MB_CTR_OFF 0x0 -#define FE_AD_REG_COMM_MB_CTR_ON 0x1 -#define FE_AD_REG_COMM_MB_OBS__B 1 -#define FE_AD_REG_COMM_MB_OBS__W 1 -#define FE_AD_REG_COMM_MB_OBS__M 0x2 -#define FE_AD_REG_COMM_MB_OBS_OFF 0x0 -#define FE_AD_REG_COMM_MB_OBS_ON 0x2 - -#define FE_AD_REG_COMM_SERVICE0__A 0xC10003 -#define FE_AD_REG_COMM_SERVICE0__W 10 -#define FE_AD_REG_COMM_SERVICE0__M 0x3FF -#define FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 -#define FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 -#define FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 - -#define FE_AD_REG_COMM_SERVICE1__A 0xC10004 -#define FE_AD_REG_COMM_SERVICE1__W 11 -#define FE_AD_REG_COMM_SERVICE1__M 0x7FF - -#define FE_AD_REG_COMM_INT_STA__A 0xC10007 -#define FE_AD_REG_COMM_INT_STA__W 2 -#define FE_AD_REG_COMM_INT_STA__M 0x3 -#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 -#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 -#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 - -#define FE_AD_REG_COMM_INT_MSK__A 0xC10008 -#define FE_AD_REG_COMM_INT_MSK__W 2 -#define FE_AD_REG_COMM_INT_MSK__M 0x3 -#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 -#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 -#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 - -#define FE_AD_REG_CUR_SEL__A 0xC10010 -#define FE_AD_REG_CUR_SEL__W 2 -#define FE_AD_REG_CUR_SEL__M 0x3 -#define FE_AD_REG_CUR_SEL_INIT 0x2 - -#define FE_AD_REG_OVERFLOW__A 0xC10011 -#define FE_AD_REG_OVERFLOW__W 1 -#define FE_AD_REG_OVERFLOW__M 0x1 -#define FE_AD_REG_OVERFLOW_INIT 0x0 - -#define FE_AD_REG_FDB_IN__A 0xC10012 -#define FE_AD_REG_FDB_IN__W 1 -#define FE_AD_REG_FDB_IN__M 0x1 -#define FE_AD_REG_FDB_IN_INIT 0x0 - -#define FE_AD_REG_PD__A 0xC10013 -#define FE_AD_REG_PD__W 1 -#define FE_AD_REG_PD__M 0x1 -#define FE_AD_REG_PD_INIT 0x1 - -#define FE_AD_REG_INVEXT__A 0xC10014 -#define FE_AD_REG_INVEXT__W 1 -#define FE_AD_REG_INVEXT__M 0x1 -#define FE_AD_REG_INVEXT_INIT 0x0 - -#define FE_AD_REG_CLKNEG__A 0xC10015 -#define FE_AD_REG_CLKNEG__W 1 -#define FE_AD_REG_CLKNEG__M 0x1 -#define FE_AD_REG_CLKNEG_INIT 0x0 - -#define FE_AD_REG_MON_IN_MUX__A 0xC10016 -#define FE_AD_REG_MON_IN_MUX__W 2 -#define FE_AD_REG_MON_IN_MUX__M 0x3 -#define FE_AD_REG_MON_IN_MUX_INIT 0x0 - -#define FE_AD_REG_MON_IN5__A 0xC10017 -#define FE_AD_REG_MON_IN5__W 10 -#define FE_AD_REG_MON_IN5__M 0x3FF -#define FE_AD_REG_MON_IN5_INIT 0x0 - -#define FE_AD_REG_MON_IN4__A 0xC10018 -#define FE_AD_REG_MON_IN4__W 10 -#define FE_AD_REG_MON_IN4__M 0x3FF -#define FE_AD_REG_MON_IN4_INIT 0x0 - -#define FE_AD_REG_MON_IN3__A 0xC10019 -#define FE_AD_REG_MON_IN3__W 10 -#define FE_AD_REG_MON_IN3__M 0x3FF -#define FE_AD_REG_MON_IN3_INIT 0x0 - -#define FE_AD_REG_MON_IN2__A 0xC1001A -#define FE_AD_REG_MON_IN2__W 10 -#define FE_AD_REG_MON_IN2__M 0x3FF -#define FE_AD_REG_MON_IN2_INIT 0x0 - -#define FE_AD_REG_MON_IN1__A 0xC1001B -#define FE_AD_REG_MON_IN1__W 10 -#define FE_AD_REG_MON_IN1__M 0x3FF -#define FE_AD_REG_MON_IN1_INIT 0x0 - -#define FE_AD_REG_MON_IN0__A 0xC1001C -#define FE_AD_REG_MON_IN0__W 10 -#define FE_AD_REG_MON_IN0__M 0x3FF -#define FE_AD_REG_MON_IN0_INIT 0x0 - -#define FE_AD_REG_MON_IN_VAL__A 0xC1001D -#define FE_AD_REG_MON_IN_VAL__W 1 -#define FE_AD_REG_MON_IN_VAL__M 0x1 -#define FE_AD_REG_MON_IN_VAL_INIT 0x0 - -#define FE_AD_REG_CTR_CLK_O__A 0xC1001E -#define FE_AD_REG_CTR_CLK_O__W 1 -#define FE_AD_REG_CTR_CLK_O__M 0x1 -#define FE_AD_REG_CTR_CLK_O_INIT 0x0 - -#define FE_AD_REG_CTR_CLK_E_O__A 0xC1001F -#define FE_AD_REG_CTR_CLK_E_O__W 1 -#define FE_AD_REG_CTR_CLK_E_O__M 0x1 -#define FE_AD_REG_CTR_CLK_E_O_INIT 0x1 - -#define FE_AD_REG_CTR_VAL_O__A 0xC10020 -#define FE_AD_REG_CTR_VAL_O__W 1 -#define FE_AD_REG_CTR_VAL_O__M 0x1 -#define FE_AD_REG_CTR_VAL_O_INIT 0x0 - -#define FE_AD_REG_CTR_VAL_E_O__A 0xC10021 -#define FE_AD_REG_CTR_VAL_E_O__W 1 -#define FE_AD_REG_CTR_VAL_E_O__M 0x1 -#define FE_AD_REG_CTR_VAL_E_O_INIT 0x1 - -#define FE_AD_REG_CTR_DATA_O__A 0xC10022 -#define FE_AD_REG_CTR_DATA_O__W 10 -#define FE_AD_REG_CTR_DATA_O__M 0x3FF -#define FE_AD_REG_CTR_DATA_O_INIT 0x0 - -#define FE_AD_REG_CTR_DATA_E_O__A 0xC10023 -#define FE_AD_REG_CTR_DATA_E_O__W 10 -#define FE_AD_REG_CTR_DATA_E_O__M 0x3FF -#define FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF - -#define FE_AG_SID 0x2 - -#define FE_AG_REG_COMM_EXEC__A 0xC20000 -#define FE_AG_REG_COMM_EXEC__W 3 -#define FE_AG_REG_COMM_EXEC__M 0x7 -#define FE_AG_REG_COMM_EXEC_CTL__B 0 -#define FE_AG_REG_COMM_EXEC_CTL__W 3 -#define FE_AG_REG_COMM_EXEC_CTL__M 0x7 -#define FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_AG_REG_COMM_STATE__A 0xC20001 -#define FE_AG_REG_COMM_STATE__W 4 -#define FE_AG_REG_COMM_STATE__M 0xF - -#define FE_AG_REG_COMM_MB__A 0xC20002 -#define FE_AG_REG_COMM_MB__W 2 -#define FE_AG_REG_COMM_MB__M 0x3 -#define FE_AG_REG_COMM_MB_CTR__B 0 -#define FE_AG_REG_COMM_MB_CTR__W 1 -#define FE_AG_REG_COMM_MB_CTR__M 0x1 -#define FE_AG_REG_COMM_MB_CTR_OFF 0x0 -#define FE_AG_REG_COMM_MB_CTR_ON 0x1 -#define FE_AG_REG_COMM_MB_OBS__B 1 -#define FE_AG_REG_COMM_MB_OBS__W 1 -#define FE_AG_REG_COMM_MB_OBS__M 0x2 -#define FE_AG_REG_COMM_MB_OBS_OFF 0x0 -#define FE_AG_REG_COMM_MB_OBS_ON 0x2 - -#define FE_AG_REG_COMM_SERVICE0__A 0xC20003 -#define FE_AG_REG_COMM_SERVICE0__W 10 -#define FE_AG_REG_COMM_SERVICE0__M 0x3FF - -#define FE_AG_REG_COMM_SERVICE1__A 0xC20004 -#define FE_AG_REG_COMM_SERVICE1__W 11 -#define FE_AG_REG_COMM_SERVICE1__M 0x7FF - -#define FE_AG_REG_COMM_INT_STA__A 0xC20007 -#define FE_AG_REG_COMM_INT_STA__W 8 -#define FE_AG_REG_COMM_INT_STA__M 0xFF -#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 -#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 -#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 -#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 -#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 -#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 -#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 -#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 -#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 -#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 -#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 -#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 -#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__B 6 -#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__M 0x40 -#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 -#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 - -#define FE_AG_REG_COMM_INT_MSK__A 0xC20008 -#define FE_AG_REG_COMM_INT_MSK__W 8 -#define FE_AG_REG_COMM_INT_MSK__M 0xFF -#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 -#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 -#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 -#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 -#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 -#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 -#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 -#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 -#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 -#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 -#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 -#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 -#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__B 6 -#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__M 0x40 -#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 -#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 - -#define FE_AG_REG_AG_MODE_LOP__A 0xC20010 -#define FE_AG_REG_AG_MODE_LOP__W 16 -#define FE_AG_REG_AG_MODE_LOP__M 0xFFFF -#define FE_AG_REG_AG_MODE_LOP_INIT 0x0 - -#define FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 -#define FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 -#define FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 - -#define FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 -#define FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 - -#define FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 -#define FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 -#define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 - -#define FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 -#define FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 -#define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 - -#define FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 -#define FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 -#define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 - -#define FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 -#define FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 -#define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 - -#define FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 -#define FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 -#define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 - -#define FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 -#define FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 -#define FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 - -#define FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 -#define FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 -#define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 - -#define FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 -#define FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 -#define FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 - -#define FE_AG_REG_AG_MODE_LOP_MODE_A__B 10 -#define FE_AG_REG_AG_MODE_LOP_MODE_A__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_A__M 0x400 -#define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_B 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_CB 0x400 - -#define FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 -#define FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 -#define FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 - -#define FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 -#define FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 -#define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 - -#define FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 -#define FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 -#define FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 - -#define FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 -#define FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 -#define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 - -#define FE_AG_REG_AG_MODE_LOP_MODE_F__B 15 -#define FE_AG_REG_AG_MODE_LOP_MODE_F__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_F__M 0x8000 -#define FE_AG_REG_AG_MODE_LOP_MODE_F_DISABLE 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_F_ENABLE 0x8000 - -#define FE_AG_REG_AG_MODE_HIP__A 0xC20011 -#define FE_AG_REG_AG_MODE_HIP__W 2 -#define FE_AG_REG_AG_MODE_HIP__M 0x3 -#define FE_AG_REG_AG_MODE_HIP_INIT 0x0 - -#define FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 -#define FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 -#define FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 -#define FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 -#define FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 - -#define FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 -#define FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 -#define FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 -#define FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 -#define FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 - -#define FE_AG_REG_AG_PGA_MODE__A 0xC20012 -#define FE_AG_REG_AG_PGA_MODE__W 3 -#define FE_AG_REG_AG_PGA_MODE__M 0x7 -#define FE_AG_REG_AG_PGA_MODE_INIT 0x0 -#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 -#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 -#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 -#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 -#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 -#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 -#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 -#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 - -#define FE_AG_REG_AG_AGC_SIO__A 0xC20013 -#define FE_AG_REG_AG_AGC_SIO__W 2 -#define FE_AG_REG_AG_AGC_SIO__M 0x3 -#define FE_AG_REG_AG_AGC_SIO_INIT 0x3 - -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 - -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 - -#define FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 -#define FE_AG_REG_AG_AGC_USR_DAT__W 2 -#define FE_AG_REG_AG_AGC_USR_DAT__M 0x3 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 - -#define FE_AG_REG_AG_PWD__A 0xC20015 -#define FE_AG_REG_AG_PWD__W 5 -#define FE_AG_REG_AG_PWD__M 0x1F -#define FE_AG_REG_AG_PWD_INIT 0x1F - -#define FE_AG_REG_AG_PWD_PWD_PD1__B 0 -#define FE_AG_REG_AG_PWD_PWD_PD1__W 1 -#define FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 -#define FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 -#define FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 - -#define FE_AG_REG_AG_PWD_PWD_PD2__B 1 -#define FE_AG_REG_AG_PWD_PWD_PD2__W 1 -#define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 -#define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 -#define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 - -#define FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 -#define FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 -#define FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 -#define FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 -#define FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 - -#define FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 -#define FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 -#define FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 -#define FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 -#define FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 - -#define FE_AG_REG_AG_PWD_PWD_AAF__B 4 -#define FE_AG_REG_AG_PWD_PWD_AAF__W 1 -#define FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 -#define FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 -#define FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 - -#define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 -#define FE_AG_REG_DCE_AUR_CNT__W 5 -#define FE_AG_REG_DCE_AUR_CNT__M 0x1F -#define FE_AG_REG_DCE_AUR_CNT_INIT 0x0 - -#define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 -#define FE_AG_REG_DCE_RUR_CNT__W 5 -#define FE_AG_REG_DCE_RUR_CNT__M 0x1F -#define FE_AG_REG_DCE_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_DCE_AVE_DAT__A 0xC20018 -#define FE_AG_REG_DCE_AVE_DAT__W 10 -#define FE_AG_REG_DCE_AVE_DAT__M 0x3FF - -#define FE_AG_REG_DEC_AVE_WRI__A 0xC20019 -#define FE_AG_REG_DEC_AVE_WRI__W 10 -#define FE_AG_REG_DEC_AVE_WRI__M 0x3FF -#define FE_AG_REG_DEC_AVE_WRI_INIT 0x0 - -#define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A -#define FE_AG_REG_ACE_AUR_CNT__W 5 -#define FE_AG_REG_ACE_AUR_CNT__M 0x1F -#define FE_AG_REG_ACE_AUR_CNT_INIT 0x0 - -#define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B -#define FE_AG_REG_ACE_RUR_CNT__W 5 -#define FE_AG_REG_ACE_RUR_CNT__M 0x1F -#define FE_AG_REG_ACE_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_ACE_AVE_DAT__A 0xC2001C -#define FE_AG_REG_ACE_AVE_DAT__W 10 -#define FE_AG_REG_ACE_AVE_DAT__M 0x3FF - -#define FE_AG_REG_AEC_AVE_INC__A 0xC2001D -#define FE_AG_REG_AEC_AVE_INC__W 10 -#define FE_AG_REG_AEC_AVE_INC__M 0x3FF -#define FE_AG_REG_AEC_AVE_INC_INIT 0x0 - -#define FE_AG_REG_AEC_AVE_DAT__A 0xC2001E -#define FE_AG_REG_AEC_AVE_DAT__W 10 -#define FE_AG_REG_AEC_AVE_DAT__M 0x3FF - -#define FE_AG_REG_AEC_CLP_LVL__A 0xC2001F -#define FE_AG_REG_AEC_CLP_LVL__W 16 -#define FE_AG_REG_AEC_CLP_LVL__M 0xFFFF -#define FE_AG_REG_AEC_CLP_LVL_INIT 0x0 - -#define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 -#define FE_AG_REG_CDR_RUR_CNT__W 5 -#define FE_AG_REG_CDR_RUR_CNT__M 0x1F -#define FE_AG_REG_CDR_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_CDR_CLP_DAT__A 0xC20021 -#define FE_AG_REG_CDR_CLP_DAT__W 16 -#define FE_AG_REG_CDR_CLP_DAT__M 0xFFFF - -#define FE_AG_REG_CDR_CLP_POS__A 0xC20022 -#define FE_AG_REG_CDR_CLP_POS__W 10 -#define FE_AG_REG_CDR_CLP_POS__M 0x3FF -#define FE_AG_REG_CDR_CLP_POS_INIT 0x0 - -#define FE_AG_REG_CDR_CLP_NEG__A 0xC20023 -#define FE_AG_REG_CDR_CLP_NEG__W 10 -#define FE_AG_REG_CDR_CLP_NEG__M 0x3FF -#define FE_AG_REG_CDR_CLP_NEG_INIT 0x0 - -#define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 -#define FE_AG_REG_EGC_RUR_CNT__W 5 -#define FE_AG_REG_EGC_RUR_CNT__M 0x1F -#define FE_AG_REG_EGC_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_EGC_SET_LVL__A 0xC20025 -#define FE_AG_REG_EGC_SET_LVL__W 9 -#define FE_AG_REG_EGC_SET_LVL__M 0x1FF -#define FE_AG_REG_EGC_SET_LVL_INIT 0x0 - -#define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 -#define FE_AG_REG_EGC_FLA_RGN__W 9 -#define FE_AG_REG_EGC_FLA_RGN__M 0x1FF -#define FE_AG_REG_EGC_FLA_RGN_INIT 0x0 - -#define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 -#define FE_AG_REG_EGC_SLO_RGN__W 9 -#define FE_AG_REG_EGC_SLO_RGN__M 0x1FF -#define FE_AG_REG_EGC_SLO_RGN_INIT 0x0 - -#define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 -#define FE_AG_REG_EGC_JMP_PSN__W 4 -#define FE_AG_REG_EGC_JMP_PSN__M 0xF -#define FE_AG_REG_EGC_JMP_PSN_INIT 0x0 - -#define FE_AG_REG_EGC_FLA_INC__A 0xC20029 -#define FE_AG_REG_EGC_FLA_INC__W 16 -#define FE_AG_REG_EGC_FLA_INC__M 0xFFFF -#define FE_AG_REG_EGC_FLA_INC_INIT 0x0 - -#define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A -#define FE_AG_REG_EGC_FLA_DEC__W 16 -#define FE_AG_REG_EGC_FLA_DEC__M 0xFFFF -#define FE_AG_REG_EGC_FLA_DEC_INIT 0x0 - -#define FE_AG_REG_EGC_SLO_INC__A 0xC2002B -#define FE_AG_REG_EGC_SLO_INC__W 16 -#define FE_AG_REG_EGC_SLO_INC__M 0xFFFF -#define FE_AG_REG_EGC_SLO_INC_INIT 0x0 - -#define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C -#define FE_AG_REG_EGC_SLO_DEC__W 16 -#define FE_AG_REG_EGC_SLO_DEC__M 0xFFFF -#define FE_AG_REG_EGC_SLO_DEC_INIT 0x0 - -#define FE_AG_REG_EGC_FAS_INC__A 0xC2002D -#define FE_AG_REG_EGC_FAS_INC__W 16 -#define FE_AG_REG_EGC_FAS_INC__M 0xFFFF -#define FE_AG_REG_EGC_FAS_INC_INIT 0x0 - -#define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E -#define FE_AG_REG_EGC_FAS_DEC__W 16 -#define FE_AG_REG_EGC_FAS_DEC__M 0xFFFF -#define FE_AG_REG_EGC_FAS_DEC_INIT 0x0 - -#define FE_AG_REG_EGC_MAP_DAT__A 0xC2002F -#define FE_AG_REG_EGC_MAP_DAT__W 16 -#define FE_AG_REG_EGC_MAP_DAT__M 0xFFFF - -#define FE_AG_REG_PM1_AGC_WRI__A 0xC20030 -#define FE_AG_REG_PM1_AGC_WRI__W 11 -#define FE_AG_REG_PM1_AGC_WRI__M 0x7FF -#define FE_AG_REG_PM1_AGC_WRI_INIT 0x0 - -#define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 -#define FE_AG_REG_GC1_AGC_RIC__W 16 -#define FE_AG_REG_GC1_AGC_RIC__M 0xFFFF -#define FE_AG_REG_GC1_AGC_RIC_INIT 0x0 - -#define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 -#define FE_AG_REG_GC1_AGC_OFF__W 16 -#define FE_AG_REG_GC1_AGC_OFF__M 0xFFFF -#define FE_AG_REG_GC1_AGC_OFF_INIT 0x0 - -#define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 -#define FE_AG_REG_GC1_AGC_MAX__W 10 -#define FE_AG_REG_GC1_AGC_MAX__M 0x3FF -#define FE_AG_REG_GC1_AGC_MAX_INIT 0x0 - -#define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 -#define FE_AG_REG_GC1_AGC_MIN__W 10 -#define FE_AG_REG_GC1_AGC_MIN__M 0x3FF -#define FE_AG_REG_GC1_AGC_MIN_INIT 0x0 - -#define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 -#define FE_AG_REG_GC1_AGC_DAT__W 10 -#define FE_AG_REG_GC1_AGC_DAT__M 0x3FF - -#define FE_AG_REG_PM2_AGC_WRI__A 0xC20036 -#define FE_AG_REG_PM2_AGC_WRI__W 11 -#define FE_AG_REG_PM2_AGC_WRI__M 0x7FF -#define FE_AG_REG_PM2_AGC_WRI_INIT 0x0 - -#define FE_AG_REG_GC2_AGC_RIC__A 0xC20037 -#define FE_AG_REG_GC2_AGC_RIC__W 16 -#define FE_AG_REG_GC2_AGC_RIC__M 0xFFFF -#define FE_AG_REG_GC2_AGC_RIC_INIT 0x0 - -#define FE_AG_REG_GC2_AGC_OFF__A 0xC20038 -#define FE_AG_REG_GC2_AGC_OFF__W 16 -#define FE_AG_REG_GC2_AGC_OFF__M 0xFFFF -#define FE_AG_REG_GC2_AGC_OFF_INIT 0x0 - -#define FE_AG_REG_GC2_AGC_MAX__A 0xC20039 -#define FE_AG_REG_GC2_AGC_MAX__W 10 -#define FE_AG_REG_GC2_AGC_MAX__M 0x3FF -#define FE_AG_REG_GC2_AGC_MAX_INIT 0x0 - -#define FE_AG_REG_GC2_AGC_MIN__A 0xC2003A -#define FE_AG_REG_GC2_AGC_MIN__W 10 -#define FE_AG_REG_GC2_AGC_MIN__M 0x3FF -#define FE_AG_REG_GC2_AGC_MIN_INIT 0x0 - -#define FE_AG_REG_GC2_AGC_DAT__A 0xC2003B -#define FE_AG_REG_GC2_AGC_DAT__W 10 -#define FE_AG_REG_GC2_AGC_DAT__M 0x3FF - -#define FE_AG_REG_IND_WIN__A 0xC2003C -#define FE_AG_REG_IND_WIN__W 5 -#define FE_AG_REG_IND_WIN__M 0x1F -#define FE_AG_REG_IND_WIN_INIT 0x0 - -#define FE_AG_REG_IND_THD_LOL__A 0xC2003D -#define FE_AG_REG_IND_THD_LOL__W 6 -#define FE_AG_REG_IND_THD_LOL__M 0x3F -#define FE_AG_REG_IND_THD_LOL_INIT 0x0 - -#define FE_AG_REG_IND_THD_HIL__A 0xC2003E -#define FE_AG_REG_IND_THD_HIL__W 6 -#define FE_AG_REG_IND_THD_HIL__M 0x3F -#define FE_AG_REG_IND_THD_HIL_INIT 0x0 - -#define FE_AG_REG_IND_DEL__A 0xC2003F -#define FE_AG_REG_IND_DEL__W 7 -#define FE_AG_REG_IND_DEL__M 0x7F -#define FE_AG_REG_IND_DEL_INIT 0x0 - -#define FE_AG_REG_IND_PD1_WRI__A 0xC20040 -#define FE_AG_REG_IND_PD1_WRI__W 6 -#define FE_AG_REG_IND_PD1_WRI__M 0x3F -#define FE_AG_REG_IND_PD1_WRI_INIT 0x1F - -#define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 -#define FE_AG_REG_PDA_AUR_CNT__W 5 -#define FE_AG_REG_PDA_AUR_CNT__M 0x1F -#define FE_AG_REG_PDA_AUR_CNT_INIT 0x0 - -#define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 -#define FE_AG_REG_PDA_RUR_CNT__W 5 -#define FE_AG_REG_PDA_RUR_CNT__M 0x1F -#define FE_AG_REG_PDA_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 -#define FE_AG_REG_PDA_AVE_DAT__W 6 -#define FE_AG_REG_PDA_AVE_DAT__M 0x3F - -#define FE_AG_REG_PDC_RUR_CNT__A 0xC20044 -#define FE_AG_REG_PDC_RUR_CNT__W 5 -#define FE_AG_REG_PDC_RUR_CNT__M 0x1F -#define FE_AG_REG_PDC_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_PDC_SET_LVL__A 0xC20045 -#define FE_AG_REG_PDC_SET_LVL__W 6 -#define FE_AG_REG_PDC_SET_LVL__M 0x3F -#define FE_AG_REG_PDC_SET_LVL_INIT 0x10 - -#define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 -#define FE_AG_REG_PDC_FLA_RGN__W 6 -#define FE_AG_REG_PDC_FLA_RGN__M 0x3F -#define FE_AG_REG_PDC_FLA_RGN_INIT 0x0 - -#define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 -#define FE_AG_REG_PDC_JMP_PSN__W 3 -#define FE_AG_REG_PDC_JMP_PSN__M 0x7 -#define FE_AG_REG_PDC_JMP_PSN_INIT 0x0 - -#define FE_AG_REG_PDC_FLA_STP__A 0xC20048 -#define FE_AG_REG_PDC_FLA_STP__W 16 -#define FE_AG_REG_PDC_FLA_STP__M 0xFFFF -#define FE_AG_REG_PDC_FLA_STP_INIT 0x0 - -#define FE_AG_REG_PDC_SLO_STP__A 0xC20049 -#define FE_AG_REG_PDC_SLO_STP__W 16 -#define FE_AG_REG_PDC_SLO_STP__M 0xFFFF -#define FE_AG_REG_PDC_SLO_STP_INIT 0x0 - -#define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A -#define FE_AG_REG_PDC_PD2_WRI__W 6 -#define FE_AG_REG_PDC_PD2_WRI__M 0x3F -#define FE_AG_REG_PDC_PD2_WRI_INIT 0x0 - -#define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B -#define FE_AG_REG_PDC_MAP_DAT__W 6 -#define FE_AG_REG_PDC_MAP_DAT__M 0x3F - -#define FE_AG_REG_PDC_MAX__A 0xC2004C -#define FE_AG_REG_PDC_MAX__W 6 -#define FE_AG_REG_PDC_MAX__M 0x3F -#define FE_AG_REG_PDC_MAX_INIT 0x2 - -#define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D -#define FE_AG_REG_TGA_AUR_CNT__W 5 -#define FE_AG_REG_TGA_AUR_CNT__M 0x1F -#define FE_AG_REG_TGA_AUR_CNT_INIT 0x0 - -#define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E -#define FE_AG_REG_TGA_RUR_CNT__W 5 -#define FE_AG_REG_TGA_RUR_CNT__M 0x1F -#define FE_AG_REG_TGA_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F -#define FE_AG_REG_TGA_AVE_DAT__W 6 -#define FE_AG_REG_TGA_AVE_DAT__M 0x3F - -#define FE_AG_REG_TGC_RUR_CNT__A 0xC20050 -#define FE_AG_REG_TGC_RUR_CNT__W 5 -#define FE_AG_REG_TGC_RUR_CNT__M 0x1F -#define FE_AG_REG_TGC_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_TGC_SET_LVL__A 0xC20051 -#define FE_AG_REG_TGC_SET_LVL__W 6 -#define FE_AG_REG_TGC_SET_LVL__M 0x3F -#define FE_AG_REG_TGC_SET_LVL_INIT 0x0 - -#define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 -#define FE_AG_REG_TGC_FLA_RGN__W 6 -#define FE_AG_REG_TGC_FLA_RGN__M 0x3F -#define FE_AG_REG_TGC_FLA_RGN_INIT 0x0 - -#define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 -#define FE_AG_REG_TGC_JMP_PSN__W 4 -#define FE_AG_REG_TGC_JMP_PSN__M 0xF -#define FE_AG_REG_TGC_JMP_PSN_INIT 0x0 - -#define FE_AG_REG_TGC_FLA_STP__A 0xC20054 -#define FE_AG_REG_TGC_FLA_STP__W 16 -#define FE_AG_REG_TGC_FLA_STP__M 0xFFFF -#define FE_AG_REG_TGC_FLA_STP_INIT 0x0 - -#define FE_AG_REG_TGC_SLO_STP__A 0xC20055 -#define FE_AG_REG_TGC_SLO_STP__W 16 -#define FE_AG_REG_TGC_SLO_STP__M 0xFFFF -#define FE_AG_REG_TGC_SLO_STP_INIT 0x0 - -#define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 -#define FE_AG_REG_TGC_MAP_DAT__W 10 -#define FE_AG_REG_TGC_MAP_DAT__M 0x3FF - -#define FE_AG_REG_FGA_AUR_CNT__A 0xC20057 -#define FE_AG_REG_FGA_AUR_CNT__W 5 -#define FE_AG_REG_FGA_AUR_CNT__M 0x1F -#define FE_AG_REG_FGA_AUR_CNT_INIT 0x0 - -#define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 -#define FE_AG_REG_FGA_RUR_CNT__W 5 -#define FE_AG_REG_FGA_RUR_CNT__M 0x1F -#define FE_AG_REG_FGA_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_FGA_AVE_DAT__A 0xC20059 -#define FE_AG_REG_FGA_AVE_DAT__W 10 -#define FE_AG_REG_FGA_AVE_DAT__M 0x3FF - -#define FE_AG_REG_FGC_RUR_CNT__A 0xC2005A -#define FE_AG_REG_FGC_RUR_CNT__W 5 -#define FE_AG_REG_FGC_RUR_CNT__M 0x1F -#define FE_AG_REG_FGC_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_FGC_SET_LVL__A 0xC2005B -#define FE_AG_REG_FGC_SET_LVL__W 9 -#define FE_AG_REG_FGC_SET_LVL__M 0x1FF -#define FE_AG_REG_FGC_SET_LVL_INIT 0x0 - -#define FE_AG_REG_FGC_FLA_RGN__A 0xC2005C -#define FE_AG_REG_FGC_FLA_RGN__W 9 -#define FE_AG_REG_FGC_FLA_RGN__M 0x1FF -#define FE_AG_REG_FGC_FLA_RGN_INIT 0x0 - -#define FE_AG_REG_FGC_JMP_PSN__A 0xC2005D -#define FE_AG_REG_FGC_JMP_PSN__W 4 -#define FE_AG_REG_FGC_JMP_PSN__M 0xF -#define FE_AG_REG_FGC_JMP_PSN_INIT 0x0 - -#define FE_AG_REG_FGC_FLA_STP__A 0xC2005E -#define FE_AG_REG_FGC_FLA_STP__W 16 -#define FE_AG_REG_FGC_FLA_STP__M 0xFFFF -#define FE_AG_REG_FGC_FLA_STP_INIT 0x0 - -#define FE_AG_REG_FGC_SLO_STP__A 0xC2005F -#define FE_AG_REG_FGC_SLO_STP__W 16 -#define FE_AG_REG_FGC_SLO_STP__M 0xFFFF -#define FE_AG_REG_FGC_SLO_STP_INIT 0x0 - -#define FE_AG_REG_FGC_MAP_DAT__A 0xC20060 -#define FE_AG_REG_FGC_MAP_DAT__W 10 -#define FE_AG_REG_FGC_MAP_DAT__M 0x3FF - -#define FE_AG_REG_FGM_WRI__A 0xC20061 -#define FE_AG_REG_FGM_WRI__W 10 -#define FE_AG_REG_FGM_WRI__M 0x3FF -#define FE_AG_REG_FGM_WRI_INIT 0x20 - -#define FE_AG_REG_BGC_RUR_CNT__A 0xC20062 -#define FE_AG_REG_BGC_RUR_CNT__W 5 -#define FE_AG_REG_BGC_RUR_CNT__M 0x1F -#define FE_AG_REG_BGC_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_BGC_SET_LVL__A 0xC20063 -#define FE_AG_REG_BGC_SET_LVL__W 9 -#define FE_AG_REG_BGC_SET_LVL__M 0x1FF -#define FE_AG_REG_BGC_SET_LVL_INIT 0x0 - -#define FE_AG_REG_BGC_FLA_RGN__A 0xC20064 -#define FE_AG_REG_BGC_FLA_RGN__W 9 -#define FE_AG_REG_BGC_FLA_RGN__M 0x1FF -#define FE_AG_REG_BGC_FLA_RGN_INIT 0x0 - -#define FE_AG_REG_BGC_JMP_PSN__A 0xC20065 -#define FE_AG_REG_BGC_JMP_PSN__W 4 -#define FE_AG_REG_BGC_JMP_PSN__M 0xF -#define FE_AG_REG_BGC_JMP_PSN_INIT 0x0 - -#define FE_AG_REG_BGC_FLA_STP__A 0xC20066 -#define FE_AG_REG_BGC_FLA_STP__W 16 -#define FE_AG_REG_BGC_FLA_STP__M 0xFFFF -#define FE_AG_REG_BGC_FLA_STP_INIT 0x0 - -#define FE_AG_REG_BGC_SLO_STP__A 0xC20067 -#define FE_AG_REG_BGC_SLO_STP__W 16 -#define FE_AG_REG_BGC_SLO_STP__M 0xFFFF -#define FE_AG_REG_BGC_SLO_STP_INIT 0x0 - -#define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 -#define FE_AG_REG_BGC_FGC_WRI__W 4 -#define FE_AG_REG_BGC_FGC_WRI__M 0xF -#define FE_AG_REG_BGC_FGC_WRI_INIT 0x7 - -#define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 -#define FE_AG_REG_BGC_CGC_WRI__W 2 -#define FE_AG_REG_BGC_CGC_WRI__M 0x3 -#define FE_AG_REG_BGC_CGC_WRI_INIT 0x1 - -#define FE_AG_REG_BGC_FGC_DAT__A 0xC2006A -#define FE_AG_REG_BGC_FGC_DAT__W 4 -#define FE_AG_REG_BGC_FGC_DAT__M 0xF - -#define FE_FS_SID 0x3 - -#define FE_FS_REG_COMM_EXEC__A 0xC30000 -#define FE_FS_REG_COMM_EXEC__W 3 -#define FE_FS_REG_COMM_EXEC__M 0x7 -#define FE_FS_REG_COMM_EXEC_CTL__B 0 -#define FE_FS_REG_COMM_EXEC_CTL__W 3 -#define FE_FS_REG_COMM_EXEC_CTL__M 0x7 -#define FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_FS_REG_COMM_STATE__A 0xC30001 -#define FE_FS_REG_COMM_STATE__W 4 -#define FE_FS_REG_COMM_STATE__M 0xF - -#define FE_FS_REG_COMM_MB__A 0xC30002 -#define FE_FS_REG_COMM_MB__W 3 -#define FE_FS_REG_COMM_MB__M 0x7 -#define FE_FS_REG_COMM_MB_CTR__B 0 -#define FE_FS_REG_COMM_MB_CTR__W 1 -#define FE_FS_REG_COMM_MB_CTR__M 0x1 -#define FE_FS_REG_COMM_MB_CTR_OFF 0x0 -#define FE_FS_REG_COMM_MB_CTR_ON 0x1 -#define FE_FS_REG_COMM_MB_OBS__B 1 -#define FE_FS_REG_COMM_MB_OBS__W 1 -#define FE_FS_REG_COMM_MB_OBS__M 0x2 -#define FE_FS_REG_COMM_MB_OBS_OFF 0x0 -#define FE_FS_REG_COMM_MB_OBS_ON 0x2 -#define FE_FS_REG_COMM_MB_MUX__B 2 -#define FE_FS_REG_COMM_MB_MUX__W 1 -#define FE_FS_REG_COMM_MB_MUX__M 0x4 -#define FE_FS_REG_COMM_MB_MUX_REAL 0x0 -#define FE_FS_REG_COMM_MB_MUX_IMAG 0x4 - -#define FE_FS_REG_COMM_SERVICE0__A 0xC30003 -#define FE_FS_REG_COMM_SERVICE0__W 10 -#define FE_FS_REG_COMM_SERVICE0__M 0x3FF - -#define FE_FS_REG_COMM_SERVICE1__A 0xC30004 -#define FE_FS_REG_COMM_SERVICE1__W 11 -#define FE_FS_REG_COMM_SERVICE1__M 0x7FF - -#define FE_FS_REG_COMM_ACT__A 0xC30005 -#define FE_FS_REG_COMM_ACT__W 2 -#define FE_FS_REG_COMM_ACT__M 0x3 - -#define FE_FS_REG_COMM_CNT__A 0xC30006 -#define FE_FS_REG_COMM_CNT__W 16 -#define FE_FS_REG_COMM_CNT__M 0xFFFF - -#define FE_FS_REG_ADD_INC_LOP__A 0xC30010 -#define FE_FS_REG_ADD_INC_LOP__W 16 -#define FE_FS_REG_ADD_INC_LOP__M 0xFFFF -#define FE_FS_REG_ADD_INC_LOP_INIT 0x0 - -#define FE_FS_REG_ADD_INC_HIP__A 0xC30011 -#define FE_FS_REG_ADD_INC_HIP__W 12 -#define FE_FS_REG_ADD_INC_HIP__M 0xFFF -#define FE_FS_REG_ADD_INC_HIP_INIT 0x0 - -#define FE_FS_REG_ADD_OFF__A 0xC30012 -#define FE_FS_REG_ADD_OFF__W 12 -#define FE_FS_REG_ADD_OFF__M 0xFFF -#define FE_FS_REG_ADD_OFF_INIT 0x0 - -#define FE_FS_REG_ADD_OFF_VAL__A 0xC30013 -#define FE_FS_REG_ADD_OFF_VAL__W 1 -#define FE_FS_REG_ADD_OFF_VAL__M 0x1 -#define FE_FS_REG_ADD_OFF_VAL_INIT 0x0 - -#define FE_FD_SID 0x4 - -#define FE_FD_REG_COMM_EXEC__A 0xC40000 -#define FE_FD_REG_COMM_EXEC__W 3 -#define FE_FD_REG_COMM_EXEC__M 0x7 -#define FE_FD_REG_COMM_EXEC_CTL__B 0 -#define FE_FD_REG_COMM_EXEC_CTL__W 3 -#define FE_FD_REG_COMM_EXEC_CTL__M 0x7 -#define FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_FD_REG_COMM_MB__A 0xC40002 -#define FE_FD_REG_COMM_MB__W 3 -#define FE_FD_REG_COMM_MB__M 0x7 -#define FE_FD_REG_COMM_MB_CTR__B 0 -#define FE_FD_REG_COMM_MB_CTR__W 1 -#define FE_FD_REG_COMM_MB_CTR__M 0x1 -#define FE_FD_REG_COMM_MB_CTR_OFF 0x0 -#define FE_FD_REG_COMM_MB_CTR_ON 0x1 -#define FE_FD_REG_COMM_MB_OBS__B 1 -#define FE_FD_REG_COMM_MB_OBS__W 1 -#define FE_FD_REG_COMM_MB_OBS__M 0x2 -#define FE_FD_REG_COMM_MB_OBS_OFF 0x0 -#define FE_FD_REG_COMM_MB_OBS_ON 0x2 - -#define FE_FD_REG_COMM_SERVICE0__A 0xC40003 -#define FE_FD_REG_COMM_SERVICE0__W 10 -#define FE_FD_REG_COMM_SERVICE0__M 0x3FF -#define FE_FD_REG_COMM_SERVICE1__A 0xC40004 -#define FE_FD_REG_COMM_SERVICE1__W 11 -#define FE_FD_REG_COMM_SERVICE1__M 0x7FF - -#define FE_FD_REG_COMM_INT_STA__A 0xC40007 -#define FE_FD_REG_COMM_INT_STA__W 1 -#define FE_FD_REG_COMM_INT_STA__M 0x1 -#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define FE_FD_REG_COMM_INT_MSK__A 0xC40008 -#define FE_FD_REG_COMM_INT_MSK__W 1 -#define FE_FD_REG_COMM_INT_MSK__M 0x1 -#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - -#define FE_FD_REG_SCL__A 0xC40010 -#define FE_FD_REG_SCL__W 6 -#define FE_FD_REG_SCL__M 0x3F - -#define FE_FD_REG_MAX_LEV__A 0xC40011 -#define FE_FD_REG_MAX_LEV__W 3 -#define FE_FD_REG_MAX_LEV__M 0x7 - -#define FE_FD_REG_NR__A 0xC40012 -#define FE_FD_REG_NR__W 5 -#define FE_FD_REG_NR__M 0x1F - -#define FE_FD_REG_MEAS_SEL__A 0xC40013 -#define FE_FD_REG_MEAS_SEL__W 1 -#define FE_FD_REG_MEAS_SEL__M 0x1 - -#define FE_FD_REG_MEAS_VAL__A 0xC40014 -#define FE_FD_REG_MEAS_VAL__W 1 -#define FE_FD_REG_MEAS_VAL__M 0x1 - -#define FE_FD_REG_MAX__A 0xC40015 -#define FE_FD_REG_MAX__W 16 -#define FE_FD_REG_MAX__M 0xFFFF - -#define FE_FD_REG_POWER__A 0xC40016 -#define FE_FD_REG_POWER__W 10 -#define FE_FD_REG_POWER__M 0x3FF - -#define FE_IF_SID 0x5 - -#define FE_IF_REG_COMM_EXEC__A 0xC50000 -#define FE_IF_REG_COMM_EXEC__W 3 -#define FE_IF_REG_COMM_EXEC__M 0x7 -#define FE_IF_REG_COMM_EXEC_CTL__B 0 -#define FE_IF_REG_COMM_EXEC_CTL__W 3 -#define FE_IF_REG_COMM_EXEC_CTL__M 0x7 -#define FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_IF_REG_COMM_MB__A 0xC50002 -#define FE_IF_REG_COMM_MB__W 3 -#define FE_IF_REG_COMM_MB__M 0x7 -#define FE_IF_REG_COMM_MB_CTR__B 0 -#define FE_IF_REG_COMM_MB_CTR__W 1 -#define FE_IF_REG_COMM_MB_CTR__M 0x1 -#define FE_IF_REG_COMM_MB_CTR_OFF 0x0 -#define FE_IF_REG_COMM_MB_CTR_ON 0x1 -#define FE_IF_REG_COMM_MB_OBS__B 1 -#define FE_IF_REG_COMM_MB_OBS__W 1 -#define FE_IF_REG_COMM_MB_OBS__M 0x2 -#define FE_IF_REG_COMM_MB_OBS_OFF 0x0 -#define FE_IF_REG_COMM_MB_OBS_ON 0x2 - -#define FE_IF_REG_INCR0__A 0xC50010 -#define FE_IF_REG_INCR0__W 16 -#define FE_IF_REG_INCR0__M 0xFFFF -#define FE_IF_REG_INCR0_INIT 0x0 - -#define FE_IF_REG_INCR1__A 0xC50011 -#define FE_IF_REG_INCR1__W 8 -#define FE_IF_REG_INCR1__M 0xFF -#define FE_IF_REG_INCR1_INIT 0x28 - -#define FE_CF_SID 0x6 - -#define FE_CF_REG_COMM_EXEC__A 0xC60000 -#define FE_CF_REG_COMM_EXEC__W 3 -#define FE_CF_REG_COMM_EXEC__M 0x7 -#define FE_CF_REG_COMM_EXEC_CTL__B 0 -#define FE_CF_REG_COMM_EXEC_CTL__W 3 -#define FE_CF_REG_COMM_EXEC_CTL__M 0x7 -#define FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_CF_REG_COMM_MB__A 0xC60002 -#define FE_CF_REG_COMM_MB__W 3 -#define FE_CF_REG_COMM_MB__M 0x7 -#define FE_CF_REG_COMM_MB_CTR__B 0 -#define FE_CF_REG_COMM_MB_CTR__W 1 -#define FE_CF_REG_COMM_MB_CTR__M 0x1 -#define FE_CF_REG_COMM_MB_CTR_OFF 0x0 -#define FE_CF_REG_COMM_MB_CTR_ON 0x1 -#define FE_CF_REG_COMM_MB_OBS__B 1 -#define FE_CF_REG_COMM_MB_OBS__W 1 -#define FE_CF_REG_COMM_MB_OBS__M 0x2 -#define FE_CF_REG_COMM_MB_OBS_OFF 0x0 -#define FE_CF_REG_COMM_MB_OBS_ON 0x2 - -#define FE_CF_REG_COMM_SERVICE0__A 0xC60003 -#define FE_CF_REG_COMM_SERVICE0__W 10 -#define FE_CF_REG_COMM_SERVICE0__M 0x3FF -#define FE_CF_REG_COMM_SERVICE1__A 0xC60004 -#define FE_CF_REG_COMM_SERVICE1__W 11 -#define FE_CF_REG_COMM_SERVICE1__M 0x7FF - -#define FE_CF_REG_COMM_INT_STA__A 0xC60007 -#define FE_CF_REG_COMM_INT_STA__W 2 -#define FE_CF_REG_COMM_INT_STA__M 0x3 -#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define FE_CF_REG_COMM_INT_MSK__A 0xC60008 -#define FE_CF_REG_COMM_INT_MSK__W 2 -#define FE_CF_REG_COMM_INT_MSK__M 0x3 -#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - -#define FE_CF_REG_SCL__A 0xC60010 -#define FE_CF_REG_SCL__W 9 -#define FE_CF_REG_SCL__M 0x1FF - -#define FE_CF_REG_MAX_LEV__A 0xC60011 -#define FE_CF_REG_MAX_LEV__W 3 -#define FE_CF_REG_MAX_LEV__M 0x7 - -#define FE_CF_REG_NR__A 0xC60012 -#define FE_CF_REG_NR__W 5 -#define FE_CF_REG_NR__M 0x1F - -#define FE_CF_REG_IMP_VAL__A 0xC60013 -#define FE_CF_REG_IMP_VAL__W 1 -#define FE_CF_REG_IMP_VAL__M 0x1 - -#define FE_CF_REG_MEAS_VAL__A 0xC60014 -#define FE_CF_REG_MEAS_VAL__W 1 -#define FE_CF_REG_MEAS_VAL__M 0x1 - -#define FE_CF_REG_MAX__A 0xC60015 -#define FE_CF_REG_MAX__W 16 -#define FE_CF_REG_MAX__M 0xFFFF - -#define FE_CF_REG_POWER__A 0xC60016 -#define FE_CF_REG_POWER__W 10 -#define FE_CF_REG_POWER__M 0x3FF - -#define FE_CU_SID 0x7 - -#define FE_CU_REG_COMM_EXEC__A 0xC70000 -#define FE_CU_REG_COMM_EXEC__W 3 -#define FE_CU_REG_COMM_EXEC__M 0x7 -#define FE_CU_REG_COMM_EXEC_CTL__B 0 -#define FE_CU_REG_COMM_EXEC_CTL__W 3 -#define FE_CU_REG_COMM_EXEC_CTL__M 0x7 -#define FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_CU_REG_COMM_STATE__A 0xC70001 -#define FE_CU_REG_COMM_STATE__W 4 -#define FE_CU_REG_COMM_STATE__M 0xF - -#define FE_CU_REG_COMM_MB__A 0xC70002 -#define FE_CU_REG_COMM_MB__W 3 -#define FE_CU_REG_COMM_MB__M 0x7 -#define FE_CU_REG_COMM_MB_CTR__B 0 -#define FE_CU_REG_COMM_MB_CTR__W 1 -#define FE_CU_REG_COMM_MB_CTR__M 0x1 -#define FE_CU_REG_COMM_MB_CTR_OFF 0x0 -#define FE_CU_REG_COMM_MB_CTR_ON 0x1 -#define FE_CU_REG_COMM_MB_OBS__B 1 -#define FE_CU_REG_COMM_MB_OBS__W 1 -#define FE_CU_REG_COMM_MB_OBS__M 0x2 -#define FE_CU_REG_COMM_MB_OBS_OFF 0x0 -#define FE_CU_REG_COMM_MB_OBS_ON 0x2 -#define FE_CU_REG_COMM_MB_MUX__B 2 -#define FE_CU_REG_COMM_MB_MUX__W 1 -#define FE_CU_REG_COMM_MB_MUX__M 0x4 -#define FE_CU_REG_COMM_MB_MUX_REAL 0x0 -#define FE_CU_REG_COMM_MB_MUX_IMAG 0x4 - -#define FE_CU_REG_COMM_SERVICE0__A 0xC70003 -#define FE_CU_REG_COMM_SERVICE0__W 10 -#define FE_CU_REG_COMM_SERVICE0__M 0x3FF - -#define FE_CU_REG_COMM_SERVICE1__A 0xC70004 -#define FE_CU_REG_COMM_SERVICE1__W 11 -#define FE_CU_REG_COMM_SERVICE1__M 0x7FF - -#define FE_CU_REG_COMM_ACT__A 0xC70005 -#define FE_CU_REG_COMM_ACT__W 2 -#define FE_CU_REG_COMM_ACT__M 0x3 - -#define FE_CU_REG_COMM_CNT__A 0xC70006 -#define FE_CU_REG_COMM_CNT__W 16 -#define FE_CU_REG_COMM_CNT__M 0xFFFF - -#define FE_CU_REG_COMM_INT_STA__A 0xC70007 -#define FE_CU_REG_COMM_INT_STA__W 2 -#define FE_CU_REG_COMM_INT_STA__M 0x3 -#define FE_CU_REG_COMM_INT_STA_FE_START__B 0 -#define FE_CU_REG_COMM_INT_STA_FE_START__W 1 -#define FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 -#define FE_CU_REG_COMM_INT_STA_FT_START__B 1 -#define FE_CU_REG_COMM_INT_STA_FT_START__W 1 -#define FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 - -#define FE_CU_REG_COMM_INT_MSK__A 0xC70008 -#define FE_CU_REG_COMM_INT_MSK__W 2 -#define FE_CU_REG_COMM_INT_MSK__M 0x3 -#define FE_CU_REG_COMM_INT_MSK_FE_START__B 0 -#define FE_CU_REG_COMM_INT_MSK_FE_START__W 1 -#define FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 -#define FE_CU_REG_COMM_INT_MSK_FT_START__B 1 -#define FE_CU_REG_COMM_INT_MSK_FT_START__W 1 -#define FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 - -#define FE_CU_REG_MODE__A 0xC70010 -#define FE_CU_REG_MODE__W 3 -#define FE_CU_REG_MODE__M 0x7 -#define FE_CU_REG_MODE_INIT 0x0 - -#define FE_CU_REG_MODE_FFT__B 0 -#define FE_CU_REG_MODE_FFT__W 1 -#define FE_CU_REG_MODE_FFT__M 0x1 -#define FE_CU_REG_MODE_FFT_M8K 0x0 -#define FE_CU_REG_MODE_FFT_M2K 0x1 - -#define FE_CU_REG_MODE_COR__B 1 -#define FE_CU_REG_MODE_COR__W 1 -#define FE_CU_REG_MODE_COR__M 0x2 -#define FE_CU_REG_MODE_COR_OFF 0x0 -#define FE_CU_REG_MODE_COR_ON 0x2 - -#define FE_CU_REG_MODE_IFD__B 2 -#define FE_CU_REG_MODE_IFD__W 1 -#define FE_CU_REG_MODE_IFD__M 0x4 -#define FE_CU_REG_MODE_IFD_ENABLE 0x0 -#define FE_CU_REG_MODE_IFD_DISABLE 0x4 - -#define FE_CU_REG_FRM_CNT_RST__A 0xC70011 -#define FE_CU_REG_FRM_CNT_RST__W 15 -#define FE_CU_REG_FRM_CNT_RST__M 0x7FFF -#define FE_CU_REG_FRM_CNT_RST_INIT 0x0 - -#define FE_CU_REG_FRM_CNT_STR__A 0xC70012 -#define FE_CU_REG_FRM_CNT_STR__W 15 -#define FE_CU_REG_FRM_CNT_STR__M 0x7FFF -#define FE_CU_REG_FRM_CNT_STR_INIT 0x0 - -#define FE_CU_REG_FRM_SMP_CNT__A 0xC70013 -#define FE_CU_REG_FRM_SMP_CNT__W 15 -#define FE_CU_REG_FRM_SMP_CNT__M 0x7FFF - -#define FE_CU_REG_FRM_SMB_CNT__A 0xC70014 -#define FE_CU_REG_FRM_SMB_CNT__W 16 -#define FE_CU_REG_FRM_SMB_CNT__M 0xFFFF - -#define FE_CU_REG_CMP_MAX_DAT__A 0xC70015 -#define FE_CU_REG_CMP_MAX_DAT__W 12 -#define FE_CU_REG_CMP_MAX_DAT__M 0xFFF - -#define FE_CU_REG_CMP_MAX_ADR__A 0xC70016 -#define FE_CU_REG_CMP_MAX_ADR__W 10 -#define FE_CU_REG_CMP_MAX_ADR__M 0x3FF - -#define FE_CU_REG_CTR_NF1_WLO__A 0xC70017 -#define FE_CU_REG_CTR_NF1_WLO__W 15 -#define FE_CU_REG_CTR_NF1_WLO__M 0x7FFF -#define FE_CU_REG_CTR_NF1_WLO_INIT 0x0 - -#define FE_CU_REG_CTR_NF1_WHI__A 0xC70018 -#define FE_CU_REG_CTR_NF1_WHI__W 15 -#define FE_CU_REG_CTR_NF1_WHI__M 0x7FFF -#define FE_CU_REG_CTR_NF1_WHI_INIT 0x0 - -#define FE_CU_REG_CTR_NF2_WLO__A 0xC70019 -#define FE_CU_REG_CTR_NF2_WLO__W 15 -#define FE_CU_REG_CTR_NF2_WLO__M 0x7FFF -#define FE_CU_REG_CTR_NF2_WLO_INIT 0x0 - -#define FE_CU_REG_CTR_NF2_WHI__A 0xC7001A -#define FE_CU_REG_CTR_NF2_WHI__W 15 -#define FE_CU_REG_CTR_NF2_WHI__M 0x7FFF -#define FE_CU_REG_CTR_NF2_WHI_INIT 0x0 - -#define FE_CU_REG_DIV_NF1_REA__A 0xC7001B -#define FE_CU_REG_DIV_NF1_REA__W 12 -#define FE_CU_REG_DIV_NF1_REA__M 0xFFF - -#define FE_CU_REG_DIV_NF1_IMA__A 0xC7001C -#define FE_CU_REG_DIV_NF1_IMA__W 12 -#define FE_CU_REG_DIV_NF1_IMA__M 0xFFF - -#define FE_CU_REG_DIV_NF2_REA__A 0xC7001D -#define FE_CU_REG_DIV_NF2_REA__W 12 -#define FE_CU_REG_DIV_NF2_REA__M 0xFFF - -#define FE_CU_REG_DIV_NF2_IMA__A 0xC7001E -#define FE_CU_REG_DIV_NF2_IMA__W 12 -#define FE_CU_REG_DIV_NF2_IMA__M 0xFFF - -#define FE_CU_BUF_RAM__A 0xC80000 - -#define FE_CU_CMP_RAM__A 0xC90000 - -#define FT_SID 0x8 - -#define FT_COMM_EXEC__A 0x1000000 -#define FT_COMM_EXEC__W 3 -#define FT_COMM_EXEC__M 0x7 -#define FT_COMM_EXEC_CTL__B 0 -#define FT_COMM_EXEC_CTL__W 3 -#define FT_COMM_EXEC_CTL__M 0x7 -#define FT_COMM_EXEC_CTL_STOP 0x0 -#define FT_COMM_EXEC_CTL_ACTIVE 0x1 -#define FT_COMM_EXEC_CTL_HOLD 0x2 -#define FT_COMM_EXEC_CTL_STEP 0x3 -#define FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define FT_COMM_STATE__A 0x1000001 -#define FT_COMM_STATE__W 16 -#define FT_COMM_STATE__M 0xFFFF -#define FT_COMM_MB__A 0x1000002 -#define FT_COMM_MB__W 16 -#define FT_COMM_MB__M 0xFFFF -#define FT_COMM_SERVICE0__A 0x1000003 -#define FT_COMM_SERVICE0__W 16 -#define FT_COMM_SERVICE0__M 0xFFFF -#define FT_COMM_SERVICE1__A 0x1000004 -#define FT_COMM_SERVICE1__W 16 -#define FT_COMM_SERVICE1__M 0xFFFF -#define FT_COMM_INT_STA__A 0x1000007 -#define FT_COMM_INT_STA__W 16 -#define FT_COMM_INT_STA__M 0xFFFF -#define FT_COMM_INT_MSK__A 0x1000008 -#define FT_COMM_INT_MSK__W 16 -#define FT_COMM_INT_MSK__M 0xFFFF - -#define FT_REG_COMM_EXEC__A 0x1010000 -#define FT_REG_COMM_EXEC__W 3 -#define FT_REG_COMM_EXEC__M 0x7 -#define FT_REG_COMM_EXEC_CTL__B 0 -#define FT_REG_COMM_EXEC_CTL__W 3 -#define FT_REG_COMM_EXEC_CTL__M 0x7 -#define FT_REG_COMM_EXEC_CTL_STOP 0x0 -#define FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FT_REG_COMM_MB__A 0x1010002 -#define FT_REG_COMM_MB__W 3 -#define FT_REG_COMM_MB__M 0x7 -#define FT_REG_COMM_MB_CTR__B 0 -#define FT_REG_COMM_MB_CTR__W 1 -#define FT_REG_COMM_MB_CTR__M 0x1 -#define FT_REG_COMM_MB_CTR_OFF 0x0 -#define FT_REG_COMM_MB_CTR_ON 0x1 -#define FT_REG_COMM_MB_OBS__B 1 -#define FT_REG_COMM_MB_OBS__W 1 -#define FT_REG_COMM_MB_OBS__M 0x2 -#define FT_REG_COMM_MB_OBS_OFF 0x0 -#define FT_REG_COMM_MB_OBS_ON 0x2 - -#define FT_REG_COMM_SERVICE0__A 0x1010003 -#define FT_REG_COMM_SERVICE0__W 10 -#define FT_REG_COMM_SERVICE0__M 0x3FF -#define FT_REG_COMM_SERVICE0_FT__B 8 -#define FT_REG_COMM_SERVICE0_FT__W 1 -#define FT_REG_COMM_SERVICE0_FT__M 0x100 - -#define FT_REG_COMM_SERVICE1__A 0x1010004 -#define FT_REG_COMM_SERVICE1__W 11 -#define FT_REG_COMM_SERVICE1__M 0x7FF - -#define FT_REG_COMM_INT_STA__A 0x1010007 -#define FT_REG_COMM_INT_STA__W 2 -#define FT_REG_COMM_INT_STA__M 0x3 -#define FT_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define FT_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define FT_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define FT_REG_COMM_INT_MSK__A 0x1010008 -#define FT_REG_COMM_INT_MSK__W 2 -#define FT_REG_COMM_INT_MSK__M 0x3 -#define FT_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define FT_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define FT_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - -#define FT_REG_MODE_2K__A 0x1010010 -#define FT_REG_MODE_2K__W 1 -#define FT_REG_MODE_2K__M 0x1 -#define FT_REG_MODE_2K_MODE_8K 0x0 -#define FT_REG_MODE_2K_MODE_2K 0x1 -#define FT_REG_MODE_2K_INIT 0x0 - -#define FT_REG_BUS_MOD__A 0x1010011 -#define FT_REG_BUS_MOD__W 1 -#define FT_REG_BUS_MOD__M 0x1 -#define FT_REG_BUS_MOD_INPUT 0x0 -#define FT_REG_BUS_MOD_PILOT 0x1 -#define FT_REG_BUS_MOD_INIT 0x0 - -#define FT_REG_BUS_REAL__A 0x1010012 -#define FT_REG_BUS_REAL__W 10 -#define FT_REG_BUS_REAL__M 0x3FF -#define FT_REG_BUS_REAL_INIT 0x0 - -#define FT_REG_BUS_IMAG__A 0x1010013 -#define FT_REG_BUS_IMAG__W 10 -#define FT_REG_BUS_IMAG__M 0x3FF -#define FT_REG_BUS_IMAG_INIT 0x0 - -#define FT_REG_BUS_VAL__A 0x1010014 -#define FT_REG_BUS_VAL__W 1 -#define FT_REG_BUS_VAL__M 0x1 -#define FT_REG_BUS_VAL_INIT 0x0 - -#define FT_REG_PEAK__A 0x1010015 -#define FT_REG_PEAK__W 11 -#define FT_REG_PEAK__M 0x7FF -#define FT_REG_PEAK_INIT 0x0 - -#define FT_REG_NORM_OFF__A 0x1010016 -#define FT_REG_NORM_OFF__W 4 -#define FT_REG_NORM_OFF__M 0xF -#define FT_REG_NORM_OFF_INIT 0x2 - -#define FT_ST1_RAM__A 0x1020000 - -#define FT_ST2_RAM__A 0x1030000 - -#define FT_ST3_RAM__A 0x1040000 - -#define FT_ST5_RAM__A 0x1050000 - -#define FT_ST6_RAM__A 0x1060000 - -#define FT_ST8_RAM__A 0x1070000 - -#define FT_ST9_RAM__A 0x1080000 - -#define CP_SID 0x9 - -#define CP_COMM_EXEC__A 0x1400000 -#define CP_COMM_EXEC__W 3 -#define CP_COMM_EXEC__M 0x7 -#define CP_COMM_EXEC_CTL__B 0 -#define CP_COMM_EXEC_CTL__W 3 -#define CP_COMM_EXEC_CTL__M 0x7 -#define CP_COMM_EXEC_CTL_STOP 0x0 -#define CP_COMM_EXEC_CTL_ACTIVE 0x1 -#define CP_COMM_EXEC_CTL_HOLD 0x2 -#define CP_COMM_EXEC_CTL_STEP 0x3 -#define CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define CP_COMM_STATE__A 0x1400001 -#define CP_COMM_STATE__W 16 -#define CP_COMM_STATE__M 0xFFFF -#define CP_COMM_MB__A 0x1400002 -#define CP_COMM_MB__W 16 -#define CP_COMM_MB__M 0xFFFF -#define CP_COMM_SERVICE0__A 0x1400003 -#define CP_COMM_SERVICE0__W 16 -#define CP_COMM_SERVICE0__M 0xFFFF -#define CP_COMM_SERVICE1__A 0x1400004 -#define CP_COMM_SERVICE1__W 16 -#define CP_COMM_SERVICE1__M 0xFFFF -#define CP_COMM_INT_STA__A 0x1400007 -#define CP_COMM_INT_STA__W 16 -#define CP_COMM_INT_STA__M 0xFFFF -#define CP_COMM_INT_MSK__A 0x1400008 -#define CP_COMM_INT_MSK__W 16 -#define CP_COMM_INT_MSK__M 0xFFFF - -#define CP_REG_COMM_EXEC__A 0x1410000 -#define CP_REG_COMM_EXEC__W 3 -#define CP_REG_COMM_EXEC__M 0x7 -#define CP_REG_COMM_EXEC_CTL__B 0 -#define CP_REG_COMM_EXEC_CTL__W 3 -#define CP_REG_COMM_EXEC_CTL__M 0x7 -#define CP_REG_COMM_EXEC_CTL_STOP 0x0 -#define CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define CP_REG_COMM_EXEC_CTL_HOLD 0x2 -#define CP_REG_COMM_EXEC_CTL_STEP 0x3 - -#define CP_REG_COMM_MB__A 0x1410002 -#define CP_REG_COMM_MB__W 3 -#define CP_REG_COMM_MB__M 0x7 -#define CP_REG_COMM_MB_CTR__B 0 -#define CP_REG_COMM_MB_CTR__W 1 -#define CP_REG_COMM_MB_CTR__M 0x1 -#define CP_REG_COMM_MB_CTR_OFF 0x0 -#define CP_REG_COMM_MB_CTR_ON 0x1 -#define CP_REG_COMM_MB_OBS__B 1 -#define CP_REG_COMM_MB_OBS__W 1 -#define CP_REG_COMM_MB_OBS__M 0x2 -#define CP_REG_COMM_MB_OBS_OFF 0x0 -#define CP_REG_COMM_MB_OBS_ON 0x2 - -#define CP_REG_COMM_SERVICE0__A 0x1410003 -#define CP_REG_COMM_SERVICE0__W 10 -#define CP_REG_COMM_SERVICE0__M 0x3FF -#define CP_REG_COMM_SERVICE0_CP__B 9 -#define CP_REG_COMM_SERVICE0_CP__W 1 -#define CP_REG_COMM_SERVICE0_CP__M 0x200 - -#define CP_REG_COMM_SERVICE1__A 0x1410004 -#define CP_REG_COMM_SERVICE1__W 11 -#define CP_REG_COMM_SERVICE1__M 0x7FF - -#define CP_REG_COMM_INT_STA__A 0x1410007 -#define CP_REG_COMM_INT_STA__W 2 -#define CP_REG_COMM_INT_STA__M 0x3 -#define CP_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define CP_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define CP_REG_COMM_INT_MSK__A 0x1410008 -#define CP_REG_COMM_INT_MSK__W 2 -#define CP_REG_COMM_INT_MSK__M 0x3 -#define CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - -#define CP_REG_MODE_2K__A 0x1410010 -#define CP_REG_MODE_2K__W 1 -#define CP_REG_MODE_2K__M 0x1 -#define CP_REG_MODE_2K_INIT 0x0 - -#define CP_REG_INTERVAL__A 0x1410011 -#define CP_REG_INTERVAL__W 4 -#define CP_REG_INTERVAL__M 0xF -#define CP_REG_INTERVAL_INIT 0x5 - -#define CP_REG_SKIP_START0__A 0x1410012 -#define CP_REG_SKIP_START0__W 13 -#define CP_REG_SKIP_START0__M 0x1FFF -#define CP_REG_SKIP_START0_INIT 0x0 - -#define CP_REG_SKIP_STOP0__A 0x1410013 -#define CP_REG_SKIP_STOP0__W 13 -#define CP_REG_SKIP_STOP0__M 0x1FFF -#define CP_REG_SKIP_STOP0_INIT 0x0 - -#define CP_REG_SKIP_START1__A 0x1410014 -#define CP_REG_SKIP_START1__W 13 -#define CP_REG_SKIP_START1__M 0x1FFF -#define CP_REG_SKIP_START1_INIT 0x0 - -#define CP_REG_SKIP_STOP1__A 0x1410015 -#define CP_REG_SKIP_STOP1__W 13 -#define CP_REG_SKIP_STOP1__M 0x1FFF -#define CP_REG_SKIP_STOP1_INIT 0x0 - -#define CP_REG_SKIP_START2__A 0x1410016 -#define CP_REG_SKIP_START2__W 13 -#define CP_REG_SKIP_START2__M 0x1FFF -#define CP_REG_SKIP_START2_INIT 0x0 - -#define CP_REG_SKIP_STOP2__A 0x1410017 -#define CP_REG_SKIP_STOP2__W 13 -#define CP_REG_SKIP_STOP2__M 0x1FFF -#define CP_REG_SKIP_STOP2_INIT 0x0 - -#define CP_REG_SKIP_ENA__A 0x1410018 -#define CP_REG_SKIP_ENA__W 3 -#define CP_REG_SKIP_ENA__M 0x7 - -#define CP_REG_SKIP_ENA_CPL__B 0 -#define CP_REG_SKIP_ENA_CPL__W 1 -#define CP_REG_SKIP_ENA_CPL__M 0x1 - -#define CP_REG_SKIP_ENA_SPD__B 1 -#define CP_REG_SKIP_ENA_SPD__W 1 -#define CP_REG_SKIP_ENA_SPD__M 0x2 - -#define CP_REG_SKIP_ENA_CPD__B 2 -#define CP_REG_SKIP_ENA_CPD__W 1 -#define CP_REG_SKIP_ENA_CPD__M 0x4 -#define CP_REG_SKIP_ENA_INIT 0x0 - -#define CP_REG_BR_MODE_MIX__A 0x1410020 -#define CP_REG_BR_MODE_MIX__W 1 -#define CP_REG_BR_MODE_MIX__M 0x1 -#define CP_REG_BR_MODE_MIX_INIT 0x0 - -#define CP_REG_BR_SMB_NR__A 0x1410021 -#define CP_REG_BR_SMB_NR__W 3 -#define CP_REG_BR_SMB_NR__M 0x7 - -#define CP_REG_BR_SMB_NR_SMB__B 0 -#define CP_REG_BR_SMB_NR_SMB__W 2 -#define CP_REG_BR_SMB_NR_SMB__M 0x3 - -#define CP_REG_BR_SMB_NR_VAL__B 2 -#define CP_REG_BR_SMB_NR_VAL__W 1 -#define CP_REG_BR_SMB_NR_VAL__M 0x4 -#define CP_REG_BR_SMB_NR_INIT 0x0 - -#define CP_REG_BR_CP_SMB_NR__A 0x1410022 -#define CP_REG_BR_CP_SMB_NR__W 2 -#define CP_REG_BR_CP_SMB_NR__M 0x3 -#define CP_REG_BR_CP_SMB_NR_INIT 0x0 - -#define CP_REG_BR_SPL_OFFSET__A 0x1410023 -#define CP_REG_BR_SPL_OFFSET__W 3 -#define CP_REG_BR_SPL_OFFSET__M 0x7 -#define CP_REG_BR_SPL_OFFSET_INIT 0x0 - -#define CP_REG_BR_STR_DEL__A 0x1410024 -#define CP_REG_BR_STR_DEL__W 10 -#define CP_REG_BR_STR_DEL__M 0x3FF -#define CP_REG_BR_STR_DEL_INIT 0xA - -#define CP_REG_RT_ANG_INC0__A 0x1410030 -#define CP_REG_RT_ANG_INC0__W 16 -#define CP_REG_RT_ANG_INC0__M 0xFFFF -#define CP_REG_RT_ANG_INC0_INIT 0x0 - -#define CP_REG_RT_ANG_INC1__A 0x1410031 -#define CP_REG_RT_ANG_INC1__W 8 -#define CP_REG_RT_ANG_INC1__M 0xFF -#define CP_REG_RT_ANG_INC1_INIT 0x0 - -#define CP_REG_RT_DETECT_ENA__A 0x1410032 -#define CP_REG_RT_DETECT_ENA__W 2 -#define CP_REG_RT_DETECT_ENA__M 0x3 - -#define CP_REG_RT_DETECT_ENA_SCATTERED__B 0 -#define CP_REG_RT_DETECT_ENA_SCATTERED__W 1 -#define CP_REG_RT_DETECT_ENA_SCATTERED__M 0x1 - -#define CP_REG_RT_DETECT_ENA_CONTINUOUS__B 1 -#define CP_REG_RT_DETECT_ENA_CONTINUOUS__W 1 -#define CP_REG_RT_DETECT_ENA_CONTINUOUS__M 0x2 -#define CP_REG_RT_DETECT_ENA_INIT 0x0 - -#define CP_REG_RT_DETECT_TRH__A 0x1410033 -#define CP_REG_RT_DETECT_TRH__W 2 -#define CP_REG_RT_DETECT_TRH__M 0x3 -#define CP_REG_RT_DETECT_TRH_INIT 0x3 - -#define CP_REG_RT_SPD_RELIABLE__A 0x1410034 -#define CP_REG_RT_SPD_RELIABLE__W 3 -#define CP_REG_RT_SPD_RELIABLE__M 0x7 -#define CP_REG_RT_SPD_RELIABLE_INIT 0x0 - -#define CP_REG_RT_SPD_DIRECTION__A 0x1410035 -#define CP_REG_RT_SPD_DIRECTION__W 1 -#define CP_REG_RT_SPD_DIRECTION__M 0x1 -#define CP_REG_RT_SPD_DIRECTION_INIT 0x0 - -#define CP_REG_RT_SPD_MOD__A 0x1410036 -#define CP_REG_RT_SPD_MOD__W 2 -#define CP_REG_RT_SPD_MOD__M 0x3 -#define CP_REG_RT_SPD_MOD_INIT 0x0 - -#define CP_REG_RT_SPD_SMB__A 0x1410037 -#define CP_REG_RT_SPD_SMB__W 2 -#define CP_REG_RT_SPD_SMB__M 0x3 -#define CP_REG_RT_SPD_SMB_INIT 0x0 - -#define CP_REG_RT_CPD_MODE__A 0x1410038 -#define CP_REG_RT_CPD_MODE__W 3 -#define CP_REG_RT_CPD_MODE__M 0x7 - -#define CP_REG_RT_CPD_MODE_MOD3__B 0 -#define CP_REG_RT_CPD_MODE_MOD3__W 2 -#define CP_REG_RT_CPD_MODE_MOD3__M 0x3 - -#define CP_REG_RT_CPD_MODE_ADD__B 2 -#define CP_REG_RT_CPD_MODE_ADD__W 1 -#define CP_REG_RT_CPD_MODE_ADD__M 0x4 -#define CP_REG_RT_CPD_MODE_INIT 0x0 - -#define CP_REG_RT_CPD_RELIABLE__A 0x1410039 -#define CP_REG_RT_CPD_RELIABLE__W 3 -#define CP_REG_RT_CPD_RELIABLE__M 0x7 -#define CP_REG_RT_CPD_RELIABLE_INIT 0x0 - -#define CP_REG_RT_CPD_BIN__A 0x141003A -#define CP_REG_RT_CPD_BIN__W 5 -#define CP_REG_RT_CPD_BIN__M 0x1F -#define CP_REG_RT_CPD_BIN_INIT 0x0 - -#define CP_REG_RT_CPD_MAX__A 0x141003B -#define CP_REG_RT_CPD_MAX__W 4 -#define CP_REG_RT_CPD_MAX__M 0xF -#define CP_REG_RT_CPD_MAX_INIT 0x0 - -#define CP_REG_RT_SUPR_VAL__A 0x141003C -#define CP_REG_RT_SUPR_VAL__W 2 -#define CP_REG_RT_SUPR_VAL__M 0x3 - -#define CP_REG_RT_SUPR_VAL_CE__B 0 -#define CP_REG_RT_SUPR_VAL_CE__W 1 -#define CP_REG_RT_SUPR_VAL_CE__M 0x1 - -#define CP_REG_RT_SUPR_VAL_DL__B 1 -#define CP_REG_RT_SUPR_VAL_DL__W 1 -#define CP_REG_RT_SUPR_VAL_DL__M 0x2 -#define CP_REG_RT_SUPR_VAL_INIT 0x0 - -#define CP_REG_RT_EXP_AVE__A 0x141003D -#define CP_REG_RT_EXP_AVE__W 5 -#define CP_REG_RT_EXP_AVE__M 0x1F -#define CP_REG_RT_EXP_AVE_INIT 0x0 - -#define CP_REG_RT_EXP_MARG__A 0x141003E -#define CP_REG_RT_EXP_MARG__W 5 -#define CP_REG_RT_EXP_MARG__M 0x1F -#define CP_REG_RT_EXP_MARG_INIT 0x0 - -#define CP_REG_AC_NEXP_OFFS__A 0x1410040 -#define CP_REG_AC_NEXP_OFFS__W 8 -#define CP_REG_AC_NEXP_OFFS__M 0xFF -#define CP_REG_AC_NEXP_OFFS_INIT 0x0 - -#define CP_REG_AC_AVER_POW__A 0x1410041 -#define CP_REG_AC_AVER_POW__W 8 -#define CP_REG_AC_AVER_POW__M 0xFF -#define CP_REG_AC_AVER_POW_INIT 0x5F - -#define CP_REG_AC_MAX_POW__A 0x1410042 -#define CP_REG_AC_MAX_POW__W 8 -#define CP_REG_AC_MAX_POW__M 0xFF -#define CP_REG_AC_MAX_POW_INIT 0x7A - -#define CP_REG_AC_WEIGHT_MAN__A 0x1410043 -#define CP_REG_AC_WEIGHT_MAN__W 6 -#define CP_REG_AC_WEIGHT_MAN__M 0x3F -#define CP_REG_AC_WEIGHT_MAN_INIT 0x31 - -#define CP_REG_AC_WEIGHT_EXP__A 0x1410044 -#define CP_REG_AC_WEIGHT_EXP__W 5 -#define CP_REG_AC_WEIGHT_EXP__M 0x1F -#define CP_REG_AC_WEIGHT_EXP_INIT 0x10 - -#define CP_REG_AC_GAIN_MAN__A 0x1410045 -#define CP_REG_AC_GAIN_MAN__W 16 -#define CP_REG_AC_GAIN_MAN__M 0xFFFF -#define CP_REG_AC_GAIN_MAN_INIT 0x0 - -#define CP_REG_AC_GAIN_EXP__A 0x1410046 -#define CP_REG_AC_GAIN_EXP__W 5 -#define CP_REG_AC_GAIN_EXP__M 0x1F -#define CP_REG_AC_GAIN_EXP_INIT 0x0 - -#define CP_REG_AC_AMP_MODE__A 0x1410047 -#define CP_REG_AC_AMP_MODE__W 2 -#define CP_REG_AC_AMP_MODE__M 0x3 -#define CP_REG_AC_AMP_MODE_NEW 0x0 -#define CP_REG_AC_AMP_MODE_OLD 0x1 -#define CP_REG_AC_AMP_MODE_FIXED 0x2 -#define CP_REG_AC_AMP_MODE_INIT 0x2 - -#define CP_REG_AC_AMP_FIX__A 0x1410048 -#define CP_REG_AC_AMP_FIX__W 14 -#define CP_REG_AC_AMP_FIX__M 0x3FFF -#define CP_REG_AC_AMP_FIX_INIT 0x1FF - -#define CP_REG_AC_AMP_READ__A 0x1410049 -#define CP_REG_AC_AMP_READ__W 14 -#define CP_REG_AC_AMP_READ__M 0x3FFF -#define CP_REG_AC_AMP_READ_INIT 0x0 - -#define CP_REG_AC_ANG_MODE__A 0x141004A -#define CP_REG_AC_ANG_MODE__W 2 -#define CP_REG_AC_ANG_MODE__M 0x3 -#define CP_REG_AC_ANG_MODE_NEW 0x0 -#define CP_REG_AC_ANG_MODE_OLD 0x1 -#define CP_REG_AC_ANG_MODE_NO_INT 0x2 -#define CP_REG_AC_ANG_MODE_OFFSET 0x3 -#define CP_REG_AC_ANG_MODE_INIT 0x3 - -#define CP_REG_AC_ANG_OFFS__A 0x141004B -#define CP_REG_AC_ANG_OFFS__W 14 -#define CP_REG_AC_ANG_OFFS__M 0x3FFF -#define CP_REG_AC_ANG_OFFS_INIT 0x0 - -#define CP_REG_AC_ANG_READ__A 0x141004C -#define CP_REG_AC_ANG_READ__W 16 -#define CP_REG_AC_ANG_READ__M 0xFFFF -#define CP_REG_AC_ANG_READ_INIT 0x0 - -#define CP_REG_DL_MB_WR_ADDR__A 0x1410050 -#define CP_REG_DL_MB_WR_ADDR__W 15 -#define CP_REG_DL_MB_WR_ADDR__M 0x7FFF -#define CP_REG_DL_MB_WR_ADDR_INIT 0x0 - -#define CP_REG_DL_MB_WR_CTR__A 0x1410051 -#define CP_REG_DL_MB_WR_CTR__W 5 -#define CP_REG_DL_MB_WR_CTR__M 0x1F - -#define CP_REG_DL_MB_WR_CTR_WORD__B 2 -#define CP_REG_DL_MB_WR_CTR_WORD__W 3 -#define CP_REG_DL_MB_WR_CTR_WORD__M 0x1C - -#define CP_REG_DL_MB_WR_CTR_OBS__B 1 -#define CP_REG_DL_MB_WR_CTR_OBS__W 1 -#define CP_REG_DL_MB_WR_CTR_OBS__M 0x2 - -#define CP_REG_DL_MB_WR_CTR_CTR__B 0 -#define CP_REG_DL_MB_WR_CTR_CTR__W 1 -#define CP_REG_DL_MB_WR_CTR_CTR__M 0x1 -#define CP_REG_DL_MB_WR_CTR_INIT 0x0 - -#define CP_REG_DL_MB_RD_ADDR__A 0x1410052 -#define CP_REG_DL_MB_RD_ADDR__W 15 -#define CP_REG_DL_MB_RD_ADDR__M 0x7FFF -#define CP_REG_DL_MB_RD_ADDR_INIT 0x0 - -#define CP_REG_DL_MB_RD_CTR__A 0x1410053 -#define CP_REG_DL_MB_RD_CTR__W 11 -#define CP_REG_DL_MB_RD_CTR__M 0x7FF - -#define CP_REG_DL_MB_RD_CTR_TEST__B 10 -#define CP_REG_DL_MB_RD_CTR_TEST__W 1 -#define CP_REG_DL_MB_RD_CTR_TEST__M 0x400 - -#define CP_REG_DL_MB_RD_CTR_OFFSET__B 8 -#define CP_REG_DL_MB_RD_CTR_OFFSET__W 2 -#define CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 - -#define CP_REG_DL_MB_RD_CTR_VALID__B 5 -#define CP_REG_DL_MB_RD_CTR_VALID__W 3 -#define CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 - -#define CP_REG_DL_MB_RD_CTR_WORD__B 2 -#define CP_REG_DL_MB_RD_CTR_WORD__W 3 -#define CP_REG_DL_MB_RD_CTR_WORD__M 0x1C - -#define CP_REG_DL_MB_RD_CTR_OBS__B 1 -#define CP_REG_DL_MB_RD_CTR_OBS__W 1 -#define CP_REG_DL_MB_RD_CTR_OBS__M 0x2 - -#define CP_REG_DL_MB_RD_CTR_CTR__B 0 -#define CP_REG_DL_MB_RD_CTR_CTR__W 1 -#define CP_REG_DL_MB_RD_CTR_CTR__M 0x1 -#define CP_REG_DL_MB_RD_CTR_INIT 0x0 - -#define CP_BR_BUF_RAM__A 0x1420000 - -#define CP_BR_CPL_RAM__A 0x1430000 - -#define CP_PB_DL0_RAM__A 0x1440000 - -#define CP_PB_DL1_RAM__A 0x1450000 - -#define CP_PB_DL2_RAM__A 0x1460000 - -#define CE_SID 0xA - -#define CE_COMM_EXEC__A 0x1800000 -#define CE_COMM_EXEC__W 3 -#define CE_COMM_EXEC__M 0x7 -#define CE_COMM_EXEC_CTL__B 0 -#define CE_COMM_EXEC_CTL__W 3 -#define CE_COMM_EXEC_CTL__M 0x7 -#define CE_COMM_EXEC_CTL_STOP 0x0 -#define CE_COMM_EXEC_CTL_ACTIVE 0x1 -#define CE_COMM_EXEC_CTL_HOLD 0x2 -#define CE_COMM_EXEC_CTL_STEP 0x3 -#define CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define CE_COMM_STATE__A 0x1800001 -#define CE_COMM_STATE__W 16 -#define CE_COMM_STATE__M 0xFFFF -#define CE_COMM_MB__A 0x1800002 -#define CE_COMM_MB__W 16 -#define CE_COMM_MB__M 0xFFFF -#define CE_COMM_SERVICE0__A 0x1800003 -#define CE_COMM_SERVICE0__W 16 -#define CE_COMM_SERVICE0__M 0xFFFF -#define CE_COMM_SERVICE1__A 0x1800004 -#define CE_COMM_SERVICE1__W 16 -#define CE_COMM_SERVICE1__M 0xFFFF -#define CE_COMM_INT_STA__A 0x1800007 -#define CE_COMM_INT_STA__W 16 -#define CE_COMM_INT_STA__M 0xFFFF -#define CE_COMM_INT_MSK__A 0x1800008 -#define CE_COMM_INT_MSK__W 16 -#define CE_COMM_INT_MSK__M 0xFFFF - -#define CE_REG_COMM_EXEC__A 0x1810000 -#define CE_REG_COMM_EXEC__W 3 -#define CE_REG_COMM_EXEC__M 0x7 -#define CE_REG_COMM_EXEC_CTL__B 0 -#define CE_REG_COMM_EXEC_CTL__W 3 -#define CE_REG_COMM_EXEC_CTL__M 0x7 -#define CE_REG_COMM_EXEC_CTL_STOP 0x0 -#define CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define CE_REG_COMM_EXEC_CTL_HOLD 0x2 -#define CE_REG_COMM_EXEC_CTL_STEP 0x3 - -#define CE_REG_COMM_MB__A 0x1810002 -#define CE_REG_COMM_MB__W 4 -#define CE_REG_COMM_MB__M 0xF -#define CE_REG_COMM_MB_CTR__B 0 -#define CE_REG_COMM_MB_CTR__W 1 -#define CE_REG_COMM_MB_CTR__M 0x1 -#define CE_REG_COMM_MB_CTR_OFF 0x0 -#define CE_REG_COMM_MB_CTR_ON 0x1 -#define CE_REG_COMM_MB_OBS__B 1 -#define CE_REG_COMM_MB_OBS__W 1 -#define CE_REG_COMM_MB_OBS__M 0x2 -#define CE_REG_COMM_MB_OBS_OFF 0x0 -#define CE_REG_COMM_MB_OBS_ON 0x2 -#define CE_REG_COMM_MB_OBS_SEL__B 2 -#define CE_REG_COMM_MB_OBS_SEL__W 2 -#define CE_REG_COMM_MB_OBS_SEL__M 0xC -#define CE_REG_COMM_MB_OBS_SEL_FI 0x0 -#define CE_REG_COMM_MB_OBS_SEL_TP 0x4 -#define CE_REG_COMM_MB_OBS_SEL_TI 0x8 -#define CE_REG_COMM_MB_OBS_SEL_FR 0x8 - -#define CE_REG_COMM_SERVICE0__A 0x1810003 -#define CE_REG_COMM_SERVICE0__W 10 -#define CE_REG_COMM_SERVICE0__M 0x3FF -#define CE_REG_COMM_SERVICE0_FT__B 8 -#define CE_REG_COMM_SERVICE0_FT__W 1 -#define CE_REG_COMM_SERVICE0_FT__M 0x100 - -#define CE_REG_COMM_SERVICE1__A 0x1810004 -#define CE_REG_COMM_SERVICE1__W 11 -#define CE_REG_COMM_SERVICE1__M 0x7FF - -#define CE_REG_COMM_INT_STA__A 0x1810007 -#define CE_REG_COMM_INT_STA__W 3 -#define CE_REG_COMM_INT_STA__M 0x7 -#define CE_REG_COMM_INT_STA_CE_PE__B 0 -#define CE_REG_COMM_INT_STA_CE_PE__W 1 -#define CE_REG_COMM_INT_STA_CE_PE__M 0x1 -#define CE_REG_COMM_INT_STA_CE_IR__B 1 -#define CE_REG_COMM_INT_STA_CE_IR__W 1 -#define CE_REG_COMM_INT_STA_CE_IR__M 0x2 -#define CE_REG_COMM_INT_STA_CE_FI__B 2 -#define CE_REG_COMM_INT_STA_CE_FI__W 1 -#define CE_REG_COMM_INT_STA_CE_FI__M 0x4 - -#define CE_REG_COMM_INT_MSK__A 0x1810008 -#define CE_REG_COMM_INT_MSK__W 3 -#define CE_REG_COMM_INT_MSK__M 0x7 -#define CE_REG_COMM_INT_MSK_CE_PE__B 0 -#define CE_REG_COMM_INT_MSK_CE_PE__W 1 -#define CE_REG_COMM_INT_MSK_CE_PE__M 0x1 -#define CE_REG_COMM_INT_MSK_CE_IR__B 1 -#define CE_REG_COMM_INT_MSK_CE_IR__W 1 -#define CE_REG_COMM_INT_MSK_CE_IR__M 0x2 -#define CE_REG_COMM_INT_MSK_CE_FI__B 2 -#define CE_REG_COMM_INT_MSK_CE_FI__W 1 -#define CE_REG_COMM_INT_MSK_CE_FI__M 0x4 - -#define CE_REG_2K__A 0x1810010 -#define CE_REG_2K__W 1 -#define CE_REG_2K__M 0x1 -#define CE_REG_2K_INIT 0x0 - -#define CE_REG_TAPSET__A 0x1810011 -#define CE_REG_TAPSET__W 2 -#define CE_REG_TAPSET__M 0x3 - -#define CE_REG_TAPSET_MOTION_INIT 0x0 - -#define CE_REG_TAPSET_MOTION_NO 0x0 - -#define CE_REG_TAPSET_MOTION_LOW 0x1 - -#define CE_REG_TAPSET_MOTION_HIGH 0x2 - -#define CE_REG_TAPSET_MOTION_UNDEFINED 0x3 - -#define CE_REG_AVG_POW__A 0x1810012 -#define CE_REG_AVG_POW__W 8 -#define CE_REG_AVG_POW__M 0xFF -#define CE_REG_AVG_POW_INIT 0x0 - -#define CE_REG_MAX_POW__A 0x1810013 -#define CE_REG_MAX_POW__W 8 -#define CE_REG_MAX_POW__M 0xFF -#define CE_REG_MAX_POW_INIT 0x0 - -#define CE_REG_ATT__A 0x1810014 -#define CE_REG_ATT__W 8 -#define CE_REG_ATT__M 0xFF -#define CE_REG_ATT_INIT 0x0 - -#define CE_REG_NRED__A 0x1810015 -#define CE_REG_NRED__W 6 -#define CE_REG_NRED__M 0x3F -#define CE_REG_NRED_INIT 0x0 - -#define CE_REG_PU_SIGN__A 0x1810020 -#define CE_REG_PU_SIGN__W 1 -#define CE_REG_PU_SIGN__M 0x1 -#define CE_REG_PU_SIGN_INIT 0x0 - -#define CE_REG_PU_MIX__A 0x1810021 -#define CE_REG_PU_MIX__W 7 -#define CE_REG_PU_MIX__M 0x7F -#define CE_REG_PU_MIX_INIT 0x0 - -#define CE_REG_PB_PILOT_REQ__A 0x1810030 -#define CE_REG_PB_PILOT_REQ__W 15 -#define CE_REG_PB_PILOT_REQ__M 0x7FFF -#define CE_REG_PB_PILOT_REQ_INIT 0x0 -#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 -#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 -#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 -#define CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 -#define CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 -#define CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF - -#define CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 -#define CE_REG_PB_PILOT_REQ_VALID__W 1 -#define CE_REG_PB_PILOT_REQ_VALID__M 0x1 -#define CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 - -#define CE_REG_PB_FREEZE__A 0x1810032 -#define CE_REG_PB_FREEZE__W 1 -#define CE_REG_PB_FREEZE__M 0x1 -#define CE_REG_PB_FREEZE_INIT 0x0 - -#define CE_REG_PB_PILOT_EXP__A 0x1810038 -#define CE_REG_PB_PILOT_EXP__W 4 -#define CE_REG_PB_PILOT_EXP__M 0xF -#define CE_REG_PB_PILOT_EXP_INIT 0x0 - -#define CE_REG_PB_PILOT_REAL__A 0x1810039 -#define CE_REG_PB_PILOT_REAL__W 10 -#define CE_REG_PB_PILOT_REAL__M 0x3FF -#define CE_REG_PB_PILOT_REAL_INIT 0x0 - -#define CE_REG_PB_PILOT_IMAG__A 0x181003A -#define CE_REG_PB_PILOT_IMAG__W 10 -#define CE_REG_PB_PILOT_IMAG__M 0x3FF -#define CE_REG_PB_PILOT_IMAG_INIT 0x0 - -#define CE_REG_PB_SMBNR__A 0x181003B -#define CE_REG_PB_SMBNR__W 5 -#define CE_REG_PB_SMBNR__M 0x1F -#define CE_REG_PB_SMBNR_INIT 0x0 - -#define CE_REG_NE_PILOT_REQ__A 0x1810040 -#define CE_REG_NE_PILOT_REQ__W 12 -#define CE_REG_NE_PILOT_REQ__M 0xFFF -#define CE_REG_NE_PILOT_REQ_INIT 0x0 - -#define CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 -#define CE_REG_NE_PILOT_REQ_VALID__W 2 -#define CE_REG_NE_PILOT_REQ_VALID__M 0x3 -#define CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 -#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 -#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 -#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 -#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 -#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 -#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 - -#define CE_REG_NE_PILOT_DATA__A 0x1810042 -#define CE_REG_NE_PILOT_DATA__W 10 -#define CE_REG_NE_PILOT_DATA__M 0x3FF -#define CE_REG_NE_PILOT_DATA_INIT 0x0 - -#define CE_REG_NE_ERR_SELECT__A 0x1810043 -#define CE_REG_NE_ERR_SELECT__W 3 -#define CE_REG_NE_ERR_SELECT__M 0x7 -#define CE_REG_NE_ERR_SELECT_INIT 0x0 - -#define CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 -#define CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 -#define CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 - -#define CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 -#define CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 -#define CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 - -#define CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 -#define CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 -#define CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 - -#define CE_REG_NE_TD_CAL__A 0x1810044 -#define CE_REG_NE_TD_CAL__W 9 -#define CE_REG_NE_TD_CAL__M 0x1FF -#define CE_REG_NE_TD_CAL_INIT 0x0 - -#define CE_REG_NE_FD_CAL__A 0x1810045 -#define CE_REG_NE_FD_CAL__W 9 -#define CE_REG_NE_FD_CAL__M 0x1FF -#define CE_REG_NE_FD_CAL_INIT 0x0 - -#define CE_REG_NE_MIXAVG__A 0x1810046 -#define CE_REG_NE_MIXAVG__W 3 -#define CE_REG_NE_MIXAVG__M 0x7 -#define CE_REG_NE_MIXAVG_INIT 0x0 - -#define CE_REG_NE_NUPD_OFS__A 0x1810047 -#define CE_REG_NE_NUPD_OFS__W 7 -#define CE_REG_NE_NUPD_OFS__M 0x7F -#define CE_REG_NE_NUPD_OFS_INIT 0x0 - -#define CE_REG_NE_TD_POW__A 0x1810048 -#define CE_REG_NE_TD_POW__W 15 -#define CE_REG_NE_TD_POW__M 0x7FFF -#define CE_REG_NE_TD_POW_INIT 0x0 - -#define CE_REG_NE_TD_POW_EXPONENT__B 10 -#define CE_REG_NE_TD_POW_EXPONENT__W 5 -#define CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 - -#define CE_REG_NE_TD_POW_MANTISSA__B 0 -#define CE_REG_NE_TD_POW_MANTISSA__W 10 -#define CE_REG_NE_TD_POW_MANTISSA__M 0x3FF - -#define CE_REG_NE_FD_POW__A 0x1810049 -#define CE_REG_NE_FD_POW__W 15 -#define CE_REG_NE_FD_POW__M 0x7FFF -#define CE_REG_NE_FD_POW_INIT 0x0 - -#define CE_REG_NE_FD_POW_EXPONENT__B 10 -#define CE_REG_NE_FD_POW_EXPONENT__W 5 -#define CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 - -#define CE_REG_NE_FD_POW_MANTISSA__B 0 -#define CE_REG_NE_FD_POW_MANTISSA__W 10 -#define CE_REG_NE_FD_POW_MANTISSA__M 0x3FF - -#define CE_REG_NE_NEXP_AVG__A 0x181004A -#define CE_REG_NE_NEXP_AVG__W 8 -#define CE_REG_NE_NEXP_AVG__M 0xFF -#define CE_REG_NE_NEXP_AVG_INIT 0x0 - -#define CE_REG_NE_OFFSET__A 0x181004B -#define CE_REG_NE_OFFSET__W 9 -#define CE_REG_NE_OFFSET__M 0x1FF -#define CE_REG_NE_OFFSET_INIT 0x0 - -#define CE_REG_PE_NEXP_OFFS__A 0x1810050 -#define CE_REG_PE_NEXP_OFFS__W 8 -#define CE_REG_PE_NEXP_OFFS__M 0xFF -#define CE_REG_PE_NEXP_OFFS_INIT 0x0 - -#define CE_REG_PE_TIMESHIFT__A 0x1810051 -#define CE_REG_PE_TIMESHIFT__W 14 -#define CE_REG_PE_TIMESHIFT__M 0x3FFF -#define CE_REG_PE_TIMESHIFT_INIT 0x0 - -#define CE_REG_PE_DIF_REAL_L__A 0x1810052 -#define CE_REG_PE_DIF_REAL_L__W 16 -#define CE_REG_PE_DIF_REAL_L__M 0xFFFF -#define CE_REG_PE_DIF_REAL_L_INIT 0x0 - -#define CE_REG_PE_DIF_IMAG_L__A 0x1810053 -#define CE_REG_PE_DIF_IMAG_L__W 16 -#define CE_REG_PE_DIF_IMAG_L__M 0xFFFF -#define CE_REG_PE_DIF_IMAG_L_INIT 0x0 - -#define CE_REG_PE_DIF_REAL_R__A 0x1810054 -#define CE_REG_PE_DIF_REAL_R__W 16 -#define CE_REG_PE_DIF_REAL_R__M 0xFFFF -#define CE_REG_PE_DIF_REAL_R_INIT 0x0 - -#define CE_REG_PE_DIF_IMAG_R__A 0x1810055 -#define CE_REG_PE_DIF_IMAG_R__W 16 -#define CE_REG_PE_DIF_IMAG_R__M 0xFFFF -#define CE_REG_PE_DIF_IMAG_R_INIT 0x0 - -#define CE_REG_PE_ABS_REAL_L__A 0x1810056 -#define CE_REG_PE_ABS_REAL_L__W 16 -#define CE_REG_PE_ABS_REAL_L__M 0xFFFF -#define CE_REG_PE_ABS_REAL_L_INIT 0x0 - -#define CE_REG_PE_ABS_IMAG_L__A 0x1810057 -#define CE_REG_PE_ABS_IMAG_L__W 16 -#define CE_REG_PE_ABS_IMAG_L__M 0xFFFF -#define CE_REG_PE_ABS_IMAG_L_INIT 0x0 - -#define CE_REG_PE_ABS_REAL_R__A 0x1810058 -#define CE_REG_PE_ABS_REAL_R__W 16 -#define CE_REG_PE_ABS_REAL_R__M 0xFFFF -#define CE_REG_PE_ABS_REAL_R_INIT 0x0 - -#define CE_REG_PE_ABS_IMAG_R__A 0x1810059 -#define CE_REG_PE_ABS_IMAG_R__W 16 -#define CE_REG_PE_ABS_IMAG_R__M 0xFFFF -#define CE_REG_PE_ABS_IMAG_R_INIT 0x0 - -#define CE_REG_PE_ABS_EXP_L__A 0x181005A -#define CE_REG_PE_ABS_EXP_L__W 5 -#define CE_REG_PE_ABS_EXP_L__M 0x1F -#define CE_REG_PE_ABS_EXP_L_INIT 0x0 - -#define CE_REG_PE_ABS_EXP_R__A 0x181005B -#define CE_REG_PE_ABS_EXP_R__W 5 -#define CE_REG_PE_ABS_EXP_R__M 0x1F -#define CE_REG_PE_ABS_EXP_R_INIT 0x0 - -#define CE_REG_TP_UPDATE_MODE__A 0x1810060 -#define CE_REG_TP_UPDATE_MODE__W 1 -#define CE_REG_TP_UPDATE_MODE__M 0x1 -#define CE_REG_TP_UPDATE_MODE_INIT 0x0 - -#define CE_REG_TP_LMS_TAP_ON__A 0x1810061 -#define CE_REG_TP_LMS_TAP_ON__W 1 -#define CE_REG_TP_LMS_TAP_ON__M 0x1 - -#define CE_REG_TP_A0_TAP_NEW__A 0x1810064 -#define CE_REG_TP_A0_TAP_NEW__W 10 -#define CE_REG_TP_A0_TAP_NEW__M 0x3FF - -#define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 -#define CE_REG_TP_A0_TAP_NEW_VALID__W 1 -#define CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 - -#define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 -#define CE_REG_TP_A0_MU_LMS_STEP__W 5 -#define CE_REG_TP_A0_MU_LMS_STEP__M 0x1F - -#define CE_REG_TP_A0_TAP_CURR__A 0x1810067 -#define CE_REG_TP_A0_TAP_CURR__W 10 -#define CE_REG_TP_A0_TAP_CURR__M 0x3FF - -#define CE_REG_TP_A1_TAP_NEW__A 0x1810068 -#define CE_REG_TP_A1_TAP_NEW__W 10 -#define CE_REG_TP_A1_TAP_NEW__M 0x3FF - -#define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 -#define CE_REG_TP_A1_TAP_NEW_VALID__W 1 -#define CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 - -#define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A -#define CE_REG_TP_A1_MU_LMS_STEP__W 5 -#define CE_REG_TP_A1_MU_LMS_STEP__M 0x1F - -#define CE_REG_TP_A1_TAP_CURR__A 0x181006B -#define CE_REG_TP_A1_TAP_CURR__W 10 -#define CE_REG_TP_A1_TAP_CURR__M 0x3FF - -#define CE_REG_TP_DOPP_ENERGY__A 0x181006C -#define CE_REG_TP_DOPP_ENERGY__W 15 -#define CE_REG_TP_DOPP_ENERGY__M 0x7FFF -#define CE_REG_TP_DOPP_ENERGY_INIT 0x0 - -#define CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 -#define CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 -#define CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 - -#define CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 -#define CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 -#define CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF - -#define CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D -#define CE_REG_TP_DOPP_DIFF_ENERGY__W 15 -#define CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF -#define CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 - -#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 -#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 -#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 - -#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 -#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 -#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF - -#define CE_REG_TP_A0_TAP_ENERGY__A 0x181006E -#define CE_REG_TP_A0_TAP_ENERGY__W 15 -#define CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF -#define CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 - -#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 -#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 -#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 - -#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 -#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 -#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF - -#define CE_REG_TP_A1_TAP_ENERGY__A 0x181006F -#define CE_REG_TP_A1_TAP_ENERGY__W 15 -#define CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF -#define CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 - -#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 -#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 -#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 - -#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 -#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 -#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF - -#define CE_REG_TI_NEXP_OFFS__A 0x1810070 -#define CE_REG_TI_NEXP_OFFS__W 8 -#define CE_REG_TI_NEXP_OFFS__M 0xFF -#define CE_REG_TI_NEXP_OFFS_INIT 0x0 - -#define CE_REG_TI_PEAK__A 0x1810071 -#define CE_REG_TI_PEAK__W 8 -#define CE_REG_TI_PEAK__M 0xFF -#define CE_REG_TI_PEAK_INIT 0x0 - -#define CE_REG_FI_SHT_INCR__A 0x1810090 -#define CE_REG_FI_SHT_INCR__W 7 -#define CE_REG_FI_SHT_INCR__M 0x7F -#define CE_REG_FI_SHT_INCR_INIT 0x9 - -#define CE_REG_FI_EXP_NORM__A 0x1810091 -#define CE_REG_FI_EXP_NORM__W 4 -#define CE_REG_FI_EXP_NORM__M 0xF -#define CE_REG_FI_EXP_NORM_INIT 0x4 - -#define CE_REG_FI_SUPR_VAL__A 0x1810092 -#define CE_REG_FI_SUPR_VAL__W 1 -#define CE_REG_FI_SUPR_VAL__M 0x1 -#define CE_REG_FI_SUPR_VAL_INIT 0x1 - -#define CE_REG_IR_INPUTSEL__A 0x18100A0 -#define CE_REG_IR_INPUTSEL__W 1 -#define CE_REG_IR_INPUTSEL__M 0x1 -#define CE_REG_IR_INPUTSEL_INIT 0x0 - -#define CE_REG_IR_STARTPOS__A 0x18100A1 -#define CE_REG_IR_STARTPOS__W 8 -#define CE_REG_IR_STARTPOS__M 0xFF -#define CE_REG_IR_STARTPOS_INIT 0x0 - -#define CE_REG_IR_NEXP_THRES__A 0x18100A2 -#define CE_REG_IR_NEXP_THRES__W 8 -#define CE_REG_IR_NEXP_THRES__M 0xFF -#define CE_REG_IR_NEXP_THRES_INIT 0x0 - -#define CE_REG_IR_LENGTH__A 0x18100A3 -#define CE_REG_IR_LENGTH__W 4 -#define CE_REG_IR_LENGTH__M 0xF -#define CE_REG_IR_LENGTH_INIT 0x0 - -#define CE_REG_IR_FREQ__A 0x18100A4 -#define CE_REG_IR_FREQ__W 11 -#define CE_REG_IR_FREQ__M 0x7FF -#define CE_REG_IR_FREQ_INIT 0x0 - -#define CE_REG_IR_FREQINC__A 0x18100A5 -#define CE_REG_IR_FREQINC__W 11 -#define CE_REG_IR_FREQINC__M 0x7FF -#define CE_REG_IR_FREQINC_INIT 0x0 - -#define CE_REG_IR_KAISINC__A 0x18100A6 -#define CE_REG_IR_KAISINC__W 15 -#define CE_REG_IR_KAISINC__M 0x7FFF -#define CE_REG_IR_KAISINC_INIT 0x0 - -#define CE_REG_IR_CTL__A 0x18100A7 -#define CE_REG_IR_CTL__W 3 -#define CE_REG_IR_CTL__M 0x7 -#define CE_REG_IR_CTL_INIT 0x0 - -#define CE_REG_IR_REAL__A 0x18100A8 -#define CE_REG_IR_REAL__W 16 -#define CE_REG_IR_REAL__M 0xFFFF -#define CE_REG_IR_REAL_INIT 0x0 - -#define CE_REG_IR_IMAG__A 0x18100A9 -#define CE_REG_IR_IMAG__W 16 -#define CE_REG_IR_IMAG__M 0xFFFF -#define CE_REG_IR_IMAG_INIT 0x0 - -#define CE_REG_IR_INDEX__A 0x18100AA -#define CE_REG_IR_INDEX__W 12 -#define CE_REG_IR_INDEX__M 0xFFF -#define CE_REG_IR_INDEX_INIT 0x0 - -#define CE_REG_FR_TREAL00__A 0x1820010 -#define CE_REG_FR_TREAL00__W 11 -#define CE_REG_FR_TREAL00__M 0x7FF -#define CE_REG_FR_TREAL00_INIT 0x52 - -#define CE_REG_FR_TIMAG00__A 0x1820011 -#define CE_REG_FR_TIMAG00__W 11 -#define CE_REG_FR_TIMAG00__M 0x7FF -#define CE_REG_FR_TIMAG00_INIT 0x0 - -#define CE_REG_FR_TREAL01__A 0x1820012 -#define CE_REG_FR_TREAL01__W 11 -#define CE_REG_FR_TREAL01__M 0x7FF -#define CE_REG_FR_TREAL01_INIT 0x52 - -#define CE_REG_FR_TIMAG01__A 0x1820013 -#define CE_REG_FR_TIMAG01__W 11 -#define CE_REG_FR_TIMAG01__M 0x7FF -#define CE_REG_FR_TIMAG01_INIT 0x0 - -#define CE_REG_FR_TREAL02__A 0x1820014 -#define CE_REG_FR_TREAL02__W 11 -#define CE_REG_FR_TREAL02__M 0x7FF -#define CE_REG_FR_TREAL02_INIT 0x52 - -#define CE_REG_FR_TIMAG02__A 0x1820015 -#define CE_REG_FR_TIMAG02__W 11 -#define CE_REG_FR_TIMAG02__M 0x7FF -#define CE_REG_FR_TIMAG02_INIT 0x0 - -#define CE_REG_FR_TREAL03__A 0x1820016 -#define CE_REG_FR_TREAL03__W 11 -#define CE_REG_FR_TREAL03__M 0x7FF -#define CE_REG_FR_TREAL03_INIT 0x52 - -#define CE_REG_FR_TIMAG03__A 0x1820017 -#define CE_REG_FR_TIMAG03__W 11 -#define CE_REG_FR_TIMAG03__M 0x7FF -#define CE_REG_FR_TIMAG03_INIT 0x0 - -#define CE_REG_FR_TREAL04__A 0x1820018 -#define CE_REG_FR_TREAL04__W 11 -#define CE_REG_FR_TREAL04__M 0x7FF -#define CE_REG_FR_TREAL04_INIT 0x52 - -#define CE_REG_FR_TIMAG04__A 0x1820019 -#define CE_REG_FR_TIMAG04__W 11 -#define CE_REG_FR_TIMAG04__M 0x7FF -#define CE_REG_FR_TIMAG04_INIT 0x0 - -#define CE_REG_FR_TREAL05__A 0x182001A -#define CE_REG_FR_TREAL05__W 11 -#define CE_REG_FR_TREAL05__M 0x7FF -#define CE_REG_FR_TREAL05_INIT 0x52 - -#define CE_REG_FR_TIMAG05__A 0x182001B -#define CE_REG_FR_TIMAG05__W 11 -#define CE_REG_FR_TIMAG05__M 0x7FF -#define CE_REG_FR_TIMAG05_INIT 0x0 - -#define CE_REG_FR_TREAL06__A 0x182001C -#define CE_REG_FR_TREAL06__W 11 -#define CE_REG_FR_TREAL06__M 0x7FF -#define CE_REG_FR_TREAL06_INIT 0x52 - -#define CE_REG_FR_TIMAG06__A 0x182001D -#define CE_REG_FR_TIMAG06__W 11 -#define CE_REG_FR_TIMAG06__M 0x7FF -#define CE_REG_FR_TIMAG06_INIT 0x0 - -#define CE_REG_FR_TREAL07__A 0x182001E -#define CE_REG_FR_TREAL07__W 11 -#define CE_REG_FR_TREAL07__M 0x7FF -#define CE_REG_FR_TREAL07_INIT 0x52 - -#define CE_REG_FR_TIMAG07__A 0x182001F -#define CE_REG_FR_TIMAG07__W 11 -#define CE_REG_FR_TIMAG07__M 0x7FF -#define CE_REG_FR_TIMAG07_INIT 0x0 - -#define CE_REG_FR_TREAL08__A 0x1820020 -#define CE_REG_FR_TREAL08__W 11 -#define CE_REG_FR_TREAL08__M 0x7FF -#define CE_REG_FR_TREAL08_INIT 0x52 - -#define CE_REG_FR_TIMAG08__A 0x1820021 -#define CE_REG_FR_TIMAG08__W 11 -#define CE_REG_FR_TIMAG08__M 0x7FF -#define CE_REG_FR_TIMAG08_INIT 0x0 - -#define CE_REG_FR_TREAL09__A 0x1820022 -#define CE_REG_FR_TREAL09__W 11 -#define CE_REG_FR_TREAL09__M 0x7FF -#define CE_REG_FR_TREAL09_INIT 0x52 - -#define CE_REG_FR_TIMAG09__A 0x1820023 -#define CE_REG_FR_TIMAG09__W 11 -#define CE_REG_FR_TIMAG09__M 0x7FF -#define CE_REG_FR_TIMAG09_INIT 0x0 - -#define CE_REG_FR_TREAL10__A 0x1820024 -#define CE_REG_FR_TREAL10__W 11 -#define CE_REG_FR_TREAL10__M 0x7FF -#define CE_REG_FR_TREAL10_INIT 0x52 - -#define CE_REG_FR_TIMAG10__A 0x1820025 -#define CE_REG_FR_TIMAG10__W 11 -#define CE_REG_FR_TIMAG10__M 0x7FF -#define CE_REG_FR_TIMAG10_INIT 0x0 - -#define CE_REG_FR_TREAL11__A 0x1820026 -#define CE_REG_FR_TREAL11__W 11 -#define CE_REG_FR_TREAL11__M 0x7FF -#define CE_REG_FR_TREAL11_INIT 0x52 - -#define CE_REG_FR_TIMAG11__A 0x1820027 -#define CE_REG_FR_TIMAG11__W 11 -#define CE_REG_FR_TIMAG11__M 0x7FF -#define CE_REG_FR_TIMAG11_INIT 0x0 - -#define CE_REG_FR_MID_TAP__A 0x1820028 -#define CE_REG_FR_MID_TAP__W 11 -#define CE_REG_FR_MID_TAP__M 0x7FF -#define CE_REG_FR_MID_TAP_INIT 0x51 - -#define CE_REG_FR_SQS_G00__A 0x1820029 -#define CE_REG_FR_SQS_G00__W 8 -#define CE_REG_FR_SQS_G00__M 0xFF -#define CE_REG_FR_SQS_G00_INIT 0xB - -#define CE_REG_FR_SQS_G01__A 0x182002A -#define CE_REG_FR_SQS_G01__W 8 -#define CE_REG_FR_SQS_G01__M 0xFF -#define CE_REG_FR_SQS_G01_INIT 0xB - -#define CE_REG_FR_SQS_G02__A 0x182002B -#define CE_REG_FR_SQS_G02__W 8 -#define CE_REG_FR_SQS_G02__M 0xFF -#define CE_REG_FR_SQS_G02_INIT 0xB - -#define CE_REG_FR_SQS_G03__A 0x182002C -#define CE_REG_FR_SQS_G03__W 8 -#define CE_REG_FR_SQS_G03__M 0xFF -#define CE_REG_FR_SQS_G03_INIT 0xB - -#define CE_REG_FR_SQS_G04__A 0x182002D -#define CE_REG_FR_SQS_G04__W 8 -#define CE_REG_FR_SQS_G04__M 0xFF -#define CE_REG_FR_SQS_G04_INIT 0xB - -#define CE_REG_FR_SQS_G05__A 0x182002E -#define CE_REG_FR_SQS_G05__W 8 -#define CE_REG_FR_SQS_G05__M 0xFF -#define CE_REG_FR_SQS_G05_INIT 0xB - -#define CE_REG_FR_SQS_G06__A 0x182002F -#define CE_REG_FR_SQS_G06__W 8 -#define CE_REG_FR_SQS_G06__M 0xFF -#define CE_REG_FR_SQS_G06_INIT 0xB - -#define CE_REG_FR_SQS_G07__A 0x1820030 -#define CE_REG_FR_SQS_G07__W 8 -#define CE_REG_FR_SQS_G07__M 0xFF -#define CE_REG_FR_SQS_G07_INIT 0xB - -#define CE_REG_FR_SQS_G08__A 0x1820031 -#define CE_REG_FR_SQS_G08__W 8 -#define CE_REG_FR_SQS_G08__M 0xFF -#define CE_REG_FR_SQS_G08_INIT 0xB - -#define CE_REG_FR_SQS_G09__A 0x1820032 -#define CE_REG_FR_SQS_G09__W 8 -#define CE_REG_FR_SQS_G09__M 0xFF -#define CE_REG_FR_SQS_G09_INIT 0xB - -#define CE_REG_FR_SQS_G10__A 0x1820033 -#define CE_REG_FR_SQS_G10__W 8 -#define CE_REG_FR_SQS_G10__M 0xFF -#define CE_REG_FR_SQS_G10_INIT 0xB - -#define CE_REG_FR_SQS_G11__A 0x1820034 -#define CE_REG_FR_SQS_G11__W 8 -#define CE_REG_FR_SQS_G11__M 0xFF -#define CE_REG_FR_SQS_G11_INIT 0xB - -#define CE_REG_FR_SQS_G12__A 0x1820035 -#define CE_REG_FR_SQS_G12__W 8 -#define CE_REG_FR_SQS_G12__M 0xFF -#define CE_REG_FR_SQS_G12_INIT 0x5 - -#define CE_REG_FR_RIO_G00__A 0x1820036 -#define CE_REG_FR_RIO_G00__W 9 -#define CE_REG_FR_RIO_G00__M 0x1FF -#define CE_REG_FR_RIO_G00_INIT 0x1FF - -#define CE_REG_FR_RIO_G01__A 0x1820037 -#define CE_REG_FR_RIO_G01__W 9 -#define CE_REG_FR_RIO_G01__M 0x1FF -#define CE_REG_FR_RIO_G01_INIT 0x190 - -#define CE_REG_FR_RIO_G02__A 0x1820038 -#define CE_REG_FR_RIO_G02__W 9 -#define CE_REG_FR_RIO_G02__M 0x1FF -#define CE_REG_FR_RIO_G02_INIT 0x10B - -#define CE_REG_FR_RIO_G03__A 0x1820039 -#define CE_REG_FR_RIO_G03__W 9 -#define CE_REG_FR_RIO_G03__M 0x1FF -#define CE_REG_FR_RIO_G03_INIT 0xC8 - -#define CE_REG_FR_RIO_G04__A 0x182003A -#define CE_REG_FR_RIO_G04__W 9 -#define CE_REG_FR_RIO_G04__M 0x1FF -#define CE_REG_FR_RIO_G04_INIT 0xA0 - -#define CE_REG_FR_RIO_G05__A 0x182003B -#define CE_REG_FR_RIO_G05__W 9 -#define CE_REG_FR_RIO_G05__M 0x1FF -#define CE_REG_FR_RIO_G05_INIT 0x85 - -#define CE_REG_FR_RIO_G06__A 0x182003C -#define CE_REG_FR_RIO_G06__W 9 -#define CE_REG_FR_RIO_G06__M 0x1FF -#define CE_REG_FR_RIO_G06_INIT 0x72 - -#define CE_REG_FR_RIO_G07__A 0x182003D -#define CE_REG_FR_RIO_G07__W 9 -#define CE_REG_FR_RIO_G07__M 0x1FF -#define CE_REG_FR_RIO_G07_INIT 0x64 - -#define CE_REG_FR_RIO_G08__A 0x182003E -#define CE_REG_FR_RIO_G08__W 9 -#define CE_REG_FR_RIO_G08__M 0x1FF -#define CE_REG_FR_RIO_G08_INIT 0x59 - -#define CE_REG_FR_RIO_G09__A 0x182003F -#define CE_REG_FR_RIO_G09__W 9 -#define CE_REG_FR_RIO_G09__M 0x1FF -#define CE_REG_FR_RIO_G09_INIT 0x50 - -#define CE_REG_FR_RIO_G10__A 0x1820040 -#define CE_REG_FR_RIO_G10__W 9 -#define CE_REG_FR_RIO_G10__M 0x1FF -#define CE_REG_FR_RIO_G10_INIT 0x49 - -#define CE_REG_FR_MODE__A 0x1820041 -#define CE_REG_FR_MODE__W 6 -#define CE_REG_FR_MODE__M 0x3F - -#define CE_REG_FR_MODE_UPDATE_ENABLE__B 0 -#define CE_REG_FR_MODE_UPDATE_ENABLE__W 1 -#define CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 - -#define CE_REG_FR_MODE_ERROR_SHIFT__B 1 -#define CE_REG_FR_MODE_ERROR_SHIFT__W 1 -#define CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 - -#define CE_REG_FR_MODE_NEXP_UPDATE__B 2 -#define CE_REG_FR_MODE_NEXP_UPDATE__W 1 -#define CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 - -#define CE_REG_FR_MODE_MANUAL_SHIFT__B 3 -#define CE_REG_FR_MODE_MANUAL_SHIFT__W 1 -#define CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 - -#define CE_REG_FR_MODE_SQUASH_MODE__B 4 -#define CE_REG_FR_MODE_SQUASH_MODE__W 1 -#define CE_REG_FR_MODE_SQUASH_MODE__M 0x10 - -#define CE_REG_FR_MODE_UPDATE_MODE__B 5 -#define CE_REG_FR_MODE_UPDATE_MODE__W 1 -#define CE_REG_FR_MODE_UPDATE_MODE__M 0x20 -#define CE_REG_FR_MODE_INIT 0x3E - -#define CE_REG_FR_SQS_TRH__A 0x1820042 -#define CE_REG_FR_SQS_TRH__W 8 -#define CE_REG_FR_SQS_TRH__M 0xFF -#define CE_REG_FR_SQS_TRH_INIT 0x80 - -#define CE_REG_FR_RIO_GAIN__A 0x1820043 -#define CE_REG_FR_RIO_GAIN__W 3 -#define CE_REG_FR_RIO_GAIN__M 0x7 -#define CE_REG_FR_RIO_GAIN_INIT 0x2 - -#define CE_REG_FR_BYPASS__A 0x1820044 -#define CE_REG_FR_BYPASS__W 10 -#define CE_REG_FR_BYPASS__M 0x3FF - -#define CE_REG_FR_BYPASS_RUN_IN__B 0 -#define CE_REG_FR_BYPASS_RUN_IN__W 4 -#define CE_REG_FR_BYPASS_RUN_IN__M 0xF - -#define CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 -#define CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 -#define CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 - -#define CE_REG_FR_BYPASS_TOTAL__B 9 -#define CE_REG_FR_BYPASS_TOTAL__W 1 -#define CE_REG_FR_BYPASS_TOTAL__M 0x200 -#define CE_REG_FR_BYPASS_INIT 0x13B - -#define CE_REG_FR_PM_SET__A 0x1820045 -#define CE_REG_FR_PM_SET__W 4 -#define CE_REG_FR_PM_SET__M 0xF -#define CE_REG_FR_PM_SET_INIT 0x4 - -#define CE_REG_FR_ERR_SH__A 0x1820046 -#define CE_REG_FR_ERR_SH__W 4 -#define CE_REG_FR_ERR_SH__M 0xF -#define CE_REG_FR_ERR_SH_INIT 0x4 - -#define CE_REG_FR_MAN_SH__A 0x1820047 -#define CE_REG_FR_MAN_SH__W 4 -#define CE_REG_FR_MAN_SH__M 0xF -#define CE_REG_FR_MAN_SH_INIT 0x7 - -#define CE_REG_FR_TAP_SH__A 0x1820048 -#define CE_REG_FR_TAP_SH__W 3 -#define CE_REG_FR_TAP_SH__M 0x7 -#define CE_REG_FR_TAP_SH_INIT 0x3 - -#define CE_REG_FR_CLIP__A 0x1820049 -#define CE_REG_FR_CLIP__W 9 -#define CE_REG_FR_CLIP__M 0x1FF -#define CE_REG_FR_CLIP_INIT 0x49 - -#define CE_PB_RAM__A 0x1830000 - -#define CE_NE_RAM__A 0x1840000 - -#define EQ_SID 0xE - -#define EQ_COMM_EXEC__A 0x1C00000 -#define EQ_COMM_EXEC__W 3 -#define EQ_COMM_EXEC__M 0x7 -#define EQ_COMM_EXEC_CTL__B 0 -#define EQ_COMM_EXEC_CTL__W 3 -#define EQ_COMM_EXEC_CTL__M 0x7 -#define EQ_COMM_EXEC_CTL_STOP 0x0 -#define EQ_COMM_EXEC_CTL_ACTIVE 0x1 -#define EQ_COMM_EXEC_CTL_HOLD 0x2 -#define EQ_COMM_EXEC_CTL_STEP 0x3 -#define EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define EQ_COMM_STATE__A 0x1C00001 -#define EQ_COMM_STATE__W 16 -#define EQ_COMM_STATE__M 0xFFFF -#define EQ_COMM_MB__A 0x1C00002 -#define EQ_COMM_MB__W 16 -#define EQ_COMM_MB__M 0xFFFF -#define EQ_COMM_SERVICE0__A 0x1C00003 -#define EQ_COMM_SERVICE0__W 16 -#define EQ_COMM_SERVICE0__M 0xFFFF -#define EQ_COMM_SERVICE1__A 0x1C00004 -#define EQ_COMM_SERVICE1__W 16 -#define EQ_COMM_SERVICE1__M 0xFFFF -#define EQ_COMM_INT_STA__A 0x1C00007 -#define EQ_COMM_INT_STA__W 16 -#define EQ_COMM_INT_STA__M 0xFFFF -#define EQ_COMM_INT_MSK__A 0x1C00008 -#define EQ_COMM_INT_MSK__W 16 -#define EQ_COMM_INT_MSK__M 0xFFFF - -#define EQ_REG_COMM_EXEC__A 0x1C10000 -#define EQ_REG_COMM_EXEC__W 3 -#define EQ_REG_COMM_EXEC__M 0x7 -#define EQ_REG_COMM_EXEC_CTL__B 0 -#define EQ_REG_COMM_EXEC_CTL__W 3 -#define EQ_REG_COMM_EXEC_CTL__M 0x7 -#define EQ_REG_COMM_EXEC_CTL_STOP 0x0 -#define EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define EQ_REG_COMM_EXEC_CTL_HOLD 0x2 -#define EQ_REG_COMM_EXEC_CTL_STEP 0x3 - -#define EQ_REG_COMM_STATE__A 0x1C10001 -#define EQ_REG_COMM_STATE__W 4 -#define EQ_REG_COMM_STATE__M 0xF - -#define EQ_REG_COMM_MB__A 0x1C10002 -#define EQ_REG_COMM_MB__W 6 -#define EQ_REG_COMM_MB__M 0x3F -#define EQ_REG_COMM_MB_CTR__B 0 -#define EQ_REG_COMM_MB_CTR__W 1 -#define EQ_REG_COMM_MB_CTR__M 0x1 -#define EQ_REG_COMM_MB_CTR_OFF 0x0 -#define EQ_REG_COMM_MB_CTR_ON 0x1 -#define EQ_REG_COMM_MB_OBS__B 1 -#define EQ_REG_COMM_MB_OBS__W 1 -#define EQ_REG_COMM_MB_OBS__M 0x2 -#define EQ_REG_COMM_MB_OBS_OFF 0x0 -#define EQ_REG_COMM_MB_OBS_ON 0x2 -#define EQ_REG_COMM_MB_CTR_MUX__B 2 -#define EQ_REG_COMM_MB_CTR_MUX__W 2 -#define EQ_REG_COMM_MB_CTR_MUX__M 0xC -#define EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 -#define EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 -#define EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 -#define EQ_REG_COMM_MB_OBS_MUX__B 4 -#define EQ_REG_COMM_MB_OBS_MUX__W 2 -#define EQ_REG_COMM_MB_OBS_MUX__M 0x30 -#define EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 -#define EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 -#define EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 -#define EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 - -#define EQ_REG_COMM_SERVICE0__A 0x1C10003 -#define EQ_REG_COMM_SERVICE0__W 10 -#define EQ_REG_COMM_SERVICE0__M 0x3FF - -#define EQ_REG_COMM_SERVICE1__A 0x1C10004 -#define EQ_REG_COMM_SERVICE1__W 11 -#define EQ_REG_COMM_SERVICE1__M 0x7FF - -#define EQ_REG_COMM_INT_STA__A 0x1C10007 -#define EQ_REG_COMM_INT_STA__W 2 -#define EQ_REG_COMM_INT_STA__M 0x3 -#define EQ_REG_COMM_INT_STA_TPS_RDY__B 0 -#define EQ_REG_COMM_INT_STA_TPS_RDY__W 1 -#define EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 -#define EQ_REG_COMM_INT_STA_ERR_RDY__B 1 -#define EQ_REG_COMM_INT_STA_ERR_RDY__W 1 -#define EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 - -#define EQ_REG_COMM_INT_MSK__A 0x1C10008 -#define EQ_REG_COMM_INT_MSK__W 2 -#define EQ_REG_COMM_INT_MSK__M 0x3 -#define EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 -#define EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 -#define EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 -#define EQ_REG_COMM_INT_MSK_MER_RDY__B 1 -#define EQ_REG_COMM_INT_MSK_MER_RDY__W 1 -#define EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 - -#define EQ_REG_IS_MODE__A 0x1C10014 -#define EQ_REG_IS_MODE__W 4 -#define EQ_REG_IS_MODE__M 0xF -#define EQ_REG_IS_MODE_INIT 0x0 - -#define EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 -#define EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 -#define EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 -#define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 -#define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 - -#define EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 -#define EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 -#define EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 -#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 -#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 - -#define EQ_REG_IS_GAIN_MAN__A 0x1C10015 -#define EQ_REG_IS_GAIN_MAN__W 10 -#define EQ_REG_IS_GAIN_MAN__M 0x3FF -#define EQ_REG_IS_GAIN_MAN_INIT 0x0 - -#define EQ_REG_IS_GAIN_EXP__A 0x1C10016 -#define EQ_REG_IS_GAIN_EXP__W 5 -#define EQ_REG_IS_GAIN_EXP__M 0x1F -#define EQ_REG_IS_GAIN_EXP_INIT 0x0 - -#define EQ_REG_IS_CLIP_EXP__A 0x1C10017 -#define EQ_REG_IS_CLIP_EXP__W 5 -#define EQ_REG_IS_CLIP_EXP__M 0x1F -#define EQ_REG_IS_CLIP_EXP_INIT 0x0 - -#define EQ_REG_DV_MODE__A 0x1C1001E -#define EQ_REG_DV_MODE__W 4 -#define EQ_REG_DV_MODE__M 0xF -#define EQ_REG_DV_MODE_INIT 0x0 - -#define EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 -#define EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 -#define EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 -#define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 -#define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 - -#define EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 -#define EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 -#define EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 -#define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 -#define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 - -#define EQ_REG_DV_MODE_CLP_REA_ENA__B 2 -#define EQ_REG_DV_MODE_CLP_REA_ENA__W 1 -#define EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 -#define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 -#define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 - -#define EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 -#define EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 -#define EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 -#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 -#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 - -#define EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F -#define EQ_REG_DV_POS_CLIP_DAT__W 16 -#define EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF - -#define EQ_REG_SN_MODE__A 0x1C10028 -#define EQ_REG_SN_MODE__W 8 -#define EQ_REG_SN_MODE__M 0xFF -#define EQ_REG_SN_MODE_INIT 0x0 - -#define EQ_REG_SN_MODE_MODE_0__B 0 -#define EQ_REG_SN_MODE_MODE_0__W 1 -#define EQ_REG_SN_MODE_MODE_0__M 0x1 -#define EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 - -#define EQ_REG_SN_MODE_MODE_1__B 1 -#define EQ_REG_SN_MODE_MODE_1__W 1 -#define EQ_REG_SN_MODE_MODE_1__M 0x2 -#define EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 - -#define EQ_REG_SN_MODE_MODE_2__B 2 -#define EQ_REG_SN_MODE_MODE_2__W 1 -#define EQ_REG_SN_MODE_MODE_2__M 0x4 -#define EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 - -#define EQ_REG_SN_MODE_MODE_3__B 3 -#define EQ_REG_SN_MODE_MODE_3__W 1 -#define EQ_REG_SN_MODE_MODE_3__M 0x8 -#define EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 - -#define EQ_REG_SN_MODE_MODE_4__B 4 -#define EQ_REG_SN_MODE_MODE_4__W 1 -#define EQ_REG_SN_MODE_MODE_4__M 0x10 -#define EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 - -#define EQ_REG_SN_MODE_MODE_5__B 5 -#define EQ_REG_SN_MODE_MODE_5__W 1 -#define EQ_REG_SN_MODE_MODE_5__M 0x20 -#define EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 - -#define EQ_REG_SN_MODE_MODE_6__B 6 -#define EQ_REG_SN_MODE_MODE_6__W 1 -#define EQ_REG_SN_MODE_MODE_6__M 0x40 -#define EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 -#define EQ_REG_SN_MODE_MODE_6_STATIC 0x40 - -#define EQ_REG_SN_MODE_MODE_7__B 7 -#define EQ_REG_SN_MODE_MODE_7__W 1 -#define EQ_REG_SN_MODE_MODE_7__M 0x80 -#define EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 -#define EQ_REG_SN_MODE_MODE_7_STATIC 0x80 - -#define EQ_REG_SN_PFIX__A 0x1C10029 -#define EQ_REG_SN_PFIX__W 8 -#define EQ_REG_SN_PFIX__M 0xFF -#define EQ_REG_SN_PFIX_INIT 0x0 - -#define EQ_REG_SN_CEGAIN__A 0x1C1002A -#define EQ_REG_SN_CEGAIN__W 8 -#define EQ_REG_SN_CEGAIN__M 0xFF -#define EQ_REG_SN_CEGAIN_INIT 0x0 - -#define EQ_REG_SN_OFFSET__A 0x1C1002B -#define EQ_REG_SN_OFFSET__W 6 -#define EQ_REG_SN_OFFSET__M 0x3F -#define EQ_REG_SN_OFFSET_INIT 0x0 - -#define EQ_REG_SN_NULLIFY__A 0x1C1002C -#define EQ_REG_SN_NULLIFY__W 6 -#define EQ_REG_SN_NULLIFY__M 0x3F -#define EQ_REG_SN_NULLIFY_INIT 0x0 - -#define EQ_REG_SN_SQUASH__A 0x1C1002D -#define EQ_REG_SN_SQUASH__W 10 -#define EQ_REG_SN_SQUASH__M 0x3FF -#define EQ_REG_SN_SQUASH_INIT 0x0 - -#define EQ_REG_SN_SQUASH_MAN__B 0 -#define EQ_REG_SN_SQUASH_MAN__W 6 -#define EQ_REG_SN_SQUASH_MAN__M 0x3F - -#define EQ_REG_SN_SQUASH_EXP__B 6 -#define EQ_REG_SN_SQUASH_EXP__W 4 -#define EQ_REG_SN_SQUASH_EXP__M 0x3C0 - -#define EQ_REG_RC_SEL_CAR__A 0x1C10032 -#define EQ_REG_RC_SEL_CAR__W 6 -#define EQ_REG_RC_SEL_CAR__M 0x3F -#define EQ_REG_RC_SEL_CAR_INIT 0x0 -#define EQ_REG_RC_SEL_CAR_DIV__B 0 -#define EQ_REG_RC_SEL_CAR_DIV__W 1 -#define EQ_REG_RC_SEL_CAR_DIV__M 0x1 -#define EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 -#define EQ_REG_RC_SEL_CAR_DIV_ON 0x1 - -#define EQ_REG_RC_SEL_CAR_PASS__B 1 -#define EQ_REG_RC_SEL_CAR_PASS__W 2 -#define EQ_REG_RC_SEL_CAR_PASS__M 0x6 -#define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 -#define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 -#define EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 -#define EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 - -#define EQ_REG_RC_SEL_CAR_LOCAL__B 3 -#define EQ_REG_RC_SEL_CAR_LOCAL__W 2 -#define EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 -#define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 -#define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 -#define EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 -#define EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 - -#define EQ_REG_RC_SEL_CAR_MEAS__B 5 -#define EQ_REG_RC_SEL_CAR_MEAS__W 1 -#define EQ_REG_RC_SEL_CAR_MEAS__M 0x20 -#define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 -#define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 - -#define EQ_REG_RC_STS__A 0x1C10033 -#define EQ_REG_RC_STS__W 12 -#define EQ_REG_RC_STS__M 0xFFF - -#define EQ_REG_RC_STS_DIFF__B 0 -#define EQ_REG_RC_STS_DIFF__W 9 -#define EQ_REG_RC_STS_DIFF__M 0x1FF - -#define EQ_REG_RC_STS_FIRST__B 9 -#define EQ_REG_RC_STS_FIRST__W 1 -#define EQ_REG_RC_STS_FIRST__M 0x200 -#define EQ_REG_RC_STS_FIRST_A_CE 0x0 -#define EQ_REG_RC_STS_FIRST_B_DRI 0x200 - -#define EQ_REG_RC_STS_SELEC__B 10 -#define EQ_REG_RC_STS_SELEC__W 1 -#define EQ_REG_RC_STS_SELEC__M 0x400 -#define EQ_REG_RC_STS_SELEC_A_CE 0x0 -#define EQ_REG_RC_STS_SELEC_B_DRI 0x400 - -#define EQ_REG_RC_STS_OVERFLOW__B 11 -#define EQ_REG_RC_STS_OVERFLOW__W 1 -#define EQ_REG_RC_STS_OVERFLOW__M 0x800 -#define EQ_REG_RC_STS_OVERFLOW_NO 0x0 -#define EQ_REG_RC_STS_OVERFLOW_YES 0x800 - -#define EQ_REG_OT_CONST__A 0x1C10046 -#define EQ_REG_OT_CONST__W 2 -#define EQ_REG_OT_CONST__M 0x3 -#define EQ_REG_OT_CONST_INIT 0x0 - -#define EQ_REG_OT_ALPHA__A 0x1C10047 -#define EQ_REG_OT_ALPHA__W 2 -#define EQ_REG_OT_ALPHA__M 0x3 -#define EQ_REG_OT_ALPHA_INIT 0x0 - -#define EQ_REG_OT_QNT_THRES0__A 0x1C10048 -#define EQ_REG_OT_QNT_THRES0__W 5 -#define EQ_REG_OT_QNT_THRES0__M 0x1F -#define EQ_REG_OT_QNT_THRES0_INIT 0x0 - -#define EQ_REG_OT_QNT_THRES1__A 0x1C10049 -#define EQ_REG_OT_QNT_THRES1__W 5 -#define EQ_REG_OT_QNT_THRES1__M 0x1F -#define EQ_REG_OT_QNT_THRES1_INIT 0x0 - -#define EQ_REG_OT_CSI_STEP__A 0x1C1004A -#define EQ_REG_OT_CSI_STEP__W 4 -#define EQ_REG_OT_CSI_STEP__M 0xF -#define EQ_REG_OT_CSI_STEP_INIT 0x0 - -#define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B -#define EQ_REG_OT_CSI_OFFSET__W 7 -#define EQ_REG_OT_CSI_OFFSET__M 0x7F -#define EQ_REG_OT_CSI_OFFSET_INIT 0x0 - -#define EQ_REG_TD_TPS_INIT__A 0x1C10050 -#define EQ_REG_TD_TPS_INIT__W 1 -#define EQ_REG_TD_TPS_INIT__M 0x1 -#define EQ_REG_TD_TPS_INIT_INIT 0x0 -#define EQ_REG_TD_TPS_INIT_POS 0x0 -#define EQ_REG_TD_TPS_INIT_NEG 0x1 - -#define EQ_REG_TD_TPS_SYNC__A 0x1C10051 -#define EQ_REG_TD_TPS_SYNC__W 16 -#define EQ_REG_TD_TPS_SYNC__M 0xFFFF -#define EQ_REG_TD_TPS_SYNC_INIT 0x0 -#define EQ_REG_TD_TPS_SYNC_ODD 0x35EE -#define EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 - -#define EQ_REG_TD_TPS_LEN__A 0x1C10052 -#define EQ_REG_TD_TPS_LEN__W 6 -#define EQ_REG_TD_TPS_LEN__M 0x3F -#define EQ_REG_TD_TPS_LEN_INIT 0x0 -#define EQ_REG_TD_TPS_LEN_DEF 0x17 -#define EQ_REG_TD_TPS_LEN_ID_SUP 0x1F - -#define EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 -#define EQ_REG_TD_TPS_FRM_NMB__W 2 -#define EQ_REG_TD_TPS_FRM_NMB__M 0x3 -#define EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 -#define EQ_REG_TD_TPS_FRM_NMB_1 0x0 -#define EQ_REG_TD_TPS_FRM_NMB_2 0x1 -#define EQ_REG_TD_TPS_FRM_NMB_3 0x2 -#define EQ_REG_TD_TPS_FRM_NMB_4 0x3 - -#define EQ_REG_TD_TPS_CONST__A 0x1C10054 -#define EQ_REG_TD_TPS_CONST__W 2 -#define EQ_REG_TD_TPS_CONST__M 0x3 -#define EQ_REG_TD_TPS_CONST_INIT 0x0 -#define EQ_REG_TD_TPS_CONST_QPSK 0x0 -#define EQ_REG_TD_TPS_CONST_16QAM 0x1 -#define EQ_REG_TD_TPS_CONST_64QAM 0x2 - -#define EQ_REG_TD_TPS_HINFO__A 0x1C10055 -#define EQ_REG_TD_TPS_HINFO__W 3 -#define EQ_REG_TD_TPS_HINFO__M 0x7 -#define EQ_REG_TD_TPS_HINFO_INIT 0x0 -#define EQ_REG_TD_TPS_HINFO_NH 0x0 -#define EQ_REG_TD_TPS_HINFO_H1 0x1 -#define EQ_REG_TD_TPS_HINFO_H2 0x2 -#define EQ_REG_TD_TPS_HINFO_H4 0x3 - -#define EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 -#define EQ_REG_TD_TPS_CODE_HP__W 3 -#define EQ_REG_TD_TPS_CODE_HP__M 0x7 -#define EQ_REG_TD_TPS_CODE_HP_INIT 0x0 -#define EQ_REG_TD_TPS_CODE_HP_1_2 0x0 -#define EQ_REG_TD_TPS_CODE_HP_2_3 0x1 -#define EQ_REG_TD_TPS_CODE_HP_3_4 0x2 -#define EQ_REG_TD_TPS_CODE_HP_5_6 0x3 -#define EQ_REG_TD_TPS_CODE_HP_7_8 0x4 - -#define EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 -#define EQ_REG_TD_TPS_CODE_LP__W 3 -#define EQ_REG_TD_TPS_CODE_LP__M 0x7 -#define EQ_REG_TD_TPS_CODE_LP_INIT 0x0 -#define EQ_REG_TD_TPS_CODE_LP_1_2 0x0 -#define EQ_REG_TD_TPS_CODE_LP_2_3 0x1 -#define EQ_REG_TD_TPS_CODE_LP_3_4 0x2 -#define EQ_REG_TD_TPS_CODE_LP_5_6 0x3 -#define EQ_REG_TD_TPS_CODE_LP_7_8 0x4 - -#define EQ_REG_TD_TPS_GUARD__A 0x1C10058 -#define EQ_REG_TD_TPS_GUARD__W 2 -#define EQ_REG_TD_TPS_GUARD__M 0x3 -#define EQ_REG_TD_TPS_GUARD_INIT 0x0 -#define EQ_REG_TD_TPS_GUARD_32 0x0 -#define EQ_REG_TD_TPS_GUARD_16 0x1 -#define EQ_REG_TD_TPS_GUARD_08 0x2 -#define EQ_REG_TD_TPS_GUARD_04 0x3 - -#define EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 -#define EQ_REG_TD_TPS_TR_MODE__W 2 -#define EQ_REG_TD_TPS_TR_MODE__M 0x3 -#define EQ_REG_TD_TPS_TR_MODE_INIT 0x0 -#define EQ_REG_TD_TPS_TR_MODE_2K 0x0 -#define EQ_REG_TD_TPS_TR_MODE_8K 0x1 - -#define EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A -#define EQ_REG_TD_TPS_CELL_ID_HI__W 8 -#define EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF -#define EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 - -#define EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B -#define EQ_REG_TD_TPS_CELL_ID_LO__W 8 -#define EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF -#define EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 - -#define EQ_REG_TD_TPS_RSV__A 0x1C1005C -#define EQ_REG_TD_TPS_RSV__W 6 -#define EQ_REG_TD_TPS_RSV__M 0x3F -#define EQ_REG_TD_TPS_RSV_INIT 0x0 - -#define EQ_REG_TD_TPS_BCH__A 0x1C1005D -#define EQ_REG_TD_TPS_BCH__W 14 -#define EQ_REG_TD_TPS_BCH__M 0x3FFF -#define EQ_REG_TD_TPS_BCH_INIT 0x0 - -#define EQ_REG_TD_SQR_ERR_I__A 0x1C1005E -#define EQ_REG_TD_SQR_ERR_I__W 16 -#define EQ_REG_TD_SQR_ERR_I__M 0xFFFF -#define EQ_REG_TD_SQR_ERR_I_INIT 0x0 - -#define EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F -#define EQ_REG_TD_SQR_ERR_Q__W 16 -#define EQ_REG_TD_SQR_ERR_Q__M 0xFFFF -#define EQ_REG_TD_SQR_ERR_Q_INIT 0x0 - -#define EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 -#define EQ_REG_TD_SQR_ERR_EXP__W 4 -#define EQ_REG_TD_SQR_ERR_EXP__M 0xF -#define EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 - -#define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 -#define EQ_REG_TD_REQ_SMB_CNT__W 16 -#define EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF -#define EQ_REG_TD_REQ_SMB_CNT_INIT 0x0 - -#define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 -#define EQ_REG_TD_TPS_PWR_OFS__W 16 -#define EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF -#define EQ_REG_TD_TPS_PWR_OFS_INIT 0x0 - -#define EC_COMM_EXEC__A 0x2000000 -#define EC_COMM_EXEC__W 3 -#define EC_COMM_EXEC__M 0x7 -#define EC_COMM_EXEC_CTL__B 0 -#define EC_COMM_EXEC_CTL__W 3 -#define EC_COMM_EXEC_CTL__M 0x7 -#define EC_COMM_EXEC_CTL_STOP 0x0 -#define EC_COMM_EXEC_CTL_ACTIVE 0x1 -#define EC_COMM_EXEC_CTL_HOLD 0x2 -#define EC_COMM_EXEC_CTL_STEP 0x3 -#define EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define EC_COMM_STATE__A 0x2000001 -#define EC_COMM_STATE__W 16 -#define EC_COMM_STATE__M 0xFFFF -#define EC_COMM_MB__A 0x2000002 -#define EC_COMM_MB__W 16 -#define EC_COMM_MB__M 0xFFFF -#define EC_COMM_SERVICE0__A 0x2000003 -#define EC_COMM_SERVICE0__W 16 -#define EC_COMM_SERVICE0__M 0xFFFF -#define EC_COMM_SERVICE1__A 0x2000004 -#define EC_COMM_SERVICE1__W 16 -#define EC_COMM_SERVICE1__M 0xFFFF -#define EC_COMM_INT_STA__A 0x2000007 -#define EC_COMM_INT_STA__W 16 -#define EC_COMM_INT_STA__M 0xFFFF -#define EC_COMM_INT_MSK__A 0x2000008 -#define EC_COMM_INT_MSK__W 16 -#define EC_COMM_INT_MSK__M 0xFFFF - -#define EC_SB_SID 0x16 - -#define EC_SB_REG_COMM_EXEC__A 0x2010000 -#define EC_SB_REG_COMM_EXEC__W 3 -#define EC_SB_REG_COMM_EXEC__M 0x7 -#define EC_SB_REG_COMM_EXEC_CTL__B 0 -#define EC_SB_REG_COMM_EXEC_CTL__W 3 -#define EC_SB_REG_COMM_EXEC_CTL__M 0x7 -#define EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 -#define EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define EC_SB_REG_COMM_STATE__A 0x2010001 -#define EC_SB_REG_COMM_STATE__W 4 -#define EC_SB_REG_COMM_STATE__M 0xF -#define EC_SB_REG_COMM_MB__A 0x2010002 -#define EC_SB_REG_COMM_MB__W 2 -#define EC_SB_REG_COMM_MB__M 0x3 -#define EC_SB_REG_COMM_MB_CTR__B 0 -#define EC_SB_REG_COMM_MB_CTR__W 1 -#define EC_SB_REG_COMM_MB_CTR__M 0x1 -#define EC_SB_REG_COMM_MB_CTR_OFF 0x0 -#define EC_SB_REG_COMM_MB_CTR_ON 0x1 -#define EC_SB_REG_COMM_MB_OBS__B 1 -#define EC_SB_REG_COMM_MB_OBS__W 1 -#define EC_SB_REG_COMM_MB_OBS__M 0x2 -#define EC_SB_REG_COMM_MB_OBS_OFF 0x0 -#define EC_SB_REG_COMM_MB_OBS_ON 0x2 - -#define EC_SB_REG_TR_MODE__A 0x2010010 -#define EC_SB_REG_TR_MODE__W 1 -#define EC_SB_REG_TR_MODE__M 0x1 -#define EC_SB_REG_TR_MODE_INIT 0x0 -#define EC_SB_REG_TR_MODE_8K 0x0 -#define EC_SB_REG_TR_MODE_2K 0x1 - -#define EC_SB_REG_CONST__A 0x2010011 -#define EC_SB_REG_CONST__W 2 -#define EC_SB_REG_CONST__M 0x3 -#define EC_SB_REG_CONST_INIT 0x2 -#define EC_SB_REG_CONST_QPSK 0x0 -#define EC_SB_REG_CONST_16QAM 0x1 -#define EC_SB_REG_CONST_64QAM 0x2 - -#define EC_SB_REG_ALPHA__A 0x2010012 -#define EC_SB_REG_ALPHA__W 3 -#define EC_SB_REG_ALPHA__M 0x7 - -#define EC_SB_REG_ALPHA_INIT 0x0 - -#define EC_SB_REG_ALPHA_NH 0x0 - -#define EC_SB_REG_ALPHA_H1 0x1 - -#define EC_SB_REG_ALPHA_H2 0x2 - -#define EC_SB_REG_ALPHA_H4 0x3 - -#define EC_SB_REG_PRIOR__A 0x2010013 -#define EC_SB_REG_PRIOR__W 1 -#define EC_SB_REG_PRIOR__M 0x1 -#define EC_SB_REG_PRIOR_INIT 0x0 -#define EC_SB_REG_PRIOR_HI 0x0 -#define EC_SB_REG_PRIOR_LO 0x1 - -#define EC_SB_REG_CSI_HI__A 0x2010014 -#define EC_SB_REG_CSI_HI__W 5 -#define EC_SB_REG_CSI_HI__M 0x1F -#define EC_SB_REG_CSI_HI_INIT 0x1F -#define EC_SB_REG_CSI_HI_MAX 0x1F -#define EC_SB_REG_CSI_HI_MIN 0x0 -#define EC_SB_REG_CSI_HI_TAG 0x0 - -#define EC_SB_REG_CSI_LO__A 0x2010015 -#define EC_SB_REG_CSI_LO__W 5 -#define EC_SB_REG_CSI_LO__M 0x1F -#define EC_SB_REG_CSI_LO_INIT 0x1F -#define EC_SB_REG_CSI_LO_MAX 0x1F -#define EC_SB_REG_CSI_LO_MIN 0x0 -#define EC_SB_REG_CSI_LO_TAG 0x0 - -#define EC_SB_REG_SMB_TGL__A 0x2010016 -#define EC_SB_REG_SMB_TGL__W 1 -#define EC_SB_REG_SMB_TGL__M 0x1 -#define EC_SB_REG_SMB_TGL_OFF 0x0 -#define EC_SB_REG_SMB_TGL_ON 0x1 - -#define EC_SB_REG_SNR_HI__A 0x2010017 -#define EC_SB_REG_SNR_HI__W 8 -#define EC_SB_REG_SNR_HI__M 0xFF -#define EC_SB_REG_SNR_HI_INIT 0xFF -#define EC_SB_REG_SNR_HI_MAX 0xFF -#define EC_SB_REG_SNR_HI_MIN 0x0 -#define EC_SB_REG_SNR_HI_TAG 0x0 - -#define EC_SB_REG_SNR_MID__A 0x2010018 -#define EC_SB_REG_SNR_MID__W 8 -#define EC_SB_REG_SNR_MID__M 0xFF -#define EC_SB_REG_SNR_MID_INIT 0xFF -#define EC_SB_REG_SNR_MID_MAX 0xFF -#define EC_SB_REG_SNR_MID_MIN 0x0 -#define EC_SB_REG_SNR_MID_TAG 0x0 - -#define EC_SB_REG_SNR_LO__A 0x2010019 -#define EC_SB_REG_SNR_LO__W 8 -#define EC_SB_REG_SNR_LO__M 0xFF -#define EC_SB_REG_SNR_LO_INIT 0xFF -#define EC_SB_REG_SNR_LO_MAX 0xFF -#define EC_SB_REG_SNR_LO_MIN 0x0 -#define EC_SB_REG_SNR_LO_TAG 0x0 - -#define EC_SB_REG_SCALE_MSB__A 0x201001A -#define EC_SB_REG_SCALE_MSB__W 6 -#define EC_SB_REG_SCALE_MSB__M 0x3F -#define EC_SB_REG_SCALE_MSB_INIT 0x30 -#define EC_SB_REG_SCALE_MSB_MAX 0x3F - -#define EC_SB_REG_SCALE_BIT2__A 0x201001B -#define EC_SB_REG_SCALE_BIT2__W 6 -#define EC_SB_REG_SCALE_BIT2__M 0x3F -#define EC_SB_REG_SCALE_BIT2_INIT 0x20 -#define EC_SB_REG_SCALE_BIT2_MAX 0x3F - -#define EC_SB_REG_SCALE_LSB__A 0x201001C -#define EC_SB_REG_SCALE_LSB__W 6 -#define EC_SB_REG_SCALE_LSB__M 0x3F -#define EC_SB_REG_SCALE_LSB_INIT 0x10 -#define EC_SB_REG_SCALE_LSB_MAX 0x3F - -#define EC_SB_REG_CSI_OFS__A 0x201001D -#define EC_SB_REG_CSI_OFS__W 4 -#define EC_SB_REG_CSI_OFS__M 0xF -#define EC_SB_REG_CSI_OFS_INIT 0x1 -#define EC_SB_REG_CSI_OFS_ADD__B 0 -#define EC_SB_REG_CSI_OFS_ADD__W 3 -#define EC_SB_REG_CSI_OFS_ADD__M 0x7 -#define EC_SB_REG_CSI_OFS_DIS__B 3 -#define EC_SB_REG_CSI_OFS_DIS__W 1 -#define EC_SB_REG_CSI_OFS_DIS__M 0x8 -#define EC_SB_REG_CSI_OFS_DIS_ENA 0x0 -#define EC_SB_REG_CSI_OFS_DIS_DIS 0x8 - -#define EC_SB_SD_RAM__A 0x2020000 - -#define EC_SB_BD0_RAM__A 0x2030000 - -#define EC_SB_BD1_RAM__A 0x2040000 - -#define EC_VD_SID 0x17 - -#define EC_VD_REG_COMM_EXEC__A 0x2090000 -#define EC_VD_REG_COMM_EXEC__W 3 -#define EC_VD_REG_COMM_EXEC__M 0x7 -#define EC_VD_REG_COMM_EXEC_CTL__B 0 -#define EC_VD_REG_COMM_EXEC_CTL__W 3 -#define EC_VD_REG_COMM_EXEC_CTL__M 0x7 -#define EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 -#define EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define EC_VD_REG_COMM_STATE__A 0x2090001 -#define EC_VD_REG_COMM_STATE__W 4 -#define EC_VD_REG_COMM_STATE__M 0xF -#define EC_VD_REG_COMM_MB__A 0x2090002 -#define EC_VD_REG_COMM_MB__W 2 -#define EC_VD_REG_COMM_MB__M 0x3 -#define EC_VD_REG_COMM_MB_CTR__B 0 -#define EC_VD_REG_COMM_MB_CTR__W 1 -#define EC_VD_REG_COMM_MB_CTR__M 0x1 -#define EC_VD_REG_COMM_MB_CTR_OFF 0x0 -#define EC_VD_REG_COMM_MB_CTR_ON 0x1 -#define EC_VD_REG_COMM_MB_OBS__B 1 -#define EC_VD_REG_COMM_MB_OBS__W 1 -#define EC_VD_REG_COMM_MB_OBS__M 0x2 -#define EC_VD_REG_COMM_MB_OBS_OFF 0x0 -#define EC_VD_REG_COMM_MB_OBS_ON 0x2 - -#define EC_VD_REG_COMM_SERVICE0__A 0x2090003 -#define EC_VD_REG_COMM_SERVICE0__W 16 -#define EC_VD_REG_COMM_SERVICE0__M 0xFFFF -#define EC_VD_REG_COMM_SERVICE1__A 0x2090004 -#define EC_VD_REG_COMM_SERVICE1__W 16 -#define EC_VD_REG_COMM_SERVICE1__M 0xFFFF -#define EC_VD_REG_COMM_INT_STA__A 0x2090007 -#define EC_VD_REG_COMM_INT_STA__W 1 -#define EC_VD_REG_COMM_INT_STA__M 0x1 -#define EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 -#define EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 -#define EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 - -#define EC_VD_REG_COMM_INT_MSK__A 0x2090008 -#define EC_VD_REG_COMM_INT_MSK__W 1 -#define EC_VD_REG_COMM_INT_MSK__M 0x1 -#define EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 -#define EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 -#define EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 - -#define EC_VD_REG_FORCE__A 0x2090010 -#define EC_VD_REG_FORCE__W 2 -#define EC_VD_REG_FORCE__M 0x3 -#define EC_VD_REG_FORCE_INIT 0x0 -#define EC_VD_REG_FORCE_FREE 0x0 -#define EC_VD_REG_FORCE_PROP 0x1 -#define EC_VD_REG_FORCE_FORCED 0x2 -#define EC_VD_REG_FORCE_FIXED 0x3 - -#define EC_VD_REG_SET_CODERATE__A 0x2090011 -#define EC_VD_REG_SET_CODERATE__W 3 -#define EC_VD_REG_SET_CODERATE__M 0x7 -#define EC_VD_REG_SET_CODERATE_INIT 0x0 -#define EC_VD_REG_SET_CODERATE_C1_2 0x0 -#define EC_VD_REG_SET_CODERATE_C2_3 0x1 -#define EC_VD_REG_SET_CODERATE_C3_4 0x2 -#define EC_VD_REG_SET_CODERATE_C5_6 0x3 -#define EC_VD_REG_SET_CODERATE_C7_8 0x4 - -#define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 -#define EC_VD_REG_REQ_SMB_CNT__W 16 -#define EC_VD_REG_REQ_SMB_CNT__M 0xFFFF -#define EC_VD_REG_REQ_SMB_CNT_INIT 0x0 - -#define EC_VD_REG_REQ_BIT_CNT__A 0x2090013 -#define EC_VD_REG_REQ_BIT_CNT__W 16 -#define EC_VD_REG_REQ_BIT_CNT__M 0xFFFF -#define EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF - -#define EC_VD_REG_RLK_ENA__A 0x2090014 -#define EC_VD_REG_RLK_ENA__W 1 -#define EC_VD_REG_RLK_ENA__M 0x1 -#define EC_VD_REG_RLK_ENA_INIT 0x0 -#define EC_VD_REG_RLK_ENA_OFF 0x0 -#define EC_VD_REG_RLK_ENA_ON 0x1 - -#define EC_VD_REG_VAL__A 0x2090015 -#define EC_VD_REG_VAL__W 2 -#define EC_VD_REG_VAL__M 0x3 -#define EC_VD_REG_VAL_INIT 0x0 -#define EC_VD_REG_VAL_CODE 0x1 -#define EC_VD_REG_VAL_CNT 0x2 - -#define EC_VD_REG_GET_CODERATE__A 0x2090016 -#define EC_VD_REG_GET_CODERATE__W 3 -#define EC_VD_REG_GET_CODERATE__M 0x7 -#define EC_VD_REG_GET_CODERATE_INIT 0x0 -#define EC_VD_REG_GET_CODERATE_C1_2 0x0 -#define EC_VD_REG_GET_CODERATE_C2_3 0x1 -#define EC_VD_REG_GET_CODERATE_C3_4 0x2 -#define EC_VD_REG_GET_CODERATE_C5_6 0x3 -#define EC_VD_REG_GET_CODERATE_C7_8 0x4 - -#define EC_VD_REG_ERR_BIT_CNT__A 0x2090017 -#define EC_VD_REG_ERR_BIT_CNT__W 16 -#define EC_VD_REG_ERR_BIT_CNT__M 0xFFFF -#define EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF - -#define EC_VD_REG_IN_BIT_CNT__A 0x2090018 -#define EC_VD_REG_IN_BIT_CNT__W 16 -#define EC_VD_REG_IN_BIT_CNT__M 0xFFFF -#define EC_VD_REG_IN_BIT_CNT_INIT 0x0 - -#define EC_VD_REG_STS__A 0x2090019 -#define EC_VD_REG_STS__W 1 -#define EC_VD_REG_STS__M 0x1 -#define EC_VD_REG_STS_INIT 0x0 -#define EC_VD_REG_STS_NO_LOCK 0x0 -#define EC_VD_REG_STS_IN_LOCK 0x1 - -#define EC_VD_REG_RLK_CNT__A 0x209001A -#define EC_VD_REG_RLK_CNT__W 16 -#define EC_VD_REG_RLK_CNT__M 0xFFFF -#define EC_VD_REG_RLK_CNT_INIT 0x0 - -#define EC_VD_TB0_RAM__A 0x20A0000 - -#define EC_VD_TB1_RAM__A 0x20B0000 - -#define EC_VD_TB2_RAM__A 0x20C0000 - -#define EC_VD_TB3_RAM__A 0x20D0000 - -#define EC_VD_RE_RAM__A 0x2100000 - -#define EC_OD_SID 0x18 - -#define EC_OD_REG_COMM_EXEC__A 0x2110000 -#define EC_OD_REG_COMM_EXEC__W 3 -#define EC_OD_REG_COMM_EXEC__M 0x7 -#define EC_OD_REG_COMM_EXEC_CTL__B 0 -#define EC_OD_REG_COMM_EXEC_CTL__W 3 -#define EC_OD_REG_COMM_EXEC_CTL__M 0x7 -#define EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 -#define EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define EC_OD_REG_COMM_MB__A 0x2110002 -#define EC_OD_REG_COMM_MB__W 3 -#define EC_OD_REG_COMM_MB__M 0x7 -#define EC_OD_REG_COMM_MB_CTR__B 0 -#define EC_OD_REG_COMM_MB_CTR__W 1 -#define EC_OD_REG_COMM_MB_CTR__M 0x1 -#define EC_OD_REG_COMM_MB_CTR_OFF 0x0 -#define EC_OD_REG_COMM_MB_CTR_ON 0x1 -#define EC_OD_REG_COMM_MB_OBS__B 1 -#define EC_OD_REG_COMM_MB_OBS__W 1 -#define EC_OD_REG_COMM_MB_OBS__M 0x2 -#define EC_OD_REG_COMM_MB_OBS_OFF 0x0 -#define EC_OD_REG_COMM_MB_OBS_ON 0x2 - -#define EC_OD_REG_COMM_SERVICE0__A 0x2110003 -#define EC_OD_REG_COMM_SERVICE0__W 10 -#define EC_OD_REG_COMM_SERVICE0__M 0x3FF -#define EC_OD_REG_COMM_SERVICE1__A 0x2110004 -#define EC_OD_REG_COMM_SERVICE1__W 11 -#define EC_OD_REG_COMM_SERVICE1__M 0x7FF - -#define EC_OD_REG_COMM_ACTIVATE__A 0x2110005 -#define EC_OD_REG_COMM_ACTIVATE__W 2 -#define EC_OD_REG_COMM_ACTIVATE__M 0x3 - -#define EC_OD_REG_COMM_COUNT__A 0x2110006 -#define EC_OD_REG_COMM_COUNT__W 16 -#define EC_OD_REG_COMM_COUNT__M 0xFFFF - -#define EC_OD_REG_COMM_INT_STA__A 0x2110007 -#define EC_OD_REG_COMM_INT_STA__W 2 -#define EC_OD_REG_COMM_INT_STA__M 0x3 -#define EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 -#define EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 -#define EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 -#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 -#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 -#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 - -#define EC_OD_REG_COMM_INT_MSK__A 0x2110008 -#define EC_OD_REG_COMM_INT_MSK__W 2 -#define EC_OD_REG_COMM_INT_MSK__M 0x3 -#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 -#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 -#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 -#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 -#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 -#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 - -#define EC_OD_REG_SYNC__A 0x2110010 -#define EC_OD_REG_SYNC__W 12 -#define EC_OD_REG_SYNC__M 0xFFF -#define EC_OD_REG_SYNC_NR_SYNC__B 0 -#define EC_OD_REG_SYNC_NR_SYNC__W 5 -#define EC_OD_REG_SYNC_NR_SYNC__M 0x1F -#define EC_OD_REG_SYNC_IN_SYNC__B 5 -#define EC_OD_REG_SYNC_IN_SYNC__W 4 -#define EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 -#define EC_OD_REG_SYNC_OUT_SYNC__B 9 -#define EC_OD_REG_SYNC_OUT_SYNC__W 3 -#define EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 - -#define EC_OD_REG_NOSYNC__A 0x2110011 -#define EC_OD_REG_NOSYNC__W 8 -#define EC_OD_REG_NOSYNC__M 0xFF - -#define EC_OD_DEINT_RAM__A 0x2120000 - -#define EC_RS_SID 0x19 - -#define EC_RS_REG_COMM_EXEC__A 0x2130000 -#define EC_RS_REG_COMM_EXEC__W 3 -#define EC_RS_REG_COMM_EXEC__M 0x7 -#define EC_RS_REG_COMM_EXEC_CTL__B 0 -#define EC_RS_REG_COMM_EXEC_CTL__W 3 -#define EC_RS_REG_COMM_EXEC_CTL__M 0x7 -#define EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 -#define EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define EC_RS_REG_COMM_STATE__A 0x2130001 -#define EC_RS_REG_COMM_STATE__W 4 -#define EC_RS_REG_COMM_STATE__M 0xF -#define EC_RS_REG_COMM_MB__A 0x2130002 -#define EC_RS_REG_COMM_MB__W 2 -#define EC_RS_REG_COMM_MB__M 0x3 -#define EC_RS_REG_COMM_MB_CTR__B 0 -#define EC_RS_REG_COMM_MB_CTR__W 1 -#define EC_RS_REG_COMM_MB_CTR__M 0x1 -#define EC_RS_REG_COMM_MB_CTR_OFF 0x0 -#define EC_RS_REG_COMM_MB_CTR_ON 0x1 -#define EC_RS_REG_COMM_MB_OBS__B 1 -#define EC_RS_REG_COMM_MB_OBS__W 1 -#define EC_RS_REG_COMM_MB_OBS__M 0x2 -#define EC_RS_REG_COMM_MB_OBS_OFF 0x0 -#define EC_RS_REG_COMM_MB_OBS_ON 0x2 - -#define EC_RS_REG_COMM_SERVICE0__A 0x2130003 -#define EC_RS_REG_COMM_SERVICE0__W 16 -#define EC_RS_REG_COMM_SERVICE0__M 0xFFFF -#define EC_RS_REG_COMM_SERVICE1__A 0x2130004 -#define EC_RS_REG_COMM_SERVICE1__W 16 -#define EC_RS_REG_COMM_SERVICE1__M 0xFFFF -#define EC_RS_REG_COMM_INT_STA__A 0x2130007 -#define EC_RS_REG_COMM_INT_STA__W 1 -#define EC_RS_REG_COMM_INT_STA__M 0x1 -#define EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 -#define EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 -#define EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 - -#define EC_RS_REG_COMM_INT_MSK__A 0x2130008 -#define EC_RS_REG_COMM_INT_MSK__W 1 -#define EC_RS_REG_COMM_INT_MSK__M 0x1 -#define EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 -#define EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 -#define EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 - -#define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 -#define EC_RS_REG_REQ_PCK_CNT__W 16 -#define EC_RS_REG_REQ_PCK_CNT__M 0xFFFF -#define EC_RS_REG_REQ_PCK_CNT_INIT 0xFF - -#define EC_RS_REG_VAL__A 0x2130011 -#define EC_RS_REG_VAL__W 1 -#define EC_RS_REG_VAL__M 0x1 -#define EC_RS_REG_VAL_INIT 0x0 -#define EC_RS_REG_VAL_PCK 0x1 - -#define EC_RS_REG_ERR_PCK_CNT__A 0x2130012 -#define EC_RS_REG_ERR_PCK_CNT__W 16 -#define EC_RS_REG_ERR_PCK_CNT__M 0xFFFF -#define EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF - -#define EC_RS_REG_ERR_SMB_CNT__A 0x2130013 -#define EC_RS_REG_ERR_SMB_CNT__W 16 -#define EC_RS_REG_ERR_SMB_CNT__M 0xFFFF -#define EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF - -#define EC_RS_REG_ERR_BIT_CNT__A 0x2130014 -#define EC_RS_REG_ERR_BIT_CNT__W 16 -#define EC_RS_REG_ERR_BIT_CNT__M 0xFFFF -#define EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF - -#define EC_RS_REG_IN_PCK_CNT__A 0x2130015 -#define EC_RS_REG_IN_PCK_CNT__W 16 -#define EC_RS_REG_IN_PCK_CNT__M 0xFFFF -#define EC_RS_REG_IN_PCK_CNT_INIT 0x0 - -#define EC_RS_EC_RAM__A 0x2140000 - -#define EC_OC_SID 0x1A - -#define EC_OC_REG_COMM_EXEC__A 0x2150000 -#define EC_OC_REG_COMM_EXEC__W 3 -#define EC_OC_REG_COMM_EXEC__M 0x7 -#define EC_OC_REG_COMM_EXEC_CTL__B 0 -#define EC_OC_REG_COMM_EXEC_CTL__W 3 -#define EC_OC_REG_COMM_EXEC_CTL__M 0x7 -#define EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 -#define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 -#define EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 - -#define EC_OC_REG_COMM_STATE__A 0x2150001 -#define EC_OC_REG_COMM_STATE__W 4 -#define EC_OC_REG_COMM_STATE__M 0xF - -#define EC_OC_REG_COMM_MB__A 0x2150002 -#define EC_OC_REG_COMM_MB__W 2 -#define EC_OC_REG_COMM_MB__M 0x3 -#define EC_OC_REG_COMM_MB_CTR__B 0 -#define EC_OC_REG_COMM_MB_CTR__W 1 -#define EC_OC_REG_COMM_MB_CTR__M 0x1 -#define EC_OC_REG_COMM_MB_CTR_OFF 0x0 -#define EC_OC_REG_COMM_MB_CTR_ON 0x1 -#define EC_OC_REG_COMM_MB_OBS__B 1 -#define EC_OC_REG_COMM_MB_OBS__W 1 -#define EC_OC_REG_COMM_MB_OBS__M 0x2 -#define EC_OC_REG_COMM_MB_OBS_OFF 0x0 -#define EC_OC_REG_COMM_MB_OBS_ON 0x2 - -#define EC_OC_REG_COMM_SERVICE0__A 0x2150003 -#define EC_OC_REG_COMM_SERVICE0__W 10 -#define EC_OC_REG_COMM_SERVICE0__M 0x3FF - -#define EC_OC_REG_COMM_SERVICE1__A 0x2150004 -#define EC_OC_REG_COMM_SERVICE1__W 11 -#define EC_OC_REG_COMM_SERVICE1__M 0x7FF - -#define EC_OC_REG_COMM_INT_STA__A 0x2150007 -#define EC_OC_REG_COMM_INT_STA__W 6 -#define EC_OC_REG_COMM_INT_STA__M 0x3F -#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 -#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 -#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 -#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 -#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 -#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 -#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 -#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 -#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 -#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 -#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 -#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 -#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 -#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 -#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 -#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 -#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 -#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 - -#define EC_OC_REG_COMM_INT_MSK__A 0x2150008 -#define EC_OC_REG_COMM_INT_MSK__W 6 -#define EC_OC_REG_COMM_INT_MSK__M 0x3F -#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 -#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 -#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 -#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 -#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 -#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 -#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 -#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 -#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 -#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 -#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 -#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 -#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 -#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 -#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 -#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 -#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 -#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 - -#define EC_OC_REG_OC_MODE_LOP__A 0x2150010 -#define EC_OC_REG_OC_MODE_LOP__W 16 -#define EC_OC_REG_OC_MODE_LOP__M 0xFFFF -#define EC_OC_REG_OC_MODE_LOP_INIT 0x0 - -#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 -#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 -#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 -#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 - -#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 -#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 -#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 -#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 -#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 - -#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 -#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 -#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 -#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 - -#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 -#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 -#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 -#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 - -#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 -#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 -#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 - -#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 -#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 -#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 - -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 - -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 - -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 - -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 - -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 - -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 - -#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 -#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 -#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 - -#define EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 -#define EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 -#define EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 -#define EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 - -#define EC_OC_REG_OC_MODE_HIP__A 0x2150011 -#define EC_OC_REG_OC_MODE_HIP__W 14 -#define EC_OC_REG_OC_MODE_HIP__M 0x3FFF -#define EC_OC_REG_OC_MODE_HIP_INIT 0x0 - -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 - -#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 -#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 - -#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 -#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 -#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 -#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 - -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 - -#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 -#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 -#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 - -#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 -#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 -#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 -#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 - -#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 -#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 -#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 -#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 - -#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 -#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 -#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 - -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 - -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 - -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 - -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 - -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 - -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 - -#define EC_OC_REG_OC_MPG_SIO__A 0x2150012 -#define EC_OC_REG_OC_MPG_SIO__W 12 -#define EC_OC_REG_OC_MPG_SIO__M 0xFFF -#define EC_OC_REG_OC_MPG_SIO_INIT 0xFFF - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 - -#define EC_OC_REG_OC_MON_SIO__A 0x2150013 -#define EC_OC_REG_OC_MON_SIO__W 12 -#define EC_OC_REG_OC_MON_SIO__M 0xFFF -#define EC_OC_REG_OC_MON_SIO_INIT 0xFFF - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__B 0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__M 0x1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_0_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_0_INPUT 0x1 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__B 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__M 0x2 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_1_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_1_INPUT 0x2 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__B 2 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__M 0x4 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_2_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_2_INPUT 0x4 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__B 3 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__M 0x8 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_3_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_3_INPUT 0x8 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__B 4 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__M 0x10 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_4_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_4_INPUT 0x10 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__B 5 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__M 0x20 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_5_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_5_INPUT 0x20 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__B 6 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__M 0x40 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_6_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_6_INPUT 0x40 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__B 7 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__M 0x80 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_7_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_7_INPUT 0x80 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__B 8 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__M 0x100 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_8_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_8_INPUT 0x100 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__B 9 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__M 0x200 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_9_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_9_INPUT 0x200 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__B 10 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__M 0x400 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_10_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_10_INPUT 0x400 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__B 11 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__M 0x800 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_INPUT 0x800 - -#define EC_OC_REG_DTO_INC_LOP__A 0x2150014 -#define EC_OC_REG_DTO_INC_LOP__W 16 -#define EC_OC_REG_DTO_INC_LOP__M 0xFFFF -#define EC_OC_REG_DTO_INC_LOP_INIT 0x0 - -#define EC_OC_REG_DTO_INC_HIP__A 0x2150015 -#define EC_OC_REG_DTO_INC_HIP__W 8 -#define EC_OC_REG_DTO_INC_HIP__M 0xFF -#define EC_OC_REG_DTO_INC_HIP_INIT 0x0 - -#define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 -#define EC_OC_REG_SNC_ISC_LVL__W 12 -#define EC_OC_REG_SNC_ISC_LVL__M 0xFFF -#define EC_OC_REG_SNC_ISC_LVL_INIT 0x0 - -#define EC_OC_REG_SNC_ISC_LVL_ISC__B 0 -#define EC_OC_REG_SNC_ISC_LVL_ISC__W 4 -#define EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF - -#define EC_OC_REG_SNC_ISC_LVL_OSC__B 4 -#define EC_OC_REG_SNC_ISC_LVL_OSC__W 4 -#define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 - -#define EC_OC_REG_SNC_ISC_LVL_NSC__B 8 -#define EC_OC_REG_SNC_ISC_LVL_NSC__W 4 -#define EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 - -#define EC_OC_REG_SNC_NSC_LVL__A 0x2150017 -#define EC_OC_REG_SNC_NSC_LVL__W 8 -#define EC_OC_REG_SNC_NSC_LVL__M 0xFF -#define EC_OC_REG_SNC_NSC_LVL_INIT 0x0 - -#define EC_OC_REG_SNC_SNC_MODE__A 0x2150019 -#define EC_OC_REG_SNC_SNC_MODE__W 2 -#define EC_OC_REG_SNC_SNC_MODE__M 0x3 -#define EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 -#define EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 -#define EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 - -#define EC_OC_REG_SNC_PCK_NMB__A 0x215001A -#define EC_OC_REG_SNC_PCK_NMB__W 16 -#define EC_OC_REG_SNC_PCK_NMB__M 0xFFFF - -#define EC_OC_REG_SNC_PCK_CNT__A 0x215001B -#define EC_OC_REG_SNC_PCK_CNT__W 16 -#define EC_OC_REG_SNC_PCK_CNT__M 0xFFFF - -#define EC_OC_REG_SNC_PCK_ERR__A 0x215001C -#define EC_OC_REG_SNC_PCK_ERR__W 16 -#define EC_OC_REG_SNC_PCK_ERR__M 0xFFFF - -#define EC_OC_REG_TMD_TOP_MODE__A 0x215001D -#define EC_OC_REG_TMD_TOP_MODE__W 2 -#define EC_OC_REG_TMD_TOP_MODE__M 0x3 -#define EC_OC_REG_TMD_TOP_MODE_INIT 0x0 -#define EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 -#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 -#define EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 -#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 - -#define EC_OC_REG_TMD_TOP_CNT__A 0x215001E -#define EC_OC_REG_TMD_TOP_CNT__W 10 -#define EC_OC_REG_TMD_TOP_CNT__M 0x3FF -#define EC_OC_REG_TMD_TOP_CNT_INIT 0x0 - -#define EC_OC_REG_TMD_HIL_MAR__A 0x215001F -#define EC_OC_REG_TMD_HIL_MAR__W 10 -#define EC_OC_REG_TMD_HIL_MAR__M 0x3FF -#define EC_OC_REG_TMD_HIL_MAR_INIT 0x0 - -#define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 -#define EC_OC_REG_TMD_LOL_MAR__W 10 -#define EC_OC_REG_TMD_LOL_MAR__M 0x3FF -#define EC_OC_REG_TMD_LOL_MAR_INIT 0x0 - -#define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 -#define EC_OC_REG_TMD_CUR_CNT__W 4 -#define EC_OC_REG_TMD_CUR_CNT__M 0xF -#define EC_OC_REG_TMD_CUR_CNT_INIT 0x0 - -#define EC_OC_REG_TMD_IUR_CNT__A 0x2150022 -#define EC_OC_REG_TMD_IUR_CNT__W 4 -#define EC_OC_REG_TMD_IUR_CNT__M 0xF -#define EC_OC_REG_TMD_IUR_CNT_INIT 0x0 - -#define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 -#define EC_OC_REG_AVR_ASH_CNT__W 4 -#define EC_OC_REG_AVR_ASH_CNT__M 0xF -#define EC_OC_REG_AVR_ASH_CNT_INIT 0x0 - -#define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 -#define EC_OC_REG_AVR_BSH_CNT__W 4 -#define EC_OC_REG_AVR_BSH_CNT__M 0xF -#define EC_OC_REG_AVR_BSH_CNT_INIT 0x0 - -#define EC_OC_REG_AVR_AVE_LOP__A 0x2150025 -#define EC_OC_REG_AVR_AVE_LOP__W 16 -#define EC_OC_REG_AVR_AVE_LOP__M 0xFFFF - -#define EC_OC_REG_AVR_AVE_HIP__A 0x2150026 -#define EC_OC_REG_AVR_AVE_HIP__W 5 -#define EC_OC_REG_AVR_AVE_HIP__M 0x1F - -#define EC_OC_REG_RCN_MODE__A 0x2150027 -#define EC_OC_REG_RCN_MODE__W 3 -#define EC_OC_REG_RCN_MODE__M 0x7 -#define EC_OC_REG_RCN_MODE_INIT 0x0 - -#define EC_OC_REG_RCN_MODE_MODE_0__B 0 -#define EC_OC_REG_RCN_MODE_MODE_0__W 1 -#define EC_OC_REG_RCN_MODE_MODE_0__M 0x1 -#define EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 -#define EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 - -#define EC_OC_REG_RCN_MODE_MODE_1__B 1 -#define EC_OC_REG_RCN_MODE_MODE_1__W 1 -#define EC_OC_REG_RCN_MODE_MODE_1__M 0x2 -#define EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 -#define EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 - -#define EC_OC_REG_RCN_MODE_MODE_2__B 2 -#define EC_OC_REG_RCN_MODE_MODE_2__W 1 -#define EC_OC_REG_RCN_MODE_MODE_2__M 0x4 -#define EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 -#define EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 - -#define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 -#define EC_OC_REG_RCN_CRA_LOP__W 16 -#define EC_OC_REG_RCN_CRA_LOP__M 0xFFFF -#define EC_OC_REG_RCN_CRA_LOP_INIT 0x0 - -#define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 -#define EC_OC_REG_RCN_CRA_HIP__W 8 -#define EC_OC_REG_RCN_CRA_HIP__M 0xFF -#define EC_OC_REG_RCN_CRA_HIP_INIT 0x0 - -#define EC_OC_REG_RCN_CST_LOP__A 0x215002A -#define EC_OC_REG_RCN_CST_LOP__W 16 -#define EC_OC_REG_RCN_CST_LOP__M 0xFFFF -#define EC_OC_REG_RCN_CST_LOP_INIT 0x0 - -#define EC_OC_REG_RCN_CST_HIP__A 0x215002B -#define EC_OC_REG_RCN_CST_HIP__W 8 -#define EC_OC_REG_RCN_CST_HIP__M 0xFF -#define EC_OC_REG_RCN_CST_HIP_INIT 0x0 - -#define EC_OC_REG_RCN_SET_LVL__A 0x215002C -#define EC_OC_REG_RCN_SET_LVL__W 9 -#define EC_OC_REG_RCN_SET_LVL__M 0x1FF -#define EC_OC_REG_RCN_SET_LVL_INIT 0x0 - -#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D -#define EC_OC_REG_RCN_GAI_LVL__W 4 -#define EC_OC_REG_RCN_GAI_LVL__M 0xF -#define EC_OC_REG_RCN_GAI_LVL_INIT 0x0 - -#define EC_OC_REG_RCN_DRA_LOP__A 0x215002E -#define EC_OC_REG_RCN_DRA_LOP__W 16 -#define EC_OC_REG_RCN_DRA_LOP__M 0xFFFF - -#define EC_OC_REG_RCN_DRA_HIP__A 0x215002F -#define EC_OC_REG_RCN_DRA_HIP__W 8 -#define EC_OC_REG_RCN_DRA_HIP__M 0xFF - -#define EC_OC_REG_RCN_DOF_LOP__A 0x2150030 -#define EC_OC_REG_RCN_DOF_LOP__W 16 -#define EC_OC_REG_RCN_DOF_LOP__M 0xFFFF - -#define EC_OC_REG_RCN_DOF_HIP__A 0x2150031 -#define EC_OC_REG_RCN_DOF_HIP__W 8 -#define EC_OC_REG_RCN_DOF_HIP__M 0xFF - -#define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 -#define EC_OC_REG_RCN_CLP_LOP__W 16 -#define EC_OC_REG_RCN_CLP_LOP__M 0xFFFF -#define EC_OC_REG_RCN_CLP_LOP_INIT 0xFFFF - -#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 -#define EC_OC_REG_RCN_CLP_HIP__W 8 -#define EC_OC_REG_RCN_CLP_HIP__M 0xFF -#define EC_OC_REG_RCN_CLP_HIP_INIT 0xFF - -#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 -#define EC_OC_REG_RCN_MAP_LOP__W 16 -#define EC_OC_REG_RCN_MAP_LOP__M 0xFFFF - -#define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 -#define EC_OC_REG_RCN_MAP_HIP__W 8 -#define EC_OC_REG_RCN_MAP_HIP__M 0xFF - -#define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 -#define EC_OC_REG_OCR_MPG_UOS__W 12 -#define EC_OC_REG_OCR_MPG_UOS__M 0xFFF -#define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 -#define EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 -#define EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 -#define EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 -#define EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 -#define EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 -#define EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 -#define EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 -#define EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 -#define EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 -#define EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 -#define EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 -#define EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 -#define EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 - -#define EC_OC_REG_OCR_MPG_UOS_ERR__B 8 -#define EC_OC_REG_OCR_MPG_UOS_ERR__W 1 -#define EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 -#define EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 - -#define EC_OC_REG_OCR_MPG_UOS_STR__B 9 -#define EC_OC_REG_OCR_MPG_UOS_STR__W 1 -#define EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 -#define EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 - -#define EC_OC_REG_OCR_MPG_UOS_VAL__B 10 -#define EC_OC_REG_OCR_MPG_UOS_VAL__W 1 -#define EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 -#define EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 - -#define EC_OC_REG_OCR_MPG_UOS_CLK__B 11 -#define EC_OC_REG_OCR_MPG_UOS_CLK__W 1 -#define EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 -#define EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 - -#define EC_OC_REG_OCR_MPG_WRI__A 0x2150037 -#define EC_OC_REG_OCR_MPG_WRI__W 12 -#define EC_OC_REG_OCR_MPG_WRI__M 0xFFF -#define EC_OC_REG_OCR_MPG_WRI_INIT 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 -#define EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 -#define EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 -#define EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 -#define EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 -#define EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 -#define EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 -#define EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 -#define EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 -#define EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 -#define EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 -#define EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 -#define EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 -#define EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 -#define EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 -#define EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 -#define EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 -#define EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 -#define EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 -#define EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 -#define EC_OC_REG_OCR_MPG_WRI_ERR__B 8 -#define EC_OC_REG_OCR_MPG_WRI_ERR__W 1 -#define EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 -#define EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 -#define EC_OC_REG_OCR_MPG_WRI_STR__B 9 -#define EC_OC_REG_OCR_MPG_WRI_STR__W 1 -#define EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 -#define EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 -#define EC_OC_REG_OCR_MPG_WRI_VAL__B 10 -#define EC_OC_REG_OCR_MPG_WRI_VAL__W 1 -#define EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 -#define EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 -#define EC_OC_REG_OCR_MPG_WRI_CLK__B 11 -#define EC_OC_REG_OCR_MPG_WRI_CLK__W 1 -#define EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 -#define EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 - -#define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 -#define EC_OC_REG_OCR_MPG_USR_DAT__W 12 -#define EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF - -#define EC_OC_REG_OCR_MON_UOS__A 0x2150039 -#define EC_OC_REG_OCR_MON_UOS__W 12 -#define EC_OC_REG_OCR_MON_UOS__M 0xFFF -#define EC_OC_REG_OCR_MON_UOS_INIT 0x0 - -#define EC_OC_REG_OCR_MON_UOS_DAT_0__B 0 -#define EC_OC_REG_OCR_MON_UOS_DAT_0__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_0__M 0x1 -#define EC_OC_REG_OCR_MON_UOS_DAT_0_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1 - -#define EC_OC_REG_OCR_MON_UOS_DAT_1__B 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_1__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_1__M 0x2 -#define EC_OC_REG_OCR_MON_UOS_DAT_1_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2 - -#define EC_OC_REG_OCR_MON_UOS_DAT_2__B 2 -#define EC_OC_REG_OCR_MON_UOS_DAT_2__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_2__M 0x4 -#define EC_OC_REG_OCR_MON_UOS_DAT_2_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4 - -#define EC_OC_REG_OCR_MON_UOS_DAT_3__B 3 -#define EC_OC_REG_OCR_MON_UOS_DAT_3__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_3__M 0x8 -#define EC_OC_REG_OCR_MON_UOS_DAT_3_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8 - -#define EC_OC_REG_OCR_MON_UOS_DAT_4__B 4 -#define EC_OC_REG_OCR_MON_UOS_DAT_4__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_4__M 0x10 -#define EC_OC_REG_OCR_MON_UOS_DAT_4_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10 - -#define EC_OC_REG_OCR_MON_UOS_DAT_5__B 5 -#define EC_OC_REG_OCR_MON_UOS_DAT_5__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_5__M 0x20 -#define EC_OC_REG_OCR_MON_UOS_DAT_5_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20 - -#define EC_OC_REG_OCR_MON_UOS_DAT_6__B 6 -#define EC_OC_REG_OCR_MON_UOS_DAT_6__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_6__M 0x40 -#define EC_OC_REG_OCR_MON_UOS_DAT_6_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40 - -#define EC_OC_REG_OCR_MON_UOS_DAT_7__B 7 -#define EC_OC_REG_OCR_MON_UOS_DAT_7__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_7__M 0x80 -#define EC_OC_REG_OCR_MON_UOS_DAT_7_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80 - -#define EC_OC_REG_OCR_MON_UOS_DAT_8__B 8 -#define EC_OC_REG_OCR_MON_UOS_DAT_8__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_8__M 0x100 -#define EC_OC_REG_OCR_MON_UOS_DAT_8_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100 - -#define EC_OC_REG_OCR_MON_UOS_DAT_9__B 9 -#define EC_OC_REG_OCR_MON_UOS_DAT_9__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_9__M 0x200 -#define EC_OC_REG_OCR_MON_UOS_DAT_9_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200 - -#define EC_OC_REG_OCR_MON_UOS_VAL__B 10 -#define EC_OC_REG_OCR_MON_UOS_VAL__W 1 -#define EC_OC_REG_OCR_MON_UOS_VAL__M 0x400 -#define EC_OC_REG_OCR_MON_UOS_VAL_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400 - -#define EC_OC_REG_OCR_MON_UOS_CLK__B 11 -#define EC_OC_REG_OCR_MON_UOS_CLK__W 1 -#define EC_OC_REG_OCR_MON_UOS_CLK__M 0x800 -#define EC_OC_REG_OCR_MON_UOS_CLK_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 - -#define EC_OC_REG_OCR_MON_WRI__A 0x215003A -#define EC_OC_REG_OCR_MON_WRI__W 12 -#define EC_OC_REG_OCR_MON_WRI__M 0xFFF -#define EC_OC_REG_OCR_MON_WRI_INIT 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_0__B 0 -#define EC_OC_REG_OCR_MON_WRI_DAT_0__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_0__M 0x1 -#define EC_OC_REG_OCR_MON_WRI_DAT_0_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_0_ENABLE 0x1 -#define EC_OC_REG_OCR_MON_WRI_DAT_1__B 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_1__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_1__M 0x2 -#define EC_OC_REG_OCR_MON_WRI_DAT_1_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_1_ENABLE 0x2 -#define EC_OC_REG_OCR_MON_WRI_DAT_2__B 2 -#define EC_OC_REG_OCR_MON_WRI_DAT_2__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_2__M 0x4 -#define EC_OC_REG_OCR_MON_WRI_DAT_2_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_2_ENABLE 0x4 -#define EC_OC_REG_OCR_MON_WRI_DAT_3__B 3 -#define EC_OC_REG_OCR_MON_WRI_DAT_3__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_3__M 0x8 -#define EC_OC_REG_OCR_MON_WRI_DAT_3_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_3_ENABLE 0x8 -#define EC_OC_REG_OCR_MON_WRI_DAT_4__B 4 -#define EC_OC_REG_OCR_MON_WRI_DAT_4__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_4__M 0x10 -#define EC_OC_REG_OCR_MON_WRI_DAT_4_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_4_ENABLE 0x10 -#define EC_OC_REG_OCR_MON_WRI_DAT_5__B 5 -#define EC_OC_REG_OCR_MON_WRI_DAT_5__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_5__M 0x20 -#define EC_OC_REG_OCR_MON_WRI_DAT_5_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_5_ENABLE 0x20 -#define EC_OC_REG_OCR_MON_WRI_DAT_6__B 6 -#define EC_OC_REG_OCR_MON_WRI_DAT_6__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_6__M 0x40 -#define EC_OC_REG_OCR_MON_WRI_DAT_6_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_6_ENABLE 0x40 -#define EC_OC_REG_OCR_MON_WRI_DAT_7__B 7 -#define EC_OC_REG_OCR_MON_WRI_DAT_7__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_7__M 0x80 -#define EC_OC_REG_OCR_MON_WRI_DAT_7_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_7_ENABLE 0x80 -#define EC_OC_REG_OCR_MON_WRI_DAT_8__B 8 -#define EC_OC_REG_OCR_MON_WRI_DAT_8__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_8__M 0x100 -#define EC_OC_REG_OCR_MON_WRI_DAT_8_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_8_ENABLE 0x100 -#define EC_OC_REG_OCR_MON_WRI_DAT_9__B 9 -#define EC_OC_REG_OCR_MON_WRI_DAT_9__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_9__M 0x200 -#define EC_OC_REG_OCR_MON_WRI_DAT_9_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_9_ENABLE 0x200 -#define EC_OC_REG_OCR_MON_WRI_VAL__B 10 -#define EC_OC_REG_OCR_MON_WRI_VAL__W 1 -#define EC_OC_REG_OCR_MON_WRI_VAL__M 0x400 -#define EC_OC_REG_OCR_MON_WRI_VAL_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_VAL_ENABLE 0x400 -#define EC_OC_REG_OCR_MON_WRI_CLK__B 11 -#define EC_OC_REG_OCR_MON_WRI_CLK__W 1 -#define EC_OC_REG_OCR_MON_WRI_CLK__M 0x800 -#define EC_OC_REG_OCR_MON_WRI_CLK_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_CLK_ENABLE 0x800 - -#define EC_OC_REG_OCR_MON_USR_DAT__A 0x215003B -#define EC_OC_REG_OCR_MON_USR_DAT__W 12 -#define EC_OC_REG_OCR_MON_USR_DAT__M 0xFFF - -#define EC_OC_REG_OCR_MON_CNT__A 0x215003C -#define EC_OC_REG_OCR_MON_CNT__W 14 -#define EC_OC_REG_OCR_MON_CNT__M 0x3FFF -#define EC_OC_REG_OCR_MON_CNT_INIT 0x0 - -#define EC_OC_REG_OCR_MON_RDX__A 0x215003D -#define EC_OC_REG_OCR_MON_RDX__W 1 -#define EC_OC_REG_OCR_MON_RDX__M 0x1 -#define EC_OC_REG_OCR_MON_RDX_INIT 0x0 - -#define EC_OC_REG_OCR_MON_RD0__A 0x215003E -#define EC_OC_REG_OCR_MON_RD0__W 10 -#define EC_OC_REG_OCR_MON_RD0__M 0x3FF - -#define EC_OC_REG_OCR_MON_RD1__A 0x215003F -#define EC_OC_REG_OCR_MON_RD1__W 10 -#define EC_OC_REG_OCR_MON_RD1__M 0x3FF - -#define EC_OC_REG_OCR_MON_RD2__A 0x2150040 -#define EC_OC_REG_OCR_MON_RD2__W 10 -#define EC_OC_REG_OCR_MON_RD2__M 0x3FF - -#define EC_OC_REG_OCR_MON_RD3__A 0x2150041 -#define EC_OC_REG_OCR_MON_RD3__W 10 -#define EC_OC_REG_OCR_MON_RD3__M 0x3FF - -#define EC_OC_REG_OCR_MON_RD4__A 0x2150042 -#define EC_OC_REG_OCR_MON_RD4__W 10 -#define EC_OC_REG_OCR_MON_RD4__M 0x3FF - -#define EC_OC_REG_OCR_MON_RD5__A 0x2150043 -#define EC_OC_REG_OCR_MON_RD5__W 10 -#define EC_OC_REG_OCR_MON_RD5__M 0x3FF - -#define EC_OC_REG_OCR_INV_MON__A 0x2150044 -#define EC_OC_REG_OCR_INV_MON__W 12 -#define EC_OC_REG_OCR_INV_MON__M 0xFFF -#define EC_OC_REG_OCR_INV_MON_INIT 0x0 - -#define EC_OC_REG_IPR_INV_MPG__A 0x2150045 -#define EC_OC_REG_IPR_INV_MPG__W 12 -#define EC_OC_REG_IPR_INV_MPG__M 0xFFF -#define EC_OC_REG_IPR_INV_MPG_INIT 0x0 - -#define EC_OC_REG_IPR_MSR_SNC__A 0x2150046 -#define EC_OC_REG_IPR_MSR_SNC__W 6 -#define EC_OC_REG_IPR_MSR_SNC__M 0x3F -#define EC_OC_REG_IPR_MSR_SNC_INIT 0x0 - -#define EC_OC_RAM__A 0x2160000 - -#define CC_SID 0x1B - -#define CC_COMM_EXEC__A 0x2400000 -#define CC_COMM_EXEC__W 3 -#define CC_COMM_EXEC__M 0x7 -#define CC_COMM_EXEC_CTL__B 0 -#define CC_COMM_EXEC_CTL__W 3 -#define CC_COMM_EXEC_CTL__M 0x7 -#define CC_COMM_EXEC_CTL_STOP 0x0 -#define CC_COMM_EXEC_CTL_ACTIVE 0x1 -#define CC_COMM_EXEC_CTL_HOLD 0x2 -#define CC_COMM_EXEC_CTL_STEP 0x3 -#define CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define CC_COMM_STATE__A 0x2400001 -#define CC_COMM_STATE__W 16 -#define CC_COMM_STATE__M 0xFFFF -#define CC_COMM_MB__A 0x2400002 -#define CC_COMM_MB__W 16 -#define CC_COMM_MB__M 0xFFFF -#define CC_COMM_SERVICE0__A 0x2400003 -#define CC_COMM_SERVICE0__W 16 -#define CC_COMM_SERVICE0__M 0xFFFF -#define CC_COMM_SERVICE1__A 0x2400004 -#define CC_COMM_SERVICE1__W 16 -#define CC_COMM_SERVICE1__M 0xFFFF -#define CC_COMM_INT_STA__A 0x2400007 -#define CC_COMM_INT_STA__W 16 -#define CC_COMM_INT_STA__M 0xFFFF -#define CC_COMM_INT_MSK__A 0x2400008 -#define CC_COMM_INT_MSK__W 16 -#define CC_COMM_INT_MSK__M 0xFFFF - -#define CC_REG_COMM_EXEC__A 0x2410000 -#define CC_REG_COMM_EXEC__W 3 -#define CC_REG_COMM_EXEC__M 0x7 -#define CC_REG_COMM_EXEC_CTL__B 0 -#define CC_REG_COMM_EXEC_CTL__W 3 -#define CC_REG_COMM_EXEC_CTL__M 0x7 -#define CC_REG_COMM_EXEC_CTL_STOP 0x0 -#define CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define CC_REG_COMM_EXEC_CTL_HOLD 0x2 -#define CC_REG_COMM_EXEC_CTL_STEP 0x3 -#define CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define CC_REG_COMM_STATE__A 0x2410001 -#define CC_REG_COMM_STATE__W 16 -#define CC_REG_COMM_STATE__M 0xFFFF -#define CC_REG_COMM_MB__A 0x2410002 -#define CC_REG_COMM_MB__W 16 -#define CC_REG_COMM_MB__M 0xFFFF -#define CC_REG_COMM_SERVICE0__A 0x2410003 -#define CC_REG_COMM_SERVICE0__W 16 -#define CC_REG_COMM_SERVICE0__M 0xFFFF -#define CC_REG_COMM_SERVICE1__A 0x2410004 -#define CC_REG_COMM_SERVICE1__W 16 -#define CC_REG_COMM_SERVICE1__M 0xFFFF -#define CC_REG_COMM_INT_STA__A 0x2410007 -#define CC_REG_COMM_INT_STA__W 16 -#define CC_REG_COMM_INT_STA__M 0xFFFF -#define CC_REG_COMM_INT_MSK__A 0x2410008 -#define CC_REG_COMM_INT_MSK__W 16 -#define CC_REG_COMM_INT_MSK__M 0xFFFF - -#define CC_REG_OSC_MODE__A 0x2410010 -#define CC_REG_OSC_MODE__W 2 -#define CC_REG_OSC_MODE__M 0x3 -#define CC_REG_OSC_MODE_OHW 0x0 -#define CC_REG_OSC_MODE_M20 0x1 -#define CC_REG_OSC_MODE_M48 0x2 - -#define CC_REG_PLL_MODE__A 0x2410011 -#define CC_REG_PLL_MODE__W 6 -#define CC_REG_PLL_MODE__M 0x3F -#define CC_REG_PLL_MODE_INIT 0xC -#define CC_REG_PLL_MODE_BYPASS__B 0 -#define CC_REG_PLL_MODE_BYPASS__W 2 -#define CC_REG_PLL_MODE_BYPASS__M 0x3 -#define CC_REG_PLL_MODE_BYPASS_OHW 0x0 -#define CC_REG_PLL_MODE_BYPASS_PLL 0x1 -#define CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 -#define CC_REG_PLL_MODE_PUMP__B 2 -#define CC_REG_PLL_MODE_PUMP__W 3 -#define CC_REG_PLL_MODE_PUMP__M 0x1C -#define CC_REG_PLL_MODE_PUMP_OFF 0x0 -#define CC_REG_PLL_MODE_PUMP_CUR_08 0x4 -#define CC_REG_PLL_MODE_PUMP_CUR_09 0x8 -#define CC_REG_PLL_MODE_PUMP_CUR_10 0xC -#define CC_REG_PLL_MODE_PUMP_CUR_11 0x10 -#define CC_REG_PLL_MODE_PUMP_CUR_12 0x14 -#define CC_REG_PLL_MODE_OUT_EN__B 5 -#define CC_REG_PLL_MODE_OUT_EN__W 1 -#define CC_REG_PLL_MODE_OUT_EN__M 0x20 -#define CC_REG_PLL_MODE_OUT_EN_OFF 0x0 -#define CC_REG_PLL_MODE_OUT_EN_ON 0x20 - -#define CC_REG_REF_DIVIDE__A 0x2410012 -#define CC_REG_REF_DIVIDE__W 4 -#define CC_REG_REF_DIVIDE__M 0xF -#define CC_REG_REF_DIVIDE_INIT 0xA -#define CC_REG_REF_DIVIDE_OHW 0x0 -#define CC_REG_REF_DIVIDE_D01 0x1 -#define CC_REG_REF_DIVIDE_D02 0x2 -#define CC_REG_REF_DIVIDE_D03 0x3 -#define CC_REG_REF_DIVIDE_D04 0x4 -#define CC_REG_REF_DIVIDE_D05 0x5 -#define CC_REG_REF_DIVIDE_D06 0x6 -#define CC_REG_REF_DIVIDE_D07 0x7 -#define CC_REG_REF_DIVIDE_D08 0x8 -#define CC_REG_REF_DIVIDE_D09 0x9 -#define CC_REG_REF_DIVIDE_D10 0xA - -#define CC_REG_REF_DELAY__A 0x2410013 -#define CC_REG_REF_DELAY__W 3 -#define CC_REG_REF_DELAY__M 0x7 -#define CC_REG_REF_DELAY_EDGE__B 0 -#define CC_REG_REF_DELAY_EDGE__W 1 -#define CC_REG_REF_DELAY_EDGE__M 0x1 -#define CC_REG_REF_DELAY_EDGE_POS 0x0 -#define CC_REG_REF_DELAY_EDGE_NEG 0x1 -#define CC_REG_REF_DELAY_DELAY__B 1 -#define CC_REG_REF_DELAY_DELAY__W 2 -#define CC_REG_REF_DELAY_DELAY__M 0x6 -#define CC_REG_REF_DELAY_DELAY_DEL_0 0x0 -#define CC_REG_REF_DELAY_DELAY_DEL_3 0x2 -#define CC_REG_REF_DELAY_DELAY_DEL_6 0x4 -#define CC_REG_REF_DELAY_DELAY_DEL_9 0x6 - -#define CC_REG_CLK_DELAY__A 0x2410014 -#define CC_REG_CLK_DELAY__W 4 -#define CC_REG_CLK_DELAY__M 0xF -#define CC_REG_CLK_DELAY_OFF 0x0 - -#define CC_REG_PWD_MODE__A 0x2410015 -#define CC_REG_PWD_MODE__W 2 -#define CC_REG_PWD_MODE__M 0x3 -#define CC_REG_PWD_MODE_UP 0x0 -#define CC_REG_PWD_MODE_DOWN_CLK 0x1 -#define CC_REG_PWD_MODE_DOWN_PLL 0x2 -#define CC_REG_PWD_MODE_DOWN_OSC 0x3 - -#define CC_REG_SOFT_RST__A 0x2410016 -#define CC_REG_SOFT_RST__W 2 -#define CC_REG_SOFT_RST__M 0x3 -#define CC_REG_SOFT_RST_SYS__B 0 -#define CC_REG_SOFT_RST_SYS__W 1 -#define CC_REG_SOFT_RST_SYS__M 0x1 -#define CC_REG_SOFT_RST_OSC__B 1 -#define CC_REG_SOFT_RST_OSC__W 1 -#define CC_REG_SOFT_RST_OSC__M 0x2 - -#define CC_REG_UPDATE__A 0x2410017 -#define CC_REG_UPDATE__W 16 -#define CC_REG_UPDATE__M 0xFFFF -#define CC_REG_UPDATE_KEY 0x3973 - -#define CC_REG_PLL_LOCK__A 0x2410018 -#define CC_REG_PLL_LOCK__W 1 -#define CC_REG_PLL_LOCK__M 0x1 -#define CC_REG_PLL_LOCK_LOCK 0x1 - -#define CC_REG_JTAGID_L__A 0x2410019 -#define CC_REG_JTAGID_L__W 16 -#define CC_REG_JTAGID_L__M 0xFFFF -#define CC_REG_JTAGID_L_INIT 0x0 - -#define CC_REG_JTAGID_H__A 0x241001A -#define CC_REG_JTAGID_H__W 16 -#define CC_REG_JTAGID_H__M 0xFFFF -#define CC_REG_JTAGID_H_INIT 0x0 - -#define LC_SID 0x1C - -#define LC_COMM_EXEC__A 0x2800000 -#define LC_COMM_EXEC__W 3 -#define LC_COMM_EXEC__M 0x7 -#define LC_COMM_EXEC_CTL__B 0 -#define LC_COMM_EXEC_CTL__W 3 -#define LC_COMM_EXEC_CTL__M 0x7 -#define LC_COMM_EXEC_CTL_STOP 0x0 -#define LC_COMM_EXEC_CTL_ACTIVE 0x1 -#define LC_COMM_EXEC_CTL_HOLD 0x2 -#define LC_COMM_EXEC_CTL_STEP 0x3 -#define LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define LC_COMM_STATE__A 0x2800001 -#define LC_COMM_STATE__W 16 -#define LC_COMM_STATE__M 0xFFFF -#define LC_COMM_MB__A 0x2800002 -#define LC_COMM_MB__W 16 -#define LC_COMM_MB__M 0xFFFF -#define LC_COMM_SERVICE0__A 0x2800003 -#define LC_COMM_SERVICE0__W 16 -#define LC_COMM_SERVICE0__M 0xFFFF -#define LC_COMM_SERVICE1__A 0x2800004 -#define LC_COMM_SERVICE1__W 16 -#define LC_COMM_SERVICE1__M 0xFFFF -#define LC_COMM_INT_STA__A 0x2800007 -#define LC_COMM_INT_STA__W 16 -#define LC_COMM_INT_STA__M 0xFFFF -#define LC_COMM_INT_MSK__A 0x2800008 -#define LC_COMM_INT_MSK__W 16 -#define LC_COMM_INT_MSK__M 0xFFFF - -#define LC_CT_REG_COMM_EXEC__A 0x2810000 -#define LC_CT_REG_COMM_EXEC__W 3 -#define LC_CT_REG_COMM_EXEC__M 0x7 -#define LC_CT_REG_COMM_EXEC_CTL__B 0 -#define LC_CT_REG_COMM_EXEC_CTL__W 3 -#define LC_CT_REG_COMM_EXEC_CTL__M 0x7 -#define LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define LC_CT_REG_COMM_STATE__A 0x2810001 -#define LC_CT_REG_COMM_STATE__W 10 -#define LC_CT_REG_COMM_STATE__M 0x3FF -#define LC_CT_REG_COMM_SERVICE0__A 0x2810003 -#define LC_CT_REG_COMM_SERVICE0__W 16 -#define LC_CT_REG_COMM_SERVICE0__M 0xFFFF -#define LC_CT_REG_COMM_SERVICE1__A 0x2810004 -#define LC_CT_REG_COMM_SERVICE1__W 16 -#define LC_CT_REG_COMM_SERVICE1__M 0xFFFF -#define LC_CT_REG_COMM_SERVICE1_LC__B 12 -#define LC_CT_REG_COMM_SERVICE1_LC__W 1 -#define LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 - -#define LC_CT_REG_COMM_INT_STA__A 0x2810007 -#define LC_CT_REG_COMM_INT_STA__W 1 -#define LC_CT_REG_COMM_INT_STA__M 0x1 -#define LC_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define LC_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define LC_CT_REG_COMM_INT_MSK__A 0x2810008 -#define LC_CT_REG_COMM_INT_MSK__W 1 -#define LC_CT_REG_COMM_INT_MSK__M 0x1 -#define LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define LC_CT_REG_CTL_STK__AX 0x2810010 -#define LC_CT_REG_CTL_STK__XSZ 4 -#define LC_CT_REG_CTL_STK__W 10 -#define LC_CT_REG_CTL_STK__M 0x3FF - -#define LC_CT_REG_CTL_BPT_IDX__A 0x281001F -#define LC_CT_REG_CTL_BPT_IDX__W 1 -#define LC_CT_REG_CTL_BPT_IDX__M 0x1 - -#define LC_CT_REG_CTL_BPT__A 0x2810020 -#define LC_CT_REG_CTL_BPT__W 10 -#define LC_CT_REG_CTL_BPT__M 0x3FF - -#define LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 -#define LC_RA_RAM_PROC_DELAY_IF__W 16 -#define LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF -#define LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 -#define LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 -#define LC_RA_RAM_PROC_DELAY_FS__W 16 -#define LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF -#define LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 -#define LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 -#define LC_RA_RAM_LOCK_TH_CRMM__W 16 -#define LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF -#define LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 -#define LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 -#define LC_RA_RAM_LOCK_TH_SRMM__W 16 -#define LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF -#define LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 -#define LC_RA_RAM_LOCK_COUNT__A 0x282000A -#define LC_RA_RAM_LOCK_COUNT__W 16 -#define LC_RA_RAM_LOCK_COUNT__M 0xFFFF -#define LC_RA_RAM_CPRTOFS_NOM__A 0x282000B -#define LC_RA_RAM_CPRTOFS_NOM__W 16 -#define LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF -#define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C -#define LC_RA_RAM_IFINCR_NOM_L__W 16 -#define LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF -#define LC_RA_RAM_IFINCR_NOM_H__A 0x282000D -#define LC_RA_RAM_IFINCR_NOM_H__W 16 -#define LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF -#define LC_RA_RAM_FSINCR_NOM_L__A 0x282000E -#define LC_RA_RAM_FSINCR_NOM_L__W 16 -#define LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF -#define LC_RA_RAM_FSINCR_NOM_H__A 0x282000F -#define LC_RA_RAM_FSINCR_NOM_H__W 16 -#define LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF -#define LC_RA_RAM_MODE_2K__A 0x2820010 -#define LC_RA_RAM_MODE_2K__W 16 -#define LC_RA_RAM_MODE_2K__M 0xFFFF -#define LC_RA_RAM_MODE_GUARD__A 0x2820011 -#define LC_RA_RAM_MODE_GUARD__W 16 -#define LC_RA_RAM_MODE_GUARD__M 0xFFFF -#define LC_RA_RAM_MODE_GUARD_32 0x0 -#define LC_RA_RAM_MODE_GUARD_16 0x1 -#define LC_RA_RAM_MODE_GUARD_8 0x2 -#define LC_RA_RAM_MODE_GUARD_4 0x3 - -#define LC_RA_RAM_MODE_ADJUST__A 0x2820012 -#define LC_RA_RAM_MODE_ADJUST__W 16 -#define LC_RA_RAM_MODE_ADJUST__M 0xFFFF -#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 -#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 -#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 -#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 -#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 -#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 -#define LC_RA_RAM_MODE_ADJUST_SRMM__B 2 -#define LC_RA_RAM_MODE_ADJUST_SRMM__W 1 -#define LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 -#define LC_RA_RAM_MODE_ADJUST_PHASE__B 3 -#define LC_RA_RAM_MODE_ADJUST_PHASE__W 1 -#define LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 -#define LC_RA_RAM_MODE_ADJUST_DELAY__B 4 -#define LC_RA_RAM_MODE_ADJUST_DELAY__W 1 -#define LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 -#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 -#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 -#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 -#define LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 -#define LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 -#define LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 -#define LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 -#define LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 -#define LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 -#define LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 -#define LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 -#define LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 -#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 -#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 -#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 - -#define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A -#define LC_RA_RAM_FILTER_SYM_SET__W 16 -#define LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF -#define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 -#define LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B -#define LC_RA_RAM_FILTER_SYM_CUR__W 16 -#define LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF -#define LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 -#define LC_RA_RAM_MAX_ABS_EXP__A 0x282001D -#define LC_RA_RAM_MAX_ABS_EXP__W 16 -#define LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF -#define LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 -#define LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F -#define LC_RA_RAM_ACTUAL_CP_CRMM__W 16 -#define LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF -#define LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 -#define LC_RA_RAM_ACTUAL_CE_CRMM__W 16 -#define LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF -#define LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 -#define LC_RA_RAM_ACTUAL_CE_SRMM__W 16 -#define LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF -#define LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 -#define LC_RA_RAM_ACTUAL_PHASE__W 16 -#define LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF -#define LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 -#define LC_RA_RAM_ACTUAL_DELAY__W 16 -#define LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF -#define LC_RA_RAM_ADJUST_CRMM__A 0x2820024 -#define LC_RA_RAM_ADJUST_CRMM__W 16 -#define LC_RA_RAM_ADJUST_CRMM__M 0xFFFF -#define LC_RA_RAM_ADJUST_SRMM__A 0x2820025 -#define LC_RA_RAM_ADJUST_SRMM__W 16 -#define LC_RA_RAM_ADJUST_SRMM__M 0xFFFF -#define LC_RA_RAM_ADJUST_PHASE__A 0x2820026 -#define LC_RA_RAM_ADJUST_PHASE__W 16 -#define LC_RA_RAM_ADJUST_PHASE__M 0xFFFF -#define LC_RA_RAM_ADJUST_DELAY__A 0x2820027 -#define LC_RA_RAM_ADJUST_DELAY__W 16 -#define LC_RA_RAM_ADJUST_DELAY__M 0xFFFF - -#define LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 -#define LC_RA_RAM_PIPE_CP_PHASE_0__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 -#define LC_RA_RAM_PIPE_CP_PHASE_1__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A -#define LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B -#define LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C -#define LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D -#define LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF - -#define LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 -#define LC_RA_RAM_PIPE_CP_CRMM_0__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 -#define LC_RA_RAM_PIPE_CP_CRMM_1__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 -#define LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 -#define LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 -#define LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 -#define LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF - -#define LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 -#define LC_RA_RAM_PIPE_CP_SRMM_0__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 -#define LC_RA_RAM_PIPE_CP_SRMM_1__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A -#define LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B -#define LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C -#define LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D -#define LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF - -#define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 -#define LC_RA_RAM_FILTER_CRMM_A__W 16 -#define LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF -#define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 -#define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 -#define LC_RA_RAM_FILTER_CRMM_B__W 16 -#define LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF -#define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 -#define LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 -#define LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 -#define LC_RA_RAM_FILTER_CRMM_Z1__W 16 -#define LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF -#define LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 -#define LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 -#define LC_RA_RAM_FILTER_CRMM_Z2__W 16 -#define LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF -#define LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 -#define LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 -#define LC_RA_RAM_FILTER_CRMM_TMP__W 16 -#define LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF - -#define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 -#define LC_RA_RAM_FILTER_SRMM_A__W 16 -#define LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF -#define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 -#define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 -#define LC_RA_RAM_FILTER_SRMM_B__W 16 -#define LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF -#define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 -#define LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A -#define LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 -#define LC_RA_RAM_FILTER_SRMM_Z1__W 16 -#define LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF -#define LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C -#define LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 -#define LC_RA_RAM_FILTER_SRMM_Z2__W 16 -#define LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF -#define LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E -#define LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 -#define LC_RA_RAM_FILTER_SRMM_TMP__W 16 -#define LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF - -#define LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 -#define LC_RA_RAM_FILTER_PHASE_A__W 16 -#define LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF -#define LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 -#define LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 -#define LC_RA_RAM_FILTER_PHASE_B__W 16 -#define LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF -#define LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 -#define LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 -#define LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 -#define LC_RA_RAM_FILTER_PHASE_Z1__W 16 -#define LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF -#define LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 -#define LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 -#define LC_RA_RAM_FILTER_PHASE_Z2__W 16 -#define LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF -#define LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 -#define LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 -#define LC_RA_RAM_FILTER_PHASE_TMP__W 16 -#define LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF - -#define LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 -#define LC_RA_RAM_FILTER_DELAY_A__W 16 -#define LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF -#define LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 -#define LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 -#define LC_RA_RAM_FILTER_DELAY_B__W 16 -#define LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF -#define LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 -#define LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A -#define LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 -#define LC_RA_RAM_FILTER_DELAY_Z1__W 16 -#define LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF -#define LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C -#define LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 -#define LC_RA_RAM_FILTER_DELAY_Z2__W 16 -#define LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF -#define LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E -#define LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 -#define LC_RA_RAM_FILTER_DELAY_TMP__W 16 -#define LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF - -#define LC_IF_RAM_TRP_BPT0__AX 0x2830000 -#define LC_IF_RAM_TRP_BPT0__XSZ 2 -#define LC_IF_RAM_TRP_BPT0__W 12 -#define LC_IF_RAM_TRP_BPT0__M 0xFFF - -#define LC_IF_RAM_TRP_STKU__AX 0x2830002 -#define LC_IF_RAM_TRP_STKU__XSZ 2 -#define LC_IF_RAM_TRP_STKU__W 12 -#define LC_IF_RAM_TRP_STKU__M 0xFFF - -#define LC_IF_RAM_TRP_WARM__AX 0x2830006 -#define LC_IF_RAM_TRP_WARM__XSZ 2 -#define LC_IF_RAM_TRP_WARM__W 12 -#define LC_IF_RAM_TRP_WARM__M 0xFFF - -#define B_HI_SID 0x10 - -#define B_HI_COMM_EXEC__A 0x400000 -#define B_HI_COMM_EXEC__W 3 -#define B_HI_COMM_EXEC__M 0x7 -#define B_HI_COMM_EXEC_CTL__B 0 -#define B_HI_COMM_EXEC_CTL__W 3 -#define B_HI_COMM_EXEC_CTL__M 0x7 -#define B_HI_COMM_EXEC_CTL_STOP 0x0 -#define B_HI_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_HI_COMM_EXEC_CTL_HOLD 0x2 -#define B_HI_COMM_EXEC_CTL_STEP 0x3 -#define B_HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_HI_COMM_STATE__A 0x400001 -#define B_HI_COMM_STATE__W 16 -#define B_HI_COMM_STATE__M 0xFFFF -#define B_HI_COMM_MB__A 0x400002 -#define B_HI_COMM_MB__W 16 -#define B_HI_COMM_MB__M 0xFFFF -#define B_HI_COMM_SERVICE0__A 0x400003 -#define B_HI_COMM_SERVICE0__W 16 -#define B_HI_COMM_SERVICE0__M 0xFFFF -#define B_HI_COMM_SERVICE1__A 0x400004 -#define B_HI_COMM_SERVICE1__W 16 -#define B_HI_COMM_SERVICE1__M 0xFFFF -#define B_HI_COMM_INT_STA__A 0x400007 -#define B_HI_COMM_INT_STA__W 16 -#define B_HI_COMM_INT_STA__M 0xFFFF -#define B_HI_COMM_INT_MSK__A 0x400008 -#define B_HI_COMM_INT_MSK__W 16 -#define B_HI_COMM_INT_MSK__M 0xFFFF - -#define B_HI_CT_REG_COMM_EXEC__A 0x410000 -#define B_HI_CT_REG_COMM_EXEC__W 3 -#define B_HI_CT_REG_COMM_EXEC__M 0x7 -#define B_HI_CT_REG_COMM_EXEC_CTL__B 0 -#define B_HI_CT_REG_COMM_EXEC_CTL__W 3 -#define B_HI_CT_REG_COMM_EXEC_CTL__M 0x7 -#define B_HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_HI_CT_REG_COMM_STATE__A 0x410001 -#define B_HI_CT_REG_COMM_STATE__W 10 -#define B_HI_CT_REG_COMM_STATE__M 0x3FF -#define B_HI_CT_REG_COMM_SERVICE0__A 0x410003 -#define B_HI_CT_REG_COMM_SERVICE0__W 16 -#define B_HI_CT_REG_COMM_SERVICE0__M 0xFFFF -#define B_HI_CT_REG_COMM_SERVICE1__A 0x410004 -#define B_HI_CT_REG_COMM_SERVICE1__W 16 -#define B_HI_CT_REG_COMM_SERVICE1__M 0xFFFF -#define B_HI_CT_REG_COMM_SERVICE1_HI__B 0 -#define B_HI_CT_REG_COMM_SERVICE1_HI__W 1 -#define B_HI_CT_REG_COMM_SERVICE1_HI__M 0x1 - -#define B_HI_CT_REG_COMM_INT_STA__A 0x410007 -#define B_HI_CT_REG_COMM_INT_STA__W 1 -#define B_HI_CT_REG_COMM_INT_STA__M 0x1 -#define B_HI_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define B_HI_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define B_HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define B_HI_CT_REG_COMM_INT_MSK__A 0x410008 -#define B_HI_CT_REG_COMM_INT_MSK__W 1 -#define B_HI_CT_REG_COMM_INT_MSK__M 0x1 -#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define B_HI_CT_REG_CTL_STK__AX 0x410010 -#define B_HI_CT_REG_CTL_STK__XSZ 4 -#define B_HI_CT_REG_CTL_STK__W 10 -#define B_HI_CT_REG_CTL_STK__M 0x3FF - -#define B_HI_CT_REG_CTL_BPT_IDX__A 0x41001F -#define B_HI_CT_REG_CTL_BPT_IDX__W 1 -#define B_HI_CT_REG_CTL_BPT_IDX__M 0x1 - -#define B_HI_CT_REG_CTL_BPT__A 0x410020 -#define B_HI_CT_REG_CTL_BPT__W 10 -#define B_HI_CT_REG_CTL_BPT__M 0x3FF - -#define B_HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 -#define B_HI_RA_RAM_SLV0_FLG_SMM__W 1 -#define B_HI_RA_RAM_SLV0_FLG_SMM__M 0x1 -#define B_HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 -#define B_HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 - -#define B_HI_RA_RAM_SLV0_DEV_ID__A 0x420011 -#define B_HI_RA_RAM_SLV0_DEV_ID__W 7 -#define B_HI_RA_RAM_SLV0_DEV_ID__M 0x7F - -#define B_HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 -#define B_HI_RA_RAM_SLV0_FLG_CRC__W 1 -#define B_HI_RA_RAM_SLV0_FLG_CRC__M 0x1 -#define B_HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 -#define B_HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 - -#define B_HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 -#define B_HI_RA_RAM_SLV0_FLG_ACC__W 3 -#define B_HI_RA_RAM_SLV0_FLG_ACC__M 0x7 -#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 -#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 -#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 -#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 -#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 -#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 -#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 -#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 -#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 -#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 - -#define B_HI_RA_RAM_SLV0_STATE__A 0x420014 -#define B_HI_RA_RAM_SLV0_STATE__W 1 -#define B_HI_RA_RAM_SLV0_STATE__M 0x1 -#define B_HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 -#define B_HI_RA_RAM_SLV0_STATE_DATA 0x1 - -#define B_HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 -#define B_HI_RA_RAM_SLV0_BLK_BNK__W 12 -#define B_HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF -#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 -#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 -#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F -#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 -#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 -#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 - -#define B_HI_RA_RAM_SLV0_ADDR__A 0x420016 -#define B_HI_RA_RAM_SLV0_ADDR__W 16 -#define B_HI_RA_RAM_SLV0_ADDR__M 0xFFFF - -#define B_HI_RA_RAM_SLV0_CRC__A 0x420017 -#define B_HI_RA_RAM_SLV0_CRC__W 16 -#define B_HI_RA_RAM_SLV0_CRC__M 0xFFFF - -#define B_HI_RA_RAM_SLV0_READBACK__A 0x420018 -#define B_HI_RA_RAM_SLV0_READBACK__W 16 -#define B_HI_RA_RAM_SLV0_READBACK__M 0xFFFF - -#define B_HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 -#define B_HI_RA_RAM_SLV1_FLG_SMM__W 1 -#define B_HI_RA_RAM_SLV1_FLG_SMM__M 0x1 -#define B_HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 -#define B_HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 - -#define B_HI_RA_RAM_SLV1_DEV_ID__A 0x420021 -#define B_HI_RA_RAM_SLV1_DEV_ID__W 7 -#define B_HI_RA_RAM_SLV1_DEV_ID__M 0x7F - -#define B_HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 -#define B_HI_RA_RAM_SLV1_FLG_CRC__W 1 -#define B_HI_RA_RAM_SLV1_FLG_CRC__M 0x1 -#define B_HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 -#define B_HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 - -#define B_HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 -#define B_HI_RA_RAM_SLV1_FLG_ACC__W 3 -#define B_HI_RA_RAM_SLV1_FLG_ACC__M 0x7 -#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 -#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 -#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 -#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 -#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 -#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 -#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 -#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 -#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 -#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 - -#define B_HI_RA_RAM_SLV1_STATE__A 0x420024 -#define B_HI_RA_RAM_SLV1_STATE__W 1 -#define B_HI_RA_RAM_SLV1_STATE__M 0x1 -#define B_HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 -#define B_HI_RA_RAM_SLV1_STATE_DATA 0x1 - -#define B_HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 -#define B_HI_RA_RAM_SLV1_BLK_BNK__W 12 -#define B_HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF -#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 -#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 -#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F -#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 -#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 -#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 - -#define B_HI_RA_RAM_SLV1_ADDR__A 0x420026 -#define B_HI_RA_RAM_SLV1_ADDR__W 16 -#define B_HI_RA_RAM_SLV1_ADDR__M 0xFFFF - -#define B_HI_RA_RAM_SLV1_CRC__A 0x420027 -#define B_HI_RA_RAM_SLV1_CRC__W 16 -#define B_HI_RA_RAM_SLV1_CRC__M 0xFFFF - -#define B_HI_RA_RAM_SLV1_READBACK__A 0x420028 -#define B_HI_RA_RAM_SLV1_READBACK__W 16 -#define B_HI_RA_RAM_SLV1_READBACK__M 0xFFFF - -#define B_HI_RA_RAM_SRV_SEM__A 0x420030 -#define B_HI_RA_RAM_SRV_SEM__W 1 -#define B_HI_RA_RAM_SRV_SEM__M 0x1 -#define B_HI_RA_RAM_SRV_SEM_FREE 0x0 -#define B_HI_RA_RAM_SRV_SEM_CLAIMED 0x1 - -#define B_HI_RA_RAM_SRV_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_RES__W 3 -#define B_HI_RA_RAM_SRV_RES__M 0x7 -#define B_HI_RA_RAM_SRV_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 -#define B_HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 -#define B_HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 -#define B_HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 - -#define B_HI_RA_RAM_SRV_CMD__A 0x420032 -#define B_HI_RA_RAM_SRV_CMD__W 3 -#define B_HI_RA_RAM_SRV_CMD__M 0x7 -#define B_HI_RA_RAM_SRV_CMD_NULL 0x0 -#define B_HI_RA_RAM_SRV_CMD_UIO 0x1 -#define B_HI_RA_RAM_SRV_CMD_RESET 0x2 -#define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3 -#define B_HI_RA_RAM_SRV_CMD_COPY 0x4 -#define B_HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 -#define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 - -#define B_HI_RA_RAM_SRV_PAR__AX 0x420033 -#define B_HI_RA_RAM_SRV_PAR__XSZ 5 -#define B_HI_RA_RAM_SRV_PAR__W 16 -#define B_HI_RA_RAM_SRV_PAR__M 0xFFFF - -#define B_HI_RA_RAM_SRV_NOP_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_NOP_RES__W 3 -#define B_HI_RA_RAM_SRV_NOP_RES__M 0x7 -#define B_HI_RA_RAM_SRV_NOP_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 - -#define B_HI_RA_RAM_SRV_UIO_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_UIO_RES__W 3 -#define B_HI_RA_RAM_SRV_UIO_RES__M 0x7 -#define B_HI_RA_RAM_SRV_UIO_RES_LO 0x0 -#define B_HI_RA_RAM_SRV_UIO_RES_HI 0x1 - -#define B_HI_RA_RAM_SRV_UIO_KEY__A 0x420033 -#define B_HI_RA_RAM_SRV_UIO_KEY__W 16 -#define B_HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF -#define B_HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 - -#define B_HI_RA_RAM_SRV_UIO_SEL__A 0x420034 -#define B_HI_RA_RAM_SRV_UIO_SEL__W 2 -#define B_HI_RA_RAM_SRV_UIO_SEL__M 0x3 -#define B_HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 -#define B_HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 - -#define B_HI_RA_RAM_SRV_UIO_SET__A 0x420035 -#define B_HI_RA_RAM_SRV_UIO_SET__W 2 -#define B_HI_RA_RAM_SRV_UIO_SET__M 0x3 -#define B_HI_RA_RAM_SRV_UIO_SET_OUT__B 0 -#define B_HI_RA_RAM_SRV_UIO_SET_OUT__W 1 -#define B_HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 -#define B_HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 -#define B_HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 -#define B_HI_RA_RAM_SRV_UIO_SET_DIR__B 1 -#define B_HI_RA_RAM_SRV_UIO_SET_DIR__W 1 -#define B_HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 -#define B_HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 -#define B_HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 - -#define B_HI_RA_RAM_SRV_RST_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_RST_RES__W 1 -#define B_HI_RA_RAM_SRV_RST_RES__M 0x1 -#define B_HI_RA_RAM_SRV_RST_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_RST_RES_ERROR 0x1 - -#define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033 -#define B_HI_RA_RAM_SRV_RST_KEY__W 16 -#define B_HI_RA_RAM_SRV_RST_KEY__M 0xFFFF -#define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 - -#define B_HI_RA_RAM_SRV_CFG_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_CFG_RES__W 1 -#define B_HI_RA_RAM_SRV_CFG_RES__M 0x1 -#define B_HI_RA_RAM_SRV_CFG_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 - -#define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033 -#define B_HI_RA_RAM_SRV_CFG_KEY__W 16 -#define B_HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF -#define B_HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 - -#define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 -#define B_HI_RA_RAM_SRV_CFG_DIV__W 5 -#define B_HI_RA_RAM_SRV_CFG_DIV__M 0x1F - -#define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035 -#define B_HI_RA_RAM_SRV_CFG_BDL__W 6 -#define B_HI_RA_RAM_SRV_CFG_BDL__M 0x3F - -#define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036 -#define B_HI_RA_RAM_SRV_CFG_WUP__W 8 -#define B_HI_RA_RAM_SRV_CFG_WUP__M 0xFF - -#define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037 -#define B_HI_RA_RAM_SRV_CFG_ACT__W 4 -#define B_HI_RA_RAM_SRV_CFG_ACT__M 0xF -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 -#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 -#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 -#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 -#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 -#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 -#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 -#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 -#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 -#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 -#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 - -#define B_HI_RA_RAM_SRV_CPY_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_CPY_RES__W 1 -#define B_HI_RA_RAM_SRV_CPY_RES__M 0x1 -#define B_HI_RA_RAM_SRV_CPY_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 - -#define B_HI_RA_RAM_SRV_CPY_SBB__A 0x420033 -#define B_HI_RA_RAM_SRV_CPY_SBB__W 12 -#define B_HI_RA_RAM_SRV_CPY_SBB__M 0xFFF -#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 -#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 -#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F -#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 -#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 -#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 - -#define B_HI_RA_RAM_SRV_CPY_SAD__A 0x420034 -#define B_HI_RA_RAM_SRV_CPY_SAD__W 16 -#define B_HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF - -#define B_HI_RA_RAM_SRV_CPY_LEN__A 0x420035 -#define B_HI_RA_RAM_SRV_CPY_LEN__W 16 -#define B_HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF - -#define B_HI_RA_RAM_SRV_CPY_DBB__A 0x420033 -#define B_HI_RA_RAM_SRV_CPY_DBB__W 12 -#define B_HI_RA_RAM_SRV_CPY_DBB__M 0xFFF -#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 -#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 -#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F -#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 -#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 -#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 - -#define B_HI_RA_RAM_SRV_CPY_DAD__A 0x420034 -#define B_HI_RA_RAM_SRV_CPY_DAD__W 16 -#define B_HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF - -#define B_HI_RA_RAM_SRV_TRM_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_TRM_RES__W 2 -#define B_HI_RA_RAM_SRV_TRM_RES__M 0x3 -#define B_HI_RA_RAM_SRV_TRM_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 -#define B_HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 - -#define B_HI_RA_RAM_SRV_TRM_MST__A 0x420033 -#define B_HI_RA_RAM_SRV_TRM_MST__W 12 -#define B_HI_RA_RAM_SRV_TRM_MST__M 0xFFF - -#define B_HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 -#define B_HI_RA_RAM_SRV_TRM_SEQ__W 7 -#define B_HI_RA_RAM_SRV_TRM_SEQ__M 0x7F - -#define B_HI_RA_RAM_SRV_TRM_TRM__A 0x420035 -#define B_HI_RA_RAM_SRV_TRM_TRM__W 15 -#define B_HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF -#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 -#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 -#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF - -#define B_HI_RA_RAM_SRV_TRM_DBB__A 0x420033 -#define B_HI_RA_RAM_SRV_TRM_DBB__W 12 -#define B_HI_RA_RAM_SRV_TRM_DBB__M 0xFFF -#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 -#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 -#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F -#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 -#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 -#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 - -#define B_HI_RA_RAM_SRV_TRM_DAD__A 0x420034 -#define B_HI_RA_RAM_SRV_TRM_DAD__W 16 -#define B_HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF - -#define B_HI_RA_RAM_USR_BEGIN__A 0x420040 -#define B_HI_RA_RAM_USR_BEGIN__W 16 -#define B_HI_RA_RAM_USR_BEGIN__M 0xFFFF - -#define B_HI_RA_RAM_USR_END__A 0x42007F -#define B_HI_RA_RAM_USR_END__W 16 -#define B_HI_RA_RAM_USR_END__M 0xFFFF - -#define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 -#define B_HI_IF_RAM_TRP_BPT0__XSZ 2 -#define B_HI_IF_RAM_TRP_BPT0__W 12 -#define B_HI_IF_RAM_TRP_BPT0__M 0xFFF - -#define B_HI_IF_RAM_TRP_STKU__AX 0x430002 -#define B_HI_IF_RAM_TRP_STKU__XSZ 2 -#define B_HI_IF_RAM_TRP_STKU__W 12 -#define B_HI_IF_RAM_TRP_STKU__M 0xFFF - -#define B_HI_IF_RAM_USR_BEGIN__A 0x430200 -#define B_HI_IF_RAM_USR_BEGIN__W 12 -#define B_HI_IF_RAM_USR_BEGIN__M 0xFFF - -#define B_HI_IF_RAM_USR_END__A 0x4303FF -#define B_HI_IF_RAM_USR_END__W 12 -#define B_HI_IF_RAM_USR_END__M 0xFFF - -#define B_SC_SID 0x11 - -#define B_SC_COMM_EXEC__A 0x800000 -#define B_SC_COMM_EXEC__W 3 -#define B_SC_COMM_EXEC__M 0x7 -#define B_SC_COMM_EXEC_CTL__B 0 -#define B_SC_COMM_EXEC_CTL__W 3 -#define B_SC_COMM_EXEC_CTL__M 0x7 -#define B_SC_COMM_EXEC_CTL_STOP 0x0 -#define B_SC_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_SC_COMM_EXEC_CTL_HOLD 0x2 -#define B_SC_COMM_EXEC_CTL_STEP 0x3 -#define B_SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_SC_COMM_STATE__A 0x800001 -#define B_SC_COMM_STATE__W 16 -#define B_SC_COMM_STATE__M 0xFFFF -#define B_SC_COMM_MB__A 0x800002 -#define B_SC_COMM_MB__W 16 -#define B_SC_COMM_MB__M 0xFFFF -#define B_SC_COMM_SERVICE0__A 0x800003 -#define B_SC_COMM_SERVICE0__W 16 -#define B_SC_COMM_SERVICE0__M 0xFFFF -#define B_SC_COMM_SERVICE1__A 0x800004 -#define B_SC_COMM_SERVICE1__W 16 -#define B_SC_COMM_SERVICE1__M 0xFFFF -#define B_SC_COMM_INT_STA__A 0x800007 -#define B_SC_COMM_INT_STA__W 16 -#define B_SC_COMM_INT_STA__M 0xFFFF -#define B_SC_COMM_INT_MSK__A 0x800008 -#define B_SC_COMM_INT_MSK__W 16 -#define B_SC_COMM_INT_MSK__M 0xFFFF - -#define B_SC_CT_REG_COMM_EXEC__A 0x810000 -#define B_SC_CT_REG_COMM_EXEC__W 3 -#define B_SC_CT_REG_COMM_EXEC__M 0x7 -#define B_SC_CT_REG_COMM_EXEC_CTL__B 0 -#define B_SC_CT_REG_COMM_EXEC_CTL__W 3 -#define B_SC_CT_REG_COMM_EXEC_CTL__M 0x7 -#define B_SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_SC_CT_REG_COMM_STATE__A 0x810001 -#define B_SC_CT_REG_COMM_STATE__W 10 -#define B_SC_CT_REG_COMM_STATE__M 0x3FF -#define B_SC_CT_REG_COMM_SERVICE0__A 0x810003 -#define B_SC_CT_REG_COMM_SERVICE0__W 16 -#define B_SC_CT_REG_COMM_SERVICE0__M 0xFFFF -#define B_SC_CT_REG_COMM_SERVICE1__A 0x810004 -#define B_SC_CT_REG_COMM_SERVICE1__W 16 -#define B_SC_CT_REG_COMM_SERVICE1__M 0xFFFF -#define B_SC_CT_REG_COMM_SERVICE1_SC__B 1 -#define B_SC_CT_REG_COMM_SERVICE1_SC__W 1 -#define B_SC_CT_REG_COMM_SERVICE1_SC__M 0x2 - -#define B_SC_CT_REG_COMM_INT_STA__A 0x810007 -#define B_SC_CT_REG_COMM_INT_STA__W 1 -#define B_SC_CT_REG_COMM_INT_STA__M 0x1 -#define B_SC_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define B_SC_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define B_SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define B_SC_CT_REG_COMM_INT_MSK__A 0x810008 -#define B_SC_CT_REG_COMM_INT_MSK__W 1 -#define B_SC_CT_REG_COMM_INT_MSK__M 0x1 -#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define B_SC_CT_REG_CTL_STK__AX 0x810010 -#define B_SC_CT_REG_CTL_STK__XSZ 4 -#define B_SC_CT_REG_CTL_STK__W 10 -#define B_SC_CT_REG_CTL_STK__M 0x3FF - -#define B_SC_CT_REG_CTL_BPT_IDX__A 0x81001F -#define B_SC_CT_REG_CTL_BPT_IDX__W 1 -#define B_SC_CT_REG_CTL_BPT_IDX__M 0x1 - -#define B_SC_CT_REG_CTL_BPT__A 0x810020 -#define B_SC_CT_REG_CTL_BPT__W 10 -#define B_SC_CT_REG_CTL_BPT__M 0x3FF - -#define B_SC_RA_RAM_PARAM0__A 0x820040 -#define B_SC_RA_RAM_PARAM0__W 16 -#define B_SC_RA_RAM_PARAM0__M 0xFFFF -#define B_SC_RA_RAM_PARAM1__A 0x820041 -#define B_SC_RA_RAM_PARAM1__W 16 -#define B_SC_RA_RAM_PARAM1__M 0xFFFF -#define B_SC_RA_RAM_CMD_ADDR__A 0x820042 -#define B_SC_RA_RAM_CMD_ADDR__W 16 -#define B_SC_RA_RAM_CMD_ADDR__M 0xFFFF -#define B_SC_RA_RAM_CMD__A 0x820043 -#define B_SC_RA_RAM_CMD__W 16 -#define B_SC_RA_RAM_CMD__M 0xFFFF -#define B_SC_RA_RAM_CMD_NULL 0x0 -#define B_SC_RA_RAM_CMD_PROC_START 0x1 -#define B_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 -#define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 -#define B_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 -#define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 -#define B_SC_RA_RAM_CMD_USER_IO 0x6 -#define B_SC_RA_RAM_CMD_SET_TIMER 0x7 -#define B_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 -#define B_SC_RA_RAM_CMD_MAX 0x9 -#define B_SC_RA_RAM_CMDBLOCK__C 0x4 - -#define B_SC_RA_RAM_PROC_ACTIVATE__A 0x820044 -#define B_SC_RA_RAM_PROC_ACTIVATE__W 16 -#define B_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF -#define B_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF -#define B_SC_RA_RAM_PROC_TERMINATED__A 0x820045 -#define B_SC_RA_RAM_PROC_TERMINATED__W 16 -#define B_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF -#define B_SC_RA_RAM_SW_EVENT__A 0x820046 -#define B_SC_RA_RAM_SW_EVENT__W 14 -#define B_SC_RA_RAM_SW_EVENT__M 0x3FFF -#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 -#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 -#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 -#define B_SC_RA_RAM_SW_EVENT_RUN__B 1 -#define B_SC_RA_RAM_SW_EVENT_RUN__W 1 -#define B_SC_RA_RAM_SW_EVENT_RUN__M 0x2 -#define B_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 -#define B_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 -#define B_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 -#define B_SC_RA_RAM_SW_EVENT_FT_START__B 3 -#define B_SC_RA_RAM_SW_EVENT_FT_START__W 1 -#define B_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 -#define B_SC_RA_RAM_SW_EVENT_FI_START__B 4 -#define B_SC_RA_RAM_SW_EVENT_FI_START__W 1 -#define B_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 -#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 -#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 -#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 -#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 -#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 -#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 -#define B_SC_RA_RAM_SW_EVENT_CE_IR__B 7 -#define B_SC_RA_RAM_SW_EVENT_CE_IR__W 1 -#define B_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 -#define B_SC_RA_RAM_SW_EVENT_FE_FD__B 8 -#define B_SC_RA_RAM_SW_EVENT_FE_FD__W 1 -#define B_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 -#define B_SC_RA_RAM_SW_EVENT_FE_CF__B 9 -#define B_SC_RA_RAM_SW_EVENT_FE_CF__W 1 -#define B_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 -#define B_SC_RA_RAM_SW_EVENT_NF_READY__B 12 -#define B_SC_RA_RAM_SW_EVENT_NF_READY__W 1 -#define B_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 - -#define B_SC_RA_RAM_LOCKTRACK__A 0x820047 -#define B_SC_RA_RAM_LOCKTRACK__W 16 -#define B_SC_RA_RAM_LOCKTRACK__M 0xFFFF -#define B_SC_RA_RAM_LOCKTRACK_NULL 0x0 -#define B_SC_RA_RAM_LOCKTRACK_MIN 0x1 -#define B_SC_RA_RAM_LOCKTRACK_RESET 0x1 -#define B_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 -#define B_SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 -#define B_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 -#define B_SC_RA_RAM_LOCKTRACK_LC 0x5 -#define B_SC_RA_RAM_LOCKTRACK_P_ECHO 0x6 -#define B_SC_RA_RAM_LOCKTRACK_NE_INIT 0x7 -#define B_SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x8 -#define B_SC_RA_RAM_LOCKTRACK_TRACK 0x9 -#define B_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xA -#define B_SC_RA_RAM_LOCKTRACK_MAX 0xB - -#define B_SC_RA_RAM_OP_PARAM__A 0x820048 -#define B_SC_RA_RAM_OP_PARAM__W 13 -#define B_SC_RA_RAM_OP_PARAM__M 0x1FFF -#define B_SC_RA_RAM_OP_PARAM_MODE__B 0 -#define B_SC_RA_RAM_OP_PARAM_MODE__W 2 -#define B_SC_RA_RAM_OP_PARAM_MODE__M 0x3 -#define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 -#define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 -#define B_SC_RA_RAM_OP_PARAM_GUARD__B 2 -#define B_SC_RA_RAM_OP_PARAM_GUARD__W 2 -#define B_SC_RA_RAM_OP_PARAM_GUARD__M 0xC -#define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 -#define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 -#define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 -#define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC -#define B_SC_RA_RAM_OP_PARAM_CONST__B 4 -#define B_SC_RA_RAM_OP_PARAM_CONST__W 2 -#define B_SC_RA_RAM_OP_PARAM_CONST__M 0x30 -#define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 -#define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 -#define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 -#define B_SC_RA_RAM_OP_PARAM_HIER__B 6 -#define B_SC_RA_RAM_OP_PARAM_HIER__W 3 -#define B_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 -#define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 -#define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 -#define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 -#define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 -#define B_SC_RA_RAM_OP_PARAM_RATE__B 9 -#define B_SC_RA_RAM_OP_PARAM_RATE__W 3 -#define B_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 -#define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 -#define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 -#define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 -#define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 -#define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 -#define B_SC_RA_RAM_OP_PARAM_PRIO__B 12 -#define B_SC_RA_RAM_OP_PARAM_PRIO__W 1 -#define B_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 -#define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 -#define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 - -#define B_SC_RA_RAM_OP_AUTO__A 0x820049 -#define B_SC_RA_RAM_OP_AUTO__W 6 -#define B_SC_RA_RAM_OP_AUTO__M 0x3F -#define B_SC_RA_RAM_OP_AUTO__PRE 0x1F -#define B_SC_RA_RAM_OP_AUTO_MODE__B 0 -#define B_SC_RA_RAM_OP_AUTO_MODE__W 1 -#define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1 -#define B_SC_RA_RAM_OP_AUTO_GUARD__B 1 -#define B_SC_RA_RAM_OP_AUTO_GUARD__W 1 -#define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 -#define B_SC_RA_RAM_OP_AUTO_CONST__B 2 -#define B_SC_RA_RAM_OP_AUTO_CONST__W 1 -#define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4 -#define B_SC_RA_RAM_OP_AUTO_HIER__B 3 -#define B_SC_RA_RAM_OP_AUTO_HIER__W 1 -#define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8 -#define B_SC_RA_RAM_OP_AUTO_RATE__B 4 -#define B_SC_RA_RAM_OP_AUTO_RATE__W 1 -#define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10 -#define B_SC_RA_RAM_OP_AUTO_PRIO__B 5 -#define B_SC_RA_RAM_OP_AUTO_PRIO__W 1 -#define B_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 - -#define B_SC_RA_RAM_PILOT_STATUS__A 0x82004A -#define B_SC_RA_RAM_PILOT_STATUS__W 16 -#define B_SC_RA_RAM_PILOT_STATUS__M 0xFFFF -#define B_SC_RA_RAM_PILOT_STATUS_OK 0x0 -#define B_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 -#define B_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 -#define B_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 - -#define B_SC_RA_RAM_LOCK__A 0x82004B -#define B_SC_RA_RAM_LOCK__W 4 -#define B_SC_RA_RAM_LOCK__M 0xF -#define B_SC_RA_RAM_LOCK_DEMOD__B 0 -#define B_SC_RA_RAM_LOCK_DEMOD__W 1 -#define B_SC_RA_RAM_LOCK_DEMOD__M 0x1 -#define B_SC_RA_RAM_LOCK_FEC__B 1 -#define B_SC_RA_RAM_LOCK_FEC__W 1 -#define B_SC_RA_RAM_LOCK_FEC__M 0x2 -#define B_SC_RA_RAM_LOCK_MPEG__B 2 -#define B_SC_RA_RAM_LOCK_MPEG__W 1 -#define B_SC_RA_RAM_LOCK_MPEG__M 0x4 -#define B_SC_RA_RAM_LOCK_NODVBT__B 3 -#define B_SC_RA_RAM_LOCK_NODVBT__W 1 -#define B_SC_RA_RAM_LOCK_NODVBT__M 0x8 - -#define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C -#define B_SC_RA_RAM_BE_OPT_ENA__W 5 -#define B_SC_RA_RAM_BE_OPT_ENA__M 0x1F -#define B_SC_RA_RAM_BE_OPT_ENA__PRE 0x1E -#define B_SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 -#define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 -#define B_SC_RA_RAM_BE_OPT_ENA_CSI_OPT 0x2 -#define B_SC_RA_RAM_BE_OPT_ENA_CAL_OPT 0x3 -#define B_SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 -#define B_SC_RA_RAM_BE_OPT_ENA_MAX 0x5 - -#define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D -#define B_SC_RA_RAM_BE_OPT_DELAY__W 16 -#define B_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF -#define B_SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 -#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E -#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 -#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF -#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 -#define B_SC_RA_RAM_ECHO_THRES__A 0x82004F -#define B_SC_RA_RAM_ECHO_THRES__W 16 -#define B_SC_RA_RAM_ECHO_THRES__M 0xFFFF -#define B_SC_RA_RAM_ECHO_THRES__PRE 0x2A -#define B_SC_RA_RAM_CONFIG__A 0x820050 -#define B_SC_RA_RAM_CONFIG__W 16 -#define B_SC_RA_RAM_CONFIG__M 0xFFFF -#define B_SC_RA_RAM_CONFIG__PRE 0x14 -#define B_SC_RA_RAM_CONFIG_ID__B 0 -#define B_SC_RA_RAM_CONFIG_ID__W 1 -#define B_SC_RA_RAM_CONFIG_ID__M 0x1 -#define B_SC_RA_RAM_CONFIG_ID_PRO 0x0 -#define B_SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 -#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 -#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 -#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 -#define B_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 -#define B_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 -#define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 -#define B_SC_RA_RAM_CONFIG_MIXMODE__B 3 -#define B_SC_RA_RAM_CONFIG_MIXMODE__W 1 -#define B_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 -#define B_SC_RA_RAM_CONFIG_FREQSCAN__B 4 -#define B_SC_RA_RAM_CONFIG_FREQSCAN__W 1 -#define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 -#define B_SC_RA_RAM_CONFIG_SLAVE__B 5 -#define B_SC_RA_RAM_CONFIG_SLAVE__W 1 -#define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20 -#define B_SC_RA_RAM_CONFIG_FAR_OFF__B 6 -#define B_SC_RA_RAM_CONFIG_FAR_OFF__W 1 -#define B_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 -#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 -#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 -#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 -#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 -#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 -#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 -#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 -#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 -#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 -#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 -#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 -#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 -#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 -#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 -#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 - -#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x820054 -#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 -#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF -#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 - -#define B_SC_RA_RAM_FR_2K_MAN_SH__A 0x820055 -#define B_SC_RA_RAM_FR_2K_MAN_SH__W 16 -#define B_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 -#define B_SC_RA_RAM_FR_2K_TAP_SH__A 0x820056 -#define B_SC_RA_RAM_FR_2K_TAP_SH__W 16 -#define B_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 -#define B_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x820057 -#define B_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 -#define B_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF -#define B_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 -#define B_SC_RA_RAM_FR_2K_LEAK_SH__A 0x820058 -#define B_SC_RA_RAM_FR_2K_LEAK_SH__W 16 -#define B_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 - -#define B_SC_RA_RAM_FR_8K_MAN_SH__A 0x820059 -#define B_SC_RA_RAM_FR_8K_MAN_SH__W 16 -#define B_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 -#define B_SC_RA_RAM_FR_8K_TAP_SH__A 0x82005A -#define B_SC_RA_RAM_FR_8K_TAP_SH__W 16 -#define B_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x4 -#define B_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x82005B -#define B_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 -#define B_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF -#define B_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 -#define B_SC_RA_RAM_FR_8K_LEAK_SH__A 0x82005C -#define B_SC_RA_RAM_FR_8K_LEAK_SH__W 16 -#define B_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x2 - -#define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D -#define B_SC_RA_RAM_CO_TD_CAL_2K__W 16 -#define B_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF -#define B_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB -#define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E -#define B_SC_RA_RAM_CO_TD_CAL_8K__W 16 -#define B_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF -#define B_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 -#define B_SC_RA_RAM_MOTION_OFFSET__A 0x82005F -#define B_SC_RA_RAM_MOTION_OFFSET__W 16 -#define B_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF -#define B_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 -#define B_SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 -#define B_SC_RA_RAM_STATE_PROC_STOP__XSZ 10 -#define B_SC_RA_RAM_STATE_PROC_STOP__W 16 -#define B_SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF -#define B_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE -#define B_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 -#define B_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_10__PRE 0xFFFE -#define B_SC_RA_RAM_STATE_PROC_START__AX 0x820070 -#define B_SC_RA_RAM_STATE_PROC_START__XSZ 10 -#define B_SC_RA_RAM_STATE_PROC_START__W 16 -#define B_SC_RA_RAM_STATE_PROC_START__M 0xFFFF -#define B_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 -#define B_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 -#define B_SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 -#define B_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 -#define B_SC_RA_RAM_STATE_PROC_START_5__PRE 0x100 -#define B_SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_START_7__PRE 0x40 -#define B_SC_RA_RAM_STATE_PROC_START_8__PRE 0x10 -#define B_SC_RA_RAM_STATE_PROC_START_9__PRE 0x30 -#define B_SC_RA_RAM_STATE_PROC_START_10__PRE 0x0 -#define B_SC_RA_RAM_IF_SAVE__AX 0x82008E -#define B_SC_RA_RAM_IF_SAVE__XSZ 2 -#define B_SC_RA_RAM_IF_SAVE__W 16 -#define B_SC_RA_RAM_IF_SAVE__M 0xFFFF -#define B_SC_RA_RAM_FR_THRES__A 0x82007D -#define B_SC_RA_RAM_FR_THRES__W 16 -#define B_SC_RA_RAM_FR_THRES__M 0xFFFF -#define B_SC_RA_RAM_FR_THRES__PRE 0x1A2C -#define B_SC_RA_RAM_STATUS__A 0x82007E -#define B_SC_RA_RAM_STATUS__W 16 -#define B_SC_RA_RAM_STATUS__M 0xFFFF -#define B_SC_RA_RAM_NF_BORDER_INIT__A 0x82007F -#define B_SC_RA_RAM_NF_BORDER_INIT__W 16 -#define B_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF -#define B_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 -#define B_SC_RA_RAM_TIMER__A 0x820080 -#define B_SC_RA_RAM_TIMER__W 16 -#define B_SC_RA_RAM_TIMER__M 0xFFFF -#define B_SC_RA_RAM_FI_OFFSET__A 0x820081 -#define B_SC_RA_RAM_FI_OFFSET__W 16 -#define B_SC_RA_RAM_FI_OFFSET__M 0xFFFF -#define B_SC_RA_RAM_FI_OFFSET__PRE 0x382 -#define B_SC_RA_RAM_ECHO_GUARD__A 0x820082 -#define B_SC_RA_RAM_ECHO_GUARD__W 16 -#define B_SC_RA_RAM_ECHO_GUARD__M 0xFFFF -#define B_SC_RA_RAM_ECHO_GUARD__PRE 0x18 -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__A 0x8200BA -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__W 16 -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__M 0xFFFF -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__PRE 0x3 -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__A 0x8200BB -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__W 16 -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__M 0xFFFF -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__PRE 0x0 - -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 - -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC - -#define B_SC_RA_RAM_IR_FREQ__A 0x8200D0 -#define B_SC_RA_RAM_IR_FREQ__W 16 -#define B_SC_RA_RAM_IR_FREQ__M 0xFFFF -#define B_SC_RA_RAM_IR_FREQ__PRE 0x0 - -#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 -#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 -#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF -#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 -#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 -#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 -#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF -#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 -#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 -#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 -#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF -#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 - -#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 -#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 -#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF -#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 -#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 -#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 -#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF -#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 -#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 -#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 -#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF -#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 - -#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 -#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 -#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF -#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 -#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 -#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 -#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF -#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 -#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 -#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 -#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF -#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 - -#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA -#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 -#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF -#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB -#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB -#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 -#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF -#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 -#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC -#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 -#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF -#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 - -#define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD -#define B_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 -#define B_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF -#define B_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 -#define B_SC_RA_RAM_ECHO_SHT_LIM__A 0x8200DE -#define B_SC_RA_RAM_ECHO_SHT_LIM__W 16 -#define B_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF -#define B_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x8200DF -#define B_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF -#define B_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0xCC0 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 - -#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 -#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 -#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 -#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 -#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 -#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 -#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 -#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 -#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 - -#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 -#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 -#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE -#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 -#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 -#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 -#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 -#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 -#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 - -#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 -#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 -#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF -#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 -#define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 -#define B_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 -#define B_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF -#define B_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C - -#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA -#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 -#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF -#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 -#define B_SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB -#define B_SC_RA_RAM_TPS_TIMEOUT__W 16 -#define B_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF -#define B_SC_RA_RAM_BAND__A 0x8200EC -#define B_SC_RA_RAM_BAND__W 16 -#define B_SC_RA_RAM_BAND__M 0xFFFF -#define B_SC_RA_RAM_BAND__PRE 0x0 -#define B_SC_RA_RAM_BAND_INTERVAL__B 0 -#define B_SC_RA_RAM_BAND_INTERVAL__W 4 -#define B_SC_RA_RAM_BAND_INTERVAL__M 0xF -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 - -#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED -#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 -#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF -#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 -#define B_SC_RA_RAM_REG__AX 0x8200F0 -#define B_SC_RA_RAM_REG__XSZ 2 -#define B_SC_RA_RAM_REG__W 16 -#define B_SC_RA_RAM_REG__M 0xFFFF -#define B_SC_RA_RAM_BREAK__A 0x8200F2 -#define B_SC_RA_RAM_BREAK__W 16 -#define B_SC_RA_RAM_BREAK__M 0xFFFF -#define B_SC_RA_RAM_BOOTCOUNT__A 0x8200F3 -#define B_SC_RA_RAM_BOOTCOUNT__W 16 -#define B_SC_RA_RAM_BOOTCOUNT__M 0xFFFF - -#define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 -#define B_SC_RA_RAM_LC_ABS_2K__W 16 -#define B_SC_RA_RAM_LC_ABS_2K__M 0xFFFF -#define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F -#define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5 -#define B_SC_RA_RAM_LC_ABS_8K__W 16 -#define B_SC_RA_RAM_LC_ABS_8K__M 0xFFFF -#define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F -#define B_SC_RA_RAM_NE_ERR_SELECT__A 0x8200F6 -#define B_SC_RA_RAM_NE_ERR_SELECT__W 16 -#define B_SC_RA_RAM_NE_ERR_SELECT__M 0xFFFF -#define B_SC_RA_RAM_NE_ERR_SELECT__PRE 0x19 -#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x8200F7 -#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 -#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF -#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 -#define B_SC_RA_RAM_RELOCK__A 0x8200FE -#define B_SC_RA_RAM_RELOCK__W 16 -#define B_SC_RA_RAM_RELOCK__M 0xFFFF -#define B_SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF -#define B_SC_RA_RAM_STACKUNDERFLOW__W 16 -#define B_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF - -#define B_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 -#define B_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 -#define B_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF -#define B_SC_RA_RAM_NF_PREPOST__A 0x820149 -#define B_SC_RA_RAM_NF_PREPOST__W 16 -#define B_SC_RA_RAM_NF_PREPOST__M 0xFFFF -#define B_SC_RA_RAM_NF_PREBORDER__A 0x82014A -#define B_SC_RA_RAM_NF_PREBORDER__W 16 -#define B_SC_RA_RAM_NF_PREBORDER__M 0xFFFF -#define B_SC_RA_RAM_NF_START__A 0x82014B -#define B_SC_RA_RAM_NF_START__W 16 -#define B_SC_RA_RAM_NF_START__M 0xFFFF -#define B_SC_RA_RAM_NF_MINISI__AX 0x82014C -#define B_SC_RA_RAM_NF_MINISI__XSZ 2 -#define B_SC_RA_RAM_NF_MINISI__W 16 -#define B_SC_RA_RAM_NF_MINISI__M 0xFFFF -#define B_SC_RA_RAM_NF_MAXECHO__A 0x82014E -#define B_SC_RA_RAM_NF_MAXECHO__W 16 -#define B_SC_RA_RAM_NF_MAXECHO__M 0xFFFF -#define B_SC_RA_RAM_NF_NRECHOES__A 0x82014F -#define B_SC_RA_RAM_NF_NRECHOES__W 16 -#define B_SC_RA_RAM_NF_NRECHOES__M 0xFFFF -#define B_SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 -#define B_SC_RA_RAM_NF_ECHOTABLE__XSZ 16 -#define B_SC_RA_RAM_NF_ECHOTABLE__W 16 -#define B_SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF - -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 - -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 - -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 - -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 - -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 - -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 - -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 - -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 -#define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE -#define B_SC_RA_RAM_DRIVER_VERSION__XSZ 2 -#define B_SC_RA_RAM_DRIVER_VERSION__W 16 -#define B_SC_RA_RAM_DRIVER_VERSION__M 0xFFFF -#define B_SC_RA_RAM_EVENT0_MIN 0x7 -#define B_SC_RA_RAM_EVENT0_FE_CU 0x7 -#define B_SC_RA_RAM_EVENT0_CE 0xA -#define B_SC_RA_RAM_EVENT0_EQ 0xE -#define B_SC_RA_RAM_EVENT0_MAX 0xF -#define B_SC_RA_RAM_PROC_LOCKTRACK 0x0 -#define B_SC_RA_RAM_PROC_MODE_GUARD 0x1 -#define B_SC_RA_RAM_PROC_PILOTS 0x2 -#define B_SC_RA_RAM_PROC_FESTART_ADJUST 0x3 -#define B_SC_RA_RAM_PROC_ECHO 0x4 -#define B_SC_RA_RAM_PROC_BE_OPT 0x5 -#define B_SC_RA_RAM_PROC_LOCK_MON 0x6 -#define B_SC_RA_RAM_PROC_EQ 0x7 -#define B_SC_RA_RAM_PROC_ECHO_DIVERSITY 0x8 -#define B_SC_RA_RAM_PROC_MAX 0x9 - -#define B_SC_IF_RAM_TRP_RST__AX 0x830000 -#define B_SC_IF_RAM_TRP_RST__XSZ 2 -#define B_SC_IF_RAM_TRP_RST__W 12 -#define B_SC_IF_RAM_TRP_RST__M 0xFFF - -#define B_SC_IF_RAM_TRP_BPT0__AX 0x830002 -#define B_SC_IF_RAM_TRP_BPT0__XSZ 2 -#define B_SC_IF_RAM_TRP_BPT0__W 12 -#define B_SC_IF_RAM_TRP_BPT0__M 0xFFF - -#define B_SC_IF_RAM_TRP_STKU__AX 0x830004 -#define B_SC_IF_RAM_TRP_STKU__XSZ 2 -#define B_SC_IF_RAM_TRP_STKU__W 12 -#define B_SC_IF_RAM_TRP_STKU__M 0xFFF - -#define B_SC_IF_RAM_VERSION_MA_MI__A 0x830FFE -#define B_SC_IF_RAM_VERSION_MA_MI__W 12 -#define B_SC_IF_RAM_VERSION_MA_MI__M 0xFFF - -#define B_SC_IF_RAM_VERSION_PATCH__A 0x830FFF -#define B_SC_IF_RAM_VERSION_PATCH__W 12 -#define B_SC_IF_RAM_VERSION_PATCH__M 0xFFF - -#define B_FE_COMM_EXEC__A 0xC00000 -#define B_FE_COMM_EXEC__W 3 -#define B_FE_COMM_EXEC__M 0x7 -#define B_FE_COMM_EXEC_CTL__B 0 -#define B_FE_COMM_EXEC_CTL__W 3 -#define B_FE_COMM_EXEC_CTL__M 0x7 -#define B_FE_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_COMM_EXEC_CTL_STEP 0x3 -#define B_FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_FE_COMM_STATE__A 0xC00001 -#define B_FE_COMM_STATE__W 16 -#define B_FE_COMM_STATE__M 0xFFFF -#define B_FE_COMM_MB__A 0xC00002 -#define B_FE_COMM_MB__W 16 -#define B_FE_COMM_MB__M 0xFFFF -#define B_FE_COMM_SERVICE0__A 0xC00003 -#define B_FE_COMM_SERVICE0__W 16 -#define B_FE_COMM_SERVICE0__M 0xFFFF -#define B_FE_COMM_SERVICE1__A 0xC00004 -#define B_FE_COMM_SERVICE1__W 16 -#define B_FE_COMM_SERVICE1__M 0xFFFF -#define B_FE_COMM_INT_STA__A 0xC00007 -#define B_FE_COMM_INT_STA__W 16 -#define B_FE_COMM_INT_STA__M 0xFFFF -#define B_FE_COMM_INT_MSK__A 0xC00008 -#define B_FE_COMM_INT_MSK__W 16 -#define B_FE_COMM_INT_MSK__M 0xFFFF - -#define B_FE_AD_SID 0x1 - -#define B_FE_AD_REG_COMM_EXEC__A 0xC10000 -#define B_FE_AD_REG_COMM_EXEC__W 3 -#define B_FE_AD_REG_COMM_EXEC__M 0x7 -#define B_FE_AD_REG_COMM_EXEC_CTL__B 0 -#define B_FE_AD_REG_COMM_EXEC_CTL__W 3 -#define B_FE_AD_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_AD_REG_COMM_MB__A 0xC10002 -#define B_FE_AD_REG_COMM_MB__W 2 -#define B_FE_AD_REG_COMM_MB__M 0x3 -#define B_FE_AD_REG_COMM_MB_CTR__B 0 -#define B_FE_AD_REG_COMM_MB_CTR__W 1 -#define B_FE_AD_REG_COMM_MB_CTR__M 0x1 -#define B_FE_AD_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_AD_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_AD_REG_COMM_MB_OBS__B 1 -#define B_FE_AD_REG_COMM_MB_OBS__W 1 -#define B_FE_AD_REG_COMM_MB_OBS__M 0x2 -#define B_FE_AD_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_AD_REG_COMM_MB_OBS_ON 0x2 - -#define B_FE_AD_REG_COMM_SERVICE0__A 0xC10003 -#define B_FE_AD_REG_COMM_SERVICE0__W 10 -#define B_FE_AD_REG_COMM_SERVICE0__M 0x3FF -#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 -#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 -#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 - -#define B_FE_AD_REG_COMM_SERVICE1__A 0xC10004 -#define B_FE_AD_REG_COMM_SERVICE1__W 11 -#define B_FE_AD_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_AD_REG_COMM_INT_STA__A 0xC10007 -#define B_FE_AD_REG_COMM_INT_STA__W 2 -#define B_FE_AD_REG_COMM_INT_STA__M 0x3 -#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 -#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 -#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 - -#define B_FE_AD_REG_COMM_INT_MSK__A 0xC10008 -#define B_FE_AD_REG_COMM_INT_MSK__W 2 -#define B_FE_AD_REG_COMM_INT_MSK__M 0x3 -#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 -#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 -#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 - -#define B_FE_AD_REG_CUR_SEL__A 0xC10010 -#define B_FE_AD_REG_CUR_SEL__W 2 -#define B_FE_AD_REG_CUR_SEL__M 0x3 -#define B_FE_AD_REG_CUR_SEL_INIT 0x2 - -#define B_FE_AD_REG_OVERFLOW__A 0xC10011 -#define B_FE_AD_REG_OVERFLOW__W 1 -#define B_FE_AD_REG_OVERFLOW__M 0x1 -#define B_FE_AD_REG_OVERFLOW_INIT 0x0 - -#define B_FE_AD_REG_FDB_IN__A 0xC10012 -#define B_FE_AD_REG_FDB_IN__W 1 -#define B_FE_AD_REG_FDB_IN__M 0x1 -#define B_FE_AD_REG_FDB_IN_INIT 0x0 - -#define B_FE_AD_REG_PD__A 0xC10013 -#define B_FE_AD_REG_PD__W 1 -#define B_FE_AD_REG_PD__M 0x1 -#define B_FE_AD_REG_PD_INIT 0x1 - -#define B_FE_AD_REG_INVEXT__A 0xC10014 -#define B_FE_AD_REG_INVEXT__W 1 -#define B_FE_AD_REG_INVEXT__M 0x1 -#define B_FE_AD_REG_INVEXT_INIT 0x0 - -#define B_FE_AD_REG_CLKNEG__A 0xC10015 -#define B_FE_AD_REG_CLKNEG__W 1 -#define B_FE_AD_REG_CLKNEG__M 0x1 -#define B_FE_AD_REG_CLKNEG_INIT 0x0 - -#define B_FE_AD_REG_MON_IN_MUX__A 0xC10016 -#define B_FE_AD_REG_MON_IN_MUX__W 2 -#define B_FE_AD_REG_MON_IN_MUX__M 0x3 -#define B_FE_AD_REG_MON_IN_MUX_INIT 0x0 - -#define B_FE_AD_REG_MON_IN5__A 0xC10017 -#define B_FE_AD_REG_MON_IN5__W 10 -#define B_FE_AD_REG_MON_IN5__M 0x3FF -#define B_FE_AD_REG_MON_IN5_INIT 0x0 - -#define B_FE_AD_REG_MON_IN4__A 0xC10018 -#define B_FE_AD_REG_MON_IN4__W 10 -#define B_FE_AD_REG_MON_IN4__M 0x3FF -#define B_FE_AD_REG_MON_IN4_INIT 0x0 - -#define B_FE_AD_REG_MON_IN3__A 0xC10019 -#define B_FE_AD_REG_MON_IN3__W 10 -#define B_FE_AD_REG_MON_IN3__M 0x3FF -#define B_FE_AD_REG_MON_IN3_INIT 0x0 - -#define B_FE_AD_REG_MON_IN2__A 0xC1001A -#define B_FE_AD_REG_MON_IN2__W 10 -#define B_FE_AD_REG_MON_IN2__M 0x3FF -#define B_FE_AD_REG_MON_IN2_INIT 0x0 - -#define B_FE_AD_REG_MON_IN1__A 0xC1001B -#define B_FE_AD_REG_MON_IN1__W 10 -#define B_FE_AD_REG_MON_IN1__M 0x3FF -#define B_FE_AD_REG_MON_IN1_INIT 0x0 - -#define B_FE_AD_REG_MON_IN0__A 0xC1001C -#define B_FE_AD_REG_MON_IN0__W 10 -#define B_FE_AD_REG_MON_IN0__M 0x3FF -#define B_FE_AD_REG_MON_IN0_INIT 0x0 - -#define B_FE_AD_REG_MON_IN_VAL__A 0xC1001D -#define B_FE_AD_REG_MON_IN_VAL__W 1 -#define B_FE_AD_REG_MON_IN_VAL__M 0x1 -#define B_FE_AD_REG_MON_IN_VAL_INIT 0x0 - -#define B_FE_AD_REG_CTR_CLK_O__A 0xC1001E -#define B_FE_AD_REG_CTR_CLK_O__W 1 -#define B_FE_AD_REG_CTR_CLK_O__M 0x1 -#define B_FE_AD_REG_CTR_CLK_O_INIT 0x0 - -#define B_FE_AD_REG_CTR_CLK_E_O__A 0xC1001F -#define B_FE_AD_REG_CTR_CLK_E_O__W 1 -#define B_FE_AD_REG_CTR_CLK_E_O__M 0x1 -#define B_FE_AD_REG_CTR_CLK_E_O_INIT 0x1 - -#define B_FE_AD_REG_CTR_VAL_O__A 0xC10020 -#define B_FE_AD_REG_CTR_VAL_O__W 1 -#define B_FE_AD_REG_CTR_VAL_O__M 0x1 -#define B_FE_AD_REG_CTR_VAL_O_INIT 0x0 - -#define B_FE_AD_REG_CTR_VAL_E_O__A 0xC10021 -#define B_FE_AD_REG_CTR_VAL_E_O__W 1 -#define B_FE_AD_REG_CTR_VAL_E_O__M 0x1 -#define B_FE_AD_REG_CTR_VAL_E_O_INIT 0x1 - -#define B_FE_AD_REG_CTR_DATA_O__A 0xC10022 -#define B_FE_AD_REG_CTR_DATA_O__W 10 -#define B_FE_AD_REG_CTR_DATA_O__M 0x3FF -#define B_FE_AD_REG_CTR_DATA_O_INIT 0x0 - -#define B_FE_AD_REG_CTR_DATA_E_O__A 0xC10023 -#define B_FE_AD_REG_CTR_DATA_E_O__W 10 -#define B_FE_AD_REG_CTR_DATA_E_O__M 0x3FF -#define B_FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF - -#define B_FE_AG_SID 0x2 - -#define B_FE_AG_REG_COMM_EXEC__A 0xC20000 -#define B_FE_AG_REG_COMM_EXEC__W 3 -#define B_FE_AG_REG_COMM_EXEC__M 0x7 -#define B_FE_AG_REG_COMM_EXEC_CTL__B 0 -#define B_FE_AG_REG_COMM_EXEC_CTL__W 3 -#define B_FE_AG_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_AG_REG_COMM_STATE__A 0xC20001 -#define B_FE_AG_REG_COMM_STATE__W 4 -#define B_FE_AG_REG_COMM_STATE__M 0xF - -#define B_FE_AG_REG_COMM_MB__A 0xC20002 -#define B_FE_AG_REG_COMM_MB__W 4 -#define B_FE_AG_REG_COMM_MB__M 0xF -#define B_FE_AG_REG_COMM_MB_OBS__B 1 -#define B_FE_AG_REG_COMM_MB_OBS__W 1 -#define B_FE_AG_REG_COMM_MB_OBS__M 0x2 -#define B_FE_AG_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_AG_REG_COMM_MB_OBS_ON 0x2 -#define B_FE_AG_REG_COMM_MB_MUX__B 2 -#define B_FE_AG_REG_COMM_MB_MUX__W 2 -#define B_FE_AG_REG_COMM_MB_MUX__M 0xC -#define B_FE_AG_REG_COMM_MB_MUX_DAT 0x0 -#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD2 0x4 -#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD1 0x8 -#define B_FE_AG_REG_COMM_MB_MUX_DAT_IND_PD1 0xC - -#define B_FE_AG_REG_COMM_SERVICE0__A 0xC20003 -#define B_FE_AG_REG_COMM_SERVICE0__W 10 -#define B_FE_AG_REG_COMM_SERVICE0__M 0x3FF - -#define B_FE_AG_REG_COMM_SERVICE1__A 0xC20004 -#define B_FE_AG_REG_COMM_SERVICE1__W 11 -#define B_FE_AG_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_AG_REG_COMM_INT_STA__A 0xC20007 -#define B_FE_AG_REG_COMM_INT_STA__W 8 -#define B_FE_AG_REG_COMM_INT_STA__M 0xFF -#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 -#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 -#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 -#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 -#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 -#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 -#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 -#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 -#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 -#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 -#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 -#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 -#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 -#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 - -#define B_FE_AG_REG_COMM_INT_MSK__A 0xC20008 -#define B_FE_AG_REG_COMM_INT_MSK__W 8 -#define B_FE_AG_REG_COMM_INT_MSK__M 0xFF -#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 -#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 -#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 -#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 -#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 -#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 -#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 -#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 -#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 -#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 -#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 -#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 -#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 -#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 - -#define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 -#define B_FE_AG_REG_AG_MODE_LOP__W 15 -#define B_FE_AG_REG_AG_MODE_LOP__M 0x7FFF -#define B_FE_AG_REG_AG_MODE_LOP_INIT 0x81E - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 - -#define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 -#define B_FE_AG_REG_AG_MODE_HIP__W 5 -#define B_FE_AG_REG_AG_MODE_HIP__M 0x1F -#define B_FE_AG_REG_AG_MODE_HIP_INIT 0x0 - -#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 - -#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 - -#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__B 2 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__W 1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__M 0x4 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH1 0x0 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH2 0x4 - -#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__B 3 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__W 1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8 - -#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__B 4 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__W 1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__M 0x10 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH1 0x0 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH2 0x10 - -#define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 -#define B_FE_AG_REG_AG_PGA_MODE__W 3 -#define B_FE_AG_REG_AG_PGA_MODE__M 0x7 -#define B_FE_AG_REG_AG_PGA_MODE_INIT 0x3 -#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 -#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 -#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 -#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 -#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 -#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 -#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 -#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 - -#define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 -#define B_FE_AG_REG_AG_AGC_SIO__W 2 -#define B_FE_AG_REG_AG_AGC_SIO__M 0x3 -#define B_FE_AG_REG_AG_AGC_SIO_INIT 0x3 - -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 - -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 - -#define B_FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 -#define B_FE_AG_REG_AG_AGC_USR_DAT__W 2 -#define B_FE_AG_REG_AG_AGC_USR_DAT__M 0x3 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 - -#define B_FE_AG_REG_AG_PWD__A 0xC20015 -#define B_FE_AG_REG_AG_PWD__W 5 -#define B_FE_AG_REG_AG_PWD__M 0x1F -#define B_FE_AG_REG_AG_PWD_INIT 0x6 - -#define B_FE_AG_REG_AG_PWD_PWD_PD1__B 0 -#define B_FE_AG_REG_AG_PWD_PWD_PD1__W 1 -#define B_FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 -#define B_FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 -#define B_FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 - -#define B_FE_AG_REG_AG_PWD_PWD_PD2__B 1 -#define B_FE_AG_REG_AG_PWD_PWD_PD2__W 1 -#define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 -#define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 -#define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 - -#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 - -#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 - -#define B_FE_AG_REG_AG_PWD_PWD_AAF__B 4 -#define B_FE_AG_REG_AG_PWD_PWD_AAF__W 1 -#define B_FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 -#define B_FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 -#define B_FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 - -#define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 -#define B_FE_AG_REG_DCE_AUR_CNT__W 5 -#define B_FE_AG_REG_DCE_AUR_CNT__M 0x1F -#define B_FE_AG_REG_DCE_AUR_CNT_INIT 0x10 - -#define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 -#define B_FE_AG_REG_DCE_RUR_CNT__W 5 -#define B_FE_AG_REG_DCE_RUR_CNT__M 0x1F -#define B_FE_AG_REG_DCE_RUR_CNT_INIT 0x0 - -#define B_FE_AG_REG_DCE_AVE_DAT__A 0xC20018 -#define B_FE_AG_REG_DCE_AVE_DAT__W 10 -#define B_FE_AG_REG_DCE_AVE_DAT__M 0x3FF - -#define B_FE_AG_REG_DEC_AVE_WRI__A 0xC20019 -#define B_FE_AG_REG_DEC_AVE_WRI__W 10 -#define B_FE_AG_REG_DEC_AVE_WRI__M 0x3FF -#define B_FE_AG_REG_DEC_AVE_WRI_INIT 0x0 - -#define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A -#define B_FE_AG_REG_ACE_AUR_CNT__W 5 -#define B_FE_AG_REG_ACE_AUR_CNT__M 0x1F -#define B_FE_AG_REG_ACE_AUR_CNT_INIT 0xE - -#define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B -#define B_FE_AG_REG_ACE_RUR_CNT__W 5 -#define B_FE_AG_REG_ACE_RUR_CNT__M 0x1F -#define B_FE_AG_REG_ACE_RUR_CNT_INIT 0x0 - -#define B_FE_AG_REG_ACE_AVE_DAT__A 0xC2001C -#define B_FE_AG_REG_ACE_AVE_DAT__W 10 -#define B_FE_AG_REG_ACE_AVE_DAT__M 0x3FF - -#define B_FE_AG_REG_AEC_AVE_INC__A 0xC2001D -#define B_FE_AG_REG_AEC_AVE_INC__W 10 -#define B_FE_AG_REG_AEC_AVE_INC__M 0x3FF -#define B_FE_AG_REG_AEC_AVE_INC_INIT 0x0 - -#define B_FE_AG_REG_AEC_AVE_DAT__A 0xC2001E -#define B_FE_AG_REG_AEC_AVE_DAT__W 10 -#define B_FE_AG_REG_AEC_AVE_DAT__M 0x3FF - -#define B_FE_AG_REG_AEC_CLP_LVL__A 0xC2001F -#define B_FE_AG_REG_AEC_CLP_LVL__W 16 -#define B_FE_AG_REG_AEC_CLP_LVL__M 0xFFFF -#define B_FE_AG_REG_AEC_CLP_LVL_INIT 0x0 - -#define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 -#define B_FE_AG_REG_CDR_RUR_CNT__W 5 -#define B_FE_AG_REG_CDR_RUR_CNT__M 0x1F -#define B_FE_AG_REG_CDR_RUR_CNT_INIT 0x10 - -#define B_FE_AG_REG_CDR_CLP_DAT__A 0xC20021 -#define B_FE_AG_REG_CDR_CLP_DAT__W 16 -#define B_FE_AG_REG_CDR_CLP_DAT__M 0xFFFF - -#define B_FE_AG_REG_CDR_CLP_POS__A 0xC20022 -#define B_FE_AG_REG_CDR_CLP_POS__W 10 -#define B_FE_AG_REG_CDR_CLP_POS__M 0x3FF -#define B_FE_AG_REG_CDR_CLP_POS_INIT 0x16A - -#define B_FE_AG_REG_CDR_CLP_NEG__A 0xC20023 -#define B_FE_AG_REG_CDR_CLP_NEG__W 10 -#define B_FE_AG_REG_CDR_CLP_NEG__M 0x3FF -#define B_FE_AG_REG_CDR_CLP_NEG_INIT 0x296 - -#define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 -#define B_FE_AG_REG_EGC_RUR_CNT__W 5 -#define B_FE_AG_REG_EGC_RUR_CNT__M 0x1F -#define B_FE_AG_REG_EGC_RUR_CNT_INIT 0x0 - -#define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 -#define B_FE_AG_REG_EGC_SET_LVL__W 9 -#define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF -#define B_FE_AG_REG_EGC_SET_LVL_INIT 0x46 - -#define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 -#define B_FE_AG_REG_EGC_FLA_RGN__W 9 -#define B_FE_AG_REG_EGC_FLA_RGN__M 0x1FF -#define B_FE_AG_REG_EGC_FLA_RGN_INIT 0x4 - -#define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 -#define B_FE_AG_REG_EGC_SLO_RGN__W 9 -#define B_FE_AG_REG_EGC_SLO_RGN__M 0x1FF -#define B_FE_AG_REG_EGC_SLO_RGN_INIT 0x1F - -#define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 -#define B_FE_AG_REG_EGC_JMP_PSN__W 4 -#define B_FE_AG_REG_EGC_JMP_PSN__M 0xF -#define B_FE_AG_REG_EGC_JMP_PSN_INIT 0x0 - -#define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 -#define B_FE_AG_REG_EGC_FLA_INC__W 16 -#define B_FE_AG_REG_EGC_FLA_INC__M 0xFFFF -#define B_FE_AG_REG_EGC_FLA_INC_INIT 0x0 - -#define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A -#define B_FE_AG_REG_EGC_FLA_DEC__W 16 -#define B_FE_AG_REG_EGC_FLA_DEC__M 0xFFFF -#define B_FE_AG_REG_EGC_FLA_DEC_INIT 0x0 - -#define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B -#define B_FE_AG_REG_EGC_SLO_INC__W 16 -#define B_FE_AG_REG_EGC_SLO_INC__M 0xFFFF -#define B_FE_AG_REG_EGC_SLO_INC_INIT 0x3 - -#define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C -#define B_FE_AG_REG_EGC_SLO_DEC__W 16 -#define B_FE_AG_REG_EGC_SLO_DEC__M 0xFFFF -#define B_FE_AG_REG_EGC_SLO_DEC_INIT 0x3 - -#define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D -#define B_FE_AG_REG_EGC_FAS_INC__W 16 -#define B_FE_AG_REG_EGC_FAS_INC__M 0xFFFF -#define B_FE_AG_REG_EGC_FAS_INC_INIT 0xE - -#define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E -#define B_FE_AG_REG_EGC_FAS_DEC__W 16 -#define B_FE_AG_REG_EGC_FAS_DEC__M 0xFFFF -#define B_FE_AG_REG_EGC_FAS_DEC_INIT 0xE - -#define B_FE_AG_REG_EGC_MAP_DAT__A 0xC2002F -#define B_FE_AG_REG_EGC_MAP_DAT__W 16 -#define B_FE_AG_REG_EGC_MAP_DAT__M 0xFFFF - -#define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030 -#define B_FE_AG_REG_PM1_AGC_WRI__W 11 -#define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF -#define B_FE_AG_REG_PM1_AGC_WRI_INIT 0x0 - -#define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 -#define B_FE_AG_REG_GC1_AGC_RIC__W 16 -#define B_FE_AG_REG_GC1_AGC_RIC__M 0xFFFF -#define B_FE_AG_REG_GC1_AGC_RIC_INIT 0x64 - -#define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 -#define B_FE_AG_REG_GC1_AGC_OFF__W 16 -#define B_FE_AG_REG_GC1_AGC_OFF__M 0xFFFF -#define B_FE_AG_REG_GC1_AGC_OFF_INIT 0xFEC8 - -#define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 -#define B_FE_AG_REG_GC1_AGC_MAX__W 10 -#define B_FE_AG_REG_GC1_AGC_MAX__M 0x3FF -#define B_FE_AG_REG_GC1_AGC_MAX_INIT 0x1FF - -#define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 -#define B_FE_AG_REG_GC1_AGC_MIN__W 10 -#define B_FE_AG_REG_GC1_AGC_MIN__M 0x3FF -#define B_FE_AG_REG_GC1_AGC_MIN_INIT 0x200 - -#define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 -#define B_FE_AG_REG_GC1_AGC_DAT__W 10 -#define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF - -#define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036 -#define B_FE_AG_REG_PM2_AGC_WRI__W 11 -#define B_FE_AG_REG_PM2_AGC_WRI__M 0x7FF -#define B_FE_AG_REG_PM2_AGC_WRI_INIT 0x0 - -#define B_FE_AG_REG_GC2_AGC_RIC__A 0xC20037 -#define B_FE_AG_REG_GC2_AGC_RIC__W 16 -#define B_FE_AG_REG_GC2_AGC_RIC__M 0xFFFF -#define B_FE_AG_REG_GC2_AGC_RIC_INIT 0x64 - -#define B_FE_AG_REG_GC2_AGC_OFF__A 0xC20038 -#define B_FE_AG_REG_GC2_AGC_OFF__W 16 -#define B_FE_AG_REG_GC2_AGC_OFF__M 0xFFFF -#define B_FE_AG_REG_GC2_AGC_OFF_INIT 0xFEC8 - -#define B_FE_AG_REG_GC2_AGC_MAX__A 0xC20039 -#define B_FE_AG_REG_GC2_AGC_MAX__W 10 -#define B_FE_AG_REG_GC2_AGC_MAX__M 0x3FF -#define B_FE_AG_REG_GC2_AGC_MAX_INIT 0x1FF - -#define B_FE_AG_REG_GC2_AGC_MIN__A 0xC2003A -#define B_FE_AG_REG_GC2_AGC_MIN__W 10 -#define B_FE_AG_REG_GC2_AGC_MIN__M 0x3FF -#define B_FE_AG_REG_GC2_AGC_MIN_INIT 0x200 - -#define B_FE_AG_REG_GC2_AGC_DAT__A 0xC2003B -#define B_FE_AG_REG_GC2_AGC_DAT__W 10 -#define B_FE_AG_REG_GC2_AGC_DAT__M 0x3FF - -#define B_FE_AG_REG_IND_WIN__A 0xC2003C -#define B_FE_AG_REG_IND_WIN__W 5 -#define B_FE_AG_REG_IND_WIN__M 0x1F -#define B_FE_AG_REG_IND_WIN_INIT 0x0 - -#define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D -#define B_FE_AG_REG_IND_THD_LOL__W 6 -#define B_FE_AG_REG_IND_THD_LOL__M 0x3F -#define B_FE_AG_REG_IND_THD_LOL_INIT 0x5 - -#define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E -#define B_FE_AG_REG_IND_THD_HIL__W 6 -#define B_FE_AG_REG_IND_THD_HIL__M 0x3F -#define B_FE_AG_REG_IND_THD_HIL_INIT 0xF - -#define B_FE_AG_REG_IND_DEL__A 0xC2003F -#define B_FE_AG_REG_IND_DEL__W 7 -#define B_FE_AG_REG_IND_DEL__M 0x7F -#define B_FE_AG_REG_IND_DEL_INIT 0x32 - -#define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 -#define B_FE_AG_REG_IND_PD1_WRI__W 6 -#define B_FE_AG_REG_IND_PD1_WRI__M 0x3F -#define B_FE_AG_REG_IND_PD1_WRI_INIT 0x1E - -#define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 -#define B_FE_AG_REG_PDA_AUR_CNT__W 5 -#define B_FE_AG_REG_PDA_AUR_CNT__M 0x1F -#define B_FE_AG_REG_PDA_AUR_CNT_INIT 0x10 - -#define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 -#define B_FE_AG_REG_PDA_RUR_CNT__W 5 -#define B_FE_AG_REG_PDA_RUR_CNT__M 0x1F -#define B_FE_AG_REG_PDA_RUR_CNT_INIT 0x0 - -#define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 -#define B_FE_AG_REG_PDA_AVE_DAT__W 6 -#define B_FE_AG_REG_PDA_AVE_DAT__M 0x3F - -#define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044 -#define B_FE_AG_REG_PDC_RUR_CNT__W 5 -#define B_FE_AG_REG_PDC_RUR_CNT__M 0x1F -#define B_FE_AG_REG_PDC_RUR_CNT_INIT 0x0 - -#define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 -#define B_FE_AG_REG_PDC_SET_LVL__W 6 -#define B_FE_AG_REG_PDC_SET_LVL__M 0x3F -#define B_FE_AG_REG_PDC_SET_LVL_INIT 0x10 - -#define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 -#define B_FE_AG_REG_PDC_FLA_RGN__W 6 -#define B_FE_AG_REG_PDC_FLA_RGN__M 0x3F -#define B_FE_AG_REG_PDC_FLA_RGN_INIT 0x0 - -#define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 -#define B_FE_AG_REG_PDC_JMP_PSN__W 3 -#define B_FE_AG_REG_PDC_JMP_PSN__M 0x7 -#define B_FE_AG_REG_PDC_JMP_PSN_INIT 0x0 - -#define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 -#define B_FE_AG_REG_PDC_FLA_STP__W 16 -#define B_FE_AG_REG_PDC_FLA_STP__M 0xFFFF -#define B_FE_AG_REG_PDC_FLA_STP_INIT 0x0 - -#define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 -#define B_FE_AG_REG_PDC_SLO_STP__W 16 -#define B_FE_AG_REG_PDC_SLO_STP__M 0xFFFF -#define B_FE_AG_REG_PDC_SLO_STP_INIT 0x1 - -#define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A -#define B_FE_AG_REG_PDC_PD2_WRI__W 6 -#define B_FE_AG_REG_PDC_PD2_WRI__M 0x3F -#define B_FE_AG_REG_PDC_PD2_WRI_INIT 0x1F - -#define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B -#define B_FE_AG_REG_PDC_MAP_DAT__W 6 -#define B_FE_AG_REG_PDC_MAP_DAT__M 0x3F - -#define B_FE_AG_REG_PDC_MAX__A 0xC2004C -#define B_FE_AG_REG_PDC_MAX__W 6 -#define B_FE_AG_REG_PDC_MAX__M 0x3F -#define B_FE_AG_REG_PDC_MAX_INIT 0x2 - -#define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D -#define B_FE_AG_REG_TGA_AUR_CNT__W 5 -#define B_FE_AG_REG_TGA_AUR_CNT__M 0x1F -#define B_FE_AG_REG_TGA_AUR_CNT_INIT 0x10 - -#define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E -#define B_FE_AG_REG_TGA_RUR_CNT__W 5 -#define B_FE_AG_REG_TGA_RUR_CNT__M 0x1F -#define B_FE_AG_REG_TGA_RUR_CNT_INIT 0x0 - -#define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F -#define B_FE_AG_REG_TGA_AVE_DAT__W 6 -#define B_FE_AG_REG_TGA_AVE_DAT__M 0x3F - -#define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050 -#define B_FE_AG_REG_TGC_RUR_CNT__W 5 -#define B_FE_AG_REG_TGC_RUR_CNT__M 0x1F -#define B_FE_AG_REG_TGC_RUR_CNT_INIT 0x0 - -#define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 -#define B_FE_AG_REG_TGC_SET_LVL__W 6 -#define B_FE_AG_REG_TGC_SET_LVL__M 0x3F -#define B_FE_AG_REG_TGC_SET_LVL_INIT 0x18 - -#define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 -#define B_FE_AG_REG_TGC_FLA_RGN__W 6 -#define B_FE_AG_REG_TGC_FLA_RGN__M 0x3F -#define B_FE_AG_REG_TGC_FLA_RGN_INIT 0x0 - -#define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 -#define B_FE_AG_REG_TGC_JMP_PSN__W 4 -#define B_FE_AG_REG_TGC_JMP_PSN__M 0xF -#define B_FE_AG_REG_TGC_JMP_PSN_INIT 0x0 - -#define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 -#define B_FE_AG_REG_TGC_FLA_STP__W 16 -#define B_FE_AG_REG_TGC_FLA_STP__M 0xFFFF -#define B_FE_AG_REG_TGC_FLA_STP_INIT 0x0 - -#define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 -#define B_FE_AG_REG_TGC_SLO_STP__W 16 -#define B_FE_AG_REG_TGC_SLO_STP__M 0xFFFF -#define B_FE_AG_REG_TGC_SLO_STP_INIT 0x1 - -#define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 -#define B_FE_AG_REG_TGC_MAP_DAT__W 10 -#define B_FE_AG_REG_TGC_MAP_DAT__M 0x3FF - -#define B_FE_AG_REG_FGM_WRI__A 0xC20061 -#define B_FE_AG_REG_FGM_WRI__W 10 -#define B_FE_AG_REG_FGM_WRI__M 0x3FF -#define B_FE_AG_REG_FGM_WRI_INIT 0x80 - -#define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 -#define B_FE_AG_REG_BGC_FGC_WRI__W 4 -#define B_FE_AG_REG_BGC_FGC_WRI__M 0xF -#define B_FE_AG_REG_BGC_FGC_WRI_INIT 0x0 - -#define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 -#define B_FE_AG_REG_BGC_CGC_WRI__W 2 -#define B_FE_AG_REG_BGC_CGC_WRI__M 0x3 -#define B_FE_AG_REG_BGC_CGC_WRI_INIT 0x0 - -#define B_FE_AG_REG_BGC_THD_LVL__A 0xC2006B -#define B_FE_AG_REG_BGC_THD_LVL__W 4 -#define B_FE_AG_REG_BGC_THD_LVL__M 0xF -#define B_FE_AG_REG_BGC_THD_LVL_INIT 0xF - -#define B_FE_AG_REG_BGC_THD_INC__A 0xC2006C -#define B_FE_AG_REG_BGC_THD_INC__W 4 -#define B_FE_AG_REG_BGC_THD_INC__M 0xF -#define B_FE_AG_REG_BGC_THD_INC_INIT 0x8 - -#define B_FE_AG_REG_BGC_DAT__A 0xC2006D -#define B_FE_AG_REG_BGC_DAT__W 4 -#define B_FE_AG_REG_BGC_DAT__M 0xF - -#define B_FE_AG_REG_IND_PD1_COM__A 0xC2006E -#define B_FE_AG_REG_IND_PD1_COM__W 6 -#define B_FE_AG_REG_IND_PD1_COM__M 0x3F -#define B_FE_AG_REG_IND_PD1_COM_INIT 0x7 - -#define B_FE_AG_REG_AG_AGC_BUF__A 0xC2006F -#define B_FE_AG_REG_AG_AGC_BUF__W 2 -#define B_FE_AG_REG_AG_AGC_BUF__M 0x3 -#define B_FE_AG_REG_AG_AGC_BUF_INIT 0x3 - -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__B 0 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__W 1 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__M 0x1 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_SLOW 0x0 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_FAST 0x1 - -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__B 1 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__W 1 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__M 0x2 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_SLOW 0x0 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_FAST 0x2 - -#define B_FE_AG_REG_PMX_SPE__A 0xC20070 -#define B_FE_AG_REG_PMX_SPE__W 3 -#define B_FE_AG_REG_PMX_SPE__M 0x7 -#define B_FE_AG_REG_PMX_SPE_INIT 0x1 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_1 0x0 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_2 0x1 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_3 0x2 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_4 0x3 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_5 0x4 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_6 0x5 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_7 0x6 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_8 0x7 - -#define B_FE_FS_SID 0x3 - -#define B_FE_FS_REG_COMM_EXEC__A 0xC30000 -#define B_FE_FS_REG_COMM_EXEC__W 3 -#define B_FE_FS_REG_COMM_EXEC__M 0x7 -#define B_FE_FS_REG_COMM_EXEC_CTL__B 0 -#define B_FE_FS_REG_COMM_EXEC_CTL__W 3 -#define B_FE_FS_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_FS_REG_COMM_STATE__A 0xC30001 -#define B_FE_FS_REG_COMM_STATE__W 4 -#define B_FE_FS_REG_COMM_STATE__M 0xF - -#define B_FE_FS_REG_COMM_MB__A 0xC30002 -#define B_FE_FS_REG_COMM_MB__W 3 -#define B_FE_FS_REG_COMM_MB__M 0x7 -#define B_FE_FS_REG_COMM_MB_CTR__B 0 -#define B_FE_FS_REG_COMM_MB_CTR__W 1 -#define B_FE_FS_REG_COMM_MB_CTR__M 0x1 -#define B_FE_FS_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_FS_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_FS_REG_COMM_MB_OBS__B 1 -#define B_FE_FS_REG_COMM_MB_OBS__W 1 -#define B_FE_FS_REG_COMM_MB_OBS__M 0x2 -#define B_FE_FS_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_FS_REG_COMM_MB_OBS_ON 0x2 -#define B_FE_FS_REG_COMM_MB_MUX__B 2 -#define B_FE_FS_REG_COMM_MB_MUX__W 1 -#define B_FE_FS_REG_COMM_MB_MUX__M 0x4 -#define B_FE_FS_REG_COMM_MB_MUX_REAL 0x0 -#define B_FE_FS_REG_COMM_MB_MUX_IMAG 0x4 - -#define B_FE_FS_REG_COMM_SERVICE0__A 0xC30003 -#define B_FE_FS_REG_COMM_SERVICE0__W 10 -#define B_FE_FS_REG_COMM_SERVICE0__M 0x3FF - -#define B_FE_FS_REG_COMM_SERVICE1__A 0xC30004 -#define B_FE_FS_REG_COMM_SERVICE1__W 11 -#define B_FE_FS_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_FS_REG_COMM_ACT__A 0xC30005 -#define B_FE_FS_REG_COMM_ACT__W 2 -#define B_FE_FS_REG_COMM_ACT__M 0x3 - -#define B_FE_FS_REG_COMM_CNT__A 0xC30006 -#define B_FE_FS_REG_COMM_CNT__W 16 -#define B_FE_FS_REG_COMM_CNT__M 0xFFFF - -#define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010 -#define B_FE_FS_REG_ADD_INC_LOP__W 16 -#define B_FE_FS_REG_ADD_INC_LOP__M 0xFFFF -#define B_FE_FS_REG_ADD_INC_LOP_INIT 0x0 - -#define B_FE_FS_REG_ADD_INC_HIP__A 0xC30011 -#define B_FE_FS_REG_ADD_INC_HIP__W 12 -#define B_FE_FS_REG_ADD_INC_HIP__M 0xFFF -#define B_FE_FS_REG_ADD_INC_HIP_INIT 0xC00 - -#define B_FE_FS_REG_ADD_OFF__A 0xC30012 -#define B_FE_FS_REG_ADD_OFF__W 12 -#define B_FE_FS_REG_ADD_OFF__M 0xFFF -#define B_FE_FS_REG_ADD_OFF_INIT 0x0 - -#define B_FE_FS_REG_ADD_OFF_VAL__A 0xC30013 -#define B_FE_FS_REG_ADD_OFF_VAL__W 1 -#define B_FE_FS_REG_ADD_OFF_VAL__M 0x1 -#define B_FE_FS_REG_ADD_OFF_VAL_INIT 0x0 - -#define B_FE_FD_SID 0x4 - -#define B_FE_FD_REG_COMM_EXEC__A 0xC40000 -#define B_FE_FD_REG_COMM_EXEC__W 3 -#define B_FE_FD_REG_COMM_EXEC__M 0x7 -#define B_FE_FD_REG_COMM_EXEC_CTL__B 0 -#define B_FE_FD_REG_COMM_EXEC_CTL__W 3 -#define B_FE_FD_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_FD_REG_COMM_MB__A 0xC40002 -#define B_FE_FD_REG_COMM_MB__W 3 -#define B_FE_FD_REG_COMM_MB__M 0x7 -#define B_FE_FD_REG_COMM_MB_CTR__B 0 -#define B_FE_FD_REG_COMM_MB_CTR__W 1 -#define B_FE_FD_REG_COMM_MB_CTR__M 0x1 -#define B_FE_FD_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_FD_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_FD_REG_COMM_MB_OBS__B 1 -#define B_FE_FD_REG_COMM_MB_OBS__W 1 -#define B_FE_FD_REG_COMM_MB_OBS__M 0x2 -#define B_FE_FD_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_FD_REG_COMM_MB_OBS_ON 0x2 - -#define B_FE_FD_REG_COMM_SERVICE0__A 0xC40003 -#define B_FE_FD_REG_COMM_SERVICE0__W 10 -#define B_FE_FD_REG_COMM_SERVICE0__M 0x3FF -#define B_FE_FD_REG_COMM_SERVICE1__A 0xC40004 -#define B_FE_FD_REG_COMM_SERVICE1__W 11 -#define B_FE_FD_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_FD_REG_COMM_INT_STA__A 0xC40007 -#define B_FE_FD_REG_COMM_INT_STA__W 1 -#define B_FE_FD_REG_COMM_INT_STA__M 0x1 -#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define B_FE_FD_REG_COMM_INT_MSK__A 0xC40008 -#define B_FE_FD_REG_COMM_INT_MSK__W 1 -#define B_FE_FD_REG_COMM_INT_MSK__M 0x1 -#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - -#define B_FE_FD_REG_SCL__A 0xC40010 -#define B_FE_FD_REG_SCL__W 6 -#define B_FE_FD_REG_SCL__M 0x3F - -#define B_FE_FD_REG_MAX_LEV__A 0xC40011 -#define B_FE_FD_REG_MAX_LEV__W 3 -#define B_FE_FD_REG_MAX_LEV__M 0x7 - -#define B_FE_FD_REG_NR__A 0xC40012 -#define B_FE_FD_REG_NR__W 5 -#define B_FE_FD_REG_NR__M 0x1F - -#define B_FE_FD_REG_MEAS_SEL__A 0xC40013 -#define B_FE_FD_REG_MEAS_SEL__W 1 -#define B_FE_FD_REG_MEAS_SEL__M 0x1 - -#define B_FE_FD_REG_MEAS_VAL__A 0xC40014 -#define B_FE_FD_REG_MEAS_VAL__W 1 -#define B_FE_FD_REG_MEAS_VAL__M 0x1 - -#define B_FE_FD_REG_MAX__A 0xC40015 -#define B_FE_FD_REG_MAX__W 16 -#define B_FE_FD_REG_MAX__M 0xFFFF - -#define B_FE_IF_SID 0x5 - -#define B_FE_IF_REG_COMM_EXEC__A 0xC50000 -#define B_FE_IF_REG_COMM_EXEC__W 3 -#define B_FE_IF_REG_COMM_EXEC__M 0x7 -#define B_FE_IF_REG_COMM_EXEC_CTL__B 0 -#define B_FE_IF_REG_COMM_EXEC_CTL__W 3 -#define B_FE_IF_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_IF_REG_COMM_MB__A 0xC50002 -#define B_FE_IF_REG_COMM_MB__W 3 -#define B_FE_IF_REG_COMM_MB__M 0x7 -#define B_FE_IF_REG_COMM_MB_CTR__B 0 -#define B_FE_IF_REG_COMM_MB_CTR__W 1 -#define B_FE_IF_REG_COMM_MB_CTR__M 0x1 -#define B_FE_IF_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_IF_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_IF_REG_COMM_MB_OBS__B 1 -#define B_FE_IF_REG_COMM_MB_OBS__W 1 -#define B_FE_IF_REG_COMM_MB_OBS__M 0x2 -#define B_FE_IF_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_IF_REG_COMM_MB_OBS_ON 0x2 - -#define B_FE_IF_REG_INCR0__A 0xC50010 -#define B_FE_IF_REG_INCR0__W 16 -#define B_FE_IF_REG_INCR0__M 0xFFFF -#define B_FE_IF_REG_INCR0_INIT 0x0 - -#define B_FE_IF_REG_INCR1__A 0xC50011 -#define B_FE_IF_REG_INCR1__W 8 -#define B_FE_IF_REG_INCR1__M 0xFF -#define B_FE_IF_REG_INCR1_INIT 0x28 - -#define B_FE_CF_SID 0x6 - -#define B_FE_CF_REG_COMM_EXEC__A 0xC60000 -#define B_FE_CF_REG_COMM_EXEC__W 3 -#define B_FE_CF_REG_COMM_EXEC__M 0x7 -#define B_FE_CF_REG_COMM_EXEC_CTL__B 0 -#define B_FE_CF_REG_COMM_EXEC_CTL__W 3 -#define B_FE_CF_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_CF_REG_COMM_MB__A 0xC60002 -#define B_FE_CF_REG_COMM_MB__W 3 -#define B_FE_CF_REG_COMM_MB__M 0x7 -#define B_FE_CF_REG_COMM_MB_CTR__B 0 -#define B_FE_CF_REG_COMM_MB_CTR__W 1 -#define B_FE_CF_REG_COMM_MB_CTR__M 0x1 -#define B_FE_CF_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_CF_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_CF_REG_COMM_MB_OBS__B 1 -#define B_FE_CF_REG_COMM_MB_OBS__W 1 -#define B_FE_CF_REG_COMM_MB_OBS__M 0x2 -#define B_FE_CF_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_CF_REG_COMM_MB_OBS_ON 0x2 - -#define B_FE_CF_REG_COMM_SERVICE0__A 0xC60003 -#define B_FE_CF_REG_COMM_SERVICE0__W 10 -#define B_FE_CF_REG_COMM_SERVICE0__M 0x3FF -#define B_FE_CF_REG_COMM_SERVICE1__A 0xC60004 -#define B_FE_CF_REG_COMM_SERVICE1__W 11 -#define B_FE_CF_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_CF_REG_COMM_INT_STA__A 0xC60007 -#define B_FE_CF_REG_COMM_INT_STA__W 2 -#define B_FE_CF_REG_COMM_INT_STA__M 0x3 -#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define B_FE_CF_REG_COMM_INT_MSK__A 0xC60008 -#define B_FE_CF_REG_COMM_INT_MSK__W 2 -#define B_FE_CF_REG_COMM_INT_MSK__M 0x3 -#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - -#define B_FE_CF_REG_SCL__A 0xC60010 -#define B_FE_CF_REG_SCL__W 9 -#define B_FE_CF_REG_SCL__M 0x1FF - -#define B_FE_CF_REG_MAX_LEV__A 0xC60011 -#define B_FE_CF_REG_MAX_LEV__W 3 -#define B_FE_CF_REG_MAX_LEV__M 0x7 - -#define B_FE_CF_REG_NR__A 0xC60012 -#define B_FE_CF_REG_NR__W 5 -#define B_FE_CF_REG_NR__M 0x1F - -#define B_FE_CF_REG_IMP_VAL__A 0xC60013 -#define B_FE_CF_REG_IMP_VAL__W 1 -#define B_FE_CF_REG_IMP_VAL__M 0x1 - -#define B_FE_CF_REG_MEAS_VAL__A 0xC60014 -#define B_FE_CF_REG_MEAS_VAL__W 1 -#define B_FE_CF_REG_MEAS_VAL__M 0x1 - -#define B_FE_CF_REG_MAX__A 0xC60015 -#define B_FE_CF_REG_MAX__W 16 -#define B_FE_CF_REG_MAX__M 0xFFFF - -#define B_FE_CU_SID 0x7 - -#define B_FE_CU_REG_COMM_EXEC__A 0xC70000 -#define B_FE_CU_REG_COMM_EXEC__W 3 -#define B_FE_CU_REG_COMM_EXEC__M 0x7 -#define B_FE_CU_REG_COMM_EXEC_CTL__B 0 -#define B_FE_CU_REG_COMM_EXEC_CTL__W 3 -#define B_FE_CU_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_CU_REG_COMM_STATE__A 0xC70001 -#define B_FE_CU_REG_COMM_STATE__W 4 -#define B_FE_CU_REG_COMM_STATE__M 0xF - -#define B_FE_CU_REG_COMM_MB__A 0xC70002 -#define B_FE_CU_REG_COMM_MB__W 3 -#define B_FE_CU_REG_COMM_MB__M 0x7 -#define B_FE_CU_REG_COMM_MB_CTR__B 0 -#define B_FE_CU_REG_COMM_MB_CTR__W 1 -#define B_FE_CU_REG_COMM_MB_CTR__M 0x1 -#define B_FE_CU_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_CU_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_CU_REG_COMM_MB_OBS__B 1 -#define B_FE_CU_REG_COMM_MB_OBS__W 1 -#define B_FE_CU_REG_COMM_MB_OBS__M 0x2 -#define B_FE_CU_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_CU_REG_COMM_MB_OBS_ON 0x2 -#define B_FE_CU_REG_COMM_MB_MUX__B 2 -#define B_FE_CU_REG_COMM_MB_MUX__W 1 -#define B_FE_CU_REG_COMM_MB_MUX__M 0x4 -#define B_FE_CU_REG_COMM_MB_MUX_REAL 0x0 -#define B_FE_CU_REG_COMM_MB_MUX_IMAG 0x4 - -#define B_FE_CU_REG_COMM_SERVICE0__A 0xC70003 -#define B_FE_CU_REG_COMM_SERVICE0__W 10 -#define B_FE_CU_REG_COMM_SERVICE0__M 0x3FF - -#define B_FE_CU_REG_COMM_SERVICE1__A 0xC70004 -#define B_FE_CU_REG_COMM_SERVICE1__W 11 -#define B_FE_CU_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_CU_REG_COMM_ACT__A 0xC70005 -#define B_FE_CU_REG_COMM_ACT__W 2 -#define B_FE_CU_REG_COMM_ACT__M 0x3 - -#define B_FE_CU_REG_COMM_CNT__A 0xC70006 -#define B_FE_CU_REG_COMM_CNT__W 16 -#define B_FE_CU_REG_COMM_CNT__M 0xFFFF - -#define B_FE_CU_REG_COMM_INT_STA__A 0xC70007 -#define B_FE_CU_REG_COMM_INT_STA__W 4 -#define B_FE_CU_REG_COMM_INT_STA__M 0xF -#define B_FE_CU_REG_COMM_INT_STA_FE_START__B 0 -#define B_FE_CU_REG_COMM_INT_STA_FE_START__W 1 -#define B_FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 -#define B_FE_CU_REG_COMM_INT_STA_FT_START__B 1 -#define B_FE_CU_REG_COMM_INT_STA_FT_START__W 1 -#define B_FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 -#define B_FE_CU_REG_COMM_INT_STA_SB_START__B 2 -#define B_FE_CU_REG_COMM_INT_STA_SB_START__W 1 -#define B_FE_CU_REG_COMM_INT_STA_SB_START__M 0x4 -#define B_FE_CU_REG_COMM_INT_STA_NF_READY__B 3 -#define B_FE_CU_REG_COMM_INT_STA_NF_READY__W 1 -#define B_FE_CU_REG_COMM_INT_STA_NF_READY__M 0x8 - -#define B_FE_CU_REG_COMM_INT_MSK__A 0xC70008 -#define B_FE_CU_REG_COMM_INT_MSK__W 4 -#define B_FE_CU_REG_COMM_INT_MSK__M 0xF -#define B_FE_CU_REG_COMM_INT_MSK_FE_START__B 0 -#define B_FE_CU_REG_COMM_INT_MSK_FE_START__W 1 -#define B_FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 -#define B_FE_CU_REG_COMM_INT_MSK_FT_START__B 1 -#define B_FE_CU_REG_COMM_INT_MSK_FT_START__W 1 -#define B_FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 -#define B_FE_CU_REG_COMM_INT_MSK_SB_START__B 2 -#define B_FE_CU_REG_COMM_INT_MSK_SB_START__W 1 -#define B_FE_CU_REG_COMM_INT_MSK_SB_START__M 0x4 -#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__B 3 -#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__W 1 -#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__M 0x8 - -#define B_FE_CU_REG_MODE__A 0xC70010 -#define B_FE_CU_REG_MODE__W 5 -#define B_FE_CU_REG_MODE__M 0x1F -#define B_FE_CU_REG_MODE_INIT 0x0 - -#define B_FE_CU_REG_MODE_FFT__B 0 -#define B_FE_CU_REG_MODE_FFT__W 1 -#define B_FE_CU_REG_MODE_FFT__M 0x1 -#define B_FE_CU_REG_MODE_FFT_M8K 0x0 -#define B_FE_CU_REG_MODE_FFT_M2K 0x1 - -#define B_FE_CU_REG_MODE_COR__B 1 -#define B_FE_CU_REG_MODE_COR__W 1 -#define B_FE_CU_REG_MODE_COR__M 0x2 -#define B_FE_CU_REG_MODE_COR_OFF 0x0 -#define B_FE_CU_REG_MODE_COR_ON 0x2 - -#define B_FE_CU_REG_MODE_IFD__B 2 -#define B_FE_CU_REG_MODE_IFD__W 1 -#define B_FE_CU_REG_MODE_IFD__M 0x4 -#define B_FE_CU_REG_MODE_IFD_ENABLE 0x0 -#define B_FE_CU_REG_MODE_IFD_DISABLE 0x4 - -#define B_FE_CU_REG_MODE_SEL__B 3 -#define B_FE_CU_REG_MODE_SEL__W 1 -#define B_FE_CU_REG_MODE_SEL__M 0x8 -#define B_FE_CU_REG_MODE_SEL_COR 0x0 -#define B_FE_CU_REG_MODE_SEL_COR_NFC 0x8 - -#define B_FE_CU_REG_MODE_FES__B 4 -#define B_FE_CU_REG_MODE_FES__W 1 -#define B_FE_CU_REG_MODE_FES__M 0x10 -#define B_FE_CU_REG_MODE_FES_SEL_RST 0x0 -#define B_FE_CU_REG_MODE_FES_SEL_UPD 0x10 - -#define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 -#define B_FE_CU_REG_FRM_CNT_RST__W 15 -#define B_FE_CU_REG_FRM_CNT_RST__M 0x7FFF -#define B_FE_CU_REG_FRM_CNT_RST_INIT 0x20FF - -#define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 -#define B_FE_CU_REG_FRM_CNT_STR__W 15 -#define B_FE_CU_REG_FRM_CNT_STR__M 0x7FFF -#define B_FE_CU_REG_FRM_CNT_STR_INIT 0x1E - -#define B_FE_CU_REG_FRM_SMP_CNT__A 0xC70013 -#define B_FE_CU_REG_FRM_SMP_CNT__W 15 -#define B_FE_CU_REG_FRM_SMP_CNT__M 0x7FFF - -#define B_FE_CU_REG_FRM_SMB_CNT__A 0xC70014 -#define B_FE_CU_REG_FRM_SMB_CNT__W 16 -#define B_FE_CU_REG_FRM_SMB_CNT__M 0xFFFF - -#define B_FE_CU_REG_CMP_MAX_DAT__A 0xC70015 -#define B_FE_CU_REG_CMP_MAX_DAT__W 12 -#define B_FE_CU_REG_CMP_MAX_DAT__M 0xFFF - -#define B_FE_CU_REG_CMP_MAX_ADR__A 0xC70016 -#define B_FE_CU_REG_CMP_MAX_ADR__W 10 -#define B_FE_CU_REG_CMP_MAX_ADR__M 0x3FF - -#define B_FE_CU_REG_BUF_NFC_DEL__A 0xC7001F -#define B_FE_CU_REG_BUF_NFC_DEL__W 14 -#define B_FE_CU_REG_BUF_NFC_DEL__M 0x3FFF -#define B_FE_CU_REG_BUF_NFC_DEL_INIT 0x0 - -#define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 -#define B_FE_CU_REG_CTR_NFC_ICR__W 5 -#define B_FE_CU_REG_CTR_NFC_ICR__M 0x1F -#define B_FE_CU_REG_CTR_NFC_ICR_INIT 0x0 - -#define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 -#define B_FE_CU_REG_CTR_NFC_OCR__W 15 -#define B_FE_CU_REG_CTR_NFC_OCR__M 0x7FFF -#define B_FE_CU_REG_CTR_NFC_OCR_INIT 0x61A8 - -#define B_FE_CU_REG_CTR_NFC_CNT__A 0xC70022 -#define B_FE_CU_REG_CTR_NFC_CNT__W 15 -#define B_FE_CU_REG_CTR_NFC_CNT__M 0x7FFF - -#define B_FE_CU_REG_CTR_NFC_STS__A 0xC70023 -#define B_FE_CU_REG_CTR_NFC_STS__W 3 -#define B_FE_CU_REG_CTR_NFC_STS__M 0x7 -#define B_FE_CU_REG_CTR_NFC_STS_RUN 0x0 -#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_IMA 0x1 -#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_REA 0x2 -#define B_FE_CU_REG_CTR_NFC_STS_CNT_MAX 0x4 - -#define B_FE_CU_REG_DIV_NFC_REA__A 0xC70024 -#define B_FE_CU_REG_DIV_NFC_REA__W 14 -#define B_FE_CU_REG_DIV_NFC_REA__M 0x3FFF - -#define B_FE_CU_REG_DIV_NFC_IMA__A 0xC70025 -#define B_FE_CU_REG_DIV_NFC_IMA__W 14 -#define B_FE_CU_REG_DIV_NFC_IMA__M 0x3FFF - -#define B_FE_CU_REG_FRM_CNT_UPD__A 0xC70026 -#define B_FE_CU_REG_FRM_CNT_UPD__W 15 -#define B_FE_CU_REG_FRM_CNT_UPD__M 0x7FFF -#define B_FE_CU_REG_FRM_CNT_UPD_INIT 0x20FF - -#define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 -#define B_FE_CU_REG_DIV_NFC_CLP__W 2 -#define B_FE_CU_REG_DIV_NFC_CLP__M 0x3 -#define B_FE_CU_REG_DIV_NFC_CLP_INIT 0x1 -#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S11 0x0 -#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S12 0x1 -#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S13 0x2 -#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S14 0x3 - -#define B_FE_CU_BUF_RAM__A 0xC80000 - -#define B_FE_CU_CMP_RAM__A 0xC90000 - -#define B_FT_SID 0x8 - -#define B_FT_COMM_EXEC__A 0x1000000 -#define B_FT_COMM_EXEC__W 3 -#define B_FT_COMM_EXEC__M 0x7 -#define B_FT_COMM_EXEC_CTL__B 0 -#define B_FT_COMM_EXEC_CTL__W 3 -#define B_FT_COMM_EXEC_CTL__M 0x7 -#define B_FT_COMM_EXEC_CTL_STOP 0x0 -#define B_FT_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FT_COMM_EXEC_CTL_HOLD 0x2 -#define B_FT_COMM_EXEC_CTL_STEP 0x3 -#define B_FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_FT_COMM_STATE__A 0x1000001 -#define B_FT_COMM_STATE__W 16 -#define B_FT_COMM_STATE__M 0xFFFF -#define B_FT_COMM_MB__A 0x1000002 -#define B_FT_COMM_MB__W 16 -#define B_FT_COMM_MB__M 0xFFFF -#define B_FT_COMM_SERVICE0__A 0x1000003 -#define B_FT_COMM_SERVICE0__W 16 -#define B_FT_COMM_SERVICE0__M 0xFFFF -#define B_FT_COMM_SERVICE1__A 0x1000004 -#define B_FT_COMM_SERVICE1__W 16 -#define B_FT_COMM_SERVICE1__M 0xFFFF -#define B_FT_COMM_INT_STA__A 0x1000007 -#define B_FT_COMM_INT_STA__W 16 -#define B_FT_COMM_INT_STA__M 0xFFFF -#define B_FT_COMM_INT_MSK__A 0x1000008 -#define B_FT_COMM_INT_MSK__W 16 -#define B_FT_COMM_INT_MSK__M 0xFFFF - -#define B_FT_REG_COMM_EXEC__A 0x1010000 -#define B_FT_REG_COMM_EXEC__W 3 -#define B_FT_REG_COMM_EXEC__M 0x7 -#define B_FT_REG_COMM_EXEC_CTL__B 0 -#define B_FT_REG_COMM_EXEC_CTL__W 3 -#define B_FT_REG_COMM_EXEC_CTL__M 0x7 -#define B_FT_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FT_REG_COMM_MB__A 0x1010002 -#define B_FT_REG_COMM_MB__W 3 -#define B_FT_REG_COMM_MB__M 0x7 -#define B_FT_REG_COMM_MB_CTR__B 0 -#define B_FT_REG_COMM_MB_CTR__W 1 -#define B_FT_REG_COMM_MB_CTR__M 0x1 -#define B_FT_REG_COMM_MB_CTR_OFF 0x0 -#define B_FT_REG_COMM_MB_CTR_ON 0x1 -#define B_FT_REG_COMM_MB_OBS__B 1 -#define B_FT_REG_COMM_MB_OBS__W 1 -#define B_FT_REG_COMM_MB_OBS__M 0x2 -#define B_FT_REG_COMM_MB_OBS_OFF 0x0 -#define B_FT_REG_COMM_MB_OBS_ON 0x2 - -#define B_FT_REG_MODE_2K__A 0x1010010 -#define B_FT_REG_MODE_2K__W 1 -#define B_FT_REG_MODE_2K__M 0x1 -#define B_FT_REG_MODE_2K_MODE_8K 0x0 -#define B_FT_REG_MODE_2K_MODE_2K 0x1 -#define B_FT_REG_MODE_2K_INIT 0x0 - -#define B_FT_REG_NORM_OFF__A 0x1010016 -#define B_FT_REG_NORM_OFF__W 4 -#define B_FT_REG_NORM_OFF__M 0xF -#define B_FT_REG_NORM_OFF_INIT 0x2 - -#define B_FT_ST1_RAM__A 0x1020000 - -#define B_FT_ST2_RAM__A 0x1030000 - -#define B_FT_ST3_RAM__A 0x1040000 - -#define B_FT_ST5_RAM__A 0x1050000 - -#define B_FT_ST6_RAM__A 0x1060000 - -#define B_FT_ST8_RAM__A 0x1070000 - -#define B_FT_ST9_RAM__A 0x1080000 - -#define B_CP_SID 0x9 - -#define B_CP_COMM_EXEC__A 0x1400000 -#define B_CP_COMM_EXEC__W 3 -#define B_CP_COMM_EXEC__M 0x7 -#define B_CP_COMM_EXEC_CTL__B 0 -#define B_CP_COMM_EXEC_CTL__W 3 -#define B_CP_COMM_EXEC_CTL__M 0x7 -#define B_CP_COMM_EXEC_CTL_STOP 0x0 -#define B_CP_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CP_COMM_EXEC_CTL_HOLD 0x2 -#define B_CP_COMM_EXEC_CTL_STEP 0x3 -#define B_CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_CP_COMM_STATE__A 0x1400001 -#define B_CP_COMM_STATE__W 16 -#define B_CP_COMM_STATE__M 0xFFFF -#define B_CP_COMM_MB__A 0x1400002 -#define B_CP_COMM_MB__W 16 -#define B_CP_COMM_MB__M 0xFFFF -#define B_CP_COMM_SERVICE0__A 0x1400003 -#define B_CP_COMM_SERVICE0__W 16 -#define B_CP_COMM_SERVICE0__M 0xFFFF -#define B_CP_COMM_SERVICE1__A 0x1400004 -#define B_CP_COMM_SERVICE1__W 16 -#define B_CP_COMM_SERVICE1__M 0xFFFF -#define B_CP_COMM_INT_STA__A 0x1400007 -#define B_CP_COMM_INT_STA__W 16 -#define B_CP_COMM_INT_STA__M 0xFFFF -#define B_CP_COMM_INT_MSK__A 0x1400008 -#define B_CP_COMM_INT_MSK__W 16 -#define B_CP_COMM_INT_MSK__M 0xFFFF - -#define B_CP_REG_COMM_EXEC__A 0x1410000 -#define B_CP_REG_COMM_EXEC__W 3 -#define B_CP_REG_COMM_EXEC__M 0x7 -#define B_CP_REG_COMM_EXEC_CTL__B 0 -#define B_CP_REG_COMM_EXEC_CTL__W 3 -#define B_CP_REG_COMM_EXEC_CTL__M 0x7 -#define B_CP_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CP_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_CP_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_CP_REG_COMM_MB__A 0x1410002 -#define B_CP_REG_COMM_MB__W 3 -#define B_CP_REG_COMM_MB__M 0x7 -#define B_CP_REG_COMM_MB_CTR__B 0 -#define B_CP_REG_COMM_MB_CTR__W 1 -#define B_CP_REG_COMM_MB_CTR__M 0x1 -#define B_CP_REG_COMM_MB_CTR_OFF 0x0 -#define B_CP_REG_COMM_MB_CTR_ON 0x1 -#define B_CP_REG_COMM_MB_OBS__B 1 -#define B_CP_REG_COMM_MB_OBS__W 1 -#define B_CP_REG_COMM_MB_OBS__M 0x2 -#define B_CP_REG_COMM_MB_OBS_OFF 0x0 -#define B_CP_REG_COMM_MB_OBS_ON 0x2 - -#define B_CP_REG_COMM_SERVICE0__A 0x1410003 -#define B_CP_REG_COMM_SERVICE0__W 10 -#define B_CP_REG_COMM_SERVICE0__M 0x3FF -#define B_CP_REG_COMM_SERVICE0_CP__B 9 -#define B_CP_REG_COMM_SERVICE0_CP__W 1 -#define B_CP_REG_COMM_SERVICE0_CP__M 0x200 - -#define B_CP_REG_COMM_SERVICE1__A 0x1410004 -#define B_CP_REG_COMM_SERVICE1__W 11 -#define B_CP_REG_COMM_SERVICE1__M 0x7FF - -#define B_CP_REG_COMM_INT_STA__A 0x1410007 -#define B_CP_REG_COMM_INT_STA__W 2 -#define B_CP_REG_COMM_INT_STA__M 0x3 -#define B_CP_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define B_CP_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define B_CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define B_CP_REG_COMM_INT_MSK__A 0x1410008 -#define B_CP_REG_COMM_INT_MSK__W 2 -#define B_CP_REG_COMM_INT_MSK__M 0x3 -#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - -#define B_CP_REG_MODE_2K__A 0x1410010 -#define B_CP_REG_MODE_2K__W 1 -#define B_CP_REG_MODE_2K__M 0x1 -#define B_CP_REG_MODE_2K_INIT 0x0 - -#define B_CP_REG_INTERVAL__A 0x1410011 -#define B_CP_REG_INTERVAL__W 4 -#define B_CP_REG_INTERVAL__M 0xF -#define B_CP_REG_INTERVAL_INIT 0x5 - -#define B_CP_REG_DETECT_ENA__A 0x1410012 -#define B_CP_REG_DETECT_ENA__W 2 -#define B_CP_REG_DETECT_ENA__M 0x3 - -#define B_CP_REG_DETECT_ENA_SCATTERED__B 0 -#define B_CP_REG_DETECT_ENA_SCATTERED__W 1 -#define B_CP_REG_DETECT_ENA_SCATTERED__M 0x1 - -#define B_CP_REG_DETECT_ENA_CONTINUOUS__B 1 -#define B_CP_REG_DETECT_ENA_CONTINUOUS__W 1 -#define B_CP_REG_DETECT_ENA_CONTINUOUS__M 0x2 -#define B_CP_REG_DETECT_ENA_INIT 0x0 - -#define B_CP_REG_BR_SMB_NR__A 0x1410021 -#define B_CP_REG_BR_SMB_NR__W 4 -#define B_CP_REG_BR_SMB_NR__M 0xF - -#define B_CP_REG_BR_SMB_NR_SMB__B 0 -#define B_CP_REG_BR_SMB_NR_SMB__W 2 -#define B_CP_REG_BR_SMB_NR_SMB__M 0x3 - -#define B_CP_REG_BR_SMB_NR_VAL__B 2 -#define B_CP_REG_BR_SMB_NR_VAL__W 1 -#define B_CP_REG_BR_SMB_NR_VAL__M 0x4 - -#define B_CP_REG_BR_SMB_NR_OFFSET__B 3 -#define B_CP_REG_BR_SMB_NR_OFFSET__W 1 -#define B_CP_REG_BR_SMB_NR_OFFSET__M 0x8 -#define B_CP_REG_BR_SMB_NR_INIT 0x0 - -#define B_CP_REG_BR_CP_SMB_NR__A 0x1410022 -#define B_CP_REG_BR_CP_SMB_NR__W 2 -#define B_CP_REG_BR_CP_SMB_NR__M 0x3 -#define B_CP_REG_BR_CP_SMB_NR_INIT 0x0 - -#define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 -#define B_CP_REG_BR_SPL_OFFSET__W 3 -#define B_CP_REG_BR_SPL_OFFSET__M 0x7 -#define B_CP_REG_BR_SPL_OFFSET_INIT 0x0 - -#define B_CP_REG_BR_STR_DEL__A 0x1410024 -#define B_CP_REG_BR_STR_DEL__W 10 -#define B_CP_REG_BR_STR_DEL__M 0x3FF -#define B_CP_REG_BR_STR_DEL_INIT 0xA - -#define B_CP_REG_BR_EXP_ADJ__A 0x1410025 -#define B_CP_REG_BR_EXP_ADJ__W 5 -#define B_CP_REG_BR_EXP_ADJ__M 0x1F -#define B_CP_REG_BR_EXP_ADJ_INIT 0x10 - -#define B_CP_REG_RT_ANG_INC0__A 0x1410030 -#define B_CP_REG_RT_ANG_INC0__W 16 -#define B_CP_REG_RT_ANG_INC0__M 0xFFFF -#define B_CP_REG_RT_ANG_INC0_INIT 0x0 - -#define B_CP_REG_RT_ANG_INC1__A 0x1410031 -#define B_CP_REG_RT_ANG_INC1__W 8 -#define B_CP_REG_RT_ANG_INC1__M 0xFF -#define B_CP_REG_RT_ANG_INC1_INIT 0x0 - -#define B_CP_REG_RT_SPD_EXP_MARG__A 0x1410032 -#define B_CP_REG_RT_SPD_EXP_MARG__W 5 -#define B_CP_REG_RT_SPD_EXP_MARG__M 0x1F -#define B_CP_REG_RT_SPD_EXP_MARG_INIT 0x5 - -#define B_CP_REG_RT_DETECT_TRH__A 0x1410033 -#define B_CP_REG_RT_DETECT_TRH__W 2 -#define B_CP_REG_RT_DETECT_TRH__M 0x3 -#define B_CP_REG_RT_DETECT_TRH_INIT 0x3 - -#define B_CP_REG_RT_SPD_RELIABLE__A 0x1410034 -#define B_CP_REG_RT_SPD_RELIABLE__W 3 -#define B_CP_REG_RT_SPD_RELIABLE__M 0x7 -#define B_CP_REG_RT_SPD_RELIABLE_INIT 0x0 - -#define B_CP_REG_RT_SPD_DIRECTION__A 0x1410035 -#define B_CP_REG_RT_SPD_DIRECTION__W 1 -#define B_CP_REG_RT_SPD_DIRECTION__M 0x1 -#define B_CP_REG_RT_SPD_DIRECTION_INIT 0x0 - -#define B_CP_REG_RT_SPD_MOD__A 0x1410036 -#define B_CP_REG_RT_SPD_MOD__W 2 -#define B_CP_REG_RT_SPD_MOD__M 0x3 -#define B_CP_REG_RT_SPD_MOD_INIT 0x0 - -#define B_CP_REG_RT_SPD_SMB__A 0x1410037 -#define B_CP_REG_RT_SPD_SMB__W 2 -#define B_CP_REG_RT_SPD_SMB__M 0x3 -#define B_CP_REG_RT_SPD_SMB_INIT 0x0 - -#define B_CP_REG_RT_CPD_MODE__A 0x1410038 -#define B_CP_REG_RT_CPD_MODE__W 3 -#define B_CP_REG_RT_CPD_MODE__M 0x7 - -#define B_CP_REG_RT_CPD_MODE_MOD3__B 0 -#define B_CP_REG_RT_CPD_MODE_MOD3__W 2 -#define B_CP_REG_RT_CPD_MODE_MOD3__M 0x3 - -#define B_CP_REG_RT_CPD_MODE_ADD__B 2 -#define B_CP_REG_RT_CPD_MODE_ADD__W 1 -#define B_CP_REG_RT_CPD_MODE_ADD__M 0x4 -#define B_CP_REG_RT_CPD_MODE_INIT 0x0 - -#define B_CP_REG_RT_CPD_RELIABLE__A 0x1410039 -#define B_CP_REG_RT_CPD_RELIABLE__W 3 -#define B_CP_REG_RT_CPD_RELIABLE__M 0x7 -#define B_CP_REG_RT_CPD_RELIABLE_INIT 0x0 - -#define B_CP_REG_RT_CPD_BIN__A 0x141003A -#define B_CP_REG_RT_CPD_BIN__W 5 -#define B_CP_REG_RT_CPD_BIN__M 0x1F -#define B_CP_REG_RT_CPD_BIN_INIT 0x0 - -#define B_CP_REG_RT_CPD_MAX__A 0x141003B -#define B_CP_REG_RT_CPD_MAX__W 4 -#define B_CP_REG_RT_CPD_MAX__M 0xF -#define B_CP_REG_RT_CPD_MAX_INIT 0x0 - -#define B_CP_REG_RT_SUPR_VAL__A 0x141003C -#define B_CP_REG_RT_SUPR_VAL__W 2 -#define B_CP_REG_RT_SUPR_VAL__M 0x3 - -#define B_CP_REG_RT_SUPR_VAL_CE__B 0 -#define B_CP_REG_RT_SUPR_VAL_CE__W 1 -#define B_CP_REG_RT_SUPR_VAL_CE__M 0x1 - -#define B_CP_REG_RT_SUPR_VAL_DL__B 1 -#define B_CP_REG_RT_SUPR_VAL_DL__W 1 -#define B_CP_REG_RT_SUPR_VAL_DL__M 0x2 -#define B_CP_REG_RT_SUPR_VAL_INIT 0x0 - -#define B_CP_REG_RT_EXP_AVE__A 0x141003D -#define B_CP_REG_RT_EXP_AVE__W 5 -#define B_CP_REG_RT_EXP_AVE__M 0x1F -#define B_CP_REG_RT_EXP_AVE_INIT 0x0 - -#define B_CP_REG_RT_CPD_EXP_MARG__A 0x141003E -#define B_CP_REG_RT_CPD_EXP_MARG__W 5 -#define B_CP_REG_RT_CPD_EXP_MARG__M 0x1F -#define B_CP_REG_RT_CPD_EXP_MARG_INIT 0x3 - -#define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 -#define B_CP_REG_AC_NEXP_OFFS__W 8 -#define B_CP_REG_AC_NEXP_OFFS__M 0xFF -#define B_CP_REG_AC_NEXP_OFFS_INIT 0x0 - -#define B_CP_REG_AC_AVER_POW__A 0x1410041 -#define B_CP_REG_AC_AVER_POW__W 8 -#define B_CP_REG_AC_AVER_POW__M 0xFF -#define B_CP_REG_AC_AVER_POW_INIT 0x5F - -#define B_CP_REG_AC_MAX_POW__A 0x1410042 -#define B_CP_REG_AC_MAX_POW__W 8 -#define B_CP_REG_AC_MAX_POW__M 0xFF -#define B_CP_REG_AC_MAX_POW_INIT 0x7A - -#define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 -#define B_CP_REG_AC_WEIGHT_MAN__W 6 -#define B_CP_REG_AC_WEIGHT_MAN__M 0x3F -#define B_CP_REG_AC_WEIGHT_MAN_INIT 0x31 - -#define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 -#define B_CP_REG_AC_WEIGHT_EXP__W 5 -#define B_CP_REG_AC_WEIGHT_EXP__M 0x1F -#define B_CP_REG_AC_WEIGHT_EXP_INIT 0x10 - -#define B_CP_REG_AC_GAIN_MAN__A 0x1410045 -#define B_CP_REG_AC_GAIN_MAN__W 16 -#define B_CP_REG_AC_GAIN_MAN__M 0xFFFF -#define B_CP_REG_AC_GAIN_MAN_INIT 0x0 - -#define B_CP_REG_AC_GAIN_EXP__A 0x1410046 -#define B_CP_REG_AC_GAIN_EXP__W 5 -#define B_CP_REG_AC_GAIN_EXP__M 0x1F -#define B_CP_REG_AC_GAIN_EXP_INIT 0x0 - -#define B_CP_REG_AC_AMP_MODE__A 0x1410047 -#define B_CP_REG_AC_AMP_MODE__W 2 -#define B_CP_REG_AC_AMP_MODE__M 0x3 -#define B_CP_REG_AC_AMP_MODE_NEW 0x0 -#define B_CP_REG_AC_AMP_MODE_OLD 0x1 -#define B_CP_REG_AC_AMP_MODE_FIXED 0x2 -#define B_CP_REG_AC_AMP_MODE_INIT 0x2 - -#define B_CP_REG_AC_AMP_FIX__A 0x1410048 -#define B_CP_REG_AC_AMP_FIX__W 14 -#define B_CP_REG_AC_AMP_FIX__M 0x3FFF -#define B_CP_REG_AC_AMP_FIX_INIT 0x1FF - -#define B_CP_REG_AC_AMP_READ__A 0x1410049 -#define B_CP_REG_AC_AMP_READ__W 14 -#define B_CP_REG_AC_AMP_READ__M 0x3FFF -#define B_CP_REG_AC_AMP_READ_INIT 0x0 - -#define B_CP_REG_AC_ANG_MODE__A 0x141004A -#define B_CP_REG_AC_ANG_MODE__W 2 -#define B_CP_REG_AC_ANG_MODE__M 0x3 -#define B_CP_REG_AC_ANG_MODE_NEW 0x0 -#define B_CP_REG_AC_ANG_MODE_OLD 0x1 -#define B_CP_REG_AC_ANG_MODE_NO_INT 0x2 -#define B_CP_REG_AC_ANG_MODE_OFFSET 0x3 -#define B_CP_REG_AC_ANG_MODE_INIT 0x3 - -#define B_CP_REG_AC_ANG_OFFS__A 0x141004B -#define B_CP_REG_AC_ANG_OFFS__W 14 -#define B_CP_REG_AC_ANG_OFFS__M 0x3FFF -#define B_CP_REG_AC_ANG_OFFS_INIT 0x0 - -#define B_CP_REG_AC_ANG_READ__A 0x141004C -#define B_CP_REG_AC_ANG_READ__W 16 -#define B_CP_REG_AC_ANG_READ__M 0xFFFF -#define B_CP_REG_AC_ANG_READ_INIT 0x0 - -#define B_CP_REG_AC_ACCU_REAL0__A 0x1410060 -#define B_CP_REG_AC_ACCU_REAL0__W 8 -#define B_CP_REG_AC_ACCU_REAL0__M 0xFF -#define B_CP_REG_AC_ACCU_REAL0_INIT 0x0 - -#define B_CP_REG_AC_ACCU_IMAG0__A 0x1410061 -#define B_CP_REG_AC_ACCU_IMAG0__W 8 -#define B_CP_REG_AC_ACCU_IMAG0__M 0xFF -#define B_CP_REG_AC_ACCU_IMAG0_INIT 0x0 - -#define B_CP_REG_AC_ACCU_REAL1__A 0x1410062 -#define B_CP_REG_AC_ACCU_REAL1__W 8 -#define B_CP_REG_AC_ACCU_REAL1__M 0xFF -#define B_CP_REG_AC_ACCU_REAL1_INIT 0x0 - -#define B_CP_REG_AC_ACCU_IMAG1__A 0x1410063 -#define B_CP_REG_AC_ACCU_IMAG1__W 8 -#define B_CP_REG_AC_ACCU_IMAG1__M 0xFF -#define B_CP_REG_AC_ACCU_IMAG1_INIT 0x0 - -#define B_CP_REG_DL_MB_WR_ADDR__A 0x1410050 -#define B_CP_REG_DL_MB_WR_ADDR__W 15 -#define B_CP_REG_DL_MB_WR_ADDR__M 0x7FFF -#define B_CP_REG_DL_MB_WR_ADDR_INIT 0x0 - -#define B_CP_REG_DL_MB_WR_CTR__A 0x1410051 -#define B_CP_REG_DL_MB_WR_CTR__W 5 -#define B_CP_REG_DL_MB_WR_CTR__M 0x1F - -#define B_CP_REG_DL_MB_WR_CTR_WORD__B 2 -#define B_CP_REG_DL_MB_WR_CTR_WORD__W 3 -#define B_CP_REG_DL_MB_WR_CTR_WORD__M 0x1C - -#define B_CP_REG_DL_MB_WR_CTR_OBS__B 1 -#define B_CP_REG_DL_MB_WR_CTR_OBS__W 1 -#define B_CP_REG_DL_MB_WR_CTR_OBS__M 0x2 - -#define B_CP_REG_DL_MB_WR_CTR_CTR__B 0 -#define B_CP_REG_DL_MB_WR_CTR_CTR__W 1 -#define B_CP_REG_DL_MB_WR_CTR_CTR__M 0x1 -#define B_CP_REG_DL_MB_WR_CTR_INIT 0x0 - -#define B_CP_REG_DL_MB_RD_ADDR__A 0x1410052 -#define B_CP_REG_DL_MB_RD_ADDR__W 15 -#define B_CP_REG_DL_MB_RD_ADDR__M 0x7FFF -#define B_CP_REG_DL_MB_RD_ADDR_INIT 0x0 - -#define B_CP_REG_DL_MB_RD_CTR__A 0x1410053 -#define B_CP_REG_DL_MB_RD_CTR__W 11 -#define B_CP_REG_DL_MB_RD_CTR__M 0x7FF - -#define B_CP_REG_DL_MB_RD_CTR_TEST__B 10 -#define B_CP_REG_DL_MB_RD_CTR_TEST__W 1 -#define B_CP_REG_DL_MB_RD_CTR_TEST__M 0x400 - -#define B_CP_REG_DL_MB_RD_CTR_OFFSET__B 8 -#define B_CP_REG_DL_MB_RD_CTR_OFFSET__W 2 -#define B_CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 - -#define B_CP_REG_DL_MB_RD_CTR_VALID__B 5 -#define B_CP_REG_DL_MB_RD_CTR_VALID__W 3 -#define B_CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 - -#define B_CP_REG_DL_MB_RD_CTR_WORD__B 2 -#define B_CP_REG_DL_MB_RD_CTR_WORD__W 3 -#define B_CP_REG_DL_MB_RD_CTR_WORD__M 0x1C - -#define B_CP_REG_DL_MB_RD_CTR_OBS__B 1 -#define B_CP_REG_DL_MB_RD_CTR_OBS__W 1 -#define B_CP_REG_DL_MB_RD_CTR_OBS__M 0x2 - -#define B_CP_REG_DL_MB_RD_CTR_CTR__B 0 -#define B_CP_REG_DL_MB_RD_CTR_CTR__W 1 -#define B_CP_REG_DL_MB_RD_CTR_CTR__M 0x1 -#define B_CP_REG_DL_MB_RD_CTR_INIT 0x0 - -#define B_CP_BR_BUF_RAM__A 0x1420000 - -#define B_CP_BR_CPL_RAM__A 0x1430000 - -#define B_CP_PB_DL0_RAM__A 0x1440000 - -#define B_CP_PB_DL1_RAM__A 0x1450000 - -#define B_CP_PB_DL2_RAM__A 0x1460000 - -#define B_CE_SID 0xA - -#define B_CE_COMM_EXEC__A 0x1800000 -#define B_CE_COMM_EXEC__W 3 -#define B_CE_COMM_EXEC__M 0x7 -#define B_CE_COMM_EXEC_CTL__B 0 -#define B_CE_COMM_EXEC_CTL__W 3 -#define B_CE_COMM_EXEC_CTL__M 0x7 -#define B_CE_COMM_EXEC_CTL_STOP 0x0 -#define B_CE_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CE_COMM_EXEC_CTL_HOLD 0x2 -#define B_CE_COMM_EXEC_CTL_STEP 0x3 -#define B_CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_CE_COMM_STATE__A 0x1800001 -#define B_CE_COMM_STATE__W 16 -#define B_CE_COMM_STATE__M 0xFFFF -#define B_CE_COMM_MB__A 0x1800002 -#define B_CE_COMM_MB__W 16 -#define B_CE_COMM_MB__M 0xFFFF -#define B_CE_COMM_SERVICE0__A 0x1800003 -#define B_CE_COMM_SERVICE0__W 16 -#define B_CE_COMM_SERVICE0__M 0xFFFF -#define B_CE_COMM_SERVICE1__A 0x1800004 -#define B_CE_COMM_SERVICE1__W 16 -#define B_CE_COMM_SERVICE1__M 0xFFFF -#define B_CE_COMM_INT_STA__A 0x1800007 -#define B_CE_COMM_INT_STA__W 16 -#define B_CE_COMM_INT_STA__M 0xFFFF -#define B_CE_COMM_INT_MSK__A 0x1800008 -#define B_CE_COMM_INT_MSK__W 16 -#define B_CE_COMM_INT_MSK__M 0xFFFF - -#define B_CE_REG_COMM_EXEC__A 0x1810000 -#define B_CE_REG_COMM_EXEC__W 3 -#define B_CE_REG_COMM_EXEC__M 0x7 -#define B_CE_REG_COMM_EXEC_CTL__B 0 -#define B_CE_REG_COMM_EXEC_CTL__W 3 -#define B_CE_REG_COMM_EXEC_CTL__M 0x7 -#define B_CE_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CE_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_CE_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_CE_REG_COMM_MB__A 0x1810002 -#define B_CE_REG_COMM_MB__W 4 -#define B_CE_REG_COMM_MB__M 0xF -#define B_CE_REG_COMM_MB_CTR__B 0 -#define B_CE_REG_COMM_MB_CTR__W 1 -#define B_CE_REG_COMM_MB_CTR__M 0x1 -#define B_CE_REG_COMM_MB_CTR_OFF 0x0 -#define B_CE_REG_COMM_MB_CTR_ON 0x1 -#define B_CE_REG_COMM_MB_OBS__B 1 -#define B_CE_REG_COMM_MB_OBS__W 1 -#define B_CE_REG_COMM_MB_OBS__M 0x2 -#define B_CE_REG_COMM_MB_OBS_OFF 0x0 -#define B_CE_REG_COMM_MB_OBS_ON 0x2 -#define B_CE_REG_COMM_MB_OBS_SEL__B 2 -#define B_CE_REG_COMM_MB_OBS_SEL__W 2 -#define B_CE_REG_COMM_MB_OBS_SEL__M 0xC -#define B_CE_REG_COMM_MB_OBS_SEL_FI 0x0 -#define B_CE_REG_COMM_MB_OBS_SEL_TP 0x4 -#define B_CE_REG_COMM_MB_OBS_SEL_TI 0x8 -#define B_CE_REG_COMM_MB_OBS_SEL_FR 0x8 - -#define B_CE_REG_COMM_SERVICE0__A 0x1810003 -#define B_CE_REG_COMM_SERVICE0__W 10 -#define B_CE_REG_COMM_SERVICE0__M 0x3FF -#define B_CE_REG_COMM_SERVICE0_FT__B 8 -#define B_CE_REG_COMM_SERVICE0_FT__W 1 -#define B_CE_REG_COMM_SERVICE0_FT__M 0x100 - -#define B_CE_REG_COMM_SERVICE1__A 0x1810004 -#define B_CE_REG_COMM_SERVICE1__W 11 -#define B_CE_REG_COMM_SERVICE1__M 0x7FF - -#define B_CE_REG_COMM_INT_STA__A 0x1810007 -#define B_CE_REG_COMM_INT_STA__W 3 -#define B_CE_REG_COMM_INT_STA__M 0x7 -#define B_CE_REG_COMM_INT_STA_CE_PE__B 0 -#define B_CE_REG_COMM_INT_STA_CE_PE__W 1 -#define B_CE_REG_COMM_INT_STA_CE_PE__M 0x1 -#define B_CE_REG_COMM_INT_STA_CE_IR__B 1 -#define B_CE_REG_COMM_INT_STA_CE_IR__W 1 -#define B_CE_REG_COMM_INT_STA_CE_IR__M 0x2 -#define B_CE_REG_COMM_INT_STA_CE_FI__B 2 -#define B_CE_REG_COMM_INT_STA_CE_FI__W 1 -#define B_CE_REG_COMM_INT_STA_CE_FI__M 0x4 - -#define B_CE_REG_COMM_INT_MSK__A 0x1810008 -#define B_CE_REG_COMM_INT_MSK__W 3 -#define B_CE_REG_COMM_INT_MSK__M 0x7 -#define B_CE_REG_COMM_INT_MSK_CE_PE__B 0 -#define B_CE_REG_COMM_INT_MSK_CE_PE__W 1 -#define B_CE_REG_COMM_INT_MSK_CE_PE__M 0x1 -#define B_CE_REG_COMM_INT_MSK_CE_IR__B 1 -#define B_CE_REG_COMM_INT_MSK_CE_IR__W 1 -#define B_CE_REG_COMM_INT_MSK_CE_IR__M 0x2 -#define B_CE_REG_COMM_INT_MSK_CE_FI__B 2 -#define B_CE_REG_COMM_INT_MSK_CE_FI__W 1 -#define B_CE_REG_COMM_INT_MSK_CE_FI__M 0x4 - -#define B_CE_REG_2K__A 0x1810010 -#define B_CE_REG_2K__W 1 -#define B_CE_REG_2K__M 0x1 -#define B_CE_REG_2K_INIT 0x0 - -#define B_CE_REG_TAPSET__A 0x1810011 -#define B_CE_REG_TAPSET__W 4 -#define B_CE_REG_TAPSET__M 0xF - -#define B_CE_REG_TAPSET_MOTION_INIT 0x0 - -#define B_CE_REG_TAPSET_MOTION_NO 0x0 - -#define B_CE_REG_TAPSET_MOTION_LOW 0x1 - -#define B_CE_REG_TAPSET_MOTION_HIGH 0x2 - -#define B_CE_REG_TAPSET_MOTION_HIGH2 0x4 - -#define B_CE_REG_TAPSET_MOTION_UNDEFINED 0x8 - -#define B_CE_REG_AVG_POW__A 0x1810012 -#define B_CE_REG_AVG_POW__W 8 -#define B_CE_REG_AVG_POW__M 0xFF -#define B_CE_REG_AVG_POW_INIT 0x0 - -#define B_CE_REG_MAX_POW__A 0x1810013 -#define B_CE_REG_MAX_POW__W 8 -#define B_CE_REG_MAX_POW__M 0xFF -#define B_CE_REG_MAX_POW_INIT 0x0 - -#define B_CE_REG_ATT__A 0x1810014 -#define B_CE_REG_ATT__W 8 -#define B_CE_REG_ATT__M 0xFF -#define B_CE_REG_ATT_INIT 0x0 - -#define B_CE_REG_NRED__A 0x1810015 -#define B_CE_REG_NRED__W 6 -#define B_CE_REG_NRED__M 0x3F -#define B_CE_REG_NRED_INIT 0x0 - -#define B_CE_REG_PU_SIGN__A 0x1810020 -#define B_CE_REG_PU_SIGN__W 1 -#define B_CE_REG_PU_SIGN__M 0x1 -#define B_CE_REG_PU_SIGN_INIT 0x0 - -#define B_CE_REG_PU_MIX__A 0x1810021 -#define B_CE_REG_PU_MIX__W 1 -#define B_CE_REG_PU_MIX__M 0x1 -#define B_CE_REG_PU_MIX_INIT 0x0 - -#define B_CE_REG_PB_PILOT_REQ__A 0x1810030 -#define B_CE_REG_PB_PILOT_REQ__W 15 -#define B_CE_REG_PB_PILOT_REQ__M 0x7FFF -#define B_CE_REG_PB_PILOT_REQ_INIT 0x0 -#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 -#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 -#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 -#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 -#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 -#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF - -#define B_CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 -#define B_CE_REG_PB_PILOT_REQ_VALID__W 1 -#define B_CE_REG_PB_PILOT_REQ_VALID__M 0x1 -#define B_CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 - -#define B_CE_REG_PB_FREEZE__A 0x1810032 -#define B_CE_REG_PB_FREEZE__W 1 -#define B_CE_REG_PB_FREEZE__M 0x1 -#define B_CE_REG_PB_FREEZE_INIT 0x0 - -#define B_CE_REG_PB_PILOT_EXP__A 0x1810038 -#define B_CE_REG_PB_PILOT_EXP__W 4 -#define B_CE_REG_PB_PILOT_EXP__M 0xF -#define B_CE_REG_PB_PILOT_EXP_INIT 0x0 - -#define B_CE_REG_PB_PILOT_REAL__A 0x1810039 -#define B_CE_REG_PB_PILOT_REAL__W 10 -#define B_CE_REG_PB_PILOT_REAL__M 0x3FF -#define B_CE_REG_PB_PILOT_REAL_INIT 0x0 - -#define B_CE_REG_PB_PILOT_IMAG__A 0x181003A -#define B_CE_REG_PB_PILOT_IMAG__W 10 -#define B_CE_REG_PB_PILOT_IMAG__M 0x3FF -#define B_CE_REG_PB_PILOT_IMAG_INIT 0x0 - -#define B_CE_REG_PB_SMBNR__A 0x181003B -#define B_CE_REG_PB_SMBNR__W 5 -#define B_CE_REG_PB_SMBNR__M 0x1F -#define B_CE_REG_PB_SMBNR_INIT 0x0 - -#define B_CE_REG_NE_PILOT_REQ__A 0x1810040 -#define B_CE_REG_NE_PILOT_REQ__W 12 -#define B_CE_REG_NE_PILOT_REQ__M 0xFFF -#define B_CE_REG_NE_PILOT_REQ_INIT 0x0 - -#define B_CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 -#define B_CE_REG_NE_PILOT_REQ_VALID__W 2 -#define B_CE_REG_NE_PILOT_REQ_VALID__M 0x3 -#define B_CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 -#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 -#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 -#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 -#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 -#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 -#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 - -#define B_CE_REG_NE_PILOT_DATA__A 0x1810042 -#define B_CE_REG_NE_PILOT_DATA__W 10 -#define B_CE_REG_NE_PILOT_DATA__M 0x3FF -#define B_CE_REG_NE_PILOT_DATA_INIT 0x0 - -#define B_CE_REG_NE_ERR_SELECT__A 0x1810043 -#define B_CE_REG_NE_ERR_SELECT__W 5 -#define B_CE_REG_NE_ERR_SELECT__M 0x1F -#define B_CE_REG_NE_ERR_SELECT_INIT 0x7 - -#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__B 4 -#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__W 1 -#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__M 0x10 - -#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__B 3 -#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__W 1 -#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__M 0x8 - -#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 -#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 -#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 - -#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 -#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 -#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 - -#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 -#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 -#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 - -#define B_CE_REG_NE_TD_CAL__A 0x1810044 -#define B_CE_REG_NE_TD_CAL__W 9 -#define B_CE_REG_NE_TD_CAL__M 0x1FF -#define B_CE_REG_NE_TD_CAL_INIT 0x1E8 - -#define B_CE_REG_NE_FD_CAL__A 0x1810045 -#define B_CE_REG_NE_FD_CAL__W 9 -#define B_CE_REG_NE_FD_CAL__M 0x1FF -#define B_CE_REG_NE_FD_CAL_INIT 0x1D9 - -#define B_CE_REG_NE_MIXAVG__A 0x1810046 -#define B_CE_REG_NE_MIXAVG__W 3 -#define B_CE_REG_NE_MIXAVG__M 0x7 -#define B_CE_REG_NE_MIXAVG_INIT 0x6 - -#define B_CE_REG_NE_NUPD_OFS__A 0x1810047 -#define B_CE_REG_NE_NUPD_OFS__W 4 -#define B_CE_REG_NE_NUPD_OFS__M 0xF -#define B_CE_REG_NE_NUPD_OFS_INIT 0x4 - -#define B_CE_REG_NE_TD_POW__A 0x1810048 -#define B_CE_REG_NE_TD_POW__W 15 -#define B_CE_REG_NE_TD_POW__M 0x7FFF -#define B_CE_REG_NE_TD_POW_INIT 0x0 - -#define B_CE_REG_NE_TD_POW_EXPONENT__B 10 -#define B_CE_REG_NE_TD_POW_EXPONENT__W 5 -#define B_CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 - -#define B_CE_REG_NE_TD_POW_MANTISSA__B 0 -#define B_CE_REG_NE_TD_POW_MANTISSA__W 10 -#define B_CE_REG_NE_TD_POW_MANTISSA__M 0x3FF - -#define B_CE_REG_NE_FD_POW__A 0x1810049 -#define B_CE_REG_NE_FD_POW__W 15 -#define B_CE_REG_NE_FD_POW__M 0x7FFF -#define B_CE_REG_NE_FD_POW_INIT 0x0 - -#define B_CE_REG_NE_FD_POW_EXPONENT__B 10 -#define B_CE_REG_NE_FD_POW_EXPONENT__W 5 -#define B_CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 - -#define B_CE_REG_NE_FD_POW_MANTISSA__B 0 -#define B_CE_REG_NE_FD_POW_MANTISSA__W 10 -#define B_CE_REG_NE_FD_POW_MANTISSA__M 0x3FF - -#define B_CE_REG_NE_NEXP_AVG__A 0x181004A -#define B_CE_REG_NE_NEXP_AVG__W 8 -#define B_CE_REG_NE_NEXP_AVG__M 0xFF -#define B_CE_REG_NE_NEXP_AVG_INIT 0x0 - -#define B_CE_REG_NE_OFFSET__A 0x181004B -#define B_CE_REG_NE_OFFSET__W 9 -#define B_CE_REG_NE_OFFSET__M 0x1FF -#define B_CE_REG_NE_OFFSET_INIT 0x0 - -#define B_CE_REG_NE_NUPD_TRH__A 0x181004C -#define B_CE_REG_NE_NUPD_TRH__W 5 -#define B_CE_REG_NE_NUPD_TRH__M 0x1F -#define B_CE_REG_NE_NUPD_TRH_INIT 0x14 - -#define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 -#define B_CE_REG_PE_NEXP_OFFS__W 8 -#define B_CE_REG_PE_NEXP_OFFS__M 0xFF -#define B_CE_REG_PE_NEXP_OFFS_INIT 0x0 - -#define B_CE_REG_PE_TIMESHIFT__A 0x1810051 -#define B_CE_REG_PE_TIMESHIFT__W 14 -#define B_CE_REG_PE_TIMESHIFT__M 0x3FFF -#define B_CE_REG_PE_TIMESHIFT_INIT 0x0 - -#define B_CE_REG_PE_DIF_REAL_L__A 0x1810052 -#define B_CE_REG_PE_DIF_REAL_L__W 16 -#define B_CE_REG_PE_DIF_REAL_L__M 0xFFFF -#define B_CE_REG_PE_DIF_REAL_L_INIT 0x0 - -#define B_CE_REG_PE_DIF_IMAG_L__A 0x1810053 -#define B_CE_REG_PE_DIF_IMAG_L__W 16 -#define B_CE_REG_PE_DIF_IMAG_L__M 0xFFFF -#define B_CE_REG_PE_DIF_IMAG_L_INIT 0x0 - -#define B_CE_REG_PE_DIF_REAL_R__A 0x1810054 -#define B_CE_REG_PE_DIF_REAL_R__W 16 -#define B_CE_REG_PE_DIF_REAL_R__M 0xFFFF -#define B_CE_REG_PE_DIF_REAL_R_INIT 0x0 - -#define B_CE_REG_PE_DIF_IMAG_R__A 0x1810055 -#define B_CE_REG_PE_DIF_IMAG_R__W 16 -#define B_CE_REG_PE_DIF_IMAG_R__M 0xFFFF -#define B_CE_REG_PE_DIF_IMAG_R_INIT 0x0 - -#define B_CE_REG_PE_ABS_REAL_L__A 0x1810056 -#define B_CE_REG_PE_ABS_REAL_L__W 16 -#define B_CE_REG_PE_ABS_REAL_L__M 0xFFFF -#define B_CE_REG_PE_ABS_REAL_L_INIT 0x0 - -#define B_CE_REG_PE_ABS_IMAG_L__A 0x1810057 -#define B_CE_REG_PE_ABS_IMAG_L__W 16 -#define B_CE_REG_PE_ABS_IMAG_L__M 0xFFFF -#define B_CE_REG_PE_ABS_IMAG_L_INIT 0x0 - -#define B_CE_REG_PE_ABS_REAL_R__A 0x1810058 -#define B_CE_REG_PE_ABS_REAL_R__W 16 -#define B_CE_REG_PE_ABS_REAL_R__M 0xFFFF -#define B_CE_REG_PE_ABS_REAL_R_INIT 0x0 - -#define B_CE_REG_PE_ABS_IMAG_R__A 0x1810059 -#define B_CE_REG_PE_ABS_IMAG_R__W 16 -#define B_CE_REG_PE_ABS_IMAG_R__M 0xFFFF -#define B_CE_REG_PE_ABS_IMAG_R_INIT 0x0 - -#define B_CE_REG_PE_ABS_EXP_L__A 0x181005A -#define B_CE_REG_PE_ABS_EXP_L__W 5 -#define B_CE_REG_PE_ABS_EXP_L__M 0x1F -#define B_CE_REG_PE_ABS_EXP_L_INIT 0x0 - -#define B_CE_REG_PE_ABS_EXP_R__A 0x181005B -#define B_CE_REG_PE_ABS_EXP_R__W 5 -#define B_CE_REG_PE_ABS_EXP_R__M 0x1F -#define B_CE_REG_PE_ABS_EXP_R_INIT 0x0 - -#define B_CE_REG_TP_UPDATE_MODE__A 0x1810060 -#define B_CE_REG_TP_UPDATE_MODE__W 1 -#define B_CE_REG_TP_UPDATE_MODE__M 0x1 -#define B_CE_REG_TP_UPDATE_MODE_INIT 0x0 - -#define B_CE_REG_TP_LMS_TAP_ON__A 0x1810061 -#define B_CE_REG_TP_LMS_TAP_ON__W 1 -#define B_CE_REG_TP_LMS_TAP_ON__M 0x1 - -#define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064 -#define B_CE_REG_TP_A0_TAP_NEW__W 10 -#define B_CE_REG_TP_A0_TAP_NEW__M 0x3FF - -#define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 -#define B_CE_REG_TP_A0_TAP_NEW_VALID__W 1 -#define B_CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 - -#define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 -#define B_CE_REG_TP_A0_MU_LMS_STEP__W 5 -#define B_CE_REG_TP_A0_MU_LMS_STEP__M 0x1F - -#define B_CE_REG_TP_A0_TAP_CURR__A 0x1810067 -#define B_CE_REG_TP_A0_TAP_CURR__W 10 -#define B_CE_REG_TP_A0_TAP_CURR__M 0x3FF - -#define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068 -#define B_CE_REG_TP_A1_TAP_NEW__W 10 -#define B_CE_REG_TP_A1_TAP_NEW__M 0x3FF - -#define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 -#define B_CE_REG_TP_A1_TAP_NEW_VALID__W 1 -#define B_CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 - -#define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A -#define B_CE_REG_TP_A1_MU_LMS_STEP__W 5 -#define B_CE_REG_TP_A1_MU_LMS_STEP__M 0x1F - -#define B_CE_REG_TP_A1_TAP_CURR__A 0x181006B -#define B_CE_REG_TP_A1_TAP_CURR__W 10 -#define B_CE_REG_TP_A1_TAP_CURR__M 0x3FF - -#define B_CE_REG_TP_DOPP_ENERGY__A 0x181006C -#define B_CE_REG_TP_DOPP_ENERGY__W 15 -#define B_CE_REG_TP_DOPP_ENERGY__M 0x7FFF -#define B_CE_REG_TP_DOPP_ENERGY_INIT 0x0 - -#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 -#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 -#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 - -#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 -#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 -#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF - -#define B_CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D -#define B_CE_REG_TP_DOPP_DIFF_ENERGY__W 15 -#define B_CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 - -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 - -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF - -#define B_CE_REG_TP_A0_TAP_ENERGY__A 0x181006E -#define B_CE_REG_TP_A0_TAP_ENERGY__W 15 -#define B_CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF -#define B_CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 - -#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 -#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 -#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 - -#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 -#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 -#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF - -#define B_CE_REG_TP_A1_TAP_ENERGY__A 0x181006F -#define B_CE_REG_TP_A1_TAP_ENERGY__W 15 -#define B_CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF -#define B_CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 - -#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 -#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 -#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 - -#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 -#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 -#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF - -#define B_CE_REG_TI_SYM_CNT__A 0x1810072 -#define B_CE_REG_TI_SYM_CNT__W 6 -#define B_CE_REG_TI_SYM_CNT__M 0x3F -#define B_CE_REG_TI_SYM_CNT_INIT 0x0 - -#define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 -#define B_CE_REG_TI_PHN_ENABLE__W 1 -#define B_CE_REG_TI_PHN_ENABLE__M 0x1 -#define B_CE_REG_TI_PHN_ENABLE_INIT 0x0 - -#define B_CE_REG_TI_SHIFT__A 0x1810074 -#define B_CE_REG_TI_SHIFT__W 2 -#define B_CE_REG_TI_SHIFT__M 0x3 -#define B_CE_REG_TI_SHIFT_INIT 0x0 - -#define B_CE_REG_TI_SLOW__A 0x1810075 -#define B_CE_REG_TI_SLOW__W 1 -#define B_CE_REG_TI_SLOW__M 0x1 -#define B_CE_REG_TI_SLOW_INIT 0x0 - -#define B_CE_REG_TI_MGAIN__A 0x1810076 -#define B_CE_REG_TI_MGAIN__W 8 -#define B_CE_REG_TI_MGAIN__M 0xFF -#define B_CE_REG_TI_MGAIN_INIT 0x0 - -#define B_CE_REG_TI_ACCU1__A 0x1810077 -#define B_CE_REG_TI_ACCU1__W 8 -#define B_CE_REG_TI_ACCU1__M 0xFF -#define B_CE_REG_TI_ACCU1_INIT 0x0 - -#define B_CE_REG_NI_PER_LEFT__A 0x18100B0 -#define B_CE_REG_NI_PER_LEFT__W 5 -#define B_CE_REG_NI_PER_LEFT__M 0x1F -#define B_CE_REG_NI_PER_LEFT_INIT 0xE - -#define B_CE_REG_NI_PER_RIGHT__A 0x18100B1 -#define B_CE_REG_NI_PER_RIGHT__W 5 -#define B_CE_REG_NI_PER_RIGHT__M 0x1F -#define B_CE_REG_NI_PER_RIGHT_INIT 0x7 - -#define B_CE_REG_NI_POS_LR__A 0x18100B2 -#define B_CE_REG_NI_POS_LR__W 9 -#define B_CE_REG_NI_POS_LR__M 0x1FF -#define B_CE_REG_NI_POS_LR_INIT 0xA0 - -#define B_CE_REG_FI_SHT_INCR__A 0x1810090 -#define B_CE_REG_FI_SHT_INCR__W 7 -#define B_CE_REG_FI_SHT_INCR__M 0x7F -#define B_CE_REG_FI_SHT_INCR_INIT 0x9 - -#define B_CE_REG_FI_EXP_NORM__A 0x1810091 -#define B_CE_REG_FI_EXP_NORM__W 4 -#define B_CE_REG_FI_EXP_NORM__M 0xF -#define B_CE_REG_FI_EXP_NORM_INIT 0x4 - -#define B_CE_REG_FI_SUPR_VAL__A 0x1810092 -#define B_CE_REG_FI_SUPR_VAL__W 1 -#define B_CE_REG_FI_SUPR_VAL__M 0x1 -#define B_CE_REG_FI_SUPR_VAL_INIT 0x1 - -#define B_CE_REG_IR_INPUTSEL__A 0x18100A0 -#define B_CE_REG_IR_INPUTSEL__W 1 -#define B_CE_REG_IR_INPUTSEL__M 0x1 -#define B_CE_REG_IR_INPUTSEL_INIT 0x0 - -#define B_CE_REG_IR_STARTPOS__A 0x18100A1 -#define B_CE_REG_IR_STARTPOS__W 8 -#define B_CE_REG_IR_STARTPOS__M 0xFF -#define B_CE_REG_IR_STARTPOS_INIT 0x0 - -#define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 -#define B_CE_REG_IR_NEXP_THRES__W 8 -#define B_CE_REG_IR_NEXP_THRES__M 0xFF -#define B_CE_REG_IR_NEXP_THRES_INIT 0x0 - -#define B_CE_REG_IR_LENGTH__A 0x18100A3 -#define B_CE_REG_IR_LENGTH__W 4 -#define B_CE_REG_IR_LENGTH__M 0xF -#define B_CE_REG_IR_LENGTH_INIT 0x0 - -#define B_CE_REG_IR_FREQ__A 0x18100A4 -#define B_CE_REG_IR_FREQ__W 11 -#define B_CE_REG_IR_FREQ__M 0x7FF -#define B_CE_REG_IR_FREQ_INIT 0x0 - -#define B_CE_REG_IR_FREQINC__A 0x18100A5 -#define B_CE_REG_IR_FREQINC__W 11 -#define B_CE_REG_IR_FREQINC__M 0x7FF -#define B_CE_REG_IR_FREQINC_INIT 0x0 - -#define B_CE_REG_IR_KAISINC__A 0x18100A6 -#define B_CE_REG_IR_KAISINC__W 15 -#define B_CE_REG_IR_KAISINC__M 0x7FFF -#define B_CE_REG_IR_KAISINC_INIT 0x0 - -#define B_CE_REG_IR_CTL__A 0x18100A7 -#define B_CE_REG_IR_CTL__W 3 -#define B_CE_REG_IR_CTL__M 0x7 -#define B_CE_REG_IR_CTL_INIT 0x0 - -#define B_CE_REG_IR_REAL__A 0x18100A8 -#define B_CE_REG_IR_REAL__W 16 -#define B_CE_REG_IR_REAL__M 0xFFFF -#define B_CE_REG_IR_REAL_INIT 0x0 - -#define B_CE_REG_IR_IMAG__A 0x18100A9 -#define B_CE_REG_IR_IMAG__W 16 -#define B_CE_REG_IR_IMAG__M 0xFFFF -#define B_CE_REG_IR_IMAG_INIT 0x0 - -#define B_CE_REG_IR_INDEX__A 0x18100AA -#define B_CE_REG_IR_INDEX__W 12 -#define B_CE_REG_IR_INDEX__M 0xFFF -#define B_CE_REG_IR_INDEX_INIT 0x0 - -#define B_CE_REG_FR_COMM_EXEC__A 0x1820000 -#define B_CE_REG_FR_COMM_EXEC__W 1 -#define B_CE_REG_FR_COMM_EXEC__M 0x1 - -#define B_CE_REG_FR_TREAL00__A 0x1820010 -#define B_CE_REG_FR_TREAL00__W 11 -#define B_CE_REG_FR_TREAL00__M 0x7FF -#define B_CE_REG_FR_TREAL00_INIT 0x52 - -#define B_CE_REG_FR_TIMAG00__A 0x1820011 -#define B_CE_REG_FR_TIMAG00__W 11 -#define B_CE_REG_FR_TIMAG00__M 0x7FF -#define B_CE_REG_FR_TIMAG00_INIT 0x0 - -#define B_CE_REG_FR_TREAL01__A 0x1820012 -#define B_CE_REG_FR_TREAL01__W 11 -#define B_CE_REG_FR_TREAL01__M 0x7FF -#define B_CE_REG_FR_TREAL01_INIT 0x52 - -#define B_CE_REG_FR_TIMAG01__A 0x1820013 -#define B_CE_REG_FR_TIMAG01__W 11 -#define B_CE_REG_FR_TIMAG01__M 0x7FF -#define B_CE_REG_FR_TIMAG01_INIT 0x0 - -#define B_CE_REG_FR_TREAL02__A 0x1820014 -#define B_CE_REG_FR_TREAL02__W 11 -#define B_CE_REG_FR_TREAL02__M 0x7FF -#define B_CE_REG_FR_TREAL02_INIT 0x52 - -#define B_CE_REG_FR_TIMAG02__A 0x1820015 -#define B_CE_REG_FR_TIMAG02__W 11 -#define B_CE_REG_FR_TIMAG02__M 0x7FF -#define B_CE_REG_FR_TIMAG02_INIT 0x0 - -#define B_CE_REG_FR_TREAL03__A 0x1820016 -#define B_CE_REG_FR_TREAL03__W 11 -#define B_CE_REG_FR_TREAL03__M 0x7FF -#define B_CE_REG_FR_TREAL03_INIT 0x52 - -#define B_CE_REG_FR_TIMAG03__A 0x1820017 -#define B_CE_REG_FR_TIMAG03__W 11 -#define B_CE_REG_FR_TIMAG03__M 0x7FF -#define B_CE_REG_FR_TIMAG03_INIT 0x0 - -#define B_CE_REG_FR_TREAL04__A 0x1820018 -#define B_CE_REG_FR_TREAL04__W 11 -#define B_CE_REG_FR_TREAL04__M 0x7FF -#define B_CE_REG_FR_TREAL04_INIT 0x52 - -#define B_CE_REG_FR_TIMAG04__A 0x1820019 -#define B_CE_REG_FR_TIMAG04__W 11 -#define B_CE_REG_FR_TIMAG04__M 0x7FF -#define B_CE_REG_FR_TIMAG04_INIT 0x0 - -#define B_CE_REG_FR_TREAL05__A 0x182001A -#define B_CE_REG_FR_TREAL05__W 11 -#define B_CE_REG_FR_TREAL05__M 0x7FF -#define B_CE_REG_FR_TREAL05_INIT 0x52 - -#define B_CE_REG_FR_TIMAG05__A 0x182001B -#define B_CE_REG_FR_TIMAG05__W 11 -#define B_CE_REG_FR_TIMAG05__M 0x7FF -#define B_CE_REG_FR_TIMAG05_INIT 0x0 - -#define B_CE_REG_FR_TREAL06__A 0x182001C -#define B_CE_REG_FR_TREAL06__W 11 -#define B_CE_REG_FR_TREAL06__M 0x7FF -#define B_CE_REG_FR_TREAL06_INIT 0x52 - -#define B_CE_REG_FR_TIMAG06__A 0x182001D -#define B_CE_REG_FR_TIMAG06__W 11 -#define B_CE_REG_FR_TIMAG06__M 0x7FF -#define B_CE_REG_FR_TIMAG06_INIT 0x0 - -#define B_CE_REG_FR_TREAL07__A 0x182001E -#define B_CE_REG_FR_TREAL07__W 11 -#define B_CE_REG_FR_TREAL07__M 0x7FF -#define B_CE_REG_FR_TREAL07_INIT 0x52 - -#define B_CE_REG_FR_TIMAG07__A 0x182001F -#define B_CE_REG_FR_TIMAG07__W 11 -#define B_CE_REG_FR_TIMAG07__M 0x7FF -#define B_CE_REG_FR_TIMAG07_INIT 0x0 - -#define B_CE_REG_FR_TREAL08__A 0x1820020 -#define B_CE_REG_FR_TREAL08__W 11 -#define B_CE_REG_FR_TREAL08__M 0x7FF -#define B_CE_REG_FR_TREAL08_INIT 0x52 - -#define B_CE_REG_FR_TIMAG08__A 0x1820021 -#define B_CE_REG_FR_TIMAG08__W 11 -#define B_CE_REG_FR_TIMAG08__M 0x7FF -#define B_CE_REG_FR_TIMAG08_INIT 0x0 - -#define B_CE_REG_FR_TREAL09__A 0x1820022 -#define B_CE_REG_FR_TREAL09__W 11 -#define B_CE_REG_FR_TREAL09__M 0x7FF -#define B_CE_REG_FR_TREAL09_INIT 0x52 - -#define B_CE_REG_FR_TIMAG09__A 0x1820023 -#define B_CE_REG_FR_TIMAG09__W 11 -#define B_CE_REG_FR_TIMAG09__M 0x7FF -#define B_CE_REG_FR_TIMAG09_INIT 0x0 - -#define B_CE_REG_FR_TREAL10__A 0x1820024 -#define B_CE_REG_FR_TREAL10__W 11 -#define B_CE_REG_FR_TREAL10__M 0x7FF -#define B_CE_REG_FR_TREAL10_INIT 0x52 - -#define B_CE_REG_FR_TIMAG10__A 0x1820025 -#define B_CE_REG_FR_TIMAG10__W 11 -#define B_CE_REG_FR_TIMAG10__M 0x7FF -#define B_CE_REG_FR_TIMAG10_INIT 0x0 - -#define B_CE_REG_FR_TREAL11__A 0x1820026 -#define B_CE_REG_FR_TREAL11__W 11 -#define B_CE_REG_FR_TREAL11__M 0x7FF -#define B_CE_REG_FR_TREAL11_INIT 0x52 - -#define B_CE_REG_FR_TIMAG11__A 0x1820027 -#define B_CE_REG_FR_TIMAG11__W 11 -#define B_CE_REG_FR_TIMAG11__M 0x7FF -#define B_CE_REG_FR_TIMAG11_INIT 0x0 - -#define B_CE_REG_FR_MID_TAP__A 0x1820028 -#define B_CE_REG_FR_MID_TAP__W 11 -#define B_CE_REG_FR_MID_TAP__M 0x7FF -#define B_CE_REG_FR_MID_TAP_INIT 0x51 - -#define B_CE_REG_FR_SQS_G00__A 0x1820029 -#define B_CE_REG_FR_SQS_G00__W 8 -#define B_CE_REG_FR_SQS_G00__M 0xFF -#define B_CE_REG_FR_SQS_G00_INIT 0xB - -#define B_CE_REG_FR_SQS_G01__A 0x182002A -#define B_CE_REG_FR_SQS_G01__W 8 -#define B_CE_REG_FR_SQS_G01__M 0xFF -#define B_CE_REG_FR_SQS_G01_INIT 0xB - -#define B_CE_REG_FR_SQS_G02__A 0x182002B -#define B_CE_REG_FR_SQS_G02__W 8 -#define B_CE_REG_FR_SQS_G02__M 0xFF -#define B_CE_REG_FR_SQS_G02_INIT 0xB - -#define B_CE_REG_FR_SQS_G03__A 0x182002C -#define B_CE_REG_FR_SQS_G03__W 8 -#define B_CE_REG_FR_SQS_G03__M 0xFF -#define B_CE_REG_FR_SQS_G03_INIT 0xB - -#define B_CE_REG_FR_SQS_G04__A 0x182002D -#define B_CE_REG_FR_SQS_G04__W 8 -#define B_CE_REG_FR_SQS_G04__M 0xFF -#define B_CE_REG_FR_SQS_G04_INIT 0xB - -#define B_CE_REG_FR_SQS_G05__A 0x182002E -#define B_CE_REG_FR_SQS_G05__W 8 -#define B_CE_REG_FR_SQS_G05__M 0xFF -#define B_CE_REG_FR_SQS_G05_INIT 0xB - -#define B_CE_REG_FR_SQS_G06__A 0x182002F -#define B_CE_REG_FR_SQS_G06__W 8 -#define B_CE_REG_FR_SQS_G06__M 0xFF -#define B_CE_REG_FR_SQS_G06_INIT 0xB - -#define B_CE_REG_FR_SQS_G07__A 0x1820030 -#define B_CE_REG_FR_SQS_G07__W 8 -#define B_CE_REG_FR_SQS_G07__M 0xFF -#define B_CE_REG_FR_SQS_G07_INIT 0xB - -#define B_CE_REG_FR_SQS_G08__A 0x1820031 -#define B_CE_REG_FR_SQS_G08__W 8 -#define B_CE_REG_FR_SQS_G08__M 0xFF -#define B_CE_REG_FR_SQS_G08_INIT 0xB - -#define B_CE_REG_FR_SQS_G09__A 0x1820032 -#define B_CE_REG_FR_SQS_G09__W 8 -#define B_CE_REG_FR_SQS_G09__M 0xFF -#define B_CE_REG_FR_SQS_G09_INIT 0xB - -#define B_CE_REG_FR_SQS_G10__A 0x1820033 -#define B_CE_REG_FR_SQS_G10__W 8 -#define B_CE_REG_FR_SQS_G10__M 0xFF -#define B_CE_REG_FR_SQS_G10_INIT 0xB - -#define B_CE_REG_FR_SQS_G11__A 0x1820034 -#define B_CE_REG_FR_SQS_G11__W 8 -#define B_CE_REG_FR_SQS_G11__M 0xFF -#define B_CE_REG_FR_SQS_G11_INIT 0xB - -#define B_CE_REG_FR_SQS_G12__A 0x1820035 -#define B_CE_REG_FR_SQS_G12__W 8 -#define B_CE_REG_FR_SQS_G12__M 0xFF -#define B_CE_REG_FR_SQS_G12_INIT 0x5 - -#define B_CE_REG_FR_RIO_G00__A 0x1820036 -#define B_CE_REG_FR_RIO_G00__W 9 -#define B_CE_REG_FR_RIO_G00__M 0x1FF -#define B_CE_REG_FR_RIO_G00_INIT 0x1FF - -#define B_CE_REG_FR_RIO_G01__A 0x1820037 -#define B_CE_REG_FR_RIO_G01__W 9 -#define B_CE_REG_FR_RIO_G01__M 0x1FF -#define B_CE_REG_FR_RIO_G01_INIT 0x190 - -#define B_CE_REG_FR_RIO_G02__A 0x1820038 -#define B_CE_REG_FR_RIO_G02__W 9 -#define B_CE_REG_FR_RIO_G02__M 0x1FF -#define B_CE_REG_FR_RIO_G02_INIT 0x10B - -#define B_CE_REG_FR_RIO_G03__A 0x1820039 -#define B_CE_REG_FR_RIO_G03__W 9 -#define B_CE_REG_FR_RIO_G03__M 0x1FF -#define B_CE_REG_FR_RIO_G03_INIT 0xC8 - -#define B_CE_REG_FR_RIO_G04__A 0x182003A -#define B_CE_REG_FR_RIO_G04__W 9 -#define B_CE_REG_FR_RIO_G04__M 0x1FF -#define B_CE_REG_FR_RIO_G04_INIT 0xA0 - -#define B_CE_REG_FR_RIO_G05__A 0x182003B -#define B_CE_REG_FR_RIO_G05__W 9 -#define B_CE_REG_FR_RIO_G05__M 0x1FF -#define B_CE_REG_FR_RIO_G05_INIT 0x85 - -#define B_CE_REG_FR_RIO_G06__A 0x182003C -#define B_CE_REG_FR_RIO_G06__W 9 -#define B_CE_REG_FR_RIO_G06__M 0x1FF -#define B_CE_REG_FR_RIO_G06_INIT 0x72 - -#define B_CE_REG_FR_RIO_G07__A 0x182003D -#define B_CE_REG_FR_RIO_G07__W 9 -#define B_CE_REG_FR_RIO_G07__M 0x1FF -#define B_CE_REG_FR_RIO_G07_INIT 0x64 - -#define B_CE_REG_FR_RIO_G08__A 0x182003E -#define B_CE_REG_FR_RIO_G08__W 9 -#define B_CE_REG_FR_RIO_G08__M 0x1FF -#define B_CE_REG_FR_RIO_G08_INIT 0x59 - -#define B_CE_REG_FR_RIO_G09__A 0x182003F -#define B_CE_REG_FR_RIO_G09__W 9 -#define B_CE_REG_FR_RIO_G09__M 0x1FF -#define B_CE_REG_FR_RIO_G09_INIT 0x50 - -#define B_CE_REG_FR_RIO_G10__A 0x1820040 -#define B_CE_REG_FR_RIO_G10__W 9 -#define B_CE_REG_FR_RIO_G10__M 0x1FF -#define B_CE_REG_FR_RIO_G10_INIT 0x49 - -#define B_CE_REG_FR_MODE__A 0x1820041 -#define B_CE_REG_FR_MODE__W 9 -#define B_CE_REG_FR_MODE__M 0x1FF - -#define B_CE_REG_FR_MODE_UPDATE_ENABLE__B 0 -#define B_CE_REG_FR_MODE_UPDATE_ENABLE__W 1 -#define B_CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 - -#define B_CE_REG_FR_MODE_ERROR_SHIFT__B 1 -#define B_CE_REG_FR_MODE_ERROR_SHIFT__W 1 -#define B_CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 - -#define B_CE_REG_FR_MODE_NEXP_UPDATE__B 2 -#define B_CE_REG_FR_MODE_NEXP_UPDATE__W 1 -#define B_CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 - -#define B_CE_REG_FR_MODE_MANUAL_SHIFT__B 3 -#define B_CE_REG_FR_MODE_MANUAL_SHIFT__W 1 -#define B_CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 - -#define B_CE_REG_FR_MODE_SQUASH_MODE__B 4 -#define B_CE_REG_FR_MODE_SQUASH_MODE__W 1 -#define B_CE_REG_FR_MODE_SQUASH_MODE__M 0x10 - -#define B_CE_REG_FR_MODE_UPDATE_MODE__B 5 -#define B_CE_REG_FR_MODE_UPDATE_MODE__W 1 -#define B_CE_REG_FR_MODE_UPDATE_MODE__M 0x20 - -#define B_CE_REG_FR_MODE_MID_MODE__B 6 -#define B_CE_REG_FR_MODE_MID_MODE__W 1 -#define B_CE_REG_FR_MODE_MID_MODE__M 0x40 - -#define B_CE_REG_FR_MODE_NOISE_MODE__B 7 -#define B_CE_REG_FR_MODE_NOISE_MODE__W 1 -#define B_CE_REG_FR_MODE_NOISE_MODE__M 0x80 - -#define B_CE_REG_FR_MODE_NOTCH_MODE__B 8 -#define B_CE_REG_FR_MODE_NOTCH_MODE__W 1 -#define B_CE_REG_FR_MODE_NOTCH_MODE__M 0x100 -#define B_CE_REG_FR_MODE_INIT 0xDE - -#define B_CE_REG_FR_SQS_TRH__A 0x1820042 -#define B_CE_REG_FR_SQS_TRH__W 8 -#define B_CE_REG_FR_SQS_TRH__M 0xFF -#define B_CE_REG_FR_SQS_TRH_INIT 0x80 - -#define B_CE_REG_FR_RIO_GAIN__A 0x1820043 -#define B_CE_REG_FR_RIO_GAIN__W 3 -#define B_CE_REG_FR_RIO_GAIN__M 0x7 -#define B_CE_REG_FR_RIO_GAIN_INIT 0x2 - -#define B_CE_REG_FR_BYPASS__A 0x1820044 -#define B_CE_REG_FR_BYPASS__W 10 -#define B_CE_REG_FR_BYPASS__M 0x3FF - -#define B_CE_REG_FR_BYPASS_RUN_IN__B 0 -#define B_CE_REG_FR_BYPASS_RUN_IN__W 4 -#define B_CE_REG_FR_BYPASS_RUN_IN__M 0xF - -#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 -#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 -#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 - -#define B_CE_REG_FR_BYPASS_TOTAL__B 9 -#define B_CE_REG_FR_BYPASS_TOTAL__W 1 -#define B_CE_REG_FR_BYPASS_TOTAL__M 0x200 -#define B_CE_REG_FR_BYPASS_INIT 0x13B - -#define B_CE_REG_FR_PM_SET__A 0x1820045 -#define B_CE_REG_FR_PM_SET__W 4 -#define B_CE_REG_FR_PM_SET__M 0xF -#define B_CE_REG_FR_PM_SET_INIT 0x4 - -#define B_CE_REG_FR_ERR_SH__A 0x1820046 -#define B_CE_REG_FR_ERR_SH__W 4 -#define B_CE_REG_FR_ERR_SH__M 0xF -#define B_CE_REG_FR_ERR_SH_INIT 0x4 - -#define B_CE_REG_FR_MAN_SH__A 0x1820047 -#define B_CE_REG_FR_MAN_SH__W 4 -#define B_CE_REG_FR_MAN_SH__M 0xF -#define B_CE_REG_FR_MAN_SH_INIT 0x7 - -#define B_CE_REG_FR_TAP_SH__A 0x1820048 -#define B_CE_REG_FR_TAP_SH__W 3 -#define B_CE_REG_FR_TAP_SH__M 0x7 -#define B_CE_REG_FR_TAP_SH_INIT 0x3 - -#define B_CE_REG_FR_CLIP__A 0x1820049 -#define B_CE_REG_FR_CLIP__W 9 -#define B_CE_REG_FR_CLIP__M 0x1FF -#define B_CE_REG_FR_CLIP_INIT 0x49 - -#define B_CE_REG_FR_LEAK_UPD__A 0x182004A -#define B_CE_REG_FR_LEAK_UPD__W 3 -#define B_CE_REG_FR_LEAK_UPD__M 0x7 -#define B_CE_REG_FR_LEAK_UPD_INIT 0x1 - -#define B_CE_REG_FR_LEAK_SH__A 0x182004B -#define B_CE_REG_FR_LEAK_SH__W 3 -#define B_CE_REG_FR_LEAK_SH__M 0x7 -#define B_CE_REG_FR_LEAK_SH_INIT 0x1 - -#define B_CE_PB_RAM__A 0x1830000 - -#define B_CE_NE_RAM__A 0x1840000 - -#define B_EQ_SID 0xE - -#define B_EQ_COMM_EXEC__A 0x1C00000 -#define B_EQ_COMM_EXEC__W 3 -#define B_EQ_COMM_EXEC__M 0x7 -#define B_EQ_COMM_EXEC_CTL__B 0 -#define B_EQ_COMM_EXEC_CTL__W 3 -#define B_EQ_COMM_EXEC_CTL__M 0x7 -#define B_EQ_COMM_EXEC_CTL_STOP 0x0 -#define B_EQ_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EQ_COMM_EXEC_CTL_HOLD 0x2 -#define B_EQ_COMM_EXEC_CTL_STEP 0x3 -#define B_EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_EQ_COMM_STATE__A 0x1C00001 -#define B_EQ_COMM_STATE__W 16 -#define B_EQ_COMM_STATE__M 0xFFFF -#define B_EQ_COMM_MB__A 0x1C00002 -#define B_EQ_COMM_MB__W 16 -#define B_EQ_COMM_MB__M 0xFFFF -#define B_EQ_COMM_SERVICE0__A 0x1C00003 -#define B_EQ_COMM_SERVICE0__W 16 -#define B_EQ_COMM_SERVICE0__M 0xFFFF -#define B_EQ_COMM_SERVICE1__A 0x1C00004 -#define B_EQ_COMM_SERVICE1__W 16 -#define B_EQ_COMM_SERVICE1__M 0xFFFF -#define B_EQ_COMM_INT_STA__A 0x1C00007 -#define B_EQ_COMM_INT_STA__W 16 -#define B_EQ_COMM_INT_STA__M 0xFFFF -#define B_EQ_COMM_INT_MSK__A 0x1C00008 -#define B_EQ_COMM_INT_MSK__W 16 -#define B_EQ_COMM_INT_MSK__M 0xFFFF - -#define B_EQ_REG_COMM_EXEC__A 0x1C10000 -#define B_EQ_REG_COMM_EXEC__W 3 -#define B_EQ_REG_COMM_EXEC__M 0x7 -#define B_EQ_REG_COMM_EXEC_CTL__B 0 -#define B_EQ_REG_COMM_EXEC_CTL__W 3 -#define B_EQ_REG_COMM_EXEC_CTL__M 0x7 -#define B_EQ_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EQ_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_EQ_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_EQ_REG_COMM_STATE__A 0x1C10001 -#define B_EQ_REG_COMM_STATE__W 4 -#define B_EQ_REG_COMM_STATE__M 0xF - -#define B_EQ_REG_COMM_MB__A 0x1C10002 -#define B_EQ_REG_COMM_MB__W 6 -#define B_EQ_REG_COMM_MB__M 0x3F -#define B_EQ_REG_COMM_MB_CTR__B 0 -#define B_EQ_REG_COMM_MB_CTR__W 1 -#define B_EQ_REG_COMM_MB_CTR__M 0x1 -#define B_EQ_REG_COMM_MB_CTR_OFF 0x0 -#define B_EQ_REG_COMM_MB_CTR_ON 0x1 -#define B_EQ_REG_COMM_MB_OBS__B 1 -#define B_EQ_REG_COMM_MB_OBS__W 1 -#define B_EQ_REG_COMM_MB_OBS__M 0x2 -#define B_EQ_REG_COMM_MB_OBS_OFF 0x0 -#define B_EQ_REG_COMM_MB_OBS_ON 0x2 -#define B_EQ_REG_COMM_MB_CTR_MUX__B 2 -#define B_EQ_REG_COMM_MB_CTR_MUX__W 2 -#define B_EQ_REG_COMM_MB_CTR_MUX__M 0xC -#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 -#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 -#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 -#define B_EQ_REG_COMM_MB_OBS_MUX__B 4 -#define B_EQ_REG_COMM_MB_OBS_MUX__W 2 -#define B_EQ_REG_COMM_MB_OBS_MUX__M 0x30 -#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 -#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 -#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 -#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 - -#define B_EQ_REG_COMM_SERVICE0__A 0x1C10003 -#define B_EQ_REG_COMM_SERVICE0__W 10 -#define B_EQ_REG_COMM_SERVICE0__M 0x3FF - -#define B_EQ_REG_COMM_SERVICE1__A 0x1C10004 -#define B_EQ_REG_COMM_SERVICE1__W 11 -#define B_EQ_REG_COMM_SERVICE1__M 0x7FF - -#define B_EQ_REG_COMM_INT_STA__A 0x1C10007 -#define B_EQ_REG_COMM_INT_STA__W 2 -#define B_EQ_REG_COMM_INT_STA__M 0x3 -#define B_EQ_REG_COMM_INT_STA_TPS_RDY__B 0 -#define B_EQ_REG_COMM_INT_STA_TPS_RDY__W 1 -#define B_EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 -#define B_EQ_REG_COMM_INT_STA_ERR_RDY__B 1 -#define B_EQ_REG_COMM_INT_STA_ERR_RDY__W 1 -#define B_EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 - -#define B_EQ_REG_COMM_INT_MSK__A 0x1C10008 -#define B_EQ_REG_COMM_INT_MSK__W 2 -#define B_EQ_REG_COMM_INT_MSK__M 0x3 -#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 -#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 -#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 -#define B_EQ_REG_COMM_INT_MSK_MER_RDY__B 1 -#define B_EQ_REG_COMM_INT_MSK_MER_RDY__W 1 -#define B_EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 - -#define B_EQ_REG_IS_MODE__A 0x1C10014 -#define B_EQ_REG_IS_MODE__W 4 -#define B_EQ_REG_IS_MODE__M 0xF -#define B_EQ_REG_IS_MODE_INIT 0x0 - -#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 -#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 -#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 -#define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 -#define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 - -#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 -#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 -#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 -#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 -#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 - -#define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 -#define B_EQ_REG_IS_GAIN_MAN__W 10 -#define B_EQ_REG_IS_GAIN_MAN__M 0x3FF -#define B_EQ_REG_IS_GAIN_MAN_INIT 0x114 - -#define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 -#define B_EQ_REG_IS_GAIN_EXP__W 5 -#define B_EQ_REG_IS_GAIN_EXP__M 0x1F -#define B_EQ_REG_IS_GAIN_EXP_INIT 0x5 - -#define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 -#define B_EQ_REG_IS_CLIP_EXP__W 5 -#define B_EQ_REG_IS_CLIP_EXP__M 0x1F -#define B_EQ_REG_IS_CLIP_EXP_INIT 0x10 - -#define B_EQ_REG_DV_MODE__A 0x1C1001E -#define B_EQ_REG_DV_MODE__W 4 -#define B_EQ_REG_DV_MODE__M 0xF -#define B_EQ_REG_DV_MODE_INIT 0xF - -#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 - -#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 - -#define B_EQ_REG_DV_MODE_CLP_REA_ENA__B 2 -#define B_EQ_REG_DV_MODE_CLP_REA_ENA__W 1 -#define B_EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 -#define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 -#define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 - -#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 -#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 -#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 -#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 -#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 - -#define B_EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F -#define B_EQ_REG_DV_POS_CLIP_DAT__W 16 -#define B_EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF - -#define B_EQ_REG_SN_MODE__A 0x1C10028 -#define B_EQ_REG_SN_MODE__W 8 -#define B_EQ_REG_SN_MODE__M 0xFF -#define B_EQ_REG_SN_MODE_INIT 0x18 - -#define B_EQ_REG_SN_MODE_MODE_0__B 0 -#define B_EQ_REG_SN_MODE_MODE_0__W 1 -#define B_EQ_REG_SN_MODE_MODE_0__M 0x1 -#define B_EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 - -#define B_EQ_REG_SN_MODE_MODE_1__B 1 -#define B_EQ_REG_SN_MODE_MODE_1__W 1 -#define B_EQ_REG_SN_MODE_MODE_1__M 0x2 -#define B_EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 - -#define B_EQ_REG_SN_MODE_MODE_2__B 2 -#define B_EQ_REG_SN_MODE_MODE_2__W 1 -#define B_EQ_REG_SN_MODE_MODE_2__M 0x4 -#define B_EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 - -#define B_EQ_REG_SN_MODE_MODE_3__B 3 -#define B_EQ_REG_SN_MODE_MODE_3__W 1 -#define B_EQ_REG_SN_MODE_MODE_3__M 0x8 -#define B_EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 - -#define B_EQ_REG_SN_MODE_MODE_4__B 4 -#define B_EQ_REG_SN_MODE_MODE_4__W 1 -#define B_EQ_REG_SN_MODE_MODE_4__M 0x10 -#define B_EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 - -#define B_EQ_REG_SN_MODE_MODE_5__B 5 -#define B_EQ_REG_SN_MODE_MODE_5__W 1 -#define B_EQ_REG_SN_MODE_MODE_5__M 0x20 -#define B_EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 - -#define B_EQ_REG_SN_MODE_MODE_6__B 6 -#define B_EQ_REG_SN_MODE_MODE_6__W 1 -#define B_EQ_REG_SN_MODE_MODE_6__M 0x40 -#define B_EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 -#define B_EQ_REG_SN_MODE_MODE_6_STATIC 0x40 - -#define B_EQ_REG_SN_MODE_MODE_7__B 7 -#define B_EQ_REG_SN_MODE_MODE_7__W 1 -#define B_EQ_REG_SN_MODE_MODE_7__M 0x80 -#define B_EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 -#define B_EQ_REG_SN_MODE_MODE_7_STATIC 0x80 - -#define B_EQ_REG_SN_PFIX__A 0x1C10029 -#define B_EQ_REG_SN_PFIX__W 8 -#define B_EQ_REG_SN_PFIX__M 0xFF -#define B_EQ_REG_SN_PFIX_INIT 0x0 - -#define B_EQ_REG_SN_CEGAIN__A 0x1C1002A -#define B_EQ_REG_SN_CEGAIN__W 8 -#define B_EQ_REG_SN_CEGAIN__M 0xFF -#define B_EQ_REG_SN_CEGAIN_INIT 0x30 - -#define B_EQ_REG_SN_OFFSET__A 0x1C1002B -#define B_EQ_REG_SN_OFFSET__W 6 -#define B_EQ_REG_SN_OFFSET__M 0x3F -#define B_EQ_REG_SN_OFFSET_INIT 0x39 - -#define B_EQ_REG_SN_NULLIFY__A 0x1C1002C -#define B_EQ_REG_SN_NULLIFY__W 6 -#define B_EQ_REG_SN_NULLIFY__M 0x3F -#define B_EQ_REG_SN_NULLIFY_INIT 0x0 - -#define B_EQ_REG_SN_SQUASH__A 0x1C1002D -#define B_EQ_REG_SN_SQUASH__W 10 -#define B_EQ_REG_SN_SQUASH__M 0x3FF -#define B_EQ_REG_SN_SQUASH_INIT 0x7 - -#define B_EQ_REG_SN_SQUASH_MAN__B 0 -#define B_EQ_REG_SN_SQUASH_MAN__W 6 -#define B_EQ_REG_SN_SQUASH_MAN__M 0x3F - -#define B_EQ_REG_SN_SQUASH_EXP__B 6 -#define B_EQ_REG_SN_SQUASH_EXP__W 4 -#define B_EQ_REG_SN_SQUASH_EXP__M 0x3C0 - -#define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 -#define B_EQ_REG_RC_SEL_CAR__W 8 -#define B_EQ_REG_RC_SEL_CAR__M 0xFF -#define B_EQ_REG_RC_SEL_CAR_INIT 0x2 -#define B_EQ_REG_RC_SEL_CAR_DIV__B 0 -#define B_EQ_REG_RC_SEL_CAR_DIV__W 1 -#define B_EQ_REG_RC_SEL_CAR_DIV__M 0x1 -#define B_EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 -#define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1 - -#define B_EQ_REG_RC_SEL_CAR_PASS__B 1 -#define B_EQ_REG_RC_SEL_CAR_PASS__W 2 -#define B_EQ_REG_RC_SEL_CAR_PASS__M 0x6 -#define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 -#define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 -#define B_EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 -#define B_EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 - -#define B_EQ_REG_RC_SEL_CAR_LOCAL__B 3 -#define B_EQ_REG_RC_SEL_CAR_LOCAL__W 2 -#define B_EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 -#define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 -#define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 -#define B_EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 -#define B_EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 - -#define B_EQ_REG_RC_SEL_CAR_MEAS__B 5 -#define B_EQ_REG_RC_SEL_CAR_MEAS__W 2 -#define B_EQ_REG_RC_SEL_CAR_MEAS__M 0x60 -#define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 -#define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 -#define B_EQ_REG_RC_SEL_CAR_MEAS_C_DRI 0x40 -#define B_EQ_REG_RC_SEL_CAR_MEAS_D_CC 0x60 - -#define B_EQ_REG_RC_SEL_CAR_FFTMODE__B 7 -#define B_EQ_REG_RC_SEL_CAR_FFTMODE__W 1 -#define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80 -#define B_EQ_REG_RC_SEL_CAR_FFTMODE_2K 0x0 -#define B_EQ_REG_RC_SEL_CAR_FFTMODE_8K 0x80 - -#define B_EQ_REG_RC_STS__A 0x1C10033 -#define B_EQ_REG_RC_STS__W 14 -#define B_EQ_REG_RC_STS__M 0x3FFF - -#define B_EQ_REG_RC_STS_DIFF__B 0 -#define B_EQ_REG_RC_STS_DIFF__W 9 -#define B_EQ_REG_RC_STS_DIFF__M 0x1FF - -#define B_EQ_REG_RC_STS_FIRST__B 9 -#define B_EQ_REG_RC_STS_FIRST__W 1 -#define B_EQ_REG_RC_STS_FIRST__M 0x200 -#define B_EQ_REG_RC_STS_FIRST_A_CE 0x0 -#define B_EQ_REG_RC_STS_FIRST_B_DRI 0x200 - -#define B_EQ_REG_RC_STS_SELEC__B 10 -#define B_EQ_REG_RC_STS_SELEC__W 1 -#define B_EQ_REG_RC_STS_SELEC__M 0x400 -#define B_EQ_REG_RC_STS_SELEC_A_CE 0x0 -#define B_EQ_REG_RC_STS_SELEC_B_DRI 0x400 - -#define B_EQ_REG_RC_STS_OVERFLOW__B 11 -#define B_EQ_REG_RC_STS_OVERFLOW__W 1 -#define B_EQ_REG_RC_STS_OVERFLOW__M 0x800 -#define B_EQ_REG_RC_STS_OVERFLOW_NO 0x0 -#define B_EQ_REG_RC_STS_OVERFLOW_YES 0x800 - -#define B_EQ_REG_RC_STS_LOC_PRS__B 12 -#define B_EQ_REG_RC_STS_LOC_PRS__W 1 -#define B_EQ_REG_RC_STS_LOC_PRS__M 0x1000 -#define B_EQ_REG_RC_STS_LOC_PRS_NO 0x0 -#define B_EQ_REG_RC_STS_LOC_PRS_YES 0x1000 - -#define B_EQ_REG_RC_STS_DRI_PRS__B 13 -#define B_EQ_REG_RC_STS_DRI_PRS__W 1 -#define B_EQ_REG_RC_STS_DRI_PRS__M 0x2000 -#define B_EQ_REG_RC_STS_DRI_PRS_NO 0x0 -#define B_EQ_REG_RC_STS_DRI_PRS_YES 0x2000 - -#define B_EQ_REG_OT_CONST__A 0x1C10046 -#define B_EQ_REG_OT_CONST__W 2 -#define B_EQ_REG_OT_CONST__M 0x3 -#define B_EQ_REG_OT_CONST_INIT 0x2 - -#define B_EQ_REG_OT_ALPHA__A 0x1C10047 -#define B_EQ_REG_OT_ALPHA__W 2 -#define B_EQ_REG_OT_ALPHA__M 0x3 -#define B_EQ_REG_OT_ALPHA_INIT 0x0 - -#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 -#define B_EQ_REG_OT_QNT_THRES0__W 5 -#define B_EQ_REG_OT_QNT_THRES0__M 0x1F -#define B_EQ_REG_OT_QNT_THRES0_INIT 0x1E - -#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 -#define B_EQ_REG_OT_QNT_THRES1__W 5 -#define B_EQ_REG_OT_QNT_THRES1__M 0x1F -#define B_EQ_REG_OT_QNT_THRES1_INIT 0x1F - -#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A -#define B_EQ_REG_OT_CSI_STEP__W 4 -#define B_EQ_REG_OT_CSI_STEP__M 0xF -#define B_EQ_REG_OT_CSI_STEP_INIT 0x5 - -#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B -#define B_EQ_REG_OT_CSI_OFFSET__W 7 -#define B_EQ_REG_OT_CSI_OFFSET__M 0x7F -#define B_EQ_REG_OT_CSI_OFFSET_INIT 0x5 - -#define B_EQ_REG_OT_CSI_GAIN__A 0x1C1004C -#define B_EQ_REG_OT_CSI_GAIN__W 8 -#define B_EQ_REG_OT_CSI_GAIN__M 0xFF -#define B_EQ_REG_OT_CSI_GAIN_INIT 0x2B - -#define B_EQ_REG_OT_CSI_MEAN__A 0x1C1004D -#define B_EQ_REG_OT_CSI_MEAN__W 7 -#define B_EQ_REG_OT_CSI_MEAN__M 0x7F - -#define B_EQ_REG_OT_CSI_VARIANCE__A 0x1C1004E -#define B_EQ_REG_OT_CSI_VARIANCE__W 7 -#define B_EQ_REG_OT_CSI_VARIANCE__M 0x7F - -#define B_EQ_REG_TD_TPS_INIT__A 0x1C10050 -#define B_EQ_REG_TD_TPS_INIT__W 1 -#define B_EQ_REG_TD_TPS_INIT__M 0x1 -#define B_EQ_REG_TD_TPS_INIT_INIT 0x0 -#define B_EQ_REG_TD_TPS_INIT_POS 0x0 -#define B_EQ_REG_TD_TPS_INIT_NEG 0x1 - -#define B_EQ_REG_TD_TPS_SYNC__A 0x1C10051 -#define B_EQ_REG_TD_TPS_SYNC__W 16 -#define B_EQ_REG_TD_TPS_SYNC__M 0xFFFF -#define B_EQ_REG_TD_TPS_SYNC_INIT 0x0 -#define B_EQ_REG_TD_TPS_SYNC_ODD 0x35EE -#define B_EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 - -#define B_EQ_REG_TD_TPS_LEN__A 0x1C10052 -#define B_EQ_REG_TD_TPS_LEN__W 6 -#define B_EQ_REG_TD_TPS_LEN__M 0x3F -#define B_EQ_REG_TD_TPS_LEN_INIT 0x0 -#define B_EQ_REG_TD_TPS_LEN_DEF 0x17 -#define B_EQ_REG_TD_TPS_LEN_ID_SUP 0x1F - -#define B_EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 -#define B_EQ_REG_TD_TPS_FRM_NMB__W 2 -#define B_EQ_REG_TD_TPS_FRM_NMB__M 0x3 -#define B_EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 -#define B_EQ_REG_TD_TPS_FRM_NMB_1 0x0 -#define B_EQ_REG_TD_TPS_FRM_NMB_2 0x1 -#define B_EQ_REG_TD_TPS_FRM_NMB_3 0x2 -#define B_EQ_REG_TD_TPS_FRM_NMB_4 0x3 - -#define B_EQ_REG_TD_TPS_CONST__A 0x1C10054 -#define B_EQ_REG_TD_TPS_CONST__W 2 -#define B_EQ_REG_TD_TPS_CONST__M 0x3 -#define B_EQ_REG_TD_TPS_CONST_INIT 0x0 -#define B_EQ_REG_TD_TPS_CONST_QPSK 0x0 -#define B_EQ_REG_TD_TPS_CONST_16QAM 0x1 -#define B_EQ_REG_TD_TPS_CONST_64QAM 0x2 - -#define B_EQ_REG_TD_TPS_HINFO__A 0x1C10055 -#define B_EQ_REG_TD_TPS_HINFO__W 3 -#define B_EQ_REG_TD_TPS_HINFO__M 0x7 -#define B_EQ_REG_TD_TPS_HINFO_INIT 0x0 -#define B_EQ_REG_TD_TPS_HINFO_NH 0x0 -#define B_EQ_REG_TD_TPS_HINFO_H1 0x1 -#define B_EQ_REG_TD_TPS_HINFO_H2 0x2 -#define B_EQ_REG_TD_TPS_HINFO_H4 0x3 - -#define B_EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 -#define B_EQ_REG_TD_TPS_CODE_HP__W 3 -#define B_EQ_REG_TD_TPS_CODE_HP__M 0x7 -#define B_EQ_REG_TD_TPS_CODE_HP_INIT 0x0 -#define B_EQ_REG_TD_TPS_CODE_HP_1_2 0x0 -#define B_EQ_REG_TD_TPS_CODE_HP_2_3 0x1 -#define B_EQ_REG_TD_TPS_CODE_HP_3_4 0x2 -#define B_EQ_REG_TD_TPS_CODE_HP_5_6 0x3 -#define B_EQ_REG_TD_TPS_CODE_HP_7_8 0x4 - -#define B_EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 -#define B_EQ_REG_TD_TPS_CODE_LP__W 3 -#define B_EQ_REG_TD_TPS_CODE_LP__M 0x7 -#define B_EQ_REG_TD_TPS_CODE_LP_INIT 0x0 -#define B_EQ_REG_TD_TPS_CODE_LP_1_2 0x0 -#define B_EQ_REG_TD_TPS_CODE_LP_2_3 0x1 -#define B_EQ_REG_TD_TPS_CODE_LP_3_4 0x2 -#define B_EQ_REG_TD_TPS_CODE_LP_5_6 0x3 -#define B_EQ_REG_TD_TPS_CODE_LP_7_8 0x4 - -#define B_EQ_REG_TD_TPS_GUARD__A 0x1C10058 -#define B_EQ_REG_TD_TPS_GUARD__W 2 -#define B_EQ_REG_TD_TPS_GUARD__M 0x3 -#define B_EQ_REG_TD_TPS_GUARD_INIT 0x0 -#define B_EQ_REG_TD_TPS_GUARD_32 0x0 -#define B_EQ_REG_TD_TPS_GUARD_16 0x1 -#define B_EQ_REG_TD_TPS_GUARD_08 0x2 -#define B_EQ_REG_TD_TPS_GUARD_04 0x3 - -#define B_EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 -#define B_EQ_REG_TD_TPS_TR_MODE__W 2 -#define B_EQ_REG_TD_TPS_TR_MODE__M 0x3 -#define B_EQ_REG_TD_TPS_TR_MODE_INIT 0x0 -#define B_EQ_REG_TD_TPS_TR_MODE_2K 0x0 -#define B_EQ_REG_TD_TPS_TR_MODE_8K 0x1 - -#define B_EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A -#define B_EQ_REG_TD_TPS_CELL_ID_HI__W 8 -#define B_EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF -#define B_EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 - -#define B_EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B -#define B_EQ_REG_TD_TPS_CELL_ID_LO__W 8 -#define B_EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF -#define B_EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 - -#define B_EQ_REG_TD_TPS_RSV__A 0x1C1005C -#define B_EQ_REG_TD_TPS_RSV__W 6 -#define B_EQ_REG_TD_TPS_RSV__M 0x3F -#define B_EQ_REG_TD_TPS_RSV_INIT 0x0 - -#define B_EQ_REG_TD_TPS_BCH__A 0x1C1005D -#define B_EQ_REG_TD_TPS_BCH__W 14 -#define B_EQ_REG_TD_TPS_BCH__M 0x3FFF -#define B_EQ_REG_TD_TPS_BCH_INIT 0x0 - -#define B_EQ_REG_TD_SQR_ERR_I__A 0x1C1005E -#define B_EQ_REG_TD_SQR_ERR_I__W 16 -#define B_EQ_REG_TD_SQR_ERR_I__M 0xFFFF -#define B_EQ_REG_TD_SQR_ERR_I_INIT 0x0 - -#define B_EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F -#define B_EQ_REG_TD_SQR_ERR_Q__W 16 -#define B_EQ_REG_TD_SQR_ERR_Q__M 0xFFFF -#define B_EQ_REG_TD_SQR_ERR_Q_INIT 0x0 - -#define B_EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 -#define B_EQ_REG_TD_SQR_ERR_EXP__W 4 -#define B_EQ_REG_TD_SQR_ERR_EXP__M 0xF -#define B_EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 - -#define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 -#define B_EQ_REG_TD_REQ_SMB_CNT__W 16 -#define B_EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF -#define B_EQ_REG_TD_REQ_SMB_CNT_INIT 0x200 - -#define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 -#define B_EQ_REG_TD_TPS_PWR_OFS__W 16 -#define B_EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF -#define B_EQ_REG_TD_TPS_PWR_OFS_INIT 0x19F - -#define B_EC_COMM_EXEC__A 0x2000000 -#define B_EC_COMM_EXEC__W 3 -#define B_EC_COMM_EXEC__M 0x7 -#define B_EC_COMM_EXEC_CTL__B 0 -#define B_EC_COMM_EXEC_CTL__W 3 -#define B_EC_COMM_EXEC_CTL__M 0x7 -#define B_EC_COMM_EXEC_CTL_STOP 0x0 -#define B_EC_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EC_COMM_EXEC_CTL_HOLD 0x2 -#define B_EC_COMM_EXEC_CTL_STEP 0x3 -#define B_EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_EC_COMM_STATE__A 0x2000001 -#define B_EC_COMM_STATE__W 16 -#define B_EC_COMM_STATE__M 0xFFFF -#define B_EC_COMM_MB__A 0x2000002 -#define B_EC_COMM_MB__W 16 -#define B_EC_COMM_MB__M 0xFFFF -#define B_EC_COMM_SERVICE0__A 0x2000003 -#define B_EC_COMM_SERVICE0__W 16 -#define B_EC_COMM_SERVICE0__M 0xFFFF -#define B_EC_COMM_SERVICE1__A 0x2000004 -#define B_EC_COMM_SERVICE1__W 16 -#define B_EC_COMM_SERVICE1__M 0xFFFF -#define B_EC_COMM_INT_STA__A 0x2000007 -#define B_EC_COMM_INT_STA__W 16 -#define B_EC_COMM_INT_STA__M 0xFFFF -#define B_EC_COMM_INT_MSK__A 0x2000008 -#define B_EC_COMM_INT_MSK__W 16 -#define B_EC_COMM_INT_MSK__M 0xFFFF - -#define B_EC_SB_SID 0x16 - -#define B_EC_SB_REG_COMM_EXEC__A 0x2010000 -#define B_EC_SB_REG_COMM_EXEC__W 3 -#define B_EC_SB_REG_COMM_EXEC__M 0x7 -#define B_EC_SB_REG_COMM_EXEC_CTL__B 0 -#define B_EC_SB_REG_COMM_EXEC_CTL__W 3 -#define B_EC_SB_REG_COMM_EXEC_CTL__M 0x7 -#define B_EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define B_EC_SB_REG_COMM_STATE__A 0x2010001 -#define B_EC_SB_REG_COMM_STATE__W 4 -#define B_EC_SB_REG_COMM_STATE__M 0xF -#define B_EC_SB_REG_COMM_MB__A 0x2010002 -#define B_EC_SB_REG_COMM_MB__W 2 -#define B_EC_SB_REG_COMM_MB__M 0x3 -#define B_EC_SB_REG_COMM_MB_CTR__B 0 -#define B_EC_SB_REG_COMM_MB_CTR__W 1 -#define B_EC_SB_REG_COMM_MB_CTR__M 0x1 -#define B_EC_SB_REG_COMM_MB_CTR_OFF 0x0 -#define B_EC_SB_REG_COMM_MB_CTR_ON 0x1 -#define B_EC_SB_REG_COMM_MB_OBS__B 1 -#define B_EC_SB_REG_COMM_MB_OBS__W 1 -#define B_EC_SB_REG_COMM_MB_OBS__M 0x2 -#define B_EC_SB_REG_COMM_MB_OBS_OFF 0x0 -#define B_EC_SB_REG_COMM_MB_OBS_ON 0x2 - -#define B_EC_SB_REG_TR_MODE__A 0x2010010 -#define B_EC_SB_REG_TR_MODE__W 1 -#define B_EC_SB_REG_TR_MODE__M 0x1 -#define B_EC_SB_REG_TR_MODE_INIT 0x0 -#define B_EC_SB_REG_TR_MODE_8K 0x0 -#define B_EC_SB_REG_TR_MODE_2K 0x1 - -#define B_EC_SB_REG_CONST__A 0x2010011 -#define B_EC_SB_REG_CONST__W 2 -#define B_EC_SB_REG_CONST__M 0x3 -#define B_EC_SB_REG_CONST_INIT 0x2 -#define B_EC_SB_REG_CONST_QPSK 0x0 -#define B_EC_SB_REG_CONST_16QAM 0x1 -#define B_EC_SB_REG_CONST_64QAM 0x2 - -#define B_EC_SB_REG_ALPHA__A 0x2010012 -#define B_EC_SB_REG_ALPHA__W 3 -#define B_EC_SB_REG_ALPHA__M 0x7 - -#define B_EC_SB_REG_ALPHA_INIT 0x0 - -#define B_EC_SB_REG_ALPHA_NH 0x0 - -#define B_EC_SB_REG_ALPHA_H1 0x1 - -#define B_EC_SB_REG_ALPHA_H2 0x2 - -#define B_EC_SB_REG_ALPHA_H4 0x3 - -#define B_EC_SB_REG_PRIOR__A 0x2010013 -#define B_EC_SB_REG_PRIOR__W 1 -#define B_EC_SB_REG_PRIOR__M 0x1 -#define B_EC_SB_REG_PRIOR_INIT 0x0 -#define B_EC_SB_REG_PRIOR_HI 0x0 -#define B_EC_SB_REG_PRIOR_LO 0x1 - -#define B_EC_SB_REG_CSI_HI__A 0x2010014 -#define B_EC_SB_REG_CSI_HI__W 5 -#define B_EC_SB_REG_CSI_HI__M 0x1F -#define B_EC_SB_REG_CSI_HI_INIT 0x1F -#define B_EC_SB_REG_CSI_HI_MAX 0x1F -#define B_EC_SB_REG_CSI_HI_MIN 0x0 -#define B_EC_SB_REG_CSI_HI_TAG 0x0 - -#define B_EC_SB_REG_CSI_LO__A 0x2010015 -#define B_EC_SB_REG_CSI_LO__W 5 -#define B_EC_SB_REG_CSI_LO__M 0x1F -#define B_EC_SB_REG_CSI_LO_INIT 0x1E -#define B_EC_SB_REG_CSI_LO_MAX 0x1F -#define B_EC_SB_REG_CSI_LO_MIN 0x0 -#define B_EC_SB_REG_CSI_LO_TAG 0x0 - -#define B_EC_SB_REG_SMB_TGL__A 0x2010016 -#define B_EC_SB_REG_SMB_TGL__W 1 -#define B_EC_SB_REG_SMB_TGL__M 0x1 -#define B_EC_SB_REG_SMB_TGL_OFF 0x0 -#define B_EC_SB_REG_SMB_TGL_ON 0x1 -#define B_EC_SB_REG_SMB_TGL_INIT 0x1 - -#define B_EC_SB_REG_SNR_HI__A 0x2010017 -#define B_EC_SB_REG_SNR_HI__W 8 -#define B_EC_SB_REG_SNR_HI__M 0xFF -#define B_EC_SB_REG_SNR_HI_INIT 0x6E -#define B_EC_SB_REG_SNR_HI_MAX 0xFF -#define B_EC_SB_REG_SNR_HI_MIN 0x0 -#define B_EC_SB_REG_SNR_HI_TAG 0x0 - -#define B_EC_SB_REG_SNR_MID__A 0x2010018 -#define B_EC_SB_REG_SNR_MID__W 8 -#define B_EC_SB_REG_SNR_MID__M 0xFF -#define B_EC_SB_REG_SNR_MID_INIT 0x6C -#define B_EC_SB_REG_SNR_MID_MAX 0xFF -#define B_EC_SB_REG_SNR_MID_MIN 0x0 -#define B_EC_SB_REG_SNR_MID_TAG 0x0 - -#define B_EC_SB_REG_SNR_LO__A 0x2010019 -#define B_EC_SB_REG_SNR_LO__W 8 -#define B_EC_SB_REG_SNR_LO__M 0xFF -#define B_EC_SB_REG_SNR_LO_INIT 0x68 -#define B_EC_SB_REG_SNR_LO_MAX 0xFF -#define B_EC_SB_REG_SNR_LO_MIN 0x0 -#define B_EC_SB_REG_SNR_LO_TAG 0x0 - -#define B_EC_SB_REG_SCALE_MSB__A 0x201001A -#define B_EC_SB_REG_SCALE_MSB__W 6 -#define B_EC_SB_REG_SCALE_MSB__M 0x3F -#define B_EC_SB_REG_SCALE_MSB_INIT 0x30 -#define B_EC_SB_REG_SCALE_MSB_MAX 0x3F - -#define B_EC_SB_REG_SCALE_BIT2__A 0x201001B -#define B_EC_SB_REG_SCALE_BIT2__W 6 -#define B_EC_SB_REG_SCALE_BIT2__M 0x3F -#define B_EC_SB_REG_SCALE_BIT2_INIT 0xC -#define B_EC_SB_REG_SCALE_BIT2_MAX 0x3F - -#define B_EC_SB_REG_SCALE_LSB__A 0x201001C -#define B_EC_SB_REG_SCALE_LSB__W 6 -#define B_EC_SB_REG_SCALE_LSB__M 0x3F -#define B_EC_SB_REG_SCALE_LSB_INIT 0x3 -#define B_EC_SB_REG_SCALE_LSB_MAX 0x3F - -#define B_EC_SB_REG_CSI_OFS0__A 0x201001D -#define B_EC_SB_REG_CSI_OFS0__W 4 -#define B_EC_SB_REG_CSI_OFS0__M 0xF -#define B_EC_SB_REG_CSI_OFS0_INIT 0x4 - -#define B_EC_SB_REG_CSI_OFS1__A 0x201001E -#define B_EC_SB_REG_CSI_OFS1__W 4 -#define B_EC_SB_REG_CSI_OFS1__M 0xF -#define B_EC_SB_REG_CSI_OFS1_INIT 0x1 - -#define B_EC_SB_REG_CSI_OFS2__A 0x201001F -#define B_EC_SB_REG_CSI_OFS2__W 4 -#define B_EC_SB_REG_CSI_OFS2__M 0xF -#define B_EC_SB_REG_CSI_OFS2_INIT 0x2 - -#define B_EC_SB_REG_MAX0__A 0x2010020 -#define B_EC_SB_REG_MAX0__W 6 -#define B_EC_SB_REG_MAX0__M 0x3F -#define B_EC_SB_REG_MAX0_INIT 0x3F - -#define B_EC_SB_REG_MAX1__A 0x2010021 -#define B_EC_SB_REG_MAX1__W 6 -#define B_EC_SB_REG_MAX1__M 0x3F -#define B_EC_SB_REG_MAX1_INIT 0x3F - -#define B_EC_SB_REG_MAX2__A 0x2010022 -#define B_EC_SB_REG_MAX2__W 6 -#define B_EC_SB_REG_MAX2__M 0x3F -#define B_EC_SB_REG_MAX2_INIT 0x3F - -#define B_EC_SB_REG_CSI_DIS__A 0x2010023 -#define B_EC_SB_REG_CSI_DIS__W 1 -#define B_EC_SB_REG_CSI_DIS__M 0x1 -#define B_EC_SB_REG_CSI_DIS_INIT 0x0 - -#define B_EC_SB_SD_RAM__A 0x2020000 - -#define B_EC_SB_BD0_RAM__A 0x2030000 - -#define B_EC_SB_BD1_RAM__A 0x2040000 - -#define B_EC_VD_SID 0x17 - -#define B_EC_VD_REG_COMM_EXEC__A 0x2090000 -#define B_EC_VD_REG_COMM_EXEC__W 3 -#define B_EC_VD_REG_COMM_EXEC__M 0x7 -#define B_EC_VD_REG_COMM_EXEC_CTL__B 0 -#define B_EC_VD_REG_COMM_EXEC_CTL__W 3 -#define B_EC_VD_REG_COMM_EXEC_CTL__M 0x7 -#define B_EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define B_EC_VD_REG_COMM_STATE__A 0x2090001 -#define B_EC_VD_REG_COMM_STATE__W 4 -#define B_EC_VD_REG_COMM_STATE__M 0xF -#define B_EC_VD_REG_COMM_MB__A 0x2090002 -#define B_EC_VD_REG_COMM_MB__W 2 -#define B_EC_VD_REG_COMM_MB__M 0x3 -#define B_EC_VD_REG_COMM_MB_CTR__B 0 -#define B_EC_VD_REG_COMM_MB_CTR__W 1 -#define B_EC_VD_REG_COMM_MB_CTR__M 0x1 -#define B_EC_VD_REG_COMM_MB_CTR_OFF 0x0 -#define B_EC_VD_REG_COMM_MB_CTR_ON 0x1 -#define B_EC_VD_REG_COMM_MB_OBS__B 1 -#define B_EC_VD_REG_COMM_MB_OBS__W 1 -#define B_EC_VD_REG_COMM_MB_OBS__M 0x2 -#define B_EC_VD_REG_COMM_MB_OBS_OFF 0x0 -#define B_EC_VD_REG_COMM_MB_OBS_ON 0x2 - -#define B_EC_VD_REG_COMM_SERVICE0__A 0x2090003 -#define B_EC_VD_REG_COMM_SERVICE0__W 16 -#define B_EC_VD_REG_COMM_SERVICE0__M 0xFFFF -#define B_EC_VD_REG_COMM_SERVICE1__A 0x2090004 -#define B_EC_VD_REG_COMM_SERVICE1__W 16 -#define B_EC_VD_REG_COMM_SERVICE1__M 0xFFFF -#define B_EC_VD_REG_COMM_INT_STA__A 0x2090007 -#define B_EC_VD_REG_COMM_INT_STA__W 1 -#define B_EC_VD_REG_COMM_INT_STA__M 0x1 -#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 -#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 -#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 - -#define B_EC_VD_REG_COMM_INT_MSK__A 0x2090008 -#define B_EC_VD_REG_COMM_INT_MSK__W 1 -#define B_EC_VD_REG_COMM_INT_MSK__M 0x1 -#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 -#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 -#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 - -#define B_EC_VD_REG_FORCE__A 0x2090010 -#define B_EC_VD_REG_FORCE__W 2 -#define B_EC_VD_REG_FORCE__M 0x3 -#define B_EC_VD_REG_FORCE_INIT 0x2 -#define B_EC_VD_REG_FORCE_FREE 0x0 -#define B_EC_VD_REG_FORCE_PROP 0x1 -#define B_EC_VD_REG_FORCE_FORCED 0x2 -#define B_EC_VD_REG_FORCE_FIXED 0x3 - -#define B_EC_VD_REG_SET_CODERATE__A 0x2090011 -#define B_EC_VD_REG_SET_CODERATE__W 3 -#define B_EC_VD_REG_SET_CODERATE__M 0x7 -#define B_EC_VD_REG_SET_CODERATE_INIT 0x1 -#define B_EC_VD_REG_SET_CODERATE_C1_2 0x0 -#define B_EC_VD_REG_SET_CODERATE_C2_3 0x1 -#define B_EC_VD_REG_SET_CODERATE_C3_4 0x2 -#define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 -#define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 - -#define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 -#define B_EC_VD_REG_REQ_SMB_CNT__W 16 -#define B_EC_VD_REG_REQ_SMB_CNT__M 0xFFFF -#define B_EC_VD_REG_REQ_SMB_CNT_INIT 0x1 - -#define B_EC_VD_REG_REQ_BIT_CNT__A 0x2090013 -#define B_EC_VD_REG_REQ_BIT_CNT__W 16 -#define B_EC_VD_REG_REQ_BIT_CNT__M 0xFFFF -#define B_EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF - -#define B_EC_VD_REG_RLK_ENA__A 0x2090014 -#define B_EC_VD_REG_RLK_ENA__W 1 -#define B_EC_VD_REG_RLK_ENA__M 0x1 -#define B_EC_VD_REG_RLK_ENA_INIT 0x1 -#define B_EC_VD_REG_RLK_ENA_OFF 0x0 -#define B_EC_VD_REG_RLK_ENA_ON 0x1 - -#define B_EC_VD_REG_VAL__A 0x2090015 -#define B_EC_VD_REG_VAL__W 2 -#define B_EC_VD_REG_VAL__M 0x3 -#define B_EC_VD_REG_VAL_INIT 0x0 -#define B_EC_VD_REG_VAL_CODE 0x1 -#define B_EC_VD_REG_VAL_CNT 0x2 - -#define B_EC_VD_REG_GET_CODERATE__A 0x2090016 -#define B_EC_VD_REG_GET_CODERATE__W 3 -#define B_EC_VD_REG_GET_CODERATE__M 0x7 -#define B_EC_VD_REG_GET_CODERATE_INIT 0x0 -#define B_EC_VD_REG_GET_CODERATE_C1_2 0x0 -#define B_EC_VD_REG_GET_CODERATE_C2_3 0x1 -#define B_EC_VD_REG_GET_CODERATE_C3_4 0x2 -#define B_EC_VD_REG_GET_CODERATE_C5_6 0x3 -#define B_EC_VD_REG_GET_CODERATE_C7_8 0x4 - -#define B_EC_VD_REG_ERR_BIT_CNT__A 0x2090017 -#define B_EC_VD_REG_ERR_BIT_CNT__W 16 -#define B_EC_VD_REG_ERR_BIT_CNT__M 0xFFFF -#define B_EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF - -#define B_EC_VD_REG_IN_BIT_CNT__A 0x2090018 -#define B_EC_VD_REG_IN_BIT_CNT__W 16 -#define B_EC_VD_REG_IN_BIT_CNT__M 0xFFFF -#define B_EC_VD_REG_IN_BIT_CNT_INIT 0x0 - -#define B_EC_VD_REG_STS__A 0x2090019 -#define B_EC_VD_REG_STS__W 1 -#define B_EC_VD_REG_STS__M 0x1 -#define B_EC_VD_REG_STS_INIT 0x0 -#define B_EC_VD_REG_STS_NO_LOCK 0x0 -#define B_EC_VD_REG_STS_IN_LOCK 0x1 - -#define B_EC_VD_REG_RLK_CNT__A 0x209001A -#define B_EC_VD_REG_RLK_CNT__W 16 -#define B_EC_VD_REG_RLK_CNT__M 0xFFFF -#define B_EC_VD_REG_RLK_CNT_INIT 0x0 - -#define B_EC_VD_TB0_RAM__A 0x20A0000 - -#define B_EC_VD_TB1_RAM__A 0x20B0000 - -#define B_EC_VD_TB2_RAM__A 0x20C0000 - -#define B_EC_VD_TB3_RAM__A 0x20D0000 - -#define B_EC_VD_RE_RAM__A 0x2100000 - -#define B_EC_OD_SID 0x18 - -#define B_EC_OD_REG_COMM_EXEC__A 0x2110000 -#define B_EC_OD_REG_COMM_EXEC__W 3 -#define B_EC_OD_REG_COMM_EXEC__M 0x7 -#define B_EC_OD_REG_COMM_EXEC_CTL__B 0 -#define B_EC_OD_REG_COMM_EXEC_CTL__W 3 -#define B_EC_OD_REG_COMM_EXEC_CTL__M 0x7 -#define B_EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_EC_OD_REG_COMM_STATE__A 0x2110001 -#define B_EC_OD_REG_COMM_STATE__W 1 -#define B_EC_OD_REG_COMM_STATE__M 0x1 -#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__B 0 -#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__W 1 -#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__M 0x1 - -#define B_EC_OD_REG_COMM_MB__A 0x2110002 -#define B_EC_OD_REG_COMM_MB__W 3 -#define B_EC_OD_REG_COMM_MB__M 0x7 -#define B_EC_OD_REG_COMM_MB_CTR__B 0 -#define B_EC_OD_REG_COMM_MB_CTR__W 1 -#define B_EC_OD_REG_COMM_MB_CTR__M 0x1 -#define B_EC_OD_REG_COMM_MB_CTR_OFF 0x0 -#define B_EC_OD_REG_COMM_MB_CTR_ON 0x1 -#define B_EC_OD_REG_COMM_MB_OBS__B 1 -#define B_EC_OD_REG_COMM_MB_OBS__W 1 -#define B_EC_OD_REG_COMM_MB_OBS__M 0x2 -#define B_EC_OD_REG_COMM_MB_OBS_OFF 0x0 -#define B_EC_OD_REG_COMM_MB_OBS_ON 0x2 - -#define B_EC_OD_REG_COMM_SERVICE0__A 0x2110003 -#define B_EC_OD_REG_COMM_SERVICE0__W 10 -#define B_EC_OD_REG_COMM_SERVICE0__M 0x3FF -#define B_EC_OD_REG_COMM_SERVICE1__A 0x2110004 -#define B_EC_OD_REG_COMM_SERVICE1__W 11 -#define B_EC_OD_REG_COMM_SERVICE1__M 0x7FF - -#define B_EC_OD_REG_COMM_ACTIVATE__A 0x2110005 -#define B_EC_OD_REG_COMM_ACTIVATE__W 2 -#define B_EC_OD_REG_COMM_ACTIVATE__M 0x3 - -#define B_EC_OD_REG_COMM_COUNT__A 0x2110006 -#define B_EC_OD_REG_COMM_COUNT__W 16 -#define B_EC_OD_REG_COMM_COUNT__M 0xFFFF - -#define B_EC_OD_REG_COMM_INT_STA__A 0x2110007 -#define B_EC_OD_REG_COMM_INT_STA__W 2 -#define B_EC_OD_REG_COMM_INT_STA__M 0x3 -#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 -#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 -#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 -#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 -#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 -#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 - -#define B_EC_OD_REG_COMM_INT_MSK__A 0x2110008 -#define B_EC_OD_REG_COMM_INT_MSK__W 2 -#define B_EC_OD_REG_COMM_INT_MSK__M 0x3 -#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 -#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 -#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 -#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 -#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 -#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 - -#define B_EC_OD_REG_SYNC__A 0x2110664 -#define B_EC_OD_REG_SYNC__W 12 -#define B_EC_OD_REG_SYNC__M 0xFFF -#define B_EC_OD_REG_SYNC_NR_SYNC__B 0 -#define B_EC_OD_REG_SYNC_NR_SYNC__W 5 -#define B_EC_OD_REG_SYNC_NR_SYNC__M 0x1F -#define B_EC_OD_REG_SYNC_IN_SYNC__B 5 -#define B_EC_OD_REG_SYNC_IN_SYNC__W 4 -#define B_EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 -#define B_EC_OD_REG_SYNC_OUT_SYNC__B 9 -#define B_EC_OD_REG_SYNC_OUT_SYNC__W 3 -#define B_EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 - -#define B_EC_OD_REG_NOSYNC__A 0x2110004 -#define B_EC_OD_REG_NOSYNC__W 8 -#define B_EC_OD_REG_NOSYNC__M 0xFF - -#define B_EC_OD_DEINT_RAM__A 0x2120000 - -#define B_EC_RS_SID 0x19 - -#define B_EC_RS_REG_COMM_EXEC__A 0x2130000 -#define B_EC_RS_REG_COMM_EXEC__W 3 -#define B_EC_RS_REG_COMM_EXEC__M 0x7 -#define B_EC_RS_REG_COMM_EXEC_CTL__B 0 -#define B_EC_RS_REG_COMM_EXEC_CTL__W 3 -#define B_EC_RS_REG_COMM_EXEC_CTL__M 0x7 -#define B_EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define B_EC_RS_REG_COMM_STATE__A 0x2130001 -#define B_EC_RS_REG_COMM_STATE__W 4 -#define B_EC_RS_REG_COMM_STATE__M 0xF -#define B_EC_RS_REG_COMM_MB__A 0x2130002 -#define B_EC_RS_REG_COMM_MB__W 2 -#define B_EC_RS_REG_COMM_MB__M 0x3 -#define B_EC_RS_REG_COMM_MB_CTR__B 0 -#define B_EC_RS_REG_COMM_MB_CTR__W 1 -#define B_EC_RS_REG_COMM_MB_CTR__M 0x1 -#define B_EC_RS_REG_COMM_MB_CTR_OFF 0x0 -#define B_EC_RS_REG_COMM_MB_CTR_ON 0x1 -#define B_EC_RS_REG_COMM_MB_OBS__B 1 -#define B_EC_RS_REG_COMM_MB_OBS__W 1 -#define B_EC_RS_REG_COMM_MB_OBS__M 0x2 -#define B_EC_RS_REG_COMM_MB_OBS_OFF 0x0 -#define B_EC_RS_REG_COMM_MB_OBS_ON 0x2 - -#define B_EC_RS_REG_COMM_SERVICE0__A 0x2130003 -#define B_EC_RS_REG_COMM_SERVICE0__W 16 -#define B_EC_RS_REG_COMM_SERVICE0__M 0xFFFF -#define B_EC_RS_REG_COMM_SERVICE1__A 0x2130004 -#define B_EC_RS_REG_COMM_SERVICE1__W 16 -#define B_EC_RS_REG_COMM_SERVICE1__M 0xFFFF -#define B_EC_RS_REG_COMM_INT_STA__A 0x2130007 -#define B_EC_RS_REG_COMM_INT_STA__W 1 -#define B_EC_RS_REG_COMM_INT_STA__M 0x1 -#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 -#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 -#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 - -#define B_EC_RS_REG_COMM_INT_MSK__A 0x2130008 -#define B_EC_RS_REG_COMM_INT_MSK__W 1 -#define B_EC_RS_REG_COMM_INT_MSK__M 0x1 -#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 -#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 -#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 - -#define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 -#define B_EC_RS_REG_REQ_PCK_CNT__W 16 -#define B_EC_RS_REG_REQ_PCK_CNT__M 0xFFFF -#define B_EC_RS_REG_REQ_PCK_CNT_INIT 0x200 - -#define B_EC_RS_REG_VAL__A 0x2130011 -#define B_EC_RS_REG_VAL__W 1 -#define B_EC_RS_REG_VAL__M 0x1 -#define B_EC_RS_REG_VAL_INIT 0x0 -#define B_EC_RS_REG_VAL_PCK 0x1 - -#define B_EC_RS_REG_ERR_PCK_CNT__A 0x2130012 -#define B_EC_RS_REG_ERR_PCK_CNT__W 16 -#define B_EC_RS_REG_ERR_PCK_CNT__M 0xFFFF -#define B_EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF - -#define B_EC_RS_REG_ERR_SMB_CNT__A 0x2130013 -#define B_EC_RS_REG_ERR_SMB_CNT__W 16 -#define B_EC_RS_REG_ERR_SMB_CNT__M 0xFFFF -#define B_EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF - -#define B_EC_RS_REG_ERR_BIT_CNT__A 0x2130014 -#define B_EC_RS_REG_ERR_BIT_CNT__W 16 -#define B_EC_RS_REG_ERR_BIT_CNT__M 0xFFFF -#define B_EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF - -#define B_EC_RS_REG_IN_PCK_CNT__A 0x2130015 -#define B_EC_RS_REG_IN_PCK_CNT__W 16 -#define B_EC_RS_REG_IN_PCK_CNT__M 0xFFFF -#define B_EC_RS_REG_IN_PCK_CNT_INIT 0x0 - -#define B_EC_RS_EC_RAM__A 0x2140000 - -#define B_EC_OC_SID 0x1A - -#define B_EC_OC_REG_COMM_EXEC__A 0x2150000 -#define B_EC_OC_REG_COMM_EXEC__W 3 -#define B_EC_OC_REG_COMM_EXEC__M 0x7 -#define B_EC_OC_REG_COMM_EXEC_CTL__B 0 -#define B_EC_OC_REG_COMM_EXEC_CTL__W 3 -#define B_EC_OC_REG_COMM_EXEC_CTL__M 0x7 -#define B_EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_EC_OC_REG_COMM_STATE__A 0x2150001 -#define B_EC_OC_REG_COMM_STATE__W 4 -#define B_EC_OC_REG_COMM_STATE__M 0xF - -#define B_EC_OC_REG_COMM_MB__A 0x2150002 -#define B_EC_OC_REG_COMM_MB__W 2 -#define B_EC_OC_REG_COMM_MB__M 0x3 -#define B_EC_OC_REG_COMM_MB_CTR__B 0 -#define B_EC_OC_REG_COMM_MB_CTR__W 1 -#define B_EC_OC_REG_COMM_MB_CTR__M 0x1 -#define B_EC_OC_REG_COMM_MB_CTR_OFF 0x0 -#define B_EC_OC_REG_COMM_MB_CTR_ON 0x1 -#define B_EC_OC_REG_COMM_MB_OBS__B 1 -#define B_EC_OC_REG_COMM_MB_OBS__W 1 -#define B_EC_OC_REG_COMM_MB_OBS__M 0x2 -#define B_EC_OC_REG_COMM_MB_OBS_OFF 0x0 -#define B_EC_OC_REG_COMM_MB_OBS_ON 0x2 - -#define B_EC_OC_REG_COMM_SERVICE0__A 0x2150003 -#define B_EC_OC_REG_COMM_SERVICE0__W 10 -#define B_EC_OC_REG_COMM_SERVICE0__M 0x3FF - -#define B_EC_OC_REG_COMM_SERVICE1__A 0x2150004 -#define B_EC_OC_REG_COMM_SERVICE1__W 11 -#define B_EC_OC_REG_COMM_SERVICE1__M 0x7FF - -#define B_EC_OC_REG_COMM_INT_STA__A 0x2150007 -#define B_EC_OC_REG_COMM_INT_STA__W 6 -#define B_EC_OC_REG_COMM_INT_STA__M 0x3F -#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 -#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 -#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 -#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 -#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 -#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 -#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 -#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 -#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 -#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 -#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 -#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 -#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 -#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 -#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 - -#define B_EC_OC_REG_COMM_INT_MSK__A 0x2150008 -#define B_EC_OC_REG_COMM_INT_MSK__W 6 -#define B_EC_OC_REG_COMM_INT_MSK__M 0x3F -#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 -#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 -#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 -#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 -#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 -#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 - -#define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 -#define B_EC_OC_REG_OC_MODE_LOP__W 16 -#define B_EC_OC_REG_OC_MODE_LOP__M 0xFFFF -#define B_EC_OC_REG_OC_MODE_LOP_INIT 0x0 - -#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 -#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 -#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 - -#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 -#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 -#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 - -#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 -#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 -#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 - -#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 -#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 -#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 - -#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 -#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 -#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 - -#define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 -#define B_EC_OC_REG_OC_MODE_HIP__W 15 -#define B_EC_OC_REG_OC_MODE_HIP__M 0x7FFF -#define B_EC_OC_REG_OC_MODE_HIP_INIT 0x5 - -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 - -#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 -#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 -#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 - -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 - -#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 -#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 -#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 - -#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 -#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 -#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 - -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 - -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 - -#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__B 14 -#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__M 0x4000 -#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_ZER 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_CLC 0x4000 - -#define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 -#define B_EC_OC_REG_OC_MPG_SIO__W 12 -#define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF -#define B_EC_OC_REG_OC_MPG_SIO_INIT 0xFFF - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 - -#define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 -#define B_EC_OC_REG_DTO_INC_LOP__W 16 -#define B_EC_OC_REG_DTO_INC_LOP__M 0xFFFF -#define B_EC_OC_REG_DTO_INC_LOP_INIT 0x0 - -#define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 -#define B_EC_OC_REG_DTO_INC_HIP__W 8 -#define B_EC_OC_REG_DTO_INC_HIP__M 0xFF -#define B_EC_OC_REG_DTO_INC_HIP_INIT 0xC0 - -#define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 -#define B_EC_OC_REG_SNC_ISC_LVL__W 12 -#define B_EC_OC_REG_SNC_ISC_LVL__M 0xFFF -#define B_EC_OC_REG_SNC_ISC_LVL_INIT 0x422 - -#define B_EC_OC_REG_SNC_ISC_LVL_ISC__B 0 -#define B_EC_OC_REG_SNC_ISC_LVL_ISC__W 4 -#define B_EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF - -#define B_EC_OC_REG_SNC_ISC_LVL_OSC__B 4 -#define B_EC_OC_REG_SNC_ISC_LVL_OSC__W 4 -#define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 - -#define B_EC_OC_REG_SNC_ISC_LVL_NSC__B 8 -#define B_EC_OC_REG_SNC_ISC_LVL_NSC__W 4 -#define B_EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 - -#define B_EC_OC_REG_SNC_NSC_LVL__A 0x2150017 -#define B_EC_OC_REG_SNC_NSC_LVL__W 8 -#define B_EC_OC_REG_SNC_NSC_LVL__M 0xFF -#define B_EC_OC_REG_SNC_NSC_LVL_INIT 0x0 - -#define B_EC_OC_REG_SNC_SNC_MODE__A 0x2150019 -#define B_EC_OC_REG_SNC_SNC_MODE__W 2 -#define B_EC_OC_REG_SNC_SNC_MODE__M 0x3 -#define B_EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 -#define B_EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 -#define B_EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 - -#define B_EC_OC_REG_SNC_PCK_NMB__A 0x215001A -#define B_EC_OC_REG_SNC_PCK_NMB__W 16 -#define B_EC_OC_REG_SNC_PCK_NMB__M 0xFFFF - -#define B_EC_OC_REG_SNC_PCK_CNT__A 0x215001B -#define B_EC_OC_REG_SNC_PCK_CNT__W 16 -#define B_EC_OC_REG_SNC_PCK_CNT__M 0xFFFF - -#define B_EC_OC_REG_SNC_PCK_ERR__A 0x215001C -#define B_EC_OC_REG_SNC_PCK_ERR__W 16 -#define B_EC_OC_REG_SNC_PCK_ERR__M 0xFFFF - -#define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D -#define B_EC_OC_REG_TMD_TOP_MODE__W 2 -#define B_EC_OC_REG_TMD_TOP_MODE__M 0x3 -#define B_EC_OC_REG_TMD_TOP_MODE_INIT 0x3 -#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 -#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 -#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 -#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 - -#define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E -#define B_EC_OC_REG_TMD_TOP_CNT__W 10 -#define B_EC_OC_REG_TMD_TOP_CNT__M 0x3FF -#define B_EC_OC_REG_TMD_TOP_CNT_INIT 0x1F4 - -#define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F -#define B_EC_OC_REG_TMD_HIL_MAR__W 10 -#define B_EC_OC_REG_TMD_HIL_MAR__M 0x3FF -#define B_EC_OC_REG_TMD_HIL_MAR_INIT 0x3C0 - -#define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 -#define B_EC_OC_REG_TMD_LOL_MAR__W 10 -#define B_EC_OC_REG_TMD_LOL_MAR__M 0x3FF -#define B_EC_OC_REG_TMD_LOL_MAR_INIT 0x40 - -#define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 -#define B_EC_OC_REG_TMD_CUR_CNT__W 4 -#define B_EC_OC_REG_TMD_CUR_CNT__M 0xF -#define B_EC_OC_REG_TMD_CUR_CNT_INIT 0x3 - -#define B_EC_OC_REG_TMD_IUR_CNT__A 0x2150022 -#define B_EC_OC_REG_TMD_IUR_CNT__W 4 -#define B_EC_OC_REG_TMD_IUR_CNT__M 0xF -#define B_EC_OC_REG_TMD_IUR_CNT_INIT 0x0 - -#define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 -#define B_EC_OC_REG_AVR_ASH_CNT__W 4 -#define B_EC_OC_REG_AVR_ASH_CNT__M 0xF -#define B_EC_OC_REG_AVR_ASH_CNT_INIT 0x6 - -#define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 -#define B_EC_OC_REG_AVR_BSH_CNT__W 4 -#define B_EC_OC_REG_AVR_BSH_CNT__M 0xF -#define B_EC_OC_REG_AVR_BSH_CNT_INIT 0x2 - -#define B_EC_OC_REG_AVR_AVE_LOP__A 0x2150025 -#define B_EC_OC_REG_AVR_AVE_LOP__W 16 -#define B_EC_OC_REG_AVR_AVE_LOP__M 0xFFFF - -#define B_EC_OC_REG_AVR_AVE_HIP__A 0x2150026 -#define B_EC_OC_REG_AVR_AVE_HIP__W 5 -#define B_EC_OC_REG_AVR_AVE_HIP__M 0x1F - -#define B_EC_OC_REG_RCN_MODE__A 0x2150027 -#define B_EC_OC_REG_RCN_MODE__W 3 -#define B_EC_OC_REG_RCN_MODE__M 0x7 -#define B_EC_OC_REG_RCN_MODE_INIT 0x7 - -#define B_EC_OC_REG_RCN_MODE_MODE_0__B 0 -#define B_EC_OC_REG_RCN_MODE_MODE_0__W 1 -#define B_EC_OC_REG_RCN_MODE_MODE_0__M 0x1 -#define B_EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 -#define B_EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 - -#define B_EC_OC_REG_RCN_MODE_MODE_1__B 1 -#define B_EC_OC_REG_RCN_MODE_MODE_1__W 1 -#define B_EC_OC_REG_RCN_MODE_MODE_1__M 0x2 -#define B_EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 -#define B_EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 - -#define B_EC_OC_REG_RCN_MODE_MODE_2__B 2 -#define B_EC_OC_REG_RCN_MODE_MODE_2__W 1 -#define B_EC_OC_REG_RCN_MODE_MODE_2__M 0x4 -#define B_EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 -#define B_EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 - -#define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 -#define B_EC_OC_REG_RCN_CRA_LOP__W 16 -#define B_EC_OC_REG_RCN_CRA_LOP__M 0xFFFF -#define B_EC_OC_REG_RCN_CRA_LOP_INIT 0x0 - -#define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 -#define B_EC_OC_REG_RCN_CRA_HIP__W 8 -#define B_EC_OC_REG_RCN_CRA_HIP__M 0xFF -#define B_EC_OC_REG_RCN_CRA_HIP_INIT 0xC0 - -#define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A -#define B_EC_OC_REG_RCN_CST_LOP__W 16 -#define B_EC_OC_REG_RCN_CST_LOP__M 0xFFFF -#define B_EC_OC_REG_RCN_CST_LOP_INIT 0x1000 - -#define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B -#define B_EC_OC_REG_RCN_CST_HIP__W 8 -#define B_EC_OC_REG_RCN_CST_HIP__M 0xFF -#define B_EC_OC_REG_RCN_CST_HIP_INIT 0x0 - -#define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C -#define B_EC_OC_REG_RCN_SET_LVL__W 9 -#define B_EC_OC_REG_RCN_SET_LVL__M 0x1FF -#define B_EC_OC_REG_RCN_SET_LVL_INIT 0x1FF - -#define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D -#define B_EC_OC_REG_RCN_GAI_LVL__W 4 -#define B_EC_OC_REG_RCN_GAI_LVL__M 0xF -#define B_EC_OC_REG_RCN_GAI_LVL_INIT 0xA - -#define B_EC_OC_REG_RCN_DRA_LOP__A 0x215002E -#define B_EC_OC_REG_RCN_DRA_LOP__W 16 -#define B_EC_OC_REG_RCN_DRA_LOP__M 0xFFFF - -#define B_EC_OC_REG_RCN_DRA_HIP__A 0x215002F -#define B_EC_OC_REG_RCN_DRA_HIP__W 8 -#define B_EC_OC_REG_RCN_DRA_HIP__M 0xFF - -#define B_EC_OC_REG_RCN_DOF_LOP__A 0x2150030 -#define B_EC_OC_REG_RCN_DOF_LOP__W 16 -#define B_EC_OC_REG_RCN_DOF_LOP__M 0xFFFF - -#define B_EC_OC_REG_RCN_DOF_HIP__A 0x2150031 -#define B_EC_OC_REG_RCN_DOF_HIP__W 8 -#define B_EC_OC_REG_RCN_DOF_HIP__M 0xFF - -#define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032 -#define B_EC_OC_REG_RCN_CLP_LOP__W 16 -#define B_EC_OC_REG_RCN_CLP_LOP__M 0xFFFF -#define B_EC_OC_REG_RCN_CLP_LOP_INIT 0x0 - -#define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 -#define B_EC_OC_REG_RCN_CLP_HIP__W 8 -#define B_EC_OC_REG_RCN_CLP_HIP__M 0xFF -#define B_EC_OC_REG_RCN_CLP_HIP_INIT 0xC0 - -#define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 -#define B_EC_OC_REG_RCN_MAP_LOP__W 16 -#define B_EC_OC_REG_RCN_MAP_LOP__M 0xFFFF - -#define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035 -#define B_EC_OC_REG_RCN_MAP_HIP__W 8 -#define B_EC_OC_REG_RCN_MAP_HIP__M 0xFF - -#define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036 -#define B_EC_OC_REG_OCR_MPG_UOS__W 12 -#define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF -#define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 - -#define B_EC_OC_REG_OCR_MPG_UOS_ERR__B 8 -#define B_EC_OC_REG_OCR_MPG_UOS_ERR__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 -#define B_EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 - -#define B_EC_OC_REG_OCR_MPG_UOS_STR__B 9 -#define B_EC_OC_REG_OCR_MPG_UOS_STR__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 -#define B_EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 - -#define B_EC_OC_REG_OCR_MPG_UOS_VAL__B 10 -#define B_EC_OC_REG_OCR_MPG_UOS_VAL__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 -#define B_EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 - -#define B_EC_OC_REG_OCR_MPG_UOS_CLK__B 11 -#define B_EC_OC_REG_OCR_MPG_UOS_CLK__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 -#define B_EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 - -#define B_EC_OC_REG_OCR_MPG_WRI__A 0x2150037 -#define B_EC_OC_REG_OCR_MPG_WRI__W 12 -#define B_EC_OC_REG_OCR_MPG_WRI__M 0xFFF -#define B_EC_OC_REG_OCR_MPG_WRI_INIT 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 -#define B_EC_OC_REG_OCR_MPG_WRI_ERR__B 8 -#define B_EC_OC_REG_OCR_MPG_WRI_ERR__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 -#define B_EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 -#define B_EC_OC_REG_OCR_MPG_WRI_STR__B 9 -#define B_EC_OC_REG_OCR_MPG_WRI_STR__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 -#define B_EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 -#define B_EC_OC_REG_OCR_MPG_WRI_VAL__B 10 -#define B_EC_OC_REG_OCR_MPG_WRI_VAL__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 -#define B_EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 -#define B_EC_OC_REG_OCR_MPG_WRI_CLK__B 11 -#define B_EC_OC_REG_OCR_MPG_WRI_CLK__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 -#define B_EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 - -#define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 -#define B_EC_OC_REG_OCR_MPG_USR_DAT__W 12 -#define B_EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF - -#define B_EC_OC_REG_OCR_MON_CNT__A 0x215003C -#define B_EC_OC_REG_OCR_MON_CNT__W 14 -#define B_EC_OC_REG_OCR_MON_CNT__M 0x3FFF -#define B_EC_OC_REG_OCR_MON_CNT_INIT 0x0 - -#define B_EC_OC_REG_OCR_MON_RDX__A 0x215003D -#define B_EC_OC_REG_OCR_MON_RDX__W 1 -#define B_EC_OC_REG_OCR_MON_RDX__M 0x1 -#define B_EC_OC_REG_OCR_MON_RDX_INIT 0x0 - -#define B_EC_OC_REG_OCR_MON_RD0__A 0x215003E -#define B_EC_OC_REG_OCR_MON_RD0__W 10 -#define B_EC_OC_REG_OCR_MON_RD0__M 0x3FF - -#define B_EC_OC_REG_OCR_MON_RD1__A 0x215003F -#define B_EC_OC_REG_OCR_MON_RD1__W 10 -#define B_EC_OC_REG_OCR_MON_RD1__M 0x3FF - -#define B_EC_OC_REG_OCR_MON_RD2__A 0x2150040 -#define B_EC_OC_REG_OCR_MON_RD2__W 10 -#define B_EC_OC_REG_OCR_MON_RD2__M 0x3FF - -#define B_EC_OC_REG_OCR_MON_RD3__A 0x2150041 -#define B_EC_OC_REG_OCR_MON_RD3__W 10 -#define B_EC_OC_REG_OCR_MON_RD3__M 0x3FF - -#define B_EC_OC_REG_OCR_MON_RD4__A 0x2150042 -#define B_EC_OC_REG_OCR_MON_RD4__W 10 -#define B_EC_OC_REG_OCR_MON_RD4__M 0x3FF - -#define B_EC_OC_REG_OCR_MON_RD5__A 0x2150043 -#define B_EC_OC_REG_OCR_MON_RD5__W 10 -#define B_EC_OC_REG_OCR_MON_RD5__M 0x3FF - -#define B_EC_OC_REG_OCR_INV_MON__A 0x2150044 -#define B_EC_OC_REG_OCR_INV_MON__W 12 -#define B_EC_OC_REG_OCR_INV_MON__M 0xFFF -#define B_EC_OC_REG_OCR_INV_MON_INIT 0x0 - -#define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 -#define B_EC_OC_REG_IPR_INV_MPG__W 12 -#define B_EC_OC_REG_IPR_INV_MPG__M 0xFFF -#define B_EC_OC_REG_IPR_INV_MPG_INIT 0x0 - -#define B_EC_OC_REG_IPR_MSR_SNC__A 0x2150046 -#define B_EC_OC_REG_IPR_MSR_SNC__W 6 -#define B_EC_OC_REG_IPR_MSR_SNC__M 0x3F -#define B_EC_OC_REG_IPR_MSR_SNC_INIT 0x0 - -#define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 -#define B_EC_OC_REG_DTO_CLKMODE__W 2 -#define B_EC_OC_REG_DTO_CLKMODE__M 0x3 -#define B_EC_OC_REG_DTO_CLKMODE_INIT 0x2 - -#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__B 0 -#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__W 1 -#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__M 0x1 -#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_EVEN_ODD 0x0 -#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_ODD_EVEN 0x1 - -#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__B 1 -#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__W 1 -#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__M 0x2 -#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_SERIAL_MODE 0x0 -#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_PARALLEL_MODE 0x2 - -#define B_EC_OC_REG_DTO_PER__A 0x2150048 -#define B_EC_OC_REG_DTO_PER__W 8 -#define B_EC_OC_REG_DTO_PER__M 0xFF -#define B_EC_OC_REG_DTO_PER_INIT 0x6 - -#define B_EC_OC_REG_DTO_BUR__A 0x2150049 -#define B_EC_OC_REG_DTO_BUR__W 2 -#define B_EC_OC_REG_DTO_BUR__M 0x3 -#define B_EC_OC_REG_DTO_BUR_INIT 0x1 -#define B_EC_OC_REG_DTO_BUR_SELECT_1 0x0 -#define B_EC_OC_REG_DTO_BUR_SELECT_188 0x1 -#define B_EC_OC_REG_DTO_BUR_SELECT_204 0x2 -#define B_EC_OC_REG_DTO_BUR_SELECT_47 0x3 - -#define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A -#define B_EC_OC_REG_RCR_CLKMODE__W 3 -#define B_EC_OC_REG_RCR_CLKMODE__M 0x7 -#define B_EC_OC_REG_RCR_CLKMODE_INIT 0x0 - -#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__B 0 -#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__W 1 -#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__M 0x1 -#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_FRACIONAL 0x0 -#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_RATIONAL 0x1 - -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__B 1 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__W 1 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__M 0x2 +#define HI_SID 0x10 + +#define HI_COMM_EXEC__A 0x400000 +#define HI_COMM_EXEC__W 3 +#define HI_COMM_EXEC__M 0x7 +#define HI_COMM_EXEC_CTL__B 0 +#define HI_COMM_EXEC_CTL__W 3 +#define HI_COMM_EXEC_CTL__M 0x7 +#define HI_COMM_EXEC_CTL_STOP 0x0 +#define HI_COMM_EXEC_CTL_ACTIVE 0x1 +#define HI_COMM_EXEC_CTL_HOLD 0x2 +#define HI_COMM_EXEC_CTL_STEP 0x3 +#define HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define HI_COMM_STATE__A 0x400001 +#define HI_COMM_STATE__W 16 +#define HI_COMM_STATE__M 0xFFFF +#define HI_COMM_MB__A 0x400002 +#define HI_COMM_MB__W 16 +#define HI_COMM_MB__M 0xFFFF +#define HI_COMM_SERVICE0__A 0x400003 +#define HI_COMM_SERVICE0__W 16 +#define HI_COMM_SERVICE0__M 0xFFFF +#define HI_COMM_SERVICE1__A 0x400004 +#define HI_COMM_SERVICE1__W 16 +#define HI_COMM_SERVICE1__M 0xFFFF +#define HI_COMM_INT_STA__A 0x400007 +#define HI_COMM_INT_STA__W 16 +#define HI_COMM_INT_STA__M 0xFFFF +#define HI_COMM_INT_MSK__A 0x400008 +#define HI_COMM_INT_MSK__W 16 +#define HI_COMM_INT_MSK__M 0xFFFF + +#define HI_CT_REG_COMM_EXEC__A 0x410000 +#define HI_CT_REG_COMM_EXEC__W 3 +#define HI_CT_REG_COMM_EXEC__M 0x7 +#define HI_CT_REG_COMM_EXEC_CTL__B 0 +#define HI_CT_REG_COMM_EXEC_CTL__W 3 +#define HI_CT_REG_COMM_EXEC_CTL__M 0x7 +#define HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 + +#define HI_CT_REG_COMM_STATE__A 0x410001 +#define HI_CT_REG_COMM_STATE__W 10 +#define HI_CT_REG_COMM_STATE__M 0x3FF +#define HI_CT_REG_COMM_SERVICE0__A 0x410003 +#define HI_CT_REG_COMM_SERVICE0__W 16 +#define HI_CT_REG_COMM_SERVICE0__M 0xFFFF +#define HI_CT_REG_COMM_SERVICE1__A 0x410004 +#define HI_CT_REG_COMM_SERVICE1__W 16 +#define HI_CT_REG_COMM_SERVICE1__M 0xFFFF +#define HI_CT_REG_COMM_SERVICE1_HI__B 0 +#define HI_CT_REG_COMM_SERVICE1_HI__W 1 +#define HI_CT_REG_COMM_SERVICE1_HI__M 0x1 + +#define HI_CT_REG_COMM_INT_STA__A 0x410007 +#define HI_CT_REG_COMM_INT_STA__W 1 +#define HI_CT_REG_COMM_INT_STA__M 0x1 +#define HI_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define HI_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + +#define HI_CT_REG_COMM_INT_MSK__A 0x410008 +#define HI_CT_REG_COMM_INT_MSK__W 1 +#define HI_CT_REG_COMM_INT_MSK__M 0x1 +#define HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + +#define HI_CT_REG_CTL_STK__AX 0x410010 +#define HI_CT_REG_CTL_STK__XSZ 4 +#define HI_CT_REG_CTL_STK__W 10 +#define HI_CT_REG_CTL_STK__M 0x3FF + +#define HI_CT_REG_CTL_BPT_IDX__A 0x41001F +#define HI_CT_REG_CTL_BPT_IDX__W 1 +#define HI_CT_REG_CTL_BPT_IDX__M 0x1 + +#define HI_CT_REG_CTL_BPT__A 0x410020 +#define HI_CT_REG_CTL_BPT__W 10 +#define HI_CT_REG_CTL_BPT__M 0x3FF + +#define HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 +#define HI_RA_RAM_SLV0_FLG_SMM__W 1 +#define HI_RA_RAM_SLV0_FLG_SMM__M 0x1 +#define HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 +#define HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 + +#define HI_RA_RAM_SLV0_DEV_ID__A 0x420011 +#define HI_RA_RAM_SLV0_DEV_ID__W 7 +#define HI_RA_RAM_SLV0_DEV_ID__M 0x7F + +#define HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 +#define HI_RA_RAM_SLV0_FLG_CRC__W 1 +#define HI_RA_RAM_SLV0_FLG_CRC__M 0x1 +#define HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 +#define HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 + +#define HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 +#define HI_RA_RAM_SLV0_FLG_ACC__W 3 +#define HI_RA_RAM_SLV0_FLG_ACC__M 0x7 +#define HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 +#define HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 +#define HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 +#define HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 +#define HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 +#define HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 +#define HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 +#define HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 +#define HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 +#define HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 + +#define HI_RA_RAM_SLV0_STATE__A 0x420014 +#define HI_RA_RAM_SLV0_STATE__W 1 +#define HI_RA_RAM_SLV0_STATE__M 0x1 +#define HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 +#define HI_RA_RAM_SLV0_STATE_DATA 0x1 + +#define HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 +#define HI_RA_RAM_SLV0_BLK_BNK__W 12 +#define HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF +#define HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 +#define HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 +#define HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F +#define HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 +#define HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 +#define HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 + +#define HI_RA_RAM_SLV0_ADDR__A 0x420016 +#define HI_RA_RAM_SLV0_ADDR__W 16 +#define HI_RA_RAM_SLV0_ADDR__M 0xFFFF + +#define HI_RA_RAM_SLV0_CRC__A 0x420017 +#define HI_RA_RAM_SLV0_CRC__W 16 +#define HI_RA_RAM_SLV0_CRC__M 0xFFFF + +#define HI_RA_RAM_SLV0_READBACK__A 0x420018 +#define HI_RA_RAM_SLV0_READBACK__W 16 +#define HI_RA_RAM_SLV0_READBACK__M 0xFFFF + +#define HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 +#define HI_RA_RAM_SLV1_FLG_SMM__W 1 +#define HI_RA_RAM_SLV1_FLG_SMM__M 0x1 +#define HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 +#define HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 + +#define HI_RA_RAM_SLV1_DEV_ID__A 0x420021 +#define HI_RA_RAM_SLV1_DEV_ID__W 7 +#define HI_RA_RAM_SLV1_DEV_ID__M 0x7F + +#define HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 +#define HI_RA_RAM_SLV1_FLG_CRC__W 1 +#define HI_RA_RAM_SLV1_FLG_CRC__M 0x1 +#define HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 +#define HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 + +#define HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 +#define HI_RA_RAM_SLV1_FLG_ACC__W 3 +#define HI_RA_RAM_SLV1_FLG_ACC__M 0x7 +#define HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 +#define HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 +#define HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 +#define HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 +#define HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 +#define HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 +#define HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 +#define HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 +#define HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 +#define HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 + +#define HI_RA_RAM_SLV1_STATE__A 0x420024 +#define HI_RA_RAM_SLV1_STATE__W 1 +#define HI_RA_RAM_SLV1_STATE__M 0x1 +#define HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 +#define HI_RA_RAM_SLV1_STATE_DATA 0x1 + +#define HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 +#define HI_RA_RAM_SLV1_BLK_BNK__W 12 +#define HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF +#define HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 +#define HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 +#define HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F +#define HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 +#define HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 +#define HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 + +#define HI_RA_RAM_SLV1_ADDR__A 0x420026 +#define HI_RA_RAM_SLV1_ADDR__W 16 +#define HI_RA_RAM_SLV1_ADDR__M 0xFFFF + +#define HI_RA_RAM_SLV1_CRC__A 0x420027 +#define HI_RA_RAM_SLV1_CRC__W 16 +#define HI_RA_RAM_SLV1_CRC__M 0xFFFF + +#define HI_RA_RAM_SLV1_READBACK__A 0x420028 +#define HI_RA_RAM_SLV1_READBACK__W 16 +#define HI_RA_RAM_SLV1_READBACK__M 0xFFFF + +#define HI_RA_RAM_SRV_SEM__A 0x420030 +#define HI_RA_RAM_SRV_SEM__W 1 +#define HI_RA_RAM_SRV_SEM__M 0x1 +#define HI_RA_RAM_SRV_SEM_FREE 0x0 +#define HI_RA_RAM_SRV_SEM_CLAIMED 0x1 + +#define HI_RA_RAM_SRV_RES__A 0x420031 +#define HI_RA_RAM_SRV_RES__W 3 +#define HI_RA_RAM_SRV_RES__M 0x7 +#define HI_RA_RAM_SRV_RES_OK 0x0 +#define HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 +#define HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 +#define HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 +#define HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 + +#define HI_RA_RAM_SRV_CMD__A 0x420032 +#define HI_RA_RAM_SRV_CMD__W 3 +#define HI_RA_RAM_SRV_CMD__M 0x7 +#define HI_RA_RAM_SRV_CMD_NULL 0x0 +#define HI_RA_RAM_SRV_CMD_UIO 0x1 +#define HI_RA_RAM_SRV_CMD_RESET 0x2 +#define HI_RA_RAM_SRV_CMD_CONFIG 0x3 +#define HI_RA_RAM_SRV_CMD_COPY 0x4 +#define HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 +#define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 + +#define HI_RA_RAM_SRV_PAR__AX 0x420033 +#define HI_RA_RAM_SRV_PAR__XSZ 5 +#define HI_RA_RAM_SRV_PAR__W 16 +#define HI_RA_RAM_SRV_PAR__M 0xFFFF + +#define HI_RA_RAM_SRV_NOP_RES__A 0x420031 +#define HI_RA_RAM_SRV_NOP_RES__W 3 +#define HI_RA_RAM_SRV_NOP_RES__M 0x7 +#define HI_RA_RAM_SRV_NOP_RES_OK 0x0 +#define HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 + +#define HI_RA_RAM_SRV_UIO_RES__A 0x420031 +#define HI_RA_RAM_SRV_UIO_RES__W 3 +#define HI_RA_RAM_SRV_UIO_RES__M 0x7 +#define HI_RA_RAM_SRV_UIO_RES_LO 0x0 +#define HI_RA_RAM_SRV_UIO_RES_HI 0x1 + +#define HI_RA_RAM_SRV_UIO_KEY__A 0x420033 +#define HI_RA_RAM_SRV_UIO_KEY__W 16 +#define HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF +#define HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 + +#define HI_RA_RAM_SRV_UIO_SEL__A 0x420034 +#define HI_RA_RAM_SRV_UIO_SEL__W 2 +#define HI_RA_RAM_SRV_UIO_SEL__M 0x3 +#define HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 +#define HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 + +#define HI_RA_RAM_SRV_UIO_SET__A 0x420035 +#define HI_RA_RAM_SRV_UIO_SET__W 2 +#define HI_RA_RAM_SRV_UIO_SET__M 0x3 +#define HI_RA_RAM_SRV_UIO_SET_OUT__B 0 +#define HI_RA_RAM_SRV_UIO_SET_OUT__W 1 +#define HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 +#define HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 +#define HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 +#define HI_RA_RAM_SRV_UIO_SET_DIR__B 1 +#define HI_RA_RAM_SRV_UIO_SET_DIR__W 1 +#define HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 +#define HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 +#define HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 + +#define HI_RA_RAM_SRV_RST_RES__A 0x420031 +#define HI_RA_RAM_SRV_RST_RES__W 1 +#define HI_RA_RAM_SRV_RST_RES__M 0x1 +#define HI_RA_RAM_SRV_RST_RES_OK 0x0 +#define HI_RA_RAM_SRV_RST_RES_ERROR 0x1 + +#define HI_RA_RAM_SRV_RST_KEY__A 0x420033 +#define HI_RA_RAM_SRV_RST_KEY__W 16 +#define HI_RA_RAM_SRV_RST_KEY__M 0xFFFF +#define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 + +#define HI_RA_RAM_SRV_CFG_RES__A 0x420031 +#define HI_RA_RAM_SRV_CFG_RES__W 1 +#define HI_RA_RAM_SRV_CFG_RES__M 0x1 +#define HI_RA_RAM_SRV_CFG_RES_OK 0x0 +#define HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 + +#define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 +#define HI_RA_RAM_SRV_CFG_KEY__W 16 +#define HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF +#define HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 + +#define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 +#define HI_RA_RAM_SRV_CFG_DIV__W 5 +#define HI_RA_RAM_SRV_CFG_DIV__M 0x1F + +#define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 +#define HI_RA_RAM_SRV_CFG_BDL__W 6 +#define HI_RA_RAM_SRV_CFG_BDL__M 0x3F + +#define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 +#define HI_RA_RAM_SRV_CFG_WUP__W 8 +#define HI_RA_RAM_SRV_CFG_WUP__M 0xFF + +#define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 +#define HI_RA_RAM_SRV_CFG_ACT__W 4 +#define HI_RA_RAM_SRV_CFG_ACT__M 0xF +#define HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 +#define HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 +#define HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 +#define HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 +#define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 +#define HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 +#define HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 +#define HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 +#define HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 +#define HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 +#define HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 +#define HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 +#define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 +#define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 +#define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 +#define HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 +#define HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 +#define HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 +#define HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 +#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 + +#define HI_RA_RAM_SRV_CPY_RES__A 0x420031 +#define HI_RA_RAM_SRV_CPY_RES__W 1 +#define HI_RA_RAM_SRV_CPY_RES__M 0x1 +#define HI_RA_RAM_SRV_CPY_RES_OK 0x0 +#define HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 + +#define HI_RA_RAM_SRV_CPY_SBB__A 0x420033 +#define HI_RA_RAM_SRV_CPY_SBB__W 12 +#define HI_RA_RAM_SRV_CPY_SBB__M 0xFFF +#define HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 +#define HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 +#define HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F +#define HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 +#define HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 +#define HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 + +#define HI_RA_RAM_SRV_CPY_SAD__A 0x420034 +#define HI_RA_RAM_SRV_CPY_SAD__W 16 +#define HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF + +#define HI_RA_RAM_SRV_CPY_LEN__A 0x420035 +#define HI_RA_RAM_SRV_CPY_LEN__W 16 +#define HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF + +#define HI_RA_RAM_SRV_CPY_DBB__A 0x420033 +#define HI_RA_RAM_SRV_CPY_DBB__W 12 +#define HI_RA_RAM_SRV_CPY_DBB__M 0xFFF +#define HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 +#define HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 +#define HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F +#define HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 +#define HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 +#define HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 + +#define HI_RA_RAM_SRV_CPY_DAD__A 0x420034 +#define HI_RA_RAM_SRV_CPY_DAD__W 16 +#define HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF + +#define HI_RA_RAM_SRV_TRM_RES__A 0x420031 +#define HI_RA_RAM_SRV_TRM_RES__W 2 +#define HI_RA_RAM_SRV_TRM_RES__M 0x3 +#define HI_RA_RAM_SRV_TRM_RES_OK 0x0 +#define HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 +#define HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 + +#define HI_RA_RAM_SRV_TRM_MST__A 0x420033 +#define HI_RA_RAM_SRV_TRM_MST__W 12 +#define HI_RA_RAM_SRV_TRM_MST__M 0xFFF + +#define HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 +#define HI_RA_RAM_SRV_TRM_SEQ__W 7 +#define HI_RA_RAM_SRV_TRM_SEQ__M 0x7F + +#define HI_RA_RAM_SRV_TRM_TRM__A 0x420035 +#define HI_RA_RAM_SRV_TRM_TRM__W 15 +#define HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF +#define HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 +#define HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 +#define HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF + +#define HI_RA_RAM_SRV_TRM_DBB__A 0x420033 +#define HI_RA_RAM_SRV_TRM_DBB__W 12 +#define HI_RA_RAM_SRV_TRM_DBB__M 0xFFF +#define HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 +#define HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 +#define HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F +#define HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 +#define HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 +#define HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 + +#define HI_RA_RAM_SRV_TRM_DAD__A 0x420034 +#define HI_RA_RAM_SRV_TRM_DAD__W 16 +#define HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF + +#define HI_RA_RAM_USR_BEGIN__A 0x420040 +#define HI_RA_RAM_USR_BEGIN__W 16 +#define HI_RA_RAM_USR_BEGIN__M 0xFFFF + +#define HI_RA_RAM_USR_END__A 0x42007F +#define HI_RA_RAM_USR_END__W 16 +#define HI_RA_RAM_USR_END__M 0xFFFF + +#define HI_IF_RAM_TRP_BPT0__AX 0x430000 +#define HI_IF_RAM_TRP_BPT0__XSZ 2 +#define HI_IF_RAM_TRP_BPT0__W 12 +#define HI_IF_RAM_TRP_BPT0__M 0xFFF + +#define HI_IF_RAM_TRP_STKU__AX 0x430002 +#define HI_IF_RAM_TRP_STKU__XSZ 2 +#define HI_IF_RAM_TRP_STKU__W 12 +#define HI_IF_RAM_TRP_STKU__M 0xFFF + +#define HI_IF_RAM_USR_BEGIN__A 0x430200 +#define HI_IF_RAM_USR_BEGIN__W 12 +#define HI_IF_RAM_USR_BEGIN__M 0xFFF + +#define HI_IF_RAM_USR_END__A 0x4303FF +#define HI_IF_RAM_USR_END__W 12 +#define HI_IF_RAM_USR_END__M 0xFFF + +#define SC_SID 0x11 + +#define SC_COMM_EXEC__A 0x800000 +#define SC_COMM_EXEC__W 3 +#define SC_COMM_EXEC__M 0x7 +#define SC_COMM_EXEC_CTL__B 0 +#define SC_COMM_EXEC_CTL__W 3 +#define SC_COMM_EXEC_CTL__M 0x7 +#define SC_COMM_EXEC_CTL_STOP 0x0 +#define SC_COMM_EXEC_CTL_ACTIVE 0x1 +#define SC_COMM_EXEC_CTL_HOLD 0x2 +#define SC_COMM_EXEC_CTL_STEP 0x3 +#define SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define SC_COMM_STATE__A 0x800001 +#define SC_COMM_STATE__W 16 +#define SC_COMM_STATE__M 0xFFFF +#define SC_COMM_MB__A 0x800002 +#define SC_COMM_MB__W 16 +#define SC_COMM_MB__M 0xFFFF +#define SC_COMM_SERVICE0__A 0x800003 +#define SC_COMM_SERVICE0__W 16 +#define SC_COMM_SERVICE0__M 0xFFFF +#define SC_COMM_SERVICE1__A 0x800004 +#define SC_COMM_SERVICE1__W 16 +#define SC_COMM_SERVICE1__M 0xFFFF +#define SC_COMM_INT_STA__A 0x800007 +#define SC_COMM_INT_STA__W 16 +#define SC_COMM_INT_STA__M 0xFFFF +#define SC_COMM_INT_MSK__A 0x800008 +#define SC_COMM_INT_MSK__W 16 +#define SC_COMM_INT_MSK__M 0xFFFF + +#define SC_CT_REG_COMM_EXEC__A 0x810000 +#define SC_CT_REG_COMM_EXEC__W 3 +#define SC_CT_REG_COMM_EXEC__M 0x7 +#define SC_CT_REG_COMM_EXEC_CTL__B 0 +#define SC_CT_REG_COMM_EXEC_CTL__W 3 +#define SC_CT_REG_COMM_EXEC_CTL__M 0x7 +#define SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 + +#define SC_CT_REG_COMM_STATE__A 0x810001 +#define SC_CT_REG_COMM_STATE__W 10 +#define SC_CT_REG_COMM_STATE__M 0x3FF +#define SC_CT_REG_COMM_SERVICE0__A 0x810003 +#define SC_CT_REG_COMM_SERVICE0__W 16 +#define SC_CT_REG_COMM_SERVICE0__M 0xFFFF +#define SC_CT_REG_COMM_SERVICE1__A 0x810004 +#define SC_CT_REG_COMM_SERVICE1__W 16 +#define SC_CT_REG_COMM_SERVICE1__M 0xFFFF +#define SC_CT_REG_COMM_SERVICE1_SC__B 1 +#define SC_CT_REG_COMM_SERVICE1_SC__W 1 +#define SC_CT_REG_COMM_SERVICE1_SC__M 0x2 + +#define SC_CT_REG_COMM_INT_STA__A 0x810007 +#define SC_CT_REG_COMM_INT_STA__W 1 +#define SC_CT_REG_COMM_INT_STA__M 0x1 +#define SC_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define SC_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + +#define SC_CT_REG_COMM_INT_MSK__A 0x810008 +#define SC_CT_REG_COMM_INT_MSK__W 1 +#define SC_CT_REG_COMM_INT_MSK__M 0x1 +#define SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + +#define SC_CT_REG_CTL_STK__AX 0x810010 +#define SC_CT_REG_CTL_STK__XSZ 4 +#define SC_CT_REG_CTL_STK__W 10 +#define SC_CT_REG_CTL_STK__M 0x3FF + +#define SC_CT_REG_CTL_BPT_IDX__A 0x81001F +#define SC_CT_REG_CTL_BPT_IDX__W 1 +#define SC_CT_REG_CTL_BPT_IDX__M 0x1 + +#define SC_CT_REG_CTL_BPT__A 0x810020 +#define SC_CT_REG_CTL_BPT__W 10 +#define SC_CT_REG_CTL_BPT__M 0x3FF + +#define SC_RA_RAM_PARAM0__A 0x820040 +#define SC_RA_RAM_PARAM0__W 16 +#define SC_RA_RAM_PARAM0__M 0xFFFF +#define SC_RA_RAM_PARAM1__A 0x820041 +#define SC_RA_RAM_PARAM1__W 16 +#define SC_RA_RAM_PARAM1__M 0xFFFF +#define SC_RA_RAM_CMD_ADDR__A 0x820042 +#define SC_RA_RAM_CMD_ADDR__W 16 +#define SC_RA_RAM_CMD_ADDR__M 0xFFFF +#define SC_RA_RAM_CMD__A 0x820043 +#define SC_RA_RAM_CMD__W 16 +#define SC_RA_RAM_CMD__M 0xFFFF +#define SC_RA_RAM_CMD_NULL 0x0 +#define SC_RA_RAM_CMD_PROC_START 0x1 +#define SC_RA_RAM_CMD_PROC_TRIGGER 0x2 +#define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +#define SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 +#define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 +#define SC_RA_RAM_CMD_USER_IO 0x6 +#define SC_RA_RAM_CMD_SET_TIMER 0x7 +#define SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 +#define SC_RA_RAM_CMD_MAX 0x8 +#define SC_RA_RAM_CMDBLOCK__C 0x4 + +#define SC_RA_RAM_PROC_ACTIVATE__A 0x820044 +#define SC_RA_RAM_PROC_ACTIVATE__W 16 +#define SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF +#define SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF +#define SC_RA_RAM_PROC_TERMINATED__A 0x820045 +#define SC_RA_RAM_PROC_TERMINATED__W 16 +#define SC_RA_RAM_PROC_TERMINATED__M 0xFFFF +#define SC_RA_RAM_SW_EVENT__A 0x820046 +#define SC_RA_RAM_SW_EVENT__W 14 +#define SC_RA_RAM_SW_EVENT__M 0x3FFF +#define SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 +#define SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 +#define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 +#define SC_RA_RAM_SW_EVENT_RUN__B 1 +#define SC_RA_RAM_SW_EVENT_RUN__W 1 +#define SC_RA_RAM_SW_EVENT_RUN__M 0x2 +#define SC_RA_RAM_SW_EVENT_TERMINATE__B 2 +#define SC_RA_RAM_SW_EVENT_TERMINATE__W 1 +#define SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 +#define SC_RA_RAM_SW_EVENT_FT_START__B 3 +#define SC_RA_RAM_SW_EVENT_FT_START__W 1 +#define SC_RA_RAM_SW_EVENT_FT_START__M 0x8 +#define SC_RA_RAM_SW_EVENT_FI_START__B 4 +#define SC_RA_RAM_SW_EVENT_FI_START__W 1 +#define SC_RA_RAM_SW_EVENT_FI_START__M 0x10 +#define SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 +#define SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 +#define SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 +#define SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 +#define SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 +#define SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 +#define SC_RA_RAM_SW_EVENT_CE_IR__B 7 +#define SC_RA_RAM_SW_EVENT_CE_IR__W 1 +#define SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 +#define SC_RA_RAM_SW_EVENT_FE_FD__B 8 +#define SC_RA_RAM_SW_EVENT_FE_FD__W 1 +#define SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 +#define SC_RA_RAM_SW_EVENT_FE_CF__B 9 +#define SC_RA_RAM_SW_EVENT_FE_CF__W 1 +#define SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__B 10 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__W 1 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__M 0x400 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__B 11 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__W 1 +#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__M 0x800 + +#define SC_RA_RAM_LOCKTRACK__A 0x820047 +#define SC_RA_RAM_LOCKTRACK__W 16 +#define SC_RA_RAM_LOCKTRACK__M 0xFFFF +#define SC_RA_RAM_LOCKTRACK_NULL 0x0 +#define SC_RA_RAM_LOCKTRACK_MIN 0x1 +#define SC_RA_RAM_LOCKTRACK_RESET 0x1 +#define SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 +#define SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 +#define SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 +#define SC_RA_RAM_LOCKTRACK_P_DETECT_MIRROR 0x5 +#define SC_RA_RAM_LOCKTRACK_LC 0x6 +#define SC_RA_RAM_LOCKTRACK_P_ECHO 0x7 +#define SC_RA_RAM_LOCKTRACK_NE_INIT 0x8 +#define SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x9 +#define SC_RA_RAM_LOCKTRACK_TRACK 0xA +#define SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xB +#define SC_RA_RAM_LOCKTRACK_SR_SCANNING 0xC +#define SC_RA_RAM_LOCKTRACK_MAX 0xD + +#define SC_RA_RAM_OP_PARAM__A 0x820048 +#define SC_RA_RAM_OP_PARAM__W 13 +#define SC_RA_RAM_OP_PARAM__M 0x1FFF +#define SC_RA_RAM_OP_PARAM_MODE__B 0 +#define SC_RA_RAM_OP_PARAM_MODE__W 2 +#define SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +#define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +#define SC_RA_RAM_OP_PARAM_GUARD__B 2 +#define SC_RA_RAM_OP_PARAM_GUARD__W 2 +#define SC_RA_RAM_OP_PARAM_GUARD__M 0xC +#define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 +#define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 +#define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 +#define SC_RA_RAM_OP_PARAM_GUARD_4 0xC +#define SC_RA_RAM_OP_PARAM_CONST__B 4 +#define SC_RA_RAM_OP_PARAM_CONST__W 2 +#define SC_RA_RAM_OP_PARAM_CONST__M 0x30 +#define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 +#define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +#define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +#define SC_RA_RAM_OP_PARAM_HIER__B 6 +#define SC_RA_RAM_OP_PARAM_HIER__W 3 +#define SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 +#define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 +#define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 +#define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 +#define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 +#define SC_RA_RAM_OP_PARAM_RATE__B 9 +#define SC_RA_RAM_OP_PARAM_RATE__W 3 +#define SC_RA_RAM_OP_PARAM_RATE__M 0xE00 +#define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 +#define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 +#define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 +#define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 +#define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 +#define SC_RA_RAM_OP_PARAM_PRIO__B 12 +#define SC_RA_RAM_OP_PARAM_PRIO__W 1 +#define SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 +#define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 +#define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 + +#define SC_RA_RAM_OP_AUTO__A 0x820049 +#define SC_RA_RAM_OP_AUTO__W 6 +#define SC_RA_RAM_OP_AUTO__M 0x3F +#define SC_RA_RAM_OP_AUTO__PRE 0x1F +#define SC_RA_RAM_OP_AUTO_MODE__B 0 +#define SC_RA_RAM_OP_AUTO_MODE__W 1 +#define SC_RA_RAM_OP_AUTO_MODE__M 0x1 +#define SC_RA_RAM_OP_AUTO_GUARD__B 1 +#define SC_RA_RAM_OP_AUTO_GUARD__W 1 +#define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 +#define SC_RA_RAM_OP_AUTO_CONST__B 2 +#define SC_RA_RAM_OP_AUTO_CONST__W 1 +#define SC_RA_RAM_OP_AUTO_CONST__M 0x4 +#define SC_RA_RAM_OP_AUTO_HIER__B 3 +#define SC_RA_RAM_OP_AUTO_HIER__W 1 +#define SC_RA_RAM_OP_AUTO_HIER__M 0x8 +#define SC_RA_RAM_OP_AUTO_RATE__B 4 +#define SC_RA_RAM_OP_AUTO_RATE__W 1 +#define SC_RA_RAM_OP_AUTO_RATE__M 0x10 +#define SC_RA_RAM_OP_AUTO_PRIO__B 5 +#define SC_RA_RAM_OP_AUTO_PRIO__W 1 +#define SC_RA_RAM_OP_AUTO_PRIO__M 0x20 + +#define SC_RA_RAM_PILOT_STATUS__A 0x82004A +#define SC_RA_RAM_PILOT_STATUS__W 16 +#define SC_RA_RAM_PILOT_STATUS__M 0xFFFF +#define SC_RA_RAM_PILOT_STATUS_OK 0x0 +#define SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 +#define SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 + +#define SC_RA_RAM_LOCK__A 0x82004B +#define SC_RA_RAM_LOCK__W 4 +#define SC_RA_RAM_LOCK__M 0xF +#define SC_RA_RAM_LOCK_DEMOD__B 0 +#define SC_RA_RAM_LOCK_DEMOD__W 1 +#define SC_RA_RAM_LOCK_DEMOD__M 0x1 +#define SC_RA_RAM_LOCK_FEC__B 1 +#define SC_RA_RAM_LOCK_FEC__W 1 +#define SC_RA_RAM_LOCK_FEC__M 0x2 +#define SC_RA_RAM_LOCK_MPEG__B 2 +#define SC_RA_RAM_LOCK_MPEG__W 1 +#define SC_RA_RAM_LOCK_MPEG__M 0x4 +#define SC_RA_RAM_LOCK_NODVBT__B 3 +#define SC_RA_RAM_LOCK_NODVBT__W 1 +#define SC_RA_RAM_LOCK_NODVBT__M 0x8 + +#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C +#define SC_RA_RAM_BE_OPT_ENA__W 5 +#define SC_RA_RAM_BE_OPT_ENA__M 0x1F +#define SC_RA_RAM_BE_OPT_ENA__PRE 0x14 +#define SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 +#define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 +#define SC_RA_RAM_BE_OPT_ENA_COCHANNEL 0x2 +#define SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 +#define SC_RA_RAM_BE_OPT_ENA_MAX 0x5 + +#define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D +#define SC_RA_RAM_BE_OPT_DELAY__W 16 +#define SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF +#define SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 +#define SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E +#define SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 +#define SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF +#define SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 +#define SC_RA_RAM_ECHO_THRES__A 0x82004F +#define SC_RA_RAM_ECHO_THRES__W 16 +#define SC_RA_RAM_ECHO_THRES__M 0xFFFF +#define SC_RA_RAM_ECHO_THRES__PRE 0x2A +#define SC_RA_RAM_CONFIG__A 0x820050 +#define SC_RA_RAM_CONFIG__W 16 +#define SC_RA_RAM_CONFIG__M 0xFFFF +#define SC_RA_RAM_CONFIG__PRE 0x54 +#define SC_RA_RAM_CONFIG_ID__B 0 +#define SC_RA_RAM_CONFIG_ID__W 1 +#define SC_RA_RAM_CONFIG_ID__M 0x1 +#define SC_RA_RAM_CONFIG_ID_PRO 0x0 +#define SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 +#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 +#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 +#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 +#define SC_RA_RAM_CONFIG_FR_ENABLE__B 2 +#define SC_RA_RAM_CONFIG_FR_ENABLE__W 1 +#define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 +#define SC_RA_RAM_CONFIG_MIXMODE__B 3 +#define SC_RA_RAM_CONFIG_MIXMODE__W 1 +#define SC_RA_RAM_CONFIG_MIXMODE__M 0x8 +#define SC_RA_RAM_CONFIG_FREQSCAN__B 4 +#define SC_RA_RAM_CONFIG_FREQSCAN__W 1 +#define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 +#define SC_RA_RAM_CONFIG_SLAVE__B 5 +#define SC_RA_RAM_CONFIG_SLAVE__W 1 +#define SC_RA_RAM_CONFIG_SLAVE__M 0x20 +#define SC_RA_RAM_CONFIG_FAR_OFF__B 6 +#define SC_RA_RAM_CONFIG_FAR_OFF__W 1 +#define SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 +#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 +#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 +#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 +#define SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 +#define SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 +#define SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 +#define SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 +#define SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 +#define SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 + +#define SC_RA_RAM_PILOT_THRES_SPD__A 0x820051 +#define SC_RA_RAM_PILOT_THRES_SPD__W 16 +#define SC_RA_RAM_PILOT_THRES_SPD__M 0xFFFF +#define SC_RA_RAM_PILOT_THRES_SPD__PRE 0x4 +#define SC_RA_RAM_PILOT_THRES_CPD__A 0x820052 +#define SC_RA_RAM_PILOT_THRES_CPD__W 16 +#define SC_RA_RAM_PILOT_THRES_CPD__M 0xFFFF +#define SC_RA_RAM_PILOT_THRES_CPD__PRE 0x4 +#define SC_RA_RAM_PILOT_THRES_FREQSCAN__A 0x820053 +#define SC_RA_RAM_PILOT_THRES_FREQSCAN__W 16 +#define SC_RA_RAM_PILOT_THRES_FREQSCAN__M 0xFFFF +#define SC_RA_RAM_PILOT_THRES_FREQSCAN__PRE 0x406 + +#define SC_RA_RAM_CO_THRES_8K__A 0x820055 +#define SC_RA_RAM_CO_THRES_8K__W 16 +#define SC_RA_RAM_CO_THRES_8K__M 0xFFFF +#define SC_RA_RAM_CO_THRES_8K__PRE 0x10E +#define SC_RA_RAM_CO_THRES_2K__A 0x820056 +#define SC_RA_RAM_CO_THRES_2K__W 16 +#define SC_RA_RAM_CO_THRES_2K__M 0xFFFF +#define SC_RA_RAM_CO_THRES_2K__PRE 0x208 +#define SC_RA_RAM_CO_LEVEL__A 0x820057 +#define SC_RA_RAM_CO_LEVEL__W 16 +#define SC_RA_RAM_CO_LEVEL__M 0xFFFF +#define SC_RA_RAM_CO_DETECT__A 0x820058 +#define SC_RA_RAM_CO_DETECT__W 16 +#define SC_RA_RAM_CO_DETECT__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__A 0x820059 +#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__PRE 0xFFDB +#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__A 0x82005A +#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__PRE 0xFFEB +#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__A 0x82005B +#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__PRE 0xFFFB +#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__A 0x82005C +#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__PRE 0xFFDD +#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__A 0x82005D +#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__PRE 0xFFED +#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__A 0x82005E +#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__W 16 +#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__M 0xFFFF +#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__PRE 0xFFFD +#define SC_RA_RAM_MOTION_OFFSET__A 0x82005F +#define SC_RA_RAM_MOTION_OFFSET__W 16 +#define SC_RA_RAM_MOTION_OFFSET__M 0xFFFF +#define SC_RA_RAM_MOTION_OFFSET__PRE 0x2 +#define SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 +#define SC_RA_RAM_STATE_PROC_STOP__XSZ 12 +#define SC_RA_RAM_STATE_PROC_STOP__W 16 +#define SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF +#define SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE +#define SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 +#define SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_10__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_STOP_11__PRE 0xFFFE +#define SC_RA_RAM_STATE_PROC_STOP_12__PRE 0xFFFE +#define SC_RA_RAM_STATE_PROC_START__AX 0x820070 +#define SC_RA_RAM_STATE_PROC_START__XSZ 12 +#define SC_RA_RAM_STATE_PROC_START__W 16 +#define SC_RA_RAM_STATE_PROC_START__M 0xFFFF +#define SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 +#define SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 +#define SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 +#define SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 +#define SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 +#define SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_START_7__PRE 0x10 +#define SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_START_9__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_START_10__PRE 0x30 +#define SC_RA_RAM_STATE_PROC_START_11__PRE 0x0 +#define SC_RA_RAM_STATE_PROC_START_12__PRE 0x0 +#define SC_RA_RAM_IF_SAVE__AX 0x82008E +#define SC_RA_RAM_IF_SAVE__XSZ 2 +#define SC_RA_RAM_IF_SAVE__W 16 +#define SC_RA_RAM_IF_SAVE__M 0xFFFF +#define SC_RA_RAM_FR_THRES__A 0x82007D +#define SC_RA_RAM_FR_THRES__W 16 +#define SC_RA_RAM_FR_THRES__M 0xFFFF +#define SC_RA_RAM_FR_THRES__PRE 0x1A2C +#define SC_RA_RAM_STATUS__A 0x82007E +#define SC_RA_RAM_STATUS__W 16 +#define SC_RA_RAM_STATUS__M 0xFFFF +#define SC_RA_RAM_NF_BORDER_INIT__A 0x82007F +#define SC_RA_RAM_NF_BORDER_INIT__W 16 +#define SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF +#define SC_RA_RAM_NF_BORDER_INIT__PRE 0x500 +#define SC_RA_RAM_TIMER__A 0x820080 +#define SC_RA_RAM_TIMER__W 16 +#define SC_RA_RAM_TIMER__M 0xFFFF +#define SC_RA_RAM_FI_OFFSET__A 0x820081 +#define SC_RA_RAM_FI_OFFSET__W 16 +#define SC_RA_RAM_FI_OFFSET__M 0xFFFF +#define SC_RA_RAM_FI_OFFSET__PRE 0x382 +#define SC_RA_RAM_ECHO_GUARD__A 0x820082 +#define SC_RA_RAM_ECHO_GUARD__W 16 +#define SC_RA_RAM_ECHO_GUARD__M 0xFFFF +#define SC_RA_RAM_ECHO_GUARD__PRE 0x18 + +#define SC_RA_RAM_IR_FREQ__A 0x8200D0 +#define SC_RA_RAM_IR_FREQ__W 16 +#define SC_RA_RAM_IR_FREQ__M 0xFFFF +#define SC_RA_RAM_IR_FREQ__PRE 0x0 + +#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 +#define SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 +#define SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 +#define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 +#define SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 +#define SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 +#define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 +#define SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 +#define SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 + +#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 +#define SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 +#define SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 +#define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 +#define SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 +#define SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 +#define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 +#define SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 +#define SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF +#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 + +#define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 +#define SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 +#define SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF +#define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 +#define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 +#define SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 +#define SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF +#define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 +#define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 +#define SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 +#define SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF +#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 + +#define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA +#define SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 +#define SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF +#define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB +#define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB +#define SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 +#define SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF +#define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 +#define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC +#define SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 +#define SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF +#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 + +#define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD +#define SC_RA_RAM_ECHO_SHIFT_LIM__W 16 +#define SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF +#define SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0xFFFF +#define SC_RA_RAM_ECHO_AGE__A 0x8200DE +#define SC_RA_RAM_ECHO_AGE__W 16 +#define SC_RA_RAM_ECHO_AGE__M 0xFFFF +#define SC_RA_RAM_ECHO_AGE__PRE 0xFFFF +#define SC_RA_RAM_ECHO_FILTER__A 0x8200DF +#define SC_RA_RAM_ECHO_FILTER__W 16 +#define SC_RA_RAM_ECHO_FILTER__M 0xFFFF +#define SC_RA_RAM_ECHO_FILTER__PRE 0x2 + +#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 +#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 +#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF +#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 +#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 +#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 +#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF +#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 +#define SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 +#define SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 +#define SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF +#define SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 + +#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 +#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 +#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF +#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE +#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 +#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 +#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF +#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 +#define SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 +#define SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 +#define SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF +#define SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 + +#define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 +#define SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 +#define SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF +#define SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x10 +#define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 +#define SC_RA_RAM_SAMPLE_RATE_STEP__W 16 +#define SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF +#define SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x113 + +#define SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA +#define SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 +#define SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF +#define SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 +#define SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB +#define SC_RA_RAM_TPS_TIMEOUT__W 16 +#define SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF +#define SC_RA_RAM_BAND__A 0x8200EC +#define SC_RA_RAM_BAND__W 16 +#define SC_RA_RAM_BAND__M 0xFFFF +#define SC_RA_RAM_BAND__PRE 0x0 +#define SC_RA_RAM_BAND_INTERVAL__B 0 +#define SC_RA_RAM_BAND_INTERVAL__W 4 +#define SC_RA_RAM_BAND_INTERVAL__M 0xF +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 +#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 +#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 + +#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED +#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 +#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF +#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 +#define SC_RA_RAM_REG__AX 0x8200F0 +#define SC_RA_RAM_REG__XSZ 2 +#define SC_RA_RAM_REG__W 16 +#define SC_RA_RAM_REG__M 0xFFFF +#define SC_RA_RAM_BREAK__A 0x8200F2 +#define SC_RA_RAM_BREAK__W 16 +#define SC_RA_RAM_BREAK__M 0xFFFF +#define SC_RA_RAM_BOOTCOUNT__A 0x8200F3 +#define SC_RA_RAM_BOOTCOUNT__W 16 +#define SC_RA_RAM_BOOTCOUNT__M 0xFFFF + +#define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 +#define SC_RA_RAM_LC_ABS_2K__W 16 +#define SC_RA_RAM_LC_ABS_2K__M 0xFFFF +#define SC_RA_RAM_LC_ABS_2K__PRE 0x1F +#define SC_RA_RAM_LC_ABS_8K__A 0x8200F5 +#define SC_RA_RAM_LC_ABS_8K__W 16 +#define SC_RA_RAM_LC_ABS_8K__M 0xFFFF +#define SC_RA_RAM_LC_ABS_8K__PRE 0x1F + +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__A 0x8200F6 +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__W 16 +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__M 0xFFFF +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__PRE 0x1 +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__A 0x8200F7 +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__W 16 +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__M 0xFFFF +#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__PRE 0x0 + +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__A 0x8200F8 +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__W 16 +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__M 0xFFFF +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__PRE 0x3 +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__A 0x8200F9 +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__W 16 +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__M 0xFFFF +#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__PRE 0x2 +#define SC_RA_RAM_RELOCK__A 0x8200FE +#define SC_RA_RAM_RELOCK__W 16 +#define SC_RA_RAM_RELOCK__M 0xFFFF +#define SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF +#define SC_RA_RAM_STACKUNDERFLOW__W 16 +#define SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF + +#define SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 +#define SC_RA_RAM_NF_MAXECHOTOKEN__W 16 +#define SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF +#define SC_RA_RAM_NF_PREPOST__A 0x820149 +#define SC_RA_RAM_NF_PREPOST__W 16 +#define SC_RA_RAM_NF_PREPOST__M 0xFFFF +#define SC_RA_RAM_NF_PREBORDER__A 0x82014A +#define SC_RA_RAM_NF_PREBORDER__W 16 +#define SC_RA_RAM_NF_PREBORDER__M 0xFFFF +#define SC_RA_RAM_NF_START__A 0x82014B +#define SC_RA_RAM_NF_START__W 16 +#define SC_RA_RAM_NF_START__M 0xFFFF +#define SC_RA_RAM_NF_MINISI__AX 0x82014C +#define SC_RA_RAM_NF_MINISI__XSZ 2 +#define SC_RA_RAM_NF_MINISI__W 16 +#define SC_RA_RAM_NF_MINISI__M 0xFFFF +#define SC_RA_RAM_NF_MAXECHO__A 0x82014E +#define SC_RA_RAM_NF_MAXECHO__W 16 +#define SC_RA_RAM_NF_MAXECHO__M 0xFFFF +#define SC_RA_RAM_NF_NRECHOES__A 0x82014F +#define SC_RA_RAM_NF_NRECHOES__W 16 +#define SC_RA_RAM_NF_NRECHOES__M 0xFFFF +#define SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 +#define SC_RA_RAM_NF_ECHOTABLE__XSZ 16 +#define SC_RA_RAM_NF_ECHOTABLE__W 16 +#define SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF + +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6 +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 + +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 + +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 + +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 + +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 + +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 + +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 + +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF +#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5 +#define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE +#define SC_RA_RAM_DRIVER_VERSION__XSZ 2 +#define SC_RA_RAM_DRIVER_VERSION__W 16 +#define SC_RA_RAM_DRIVER_VERSION__M 0xFFFF +#define SC_RA_RAM_EVENT0_MIN 0x7 +#define SC_RA_RAM_EVENT0_FE_CU 0x7 +#define SC_RA_RAM_EVENT0_CE 0xA +#define SC_RA_RAM_EVENT0_EQ 0xE +#define SC_RA_RAM_EVENT0_MAX 0xF +#define SC_RA_RAM_EVENT1_MIN 0x8 +#define SC_RA_RAM_EVENT1_EC_OD 0x8 +#define SC_RA_RAM_EVENT1_LC 0xC +#define SC_RA_RAM_EVENT1_MAX 0xD +#define SC_RA_RAM_PROC_LOCKTRACK 0x0 +#define SC_RA_RAM_PROC_MODE_GUARD 0x1 +#define SC_RA_RAM_PROC_PILOTS 0x2 +#define SC_RA_RAM_PROC_FESTART_ADJUST 0x3 +#define SC_RA_RAM_PROC_ECHO 0x4 +#define SC_RA_RAM_PROC_BE_OPT 0x5 +#define SC_RA_RAM_PROC_EQ 0x7 +#define SC_RA_RAM_PROC_MAX 0x8 + +#define SC_IF_RAM_TRP_RST__AX 0x830000 +#define SC_IF_RAM_TRP_RST__XSZ 2 +#define SC_IF_RAM_TRP_RST__W 12 +#define SC_IF_RAM_TRP_RST__M 0xFFF + +#define SC_IF_RAM_TRP_BPT0__AX 0x830002 +#define SC_IF_RAM_TRP_BPT0__XSZ 2 +#define SC_IF_RAM_TRP_BPT0__W 12 +#define SC_IF_RAM_TRP_BPT0__M 0xFFF + +#define SC_IF_RAM_TRP_STKU__AX 0x830004 +#define SC_IF_RAM_TRP_STKU__XSZ 2 +#define SC_IF_RAM_TRP_STKU__W 12 +#define SC_IF_RAM_TRP_STKU__M 0xFFF + +#define SC_IF_RAM_VERSION_MA_MI__A 0x830FFE +#define SC_IF_RAM_VERSION_MA_MI__W 12 +#define SC_IF_RAM_VERSION_MA_MI__M 0xFFF + +#define SC_IF_RAM_VERSION_PATCH__A 0x830FFF +#define SC_IF_RAM_VERSION_PATCH__W 12 +#define SC_IF_RAM_VERSION_PATCH__M 0xFFF + +#define FE_COMM_EXEC__A 0xC00000 +#define FE_COMM_EXEC__W 3 +#define FE_COMM_EXEC__M 0x7 +#define FE_COMM_EXEC_CTL__B 0 +#define FE_COMM_EXEC_CTL__W 3 +#define FE_COMM_EXEC_CTL__M 0x7 +#define FE_COMM_EXEC_CTL_STOP 0x0 +#define FE_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_COMM_EXEC_CTL_HOLD 0x2 +#define FE_COMM_EXEC_CTL_STEP 0x3 +#define FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define FE_COMM_STATE__A 0xC00001 +#define FE_COMM_STATE__W 16 +#define FE_COMM_STATE__M 0xFFFF +#define FE_COMM_MB__A 0xC00002 +#define FE_COMM_MB__W 16 +#define FE_COMM_MB__M 0xFFFF +#define FE_COMM_SERVICE0__A 0xC00003 +#define FE_COMM_SERVICE0__W 16 +#define FE_COMM_SERVICE0__M 0xFFFF +#define FE_COMM_SERVICE1__A 0xC00004 +#define FE_COMM_SERVICE1__W 16 +#define FE_COMM_SERVICE1__M 0xFFFF +#define FE_COMM_INT_STA__A 0xC00007 +#define FE_COMM_INT_STA__W 16 +#define FE_COMM_INT_STA__M 0xFFFF +#define FE_COMM_INT_MSK__A 0xC00008 +#define FE_COMM_INT_MSK__W 16 +#define FE_COMM_INT_MSK__M 0xFFFF + +#define FE_AD_SID 0x1 + +#define FE_AD_REG_COMM_EXEC__A 0xC10000 +#define FE_AD_REG_COMM_EXEC__W 3 +#define FE_AD_REG_COMM_EXEC__M 0x7 +#define FE_AD_REG_COMM_EXEC_CTL__B 0 +#define FE_AD_REG_COMM_EXEC_CTL__W 3 +#define FE_AD_REG_COMM_EXEC_CTL__M 0x7 +#define FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 + +#define FE_AD_REG_COMM_MB__A 0xC10002 +#define FE_AD_REG_COMM_MB__W 2 +#define FE_AD_REG_COMM_MB__M 0x3 +#define FE_AD_REG_COMM_MB_CTR__B 0 +#define FE_AD_REG_COMM_MB_CTR__W 1 +#define FE_AD_REG_COMM_MB_CTR__M 0x1 +#define FE_AD_REG_COMM_MB_CTR_OFF 0x0 +#define FE_AD_REG_COMM_MB_CTR_ON 0x1 +#define FE_AD_REG_COMM_MB_OBS__B 1 +#define FE_AD_REG_COMM_MB_OBS__W 1 +#define FE_AD_REG_COMM_MB_OBS__M 0x2 +#define FE_AD_REG_COMM_MB_OBS_OFF 0x0 +#define FE_AD_REG_COMM_MB_OBS_ON 0x2 + +#define FE_AD_REG_COMM_SERVICE0__A 0xC10003 +#define FE_AD_REG_COMM_SERVICE0__W 10 +#define FE_AD_REG_COMM_SERVICE0__M 0x3FF +#define FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 +#define FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 +#define FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 + +#define FE_AD_REG_COMM_SERVICE1__A 0xC10004 +#define FE_AD_REG_COMM_SERVICE1__W 11 +#define FE_AD_REG_COMM_SERVICE1__M 0x7FF + +#define FE_AD_REG_COMM_INT_STA__A 0xC10007 +#define FE_AD_REG_COMM_INT_STA__W 2 +#define FE_AD_REG_COMM_INT_STA__M 0x3 +#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 +#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 +#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 + +#define FE_AD_REG_COMM_INT_MSK__A 0xC10008 +#define FE_AD_REG_COMM_INT_MSK__W 2 +#define FE_AD_REG_COMM_INT_MSK__M 0x3 +#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 +#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 +#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 + +#define FE_AD_REG_CUR_SEL__A 0xC10010 +#define FE_AD_REG_CUR_SEL__W 2 +#define FE_AD_REG_CUR_SEL__M 0x3 +#define FE_AD_REG_CUR_SEL_INIT 0x2 + +#define FE_AD_REG_OVERFLOW__A 0xC10011 +#define FE_AD_REG_OVERFLOW__W 1 +#define FE_AD_REG_OVERFLOW__M 0x1 +#define FE_AD_REG_OVERFLOW_INIT 0x0 + +#define FE_AD_REG_FDB_IN__A 0xC10012 +#define FE_AD_REG_FDB_IN__W 1 +#define FE_AD_REG_FDB_IN__M 0x1 +#define FE_AD_REG_FDB_IN_INIT 0x0 + +#define FE_AD_REG_PD__A 0xC10013 +#define FE_AD_REG_PD__W 1 +#define FE_AD_REG_PD__M 0x1 +#define FE_AD_REG_PD_INIT 0x1 + +#define FE_AD_REG_INVEXT__A 0xC10014 +#define FE_AD_REG_INVEXT__W 1 +#define FE_AD_REG_INVEXT__M 0x1 +#define FE_AD_REG_INVEXT_INIT 0x0 + +#define FE_AD_REG_CLKNEG__A 0xC10015 +#define FE_AD_REG_CLKNEG__W 1 +#define FE_AD_REG_CLKNEG__M 0x1 +#define FE_AD_REG_CLKNEG_INIT 0x0 + +#define FE_AD_REG_MON_IN_MUX__A 0xC10016 +#define FE_AD_REG_MON_IN_MUX__W 2 +#define FE_AD_REG_MON_IN_MUX__M 0x3 +#define FE_AD_REG_MON_IN_MUX_INIT 0x0 + +#define FE_AD_REG_MON_IN5__A 0xC10017 +#define FE_AD_REG_MON_IN5__W 10 +#define FE_AD_REG_MON_IN5__M 0x3FF +#define FE_AD_REG_MON_IN5_INIT 0x0 + +#define FE_AD_REG_MON_IN4__A 0xC10018 +#define FE_AD_REG_MON_IN4__W 10 +#define FE_AD_REG_MON_IN4__M 0x3FF +#define FE_AD_REG_MON_IN4_INIT 0x0 + +#define FE_AD_REG_MON_IN3__A 0xC10019 +#define FE_AD_REG_MON_IN3__W 10 +#define FE_AD_REG_MON_IN3__M 0x3FF +#define FE_AD_REG_MON_IN3_INIT 0x0 + +#define FE_AD_REG_MON_IN2__A 0xC1001A +#define FE_AD_REG_MON_IN2__W 10 +#define FE_AD_REG_MON_IN2__M 0x3FF +#define FE_AD_REG_MON_IN2_INIT 0x0 + +#define FE_AD_REG_MON_IN1__A 0xC1001B +#define FE_AD_REG_MON_IN1__W 10 +#define FE_AD_REG_MON_IN1__M 0x3FF +#define FE_AD_REG_MON_IN1_INIT 0x0 + +#define FE_AD_REG_MON_IN0__A 0xC1001C +#define FE_AD_REG_MON_IN0__W 10 +#define FE_AD_REG_MON_IN0__M 0x3FF +#define FE_AD_REG_MON_IN0_INIT 0x0 + +#define FE_AD_REG_MON_IN_VAL__A 0xC1001D +#define FE_AD_REG_MON_IN_VAL__W 1 +#define FE_AD_REG_MON_IN_VAL__M 0x1 +#define FE_AD_REG_MON_IN_VAL_INIT 0x0 + +#define FE_AD_REG_CTR_CLK_O__A 0xC1001E +#define FE_AD_REG_CTR_CLK_O__W 1 +#define FE_AD_REG_CTR_CLK_O__M 0x1 +#define FE_AD_REG_CTR_CLK_O_INIT 0x0 + +#define FE_AD_REG_CTR_CLK_E_O__A 0xC1001F +#define FE_AD_REG_CTR_CLK_E_O__W 1 +#define FE_AD_REG_CTR_CLK_E_O__M 0x1 +#define FE_AD_REG_CTR_CLK_E_O_INIT 0x1 + +#define FE_AD_REG_CTR_VAL_O__A 0xC10020 +#define FE_AD_REG_CTR_VAL_O__W 1 +#define FE_AD_REG_CTR_VAL_O__M 0x1 +#define FE_AD_REG_CTR_VAL_O_INIT 0x0 + +#define FE_AD_REG_CTR_VAL_E_O__A 0xC10021 +#define FE_AD_REG_CTR_VAL_E_O__W 1 +#define FE_AD_REG_CTR_VAL_E_O__M 0x1 +#define FE_AD_REG_CTR_VAL_E_O_INIT 0x1 + +#define FE_AD_REG_CTR_DATA_O__A 0xC10022 +#define FE_AD_REG_CTR_DATA_O__W 10 +#define FE_AD_REG_CTR_DATA_O__M 0x3FF +#define FE_AD_REG_CTR_DATA_O_INIT 0x0 + +#define FE_AD_REG_CTR_DATA_E_O__A 0xC10023 +#define FE_AD_REG_CTR_DATA_E_O__W 10 +#define FE_AD_REG_CTR_DATA_E_O__M 0x3FF +#define FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF + +#define FE_AG_SID 0x2 + +#define FE_AG_REG_COMM_EXEC__A 0xC20000 +#define FE_AG_REG_COMM_EXEC__W 3 +#define FE_AG_REG_COMM_EXEC__M 0x7 +#define FE_AG_REG_COMM_EXEC_CTL__B 0 +#define FE_AG_REG_COMM_EXEC_CTL__W 3 +#define FE_AG_REG_COMM_EXEC_CTL__M 0x7 +#define FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 + +#define FE_AG_REG_COMM_STATE__A 0xC20001 +#define FE_AG_REG_COMM_STATE__W 4 +#define FE_AG_REG_COMM_STATE__M 0xF + +#define FE_AG_REG_COMM_MB__A 0xC20002 +#define FE_AG_REG_COMM_MB__W 2 +#define FE_AG_REG_COMM_MB__M 0x3 +#define FE_AG_REG_COMM_MB_CTR__B 0 +#define FE_AG_REG_COMM_MB_CTR__W 1 +#define FE_AG_REG_COMM_MB_CTR__M 0x1 +#define FE_AG_REG_COMM_MB_CTR_OFF 0x0 +#define FE_AG_REG_COMM_MB_CTR_ON 0x1 +#define FE_AG_REG_COMM_MB_OBS__B 1 +#define FE_AG_REG_COMM_MB_OBS__W 1 +#define FE_AG_REG_COMM_MB_OBS__M 0x2 +#define FE_AG_REG_COMM_MB_OBS_OFF 0x0 +#define FE_AG_REG_COMM_MB_OBS_ON 0x2 + +#define FE_AG_REG_COMM_SERVICE0__A 0xC20003 +#define FE_AG_REG_COMM_SERVICE0__W 10 +#define FE_AG_REG_COMM_SERVICE0__M 0x3FF + +#define FE_AG_REG_COMM_SERVICE1__A 0xC20004 +#define FE_AG_REG_COMM_SERVICE1__W 11 +#define FE_AG_REG_COMM_SERVICE1__M 0x7FF + +#define FE_AG_REG_COMM_INT_STA__A 0xC20007 +#define FE_AG_REG_COMM_INT_STA__W 8 +#define FE_AG_REG_COMM_INT_STA__M 0xFF +#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 +#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 +#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 +#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 +#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 +#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 +#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 +#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 +#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 +#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 +#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 +#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 +#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__B 6 +#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__M 0x40 +#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 +#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 +#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 + +#define FE_AG_REG_COMM_INT_MSK__A 0xC20008 +#define FE_AG_REG_COMM_INT_MSK__W 8 +#define FE_AG_REG_COMM_INT_MSK__M 0xFF +#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 +#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 +#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 +#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 +#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 +#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 +#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 +#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 +#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 +#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 +#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 +#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 +#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__B 6 +#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__M 0x40 +#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 +#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 +#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 + +#define FE_AG_REG_AG_MODE_LOP__A 0xC20010 +#define FE_AG_REG_AG_MODE_LOP__W 16 +#define FE_AG_REG_AG_MODE_LOP__M 0xFFFF +#define FE_AG_REG_AG_MODE_LOP_INIT 0x0 + +#define FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 +#define FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 +#define FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 + +#define FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 +#define FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 + +#define FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 +#define FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 +#define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 + +#define FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 +#define FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 +#define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 + +#define FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 +#define FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 +#define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 + +#define FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 +#define FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 +#define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 + +#define FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 +#define FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 +#define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 + +#define FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 +#define FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 +#define FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 + +#define FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 +#define FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 +#define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 + +#define FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 +#define FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 +#define FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 + +#define FE_AG_REG_AG_MODE_LOP_MODE_A__B 10 +#define FE_AG_REG_AG_MODE_LOP_MODE_A__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_A__M 0x400 +#define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_B 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_CB 0x400 + +#define FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 +#define FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 +#define FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 + +#define FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 +#define FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 +#define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 + +#define FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 +#define FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 +#define FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 + +#define FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 +#define FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 +#define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 + +#define FE_AG_REG_AG_MODE_LOP_MODE_F__B 15 +#define FE_AG_REG_AG_MODE_LOP_MODE_F__W 1 +#define FE_AG_REG_AG_MODE_LOP_MODE_F__M 0x8000 +#define FE_AG_REG_AG_MODE_LOP_MODE_F_DISABLE 0x0 +#define FE_AG_REG_AG_MODE_LOP_MODE_F_ENABLE 0x8000 + +#define FE_AG_REG_AG_MODE_HIP__A 0xC20011 +#define FE_AG_REG_AG_MODE_HIP__W 2 +#define FE_AG_REG_AG_MODE_HIP__M 0x3 +#define FE_AG_REG_AG_MODE_HIP_INIT 0x0 + +#define FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 +#define FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 +#define FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 +#define FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 +#define FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 + +#define FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 +#define FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 +#define FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 +#define FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 +#define FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 + +#define FE_AG_REG_AG_PGA_MODE__A 0xC20012 +#define FE_AG_REG_AG_PGA_MODE__W 3 +#define FE_AG_REG_AG_PGA_MODE__M 0x7 +#define FE_AG_REG_AG_PGA_MODE_INIT 0x0 +#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 +#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 +#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 + +#define FE_AG_REG_AG_AGC_SIO__A 0xC20013 +#define FE_AG_REG_AG_AGC_SIO__W 2 +#define FE_AG_REG_AG_AGC_SIO__M 0x3 +#define FE_AG_REG_AG_AGC_SIO_INIT 0x3 + +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 + +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 +#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 + +#define FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 +#define FE_AG_REG_AG_AGC_USR_DAT__W 2 +#define FE_AG_REG_AG_AGC_USR_DAT__M 0x3 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 +#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 + +#define FE_AG_REG_AG_PWD__A 0xC20015 +#define FE_AG_REG_AG_PWD__W 5 +#define FE_AG_REG_AG_PWD__M 0x1F +#define FE_AG_REG_AG_PWD_INIT 0x1F + +#define FE_AG_REG_AG_PWD_PWD_PD1__B 0 +#define FE_AG_REG_AG_PWD_PWD_PD1__W 1 +#define FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 +#define FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 +#define FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 + +#define FE_AG_REG_AG_PWD_PWD_PD2__B 1 +#define FE_AG_REG_AG_PWD_PWD_PD2__W 1 +#define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 +#define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 +#define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 + +#define FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 +#define FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 +#define FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 +#define FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 +#define FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 + +#define FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 +#define FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 +#define FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 +#define FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 +#define FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 + +#define FE_AG_REG_AG_PWD_PWD_AAF__B 4 +#define FE_AG_REG_AG_PWD_PWD_AAF__W 1 +#define FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 +#define FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 +#define FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 + +#define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 +#define FE_AG_REG_DCE_AUR_CNT__W 5 +#define FE_AG_REG_DCE_AUR_CNT__M 0x1F +#define FE_AG_REG_DCE_AUR_CNT_INIT 0x0 + +#define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 +#define FE_AG_REG_DCE_RUR_CNT__W 5 +#define FE_AG_REG_DCE_RUR_CNT__M 0x1F +#define FE_AG_REG_DCE_RUR_CNT_INIT 0x0 + +#define FE_AG_REG_DCE_AVE_DAT__A 0xC20018 +#define FE_AG_REG_DCE_AVE_DAT__W 10 +#define FE_AG_REG_DCE_AVE_DAT__M 0x3FF + +#define FE_AG_REG_DEC_AVE_WRI__A 0xC20019 +#define FE_AG_REG_DEC_AVE_WRI__W 10 +#define FE_AG_REG_DEC_AVE_WRI__M 0x3FF +#define FE_AG_REG_DEC_AVE_WRI_INIT 0x0 + +#define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A +#define FE_AG_REG_ACE_AUR_CNT__W 5 +#define FE_AG_REG_ACE_AUR_CNT__M 0x1F +#define FE_AG_REG_ACE_AUR_CNT_INIT 0x0 + +#define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B +#define FE_AG_REG_ACE_RUR_CNT__W 5 +#define FE_AG_REG_ACE_RUR_CNT__M 0x1F +#define FE_AG_REG_ACE_RUR_CNT_INIT 0x0 + +#define FE_AG_REG_ACE_AVE_DAT__A 0xC2001C +#define FE_AG_REG_ACE_AVE_DAT__W 10 +#define FE_AG_REG_ACE_AVE_DAT__M 0x3FF + +#define FE_AG_REG_AEC_AVE_INC__A 0xC2001D +#define FE_AG_REG_AEC_AVE_INC__W 10 +#define FE_AG_REG_AEC_AVE_INC__M 0x3FF +#define FE_AG_REG_AEC_AVE_INC_INIT 0x0 + +#define FE_AG_REG_AEC_AVE_DAT__A 0xC2001E +#define FE_AG_REG_AEC_AVE_DAT__W 10 +#define FE_AG_REG_AEC_AVE_DAT__M 0x3FF + +#define FE_AG_REG_AEC_CLP_LVL__A 0xC2001F +#define FE_AG_REG_AEC_CLP_LVL__W 16 +#define FE_AG_REG_AEC_CLP_LVL__M 0xFFFF +#define FE_AG_REG_AEC_CLP_LVL_INIT 0x0 + +#define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 +#define FE_AG_REG_CDR_RUR_CNT__W 5 +#define FE_AG_REG_CDR_RUR_CNT__M 0x1F +#define FE_AG_REG_CDR_RUR_CNT_INIT 0x0 + +#define FE_AG_REG_CDR_CLP_DAT__A 0xC20021 +#define FE_AG_REG_CDR_CLP_DAT__W 16 +#define FE_AG_REG_CDR_CLP_DAT__M 0xFFFF + +#define FE_AG_REG_CDR_CLP_POS__A 0xC20022 +#define FE_AG_REG_CDR_CLP_POS__W 10 +#define FE_AG_REG_CDR_CLP_POS__M 0x3FF +#define FE_AG_REG_CDR_CLP_POS_INIT 0x0 + +#define FE_AG_REG_CDR_CLP_NEG__A 0xC20023 +#define FE_AG_REG_CDR_CLP_NEG__W 10 +#define FE_AG_REG_CDR_CLP_NEG__M 0x3FF +#define FE_AG_REG_CDR_CLP_NEG_INIT 0x0 + +#define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 +#define FE_AG_REG_EGC_RUR_CNT__W 5 +#define FE_AG_REG_EGC_RUR_CNT__M 0x1F +#define FE_AG_REG_EGC_RUR_CNT_INIT 0x0 + +#define FE_AG_REG_EGC_SET_LVL__A 0xC20025 +#define FE_AG_REG_EGC_SET_LVL__W 9 +#define FE_AG_REG_EGC_SET_LVL__M 0x1FF +#define FE_AG_REG_EGC_SET_LVL_INIT 0x0 + +#define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 +#define FE_AG_REG_EGC_FLA_RGN__W 9 +#define FE_AG_REG_EGC_FLA_RGN__M 0x1FF +#define FE_AG_REG_EGC_FLA_RGN_INIT 0x0 + +#define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 +#define FE_AG_REG_EGC_SLO_RGN__W 9 +#define FE_AG_REG_EGC_SLO_RGN__M 0x1FF +#define FE_AG_REG_EGC_SLO_RGN_INIT 0x0 + +#define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 +#define FE_AG_REG_EGC_JMP_PSN__W 4 +#define FE_AG_REG_EGC_JMP_PSN__M 0xF +#define FE_AG_REG_EGC_JMP_PSN_INIT 0x0 + +#define FE_AG_REG_EGC_FLA_INC__A 0xC20029 +#define FE_AG_REG_EGC_FLA_INC__W 16 +#define FE_AG_REG_EGC_FLA_INC__M 0xFFFF +#define FE_AG_REG_EGC_FLA_INC_INIT 0x0 + +#define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A +#define FE_AG_REG_EGC_FLA_DEC__W 16 +#define FE_AG_REG_EGC_FLA_DEC__M 0xFFFF +#define FE_AG_REG_EGC_FLA_DEC_INIT 0x0 + +#define FE_AG_REG_EGC_SLO_INC__A 0xC2002B +#define FE_AG_REG_EGC_SLO_INC__W 16 +#define FE_AG_REG_EGC_SLO_INC__M 0xFFFF +#define FE_AG_REG_EGC_SLO_INC_INIT 0x0 + +#define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C +#define FE_AG_REG_EGC_SLO_DEC__W 16 +#define FE_AG_REG_EGC_SLO_DEC__M 0xFFFF +#define FE_AG_REG_EGC_SLO_DEC_INIT 0x0 + +#define FE_AG_REG_EGC_FAS_INC__A 0xC2002D +#define FE_AG_REG_EGC_FAS_INC__W 16 +#define FE_AG_REG_EGC_FAS_INC__M 0xFFFF +#define FE_AG_REG_EGC_FAS_INC_INIT 0x0 + +#define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E +#define FE_AG_REG_EGC_FAS_DEC__W 16 +#define FE_AG_REG_EGC_FAS_DEC__M 0xFFFF +#define FE_AG_REG_EGC_FAS_DEC_INIT 0x0 + +#define FE_AG_REG_EGC_MAP_DAT__A 0xC2002F +#define FE_AG_REG_EGC_MAP_DAT__W 16 +#define FE_AG_REG_EGC_MAP_DAT__M 0xFFFF + +#define FE_AG_REG_PM1_AGC_WRI__A 0xC20030 +#define FE_AG_REG_PM1_AGC_WRI__W 11 +#define FE_AG_REG_PM1_AGC_WRI__M 0x7FF +#define FE_AG_REG_PM1_AGC_WRI_INIT 0x0 + +#define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 +#define FE_AG_REG_GC1_AGC_RIC__W 16 +#define FE_AG_REG_GC1_AGC_RIC__M 0xFFFF +#define FE_AG_REG_GC1_AGC_RIC_INIT 0x0 + +#define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 +#define FE_AG_REG_GC1_AGC_OFF__W 16 +#define FE_AG_REG_GC1_AGC_OFF__M 0xFFFF +#define FE_AG_REG_GC1_AGC_OFF_INIT 0x0 + +#define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 +#define FE_AG_REG_GC1_AGC_MAX__W 10 +#define FE_AG_REG_GC1_AGC_MAX__M 0x3FF +#define FE_AG_REG_GC1_AGC_MAX_INIT 0x0 + +#define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 +#define FE_AG_REG_GC1_AGC_MIN__W 10 +#define FE_AG_REG_GC1_AGC_MIN__M 0x3FF +#define FE_AG_REG_GC1_AGC_MIN_INIT 0x0 + +#define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 +#define FE_AG_REG_GC1_AGC_DAT__W 10 +#define FE_AG_REG_GC1_AGC_DAT__M 0x3FF + +#define FE_AG_REG_PM2_AGC_WRI__A 0xC20036 +#define FE_AG_REG_PM2_AGC_WRI__W 11 +#define FE_AG_REG_PM2_AGC_WRI__M 0x7FF +#define FE_AG_REG_PM2_AGC_WRI_INIT 0x0 + +#define FE_AG_REG_GC2_AGC_RIC__A 0xC20037 +#define FE_AG_REG_GC2_AGC_RIC__W 16 +#define FE_AG_REG_GC2_AGC_RIC__M 0xFFFF +#define FE_AG_REG_GC2_AGC_RIC_INIT 0x0 + +#define FE_AG_REG_GC2_AGC_OFF__A 0xC20038 +#define FE_AG_REG_GC2_AGC_OFF__W 16 +#define FE_AG_REG_GC2_AGC_OFF__M 0xFFFF +#define FE_AG_REG_GC2_AGC_OFF_INIT 0x0 + +#define FE_AG_REG_GC2_AGC_MAX__A 0xC20039 +#define FE_AG_REG_GC2_AGC_MAX__W 10 +#define FE_AG_REG_GC2_AGC_MAX__M 0x3FF +#define FE_AG_REG_GC2_AGC_MAX_INIT 0x0 + +#define FE_AG_REG_GC2_AGC_MIN__A 0xC2003A +#define FE_AG_REG_GC2_AGC_MIN__W 10 +#define FE_AG_REG_GC2_AGC_MIN__M 0x3FF +#define FE_AG_REG_GC2_AGC_MIN_INIT 0x0 + +#define FE_AG_REG_GC2_AGC_DAT__A 0xC2003B +#define FE_AG_REG_GC2_AGC_DAT__W 10 +#define FE_AG_REG_GC2_AGC_DAT__M 0x3FF + +#define FE_AG_REG_IND_WIN__A 0xC2003C +#define FE_AG_REG_IND_WIN__W 5 +#define FE_AG_REG_IND_WIN__M 0x1F +#define FE_AG_REG_IND_WIN_INIT 0x0 + +#define FE_AG_REG_IND_THD_LOL__A 0xC2003D +#define FE_AG_REG_IND_THD_LOL__W 6 +#define FE_AG_REG_IND_THD_LOL__M 0x3F +#define FE_AG_REG_IND_THD_LOL_INIT 0x0 + +#define FE_AG_REG_IND_THD_HIL__A 0xC2003E +#define FE_AG_REG_IND_THD_HIL__W 6 +#define FE_AG_REG_IND_THD_HIL__M 0x3F +#define FE_AG_REG_IND_THD_HIL_INIT 0x0 + +#define FE_AG_REG_IND_DEL__A 0xC2003F +#define FE_AG_REG_IND_DEL__W 7 +#define FE_AG_REG_IND_DEL__M 0x7F +#define FE_AG_REG_IND_DEL_INIT 0x0 + +#define FE_AG_REG_IND_PD1_WRI__A 0xC20040 +#define FE_AG_REG_IND_PD1_WRI__W 6 +#define FE_AG_REG_IND_PD1_WRI__M 0x3F +#define FE_AG_REG_IND_PD1_WRI_INIT 0x1F + +#define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 +#define FE_AG_REG_PDA_AUR_CNT__W 5 +#define FE_AG_REG_PDA_AUR_CNT__M 0x1F +#define FE_AG_REG_PDA_AUR_CNT_INIT 0x0 + +#define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 +#define FE_AG_REG_PDA_RUR_CNT__W 5 +#define FE_AG_REG_PDA_RUR_CNT__M 0x1F +#define FE_AG_REG_PDA_RUR_CNT_INIT 0x0 + +#define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 +#define FE_AG_REG_PDA_AVE_DAT__W 6 +#define FE_AG_REG_PDA_AVE_DAT__M 0x3F + +#define FE_AG_REG_PDC_RUR_CNT__A 0xC20044 +#define FE_AG_REG_PDC_RUR_CNT__W 5 +#define FE_AG_REG_PDC_RUR_CNT__M 0x1F +#define FE_AG_REG_PDC_RUR_CNT_INIT 0x0 + +#define FE_AG_REG_PDC_SET_LVL__A 0xC20045 +#define FE_AG_REG_PDC_SET_LVL__W 6 +#define FE_AG_REG_PDC_SET_LVL__M 0x3F +#define FE_AG_REG_PDC_SET_LVL_INIT 0x10 + +#define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 +#define FE_AG_REG_PDC_FLA_RGN__W 6 +#define FE_AG_REG_PDC_FLA_RGN__M 0x3F +#define FE_AG_REG_PDC_FLA_RGN_INIT 0x0 + +#define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 +#define FE_AG_REG_PDC_JMP_PSN__W 3 +#define FE_AG_REG_PDC_JMP_PSN__M 0x7 +#define FE_AG_REG_PDC_JMP_PSN_INIT 0x0 + +#define FE_AG_REG_PDC_FLA_STP__A 0xC20048 +#define FE_AG_REG_PDC_FLA_STP__W 16 +#define FE_AG_REG_PDC_FLA_STP__M 0xFFFF +#define FE_AG_REG_PDC_FLA_STP_INIT 0x0 + +#define FE_AG_REG_PDC_SLO_STP__A 0xC20049 +#define FE_AG_REG_PDC_SLO_STP__W 16 +#define FE_AG_REG_PDC_SLO_STP__M 0xFFFF +#define FE_AG_REG_PDC_SLO_STP_INIT 0x0 + +#define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A +#define FE_AG_REG_PDC_PD2_WRI__W 6 +#define FE_AG_REG_PDC_PD2_WRI__M 0x3F +#define FE_AG_REG_PDC_PD2_WRI_INIT 0x0 + +#define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B +#define FE_AG_REG_PDC_MAP_DAT__W 6 +#define FE_AG_REG_PDC_MAP_DAT__M 0x3F + +#define FE_AG_REG_PDC_MAX__A 0xC2004C +#define FE_AG_REG_PDC_MAX__W 6 +#define FE_AG_REG_PDC_MAX__M 0x3F +#define FE_AG_REG_PDC_MAX_INIT 0x2 + +#define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D +#define FE_AG_REG_TGA_AUR_CNT__W 5 +#define FE_AG_REG_TGA_AUR_CNT__M 0x1F +#define FE_AG_REG_TGA_AUR_CNT_INIT 0x0 + +#define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E +#define FE_AG_REG_TGA_RUR_CNT__W 5 +#define FE_AG_REG_TGA_RUR_CNT__M 0x1F +#define FE_AG_REG_TGA_RUR_CNT_INIT 0x0 + +#define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F +#define FE_AG_REG_TGA_AVE_DAT__W 6 +#define FE_AG_REG_TGA_AVE_DAT__M 0x3F + +#define FE_AG_REG_TGC_RUR_CNT__A 0xC20050 +#define FE_AG_REG_TGC_RUR_CNT__W 5 +#define FE_AG_REG_TGC_RUR_CNT__M 0x1F +#define FE_AG_REG_TGC_RUR_CNT_INIT 0x0 + +#define FE_AG_REG_TGC_SET_LVL__A 0xC20051 +#define FE_AG_REG_TGC_SET_LVL__W 6 +#define FE_AG_REG_TGC_SET_LVL__M 0x3F +#define FE_AG_REG_TGC_SET_LVL_INIT 0x0 + +#define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 +#define FE_AG_REG_TGC_FLA_RGN__W 6 +#define FE_AG_REG_TGC_FLA_RGN__M 0x3F +#define FE_AG_REG_TGC_FLA_RGN_INIT 0x0 + +#define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 +#define FE_AG_REG_TGC_JMP_PSN__W 4 +#define FE_AG_REG_TGC_JMP_PSN__M 0xF +#define FE_AG_REG_TGC_JMP_PSN_INIT 0x0 + +#define FE_AG_REG_TGC_FLA_STP__A 0xC20054 +#define FE_AG_REG_TGC_FLA_STP__W 16 +#define FE_AG_REG_TGC_FLA_STP__M 0xFFFF +#define FE_AG_REG_TGC_FLA_STP_INIT 0x0 + +#define FE_AG_REG_TGC_SLO_STP__A 0xC20055 +#define FE_AG_REG_TGC_SLO_STP__W 16 +#define FE_AG_REG_TGC_SLO_STP__M 0xFFFF +#define FE_AG_REG_TGC_SLO_STP_INIT 0x0 + +#define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 +#define FE_AG_REG_TGC_MAP_DAT__W 10 +#define FE_AG_REG_TGC_MAP_DAT__M 0x3FF + +#define FE_AG_REG_FGA_AUR_CNT__A 0xC20057 +#define FE_AG_REG_FGA_AUR_CNT__W 5 +#define FE_AG_REG_FGA_AUR_CNT__M 0x1F +#define FE_AG_REG_FGA_AUR_CNT_INIT 0x0 + +#define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 +#define FE_AG_REG_FGA_RUR_CNT__W 5 +#define FE_AG_REG_FGA_RUR_CNT__M 0x1F +#define FE_AG_REG_FGA_RUR_CNT_INIT 0x0 + +#define FE_AG_REG_FGA_AVE_DAT__A 0xC20059 +#define FE_AG_REG_FGA_AVE_DAT__W 10 +#define FE_AG_REG_FGA_AVE_DAT__M 0x3FF + +#define FE_AG_REG_FGC_RUR_CNT__A 0xC2005A +#define FE_AG_REG_FGC_RUR_CNT__W 5 +#define FE_AG_REG_FGC_RUR_CNT__M 0x1F +#define FE_AG_REG_FGC_RUR_CNT_INIT 0x0 + +#define FE_AG_REG_FGC_SET_LVL__A 0xC2005B +#define FE_AG_REG_FGC_SET_LVL__W 9 +#define FE_AG_REG_FGC_SET_LVL__M 0x1FF +#define FE_AG_REG_FGC_SET_LVL_INIT 0x0 + +#define FE_AG_REG_FGC_FLA_RGN__A 0xC2005C +#define FE_AG_REG_FGC_FLA_RGN__W 9 +#define FE_AG_REG_FGC_FLA_RGN__M 0x1FF +#define FE_AG_REG_FGC_FLA_RGN_INIT 0x0 + +#define FE_AG_REG_FGC_JMP_PSN__A 0xC2005D +#define FE_AG_REG_FGC_JMP_PSN__W 4 +#define FE_AG_REG_FGC_JMP_PSN__M 0xF +#define FE_AG_REG_FGC_JMP_PSN_INIT 0x0 + +#define FE_AG_REG_FGC_FLA_STP__A 0xC2005E +#define FE_AG_REG_FGC_FLA_STP__W 16 +#define FE_AG_REG_FGC_FLA_STP__M 0xFFFF +#define FE_AG_REG_FGC_FLA_STP_INIT 0x0 + +#define FE_AG_REG_FGC_SLO_STP__A 0xC2005F +#define FE_AG_REG_FGC_SLO_STP__W 16 +#define FE_AG_REG_FGC_SLO_STP__M 0xFFFF +#define FE_AG_REG_FGC_SLO_STP_INIT 0x0 + +#define FE_AG_REG_FGC_MAP_DAT__A 0xC20060 +#define FE_AG_REG_FGC_MAP_DAT__W 10 +#define FE_AG_REG_FGC_MAP_DAT__M 0x3FF + +#define FE_AG_REG_FGM_WRI__A 0xC20061 +#define FE_AG_REG_FGM_WRI__W 10 +#define FE_AG_REG_FGM_WRI__M 0x3FF +#define FE_AG_REG_FGM_WRI_INIT 0x20 + +#define FE_AG_REG_BGC_RUR_CNT__A 0xC20062 +#define FE_AG_REG_BGC_RUR_CNT__W 5 +#define FE_AG_REG_BGC_RUR_CNT__M 0x1F +#define FE_AG_REG_BGC_RUR_CNT_INIT 0x0 + +#define FE_AG_REG_BGC_SET_LVL__A 0xC20063 +#define FE_AG_REG_BGC_SET_LVL__W 9 +#define FE_AG_REG_BGC_SET_LVL__M 0x1FF +#define FE_AG_REG_BGC_SET_LVL_INIT 0x0 + +#define FE_AG_REG_BGC_FLA_RGN__A 0xC20064 +#define FE_AG_REG_BGC_FLA_RGN__W 9 +#define FE_AG_REG_BGC_FLA_RGN__M 0x1FF +#define FE_AG_REG_BGC_FLA_RGN_INIT 0x0 + +#define FE_AG_REG_BGC_JMP_PSN__A 0xC20065 +#define FE_AG_REG_BGC_JMP_PSN__W 4 +#define FE_AG_REG_BGC_JMP_PSN__M 0xF +#define FE_AG_REG_BGC_JMP_PSN_INIT 0x0 + +#define FE_AG_REG_BGC_FLA_STP__A 0xC20066 +#define FE_AG_REG_BGC_FLA_STP__W 16 +#define FE_AG_REG_BGC_FLA_STP__M 0xFFFF +#define FE_AG_REG_BGC_FLA_STP_INIT 0x0 + +#define FE_AG_REG_BGC_SLO_STP__A 0xC20067 +#define FE_AG_REG_BGC_SLO_STP__W 16 +#define FE_AG_REG_BGC_SLO_STP__M 0xFFFF +#define FE_AG_REG_BGC_SLO_STP_INIT 0x0 + +#define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 +#define FE_AG_REG_BGC_FGC_WRI__W 4 +#define FE_AG_REG_BGC_FGC_WRI__M 0xF +#define FE_AG_REG_BGC_FGC_WRI_INIT 0x7 + +#define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 +#define FE_AG_REG_BGC_CGC_WRI__W 2 +#define FE_AG_REG_BGC_CGC_WRI__M 0x3 +#define FE_AG_REG_BGC_CGC_WRI_INIT 0x1 + +#define FE_AG_REG_BGC_FGC_DAT__A 0xC2006A +#define FE_AG_REG_BGC_FGC_DAT__W 4 +#define FE_AG_REG_BGC_FGC_DAT__M 0xF + +#define FE_FS_SID 0x3 + +#define FE_FS_REG_COMM_EXEC__A 0xC30000 +#define FE_FS_REG_COMM_EXEC__W 3 +#define FE_FS_REG_COMM_EXEC__M 0x7 +#define FE_FS_REG_COMM_EXEC_CTL__B 0 +#define FE_FS_REG_COMM_EXEC_CTL__W 3 +#define FE_FS_REG_COMM_EXEC_CTL__M 0x7 +#define FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 + +#define FE_FS_REG_COMM_STATE__A 0xC30001 +#define FE_FS_REG_COMM_STATE__W 4 +#define FE_FS_REG_COMM_STATE__M 0xF + +#define FE_FS_REG_COMM_MB__A 0xC30002 +#define FE_FS_REG_COMM_MB__W 3 +#define FE_FS_REG_COMM_MB__M 0x7 +#define FE_FS_REG_COMM_MB_CTR__B 0 +#define FE_FS_REG_COMM_MB_CTR__W 1 +#define FE_FS_REG_COMM_MB_CTR__M 0x1 +#define FE_FS_REG_COMM_MB_CTR_OFF 0x0 +#define FE_FS_REG_COMM_MB_CTR_ON 0x1 +#define FE_FS_REG_COMM_MB_OBS__B 1 +#define FE_FS_REG_COMM_MB_OBS__W 1 +#define FE_FS_REG_COMM_MB_OBS__M 0x2 +#define FE_FS_REG_COMM_MB_OBS_OFF 0x0 +#define FE_FS_REG_COMM_MB_OBS_ON 0x2 +#define FE_FS_REG_COMM_MB_MUX__B 2 +#define FE_FS_REG_COMM_MB_MUX__W 1 +#define FE_FS_REG_COMM_MB_MUX__M 0x4 +#define FE_FS_REG_COMM_MB_MUX_REAL 0x0 +#define FE_FS_REG_COMM_MB_MUX_IMAG 0x4 + +#define FE_FS_REG_COMM_SERVICE0__A 0xC30003 +#define FE_FS_REG_COMM_SERVICE0__W 10 +#define FE_FS_REG_COMM_SERVICE0__M 0x3FF + +#define FE_FS_REG_COMM_SERVICE1__A 0xC30004 +#define FE_FS_REG_COMM_SERVICE1__W 11 +#define FE_FS_REG_COMM_SERVICE1__M 0x7FF + +#define FE_FS_REG_COMM_ACT__A 0xC30005 +#define FE_FS_REG_COMM_ACT__W 2 +#define FE_FS_REG_COMM_ACT__M 0x3 + +#define FE_FS_REG_COMM_CNT__A 0xC30006 +#define FE_FS_REG_COMM_CNT__W 16 +#define FE_FS_REG_COMM_CNT__M 0xFFFF + +#define FE_FS_REG_ADD_INC_LOP__A 0xC30010 +#define FE_FS_REG_ADD_INC_LOP__W 16 +#define FE_FS_REG_ADD_INC_LOP__M 0xFFFF +#define FE_FS_REG_ADD_INC_LOP_INIT 0x0 + +#define FE_FS_REG_ADD_INC_HIP__A 0xC30011 +#define FE_FS_REG_ADD_INC_HIP__W 12 +#define FE_FS_REG_ADD_INC_HIP__M 0xFFF +#define FE_FS_REG_ADD_INC_HIP_INIT 0x0 + +#define FE_FS_REG_ADD_OFF__A 0xC30012 +#define FE_FS_REG_ADD_OFF__W 12 +#define FE_FS_REG_ADD_OFF__M 0xFFF +#define FE_FS_REG_ADD_OFF_INIT 0x0 + +#define FE_FS_REG_ADD_OFF_VAL__A 0xC30013 +#define FE_FS_REG_ADD_OFF_VAL__W 1 +#define FE_FS_REG_ADD_OFF_VAL__M 0x1 +#define FE_FS_REG_ADD_OFF_VAL_INIT 0x0 + +#define FE_FD_SID 0x4 + +#define FE_FD_REG_COMM_EXEC__A 0xC40000 +#define FE_FD_REG_COMM_EXEC__W 3 +#define FE_FD_REG_COMM_EXEC__M 0x7 +#define FE_FD_REG_COMM_EXEC_CTL__B 0 +#define FE_FD_REG_COMM_EXEC_CTL__W 3 +#define FE_FD_REG_COMM_EXEC_CTL__M 0x7 +#define FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 + +#define FE_FD_REG_COMM_MB__A 0xC40002 +#define FE_FD_REG_COMM_MB__W 3 +#define FE_FD_REG_COMM_MB__M 0x7 +#define FE_FD_REG_COMM_MB_CTR__B 0 +#define FE_FD_REG_COMM_MB_CTR__W 1 +#define FE_FD_REG_COMM_MB_CTR__M 0x1 +#define FE_FD_REG_COMM_MB_CTR_OFF 0x0 +#define FE_FD_REG_COMM_MB_CTR_ON 0x1 +#define FE_FD_REG_COMM_MB_OBS__B 1 +#define FE_FD_REG_COMM_MB_OBS__W 1 +#define FE_FD_REG_COMM_MB_OBS__M 0x2 +#define FE_FD_REG_COMM_MB_OBS_OFF 0x0 +#define FE_FD_REG_COMM_MB_OBS_ON 0x2 + +#define FE_FD_REG_COMM_SERVICE0__A 0xC40003 +#define FE_FD_REG_COMM_SERVICE0__W 10 +#define FE_FD_REG_COMM_SERVICE0__M 0x3FF +#define FE_FD_REG_COMM_SERVICE1__A 0xC40004 +#define FE_FD_REG_COMM_SERVICE1__W 11 +#define FE_FD_REG_COMM_SERVICE1__M 0x7FF + +#define FE_FD_REG_COMM_INT_STA__A 0xC40007 +#define FE_FD_REG_COMM_INT_STA__W 1 +#define FE_FD_REG_COMM_INT_STA__M 0x1 +#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + +#define FE_FD_REG_COMM_INT_MSK__A 0xC40008 +#define FE_FD_REG_COMM_INT_MSK__W 1 +#define FE_FD_REG_COMM_INT_MSK__M 0x1 +#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + +#define FE_FD_REG_SCL__A 0xC40010 +#define FE_FD_REG_SCL__W 6 +#define FE_FD_REG_SCL__M 0x3F + +#define FE_FD_REG_MAX_LEV__A 0xC40011 +#define FE_FD_REG_MAX_LEV__W 3 +#define FE_FD_REG_MAX_LEV__M 0x7 + +#define FE_FD_REG_NR__A 0xC40012 +#define FE_FD_REG_NR__W 5 +#define FE_FD_REG_NR__M 0x1F + +#define FE_FD_REG_MEAS_SEL__A 0xC40013 +#define FE_FD_REG_MEAS_SEL__W 1 +#define FE_FD_REG_MEAS_SEL__M 0x1 + +#define FE_FD_REG_MEAS_VAL__A 0xC40014 +#define FE_FD_REG_MEAS_VAL__W 1 +#define FE_FD_REG_MEAS_VAL__M 0x1 + +#define FE_FD_REG_MAX__A 0xC40015 +#define FE_FD_REG_MAX__W 16 +#define FE_FD_REG_MAX__M 0xFFFF + +#define FE_FD_REG_POWER__A 0xC40016 +#define FE_FD_REG_POWER__W 10 +#define FE_FD_REG_POWER__M 0x3FF + +#define FE_IF_SID 0x5 + +#define FE_IF_REG_COMM_EXEC__A 0xC50000 +#define FE_IF_REG_COMM_EXEC__W 3 +#define FE_IF_REG_COMM_EXEC__M 0x7 +#define FE_IF_REG_COMM_EXEC_CTL__B 0 +#define FE_IF_REG_COMM_EXEC_CTL__W 3 +#define FE_IF_REG_COMM_EXEC_CTL__M 0x7 +#define FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 + +#define FE_IF_REG_COMM_MB__A 0xC50002 +#define FE_IF_REG_COMM_MB__W 3 +#define FE_IF_REG_COMM_MB__M 0x7 +#define FE_IF_REG_COMM_MB_CTR__B 0 +#define FE_IF_REG_COMM_MB_CTR__W 1 +#define FE_IF_REG_COMM_MB_CTR__M 0x1 +#define FE_IF_REG_COMM_MB_CTR_OFF 0x0 +#define FE_IF_REG_COMM_MB_CTR_ON 0x1 +#define FE_IF_REG_COMM_MB_OBS__B 1 +#define FE_IF_REG_COMM_MB_OBS__W 1 +#define FE_IF_REG_COMM_MB_OBS__M 0x2 +#define FE_IF_REG_COMM_MB_OBS_OFF 0x0 +#define FE_IF_REG_COMM_MB_OBS_ON 0x2 + +#define FE_IF_REG_INCR0__A 0xC50010 +#define FE_IF_REG_INCR0__W 16 +#define FE_IF_REG_INCR0__M 0xFFFF +#define FE_IF_REG_INCR0_INIT 0x0 + +#define FE_IF_REG_INCR1__A 0xC50011 +#define FE_IF_REG_INCR1__W 8 +#define FE_IF_REG_INCR1__M 0xFF +#define FE_IF_REG_INCR1_INIT 0x28 + +#define FE_CF_SID 0x6 + +#define FE_CF_REG_COMM_EXEC__A 0xC60000 +#define FE_CF_REG_COMM_EXEC__W 3 +#define FE_CF_REG_COMM_EXEC__M 0x7 +#define FE_CF_REG_COMM_EXEC_CTL__B 0 +#define FE_CF_REG_COMM_EXEC_CTL__W 3 +#define FE_CF_REG_COMM_EXEC_CTL__M 0x7 +#define FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 + +#define FE_CF_REG_COMM_MB__A 0xC60002 +#define FE_CF_REG_COMM_MB__W 3 +#define FE_CF_REG_COMM_MB__M 0x7 +#define FE_CF_REG_COMM_MB_CTR__B 0 +#define FE_CF_REG_COMM_MB_CTR__W 1 +#define FE_CF_REG_COMM_MB_CTR__M 0x1 +#define FE_CF_REG_COMM_MB_CTR_OFF 0x0 +#define FE_CF_REG_COMM_MB_CTR_ON 0x1 +#define FE_CF_REG_COMM_MB_OBS__B 1 +#define FE_CF_REG_COMM_MB_OBS__W 1 +#define FE_CF_REG_COMM_MB_OBS__M 0x2 +#define FE_CF_REG_COMM_MB_OBS_OFF 0x0 +#define FE_CF_REG_COMM_MB_OBS_ON 0x2 + +#define FE_CF_REG_COMM_SERVICE0__A 0xC60003 +#define FE_CF_REG_COMM_SERVICE0__W 10 +#define FE_CF_REG_COMM_SERVICE0__M 0x3FF +#define FE_CF_REG_COMM_SERVICE1__A 0xC60004 +#define FE_CF_REG_COMM_SERVICE1__W 11 +#define FE_CF_REG_COMM_SERVICE1__M 0x7FF + +#define FE_CF_REG_COMM_INT_STA__A 0xC60007 +#define FE_CF_REG_COMM_INT_STA__W 2 +#define FE_CF_REG_COMM_INT_STA__M 0x3 +#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + +#define FE_CF_REG_COMM_INT_MSK__A 0xC60008 +#define FE_CF_REG_COMM_INT_MSK__W 2 +#define FE_CF_REG_COMM_INT_MSK__M 0x3 +#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + +#define FE_CF_REG_SCL__A 0xC60010 +#define FE_CF_REG_SCL__W 9 +#define FE_CF_REG_SCL__M 0x1FF + +#define FE_CF_REG_MAX_LEV__A 0xC60011 +#define FE_CF_REG_MAX_LEV__W 3 +#define FE_CF_REG_MAX_LEV__M 0x7 + +#define FE_CF_REG_NR__A 0xC60012 +#define FE_CF_REG_NR__W 5 +#define FE_CF_REG_NR__M 0x1F + +#define FE_CF_REG_IMP_VAL__A 0xC60013 +#define FE_CF_REG_IMP_VAL__W 1 +#define FE_CF_REG_IMP_VAL__M 0x1 + +#define FE_CF_REG_MEAS_VAL__A 0xC60014 +#define FE_CF_REG_MEAS_VAL__W 1 +#define FE_CF_REG_MEAS_VAL__M 0x1 + +#define FE_CF_REG_MAX__A 0xC60015 +#define FE_CF_REG_MAX__W 16 +#define FE_CF_REG_MAX__M 0xFFFF + +#define FE_CF_REG_POWER__A 0xC60016 +#define FE_CF_REG_POWER__W 10 +#define FE_CF_REG_POWER__M 0x3FF + +#define FE_CU_SID 0x7 + +#define FE_CU_REG_COMM_EXEC__A 0xC70000 +#define FE_CU_REG_COMM_EXEC__W 3 +#define FE_CU_REG_COMM_EXEC__M 0x7 +#define FE_CU_REG_COMM_EXEC_CTL__B 0 +#define FE_CU_REG_COMM_EXEC_CTL__W 3 +#define FE_CU_REG_COMM_EXEC_CTL__M 0x7 +#define FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 +#define FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 + +#define FE_CU_REG_COMM_STATE__A 0xC70001 +#define FE_CU_REG_COMM_STATE__W 4 +#define FE_CU_REG_COMM_STATE__M 0xF + +#define FE_CU_REG_COMM_MB__A 0xC70002 +#define FE_CU_REG_COMM_MB__W 3 +#define FE_CU_REG_COMM_MB__M 0x7 +#define FE_CU_REG_COMM_MB_CTR__B 0 +#define FE_CU_REG_COMM_MB_CTR__W 1 +#define FE_CU_REG_COMM_MB_CTR__M 0x1 +#define FE_CU_REG_COMM_MB_CTR_OFF 0x0 +#define FE_CU_REG_COMM_MB_CTR_ON 0x1 +#define FE_CU_REG_COMM_MB_OBS__B 1 +#define FE_CU_REG_COMM_MB_OBS__W 1 +#define FE_CU_REG_COMM_MB_OBS__M 0x2 +#define FE_CU_REG_COMM_MB_OBS_OFF 0x0 +#define FE_CU_REG_COMM_MB_OBS_ON 0x2 +#define FE_CU_REG_COMM_MB_MUX__B 2 +#define FE_CU_REG_COMM_MB_MUX__W 1 +#define FE_CU_REG_COMM_MB_MUX__M 0x4 +#define FE_CU_REG_COMM_MB_MUX_REAL 0x0 +#define FE_CU_REG_COMM_MB_MUX_IMAG 0x4 + +#define FE_CU_REG_COMM_SERVICE0__A 0xC70003 +#define FE_CU_REG_COMM_SERVICE0__W 10 +#define FE_CU_REG_COMM_SERVICE0__M 0x3FF + +#define FE_CU_REG_COMM_SERVICE1__A 0xC70004 +#define FE_CU_REG_COMM_SERVICE1__W 11 +#define FE_CU_REG_COMM_SERVICE1__M 0x7FF + +#define FE_CU_REG_COMM_ACT__A 0xC70005 +#define FE_CU_REG_COMM_ACT__W 2 +#define FE_CU_REG_COMM_ACT__M 0x3 + +#define FE_CU_REG_COMM_CNT__A 0xC70006 +#define FE_CU_REG_COMM_CNT__W 16 +#define FE_CU_REG_COMM_CNT__M 0xFFFF + +#define FE_CU_REG_COMM_INT_STA__A 0xC70007 +#define FE_CU_REG_COMM_INT_STA__W 2 +#define FE_CU_REG_COMM_INT_STA__M 0x3 +#define FE_CU_REG_COMM_INT_STA_FE_START__B 0 +#define FE_CU_REG_COMM_INT_STA_FE_START__W 1 +#define FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 +#define FE_CU_REG_COMM_INT_STA_FT_START__B 1 +#define FE_CU_REG_COMM_INT_STA_FT_START__W 1 +#define FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 + +#define FE_CU_REG_COMM_INT_MSK__A 0xC70008 +#define FE_CU_REG_COMM_INT_MSK__W 2 +#define FE_CU_REG_COMM_INT_MSK__M 0x3 +#define FE_CU_REG_COMM_INT_MSK_FE_START__B 0 +#define FE_CU_REG_COMM_INT_MSK_FE_START__W 1 +#define FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 +#define FE_CU_REG_COMM_INT_MSK_FT_START__B 1 +#define FE_CU_REG_COMM_INT_MSK_FT_START__W 1 +#define FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 + +#define FE_CU_REG_MODE__A 0xC70010 +#define FE_CU_REG_MODE__W 3 +#define FE_CU_REG_MODE__M 0x7 +#define FE_CU_REG_MODE_INIT 0x0 + +#define FE_CU_REG_MODE_FFT__B 0 +#define FE_CU_REG_MODE_FFT__W 1 +#define FE_CU_REG_MODE_FFT__M 0x1 +#define FE_CU_REG_MODE_FFT_M8K 0x0 +#define FE_CU_REG_MODE_FFT_M2K 0x1 + +#define FE_CU_REG_MODE_COR__B 1 +#define FE_CU_REG_MODE_COR__W 1 +#define FE_CU_REG_MODE_COR__M 0x2 +#define FE_CU_REG_MODE_COR_OFF 0x0 +#define FE_CU_REG_MODE_COR_ON 0x2 + +#define FE_CU_REG_MODE_IFD__B 2 +#define FE_CU_REG_MODE_IFD__W 1 +#define FE_CU_REG_MODE_IFD__M 0x4 +#define FE_CU_REG_MODE_IFD_ENABLE 0x0 +#define FE_CU_REG_MODE_IFD_DISABLE 0x4 + +#define FE_CU_REG_FRM_CNT_RST__A 0xC70011 +#define FE_CU_REG_FRM_CNT_RST__W 15 +#define FE_CU_REG_FRM_CNT_RST__M 0x7FFF +#define FE_CU_REG_FRM_CNT_RST_INIT 0x0 + +#define FE_CU_REG_FRM_CNT_STR__A 0xC70012 +#define FE_CU_REG_FRM_CNT_STR__W 15 +#define FE_CU_REG_FRM_CNT_STR__M 0x7FFF +#define FE_CU_REG_FRM_CNT_STR_INIT 0x0 + +#define FE_CU_REG_FRM_SMP_CNT__A 0xC70013 +#define FE_CU_REG_FRM_SMP_CNT__W 15 +#define FE_CU_REG_FRM_SMP_CNT__M 0x7FFF + +#define FE_CU_REG_FRM_SMB_CNT__A 0xC70014 +#define FE_CU_REG_FRM_SMB_CNT__W 16 +#define FE_CU_REG_FRM_SMB_CNT__M 0xFFFF + +#define FE_CU_REG_CMP_MAX_DAT__A 0xC70015 +#define FE_CU_REG_CMP_MAX_DAT__W 12 +#define FE_CU_REG_CMP_MAX_DAT__M 0xFFF + +#define FE_CU_REG_CMP_MAX_ADR__A 0xC70016 +#define FE_CU_REG_CMP_MAX_ADR__W 10 +#define FE_CU_REG_CMP_MAX_ADR__M 0x3FF + +#define FE_CU_REG_CTR_NF1_WLO__A 0xC70017 +#define FE_CU_REG_CTR_NF1_WLO__W 15 +#define FE_CU_REG_CTR_NF1_WLO__M 0x7FFF +#define FE_CU_REG_CTR_NF1_WLO_INIT 0x0 + +#define FE_CU_REG_CTR_NF1_WHI__A 0xC70018 +#define FE_CU_REG_CTR_NF1_WHI__W 15 +#define FE_CU_REG_CTR_NF1_WHI__M 0x7FFF +#define FE_CU_REG_CTR_NF1_WHI_INIT 0x0 + +#define FE_CU_REG_CTR_NF2_WLO__A 0xC70019 +#define FE_CU_REG_CTR_NF2_WLO__W 15 +#define FE_CU_REG_CTR_NF2_WLO__M 0x7FFF +#define FE_CU_REG_CTR_NF2_WLO_INIT 0x0 + +#define FE_CU_REG_CTR_NF2_WHI__A 0xC7001A +#define FE_CU_REG_CTR_NF2_WHI__W 15 +#define FE_CU_REG_CTR_NF2_WHI__M 0x7FFF +#define FE_CU_REG_CTR_NF2_WHI_INIT 0x0 + +#define FE_CU_REG_DIV_NF1_REA__A 0xC7001B +#define FE_CU_REG_DIV_NF1_REA__W 12 +#define FE_CU_REG_DIV_NF1_REA__M 0xFFF + +#define FE_CU_REG_DIV_NF1_IMA__A 0xC7001C +#define FE_CU_REG_DIV_NF1_IMA__W 12 +#define FE_CU_REG_DIV_NF1_IMA__M 0xFFF + +#define FE_CU_REG_DIV_NF2_REA__A 0xC7001D +#define FE_CU_REG_DIV_NF2_REA__W 12 +#define FE_CU_REG_DIV_NF2_REA__M 0xFFF + +#define FE_CU_REG_DIV_NF2_IMA__A 0xC7001E +#define FE_CU_REG_DIV_NF2_IMA__W 12 +#define FE_CU_REG_DIV_NF2_IMA__M 0xFFF + +#define FE_CU_BUF_RAM__A 0xC80000 + +#define FE_CU_CMP_RAM__A 0xC90000 + +#define FT_SID 0x8 + +#define FT_COMM_EXEC__A 0x1000000 +#define FT_COMM_EXEC__W 3 +#define FT_COMM_EXEC__M 0x7 +#define FT_COMM_EXEC_CTL__B 0 +#define FT_COMM_EXEC_CTL__W 3 +#define FT_COMM_EXEC_CTL__M 0x7 +#define FT_COMM_EXEC_CTL_STOP 0x0 +#define FT_COMM_EXEC_CTL_ACTIVE 0x1 +#define FT_COMM_EXEC_CTL_HOLD 0x2 +#define FT_COMM_EXEC_CTL_STEP 0x3 +#define FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define FT_COMM_STATE__A 0x1000001 +#define FT_COMM_STATE__W 16 +#define FT_COMM_STATE__M 0xFFFF +#define FT_COMM_MB__A 0x1000002 +#define FT_COMM_MB__W 16 +#define FT_COMM_MB__M 0xFFFF +#define FT_COMM_SERVICE0__A 0x1000003 +#define FT_COMM_SERVICE0__W 16 +#define FT_COMM_SERVICE0__M 0xFFFF +#define FT_COMM_SERVICE1__A 0x1000004 +#define FT_COMM_SERVICE1__W 16 +#define FT_COMM_SERVICE1__M 0xFFFF +#define FT_COMM_INT_STA__A 0x1000007 +#define FT_COMM_INT_STA__W 16 +#define FT_COMM_INT_STA__M 0xFFFF +#define FT_COMM_INT_MSK__A 0x1000008 +#define FT_COMM_INT_MSK__W 16 +#define FT_COMM_INT_MSK__M 0xFFFF + +#define FT_REG_COMM_EXEC__A 0x1010000 +#define FT_REG_COMM_EXEC__W 3 +#define FT_REG_COMM_EXEC__M 0x7 +#define FT_REG_COMM_EXEC_CTL__B 0 +#define FT_REG_COMM_EXEC_CTL__W 3 +#define FT_REG_COMM_EXEC_CTL__M 0x7 +#define FT_REG_COMM_EXEC_CTL_STOP 0x0 +#define FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define FT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define FT_REG_COMM_EXEC_CTL_STEP 0x3 + +#define FT_REG_COMM_MB__A 0x1010002 +#define FT_REG_COMM_MB__W 3 +#define FT_REG_COMM_MB__M 0x7 +#define FT_REG_COMM_MB_CTR__B 0 +#define FT_REG_COMM_MB_CTR__W 1 +#define FT_REG_COMM_MB_CTR__M 0x1 +#define FT_REG_COMM_MB_CTR_OFF 0x0 +#define FT_REG_COMM_MB_CTR_ON 0x1 +#define FT_REG_COMM_MB_OBS__B 1 +#define FT_REG_COMM_MB_OBS__W 1 +#define FT_REG_COMM_MB_OBS__M 0x2 +#define FT_REG_COMM_MB_OBS_OFF 0x0 +#define FT_REG_COMM_MB_OBS_ON 0x2 + +#define FT_REG_COMM_SERVICE0__A 0x1010003 +#define FT_REG_COMM_SERVICE0__W 10 +#define FT_REG_COMM_SERVICE0__M 0x3FF +#define FT_REG_COMM_SERVICE0_FT__B 8 +#define FT_REG_COMM_SERVICE0_FT__W 1 +#define FT_REG_COMM_SERVICE0_FT__M 0x100 + +#define FT_REG_COMM_SERVICE1__A 0x1010004 +#define FT_REG_COMM_SERVICE1__W 11 +#define FT_REG_COMM_SERVICE1__M 0x7FF + +#define FT_REG_COMM_INT_STA__A 0x1010007 +#define FT_REG_COMM_INT_STA__W 2 +#define FT_REG_COMM_INT_STA__M 0x3 +#define FT_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define FT_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define FT_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + +#define FT_REG_COMM_INT_MSK__A 0x1010008 +#define FT_REG_COMM_INT_MSK__W 2 +#define FT_REG_COMM_INT_MSK__M 0x3 +#define FT_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define FT_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define FT_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + +#define FT_REG_MODE_2K__A 0x1010010 +#define FT_REG_MODE_2K__W 1 +#define FT_REG_MODE_2K__M 0x1 +#define FT_REG_MODE_2K_MODE_8K 0x0 +#define FT_REG_MODE_2K_MODE_2K 0x1 +#define FT_REG_MODE_2K_INIT 0x0 + +#define FT_REG_BUS_MOD__A 0x1010011 +#define FT_REG_BUS_MOD__W 1 +#define FT_REG_BUS_MOD__M 0x1 +#define FT_REG_BUS_MOD_INPUT 0x0 +#define FT_REG_BUS_MOD_PILOT 0x1 +#define FT_REG_BUS_MOD_INIT 0x0 + +#define FT_REG_BUS_REAL__A 0x1010012 +#define FT_REG_BUS_REAL__W 10 +#define FT_REG_BUS_REAL__M 0x3FF +#define FT_REG_BUS_REAL_INIT 0x0 + +#define FT_REG_BUS_IMAG__A 0x1010013 +#define FT_REG_BUS_IMAG__W 10 +#define FT_REG_BUS_IMAG__M 0x3FF +#define FT_REG_BUS_IMAG_INIT 0x0 + +#define FT_REG_BUS_VAL__A 0x1010014 +#define FT_REG_BUS_VAL__W 1 +#define FT_REG_BUS_VAL__M 0x1 +#define FT_REG_BUS_VAL_INIT 0x0 + +#define FT_REG_PEAK__A 0x1010015 +#define FT_REG_PEAK__W 11 +#define FT_REG_PEAK__M 0x7FF +#define FT_REG_PEAK_INIT 0x0 + +#define FT_REG_NORM_OFF__A 0x1010016 +#define FT_REG_NORM_OFF__W 4 +#define FT_REG_NORM_OFF__M 0xF +#define FT_REG_NORM_OFF_INIT 0x2 + +#define FT_ST1_RAM__A 0x1020000 + +#define FT_ST2_RAM__A 0x1030000 + +#define FT_ST3_RAM__A 0x1040000 + +#define FT_ST5_RAM__A 0x1050000 + +#define FT_ST6_RAM__A 0x1060000 + +#define FT_ST8_RAM__A 0x1070000 + +#define FT_ST9_RAM__A 0x1080000 + +#define CP_SID 0x9 + +#define CP_COMM_EXEC__A 0x1400000 +#define CP_COMM_EXEC__W 3 +#define CP_COMM_EXEC__M 0x7 +#define CP_COMM_EXEC_CTL__B 0 +#define CP_COMM_EXEC_CTL__W 3 +#define CP_COMM_EXEC_CTL__M 0x7 +#define CP_COMM_EXEC_CTL_STOP 0x0 +#define CP_COMM_EXEC_CTL_ACTIVE 0x1 +#define CP_COMM_EXEC_CTL_HOLD 0x2 +#define CP_COMM_EXEC_CTL_STEP 0x3 +#define CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define CP_COMM_STATE__A 0x1400001 +#define CP_COMM_STATE__W 16 +#define CP_COMM_STATE__M 0xFFFF +#define CP_COMM_MB__A 0x1400002 +#define CP_COMM_MB__W 16 +#define CP_COMM_MB__M 0xFFFF +#define CP_COMM_SERVICE0__A 0x1400003 +#define CP_COMM_SERVICE0__W 16 +#define CP_COMM_SERVICE0__M 0xFFFF +#define CP_COMM_SERVICE1__A 0x1400004 +#define CP_COMM_SERVICE1__W 16 +#define CP_COMM_SERVICE1__M 0xFFFF +#define CP_COMM_INT_STA__A 0x1400007 +#define CP_COMM_INT_STA__W 16 +#define CP_COMM_INT_STA__M 0xFFFF +#define CP_COMM_INT_MSK__A 0x1400008 +#define CP_COMM_INT_MSK__W 16 +#define CP_COMM_INT_MSK__M 0xFFFF + +#define CP_REG_COMM_EXEC__A 0x1410000 +#define CP_REG_COMM_EXEC__W 3 +#define CP_REG_COMM_EXEC__M 0x7 +#define CP_REG_COMM_EXEC_CTL__B 0 +#define CP_REG_COMM_EXEC_CTL__W 3 +#define CP_REG_COMM_EXEC_CTL__M 0x7 +#define CP_REG_COMM_EXEC_CTL_STOP 0x0 +#define CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define CP_REG_COMM_EXEC_CTL_HOLD 0x2 +#define CP_REG_COMM_EXEC_CTL_STEP 0x3 + +#define CP_REG_COMM_MB__A 0x1410002 +#define CP_REG_COMM_MB__W 3 +#define CP_REG_COMM_MB__M 0x7 +#define CP_REG_COMM_MB_CTR__B 0 +#define CP_REG_COMM_MB_CTR__W 1 +#define CP_REG_COMM_MB_CTR__M 0x1 +#define CP_REG_COMM_MB_CTR_OFF 0x0 +#define CP_REG_COMM_MB_CTR_ON 0x1 +#define CP_REG_COMM_MB_OBS__B 1 +#define CP_REG_COMM_MB_OBS__W 1 +#define CP_REG_COMM_MB_OBS__M 0x2 +#define CP_REG_COMM_MB_OBS_OFF 0x0 +#define CP_REG_COMM_MB_OBS_ON 0x2 + +#define CP_REG_COMM_SERVICE0__A 0x1410003 +#define CP_REG_COMM_SERVICE0__W 10 +#define CP_REG_COMM_SERVICE0__M 0x3FF +#define CP_REG_COMM_SERVICE0_CP__B 9 +#define CP_REG_COMM_SERVICE0_CP__W 1 +#define CP_REG_COMM_SERVICE0_CP__M 0x200 + +#define CP_REG_COMM_SERVICE1__A 0x1410004 +#define CP_REG_COMM_SERVICE1__W 11 +#define CP_REG_COMM_SERVICE1__M 0x7FF + +#define CP_REG_COMM_INT_STA__A 0x1410007 +#define CP_REG_COMM_INT_STA__W 2 +#define CP_REG_COMM_INT_STA__M 0x3 +#define CP_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define CP_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + +#define CP_REG_COMM_INT_MSK__A 0x1410008 +#define CP_REG_COMM_INT_MSK__W 2 +#define CP_REG_COMM_INT_MSK__M 0x3 +#define CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + +#define CP_REG_MODE_2K__A 0x1410010 +#define CP_REG_MODE_2K__W 1 +#define CP_REG_MODE_2K__M 0x1 +#define CP_REG_MODE_2K_INIT 0x0 + +#define CP_REG_INTERVAL__A 0x1410011 +#define CP_REG_INTERVAL__W 4 +#define CP_REG_INTERVAL__M 0xF +#define CP_REG_INTERVAL_INIT 0x5 + +#define CP_REG_SKIP_START0__A 0x1410012 +#define CP_REG_SKIP_START0__W 13 +#define CP_REG_SKIP_START0__M 0x1FFF +#define CP_REG_SKIP_START0_INIT 0x0 + +#define CP_REG_SKIP_STOP0__A 0x1410013 +#define CP_REG_SKIP_STOP0__W 13 +#define CP_REG_SKIP_STOP0__M 0x1FFF +#define CP_REG_SKIP_STOP0_INIT 0x0 + +#define CP_REG_SKIP_START1__A 0x1410014 +#define CP_REG_SKIP_START1__W 13 +#define CP_REG_SKIP_START1__M 0x1FFF +#define CP_REG_SKIP_START1_INIT 0x0 + +#define CP_REG_SKIP_STOP1__A 0x1410015 +#define CP_REG_SKIP_STOP1__W 13 +#define CP_REG_SKIP_STOP1__M 0x1FFF +#define CP_REG_SKIP_STOP1_INIT 0x0 + +#define CP_REG_SKIP_START2__A 0x1410016 +#define CP_REG_SKIP_START2__W 13 +#define CP_REG_SKIP_START2__M 0x1FFF +#define CP_REG_SKIP_START2_INIT 0x0 + +#define CP_REG_SKIP_STOP2__A 0x1410017 +#define CP_REG_SKIP_STOP2__W 13 +#define CP_REG_SKIP_STOP2__M 0x1FFF +#define CP_REG_SKIP_STOP2_INIT 0x0 + +#define CP_REG_SKIP_ENA__A 0x1410018 +#define CP_REG_SKIP_ENA__W 3 +#define CP_REG_SKIP_ENA__M 0x7 + +#define CP_REG_SKIP_ENA_CPL__B 0 +#define CP_REG_SKIP_ENA_CPL__W 1 +#define CP_REG_SKIP_ENA_CPL__M 0x1 + +#define CP_REG_SKIP_ENA_SPD__B 1 +#define CP_REG_SKIP_ENA_SPD__W 1 +#define CP_REG_SKIP_ENA_SPD__M 0x2 + +#define CP_REG_SKIP_ENA_CPD__B 2 +#define CP_REG_SKIP_ENA_CPD__W 1 +#define CP_REG_SKIP_ENA_CPD__M 0x4 +#define CP_REG_SKIP_ENA_INIT 0x0 + +#define CP_REG_BR_MODE_MIX__A 0x1410020 +#define CP_REG_BR_MODE_MIX__W 1 +#define CP_REG_BR_MODE_MIX__M 0x1 +#define CP_REG_BR_MODE_MIX_INIT 0x0 + +#define CP_REG_BR_SMB_NR__A 0x1410021 +#define CP_REG_BR_SMB_NR__W 3 +#define CP_REG_BR_SMB_NR__M 0x7 + +#define CP_REG_BR_SMB_NR_SMB__B 0 +#define CP_REG_BR_SMB_NR_SMB__W 2 +#define CP_REG_BR_SMB_NR_SMB__M 0x3 + +#define CP_REG_BR_SMB_NR_VAL__B 2 +#define CP_REG_BR_SMB_NR_VAL__W 1 +#define CP_REG_BR_SMB_NR_VAL__M 0x4 +#define CP_REG_BR_SMB_NR_INIT 0x0 + +#define CP_REG_BR_CP_SMB_NR__A 0x1410022 +#define CP_REG_BR_CP_SMB_NR__W 2 +#define CP_REG_BR_CP_SMB_NR__M 0x3 +#define CP_REG_BR_CP_SMB_NR_INIT 0x0 + +#define CP_REG_BR_SPL_OFFSET__A 0x1410023 +#define CP_REG_BR_SPL_OFFSET__W 3 +#define CP_REG_BR_SPL_OFFSET__M 0x7 +#define CP_REG_BR_SPL_OFFSET_INIT 0x0 + +#define CP_REG_BR_STR_DEL__A 0x1410024 +#define CP_REG_BR_STR_DEL__W 10 +#define CP_REG_BR_STR_DEL__M 0x3FF +#define CP_REG_BR_STR_DEL_INIT 0xA + +#define CP_REG_RT_ANG_INC0__A 0x1410030 +#define CP_REG_RT_ANG_INC0__W 16 +#define CP_REG_RT_ANG_INC0__M 0xFFFF +#define CP_REG_RT_ANG_INC0_INIT 0x0 + +#define CP_REG_RT_ANG_INC1__A 0x1410031 +#define CP_REG_RT_ANG_INC1__W 8 +#define CP_REG_RT_ANG_INC1__M 0xFF +#define CP_REG_RT_ANG_INC1_INIT 0x0 + +#define CP_REG_RT_DETECT_ENA__A 0x1410032 +#define CP_REG_RT_DETECT_ENA__W 2 +#define CP_REG_RT_DETECT_ENA__M 0x3 + +#define CP_REG_RT_DETECT_ENA_SCATTERED__B 0 +#define CP_REG_RT_DETECT_ENA_SCATTERED__W 1 +#define CP_REG_RT_DETECT_ENA_SCATTERED__M 0x1 + +#define CP_REG_RT_DETECT_ENA_CONTINUOUS__B 1 +#define CP_REG_RT_DETECT_ENA_CONTINUOUS__W 1 +#define CP_REG_RT_DETECT_ENA_CONTINUOUS__M 0x2 +#define CP_REG_RT_DETECT_ENA_INIT 0x0 + +#define CP_REG_RT_DETECT_TRH__A 0x1410033 +#define CP_REG_RT_DETECT_TRH__W 2 +#define CP_REG_RT_DETECT_TRH__M 0x3 +#define CP_REG_RT_DETECT_TRH_INIT 0x3 + +#define CP_REG_RT_SPD_RELIABLE__A 0x1410034 +#define CP_REG_RT_SPD_RELIABLE__W 3 +#define CP_REG_RT_SPD_RELIABLE__M 0x7 +#define CP_REG_RT_SPD_RELIABLE_INIT 0x0 + +#define CP_REG_RT_SPD_DIRECTION__A 0x1410035 +#define CP_REG_RT_SPD_DIRECTION__W 1 +#define CP_REG_RT_SPD_DIRECTION__M 0x1 +#define CP_REG_RT_SPD_DIRECTION_INIT 0x0 + +#define CP_REG_RT_SPD_MOD__A 0x1410036 +#define CP_REG_RT_SPD_MOD__W 2 +#define CP_REG_RT_SPD_MOD__M 0x3 +#define CP_REG_RT_SPD_MOD_INIT 0x0 + +#define CP_REG_RT_SPD_SMB__A 0x1410037 +#define CP_REG_RT_SPD_SMB__W 2 +#define CP_REG_RT_SPD_SMB__M 0x3 +#define CP_REG_RT_SPD_SMB_INIT 0x0 + +#define CP_REG_RT_CPD_MODE__A 0x1410038 +#define CP_REG_RT_CPD_MODE__W 3 +#define CP_REG_RT_CPD_MODE__M 0x7 + +#define CP_REG_RT_CPD_MODE_MOD3__B 0 +#define CP_REG_RT_CPD_MODE_MOD3__W 2 +#define CP_REG_RT_CPD_MODE_MOD3__M 0x3 + +#define CP_REG_RT_CPD_MODE_ADD__B 2 +#define CP_REG_RT_CPD_MODE_ADD__W 1 +#define CP_REG_RT_CPD_MODE_ADD__M 0x4 +#define CP_REG_RT_CPD_MODE_INIT 0x0 + +#define CP_REG_RT_CPD_RELIABLE__A 0x1410039 +#define CP_REG_RT_CPD_RELIABLE__W 3 +#define CP_REG_RT_CPD_RELIABLE__M 0x7 +#define CP_REG_RT_CPD_RELIABLE_INIT 0x0 + +#define CP_REG_RT_CPD_BIN__A 0x141003A +#define CP_REG_RT_CPD_BIN__W 5 +#define CP_REG_RT_CPD_BIN__M 0x1F +#define CP_REG_RT_CPD_BIN_INIT 0x0 + +#define CP_REG_RT_CPD_MAX__A 0x141003B +#define CP_REG_RT_CPD_MAX__W 4 +#define CP_REG_RT_CPD_MAX__M 0xF +#define CP_REG_RT_CPD_MAX_INIT 0x0 + +#define CP_REG_RT_SUPR_VAL__A 0x141003C +#define CP_REG_RT_SUPR_VAL__W 2 +#define CP_REG_RT_SUPR_VAL__M 0x3 + +#define CP_REG_RT_SUPR_VAL_CE__B 0 +#define CP_REG_RT_SUPR_VAL_CE__W 1 +#define CP_REG_RT_SUPR_VAL_CE__M 0x1 + +#define CP_REG_RT_SUPR_VAL_DL__B 1 +#define CP_REG_RT_SUPR_VAL_DL__W 1 +#define CP_REG_RT_SUPR_VAL_DL__M 0x2 +#define CP_REG_RT_SUPR_VAL_INIT 0x0 + +#define CP_REG_RT_EXP_AVE__A 0x141003D +#define CP_REG_RT_EXP_AVE__W 5 +#define CP_REG_RT_EXP_AVE__M 0x1F +#define CP_REG_RT_EXP_AVE_INIT 0x0 + +#define CP_REG_RT_EXP_MARG__A 0x141003E +#define CP_REG_RT_EXP_MARG__W 5 +#define CP_REG_RT_EXP_MARG__M 0x1F +#define CP_REG_RT_EXP_MARG_INIT 0x0 + +#define CP_REG_AC_NEXP_OFFS__A 0x1410040 +#define CP_REG_AC_NEXP_OFFS__W 8 +#define CP_REG_AC_NEXP_OFFS__M 0xFF +#define CP_REG_AC_NEXP_OFFS_INIT 0x0 + +#define CP_REG_AC_AVER_POW__A 0x1410041 +#define CP_REG_AC_AVER_POW__W 8 +#define CP_REG_AC_AVER_POW__M 0xFF +#define CP_REG_AC_AVER_POW_INIT 0x5F + +#define CP_REG_AC_MAX_POW__A 0x1410042 +#define CP_REG_AC_MAX_POW__W 8 +#define CP_REG_AC_MAX_POW__M 0xFF +#define CP_REG_AC_MAX_POW_INIT 0x7A + +#define CP_REG_AC_WEIGHT_MAN__A 0x1410043 +#define CP_REG_AC_WEIGHT_MAN__W 6 +#define CP_REG_AC_WEIGHT_MAN__M 0x3F +#define CP_REG_AC_WEIGHT_MAN_INIT 0x31 + +#define CP_REG_AC_WEIGHT_EXP__A 0x1410044 +#define CP_REG_AC_WEIGHT_EXP__W 5 +#define CP_REG_AC_WEIGHT_EXP__M 0x1F +#define CP_REG_AC_WEIGHT_EXP_INIT 0x10 + +#define CP_REG_AC_GAIN_MAN__A 0x1410045 +#define CP_REG_AC_GAIN_MAN__W 16 +#define CP_REG_AC_GAIN_MAN__M 0xFFFF +#define CP_REG_AC_GAIN_MAN_INIT 0x0 + +#define CP_REG_AC_GAIN_EXP__A 0x1410046 +#define CP_REG_AC_GAIN_EXP__W 5 +#define CP_REG_AC_GAIN_EXP__M 0x1F +#define CP_REG_AC_GAIN_EXP_INIT 0x0 + +#define CP_REG_AC_AMP_MODE__A 0x1410047 +#define CP_REG_AC_AMP_MODE__W 2 +#define CP_REG_AC_AMP_MODE__M 0x3 +#define CP_REG_AC_AMP_MODE_NEW 0x0 +#define CP_REG_AC_AMP_MODE_OLD 0x1 +#define CP_REG_AC_AMP_MODE_FIXED 0x2 +#define CP_REG_AC_AMP_MODE_INIT 0x2 + +#define CP_REG_AC_AMP_FIX__A 0x1410048 +#define CP_REG_AC_AMP_FIX__W 14 +#define CP_REG_AC_AMP_FIX__M 0x3FFF +#define CP_REG_AC_AMP_FIX_INIT 0x1FF + +#define CP_REG_AC_AMP_READ__A 0x1410049 +#define CP_REG_AC_AMP_READ__W 14 +#define CP_REG_AC_AMP_READ__M 0x3FFF +#define CP_REG_AC_AMP_READ_INIT 0x0 + +#define CP_REG_AC_ANG_MODE__A 0x141004A +#define CP_REG_AC_ANG_MODE__W 2 +#define CP_REG_AC_ANG_MODE__M 0x3 +#define CP_REG_AC_ANG_MODE_NEW 0x0 +#define CP_REG_AC_ANG_MODE_OLD 0x1 +#define CP_REG_AC_ANG_MODE_NO_INT 0x2 +#define CP_REG_AC_ANG_MODE_OFFSET 0x3 +#define CP_REG_AC_ANG_MODE_INIT 0x3 + +#define CP_REG_AC_ANG_OFFS__A 0x141004B +#define CP_REG_AC_ANG_OFFS__W 14 +#define CP_REG_AC_ANG_OFFS__M 0x3FFF +#define CP_REG_AC_ANG_OFFS_INIT 0x0 + +#define CP_REG_AC_ANG_READ__A 0x141004C +#define CP_REG_AC_ANG_READ__W 16 +#define CP_REG_AC_ANG_READ__M 0xFFFF +#define CP_REG_AC_ANG_READ_INIT 0x0 + +#define CP_REG_DL_MB_WR_ADDR__A 0x1410050 +#define CP_REG_DL_MB_WR_ADDR__W 15 +#define CP_REG_DL_MB_WR_ADDR__M 0x7FFF +#define CP_REG_DL_MB_WR_ADDR_INIT 0x0 + +#define CP_REG_DL_MB_WR_CTR__A 0x1410051 +#define CP_REG_DL_MB_WR_CTR__W 5 +#define CP_REG_DL_MB_WR_CTR__M 0x1F + +#define CP_REG_DL_MB_WR_CTR_WORD__B 2 +#define CP_REG_DL_MB_WR_CTR_WORD__W 3 +#define CP_REG_DL_MB_WR_CTR_WORD__M 0x1C + +#define CP_REG_DL_MB_WR_CTR_OBS__B 1 +#define CP_REG_DL_MB_WR_CTR_OBS__W 1 +#define CP_REG_DL_MB_WR_CTR_OBS__M 0x2 + +#define CP_REG_DL_MB_WR_CTR_CTR__B 0 +#define CP_REG_DL_MB_WR_CTR_CTR__W 1 +#define CP_REG_DL_MB_WR_CTR_CTR__M 0x1 +#define CP_REG_DL_MB_WR_CTR_INIT 0x0 + +#define CP_REG_DL_MB_RD_ADDR__A 0x1410052 +#define CP_REG_DL_MB_RD_ADDR__W 15 +#define CP_REG_DL_MB_RD_ADDR__M 0x7FFF +#define CP_REG_DL_MB_RD_ADDR_INIT 0x0 + +#define CP_REG_DL_MB_RD_CTR__A 0x1410053 +#define CP_REG_DL_MB_RD_CTR__W 11 +#define CP_REG_DL_MB_RD_CTR__M 0x7FF + +#define CP_REG_DL_MB_RD_CTR_TEST__B 10 +#define CP_REG_DL_MB_RD_CTR_TEST__W 1 +#define CP_REG_DL_MB_RD_CTR_TEST__M 0x400 + +#define CP_REG_DL_MB_RD_CTR_OFFSET__B 8 +#define CP_REG_DL_MB_RD_CTR_OFFSET__W 2 +#define CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 + +#define CP_REG_DL_MB_RD_CTR_VALID__B 5 +#define CP_REG_DL_MB_RD_CTR_VALID__W 3 +#define CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 + +#define CP_REG_DL_MB_RD_CTR_WORD__B 2 +#define CP_REG_DL_MB_RD_CTR_WORD__W 3 +#define CP_REG_DL_MB_RD_CTR_WORD__M 0x1C + +#define CP_REG_DL_MB_RD_CTR_OBS__B 1 +#define CP_REG_DL_MB_RD_CTR_OBS__W 1 +#define CP_REG_DL_MB_RD_CTR_OBS__M 0x2 + +#define CP_REG_DL_MB_RD_CTR_CTR__B 0 +#define CP_REG_DL_MB_RD_CTR_CTR__W 1 +#define CP_REG_DL_MB_RD_CTR_CTR__M 0x1 +#define CP_REG_DL_MB_RD_CTR_INIT 0x0 + +#define CP_BR_BUF_RAM__A 0x1420000 + +#define CP_BR_CPL_RAM__A 0x1430000 + +#define CP_PB_DL0_RAM__A 0x1440000 + +#define CP_PB_DL1_RAM__A 0x1450000 + +#define CP_PB_DL2_RAM__A 0x1460000 + +#define CE_SID 0xA + +#define CE_COMM_EXEC__A 0x1800000 +#define CE_COMM_EXEC__W 3 +#define CE_COMM_EXEC__M 0x7 +#define CE_COMM_EXEC_CTL__B 0 +#define CE_COMM_EXEC_CTL__W 3 +#define CE_COMM_EXEC_CTL__M 0x7 +#define CE_COMM_EXEC_CTL_STOP 0x0 +#define CE_COMM_EXEC_CTL_ACTIVE 0x1 +#define CE_COMM_EXEC_CTL_HOLD 0x2 +#define CE_COMM_EXEC_CTL_STEP 0x3 +#define CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define CE_COMM_STATE__A 0x1800001 +#define CE_COMM_STATE__W 16 +#define CE_COMM_STATE__M 0xFFFF +#define CE_COMM_MB__A 0x1800002 +#define CE_COMM_MB__W 16 +#define CE_COMM_MB__M 0xFFFF +#define CE_COMM_SERVICE0__A 0x1800003 +#define CE_COMM_SERVICE0__W 16 +#define CE_COMM_SERVICE0__M 0xFFFF +#define CE_COMM_SERVICE1__A 0x1800004 +#define CE_COMM_SERVICE1__W 16 +#define CE_COMM_SERVICE1__M 0xFFFF +#define CE_COMM_INT_STA__A 0x1800007 +#define CE_COMM_INT_STA__W 16 +#define CE_COMM_INT_STA__M 0xFFFF +#define CE_COMM_INT_MSK__A 0x1800008 +#define CE_COMM_INT_MSK__W 16 +#define CE_COMM_INT_MSK__M 0xFFFF + +#define CE_REG_COMM_EXEC__A 0x1810000 +#define CE_REG_COMM_EXEC__W 3 +#define CE_REG_COMM_EXEC__M 0x7 +#define CE_REG_COMM_EXEC_CTL__B 0 +#define CE_REG_COMM_EXEC_CTL__W 3 +#define CE_REG_COMM_EXEC_CTL__M 0x7 +#define CE_REG_COMM_EXEC_CTL_STOP 0x0 +#define CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define CE_REG_COMM_EXEC_CTL_HOLD 0x2 +#define CE_REG_COMM_EXEC_CTL_STEP 0x3 + +#define CE_REG_COMM_MB__A 0x1810002 +#define CE_REG_COMM_MB__W 4 +#define CE_REG_COMM_MB__M 0xF +#define CE_REG_COMM_MB_CTR__B 0 +#define CE_REG_COMM_MB_CTR__W 1 +#define CE_REG_COMM_MB_CTR__M 0x1 +#define CE_REG_COMM_MB_CTR_OFF 0x0 +#define CE_REG_COMM_MB_CTR_ON 0x1 +#define CE_REG_COMM_MB_OBS__B 1 +#define CE_REG_COMM_MB_OBS__W 1 +#define CE_REG_COMM_MB_OBS__M 0x2 +#define CE_REG_COMM_MB_OBS_OFF 0x0 +#define CE_REG_COMM_MB_OBS_ON 0x2 +#define CE_REG_COMM_MB_OBS_SEL__B 2 +#define CE_REG_COMM_MB_OBS_SEL__W 2 +#define CE_REG_COMM_MB_OBS_SEL__M 0xC +#define CE_REG_COMM_MB_OBS_SEL_FI 0x0 +#define CE_REG_COMM_MB_OBS_SEL_TP 0x4 +#define CE_REG_COMM_MB_OBS_SEL_TI 0x8 +#define CE_REG_COMM_MB_OBS_SEL_FR 0x8 + +#define CE_REG_COMM_SERVICE0__A 0x1810003 +#define CE_REG_COMM_SERVICE0__W 10 +#define CE_REG_COMM_SERVICE0__M 0x3FF +#define CE_REG_COMM_SERVICE0_FT__B 8 +#define CE_REG_COMM_SERVICE0_FT__W 1 +#define CE_REG_COMM_SERVICE0_FT__M 0x100 + +#define CE_REG_COMM_SERVICE1__A 0x1810004 +#define CE_REG_COMM_SERVICE1__W 11 +#define CE_REG_COMM_SERVICE1__M 0x7FF + +#define CE_REG_COMM_INT_STA__A 0x1810007 +#define CE_REG_COMM_INT_STA__W 3 +#define CE_REG_COMM_INT_STA__M 0x7 +#define CE_REG_COMM_INT_STA_CE_PE__B 0 +#define CE_REG_COMM_INT_STA_CE_PE__W 1 +#define CE_REG_COMM_INT_STA_CE_PE__M 0x1 +#define CE_REG_COMM_INT_STA_CE_IR__B 1 +#define CE_REG_COMM_INT_STA_CE_IR__W 1 +#define CE_REG_COMM_INT_STA_CE_IR__M 0x2 +#define CE_REG_COMM_INT_STA_CE_FI__B 2 +#define CE_REG_COMM_INT_STA_CE_FI__W 1 +#define CE_REG_COMM_INT_STA_CE_FI__M 0x4 + +#define CE_REG_COMM_INT_MSK__A 0x1810008 +#define CE_REG_COMM_INT_MSK__W 3 +#define CE_REG_COMM_INT_MSK__M 0x7 +#define CE_REG_COMM_INT_MSK_CE_PE__B 0 +#define CE_REG_COMM_INT_MSK_CE_PE__W 1 +#define CE_REG_COMM_INT_MSK_CE_PE__M 0x1 +#define CE_REG_COMM_INT_MSK_CE_IR__B 1 +#define CE_REG_COMM_INT_MSK_CE_IR__W 1 +#define CE_REG_COMM_INT_MSK_CE_IR__M 0x2 +#define CE_REG_COMM_INT_MSK_CE_FI__B 2 +#define CE_REG_COMM_INT_MSK_CE_FI__W 1 +#define CE_REG_COMM_INT_MSK_CE_FI__M 0x4 + +#define CE_REG_2K__A 0x1810010 +#define CE_REG_2K__W 1 +#define CE_REG_2K__M 0x1 +#define CE_REG_2K_INIT 0x0 + +#define CE_REG_TAPSET__A 0x1810011 +#define CE_REG_TAPSET__W 2 +#define CE_REG_TAPSET__M 0x3 + +#define CE_REG_TAPSET_MOTION_INIT 0x0 + +#define CE_REG_TAPSET_MOTION_NO 0x0 + +#define CE_REG_TAPSET_MOTION_LOW 0x1 + +#define CE_REG_TAPSET_MOTION_HIGH 0x2 + +#define CE_REG_TAPSET_MOTION_UNDEFINED 0x3 + +#define CE_REG_AVG_POW__A 0x1810012 +#define CE_REG_AVG_POW__W 8 +#define CE_REG_AVG_POW__M 0xFF +#define CE_REG_AVG_POW_INIT 0x0 + +#define CE_REG_MAX_POW__A 0x1810013 +#define CE_REG_MAX_POW__W 8 +#define CE_REG_MAX_POW__M 0xFF +#define CE_REG_MAX_POW_INIT 0x0 + +#define CE_REG_ATT__A 0x1810014 +#define CE_REG_ATT__W 8 +#define CE_REG_ATT__M 0xFF +#define CE_REG_ATT_INIT 0x0 + +#define CE_REG_NRED__A 0x1810015 +#define CE_REG_NRED__W 6 +#define CE_REG_NRED__M 0x3F +#define CE_REG_NRED_INIT 0x0 + +#define CE_REG_PU_SIGN__A 0x1810020 +#define CE_REG_PU_SIGN__W 1 +#define CE_REG_PU_SIGN__M 0x1 +#define CE_REG_PU_SIGN_INIT 0x0 + +#define CE_REG_PU_MIX__A 0x1810021 +#define CE_REG_PU_MIX__W 7 +#define CE_REG_PU_MIX__M 0x7F +#define CE_REG_PU_MIX_INIT 0x0 + +#define CE_REG_PB_PILOT_REQ__A 0x1810030 +#define CE_REG_PB_PILOT_REQ__W 15 +#define CE_REG_PB_PILOT_REQ__M 0x7FFF +#define CE_REG_PB_PILOT_REQ_INIT 0x0 +#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 +#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 +#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 +#define CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 +#define CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 +#define CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF + +#define CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 +#define CE_REG_PB_PILOT_REQ_VALID__W 1 +#define CE_REG_PB_PILOT_REQ_VALID__M 0x1 +#define CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 + +#define CE_REG_PB_FREEZE__A 0x1810032 +#define CE_REG_PB_FREEZE__W 1 +#define CE_REG_PB_FREEZE__M 0x1 +#define CE_REG_PB_FREEZE_INIT 0x0 + +#define CE_REG_PB_PILOT_EXP__A 0x1810038 +#define CE_REG_PB_PILOT_EXP__W 4 +#define CE_REG_PB_PILOT_EXP__M 0xF +#define CE_REG_PB_PILOT_EXP_INIT 0x0 + +#define CE_REG_PB_PILOT_REAL__A 0x1810039 +#define CE_REG_PB_PILOT_REAL__W 10 +#define CE_REG_PB_PILOT_REAL__M 0x3FF +#define CE_REG_PB_PILOT_REAL_INIT 0x0 + +#define CE_REG_PB_PILOT_IMAG__A 0x181003A +#define CE_REG_PB_PILOT_IMAG__W 10 +#define CE_REG_PB_PILOT_IMAG__M 0x3FF +#define CE_REG_PB_PILOT_IMAG_INIT 0x0 + +#define CE_REG_PB_SMBNR__A 0x181003B +#define CE_REG_PB_SMBNR__W 5 +#define CE_REG_PB_SMBNR__M 0x1F +#define CE_REG_PB_SMBNR_INIT 0x0 + +#define CE_REG_NE_PILOT_REQ__A 0x1810040 +#define CE_REG_NE_PILOT_REQ__W 12 +#define CE_REG_NE_PILOT_REQ__M 0xFFF +#define CE_REG_NE_PILOT_REQ_INIT 0x0 + +#define CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 +#define CE_REG_NE_PILOT_REQ_VALID__W 2 +#define CE_REG_NE_PILOT_REQ_VALID__M 0x3 +#define CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 +#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 +#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 +#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 +#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 +#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 +#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 + +#define CE_REG_NE_PILOT_DATA__A 0x1810042 +#define CE_REG_NE_PILOT_DATA__W 10 +#define CE_REG_NE_PILOT_DATA__M 0x3FF +#define CE_REG_NE_PILOT_DATA_INIT 0x0 + +#define CE_REG_NE_ERR_SELECT__A 0x1810043 +#define CE_REG_NE_ERR_SELECT__W 3 +#define CE_REG_NE_ERR_SELECT__M 0x7 +#define CE_REG_NE_ERR_SELECT_INIT 0x0 + +#define CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 +#define CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 +#define CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 + +#define CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 +#define CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 +#define CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 + +#define CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 +#define CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 +#define CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 + +#define CE_REG_NE_TD_CAL__A 0x1810044 +#define CE_REG_NE_TD_CAL__W 9 +#define CE_REG_NE_TD_CAL__M 0x1FF +#define CE_REG_NE_TD_CAL_INIT 0x0 + +#define CE_REG_NE_FD_CAL__A 0x1810045 +#define CE_REG_NE_FD_CAL__W 9 +#define CE_REG_NE_FD_CAL__M 0x1FF +#define CE_REG_NE_FD_CAL_INIT 0x0 + +#define CE_REG_NE_MIXAVG__A 0x1810046 +#define CE_REG_NE_MIXAVG__W 3 +#define CE_REG_NE_MIXAVG__M 0x7 +#define CE_REG_NE_MIXAVG_INIT 0x0 + +#define CE_REG_NE_NUPD_OFS__A 0x1810047 +#define CE_REG_NE_NUPD_OFS__W 7 +#define CE_REG_NE_NUPD_OFS__M 0x7F +#define CE_REG_NE_NUPD_OFS_INIT 0x0 + +#define CE_REG_NE_TD_POW__A 0x1810048 +#define CE_REG_NE_TD_POW__W 15 +#define CE_REG_NE_TD_POW__M 0x7FFF +#define CE_REG_NE_TD_POW_INIT 0x0 + +#define CE_REG_NE_TD_POW_EXPONENT__B 10 +#define CE_REG_NE_TD_POW_EXPONENT__W 5 +#define CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 + +#define CE_REG_NE_TD_POW_MANTISSA__B 0 +#define CE_REG_NE_TD_POW_MANTISSA__W 10 +#define CE_REG_NE_TD_POW_MANTISSA__M 0x3FF + +#define CE_REG_NE_FD_POW__A 0x1810049 +#define CE_REG_NE_FD_POW__W 15 +#define CE_REG_NE_FD_POW__M 0x7FFF +#define CE_REG_NE_FD_POW_INIT 0x0 + +#define CE_REG_NE_FD_POW_EXPONENT__B 10 +#define CE_REG_NE_FD_POW_EXPONENT__W 5 +#define CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 + +#define CE_REG_NE_FD_POW_MANTISSA__B 0 +#define CE_REG_NE_FD_POW_MANTISSA__W 10 +#define CE_REG_NE_FD_POW_MANTISSA__M 0x3FF + +#define CE_REG_NE_NEXP_AVG__A 0x181004A +#define CE_REG_NE_NEXP_AVG__W 8 +#define CE_REG_NE_NEXP_AVG__M 0xFF +#define CE_REG_NE_NEXP_AVG_INIT 0x0 + +#define CE_REG_NE_OFFSET__A 0x181004B +#define CE_REG_NE_OFFSET__W 9 +#define CE_REG_NE_OFFSET__M 0x1FF +#define CE_REG_NE_OFFSET_INIT 0x0 + +#define CE_REG_PE_NEXP_OFFS__A 0x1810050 +#define CE_REG_PE_NEXP_OFFS__W 8 +#define CE_REG_PE_NEXP_OFFS__M 0xFF +#define CE_REG_PE_NEXP_OFFS_INIT 0x0 + +#define CE_REG_PE_TIMESHIFT__A 0x1810051 +#define CE_REG_PE_TIMESHIFT__W 14 +#define CE_REG_PE_TIMESHIFT__M 0x3FFF +#define CE_REG_PE_TIMESHIFT_INIT 0x0 + +#define CE_REG_PE_DIF_REAL_L__A 0x1810052 +#define CE_REG_PE_DIF_REAL_L__W 16 +#define CE_REG_PE_DIF_REAL_L__M 0xFFFF +#define CE_REG_PE_DIF_REAL_L_INIT 0x0 + +#define CE_REG_PE_DIF_IMAG_L__A 0x1810053 +#define CE_REG_PE_DIF_IMAG_L__W 16 +#define CE_REG_PE_DIF_IMAG_L__M 0xFFFF +#define CE_REG_PE_DIF_IMAG_L_INIT 0x0 + +#define CE_REG_PE_DIF_REAL_R__A 0x1810054 +#define CE_REG_PE_DIF_REAL_R__W 16 +#define CE_REG_PE_DIF_REAL_R__M 0xFFFF +#define CE_REG_PE_DIF_REAL_R_INIT 0x0 + +#define CE_REG_PE_DIF_IMAG_R__A 0x1810055 +#define CE_REG_PE_DIF_IMAG_R__W 16 +#define CE_REG_PE_DIF_IMAG_R__M 0xFFFF +#define CE_REG_PE_DIF_IMAG_R_INIT 0x0 + +#define CE_REG_PE_ABS_REAL_L__A 0x1810056 +#define CE_REG_PE_ABS_REAL_L__W 16 +#define CE_REG_PE_ABS_REAL_L__M 0xFFFF +#define CE_REG_PE_ABS_REAL_L_INIT 0x0 + +#define CE_REG_PE_ABS_IMAG_L__A 0x1810057 +#define CE_REG_PE_ABS_IMAG_L__W 16 +#define CE_REG_PE_ABS_IMAG_L__M 0xFFFF +#define CE_REG_PE_ABS_IMAG_L_INIT 0x0 + +#define CE_REG_PE_ABS_REAL_R__A 0x1810058 +#define CE_REG_PE_ABS_REAL_R__W 16 +#define CE_REG_PE_ABS_REAL_R__M 0xFFFF +#define CE_REG_PE_ABS_REAL_R_INIT 0x0 + +#define CE_REG_PE_ABS_IMAG_R__A 0x1810059 +#define CE_REG_PE_ABS_IMAG_R__W 16 +#define CE_REG_PE_ABS_IMAG_R__M 0xFFFF +#define CE_REG_PE_ABS_IMAG_R_INIT 0x0 + +#define CE_REG_PE_ABS_EXP_L__A 0x181005A +#define CE_REG_PE_ABS_EXP_L__W 5 +#define CE_REG_PE_ABS_EXP_L__M 0x1F +#define CE_REG_PE_ABS_EXP_L_INIT 0x0 + +#define CE_REG_PE_ABS_EXP_R__A 0x181005B +#define CE_REG_PE_ABS_EXP_R__W 5 +#define CE_REG_PE_ABS_EXP_R__M 0x1F +#define CE_REG_PE_ABS_EXP_R_INIT 0x0 + +#define CE_REG_TP_UPDATE_MODE__A 0x1810060 +#define CE_REG_TP_UPDATE_MODE__W 1 +#define CE_REG_TP_UPDATE_MODE__M 0x1 +#define CE_REG_TP_UPDATE_MODE_INIT 0x0 + +#define CE_REG_TP_LMS_TAP_ON__A 0x1810061 +#define CE_REG_TP_LMS_TAP_ON__W 1 +#define CE_REG_TP_LMS_TAP_ON__M 0x1 + +#define CE_REG_TP_A0_TAP_NEW__A 0x1810064 +#define CE_REG_TP_A0_TAP_NEW__W 10 +#define CE_REG_TP_A0_TAP_NEW__M 0x3FF + +#define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 +#define CE_REG_TP_A0_TAP_NEW_VALID__W 1 +#define CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 + +#define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 +#define CE_REG_TP_A0_MU_LMS_STEP__W 5 +#define CE_REG_TP_A0_MU_LMS_STEP__M 0x1F + +#define CE_REG_TP_A0_TAP_CURR__A 0x1810067 +#define CE_REG_TP_A0_TAP_CURR__W 10 +#define CE_REG_TP_A0_TAP_CURR__M 0x3FF + +#define CE_REG_TP_A1_TAP_NEW__A 0x1810068 +#define CE_REG_TP_A1_TAP_NEW__W 10 +#define CE_REG_TP_A1_TAP_NEW__M 0x3FF + +#define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 +#define CE_REG_TP_A1_TAP_NEW_VALID__W 1 +#define CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 + +#define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A +#define CE_REG_TP_A1_MU_LMS_STEP__W 5 +#define CE_REG_TP_A1_MU_LMS_STEP__M 0x1F + +#define CE_REG_TP_A1_TAP_CURR__A 0x181006B +#define CE_REG_TP_A1_TAP_CURR__W 10 +#define CE_REG_TP_A1_TAP_CURR__M 0x3FF + +#define CE_REG_TP_DOPP_ENERGY__A 0x181006C +#define CE_REG_TP_DOPP_ENERGY__W 15 +#define CE_REG_TP_DOPP_ENERGY__M 0x7FFF +#define CE_REG_TP_DOPP_ENERGY_INIT 0x0 + +#define CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 +#define CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 +#define CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 + +#define CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 +#define CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 +#define CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF + +#define CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D +#define CE_REG_TP_DOPP_DIFF_ENERGY__W 15 +#define CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF +#define CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 + +#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 +#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 +#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 + +#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 +#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 +#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF + +#define CE_REG_TP_A0_TAP_ENERGY__A 0x181006E +#define CE_REG_TP_A0_TAP_ENERGY__W 15 +#define CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF +#define CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 + +#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 +#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 +#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 + +#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 +#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 +#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF + +#define CE_REG_TP_A1_TAP_ENERGY__A 0x181006F +#define CE_REG_TP_A1_TAP_ENERGY__W 15 +#define CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF +#define CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 + +#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 +#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 +#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 + +#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 +#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 +#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF + +#define CE_REG_TI_NEXP_OFFS__A 0x1810070 +#define CE_REG_TI_NEXP_OFFS__W 8 +#define CE_REG_TI_NEXP_OFFS__M 0xFF +#define CE_REG_TI_NEXP_OFFS_INIT 0x0 + +#define CE_REG_TI_PEAK__A 0x1810071 +#define CE_REG_TI_PEAK__W 8 +#define CE_REG_TI_PEAK__M 0xFF +#define CE_REG_TI_PEAK_INIT 0x0 + +#define CE_REG_FI_SHT_INCR__A 0x1810090 +#define CE_REG_FI_SHT_INCR__W 7 +#define CE_REG_FI_SHT_INCR__M 0x7F +#define CE_REG_FI_SHT_INCR_INIT 0x9 + +#define CE_REG_FI_EXP_NORM__A 0x1810091 +#define CE_REG_FI_EXP_NORM__W 4 +#define CE_REG_FI_EXP_NORM__M 0xF +#define CE_REG_FI_EXP_NORM_INIT 0x4 + +#define CE_REG_FI_SUPR_VAL__A 0x1810092 +#define CE_REG_FI_SUPR_VAL__W 1 +#define CE_REG_FI_SUPR_VAL__M 0x1 +#define CE_REG_FI_SUPR_VAL_INIT 0x1 + +#define CE_REG_IR_INPUTSEL__A 0x18100A0 +#define CE_REG_IR_INPUTSEL__W 1 +#define CE_REG_IR_INPUTSEL__M 0x1 +#define CE_REG_IR_INPUTSEL_INIT 0x0 + +#define CE_REG_IR_STARTPOS__A 0x18100A1 +#define CE_REG_IR_STARTPOS__W 8 +#define CE_REG_IR_STARTPOS__M 0xFF +#define CE_REG_IR_STARTPOS_INIT 0x0 + +#define CE_REG_IR_NEXP_THRES__A 0x18100A2 +#define CE_REG_IR_NEXP_THRES__W 8 +#define CE_REG_IR_NEXP_THRES__M 0xFF +#define CE_REG_IR_NEXP_THRES_INIT 0x0 + +#define CE_REG_IR_LENGTH__A 0x18100A3 +#define CE_REG_IR_LENGTH__W 4 +#define CE_REG_IR_LENGTH__M 0xF +#define CE_REG_IR_LENGTH_INIT 0x0 + +#define CE_REG_IR_FREQ__A 0x18100A4 +#define CE_REG_IR_FREQ__W 11 +#define CE_REG_IR_FREQ__M 0x7FF +#define CE_REG_IR_FREQ_INIT 0x0 + +#define CE_REG_IR_FREQINC__A 0x18100A5 +#define CE_REG_IR_FREQINC__W 11 +#define CE_REG_IR_FREQINC__M 0x7FF +#define CE_REG_IR_FREQINC_INIT 0x0 + +#define CE_REG_IR_KAISINC__A 0x18100A6 +#define CE_REG_IR_KAISINC__W 15 +#define CE_REG_IR_KAISINC__M 0x7FFF +#define CE_REG_IR_KAISINC_INIT 0x0 + +#define CE_REG_IR_CTL__A 0x18100A7 +#define CE_REG_IR_CTL__W 3 +#define CE_REG_IR_CTL__M 0x7 +#define CE_REG_IR_CTL_INIT 0x0 + +#define CE_REG_IR_REAL__A 0x18100A8 +#define CE_REG_IR_REAL__W 16 +#define CE_REG_IR_REAL__M 0xFFFF +#define CE_REG_IR_REAL_INIT 0x0 + +#define CE_REG_IR_IMAG__A 0x18100A9 +#define CE_REG_IR_IMAG__W 16 +#define CE_REG_IR_IMAG__M 0xFFFF +#define CE_REG_IR_IMAG_INIT 0x0 + +#define CE_REG_IR_INDEX__A 0x18100AA +#define CE_REG_IR_INDEX__W 12 +#define CE_REG_IR_INDEX__M 0xFFF +#define CE_REG_IR_INDEX_INIT 0x0 + +#define CE_REG_FR_TREAL00__A 0x1820010 +#define CE_REG_FR_TREAL00__W 11 +#define CE_REG_FR_TREAL00__M 0x7FF +#define CE_REG_FR_TREAL00_INIT 0x52 + +#define CE_REG_FR_TIMAG00__A 0x1820011 +#define CE_REG_FR_TIMAG00__W 11 +#define CE_REG_FR_TIMAG00__M 0x7FF +#define CE_REG_FR_TIMAG00_INIT 0x0 + +#define CE_REG_FR_TREAL01__A 0x1820012 +#define CE_REG_FR_TREAL01__W 11 +#define CE_REG_FR_TREAL01__M 0x7FF +#define CE_REG_FR_TREAL01_INIT 0x52 + +#define CE_REG_FR_TIMAG01__A 0x1820013 +#define CE_REG_FR_TIMAG01__W 11 +#define CE_REG_FR_TIMAG01__M 0x7FF +#define CE_REG_FR_TIMAG01_INIT 0x0 + +#define CE_REG_FR_TREAL02__A 0x1820014 +#define CE_REG_FR_TREAL02__W 11 +#define CE_REG_FR_TREAL02__M 0x7FF +#define CE_REG_FR_TREAL02_INIT 0x52 + +#define CE_REG_FR_TIMAG02__A 0x1820015 +#define CE_REG_FR_TIMAG02__W 11 +#define CE_REG_FR_TIMAG02__M 0x7FF +#define CE_REG_FR_TIMAG02_INIT 0x0 + +#define CE_REG_FR_TREAL03__A 0x1820016 +#define CE_REG_FR_TREAL03__W 11 +#define CE_REG_FR_TREAL03__M 0x7FF +#define CE_REG_FR_TREAL03_INIT 0x52 + +#define CE_REG_FR_TIMAG03__A 0x1820017 +#define CE_REG_FR_TIMAG03__W 11 +#define CE_REG_FR_TIMAG03__M 0x7FF +#define CE_REG_FR_TIMAG03_INIT 0x0 + +#define CE_REG_FR_TREAL04__A 0x1820018 +#define CE_REG_FR_TREAL04__W 11 +#define CE_REG_FR_TREAL04__M 0x7FF +#define CE_REG_FR_TREAL04_INIT 0x52 + +#define CE_REG_FR_TIMAG04__A 0x1820019 +#define CE_REG_FR_TIMAG04__W 11 +#define CE_REG_FR_TIMAG04__M 0x7FF +#define CE_REG_FR_TIMAG04_INIT 0x0 + +#define CE_REG_FR_TREAL05__A 0x182001A +#define CE_REG_FR_TREAL05__W 11 +#define CE_REG_FR_TREAL05__M 0x7FF +#define CE_REG_FR_TREAL05_INIT 0x52 + +#define CE_REG_FR_TIMAG05__A 0x182001B +#define CE_REG_FR_TIMAG05__W 11 +#define CE_REG_FR_TIMAG05__M 0x7FF +#define CE_REG_FR_TIMAG05_INIT 0x0 + +#define CE_REG_FR_TREAL06__A 0x182001C +#define CE_REG_FR_TREAL06__W 11 +#define CE_REG_FR_TREAL06__M 0x7FF +#define CE_REG_FR_TREAL06_INIT 0x52 + +#define CE_REG_FR_TIMAG06__A 0x182001D +#define CE_REG_FR_TIMAG06__W 11 +#define CE_REG_FR_TIMAG06__M 0x7FF +#define CE_REG_FR_TIMAG06_INIT 0x0 + +#define CE_REG_FR_TREAL07__A 0x182001E +#define CE_REG_FR_TREAL07__W 11 +#define CE_REG_FR_TREAL07__M 0x7FF +#define CE_REG_FR_TREAL07_INIT 0x52 + +#define CE_REG_FR_TIMAG07__A 0x182001F +#define CE_REG_FR_TIMAG07__W 11 +#define CE_REG_FR_TIMAG07__M 0x7FF +#define CE_REG_FR_TIMAG07_INIT 0x0 + +#define CE_REG_FR_TREAL08__A 0x1820020 +#define CE_REG_FR_TREAL08__W 11 +#define CE_REG_FR_TREAL08__M 0x7FF +#define CE_REG_FR_TREAL08_INIT 0x52 + +#define CE_REG_FR_TIMAG08__A 0x1820021 +#define CE_REG_FR_TIMAG08__W 11 +#define CE_REG_FR_TIMAG08__M 0x7FF +#define CE_REG_FR_TIMAG08_INIT 0x0 + +#define CE_REG_FR_TREAL09__A 0x1820022 +#define CE_REG_FR_TREAL09__W 11 +#define CE_REG_FR_TREAL09__M 0x7FF +#define CE_REG_FR_TREAL09_INIT 0x52 + +#define CE_REG_FR_TIMAG09__A 0x1820023 +#define CE_REG_FR_TIMAG09__W 11 +#define CE_REG_FR_TIMAG09__M 0x7FF +#define CE_REG_FR_TIMAG09_INIT 0x0 + +#define CE_REG_FR_TREAL10__A 0x1820024 +#define CE_REG_FR_TREAL10__W 11 +#define CE_REG_FR_TREAL10__M 0x7FF +#define CE_REG_FR_TREAL10_INIT 0x52 + +#define CE_REG_FR_TIMAG10__A 0x1820025 +#define CE_REG_FR_TIMAG10__W 11 +#define CE_REG_FR_TIMAG10__M 0x7FF +#define CE_REG_FR_TIMAG10_INIT 0x0 + +#define CE_REG_FR_TREAL11__A 0x1820026 +#define CE_REG_FR_TREAL11__W 11 +#define CE_REG_FR_TREAL11__M 0x7FF +#define CE_REG_FR_TREAL11_INIT 0x52 + +#define CE_REG_FR_TIMAG11__A 0x1820027 +#define CE_REG_FR_TIMAG11__W 11 +#define CE_REG_FR_TIMAG11__M 0x7FF +#define CE_REG_FR_TIMAG11_INIT 0x0 + +#define CE_REG_FR_MID_TAP__A 0x1820028 +#define CE_REG_FR_MID_TAP__W 11 +#define CE_REG_FR_MID_TAP__M 0x7FF +#define CE_REG_FR_MID_TAP_INIT 0x51 + +#define CE_REG_FR_SQS_G00__A 0x1820029 +#define CE_REG_FR_SQS_G00__W 8 +#define CE_REG_FR_SQS_G00__M 0xFF +#define CE_REG_FR_SQS_G00_INIT 0xB + +#define CE_REG_FR_SQS_G01__A 0x182002A +#define CE_REG_FR_SQS_G01__W 8 +#define CE_REG_FR_SQS_G01__M 0xFF +#define CE_REG_FR_SQS_G01_INIT 0xB + +#define CE_REG_FR_SQS_G02__A 0x182002B +#define CE_REG_FR_SQS_G02__W 8 +#define CE_REG_FR_SQS_G02__M 0xFF +#define CE_REG_FR_SQS_G02_INIT 0xB + +#define CE_REG_FR_SQS_G03__A 0x182002C +#define CE_REG_FR_SQS_G03__W 8 +#define CE_REG_FR_SQS_G03__M 0xFF +#define CE_REG_FR_SQS_G03_INIT 0xB + +#define CE_REG_FR_SQS_G04__A 0x182002D +#define CE_REG_FR_SQS_G04__W 8 +#define CE_REG_FR_SQS_G04__M 0xFF +#define CE_REG_FR_SQS_G04_INIT 0xB + +#define CE_REG_FR_SQS_G05__A 0x182002E +#define CE_REG_FR_SQS_G05__W 8 +#define CE_REG_FR_SQS_G05__M 0xFF +#define CE_REG_FR_SQS_G05_INIT 0xB + +#define CE_REG_FR_SQS_G06__A 0x182002F +#define CE_REG_FR_SQS_G06__W 8 +#define CE_REG_FR_SQS_G06__M 0xFF +#define CE_REG_FR_SQS_G06_INIT 0xB + +#define CE_REG_FR_SQS_G07__A 0x1820030 +#define CE_REG_FR_SQS_G07__W 8 +#define CE_REG_FR_SQS_G07__M 0xFF +#define CE_REG_FR_SQS_G07_INIT 0xB + +#define CE_REG_FR_SQS_G08__A 0x1820031 +#define CE_REG_FR_SQS_G08__W 8 +#define CE_REG_FR_SQS_G08__M 0xFF +#define CE_REG_FR_SQS_G08_INIT 0xB + +#define CE_REG_FR_SQS_G09__A 0x1820032 +#define CE_REG_FR_SQS_G09__W 8 +#define CE_REG_FR_SQS_G09__M 0xFF +#define CE_REG_FR_SQS_G09_INIT 0xB + +#define CE_REG_FR_SQS_G10__A 0x1820033 +#define CE_REG_FR_SQS_G10__W 8 +#define CE_REG_FR_SQS_G10__M 0xFF +#define CE_REG_FR_SQS_G10_INIT 0xB + +#define CE_REG_FR_SQS_G11__A 0x1820034 +#define CE_REG_FR_SQS_G11__W 8 +#define CE_REG_FR_SQS_G11__M 0xFF +#define CE_REG_FR_SQS_G11_INIT 0xB + +#define CE_REG_FR_SQS_G12__A 0x1820035 +#define CE_REG_FR_SQS_G12__W 8 +#define CE_REG_FR_SQS_G12__M 0xFF +#define CE_REG_FR_SQS_G12_INIT 0x5 + +#define CE_REG_FR_RIO_G00__A 0x1820036 +#define CE_REG_FR_RIO_G00__W 9 +#define CE_REG_FR_RIO_G00__M 0x1FF +#define CE_REG_FR_RIO_G00_INIT 0x1FF + +#define CE_REG_FR_RIO_G01__A 0x1820037 +#define CE_REG_FR_RIO_G01__W 9 +#define CE_REG_FR_RIO_G01__M 0x1FF +#define CE_REG_FR_RIO_G01_INIT 0x190 + +#define CE_REG_FR_RIO_G02__A 0x1820038 +#define CE_REG_FR_RIO_G02__W 9 +#define CE_REG_FR_RIO_G02__M 0x1FF +#define CE_REG_FR_RIO_G02_INIT 0x10B + +#define CE_REG_FR_RIO_G03__A 0x1820039 +#define CE_REG_FR_RIO_G03__W 9 +#define CE_REG_FR_RIO_G03__M 0x1FF +#define CE_REG_FR_RIO_G03_INIT 0xC8 + +#define CE_REG_FR_RIO_G04__A 0x182003A +#define CE_REG_FR_RIO_G04__W 9 +#define CE_REG_FR_RIO_G04__M 0x1FF +#define CE_REG_FR_RIO_G04_INIT 0xA0 + +#define CE_REG_FR_RIO_G05__A 0x182003B +#define CE_REG_FR_RIO_G05__W 9 +#define CE_REG_FR_RIO_G05__M 0x1FF +#define CE_REG_FR_RIO_G05_INIT 0x85 + +#define CE_REG_FR_RIO_G06__A 0x182003C +#define CE_REG_FR_RIO_G06__W 9 +#define CE_REG_FR_RIO_G06__M 0x1FF +#define CE_REG_FR_RIO_G06_INIT 0x72 + +#define CE_REG_FR_RIO_G07__A 0x182003D +#define CE_REG_FR_RIO_G07__W 9 +#define CE_REG_FR_RIO_G07__M 0x1FF +#define CE_REG_FR_RIO_G07_INIT 0x64 + +#define CE_REG_FR_RIO_G08__A 0x182003E +#define CE_REG_FR_RIO_G08__W 9 +#define CE_REG_FR_RIO_G08__M 0x1FF +#define CE_REG_FR_RIO_G08_INIT 0x59 + +#define CE_REG_FR_RIO_G09__A 0x182003F +#define CE_REG_FR_RIO_G09__W 9 +#define CE_REG_FR_RIO_G09__M 0x1FF +#define CE_REG_FR_RIO_G09_INIT 0x50 + +#define CE_REG_FR_RIO_G10__A 0x1820040 +#define CE_REG_FR_RIO_G10__W 9 +#define CE_REG_FR_RIO_G10__M 0x1FF +#define CE_REG_FR_RIO_G10_INIT 0x49 + +#define CE_REG_FR_MODE__A 0x1820041 +#define CE_REG_FR_MODE__W 6 +#define CE_REG_FR_MODE__M 0x3F + +#define CE_REG_FR_MODE_UPDATE_ENABLE__B 0 +#define CE_REG_FR_MODE_UPDATE_ENABLE__W 1 +#define CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 + +#define CE_REG_FR_MODE_ERROR_SHIFT__B 1 +#define CE_REG_FR_MODE_ERROR_SHIFT__W 1 +#define CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 + +#define CE_REG_FR_MODE_NEXP_UPDATE__B 2 +#define CE_REG_FR_MODE_NEXP_UPDATE__W 1 +#define CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 + +#define CE_REG_FR_MODE_MANUAL_SHIFT__B 3 +#define CE_REG_FR_MODE_MANUAL_SHIFT__W 1 +#define CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 + +#define CE_REG_FR_MODE_SQUASH_MODE__B 4 +#define CE_REG_FR_MODE_SQUASH_MODE__W 1 +#define CE_REG_FR_MODE_SQUASH_MODE__M 0x10 + +#define CE_REG_FR_MODE_UPDATE_MODE__B 5 +#define CE_REG_FR_MODE_UPDATE_MODE__W 1 +#define CE_REG_FR_MODE_UPDATE_MODE__M 0x20 +#define CE_REG_FR_MODE_INIT 0x3E + +#define CE_REG_FR_SQS_TRH__A 0x1820042 +#define CE_REG_FR_SQS_TRH__W 8 +#define CE_REG_FR_SQS_TRH__M 0xFF +#define CE_REG_FR_SQS_TRH_INIT 0x80 + +#define CE_REG_FR_RIO_GAIN__A 0x1820043 +#define CE_REG_FR_RIO_GAIN__W 3 +#define CE_REG_FR_RIO_GAIN__M 0x7 +#define CE_REG_FR_RIO_GAIN_INIT 0x2 + +#define CE_REG_FR_BYPASS__A 0x1820044 +#define CE_REG_FR_BYPASS__W 10 +#define CE_REG_FR_BYPASS__M 0x3FF + +#define CE_REG_FR_BYPASS_RUN_IN__B 0 +#define CE_REG_FR_BYPASS_RUN_IN__W 4 +#define CE_REG_FR_BYPASS_RUN_IN__M 0xF + +#define CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 +#define CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 +#define CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 + +#define CE_REG_FR_BYPASS_TOTAL__B 9 +#define CE_REG_FR_BYPASS_TOTAL__W 1 +#define CE_REG_FR_BYPASS_TOTAL__M 0x200 +#define CE_REG_FR_BYPASS_INIT 0x13B + +#define CE_REG_FR_PM_SET__A 0x1820045 +#define CE_REG_FR_PM_SET__W 4 +#define CE_REG_FR_PM_SET__M 0xF +#define CE_REG_FR_PM_SET_INIT 0x4 + +#define CE_REG_FR_ERR_SH__A 0x1820046 +#define CE_REG_FR_ERR_SH__W 4 +#define CE_REG_FR_ERR_SH__M 0xF +#define CE_REG_FR_ERR_SH_INIT 0x4 + +#define CE_REG_FR_MAN_SH__A 0x1820047 +#define CE_REG_FR_MAN_SH__W 4 +#define CE_REG_FR_MAN_SH__M 0xF +#define CE_REG_FR_MAN_SH_INIT 0x7 + +#define CE_REG_FR_TAP_SH__A 0x1820048 +#define CE_REG_FR_TAP_SH__W 3 +#define CE_REG_FR_TAP_SH__M 0x7 +#define CE_REG_FR_TAP_SH_INIT 0x3 + +#define CE_REG_FR_CLIP__A 0x1820049 +#define CE_REG_FR_CLIP__W 9 +#define CE_REG_FR_CLIP__M 0x1FF +#define CE_REG_FR_CLIP_INIT 0x49 + +#define CE_PB_RAM__A 0x1830000 + +#define CE_NE_RAM__A 0x1840000 + +#define EQ_SID 0xE + +#define EQ_COMM_EXEC__A 0x1C00000 +#define EQ_COMM_EXEC__W 3 +#define EQ_COMM_EXEC__M 0x7 +#define EQ_COMM_EXEC_CTL__B 0 +#define EQ_COMM_EXEC_CTL__W 3 +#define EQ_COMM_EXEC_CTL__M 0x7 +#define EQ_COMM_EXEC_CTL_STOP 0x0 +#define EQ_COMM_EXEC_CTL_ACTIVE 0x1 +#define EQ_COMM_EXEC_CTL_HOLD 0x2 +#define EQ_COMM_EXEC_CTL_STEP 0x3 +#define EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define EQ_COMM_STATE__A 0x1C00001 +#define EQ_COMM_STATE__W 16 +#define EQ_COMM_STATE__M 0xFFFF +#define EQ_COMM_MB__A 0x1C00002 +#define EQ_COMM_MB__W 16 +#define EQ_COMM_MB__M 0xFFFF +#define EQ_COMM_SERVICE0__A 0x1C00003 +#define EQ_COMM_SERVICE0__W 16 +#define EQ_COMM_SERVICE0__M 0xFFFF +#define EQ_COMM_SERVICE1__A 0x1C00004 +#define EQ_COMM_SERVICE1__W 16 +#define EQ_COMM_SERVICE1__M 0xFFFF +#define EQ_COMM_INT_STA__A 0x1C00007 +#define EQ_COMM_INT_STA__W 16 +#define EQ_COMM_INT_STA__M 0xFFFF +#define EQ_COMM_INT_MSK__A 0x1C00008 +#define EQ_COMM_INT_MSK__W 16 +#define EQ_COMM_INT_MSK__M 0xFFFF + +#define EQ_REG_COMM_EXEC__A 0x1C10000 +#define EQ_REG_COMM_EXEC__W 3 +#define EQ_REG_COMM_EXEC__M 0x7 +#define EQ_REG_COMM_EXEC_CTL__B 0 +#define EQ_REG_COMM_EXEC_CTL__W 3 +#define EQ_REG_COMM_EXEC_CTL__M 0x7 +#define EQ_REG_COMM_EXEC_CTL_STOP 0x0 +#define EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EQ_REG_COMM_EXEC_CTL_HOLD 0x2 +#define EQ_REG_COMM_EXEC_CTL_STEP 0x3 + +#define EQ_REG_COMM_STATE__A 0x1C10001 +#define EQ_REG_COMM_STATE__W 4 +#define EQ_REG_COMM_STATE__M 0xF + +#define EQ_REG_COMM_MB__A 0x1C10002 +#define EQ_REG_COMM_MB__W 6 +#define EQ_REG_COMM_MB__M 0x3F +#define EQ_REG_COMM_MB_CTR__B 0 +#define EQ_REG_COMM_MB_CTR__W 1 +#define EQ_REG_COMM_MB_CTR__M 0x1 +#define EQ_REG_COMM_MB_CTR_OFF 0x0 +#define EQ_REG_COMM_MB_CTR_ON 0x1 +#define EQ_REG_COMM_MB_OBS__B 1 +#define EQ_REG_COMM_MB_OBS__W 1 +#define EQ_REG_COMM_MB_OBS__M 0x2 +#define EQ_REG_COMM_MB_OBS_OFF 0x0 +#define EQ_REG_COMM_MB_OBS_ON 0x2 +#define EQ_REG_COMM_MB_CTR_MUX__B 2 +#define EQ_REG_COMM_MB_CTR_MUX__W 2 +#define EQ_REG_COMM_MB_CTR_MUX__M 0xC +#define EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 +#define EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 +#define EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 +#define EQ_REG_COMM_MB_OBS_MUX__B 4 +#define EQ_REG_COMM_MB_OBS_MUX__W 2 +#define EQ_REG_COMM_MB_OBS_MUX__M 0x30 +#define EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 +#define EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 +#define EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 +#define EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 + +#define EQ_REG_COMM_SERVICE0__A 0x1C10003 +#define EQ_REG_COMM_SERVICE0__W 10 +#define EQ_REG_COMM_SERVICE0__M 0x3FF + +#define EQ_REG_COMM_SERVICE1__A 0x1C10004 +#define EQ_REG_COMM_SERVICE1__W 11 +#define EQ_REG_COMM_SERVICE1__M 0x7FF + +#define EQ_REG_COMM_INT_STA__A 0x1C10007 +#define EQ_REG_COMM_INT_STA__W 2 +#define EQ_REG_COMM_INT_STA__M 0x3 +#define EQ_REG_COMM_INT_STA_TPS_RDY__B 0 +#define EQ_REG_COMM_INT_STA_TPS_RDY__W 1 +#define EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 +#define EQ_REG_COMM_INT_STA_ERR_RDY__B 1 +#define EQ_REG_COMM_INT_STA_ERR_RDY__W 1 +#define EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 + +#define EQ_REG_COMM_INT_MSK__A 0x1C10008 +#define EQ_REG_COMM_INT_MSK__W 2 +#define EQ_REG_COMM_INT_MSK__M 0x3 +#define EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 +#define EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 +#define EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 +#define EQ_REG_COMM_INT_MSK_MER_RDY__B 1 +#define EQ_REG_COMM_INT_MSK_MER_RDY__W 1 +#define EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 + +#define EQ_REG_IS_MODE__A 0x1C10014 +#define EQ_REG_IS_MODE__W 4 +#define EQ_REG_IS_MODE__M 0xF +#define EQ_REG_IS_MODE_INIT 0x0 + +#define EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 +#define EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 +#define EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 +#define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 +#define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 + +#define EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 +#define EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 +#define EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 +#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 +#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 + +#define EQ_REG_IS_GAIN_MAN__A 0x1C10015 +#define EQ_REG_IS_GAIN_MAN__W 10 +#define EQ_REG_IS_GAIN_MAN__M 0x3FF +#define EQ_REG_IS_GAIN_MAN_INIT 0x0 + +#define EQ_REG_IS_GAIN_EXP__A 0x1C10016 +#define EQ_REG_IS_GAIN_EXP__W 5 +#define EQ_REG_IS_GAIN_EXP__M 0x1F +#define EQ_REG_IS_GAIN_EXP_INIT 0x0 + +#define EQ_REG_IS_CLIP_EXP__A 0x1C10017 +#define EQ_REG_IS_CLIP_EXP__W 5 +#define EQ_REG_IS_CLIP_EXP__M 0x1F +#define EQ_REG_IS_CLIP_EXP_INIT 0x0 + +#define EQ_REG_DV_MODE__A 0x1C1001E +#define EQ_REG_DV_MODE__W 4 +#define EQ_REG_DV_MODE__M 0xF +#define EQ_REG_DV_MODE_INIT 0x0 + +#define EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 +#define EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 +#define EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 +#define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 +#define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 + +#define EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 +#define EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 +#define EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 +#define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 +#define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 + +#define EQ_REG_DV_MODE_CLP_REA_ENA__B 2 +#define EQ_REG_DV_MODE_CLP_REA_ENA__W 1 +#define EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 +#define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 +#define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 + +#define EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 +#define EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 +#define EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 +#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 +#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 + +#define EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F +#define EQ_REG_DV_POS_CLIP_DAT__W 16 +#define EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF + +#define EQ_REG_SN_MODE__A 0x1C10028 +#define EQ_REG_SN_MODE__W 8 +#define EQ_REG_SN_MODE__M 0xFF +#define EQ_REG_SN_MODE_INIT 0x0 + +#define EQ_REG_SN_MODE_MODE_0__B 0 +#define EQ_REG_SN_MODE_MODE_0__W 1 +#define EQ_REG_SN_MODE_MODE_0__M 0x1 +#define EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 + +#define EQ_REG_SN_MODE_MODE_1__B 1 +#define EQ_REG_SN_MODE_MODE_1__W 1 +#define EQ_REG_SN_MODE_MODE_1__M 0x2 +#define EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 + +#define EQ_REG_SN_MODE_MODE_2__B 2 +#define EQ_REG_SN_MODE_MODE_2__W 1 +#define EQ_REG_SN_MODE_MODE_2__M 0x4 +#define EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 + +#define EQ_REG_SN_MODE_MODE_3__B 3 +#define EQ_REG_SN_MODE_MODE_3__W 1 +#define EQ_REG_SN_MODE_MODE_3__M 0x8 +#define EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 + +#define EQ_REG_SN_MODE_MODE_4__B 4 +#define EQ_REG_SN_MODE_MODE_4__W 1 +#define EQ_REG_SN_MODE_MODE_4__M 0x10 +#define EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 + +#define EQ_REG_SN_MODE_MODE_5__B 5 +#define EQ_REG_SN_MODE_MODE_5__W 1 +#define EQ_REG_SN_MODE_MODE_5__M 0x20 +#define EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 +#define EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 + +#define EQ_REG_SN_MODE_MODE_6__B 6 +#define EQ_REG_SN_MODE_MODE_6__W 1 +#define EQ_REG_SN_MODE_MODE_6__M 0x40 +#define EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 +#define EQ_REG_SN_MODE_MODE_6_STATIC 0x40 + +#define EQ_REG_SN_MODE_MODE_7__B 7 +#define EQ_REG_SN_MODE_MODE_7__W 1 +#define EQ_REG_SN_MODE_MODE_7__M 0x80 +#define EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 +#define EQ_REG_SN_MODE_MODE_7_STATIC 0x80 + +#define EQ_REG_SN_PFIX__A 0x1C10029 +#define EQ_REG_SN_PFIX__W 8 +#define EQ_REG_SN_PFIX__M 0xFF +#define EQ_REG_SN_PFIX_INIT 0x0 + +#define EQ_REG_SN_CEGAIN__A 0x1C1002A +#define EQ_REG_SN_CEGAIN__W 8 +#define EQ_REG_SN_CEGAIN__M 0xFF +#define EQ_REG_SN_CEGAIN_INIT 0x0 + +#define EQ_REG_SN_OFFSET__A 0x1C1002B +#define EQ_REG_SN_OFFSET__W 6 +#define EQ_REG_SN_OFFSET__M 0x3F +#define EQ_REG_SN_OFFSET_INIT 0x0 + +#define EQ_REG_SN_NULLIFY__A 0x1C1002C +#define EQ_REG_SN_NULLIFY__W 6 +#define EQ_REG_SN_NULLIFY__M 0x3F +#define EQ_REG_SN_NULLIFY_INIT 0x0 + +#define EQ_REG_SN_SQUASH__A 0x1C1002D +#define EQ_REG_SN_SQUASH__W 10 +#define EQ_REG_SN_SQUASH__M 0x3FF +#define EQ_REG_SN_SQUASH_INIT 0x0 + +#define EQ_REG_SN_SQUASH_MAN__B 0 +#define EQ_REG_SN_SQUASH_MAN__W 6 +#define EQ_REG_SN_SQUASH_MAN__M 0x3F + +#define EQ_REG_SN_SQUASH_EXP__B 6 +#define EQ_REG_SN_SQUASH_EXP__W 4 +#define EQ_REG_SN_SQUASH_EXP__M 0x3C0 + +#define EQ_REG_RC_SEL_CAR__A 0x1C10032 +#define EQ_REG_RC_SEL_CAR__W 6 +#define EQ_REG_RC_SEL_CAR__M 0x3F +#define EQ_REG_RC_SEL_CAR_INIT 0x0 +#define EQ_REG_RC_SEL_CAR_DIV__B 0 +#define EQ_REG_RC_SEL_CAR_DIV__W 1 +#define EQ_REG_RC_SEL_CAR_DIV__M 0x1 +#define EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 +#define EQ_REG_RC_SEL_CAR_DIV_ON 0x1 + +#define EQ_REG_RC_SEL_CAR_PASS__B 1 +#define EQ_REG_RC_SEL_CAR_PASS__W 2 +#define EQ_REG_RC_SEL_CAR_PASS__M 0x6 +#define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 +#define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 +#define EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 +#define EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 + +#define EQ_REG_RC_SEL_CAR_LOCAL__B 3 +#define EQ_REG_RC_SEL_CAR_LOCAL__W 2 +#define EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 +#define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 +#define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 +#define EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 +#define EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 + +#define EQ_REG_RC_SEL_CAR_MEAS__B 5 +#define EQ_REG_RC_SEL_CAR_MEAS__W 1 +#define EQ_REG_RC_SEL_CAR_MEAS__M 0x20 +#define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 +#define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 + +#define EQ_REG_RC_STS__A 0x1C10033 +#define EQ_REG_RC_STS__W 12 +#define EQ_REG_RC_STS__M 0xFFF + +#define EQ_REG_RC_STS_DIFF__B 0 +#define EQ_REG_RC_STS_DIFF__W 9 +#define EQ_REG_RC_STS_DIFF__M 0x1FF + +#define EQ_REG_RC_STS_FIRST__B 9 +#define EQ_REG_RC_STS_FIRST__W 1 +#define EQ_REG_RC_STS_FIRST__M 0x200 +#define EQ_REG_RC_STS_FIRST_A_CE 0x0 +#define EQ_REG_RC_STS_FIRST_B_DRI 0x200 + +#define EQ_REG_RC_STS_SELEC__B 10 +#define EQ_REG_RC_STS_SELEC__W 1 +#define EQ_REG_RC_STS_SELEC__M 0x400 +#define EQ_REG_RC_STS_SELEC_A_CE 0x0 +#define EQ_REG_RC_STS_SELEC_B_DRI 0x400 + +#define EQ_REG_RC_STS_OVERFLOW__B 11 +#define EQ_REG_RC_STS_OVERFLOW__W 1 +#define EQ_REG_RC_STS_OVERFLOW__M 0x800 +#define EQ_REG_RC_STS_OVERFLOW_NO 0x0 +#define EQ_REG_RC_STS_OVERFLOW_YES 0x800 + +#define EQ_REG_OT_CONST__A 0x1C10046 +#define EQ_REG_OT_CONST__W 2 +#define EQ_REG_OT_CONST__M 0x3 +#define EQ_REG_OT_CONST_INIT 0x0 + +#define EQ_REG_OT_ALPHA__A 0x1C10047 +#define EQ_REG_OT_ALPHA__W 2 +#define EQ_REG_OT_ALPHA__M 0x3 +#define EQ_REG_OT_ALPHA_INIT 0x0 + +#define EQ_REG_OT_QNT_THRES0__A 0x1C10048 +#define EQ_REG_OT_QNT_THRES0__W 5 +#define EQ_REG_OT_QNT_THRES0__M 0x1F +#define EQ_REG_OT_QNT_THRES0_INIT 0x0 + +#define EQ_REG_OT_QNT_THRES1__A 0x1C10049 +#define EQ_REG_OT_QNT_THRES1__W 5 +#define EQ_REG_OT_QNT_THRES1__M 0x1F +#define EQ_REG_OT_QNT_THRES1_INIT 0x0 + +#define EQ_REG_OT_CSI_STEP__A 0x1C1004A +#define EQ_REG_OT_CSI_STEP__W 4 +#define EQ_REG_OT_CSI_STEP__M 0xF +#define EQ_REG_OT_CSI_STEP_INIT 0x0 + +#define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B +#define EQ_REG_OT_CSI_OFFSET__W 7 +#define EQ_REG_OT_CSI_OFFSET__M 0x7F +#define EQ_REG_OT_CSI_OFFSET_INIT 0x0 + +#define EQ_REG_TD_TPS_INIT__A 0x1C10050 +#define EQ_REG_TD_TPS_INIT__W 1 +#define EQ_REG_TD_TPS_INIT__M 0x1 +#define EQ_REG_TD_TPS_INIT_INIT 0x0 +#define EQ_REG_TD_TPS_INIT_POS 0x0 +#define EQ_REG_TD_TPS_INIT_NEG 0x1 + +#define EQ_REG_TD_TPS_SYNC__A 0x1C10051 +#define EQ_REG_TD_TPS_SYNC__W 16 +#define EQ_REG_TD_TPS_SYNC__M 0xFFFF +#define EQ_REG_TD_TPS_SYNC_INIT 0x0 +#define EQ_REG_TD_TPS_SYNC_ODD 0x35EE +#define EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 + +#define EQ_REG_TD_TPS_LEN__A 0x1C10052 +#define EQ_REG_TD_TPS_LEN__W 6 +#define EQ_REG_TD_TPS_LEN__M 0x3F +#define EQ_REG_TD_TPS_LEN_INIT 0x0 +#define EQ_REG_TD_TPS_LEN_DEF 0x17 +#define EQ_REG_TD_TPS_LEN_ID_SUP 0x1F + +#define EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 +#define EQ_REG_TD_TPS_FRM_NMB__W 2 +#define EQ_REG_TD_TPS_FRM_NMB__M 0x3 +#define EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 +#define EQ_REG_TD_TPS_FRM_NMB_1 0x0 +#define EQ_REG_TD_TPS_FRM_NMB_2 0x1 +#define EQ_REG_TD_TPS_FRM_NMB_3 0x2 +#define EQ_REG_TD_TPS_FRM_NMB_4 0x3 + +#define EQ_REG_TD_TPS_CONST__A 0x1C10054 +#define EQ_REG_TD_TPS_CONST__W 2 +#define EQ_REG_TD_TPS_CONST__M 0x3 +#define EQ_REG_TD_TPS_CONST_INIT 0x0 +#define EQ_REG_TD_TPS_CONST_QPSK 0x0 +#define EQ_REG_TD_TPS_CONST_16QAM 0x1 +#define EQ_REG_TD_TPS_CONST_64QAM 0x2 + +#define EQ_REG_TD_TPS_HINFO__A 0x1C10055 +#define EQ_REG_TD_TPS_HINFO__W 3 +#define EQ_REG_TD_TPS_HINFO__M 0x7 +#define EQ_REG_TD_TPS_HINFO_INIT 0x0 +#define EQ_REG_TD_TPS_HINFO_NH 0x0 +#define EQ_REG_TD_TPS_HINFO_H1 0x1 +#define EQ_REG_TD_TPS_HINFO_H2 0x2 +#define EQ_REG_TD_TPS_HINFO_H4 0x3 + +#define EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 +#define EQ_REG_TD_TPS_CODE_HP__W 3 +#define EQ_REG_TD_TPS_CODE_HP__M 0x7 +#define EQ_REG_TD_TPS_CODE_HP_INIT 0x0 +#define EQ_REG_TD_TPS_CODE_HP_1_2 0x0 +#define EQ_REG_TD_TPS_CODE_HP_2_3 0x1 +#define EQ_REG_TD_TPS_CODE_HP_3_4 0x2 +#define EQ_REG_TD_TPS_CODE_HP_5_6 0x3 +#define EQ_REG_TD_TPS_CODE_HP_7_8 0x4 + +#define EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 +#define EQ_REG_TD_TPS_CODE_LP__W 3 +#define EQ_REG_TD_TPS_CODE_LP__M 0x7 +#define EQ_REG_TD_TPS_CODE_LP_INIT 0x0 +#define EQ_REG_TD_TPS_CODE_LP_1_2 0x0 +#define EQ_REG_TD_TPS_CODE_LP_2_3 0x1 +#define EQ_REG_TD_TPS_CODE_LP_3_4 0x2 +#define EQ_REG_TD_TPS_CODE_LP_5_6 0x3 +#define EQ_REG_TD_TPS_CODE_LP_7_8 0x4 + +#define EQ_REG_TD_TPS_GUARD__A 0x1C10058 +#define EQ_REG_TD_TPS_GUARD__W 2 +#define EQ_REG_TD_TPS_GUARD__M 0x3 +#define EQ_REG_TD_TPS_GUARD_INIT 0x0 +#define EQ_REG_TD_TPS_GUARD_32 0x0 +#define EQ_REG_TD_TPS_GUARD_16 0x1 +#define EQ_REG_TD_TPS_GUARD_08 0x2 +#define EQ_REG_TD_TPS_GUARD_04 0x3 + +#define EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 +#define EQ_REG_TD_TPS_TR_MODE__W 2 +#define EQ_REG_TD_TPS_TR_MODE__M 0x3 +#define EQ_REG_TD_TPS_TR_MODE_INIT 0x0 +#define EQ_REG_TD_TPS_TR_MODE_2K 0x0 +#define EQ_REG_TD_TPS_TR_MODE_8K 0x1 + +#define EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A +#define EQ_REG_TD_TPS_CELL_ID_HI__W 8 +#define EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF +#define EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 + +#define EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B +#define EQ_REG_TD_TPS_CELL_ID_LO__W 8 +#define EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF +#define EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 + +#define EQ_REG_TD_TPS_RSV__A 0x1C1005C +#define EQ_REG_TD_TPS_RSV__W 6 +#define EQ_REG_TD_TPS_RSV__M 0x3F +#define EQ_REG_TD_TPS_RSV_INIT 0x0 + +#define EQ_REG_TD_TPS_BCH__A 0x1C1005D +#define EQ_REG_TD_TPS_BCH__W 14 +#define EQ_REG_TD_TPS_BCH__M 0x3FFF +#define EQ_REG_TD_TPS_BCH_INIT 0x0 + +#define EQ_REG_TD_SQR_ERR_I__A 0x1C1005E +#define EQ_REG_TD_SQR_ERR_I__W 16 +#define EQ_REG_TD_SQR_ERR_I__M 0xFFFF +#define EQ_REG_TD_SQR_ERR_I_INIT 0x0 + +#define EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F +#define EQ_REG_TD_SQR_ERR_Q__W 16 +#define EQ_REG_TD_SQR_ERR_Q__M 0xFFFF +#define EQ_REG_TD_SQR_ERR_Q_INIT 0x0 + +#define EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 +#define EQ_REG_TD_SQR_ERR_EXP__W 4 +#define EQ_REG_TD_SQR_ERR_EXP__M 0xF +#define EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 + +#define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 +#define EQ_REG_TD_REQ_SMB_CNT__W 16 +#define EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF +#define EQ_REG_TD_REQ_SMB_CNT_INIT 0x0 + +#define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 +#define EQ_REG_TD_TPS_PWR_OFS__W 16 +#define EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF +#define EQ_REG_TD_TPS_PWR_OFS_INIT 0x0 + +#define EC_COMM_EXEC__A 0x2000000 +#define EC_COMM_EXEC__W 3 +#define EC_COMM_EXEC__M 0x7 +#define EC_COMM_EXEC_CTL__B 0 +#define EC_COMM_EXEC_CTL__W 3 +#define EC_COMM_EXEC_CTL__M 0x7 +#define EC_COMM_EXEC_CTL_STOP 0x0 +#define EC_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_COMM_EXEC_CTL_HOLD 0x2 +#define EC_COMM_EXEC_CTL_STEP 0x3 +#define EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define EC_COMM_STATE__A 0x2000001 +#define EC_COMM_STATE__W 16 +#define EC_COMM_STATE__M 0xFFFF +#define EC_COMM_MB__A 0x2000002 +#define EC_COMM_MB__W 16 +#define EC_COMM_MB__M 0xFFFF +#define EC_COMM_SERVICE0__A 0x2000003 +#define EC_COMM_SERVICE0__W 16 +#define EC_COMM_SERVICE0__M 0xFFFF +#define EC_COMM_SERVICE1__A 0x2000004 +#define EC_COMM_SERVICE1__W 16 +#define EC_COMM_SERVICE1__M 0xFFFF +#define EC_COMM_INT_STA__A 0x2000007 +#define EC_COMM_INT_STA__W 16 +#define EC_COMM_INT_STA__M 0xFFFF +#define EC_COMM_INT_MSK__A 0x2000008 +#define EC_COMM_INT_MSK__W 16 +#define EC_COMM_INT_MSK__M 0xFFFF + +#define EC_SB_SID 0x16 + +#define EC_SB_REG_COMM_EXEC__A 0x2010000 +#define EC_SB_REG_COMM_EXEC__W 3 +#define EC_SB_REG_COMM_EXEC__M 0x7 +#define EC_SB_REG_COMM_EXEC_CTL__B 0 +#define EC_SB_REG_COMM_EXEC_CTL__W 3 +#define EC_SB_REG_COMM_EXEC_CTL__M 0x7 +#define EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 +#define EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define EC_SB_REG_COMM_STATE__A 0x2010001 +#define EC_SB_REG_COMM_STATE__W 4 +#define EC_SB_REG_COMM_STATE__M 0xF +#define EC_SB_REG_COMM_MB__A 0x2010002 +#define EC_SB_REG_COMM_MB__W 2 +#define EC_SB_REG_COMM_MB__M 0x3 +#define EC_SB_REG_COMM_MB_CTR__B 0 +#define EC_SB_REG_COMM_MB_CTR__W 1 +#define EC_SB_REG_COMM_MB_CTR__M 0x1 +#define EC_SB_REG_COMM_MB_CTR_OFF 0x0 +#define EC_SB_REG_COMM_MB_CTR_ON 0x1 +#define EC_SB_REG_COMM_MB_OBS__B 1 +#define EC_SB_REG_COMM_MB_OBS__W 1 +#define EC_SB_REG_COMM_MB_OBS__M 0x2 +#define EC_SB_REG_COMM_MB_OBS_OFF 0x0 +#define EC_SB_REG_COMM_MB_OBS_ON 0x2 + +#define EC_SB_REG_TR_MODE__A 0x2010010 +#define EC_SB_REG_TR_MODE__W 1 +#define EC_SB_REG_TR_MODE__M 0x1 +#define EC_SB_REG_TR_MODE_INIT 0x0 +#define EC_SB_REG_TR_MODE_8K 0x0 +#define EC_SB_REG_TR_MODE_2K 0x1 + +#define EC_SB_REG_CONST__A 0x2010011 +#define EC_SB_REG_CONST__W 2 +#define EC_SB_REG_CONST__M 0x3 +#define EC_SB_REG_CONST_INIT 0x2 +#define EC_SB_REG_CONST_QPSK 0x0 +#define EC_SB_REG_CONST_16QAM 0x1 +#define EC_SB_REG_CONST_64QAM 0x2 + +#define EC_SB_REG_ALPHA__A 0x2010012 +#define EC_SB_REG_ALPHA__W 3 +#define EC_SB_REG_ALPHA__M 0x7 + +#define EC_SB_REG_ALPHA_INIT 0x0 + +#define EC_SB_REG_ALPHA_NH 0x0 + +#define EC_SB_REG_ALPHA_H1 0x1 + +#define EC_SB_REG_ALPHA_H2 0x2 + +#define EC_SB_REG_ALPHA_H4 0x3 + +#define EC_SB_REG_PRIOR__A 0x2010013 +#define EC_SB_REG_PRIOR__W 1 +#define EC_SB_REG_PRIOR__M 0x1 +#define EC_SB_REG_PRIOR_INIT 0x0 +#define EC_SB_REG_PRIOR_HI 0x0 +#define EC_SB_REG_PRIOR_LO 0x1 + +#define EC_SB_REG_CSI_HI__A 0x2010014 +#define EC_SB_REG_CSI_HI__W 5 +#define EC_SB_REG_CSI_HI__M 0x1F +#define EC_SB_REG_CSI_HI_INIT 0x1F +#define EC_SB_REG_CSI_HI_MAX 0x1F +#define EC_SB_REG_CSI_HI_MIN 0x0 +#define EC_SB_REG_CSI_HI_TAG 0x0 + +#define EC_SB_REG_CSI_LO__A 0x2010015 +#define EC_SB_REG_CSI_LO__W 5 +#define EC_SB_REG_CSI_LO__M 0x1F +#define EC_SB_REG_CSI_LO_INIT 0x1F +#define EC_SB_REG_CSI_LO_MAX 0x1F +#define EC_SB_REG_CSI_LO_MIN 0x0 +#define EC_SB_REG_CSI_LO_TAG 0x0 + +#define EC_SB_REG_SMB_TGL__A 0x2010016 +#define EC_SB_REG_SMB_TGL__W 1 +#define EC_SB_REG_SMB_TGL__M 0x1 +#define EC_SB_REG_SMB_TGL_OFF 0x0 +#define EC_SB_REG_SMB_TGL_ON 0x1 + +#define EC_SB_REG_SNR_HI__A 0x2010017 +#define EC_SB_REG_SNR_HI__W 8 +#define EC_SB_REG_SNR_HI__M 0xFF +#define EC_SB_REG_SNR_HI_INIT 0xFF +#define EC_SB_REG_SNR_HI_MAX 0xFF +#define EC_SB_REG_SNR_HI_MIN 0x0 +#define EC_SB_REG_SNR_HI_TAG 0x0 + +#define EC_SB_REG_SNR_MID__A 0x2010018 +#define EC_SB_REG_SNR_MID__W 8 +#define EC_SB_REG_SNR_MID__M 0xFF +#define EC_SB_REG_SNR_MID_INIT 0xFF +#define EC_SB_REG_SNR_MID_MAX 0xFF +#define EC_SB_REG_SNR_MID_MIN 0x0 +#define EC_SB_REG_SNR_MID_TAG 0x0 + +#define EC_SB_REG_SNR_LO__A 0x2010019 +#define EC_SB_REG_SNR_LO__W 8 +#define EC_SB_REG_SNR_LO__M 0xFF +#define EC_SB_REG_SNR_LO_INIT 0xFF +#define EC_SB_REG_SNR_LO_MAX 0xFF +#define EC_SB_REG_SNR_LO_MIN 0x0 +#define EC_SB_REG_SNR_LO_TAG 0x0 + +#define EC_SB_REG_SCALE_MSB__A 0x201001A +#define EC_SB_REG_SCALE_MSB__W 6 +#define EC_SB_REG_SCALE_MSB__M 0x3F +#define EC_SB_REG_SCALE_MSB_INIT 0x30 +#define EC_SB_REG_SCALE_MSB_MAX 0x3F + +#define EC_SB_REG_SCALE_BIT2__A 0x201001B +#define EC_SB_REG_SCALE_BIT2__W 6 +#define EC_SB_REG_SCALE_BIT2__M 0x3F +#define EC_SB_REG_SCALE_BIT2_INIT 0x20 +#define EC_SB_REG_SCALE_BIT2_MAX 0x3F + +#define EC_SB_REG_SCALE_LSB__A 0x201001C +#define EC_SB_REG_SCALE_LSB__W 6 +#define EC_SB_REG_SCALE_LSB__M 0x3F +#define EC_SB_REG_SCALE_LSB_INIT 0x10 +#define EC_SB_REG_SCALE_LSB_MAX 0x3F + +#define EC_SB_REG_CSI_OFS__A 0x201001D +#define EC_SB_REG_CSI_OFS__W 4 +#define EC_SB_REG_CSI_OFS__M 0xF +#define EC_SB_REG_CSI_OFS_INIT 0x1 +#define EC_SB_REG_CSI_OFS_ADD__B 0 +#define EC_SB_REG_CSI_OFS_ADD__W 3 +#define EC_SB_REG_CSI_OFS_ADD__M 0x7 +#define EC_SB_REG_CSI_OFS_DIS__B 3 +#define EC_SB_REG_CSI_OFS_DIS__W 1 +#define EC_SB_REG_CSI_OFS_DIS__M 0x8 +#define EC_SB_REG_CSI_OFS_DIS_ENA 0x0 +#define EC_SB_REG_CSI_OFS_DIS_DIS 0x8 + +#define EC_SB_SD_RAM__A 0x2020000 + +#define EC_SB_BD0_RAM__A 0x2030000 + +#define EC_SB_BD1_RAM__A 0x2040000 + +#define EC_VD_SID 0x17 + +#define EC_VD_REG_COMM_EXEC__A 0x2090000 +#define EC_VD_REG_COMM_EXEC__W 3 +#define EC_VD_REG_COMM_EXEC__M 0x7 +#define EC_VD_REG_COMM_EXEC_CTL__B 0 +#define EC_VD_REG_COMM_EXEC_CTL__W 3 +#define EC_VD_REG_COMM_EXEC_CTL__M 0x7 +#define EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 +#define EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define EC_VD_REG_COMM_STATE__A 0x2090001 +#define EC_VD_REG_COMM_STATE__W 4 +#define EC_VD_REG_COMM_STATE__M 0xF +#define EC_VD_REG_COMM_MB__A 0x2090002 +#define EC_VD_REG_COMM_MB__W 2 +#define EC_VD_REG_COMM_MB__M 0x3 +#define EC_VD_REG_COMM_MB_CTR__B 0 +#define EC_VD_REG_COMM_MB_CTR__W 1 +#define EC_VD_REG_COMM_MB_CTR__M 0x1 +#define EC_VD_REG_COMM_MB_CTR_OFF 0x0 +#define EC_VD_REG_COMM_MB_CTR_ON 0x1 +#define EC_VD_REG_COMM_MB_OBS__B 1 +#define EC_VD_REG_COMM_MB_OBS__W 1 +#define EC_VD_REG_COMM_MB_OBS__M 0x2 +#define EC_VD_REG_COMM_MB_OBS_OFF 0x0 +#define EC_VD_REG_COMM_MB_OBS_ON 0x2 + +#define EC_VD_REG_COMM_SERVICE0__A 0x2090003 +#define EC_VD_REG_COMM_SERVICE0__W 16 +#define EC_VD_REG_COMM_SERVICE0__M 0xFFFF +#define EC_VD_REG_COMM_SERVICE1__A 0x2090004 +#define EC_VD_REG_COMM_SERVICE1__W 16 +#define EC_VD_REG_COMM_SERVICE1__M 0xFFFF +#define EC_VD_REG_COMM_INT_STA__A 0x2090007 +#define EC_VD_REG_COMM_INT_STA__W 1 +#define EC_VD_REG_COMM_INT_STA__M 0x1 +#define EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 +#define EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 +#define EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 + +#define EC_VD_REG_COMM_INT_MSK__A 0x2090008 +#define EC_VD_REG_COMM_INT_MSK__W 1 +#define EC_VD_REG_COMM_INT_MSK__M 0x1 +#define EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 +#define EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 +#define EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 + +#define EC_VD_REG_FORCE__A 0x2090010 +#define EC_VD_REG_FORCE__W 2 +#define EC_VD_REG_FORCE__M 0x3 +#define EC_VD_REG_FORCE_INIT 0x0 +#define EC_VD_REG_FORCE_FREE 0x0 +#define EC_VD_REG_FORCE_PROP 0x1 +#define EC_VD_REG_FORCE_FORCED 0x2 +#define EC_VD_REG_FORCE_FIXED 0x3 + +#define EC_VD_REG_SET_CODERATE__A 0x2090011 +#define EC_VD_REG_SET_CODERATE__W 3 +#define EC_VD_REG_SET_CODERATE__M 0x7 +#define EC_VD_REG_SET_CODERATE_INIT 0x0 +#define EC_VD_REG_SET_CODERATE_C1_2 0x0 +#define EC_VD_REG_SET_CODERATE_C2_3 0x1 +#define EC_VD_REG_SET_CODERATE_C3_4 0x2 +#define EC_VD_REG_SET_CODERATE_C5_6 0x3 +#define EC_VD_REG_SET_CODERATE_C7_8 0x4 + +#define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 +#define EC_VD_REG_REQ_SMB_CNT__W 16 +#define EC_VD_REG_REQ_SMB_CNT__M 0xFFFF +#define EC_VD_REG_REQ_SMB_CNT_INIT 0x0 + +#define EC_VD_REG_REQ_BIT_CNT__A 0x2090013 +#define EC_VD_REG_REQ_BIT_CNT__W 16 +#define EC_VD_REG_REQ_BIT_CNT__M 0xFFFF +#define EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF + +#define EC_VD_REG_RLK_ENA__A 0x2090014 +#define EC_VD_REG_RLK_ENA__W 1 +#define EC_VD_REG_RLK_ENA__M 0x1 +#define EC_VD_REG_RLK_ENA_INIT 0x0 +#define EC_VD_REG_RLK_ENA_OFF 0x0 +#define EC_VD_REG_RLK_ENA_ON 0x1 + +#define EC_VD_REG_VAL__A 0x2090015 +#define EC_VD_REG_VAL__W 2 +#define EC_VD_REG_VAL__M 0x3 +#define EC_VD_REG_VAL_INIT 0x0 +#define EC_VD_REG_VAL_CODE 0x1 +#define EC_VD_REG_VAL_CNT 0x2 + +#define EC_VD_REG_GET_CODERATE__A 0x2090016 +#define EC_VD_REG_GET_CODERATE__W 3 +#define EC_VD_REG_GET_CODERATE__M 0x7 +#define EC_VD_REG_GET_CODERATE_INIT 0x0 +#define EC_VD_REG_GET_CODERATE_C1_2 0x0 +#define EC_VD_REG_GET_CODERATE_C2_3 0x1 +#define EC_VD_REG_GET_CODERATE_C3_4 0x2 +#define EC_VD_REG_GET_CODERATE_C5_6 0x3 +#define EC_VD_REG_GET_CODERATE_C7_8 0x4 + +#define EC_VD_REG_ERR_BIT_CNT__A 0x2090017 +#define EC_VD_REG_ERR_BIT_CNT__W 16 +#define EC_VD_REG_ERR_BIT_CNT__M 0xFFFF +#define EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF + +#define EC_VD_REG_IN_BIT_CNT__A 0x2090018 +#define EC_VD_REG_IN_BIT_CNT__W 16 +#define EC_VD_REG_IN_BIT_CNT__M 0xFFFF +#define EC_VD_REG_IN_BIT_CNT_INIT 0x0 + +#define EC_VD_REG_STS__A 0x2090019 +#define EC_VD_REG_STS__W 1 +#define EC_VD_REG_STS__M 0x1 +#define EC_VD_REG_STS_INIT 0x0 +#define EC_VD_REG_STS_NO_LOCK 0x0 +#define EC_VD_REG_STS_IN_LOCK 0x1 + +#define EC_VD_REG_RLK_CNT__A 0x209001A +#define EC_VD_REG_RLK_CNT__W 16 +#define EC_VD_REG_RLK_CNT__M 0xFFFF +#define EC_VD_REG_RLK_CNT_INIT 0x0 + +#define EC_VD_TB0_RAM__A 0x20A0000 + +#define EC_VD_TB1_RAM__A 0x20B0000 + +#define EC_VD_TB2_RAM__A 0x20C0000 + +#define EC_VD_TB3_RAM__A 0x20D0000 + +#define EC_VD_RE_RAM__A 0x2100000 + +#define EC_OD_SID 0x18 + +#define EC_OD_REG_COMM_EXEC__A 0x2110000 +#define EC_OD_REG_COMM_EXEC__W 3 +#define EC_OD_REG_COMM_EXEC__M 0x7 +#define EC_OD_REG_COMM_EXEC_CTL__B 0 +#define EC_OD_REG_COMM_EXEC_CTL__W 3 +#define EC_OD_REG_COMM_EXEC_CTL__M 0x7 +#define EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 +#define EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 + +#define EC_OD_REG_COMM_MB__A 0x2110002 +#define EC_OD_REG_COMM_MB__W 3 +#define EC_OD_REG_COMM_MB__M 0x7 +#define EC_OD_REG_COMM_MB_CTR__B 0 +#define EC_OD_REG_COMM_MB_CTR__W 1 +#define EC_OD_REG_COMM_MB_CTR__M 0x1 +#define EC_OD_REG_COMM_MB_CTR_OFF 0x0 +#define EC_OD_REG_COMM_MB_CTR_ON 0x1 +#define EC_OD_REG_COMM_MB_OBS__B 1 +#define EC_OD_REG_COMM_MB_OBS__W 1 +#define EC_OD_REG_COMM_MB_OBS__M 0x2 +#define EC_OD_REG_COMM_MB_OBS_OFF 0x0 +#define EC_OD_REG_COMM_MB_OBS_ON 0x2 + +#define EC_OD_REG_COMM_SERVICE0__A 0x2110003 +#define EC_OD_REG_COMM_SERVICE0__W 10 +#define EC_OD_REG_COMM_SERVICE0__M 0x3FF +#define EC_OD_REG_COMM_SERVICE1__A 0x2110004 +#define EC_OD_REG_COMM_SERVICE1__W 11 +#define EC_OD_REG_COMM_SERVICE1__M 0x7FF + +#define EC_OD_REG_COMM_ACTIVATE__A 0x2110005 +#define EC_OD_REG_COMM_ACTIVATE__W 2 +#define EC_OD_REG_COMM_ACTIVATE__M 0x3 + +#define EC_OD_REG_COMM_COUNT__A 0x2110006 +#define EC_OD_REG_COMM_COUNT__W 16 +#define EC_OD_REG_COMM_COUNT__M 0xFFFF + +#define EC_OD_REG_COMM_INT_STA__A 0x2110007 +#define EC_OD_REG_COMM_INT_STA__W 2 +#define EC_OD_REG_COMM_INT_STA__M 0x3 +#define EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 +#define EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 +#define EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 +#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 +#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 +#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 + +#define EC_OD_REG_COMM_INT_MSK__A 0x2110008 +#define EC_OD_REG_COMM_INT_MSK__W 2 +#define EC_OD_REG_COMM_INT_MSK__M 0x3 +#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 +#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 +#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 +#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 +#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 +#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 + +#define EC_OD_REG_SYNC__A 0x2110010 +#define EC_OD_REG_SYNC__W 12 +#define EC_OD_REG_SYNC__M 0xFFF +#define EC_OD_REG_SYNC_NR_SYNC__B 0 +#define EC_OD_REG_SYNC_NR_SYNC__W 5 +#define EC_OD_REG_SYNC_NR_SYNC__M 0x1F +#define EC_OD_REG_SYNC_IN_SYNC__B 5 +#define EC_OD_REG_SYNC_IN_SYNC__W 4 +#define EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 +#define EC_OD_REG_SYNC_OUT_SYNC__B 9 +#define EC_OD_REG_SYNC_OUT_SYNC__W 3 +#define EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 + +#define EC_OD_REG_NOSYNC__A 0x2110011 +#define EC_OD_REG_NOSYNC__W 8 +#define EC_OD_REG_NOSYNC__M 0xFF + +#define EC_OD_DEINT_RAM__A 0x2120000 + +#define EC_RS_SID 0x19 + +#define EC_RS_REG_COMM_EXEC__A 0x2130000 +#define EC_RS_REG_COMM_EXEC__W 3 +#define EC_RS_REG_COMM_EXEC__M 0x7 +#define EC_RS_REG_COMM_EXEC_CTL__B 0 +#define EC_RS_REG_COMM_EXEC_CTL__W 3 +#define EC_RS_REG_COMM_EXEC_CTL__M 0x7 +#define EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 +#define EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define EC_RS_REG_COMM_STATE__A 0x2130001 +#define EC_RS_REG_COMM_STATE__W 4 +#define EC_RS_REG_COMM_STATE__M 0xF +#define EC_RS_REG_COMM_MB__A 0x2130002 +#define EC_RS_REG_COMM_MB__W 2 +#define EC_RS_REG_COMM_MB__M 0x3 +#define EC_RS_REG_COMM_MB_CTR__B 0 +#define EC_RS_REG_COMM_MB_CTR__W 1 +#define EC_RS_REG_COMM_MB_CTR__M 0x1 +#define EC_RS_REG_COMM_MB_CTR_OFF 0x0 +#define EC_RS_REG_COMM_MB_CTR_ON 0x1 +#define EC_RS_REG_COMM_MB_OBS__B 1 +#define EC_RS_REG_COMM_MB_OBS__W 1 +#define EC_RS_REG_COMM_MB_OBS__M 0x2 +#define EC_RS_REG_COMM_MB_OBS_OFF 0x0 +#define EC_RS_REG_COMM_MB_OBS_ON 0x2 + +#define EC_RS_REG_COMM_SERVICE0__A 0x2130003 +#define EC_RS_REG_COMM_SERVICE0__W 16 +#define EC_RS_REG_COMM_SERVICE0__M 0xFFFF +#define EC_RS_REG_COMM_SERVICE1__A 0x2130004 +#define EC_RS_REG_COMM_SERVICE1__W 16 +#define EC_RS_REG_COMM_SERVICE1__M 0xFFFF +#define EC_RS_REG_COMM_INT_STA__A 0x2130007 +#define EC_RS_REG_COMM_INT_STA__W 1 +#define EC_RS_REG_COMM_INT_STA__M 0x1 +#define EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 +#define EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 +#define EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 + +#define EC_RS_REG_COMM_INT_MSK__A 0x2130008 +#define EC_RS_REG_COMM_INT_MSK__W 1 +#define EC_RS_REG_COMM_INT_MSK__M 0x1 +#define EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 +#define EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 +#define EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 + +#define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 +#define EC_RS_REG_REQ_PCK_CNT__W 16 +#define EC_RS_REG_REQ_PCK_CNT__M 0xFFFF +#define EC_RS_REG_REQ_PCK_CNT_INIT 0xFF + +#define EC_RS_REG_VAL__A 0x2130011 +#define EC_RS_REG_VAL__W 1 +#define EC_RS_REG_VAL__M 0x1 +#define EC_RS_REG_VAL_INIT 0x0 +#define EC_RS_REG_VAL_PCK 0x1 + +#define EC_RS_REG_ERR_PCK_CNT__A 0x2130012 +#define EC_RS_REG_ERR_PCK_CNT__W 16 +#define EC_RS_REG_ERR_PCK_CNT__M 0xFFFF +#define EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF + +#define EC_RS_REG_ERR_SMB_CNT__A 0x2130013 +#define EC_RS_REG_ERR_SMB_CNT__W 16 +#define EC_RS_REG_ERR_SMB_CNT__M 0xFFFF +#define EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF + +#define EC_RS_REG_ERR_BIT_CNT__A 0x2130014 +#define EC_RS_REG_ERR_BIT_CNT__W 16 +#define EC_RS_REG_ERR_BIT_CNT__M 0xFFFF +#define EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF + +#define EC_RS_REG_IN_PCK_CNT__A 0x2130015 +#define EC_RS_REG_IN_PCK_CNT__W 16 +#define EC_RS_REG_IN_PCK_CNT__M 0xFFFF +#define EC_RS_REG_IN_PCK_CNT_INIT 0x0 + +#define EC_RS_EC_RAM__A 0x2140000 + +#define EC_OC_SID 0x1A + +#define EC_OC_REG_COMM_EXEC__A 0x2150000 +#define EC_OC_REG_COMM_EXEC__W 3 +#define EC_OC_REG_COMM_EXEC__M 0x7 +#define EC_OC_REG_COMM_EXEC_CTL__B 0 +#define EC_OC_REG_COMM_EXEC_CTL__W 3 +#define EC_OC_REG_COMM_EXEC_CTL__M 0x7 +#define EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 +#define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 +#define EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 + +#define EC_OC_REG_COMM_STATE__A 0x2150001 +#define EC_OC_REG_COMM_STATE__W 4 +#define EC_OC_REG_COMM_STATE__M 0xF + +#define EC_OC_REG_COMM_MB__A 0x2150002 +#define EC_OC_REG_COMM_MB__W 2 +#define EC_OC_REG_COMM_MB__M 0x3 +#define EC_OC_REG_COMM_MB_CTR__B 0 +#define EC_OC_REG_COMM_MB_CTR__W 1 +#define EC_OC_REG_COMM_MB_CTR__M 0x1 +#define EC_OC_REG_COMM_MB_CTR_OFF 0x0 +#define EC_OC_REG_COMM_MB_CTR_ON 0x1 +#define EC_OC_REG_COMM_MB_OBS__B 1 +#define EC_OC_REG_COMM_MB_OBS__W 1 +#define EC_OC_REG_COMM_MB_OBS__M 0x2 +#define EC_OC_REG_COMM_MB_OBS_OFF 0x0 +#define EC_OC_REG_COMM_MB_OBS_ON 0x2 + +#define EC_OC_REG_COMM_SERVICE0__A 0x2150003 +#define EC_OC_REG_COMM_SERVICE0__W 10 +#define EC_OC_REG_COMM_SERVICE0__M 0x3FF + +#define EC_OC_REG_COMM_SERVICE1__A 0x2150004 +#define EC_OC_REG_COMM_SERVICE1__W 11 +#define EC_OC_REG_COMM_SERVICE1__M 0x7FF + +#define EC_OC_REG_COMM_INT_STA__A 0x2150007 +#define EC_OC_REG_COMM_INT_STA__W 6 +#define EC_OC_REG_COMM_INT_STA__M 0x3F +#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 +#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 +#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 +#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 +#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 +#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 +#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 +#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 +#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 +#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 +#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 +#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 +#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 +#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 +#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 +#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 +#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 +#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 + +#define EC_OC_REG_COMM_INT_MSK__A 0x2150008 +#define EC_OC_REG_COMM_INT_MSK__W 6 +#define EC_OC_REG_COMM_INT_MSK__M 0x3F +#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 +#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 +#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 +#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 +#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 +#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 +#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 +#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 +#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 +#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 +#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 +#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 +#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 +#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 +#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 +#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 +#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 +#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 + +#define EC_OC_REG_OC_MODE_LOP__A 0x2150010 +#define EC_OC_REG_OC_MODE_LOP__W 16 +#define EC_OC_REG_OC_MODE_LOP__M 0xFFFF +#define EC_OC_REG_OC_MODE_LOP_INIT 0x0 + +#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 +#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 +#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 +#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 + +#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 +#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 +#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 +#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 +#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 + +#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 +#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 +#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 +#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 + +#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 +#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 +#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 +#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 + +#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 +#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 +#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 + +#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 +#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 +#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 + +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 + +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 + +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 + +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 + +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 + +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 + +#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 +#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 +#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 +#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 + +#define EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 +#define EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 +#define EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 +#define EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 + +#define EC_OC_REG_OC_MODE_HIP__A 0x2150011 +#define EC_OC_REG_OC_MODE_HIP__W 14 +#define EC_OC_REG_OC_MODE_HIP__M 0x3FFF +#define EC_OC_REG_OC_MODE_HIP_INIT 0x0 + +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 + +#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 +#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 + +#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 +#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 +#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 +#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 + +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 +#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 + +#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 +#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 +#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 + +#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 +#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 +#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 +#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 + +#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 +#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 +#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 +#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 + +#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 +#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 +#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 + +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 + +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 + +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 + +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 +#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 + +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 + +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 +#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 + +#define EC_OC_REG_OC_MPG_SIO__A 0x2150012 +#define EC_OC_REG_OC_MPG_SIO__W 12 +#define EC_OC_REG_OC_MPG_SIO__M 0xFFF +#define EC_OC_REG_OC_MPG_SIO_INIT 0xFFF + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 + +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 +#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 + +#define EC_OC_REG_OC_MON_SIO__A 0x2150013 +#define EC_OC_REG_OC_MON_SIO__W 12 +#define EC_OC_REG_OC_MON_SIO__M 0xFFF +#define EC_OC_REG_OC_MON_SIO_INIT 0xFFF + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__B 0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__M 0x1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_0_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_0_INPUT 0x1 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__B 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__M 0x2 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_1_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_1_INPUT 0x2 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__B 2 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__M 0x4 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_2_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_2_INPUT 0x4 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__B 3 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__M 0x8 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_3_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_3_INPUT 0x8 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__B 4 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__M 0x10 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_4_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_4_INPUT 0x10 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__B 5 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__M 0x20 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_5_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_5_INPUT 0x20 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__B 6 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__M 0x40 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_6_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_6_INPUT 0x40 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__B 7 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__M 0x80 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_7_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_7_INPUT 0x80 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__B 8 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__M 0x100 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_8_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_8_INPUT 0x100 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__B 9 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__M 0x200 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_9_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_9_INPUT 0x200 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__B 10 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__M 0x400 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_10_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_10_INPUT 0x400 + +#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__B 11 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__W 1 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__M 0x800 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_OUTPUT 0x0 +#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_INPUT 0x800 + +#define EC_OC_REG_DTO_INC_LOP__A 0x2150014 +#define EC_OC_REG_DTO_INC_LOP__W 16 +#define EC_OC_REG_DTO_INC_LOP__M 0xFFFF +#define EC_OC_REG_DTO_INC_LOP_INIT 0x0 + +#define EC_OC_REG_DTO_INC_HIP__A 0x2150015 +#define EC_OC_REG_DTO_INC_HIP__W 8 +#define EC_OC_REG_DTO_INC_HIP__M 0xFF +#define EC_OC_REG_DTO_INC_HIP_INIT 0x0 + +#define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 +#define EC_OC_REG_SNC_ISC_LVL__W 12 +#define EC_OC_REG_SNC_ISC_LVL__M 0xFFF +#define EC_OC_REG_SNC_ISC_LVL_INIT 0x0 + +#define EC_OC_REG_SNC_ISC_LVL_ISC__B 0 +#define EC_OC_REG_SNC_ISC_LVL_ISC__W 4 +#define EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF + +#define EC_OC_REG_SNC_ISC_LVL_OSC__B 4 +#define EC_OC_REG_SNC_ISC_LVL_OSC__W 4 +#define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 + +#define EC_OC_REG_SNC_ISC_LVL_NSC__B 8 +#define EC_OC_REG_SNC_ISC_LVL_NSC__W 4 +#define EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 + +#define EC_OC_REG_SNC_NSC_LVL__A 0x2150017 +#define EC_OC_REG_SNC_NSC_LVL__W 8 +#define EC_OC_REG_SNC_NSC_LVL__M 0xFF +#define EC_OC_REG_SNC_NSC_LVL_INIT 0x0 + +#define EC_OC_REG_SNC_SNC_MODE__A 0x2150019 +#define EC_OC_REG_SNC_SNC_MODE__W 2 +#define EC_OC_REG_SNC_SNC_MODE__M 0x3 +#define EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 +#define EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 +#define EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 + +#define EC_OC_REG_SNC_PCK_NMB__A 0x215001A +#define EC_OC_REG_SNC_PCK_NMB__W 16 +#define EC_OC_REG_SNC_PCK_NMB__M 0xFFFF + +#define EC_OC_REG_SNC_PCK_CNT__A 0x215001B +#define EC_OC_REG_SNC_PCK_CNT__W 16 +#define EC_OC_REG_SNC_PCK_CNT__M 0xFFFF + +#define EC_OC_REG_SNC_PCK_ERR__A 0x215001C +#define EC_OC_REG_SNC_PCK_ERR__W 16 +#define EC_OC_REG_SNC_PCK_ERR__M 0xFFFF + +#define EC_OC_REG_TMD_TOP_MODE__A 0x215001D +#define EC_OC_REG_TMD_TOP_MODE__W 2 +#define EC_OC_REG_TMD_TOP_MODE__M 0x3 +#define EC_OC_REG_TMD_TOP_MODE_INIT 0x0 +#define EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 +#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 +#define EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 +#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 + +#define EC_OC_REG_TMD_TOP_CNT__A 0x215001E +#define EC_OC_REG_TMD_TOP_CNT__W 10 +#define EC_OC_REG_TMD_TOP_CNT__M 0x3FF +#define EC_OC_REG_TMD_TOP_CNT_INIT 0x0 + +#define EC_OC_REG_TMD_HIL_MAR__A 0x215001F +#define EC_OC_REG_TMD_HIL_MAR__W 10 +#define EC_OC_REG_TMD_HIL_MAR__M 0x3FF +#define EC_OC_REG_TMD_HIL_MAR_INIT 0x0 + +#define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 +#define EC_OC_REG_TMD_LOL_MAR__W 10 +#define EC_OC_REG_TMD_LOL_MAR__M 0x3FF +#define EC_OC_REG_TMD_LOL_MAR_INIT 0x0 + +#define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 +#define EC_OC_REG_TMD_CUR_CNT__W 4 +#define EC_OC_REG_TMD_CUR_CNT__M 0xF +#define EC_OC_REG_TMD_CUR_CNT_INIT 0x0 + +#define EC_OC_REG_TMD_IUR_CNT__A 0x2150022 +#define EC_OC_REG_TMD_IUR_CNT__W 4 +#define EC_OC_REG_TMD_IUR_CNT__M 0xF +#define EC_OC_REG_TMD_IUR_CNT_INIT 0x0 + +#define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 +#define EC_OC_REG_AVR_ASH_CNT__W 4 +#define EC_OC_REG_AVR_ASH_CNT__M 0xF +#define EC_OC_REG_AVR_ASH_CNT_INIT 0x0 + +#define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 +#define EC_OC_REG_AVR_BSH_CNT__W 4 +#define EC_OC_REG_AVR_BSH_CNT__M 0xF +#define EC_OC_REG_AVR_BSH_CNT_INIT 0x0 + +#define EC_OC_REG_AVR_AVE_LOP__A 0x2150025 +#define EC_OC_REG_AVR_AVE_LOP__W 16 +#define EC_OC_REG_AVR_AVE_LOP__M 0xFFFF + +#define EC_OC_REG_AVR_AVE_HIP__A 0x2150026 +#define EC_OC_REG_AVR_AVE_HIP__W 5 +#define EC_OC_REG_AVR_AVE_HIP__M 0x1F + +#define EC_OC_REG_RCN_MODE__A 0x2150027 +#define EC_OC_REG_RCN_MODE__W 3 +#define EC_OC_REG_RCN_MODE__M 0x7 +#define EC_OC_REG_RCN_MODE_INIT 0x0 + +#define EC_OC_REG_RCN_MODE_MODE_0__B 0 +#define EC_OC_REG_RCN_MODE_MODE_0__W 1 +#define EC_OC_REG_RCN_MODE_MODE_0__M 0x1 +#define EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 +#define EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 + +#define EC_OC_REG_RCN_MODE_MODE_1__B 1 +#define EC_OC_REG_RCN_MODE_MODE_1__W 1 +#define EC_OC_REG_RCN_MODE_MODE_1__M 0x2 +#define EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 +#define EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 + +#define EC_OC_REG_RCN_MODE_MODE_2__B 2 +#define EC_OC_REG_RCN_MODE_MODE_2__W 1 +#define EC_OC_REG_RCN_MODE_MODE_2__M 0x4 +#define EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 +#define EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 + +#define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 +#define EC_OC_REG_RCN_CRA_LOP__W 16 +#define EC_OC_REG_RCN_CRA_LOP__M 0xFFFF +#define EC_OC_REG_RCN_CRA_LOP_INIT 0x0 + +#define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 +#define EC_OC_REG_RCN_CRA_HIP__W 8 +#define EC_OC_REG_RCN_CRA_HIP__M 0xFF +#define EC_OC_REG_RCN_CRA_HIP_INIT 0x0 + +#define EC_OC_REG_RCN_CST_LOP__A 0x215002A +#define EC_OC_REG_RCN_CST_LOP__W 16 +#define EC_OC_REG_RCN_CST_LOP__M 0xFFFF +#define EC_OC_REG_RCN_CST_LOP_INIT 0x0 + +#define EC_OC_REG_RCN_CST_HIP__A 0x215002B +#define EC_OC_REG_RCN_CST_HIP__W 8 +#define EC_OC_REG_RCN_CST_HIP__M 0xFF +#define EC_OC_REG_RCN_CST_HIP_INIT 0x0 + +#define EC_OC_REG_RCN_SET_LVL__A 0x215002C +#define EC_OC_REG_RCN_SET_LVL__W 9 +#define EC_OC_REG_RCN_SET_LVL__M 0x1FF +#define EC_OC_REG_RCN_SET_LVL_INIT 0x0 + +#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D +#define EC_OC_REG_RCN_GAI_LVL__W 4 +#define EC_OC_REG_RCN_GAI_LVL__M 0xF +#define EC_OC_REG_RCN_GAI_LVL_INIT 0x0 + +#define EC_OC_REG_RCN_DRA_LOP__A 0x215002E +#define EC_OC_REG_RCN_DRA_LOP__W 16 +#define EC_OC_REG_RCN_DRA_LOP__M 0xFFFF + +#define EC_OC_REG_RCN_DRA_HIP__A 0x215002F +#define EC_OC_REG_RCN_DRA_HIP__W 8 +#define EC_OC_REG_RCN_DRA_HIP__M 0xFF + +#define EC_OC_REG_RCN_DOF_LOP__A 0x2150030 +#define EC_OC_REG_RCN_DOF_LOP__W 16 +#define EC_OC_REG_RCN_DOF_LOP__M 0xFFFF + +#define EC_OC_REG_RCN_DOF_HIP__A 0x2150031 +#define EC_OC_REG_RCN_DOF_HIP__W 8 +#define EC_OC_REG_RCN_DOF_HIP__M 0xFF + +#define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 +#define EC_OC_REG_RCN_CLP_LOP__W 16 +#define EC_OC_REG_RCN_CLP_LOP__M 0xFFFF +#define EC_OC_REG_RCN_CLP_LOP_INIT 0xFFFF + +#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 +#define EC_OC_REG_RCN_CLP_HIP__W 8 +#define EC_OC_REG_RCN_CLP_HIP__M 0xFF +#define EC_OC_REG_RCN_CLP_HIP_INIT 0xFF + +#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 +#define EC_OC_REG_RCN_MAP_LOP__W 16 +#define EC_OC_REG_RCN_MAP_LOP__M 0xFFFF + +#define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 +#define EC_OC_REG_RCN_MAP_HIP__W 8 +#define EC_OC_REG_RCN_MAP_HIP__M 0xFF + +#define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 +#define EC_OC_REG_OCR_MPG_UOS__W 12 +#define EC_OC_REG_OCR_MPG_UOS__M 0xFFF +#define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 +#define EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 +#define EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 +#define EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 +#define EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 +#define EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 +#define EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 +#define EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 +#define EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 +#define EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 +#define EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 +#define EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 + +#define EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 +#define EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 +#define EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 +#define EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 + +#define EC_OC_REG_OCR_MPG_UOS_ERR__B 8 +#define EC_OC_REG_OCR_MPG_UOS_ERR__W 1 +#define EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 +#define EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 + +#define EC_OC_REG_OCR_MPG_UOS_STR__B 9 +#define EC_OC_REG_OCR_MPG_UOS_STR__W 1 +#define EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 +#define EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 + +#define EC_OC_REG_OCR_MPG_UOS_VAL__B 10 +#define EC_OC_REG_OCR_MPG_UOS_VAL__W 1 +#define EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 +#define EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 + +#define EC_OC_REG_OCR_MPG_UOS_CLK__B 11 +#define EC_OC_REG_OCR_MPG_UOS_CLK__W 1 +#define EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 +#define EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 + +#define EC_OC_REG_OCR_MPG_WRI__A 0x2150037 +#define EC_OC_REG_OCR_MPG_WRI__W 12 +#define EC_OC_REG_OCR_MPG_WRI__M 0xFFF +#define EC_OC_REG_OCR_MPG_WRI_INIT 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 +#define EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 +#define EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 +#define EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 +#define EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 +#define EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 +#define EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 +#define EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 +#define EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 +#define EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 +#define EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 +#define EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 +#define EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 +#define EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 +#define EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 +#define EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 +#define EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 +#define EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 +#define EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 +#define EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 +#define EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 +#define EC_OC_REG_OCR_MPG_WRI_ERR__B 8 +#define EC_OC_REG_OCR_MPG_WRI_ERR__W 1 +#define EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 +#define EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 +#define EC_OC_REG_OCR_MPG_WRI_STR__B 9 +#define EC_OC_REG_OCR_MPG_WRI_STR__W 1 +#define EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 +#define EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 +#define EC_OC_REG_OCR_MPG_WRI_VAL__B 10 +#define EC_OC_REG_OCR_MPG_WRI_VAL__W 1 +#define EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 +#define EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 +#define EC_OC_REG_OCR_MPG_WRI_CLK__B 11 +#define EC_OC_REG_OCR_MPG_WRI_CLK__W 1 +#define EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 +#define EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 +#define EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 + +#define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 +#define EC_OC_REG_OCR_MPG_USR_DAT__W 12 +#define EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF + +#define EC_OC_REG_OCR_MON_UOS__A 0x2150039 +#define EC_OC_REG_OCR_MON_UOS__W 12 +#define EC_OC_REG_OCR_MON_UOS__M 0xFFF +#define EC_OC_REG_OCR_MON_UOS_INIT 0x0 + +#define EC_OC_REG_OCR_MON_UOS_DAT_0__B 0 +#define EC_OC_REG_OCR_MON_UOS_DAT_0__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_0__M 0x1 +#define EC_OC_REG_OCR_MON_UOS_DAT_0_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1 + +#define EC_OC_REG_OCR_MON_UOS_DAT_1__B 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_1__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_1__M 0x2 +#define EC_OC_REG_OCR_MON_UOS_DAT_1_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2 + +#define EC_OC_REG_OCR_MON_UOS_DAT_2__B 2 +#define EC_OC_REG_OCR_MON_UOS_DAT_2__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_2__M 0x4 +#define EC_OC_REG_OCR_MON_UOS_DAT_2_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4 + +#define EC_OC_REG_OCR_MON_UOS_DAT_3__B 3 +#define EC_OC_REG_OCR_MON_UOS_DAT_3__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_3__M 0x8 +#define EC_OC_REG_OCR_MON_UOS_DAT_3_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8 + +#define EC_OC_REG_OCR_MON_UOS_DAT_4__B 4 +#define EC_OC_REG_OCR_MON_UOS_DAT_4__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_4__M 0x10 +#define EC_OC_REG_OCR_MON_UOS_DAT_4_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10 + +#define EC_OC_REG_OCR_MON_UOS_DAT_5__B 5 +#define EC_OC_REG_OCR_MON_UOS_DAT_5__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_5__M 0x20 +#define EC_OC_REG_OCR_MON_UOS_DAT_5_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20 + +#define EC_OC_REG_OCR_MON_UOS_DAT_6__B 6 +#define EC_OC_REG_OCR_MON_UOS_DAT_6__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_6__M 0x40 +#define EC_OC_REG_OCR_MON_UOS_DAT_6_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40 + +#define EC_OC_REG_OCR_MON_UOS_DAT_7__B 7 +#define EC_OC_REG_OCR_MON_UOS_DAT_7__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_7__M 0x80 +#define EC_OC_REG_OCR_MON_UOS_DAT_7_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80 + +#define EC_OC_REG_OCR_MON_UOS_DAT_8__B 8 +#define EC_OC_REG_OCR_MON_UOS_DAT_8__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_8__M 0x100 +#define EC_OC_REG_OCR_MON_UOS_DAT_8_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100 + +#define EC_OC_REG_OCR_MON_UOS_DAT_9__B 9 +#define EC_OC_REG_OCR_MON_UOS_DAT_9__W 1 +#define EC_OC_REG_OCR_MON_UOS_DAT_9__M 0x200 +#define EC_OC_REG_OCR_MON_UOS_DAT_9_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200 + +#define EC_OC_REG_OCR_MON_UOS_VAL__B 10 +#define EC_OC_REG_OCR_MON_UOS_VAL__W 1 +#define EC_OC_REG_OCR_MON_UOS_VAL__M 0x400 +#define EC_OC_REG_OCR_MON_UOS_VAL_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400 + +#define EC_OC_REG_OCR_MON_UOS_CLK__B 11 +#define EC_OC_REG_OCR_MON_UOS_CLK__W 1 +#define EC_OC_REG_OCR_MON_UOS_CLK__M 0x800 +#define EC_OC_REG_OCR_MON_UOS_CLK_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 + +#define EC_OC_REG_OCR_MON_WRI__A 0x215003A +#define EC_OC_REG_OCR_MON_WRI__W 12 +#define EC_OC_REG_OCR_MON_WRI__M 0xFFF +#define EC_OC_REG_OCR_MON_WRI_INIT 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_0__B 0 +#define EC_OC_REG_OCR_MON_WRI_DAT_0__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_0__M 0x1 +#define EC_OC_REG_OCR_MON_WRI_DAT_0_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_0_ENABLE 0x1 +#define EC_OC_REG_OCR_MON_WRI_DAT_1__B 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_1__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_1__M 0x2 +#define EC_OC_REG_OCR_MON_WRI_DAT_1_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_1_ENABLE 0x2 +#define EC_OC_REG_OCR_MON_WRI_DAT_2__B 2 +#define EC_OC_REG_OCR_MON_WRI_DAT_2__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_2__M 0x4 +#define EC_OC_REG_OCR_MON_WRI_DAT_2_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_2_ENABLE 0x4 +#define EC_OC_REG_OCR_MON_WRI_DAT_3__B 3 +#define EC_OC_REG_OCR_MON_WRI_DAT_3__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_3__M 0x8 +#define EC_OC_REG_OCR_MON_WRI_DAT_3_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_3_ENABLE 0x8 +#define EC_OC_REG_OCR_MON_WRI_DAT_4__B 4 +#define EC_OC_REG_OCR_MON_WRI_DAT_4__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_4__M 0x10 +#define EC_OC_REG_OCR_MON_WRI_DAT_4_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_4_ENABLE 0x10 +#define EC_OC_REG_OCR_MON_WRI_DAT_5__B 5 +#define EC_OC_REG_OCR_MON_WRI_DAT_5__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_5__M 0x20 +#define EC_OC_REG_OCR_MON_WRI_DAT_5_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_5_ENABLE 0x20 +#define EC_OC_REG_OCR_MON_WRI_DAT_6__B 6 +#define EC_OC_REG_OCR_MON_WRI_DAT_6__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_6__M 0x40 +#define EC_OC_REG_OCR_MON_WRI_DAT_6_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_6_ENABLE 0x40 +#define EC_OC_REG_OCR_MON_WRI_DAT_7__B 7 +#define EC_OC_REG_OCR_MON_WRI_DAT_7__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_7__M 0x80 +#define EC_OC_REG_OCR_MON_WRI_DAT_7_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_7_ENABLE 0x80 +#define EC_OC_REG_OCR_MON_WRI_DAT_8__B 8 +#define EC_OC_REG_OCR_MON_WRI_DAT_8__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_8__M 0x100 +#define EC_OC_REG_OCR_MON_WRI_DAT_8_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_8_ENABLE 0x100 +#define EC_OC_REG_OCR_MON_WRI_DAT_9__B 9 +#define EC_OC_REG_OCR_MON_WRI_DAT_9__W 1 +#define EC_OC_REG_OCR_MON_WRI_DAT_9__M 0x200 +#define EC_OC_REG_OCR_MON_WRI_DAT_9_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_DAT_9_ENABLE 0x200 +#define EC_OC_REG_OCR_MON_WRI_VAL__B 10 +#define EC_OC_REG_OCR_MON_WRI_VAL__W 1 +#define EC_OC_REG_OCR_MON_WRI_VAL__M 0x400 +#define EC_OC_REG_OCR_MON_WRI_VAL_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_VAL_ENABLE 0x400 +#define EC_OC_REG_OCR_MON_WRI_CLK__B 11 +#define EC_OC_REG_OCR_MON_WRI_CLK__W 1 +#define EC_OC_REG_OCR_MON_WRI_CLK__M 0x800 +#define EC_OC_REG_OCR_MON_WRI_CLK_DISABLE 0x0 +#define EC_OC_REG_OCR_MON_WRI_CLK_ENABLE 0x800 + +#define EC_OC_REG_OCR_MON_USR_DAT__A 0x215003B +#define EC_OC_REG_OCR_MON_USR_DAT__W 12 +#define EC_OC_REG_OCR_MON_USR_DAT__M 0xFFF + +#define EC_OC_REG_OCR_MON_CNT__A 0x215003C +#define EC_OC_REG_OCR_MON_CNT__W 14 +#define EC_OC_REG_OCR_MON_CNT__M 0x3FFF +#define EC_OC_REG_OCR_MON_CNT_INIT 0x0 + +#define EC_OC_REG_OCR_MON_RDX__A 0x215003D +#define EC_OC_REG_OCR_MON_RDX__W 1 +#define EC_OC_REG_OCR_MON_RDX__M 0x1 +#define EC_OC_REG_OCR_MON_RDX_INIT 0x0 + +#define EC_OC_REG_OCR_MON_RD0__A 0x215003E +#define EC_OC_REG_OCR_MON_RD0__W 10 +#define EC_OC_REG_OCR_MON_RD0__M 0x3FF + +#define EC_OC_REG_OCR_MON_RD1__A 0x215003F +#define EC_OC_REG_OCR_MON_RD1__W 10 +#define EC_OC_REG_OCR_MON_RD1__M 0x3FF + +#define EC_OC_REG_OCR_MON_RD2__A 0x2150040 +#define EC_OC_REG_OCR_MON_RD2__W 10 +#define EC_OC_REG_OCR_MON_RD2__M 0x3FF + +#define EC_OC_REG_OCR_MON_RD3__A 0x2150041 +#define EC_OC_REG_OCR_MON_RD3__W 10 +#define EC_OC_REG_OCR_MON_RD3__M 0x3FF + +#define EC_OC_REG_OCR_MON_RD4__A 0x2150042 +#define EC_OC_REG_OCR_MON_RD4__W 10 +#define EC_OC_REG_OCR_MON_RD4__M 0x3FF + +#define EC_OC_REG_OCR_MON_RD5__A 0x2150043 +#define EC_OC_REG_OCR_MON_RD5__W 10 +#define EC_OC_REG_OCR_MON_RD5__M 0x3FF + +#define EC_OC_REG_OCR_INV_MON__A 0x2150044 +#define EC_OC_REG_OCR_INV_MON__W 12 +#define EC_OC_REG_OCR_INV_MON__M 0xFFF +#define EC_OC_REG_OCR_INV_MON_INIT 0x0 + +#define EC_OC_REG_IPR_INV_MPG__A 0x2150045 +#define EC_OC_REG_IPR_INV_MPG__W 12 +#define EC_OC_REG_IPR_INV_MPG__M 0xFFF +#define EC_OC_REG_IPR_INV_MPG_INIT 0x0 + +#define EC_OC_REG_IPR_MSR_SNC__A 0x2150046 +#define EC_OC_REG_IPR_MSR_SNC__W 6 +#define EC_OC_REG_IPR_MSR_SNC__M 0x3F +#define EC_OC_REG_IPR_MSR_SNC_INIT 0x0 + +#define EC_OC_RAM__A 0x2160000 + +#define CC_SID 0x1B + +#define CC_COMM_EXEC__A 0x2400000 +#define CC_COMM_EXEC__W 3 +#define CC_COMM_EXEC__M 0x7 +#define CC_COMM_EXEC_CTL__B 0 +#define CC_COMM_EXEC_CTL__W 3 +#define CC_COMM_EXEC_CTL__M 0x7 +#define CC_COMM_EXEC_CTL_STOP 0x0 +#define CC_COMM_EXEC_CTL_ACTIVE 0x1 +#define CC_COMM_EXEC_CTL_HOLD 0x2 +#define CC_COMM_EXEC_CTL_STEP 0x3 +#define CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define CC_COMM_STATE__A 0x2400001 +#define CC_COMM_STATE__W 16 +#define CC_COMM_STATE__M 0xFFFF +#define CC_COMM_MB__A 0x2400002 +#define CC_COMM_MB__W 16 +#define CC_COMM_MB__M 0xFFFF +#define CC_COMM_SERVICE0__A 0x2400003 +#define CC_COMM_SERVICE0__W 16 +#define CC_COMM_SERVICE0__M 0xFFFF +#define CC_COMM_SERVICE1__A 0x2400004 +#define CC_COMM_SERVICE1__W 16 +#define CC_COMM_SERVICE1__M 0xFFFF +#define CC_COMM_INT_STA__A 0x2400007 +#define CC_COMM_INT_STA__W 16 +#define CC_COMM_INT_STA__M 0xFFFF +#define CC_COMM_INT_MSK__A 0x2400008 +#define CC_COMM_INT_MSK__W 16 +#define CC_COMM_INT_MSK__M 0xFFFF + +#define CC_REG_COMM_EXEC__A 0x2410000 +#define CC_REG_COMM_EXEC__W 3 +#define CC_REG_COMM_EXEC__M 0x7 +#define CC_REG_COMM_EXEC_CTL__B 0 +#define CC_REG_COMM_EXEC_CTL__W 3 +#define CC_REG_COMM_EXEC_CTL__M 0x7 +#define CC_REG_COMM_EXEC_CTL_STOP 0x0 +#define CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define CC_REG_COMM_EXEC_CTL_HOLD 0x2 +#define CC_REG_COMM_EXEC_CTL_STEP 0x3 +#define CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define CC_REG_COMM_STATE__A 0x2410001 +#define CC_REG_COMM_STATE__W 16 +#define CC_REG_COMM_STATE__M 0xFFFF +#define CC_REG_COMM_MB__A 0x2410002 +#define CC_REG_COMM_MB__W 16 +#define CC_REG_COMM_MB__M 0xFFFF +#define CC_REG_COMM_SERVICE0__A 0x2410003 +#define CC_REG_COMM_SERVICE0__W 16 +#define CC_REG_COMM_SERVICE0__M 0xFFFF +#define CC_REG_COMM_SERVICE1__A 0x2410004 +#define CC_REG_COMM_SERVICE1__W 16 +#define CC_REG_COMM_SERVICE1__M 0xFFFF +#define CC_REG_COMM_INT_STA__A 0x2410007 +#define CC_REG_COMM_INT_STA__W 16 +#define CC_REG_COMM_INT_STA__M 0xFFFF +#define CC_REG_COMM_INT_MSK__A 0x2410008 +#define CC_REG_COMM_INT_MSK__W 16 +#define CC_REG_COMM_INT_MSK__M 0xFFFF + +#define CC_REG_OSC_MODE__A 0x2410010 +#define CC_REG_OSC_MODE__W 2 +#define CC_REG_OSC_MODE__M 0x3 +#define CC_REG_OSC_MODE_OHW 0x0 +#define CC_REG_OSC_MODE_M20 0x1 +#define CC_REG_OSC_MODE_M48 0x2 + +#define CC_REG_PLL_MODE__A 0x2410011 +#define CC_REG_PLL_MODE__W 6 +#define CC_REG_PLL_MODE__M 0x3F +#define CC_REG_PLL_MODE_INIT 0xC +#define CC_REG_PLL_MODE_BYPASS__B 0 +#define CC_REG_PLL_MODE_BYPASS__W 2 +#define CC_REG_PLL_MODE_BYPASS__M 0x3 +#define CC_REG_PLL_MODE_BYPASS_OHW 0x0 +#define CC_REG_PLL_MODE_BYPASS_PLL 0x1 +#define CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 +#define CC_REG_PLL_MODE_PUMP__B 2 +#define CC_REG_PLL_MODE_PUMP__W 3 +#define CC_REG_PLL_MODE_PUMP__M 0x1C +#define CC_REG_PLL_MODE_PUMP_OFF 0x0 +#define CC_REG_PLL_MODE_PUMP_CUR_08 0x4 +#define CC_REG_PLL_MODE_PUMP_CUR_09 0x8 +#define CC_REG_PLL_MODE_PUMP_CUR_10 0xC +#define CC_REG_PLL_MODE_PUMP_CUR_11 0x10 +#define CC_REG_PLL_MODE_PUMP_CUR_12 0x14 +#define CC_REG_PLL_MODE_OUT_EN__B 5 +#define CC_REG_PLL_MODE_OUT_EN__W 1 +#define CC_REG_PLL_MODE_OUT_EN__M 0x20 +#define CC_REG_PLL_MODE_OUT_EN_OFF 0x0 +#define CC_REG_PLL_MODE_OUT_EN_ON 0x20 + +#define CC_REG_REF_DIVIDE__A 0x2410012 +#define CC_REG_REF_DIVIDE__W 4 +#define CC_REG_REF_DIVIDE__M 0xF +#define CC_REG_REF_DIVIDE_INIT 0xA +#define CC_REG_REF_DIVIDE_OHW 0x0 +#define CC_REG_REF_DIVIDE_D01 0x1 +#define CC_REG_REF_DIVIDE_D02 0x2 +#define CC_REG_REF_DIVIDE_D03 0x3 +#define CC_REG_REF_DIVIDE_D04 0x4 +#define CC_REG_REF_DIVIDE_D05 0x5 +#define CC_REG_REF_DIVIDE_D06 0x6 +#define CC_REG_REF_DIVIDE_D07 0x7 +#define CC_REG_REF_DIVIDE_D08 0x8 +#define CC_REG_REF_DIVIDE_D09 0x9 +#define CC_REG_REF_DIVIDE_D10 0xA + +#define CC_REG_REF_DELAY__A 0x2410013 +#define CC_REG_REF_DELAY__W 3 +#define CC_REG_REF_DELAY__M 0x7 +#define CC_REG_REF_DELAY_EDGE__B 0 +#define CC_REG_REF_DELAY_EDGE__W 1 +#define CC_REG_REF_DELAY_EDGE__M 0x1 +#define CC_REG_REF_DELAY_EDGE_POS 0x0 +#define CC_REG_REF_DELAY_EDGE_NEG 0x1 +#define CC_REG_REF_DELAY_DELAY__B 1 +#define CC_REG_REF_DELAY_DELAY__W 2 +#define CC_REG_REF_DELAY_DELAY__M 0x6 +#define CC_REG_REF_DELAY_DELAY_DEL_0 0x0 +#define CC_REG_REF_DELAY_DELAY_DEL_3 0x2 +#define CC_REG_REF_DELAY_DELAY_DEL_6 0x4 +#define CC_REG_REF_DELAY_DELAY_DEL_9 0x6 + +#define CC_REG_CLK_DELAY__A 0x2410014 +#define CC_REG_CLK_DELAY__W 4 +#define CC_REG_CLK_DELAY__M 0xF +#define CC_REG_CLK_DELAY_OFF 0x0 + +#define CC_REG_PWD_MODE__A 0x2410015 +#define CC_REG_PWD_MODE__W 2 +#define CC_REG_PWD_MODE__M 0x3 +#define CC_REG_PWD_MODE_UP 0x0 +#define CC_REG_PWD_MODE_DOWN_CLK 0x1 +#define CC_REG_PWD_MODE_DOWN_PLL 0x2 +#define CC_REG_PWD_MODE_DOWN_OSC 0x3 + +#define CC_REG_SOFT_RST__A 0x2410016 +#define CC_REG_SOFT_RST__W 2 +#define CC_REG_SOFT_RST__M 0x3 +#define CC_REG_SOFT_RST_SYS__B 0 +#define CC_REG_SOFT_RST_SYS__W 1 +#define CC_REG_SOFT_RST_SYS__M 0x1 +#define CC_REG_SOFT_RST_OSC__B 1 +#define CC_REG_SOFT_RST_OSC__W 1 +#define CC_REG_SOFT_RST_OSC__M 0x2 + +#define CC_REG_UPDATE__A 0x2410017 +#define CC_REG_UPDATE__W 16 +#define CC_REG_UPDATE__M 0xFFFF +#define CC_REG_UPDATE_KEY 0x3973 + +#define CC_REG_PLL_LOCK__A 0x2410018 +#define CC_REG_PLL_LOCK__W 1 +#define CC_REG_PLL_LOCK__M 0x1 +#define CC_REG_PLL_LOCK_LOCK 0x1 + +#define CC_REG_JTAGID_L__A 0x2410019 +#define CC_REG_JTAGID_L__W 16 +#define CC_REG_JTAGID_L__M 0xFFFF +#define CC_REG_JTAGID_L_INIT 0x0 + +#define CC_REG_JTAGID_H__A 0x241001A +#define CC_REG_JTAGID_H__W 16 +#define CC_REG_JTAGID_H__M 0xFFFF +#define CC_REG_JTAGID_H_INIT 0x0 + +#define LC_SID 0x1C + +#define LC_COMM_EXEC__A 0x2800000 +#define LC_COMM_EXEC__W 3 +#define LC_COMM_EXEC__M 0x7 +#define LC_COMM_EXEC_CTL__B 0 +#define LC_COMM_EXEC_CTL__W 3 +#define LC_COMM_EXEC_CTL__M 0x7 +#define LC_COMM_EXEC_CTL_STOP 0x0 +#define LC_COMM_EXEC_CTL_ACTIVE 0x1 +#define LC_COMM_EXEC_CTL_HOLD 0x2 +#define LC_COMM_EXEC_CTL_STEP 0x3 +#define LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define LC_COMM_STATE__A 0x2800001 +#define LC_COMM_STATE__W 16 +#define LC_COMM_STATE__M 0xFFFF +#define LC_COMM_MB__A 0x2800002 +#define LC_COMM_MB__W 16 +#define LC_COMM_MB__M 0xFFFF +#define LC_COMM_SERVICE0__A 0x2800003 +#define LC_COMM_SERVICE0__W 16 +#define LC_COMM_SERVICE0__M 0xFFFF +#define LC_COMM_SERVICE1__A 0x2800004 +#define LC_COMM_SERVICE1__W 16 +#define LC_COMM_SERVICE1__M 0xFFFF +#define LC_COMM_INT_STA__A 0x2800007 +#define LC_COMM_INT_STA__W 16 +#define LC_COMM_INT_STA__M 0xFFFF +#define LC_COMM_INT_MSK__A 0x2800008 +#define LC_COMM_INT_MSK__W 16 +#define LC_COMM_INT_MSK__M 0xFFFF + +#define LC_CT_REG_COMM_EXEC__A 0x2810000 +#define LC_CT_REG_COMM_EXEC__W 3 +#define LC_CT_REG_COMM_EXEC__M 0x7 +#define LC_CT_REG_COMM_EXEC_CTL__B 0 +#define LC_CT_REG_COMM_EXEC_CTL__W 3 +#define LC_CT_REG_COMM_EXEC_CTL__M 0x7 +#define LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 + +#define LC_CT_REG_COMM_STATE__A 0x2810001 +#define LC_CT_REG_COMM_STATE__W 10 +#define LC_CT_REG_COMM_STATE__M 0x3FF +#define LC_CT_REG_COMM_SERVICE0__A 0x2810003 +#define LC_CT_REG_COMM_SERVICE0__W 16 +#define LC_CT_REG_COMM_SERVICE0__M 0xFFFF +#define LC_CT_REG_COMM_SERVICE1__A 0x2810004 +#define LC_CT_REG_COMM_SERVICE1__W 16 +#define LC_CT_REG_COMM_SERVICE1__M 0xFFFF +#define LC_CT_REG_COMM_SERVICE1_LC__B 12 +#define LC_CT_REG_COMM_SERVICE1_LC__W 1 +#define LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 + +#define LC_CT_REG_COMM_INT_STA__A 0x2810007 +#define LC_CT_REG_COMM_INT_STA__W 1 +#define LC_CT_REG_COMM_INT_STA__M 0x1 +#define LC_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define LC_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + +#define LC_CT_REG_COMM_INT_MSK__A 0x2810008 +#define LC_CT_REG_COMM_INT_MSK__W 1 +#define LC_CT_REG_COMM_INT_MSK__M 0x1 +#define LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + +#define LC_CT_REG_CTL_STK__AX 0x2810010 +#define LC_CT_REG_CTL_STK__XSZ 4 +#define LC_CT_REG_CTL_STK__W 10 +#define LC_CT_REG_CTL_STK__M 0x3FF + +#define LC_CT_REG_CTL_BPT_IDX__A 0x281001F +#define LC_CT_REG_CTL_BPT_IDX__W 1 +#define LC_CT_REG_CTL_BPT_IDX__M 0x1 + +#define LC_CT_REG_CTL_BPT__A 0x2810020 +#define LC_CT_REG_CTL_BPT__W 10 +#define LC_CT_REG_CTL_BPT__M 0x3FF + +#define LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 +#define LC_RA_RAM_PROC_DELAY_IF__W 16 +#define LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF +#define LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 +#define LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 +#define LC_RA_RAM_PROC_DELAY_FS__W 16 +#define LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF +#define LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 +#define LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 +#define LC_RA_RAM_LOCK_TH_CRMM__W 16 +#define LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF +#define LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 +#define LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 +#define LC_RA_RAM_LOCK_TH_SRMM__W 16 +#define LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF +#define LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 +#define LC_RA_RAM_LOCK_COUNT__A 0x282000A +#define LC_RA_RAM_LOCK_COUNT__W 16 +#define LC_RA_RAM_LOCK_COUNT__M 0xFFFF +#define LC_RA_RAM_CPRTOFS_NOM__A 0x282000B +#define LC_RA_RAM_CPRTOFS_NOM__W 16 +#define LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF +#define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C +#define LC_RA_RAM_IFINCR_NOM_L__W 16 +#define LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF +#define LC_RA_RAM_IFINCR_NOM_H__A 0x282000D +#define LC_RA_RAM_IFINCR_NOM_H__W 16 +#define LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF +#define LC_RA_RAM_FSINCR_NOM_L__A 0x282000E +#define LC_RA_RAM_FSINCR_NOM_L__W 16 +#define LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF +#define LC_RA_RAM_FSINCR_NOM_H__A 0x282000F +#define LC_RA_RAM_FSINCR_NOM_H__W 16 +#define LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF +#define LC_RA_RAM_MODE_2K__A 0x2820010 +#define LC_RA_RAM_MODE_2K__W 16 +#define LC_RA_RAM_MODE_2K__M 0xFFFF +#define LC_RA_RAM_MODE_GUARD__A 0x2820011 +#define LC_RA_RAM_MODE_GUARD__W 16 +#define LC_RA_RAM_MODE_GUARD__M 0xFFFF +#define LC_RA_RAM_MODE_GUARD_32 0x0 +#define LC_RA_RAM_MODE_GUARD_16 0x1 +#define LC_RA_RAM_MODE_GUARD_8 0x2 +#define LC_RA_RAM_MODE_GUARD_4 0x3 + +#define LC_RA_RAM_MODE_ADJUST__A 0x2820012 +#define LC_RA_RAM_MODE_ADJUST__W 16 +#define LC_RA_RAM_MODE_ADJUST__M 0xFFFF +#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 +#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 +#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 +#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 +#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 +#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 +#define LC_RA_RAM_MODE_ADJUST_SRMM__B 2 +#define LC_RA_RAM_MODE_ADJUST_SRMM__W 1 +#define LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 +#define LC_RA_RAM_MODE_ADJUST_PHASE__B 3 +#define LC_RA_RAM_MODE_ADJUST_PHASE__W 1 +#define LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 +#define LC_RA_RAM_MODE_ADJUST_DELAY__B 4 +#define LC_RA_RAM_MODE_ADJUST_DELAY__W 1 +#define LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 +#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 +#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 +#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 +#define LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 +#define LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 +#define LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 +#define LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 +#define LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 +#define LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 +#define LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 +#define LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 +#define LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 +#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 +#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 +#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 + +#define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A +#define LC_RA_RAM_FILTER_SYM_SET__W 16 +#define LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF +#define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 +#define LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B +#define LC_RA_RAM_FILTER_SYM_CUR__W 16 +#define LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF +#define LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 +#define LC_RA_RAM_MAX_ABS_EXP__A 0x282001D +#define LC_RA_RAM_MAX_ABS_EXP__W 16 +#define LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF +#define LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 +#define LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F +#define LC_RA_RAM_ACTUAL_CP_CRMM__W 16 +#define LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF +#define LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 +#define LC_RA_RAM_ACTUAL_CE_CRMM__W 16 +#define LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF +#define LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 +#define LC_RA_RAM_ACTUAL_CE_SRMM__W 16 +#define LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF +#define LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 +#define LC_RA_RAM_ACTUAL_PHASE__W 16 +#define LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF +#define LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 +#define LC_RA_RAM_ACTUAL_DELAY__W 16 +#define LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF +#define LC_RA_RAM_ADJUST_CRMM__A 0x2820024 +#define LC_RA_RAM_ADJUST_CRMM__W 16 +#define LC_RA_RAM_ADJUST_CRMM__M 0xFFFF +#define LC_RA_RAM_ADJUST_SRMM__A 0x2820025 +#define LC_RA_RAM_ADJUST_SRMM__W 16 +#define LC_RA_RAM_ADJUST_SRMM__M 0xFFFF +#define LC_RA_RAM_ADJUST_PHASE__A 0x2820026 +#define LC_RA_RAM_ADJUST_PHASE__W 16 +#define LC_RA_RAM_ADJUST_PHASE__M 0xFFFF +#define LC_RA_RAM_ADJUST_DELAY__A 0x2820027 +#define LC_RA_RAM_ADJUST_DELAY__W 16 +#define LC_RA_RAM_ADJUST_DELAY__M 0xFFFF + +#define LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 +#define LC_RA_RAM_PIPE_CP_PHASE_0__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 +#define LC_RA_RAM_PIPE_CP_PHASE_1__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A +#define LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B +#define LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C +#define LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D +#define LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 +#define LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF + +#define LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 +#define LC_RA_RAM_PIPE_CP_CRMM_0__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 +#define LC_RA_RAM_PIPE_CP_CRMM_1__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 +#define LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 +#define LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 +#define LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 +#define LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 +#define LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF + +#define LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 +#define LC_RA_RAM_PIPE_CP_SRMM_0__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 +#define LC_RA_RAM_PIPE_CP_SRMM_1__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A +#define LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B +#define LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C +#define LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF +#define LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D +#define LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 +#define LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF + +#define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 +#define LC_RA_RAM_FILTER_CRMM_A__W 16 +#define LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF +#define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 +#define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 +#define LC_RA_RAM_FILTER_CRMM_B__W 16 +#define LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF +#define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 +#define LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 +#define LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 +#define LC_RA_RAM_FILTER_CRMM_Z1__W 16 +#define LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF +#define LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 +#define LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 +#define LC_RA_RAM_FILTER_CRMM_Z2__W 16 +#define LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF +#define LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 +#define LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 +#define LC_RA_RAM_FILTER_CRMM_TMP__W 16 +#define LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF + +#define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 +#define LC_RA_RAM_FILTER_SRMM_A__W 16 +#define LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF +#define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 +#define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 +#define LC_RA_RAM_FILTER_SRMM_B__W 16 +#define LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF +#define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 +#define LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A +#define LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 +#define LC_RA_RAM_FILTER_SRMM_Z1__W 16 +#define LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF +#define LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C +#define LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 +#define LC_RA_RAM_FILTER_SRMM_Z2__W 16 +#define LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF +#define LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E +#define LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 +#define LC_RA_RAM_FILTER_SRMM_TMP__W 16 +#define LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF + +#define LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 +#define LC_RA_RAM_FILTER_PHASE_A__W 16 +#define LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF +#define LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 +#define LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 +#define LC_RA_RAM_FILTER_PHASE_B__W 16 +#define LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF +#define LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 +#define LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 +#define LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 +#define LC_RA_RAM_FILTER_PHASE_Z1__W 16 +#define LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF +#define LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 +#define LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 +#define LC_RA_RAM_FILTER_PHASE_Z2__W 16 +#define LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF +#define LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 +#define LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 +#define LC_RA_RAM_FILTER_PHASE_TMP__W 16 +#define LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF + +#define LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 +#define LC_RA_RAM_FILTER_DELAY_A__W 16 +#define LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF +#define LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 +#define LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 +#define LC_RA_RAM_FILTER_DELAY_B__W 16 +#define LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF +#define LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 +#define LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A +#define LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 +#define LC_RA_RAM_FILTER_DELAY_Z1__W 16 +#define LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF +#define LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C +#define LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 +#define LC_RA_RAM_FILTER_DELAY_Z2__W 16 +#define LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF +#define LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E +#define LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 +#define LC_RA_RAM_FILTER_DELAY_TMP__W 16 +#define LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF + +#define LC_IF_RAM_TRP_BPT0__AX 0x2830000 +#define LC_IF_RAM_TRP_BPT0__XSZ 2 +#define LC_IF_RAM_TRP_BPT0__W 12 +#define LC_IF_RAM_TRP_BPT0__M 0xFFF + +#define LC_IF_RAM_TRP_STKU__AX 0x2830002 +#define LC_IF_RAM_TRP_STKU__XSZ 2 +#define LC_IF_RAM_TRP_STKU__W 12 +#define LC_IF_RAM_TRP_STKU__M 0xFFF + +#define LC_IF_RAM_TRP_WARM__AX 0x2830006 +#define LC_IF_RAM_TRP_WARM__XSZ 2 +#define LC_IF_RAM_TRP_WARM__W 12 +#define LC_IF_RAM_TRP_WARM__M 0xFFF + +#define B_HI_SID 0x10 + +#define B_HI_COMM_EXEC__A 0x400000 +#define B_HI_COMM_EXEC__W 3 +#define B_HI_COMM_EXEC__M 0x7 +#define B_HI_COMM_EXEC_CTL__B 0 +#define B_HI_COMM_EXEC_CTL__W 3 +#define B_HI_COMM_EXEC_CTL__M 0x7 +#define B_HI_COMM_EXEC_CTL_STOP 0x0 +#define B_HI_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_HI_COMM_EXEC_CTL_HOLD 0x2 +#define B_HI_COMM_EXEC_CTL_STEP 0x3 +#define B_HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_HI_COMM_STATE__A 0x400001 +#define B_HI_COMM_STATE__W 16 +#define B_HI_COMM_STATE__M 0xFFFF +#define B_HI_COMM_MB__A 0x400002 +#define B_HI_COMM_MB__W 16 +#define B_HI_COMM_MB__M 0xFFFF +#define B_HI_COMM_SERVICE0__A 0x400003 +#define B_HI_COMM_SERVICE0__W 16 +#define B_HI_COMM_SERVICE0__M 0xFFFF +#define B_HI_COMM_SERVICE1__A 0x400004 +#define B_HI_COMM_SERVICE1__W 16 +#define B_HI_COMM_SERVICE1__M 0xFFFF +#define B_HI_COMM_INT_STA__A 0x400007 +#define B_HI_COMM_INT_STA__W 16 +#define B_HI_COMM_INT_STA__M 0xFFFF +#define B_HI_COMM_INT_MSK__A 0x400008 +#define B_HI_COMM_INT_MSK__W 16 +#define B_HI_COMM_INT_MSK__M 0xFFFF + +#define B_HI_CT_REG_COMM_EXEC__A 0x410000 +#define B_HI_CT_REG_COMM_EXEC__W 3 +#define B_HI_CT_REG_COMM_EXEC__M 0x7 +#define B_HI_CT_REG_COMM_EXEC_CTL__B 0 +#define B_HI_CT_REG_COMM_EXEC_CTL__W 3 +#define B_HI_CT_REG_COMM_EXEC_CTL__M 0x7 +#define B_HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_HI_CT_REG_COMM_STATE__A 0x410001 +#define B_HI_CT_REG_COMM_STATE__W 10 +#define B_HI_CT_REG_COMM_STATE__M 0x3FF +#define B_HI_CT_REG_COMM_SERVICE0__A 0x410003 +#define B_HI_CT_REG_COMM_SERVICE0__W 16 +#define B_HI_CT_REG_COMM_SERVICE0__M 0xFFFF +#define B_HI_CT_REG_COMM_SERVICE1__A 0x410004 +#define B_HI_CT_REG_COMM_SERVICE1__W 16 +#define B_HI_CT_REG_COMM_SERVICE1__M 0xFFFF +#define B_HI_CT_REG_COMM_SERVICE1_HI__B 0 +#define B_HI_CT_REG_COMM_SERVICE1_HI__W 1 +#define B_HI_CT_REG_COMM_SERVICE1_HI__M 0x1 + +#define B_HI_CT_REG_COMM_INT_STA__A 0x410007 +#define B_HI_CT_REG_COMM_INT_STA__W 1 +#define B_HI_CT_REG_COMM_INT_STA__M 0x1 +#define B_HI_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define B_HI_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define B_HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + +#define B_HI_CT_REG_COMM_INT_MSK__A 0x410008 +#define B_HI_CT_REG_COMM_INT_MSK__W 1 +#define B_HI_CT_REG_COMM_INT_MSK__M 0x1 +#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + +#define B_HI_CT_REG_CTL_STK__AX 0x410010 +#define B_HI_CT_REG_CTL_STK__XSZ 4 +#define B_HI_CT_REG_CTL_STK__W 10 +#define B_HI_CT_REG_CTL_STK__M 0x3FF + +#define B_HI_CT_REG_CTL_BPT_IDX__A 0x41001F +#define B_HI_CT_REG_CTL_BPT_IDX__W 1 +#define B_HI_CT_REG_CTL_BPT_IDX__M 0x1 + +#define B_HI_CT_REG_CTL_BPT__A 0x410020 +#define B_HI_CT_REG_CTL_BPT__W 10 +#define B_HI_CT_REG_CTL_BPT__M 0x3FF + +#define B_HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 +#define B_HI_RA_RAM_SLV0_FLG_SMM__W 1 +#define B_HI_RA_RAM_SLV0_FLG_SMM__M 0x1 +#define B_HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 +#define B_HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 + +#define B_HI_RA_RAM_SLV0_DEV_ID__A 0x420011 +#define B_HI_RA_RAM_SLV0_DEV_ID__W 7 +#define B_HI_RA_RAM_SLV0_DEV_ID__M 0x7F + +#define B_HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 +#define B_HI_RA_RAM_SLV0_FLG_CRC__W 1 +#define B_HI_RA_RAM_SLV0_FLG_CRC__M 0x1 +#define B_HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 +#define B_HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 + +#define B_HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 +#define B_HI_RA_RAM_SLV0_FLG_ACC__W 3 +#define B_HI_RA_RAM_SLV0_FLG_ACC__M 0x7 +#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 +#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 +#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 +#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 +#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 +#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 +#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 +#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 +#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 +#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 + +#define B_HI_RA_RAM_SLV0_STATE__A 0x420014 +#define B_HI_RA_RAM_SLV0_STATE__W 1 +#define B_HI_RA_RAM_SLV0_STATE__M 0x1 +#define B_HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 +#define B_HI_RA_RAM_SLV0_STATE_DATA 0x1 + +#define B_HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 +#define B_HI_RA_RAM_SLV0_BLK_BNK__W 12 +#define B_HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF +#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 +#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 +#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F +#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 +#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 +#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 + +#define B_HI_RA_RAM_SLV0_ADDR__A 0x420016 +#define B_HI_RA_RAM_SLV0_ADDR__W 16 +#define B_HI_RA_RAM_SLV0_ADDR__M 0xFFFF + +#define B_HI_RA_RAM_SLV0_CRC__A 0x420017 +#define B_HI_RA_RAM_SLV0_CRC__W 16 +#define B_HI_RA_RAM_SLV0_CRC__M 0xFFFF + +#define B_HI_RA_RAM_SLV0_READBACK__A 0x420018 +#define B_HI_RA_RAM_SLV0_READBACK__W 16 +#define B_HI_RA_RAM_SLV0_READBACK__M 0xFFFF + +#define B_HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 +#define B_HI_RA_RAM_SLV1_FLG_SMM__W 1 +#define B_HI_RA_RAM_SLV1_FLG_SMM__M 0x1 +#define B_HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 +#define B_HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 + +#define B_HI_RA_RAM_SLV1_DEV_ID__A 0x420021 +#define B_HI_RA_RAM_SLV1_DEV_ID__W 7 +#define B_HI_RA_RAM_SLV1_DEV_ID__M 0x7F + +#define B_HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 +#define B_HI_RA_RAM_SLV1_FLG_CRC__W 1 +#define B_HI_RA_RAM_SLV1_FLG_CRC__M 0x1 +#define B_HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 +#define B_HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 + +#define B_HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 +#define B_HI_RA_RAM_SLV1_FLG_ACC__W 3 +#define B_HI_RA_RAM_SLV1_FLG_ACC__M 0x7 +#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 +#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 +#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 +#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 +#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 +#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 +#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 +#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 +#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 +#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 + +#define B_HI_RA_RAM_SLV1_STATE__A 0x420024 +#define B_HI_RA_RAM_SLV1_STATE__W 1 +#define B_HI_RA_RAM_SLV1_STATE__M 0x1 +#define B_HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 +#define B_HI_RA_RAM_SLV1_STATE_DATA 0x1 + +#define B_HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 +#define B_HI_RA_RAM_SLV1_BLK_BNK__W 12 +#define B_HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF +#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 +#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 +#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F +#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 +#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 +#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 + +#define B_HI_RA_RAM_SLV1_ADDR__A 0x420026 +#define B_HI_RA_RAM_SLV1_ADDR__W 16 +#define B_HI_RA_RAM_SLV1_ADDR__M 0xFFFF + +#define B_HI_RA_RAM_SLV1_CRC__A 0x420027 +#define B_HI_RA_RAM_SLV1_CRC__W 16 +#define B_HI_RA_RAM_SLV1_CRC__M 0xFFFF + +#define B_HI_RA_RAM_SLV1_READBACK__A 0x420028 +#define B_HI_RA_RAM_SLV1_READBACK__W 16 +#define B_HI_RA_RAM_SLV1_READBACK__M 0xFFFF + +#define B_HI_RA_RAM_SRV_SEM__A 0x420030 +#define B_HI_RA_RAM_SRV_SEM__W 1 +#define B_HI_RA_RAM_SRV_SEM__M 0x1 +#define B_HI_RA_RAM_SRV_SEM_FREE 0x0 +#define B_HI_RA_RAM_SRV_SEM_CLAIMED 0x1 + +#define B_HI_RA_RAM_SRV_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_RES__W 3 +#define B_HI_RA_RAM_SRV_RES__M 0x7 +#define B_HI_RA_RAM_SRV_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 +#define B_HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 +#define B_HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 +#define B_HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 + +#define B_HI_RA_RAM_SRV_CMD__A 0x420032 +#define B_HI_RA_RAM_SRV_CMD__W 3 +#define B_HI_RA_RAM_SRV_CMD__M 0x7 +#define B_HI_RA_RAM_SRV_CMD_NULL 0x0 +#define B_HI_RA_RAM_SRV_CMD_UIO 0x1 +#define B_HI_RA_RAM_SRV_CMD_RESET 0x2 +#define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3 +#define B_HI_RA_RAM_SRV_CMD_COPY 0x4 +#define B_HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 +#define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 + +#define B_HI_RA_RAM_SRV_PAR__AX 0x420033 +#define B_HI_RA_RAM_SRV_PAR__XSZ 5 +#define B_HI_RA_RAM_SRV_PAR__W 16 +#define B_HI_RA_RAM_SRV_PAR__M 0xFFFF + +#define B_HI_RA_RAM_SRV_NOP_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_NOP_RES__W 3 +#define B_HI_RA_RAM_SRV_NOP_RES__M 0x7 +#define B_HI_RA_RAM_SRV_NOP_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 + +#define B_HI_RA_RAM_SRV_UIO_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_UIO_RES__W 3 +#define B_HI_RA_RAM_SRV_UIO_RES__M 0x7 +#define B_HI_RA_RAM_SRV_UIO_RES_LO 0x0 +#define B_HI_RA_RAM_SRV_UIO_RES_HI 0x1 + +#define B_HI_RA_RAM_SRV_UIO_KEY__A 0x420033 +#define B_HI_RA_RAM_SRV_UIO_KEY__W 16 +#define B_HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF +#define B_HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 + +#define B_HI_RA_RAM_SRV_UIO_SEL__A 0x420034 +#define B_HI_RA_RAM_SRV_UIO_SEL__W 2 +#define B_HI_RA_RAM_SRV_UIO_SEL__M 0x3 +#define B_HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 +#define B_HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 + +#define B_HI_RA_RAM_SRV_UIO_SET__A 0x420035 +#define B_HI_RA_RAM_SRV_UIO_SET__W 2 +#define B_HI_RA_RAM_SRV_UIO_SET__M 0x3 +#define B_HI_RA_RAM_SRV_UIO_SET_OUT__B 0 +#define B_HI_RA_RAM_SRV_UIO_SET_OUT__W 1 +#define B_HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 +#define B_HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 +#define B_HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 +#define B_HI_RA_RAM_SRV_UIO_SET_DIR__B 1 +#define B_HI_RA_RAM_SRV_UIO_SET_DIR__W 1 +#define B_HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 +#define B_HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 +#define B_HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 + +#define B_HI_RA_RAM_SRV_RST_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_RST_RES__W 1 +#define B_HI_RA_RAM_SRV_RST_RES__M 0x1 +#define B_HI_RA_RAM_SRV_RST_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_RST_RES_ERROR 0x1 + +#define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033 +#define B_HI_RA_RAM_SRV_RST_KEY__W 16 +#define B_HI_RA_RAM_SRV_RST_KEY__M 0xFFFF +#define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 + +#define B_HI_RA_RAM_SRV_CFG_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_CFG_RES__W 1 +#define B_HI_RA_RAM_SRV_CFG_RES__M 0x1 +#define B_HI_RA_RAM_SRV_CFG_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 + +#define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033 +#define B_HI_RA_RAM_SRV_CFG_KEY__W 16 +#define B_HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF +#define B_HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 + +#define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 +#define B_HI_RA_RAM_SRV_CFG_DIV__W 5 +#define B_HI_RA_RAM_SRV_CFG_DIV__M 0x1F + +#define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035 +#define B_HI_RA_RAM_SRV_CFG_BDL__W 6 +#define B_HI_RA_RAM_SRV_CFG_BDL__M 0x3F + +#define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036 +#define B_HI_RA_RAM_SRV_CFG_WUP__W 8 +#define B_HI_RA_RAM_SRV_CFG_WUP__M 0xFF + +#define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037 +#define B_HI_RA_RAM_SRV_CFG_ACT__W 4 +#define B_HI_RA_RAM_SRV_CFG_ACT__M 0xF +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 +#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 +#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 +#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 +#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 +#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 +#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 +#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 +#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 +#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 +#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 +#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 + +#define B_HI_RA_RAM_SRV_CPY_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_CPY_RES__W 1 +#define B_HI_RA_RAM_SRV_CPY_RES__M 0x1 +#define B_HI_RA_RAM_SRV_CPY_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 + +#define B_HI_RA_RAM_SRV_CPY_SBB__A 0x420033 +#define B_HI_RA_RAM_SRV_CPY_SBB__W 12 +#define B_HI_RA_RAM_SRV_CPY_SBB__M 0xFFF +#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 +#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 +#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F +#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 +#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 +#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 + +#define B_HI_RA_RAM_SRV_CPY_SAD__A 0x420034 +#define B_HI_RA_RAM_SRV_CPY_SAD__W 16 +#define B_HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF + +#define B_HI_RA_RAM_SRV_CPY_LEN__A 0x420035 +#define B_HI_RA_RAM_SRV_CPY_LEN__W 16 +#define B_HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF + +#define B_HI_RA_RAM_SRV_CPY_DBB__A 0x420033 +#define B_HI_RA_RAM_SRV_CPY_DBB__W 12 +#define B_HI_RA_RAM_SRV_CPY_DBB__M 0xFFF +#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 +#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 +#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F +#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 +#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 +#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 + +#define B_HI_RA_RAM_SRV_CPY_DAD__A 0x420034 +#define B_HI_RA_RAM_SRV_CPY_DAD__W 16 +#define B_HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF + +#define B_HI_RA_RAM_SRV_TRM_RES__A 0x420031 +#define B_HI_RA_RAM_SRV_TRM_RES__W 2 +#define B_HI_RA_RAM_SRV_TRM_RES__M 0x3 +#define B_HI_RA_RAM_SRV_TRM_RES_OK 0x0 +#define B_HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 +#define B_HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 + +#define B_HI_RA_RAM_SRV_TRM_MST__A 0x420033 +#define B_HI_RA_RAM_SRV_TRM_MST__W 12 +#define B_HI_RA_RAM_SRV_TRM_MST__M 0xFFF + +#define B_HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 +#define B_HI_RA_RAM_SRV_TRM_SEQ__W 7 +#define B_HI_RA_RAM_SRV_TRM_SEQ__M 0x7F + +#define B_HI_RA_RAM_SRV_TRM_TRM__A 0x420035 +#define B_HI_RA_RAM_SRV_TRM_TRM__W 15 +#define B_HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF +#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 +#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 +#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF + +#define B_HI_RA_RAM_SRV_TRM_DBB__A 0x420033 +#define B_HI_RA_RAM_SRV_TRM_DBB__W 12 +#define B_HI_RA_RAM_SRV_TRM_DBB__M 0xFFF +#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 +#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 +#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F +#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 +#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 +#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 + +#define B_HI_RA_RAM_SRV_TRM_DAD__A 0x420034 +#define B_HI_RA_RAM_SRV_TRM_DAD__W 16 +#define B_HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF + +#define B_HI_RA_RAM_USR_BEGIN__A 0x420040 +#define B_HI_RA_RAM_USR_BEGIN__W 16 +#define B_HI_RA_RAM_USR_BEGIN__M 0xFFFF + +#define B_HI_RA_RAM_USR_END__A 0x42007F +#define B_HI_RA_RAM_USR_END__W 16 +#define B_HI_RA_RAM_USR_END__M 0xFFFF + +#define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 +#define B_HI_IF_RAM_TRP_BPT0__XSZ 2 +#define B_HI_IF_RAM_TRP_BPT0__W 12 +#define B_HI_IF_RAM_TRP_BPT0__M 0xFFF + +#define B_HI_IF_RAM_TRP_STKU__AX 0x430002 +#define B_HI_IF_RAM_TRP_STKU__XSZ 2 +#define B_HI_IF_RAM_TRP_STKU__W 12 +#define B_HI_IF_RAM_TRP_STKU__M 0xFFF + +#define B_HI_IF_RAM_USR_BEGIN__A 0x430200 +#define B_HI_IF_RAM_USR_BEGIN__W 12 +#define B_HI_IF_RAM_USR_BEGIN__M 0xFFF + +#define B_HI_IF_RAM_USR_END__A 0x4303FF +#define B_HI_IF_RAM_USR_END__W 12 +#define B_HI_IF_RAM_USR_END__M 0xFFF + +#define B_SC_SID 0x11 + +#define B_SC_COMM_EXEC__A 0x800000 +#define B_SC_COMM_EXEC__W 3 +#define B_SC_COMM_EXEC__M 0x7 +#define B_SC_COMM_EXEC_CTL__B 0 +#define B_SC_COMM_EXEC_CTL__W 3 +#define B_SC_COMM_EXEC_CTL__M 0x7 +#define B_SC_COMM_EXEC_CTL_STOP 0x0 +#define B_SC_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_SC_COMM_EXEC_CTL_HOLD 0x2 +#define B_SC_COMM_EXEC_CTL_STEP 0x3 +#define B_SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_SC_COMM_STATE__A 0x800001 +#define B_SC_COMM_STATE__W 16 +#define B_SC_COMM_STATE__M 0xFFFF +#define B_SC_COMM_MB__A 0x800002 +#define B_SC_COMM_MB__W 16 +#define B_SC_COMM_MB__M 0xFFFF +#define B_SC_COMM_SERVICE0__A 0x800003 +#define B_SC_COMM_SERVICE0__W 16 +#define B_SC_COMM_SERVICE0__M 0xFFFF +#define B_SC_COMM_SERVICE1__A 0x800004 +#define B_SC_COMM_SERVICE1__W 16 +#define B_SC_COMM_SERVICE1__M 0xFFFF +#define B_SC_COMM_INT_STA__A 0x800007 +#define B_SC_COMM_INT_STA__W 16 +#define B_SC_COMM_INT_STA__M 0xFFFF +#define B_SC_COMM_INT_MSK__A 0x800008 +#define B_SC_COMM_INT_MSK__W 16 +#define B_SC_COMM_INT_MSK__M 0xFFFF + +#define B_SC_CT_REG_COMM_EXEC__A 0x810000 +#define B_SC_CT_REG_COMM_EXEC__W 3 +#define B_SC_CT_REG_COMM_EXEC__M 0x7 +#define B_SC_CT_REG_COMM_EXEC_CTL__B 0 +#define B_SC_CT_REG_COMM_EXEC_CTL__W 3 +#define B_SC_CT_REG_COMM_EXEC_CTL__M 0x7 +#define B_SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_SC_CT_REG_COMM_STATE__A 0x810001 +#define B_SC_CT_REG_COMM_STATE__W 10 +#define B_SC_CT_REG_COMM_STATE__M 0x3FF +#define B_SC_CT_REG_COMM_SERVICE0__A 0x810003 +#define B_SC_CT_REG_COMM_SERVICE0__W 16 +#define B_SC_CT_REG_COMM_SERVICE0__M 0xFFFF +#define B_SC_CT_REG_COMM_SERVICE1__A 0x810004 +#define B_SC_CT_REG_COMM_SERVICE1__W 16 +#define B_SC_CT_REG_COMM_SERVICE1__M 0xFFFF +#define B_SC_CT_REG_COMM_SERVICE1_SC__B 1 +#define B_SC_CT_REG_COMM_SERVICE1_SC__W 1 +#define B_SC_CT_REG_COMM_SERVICE1_SC__M 0x2 + +#define B_SC_CT_REG_COMM_INT_STA__A 0x810007 +#define B_SC_CT_REG_COMM_INT_STA__W 1 +#define B_SC_CT_REG_COMM_INT_STA__M 0x1 +#define B_SC_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define B_SC_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define B_SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + +#define B_SC_CT_REG_COMM_INT_MSK__A 0x810008 +#define B_SC_CT_REG_COMM_INT_MSK__W 1 +#define B_SC_CT_REG_COMM_INT_MSK__M 0x1 +#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + +#define B_SC_CT_REG_CTL_STK__AX 0x810010 +#define B_SC_CT_REG_CTL_STK__XSZ 4 +#define B_SC_CT_REG_CTL_STK__W 10 +#define B_SC_CT_REG_CTL_STK__M 0x3FF + +#define B_SC_CT_REG_CTL_BPT_IDX__A 0x81001F +#define B_SC_CT_REG_CTL_BPT_IDX__W 1 +#define B_SC_CT_REG_CTL_BPT_IDX__M 0x1 + +#define B_SC_CT_REG_CTL_BPT__A 0x810020 +#define B_SC_CT_REG_CTL_BPT__W 10 +#define B_SC_CT_REG_CTL_BPT__M 0x3FF + +#define B_SC_RA_RAM_PARAM0__A 0x820040 +#define B_SC_RA_RAM_PARAM0__W 16 +#define B_SC_RA_RAM_PARAM0__M 0xFFFF +#define B_SC_RA_RAM_PARAM1__A 0x820041 +#define B_SC_RA_RAM_PARAM1__W 16 +#define B_SC_RA_RAM_PARAM1__M 0xFFFF +#define B_SC_RA_RAM_CMD_ADDR__A 0x820042 +#define B_SC_RA_RAM_CMD_ADDR__W 16 +#define B_SC_RA_RAM_CMD_ADDR__M 0xFFFF +#define B_SC_RA_RAM_CMD__A 0x820043 +#define B_SC_RA_RAM_CMD__W 16 +#define B_SC_RA_RAM_CMD__M 0xFFFF +#define B_SC_RA_RAM_CMD_NULL 0x0 +#define B_SC_RA_RAM_CMD_PROC_START 0x1 +#define B_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 +#define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 +#define B_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 +#define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 +#define B_SC_RA_RAM_CMD_USER_IO 0x6 +#define B_SC_RA_RAM_CMD_SET_TIMER 0x7 +#define B_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 +#define B_SC_RA_RAM_CMD_MAX 0x9 +#define B_SC_RA_RAM_CMDBLOCK__C 0x4 + +#define B_SC_RA_RAM_PROC_ACTIVATE__A 0x820044 +#define B_SC_RA_RAM_PROC_ACTIVATE__W 16 +#define B_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF +#define B_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF +#define B_SC_RA_RAM_PROC_TERMINATED__A 0x820045 +#define B_SC_RA_RAM_PROC_TERMINATED__W 16 +#define B_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF +#define B_SC_RA_RAM_SW_EVENT__A 0x820046 +#define B_SC_RA_RAM_SW_EVENT__W 14 +#define B_SC_RA_RAM_SW_EVENT__M 0x3FFF +#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 +#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 +#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 +#define B_SC_RA_RAM_SW_EVENT_RUN__B 1 +#define B_SC_RA_RAM_SW_EVENT_RUN__W 1 +#define B_SC_RA_RAM_SW_EVENT_RUN__M 0x2 +#define B_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 +#define B_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 +#define B_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 +#define B_SC_RA_RAM_SW_EVENT_FT_START__B 3 +#define B_SC_RA_RAM_SW_EVENT_FT_START__W 1 +#define B_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 +#define B_SC_RA_RAM_SW_EVENT_FI_START__B 4 +#define B_SC_RA_RAM_SW_EVENT_FI_START__W 1 +#define B_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 +#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 +#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 +#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 +#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 +#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 +#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 +#define B_SC_RA_RAM_SW_EVENT_CE_IR__B 7 +#define B_SC_RA_RAM_SW_EVENT_CE_IR__W 1 +#define B_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 +#define B_SC_RA_RAM_SW_EVENT_FE_FD__B 8 +#define B_SC_RA_RAM_SW_EVENT_FE_FD__W 1 +#define B_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 +#define B_SC_RA_RAM_SW_EVENT_FE_CF__B 9 +#define B_SC_RA_RAM_SW_EVENT_FE_CF__W 1 +#define B_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 +#define B_SC_RA_RAM_SW_EVENT_NF_READY__B 12 +#define B_SC_RA_RAM_SW_EVENT_NF_READY__W 1 +#define B_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 + +#define B_SC_RA_RAM_LOCKTRACK__A 0x820047 +#define B_SC_RA_RAM_LOCKTRACK__W 16 +#define B_SC_RA_RAM_LOCKTRACK__M 0xFFFF +#define B_SC_RA_RAM_LOCKTRACK_NULL 0x0 +#define B_SC_RA_RAM_LOCKTRACK_MIN 0x1 +#define B_SC_RA_RAM_LOCKTRACK_RESET 0x1 +#define B_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 +#define B_SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 +#define B_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 +#define B_SC_RA_RAM_LOCKTRACK_LC 0x5 +#define B_SC_RA_RAM_LOCKTRACK_P_ECHO 0x6 +#define B_SC_RA_RAM_LOCKTRACK_NE_INIT 0x7 +#define B_SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x8 +#define B_SC_RA_RAM_LOCKTRACK_TRACK 0x9 +#define B_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xA +#define B_SC_RA_RAM_LOCKTRACK_MAX 0xB + +#define B_SC_RA_RAM_OP_PARAM__A 0x820048 +#define B_SC_RA_RAM_OP_PARAM__W 13 +#define B_SC_RA_RAM_OP_PARAM__M 0x1FFF +#define B_SC_RA_RAM_OP_PARAM_MODE__B 0 +#define B_SC_RA_RAM_OP_PARAM_MODE__W 2 +#define B_SC_RA_RAM_OP_PARAM_MODE__M 0x3 +#define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 +#define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 +#define B_SC_RA_RAM_OP_PARAM_GUARD__B 2 +#define B_SC_RA_RAM_OP_PARAM_GUARD__W 2 +#define B_SC_RA_RAM_OP_PARAM_GUARD__M 0xC +#define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 +#define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 +#define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 +#define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC +#define B_SC_RA_RAM_OP_PARAM_CONST__B 4 +#define B_SC_RA_RAM_OP_PARAM_CONST__W 2 +#define B_SC_RA_RAM_OP_PARAM_CONST__M 0x30 +#define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 +#define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 +#define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 +#define B_SC_RA_RAM_OP_PARAM_HIER__B 6 +#define B_SC_RA_RAM_OP_PARAM_HIER__W 3 +#define B_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 +#define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 +#define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 +#define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 +#define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 +#define B_SC_RA_RAM_OP_PARAM_RATE__B 9 +#define B_SC_RA_RAM_OP_PARAM_RATE__W 3 +#define B_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 +#define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 +#define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 +#define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 +#define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 +#define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 +#define B_SC_RA_RAM_OP_PARAM_PRIO__B 12 +#define B_SC_RA_RAM_OP_PARAM_PRIO__W 1 +#define B_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 +#define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 +#define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 + +#define B_SC_RA_RAM_OP_AUTO__A 0x820049 +#define B_SC_RA_RAM_OP_AUTO__W 6 +#define B_SC_RA_RAM_OP_AUTO__M 0x3F +#define B_SC_RA_RAM_OP_AUTO__PRE 0x1F +#define B_SC_RA_RAM_OP_AUTO_MODE__B 0 +#define B_SC_RA_RAM_OP_AUTO_MODE__W 1 +#define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1 +#define B_SC_RA_RAM_OP_AUTO_GUARD__B 1 +#define B_SC_RA_RAM_OP_AUTO_GUARD__W 1 +#define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 +#define B_SC_RA_RAM_OP_AUTO_CONST__B 2 +#define B_SC_RA_RAM_OP_AUTO_CONST__W 1 +#define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4 +#define B_SC_RA_RAM_OP_AUTO_HIER__B 3 +#define B_SC_RA_RAM_OP_AUTO_HIER__W 1 +#define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8 +#define B_SC_RA_RAM_OP_AUTO_RATE__B 4 +#define B_SC_RA_RAM_OP_AUTO_RATE__W 1 +#define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10 +#define B_SC_RA_RAM_OP_AUTO_PRIO__B 5 +#define B_SC_RA_RAM_OP_AUTO_PRIO__W 1 +#define B_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 + +#define B_SC_RA_RAM_PILOT_STATUS__A 0x82004A +#define B_SC_RA_RAM_PILOT_STATUS__W 16 +#define B_SC_RA_RAM_PILOT_STATUS__M 0xFFFF +#define B_SC_RA_RAM_PILOT_STATUS_OK 0x0 +#define B_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 +#define B_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 +#define B_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 + +#define B_SC_RA_RAM_LOCK__A 0x82004B +#define B_SC_RA_RAM_LOCK__W 4 +#define B_SC_RA_RAM_LOCK__M 0xF +#define B_SC_RA_RAM_LOCK_DEMOD__B 0 +#define B_SC_RA_RAM_LOCK_DEMOD__W 1 +#define B_SC_RA_RAM_LOCK_DEMOD__M 0x1 +#define B_SC_RA_RAM_LOCK_FEC__B 1 +#define B_SC_RA_RAM_LOCK_FEC__W 1 +#define B_SC_RA_RAM_LOCK_FEC__M 0x2 +#define B_SC_RA_RAM_LOCK_MPEG__B 2 +#define B_SC_RA_RAM_LOCK_MPEG__W 1 +#define B_SC_RA_RAM_LOCK_MPEG__M 0x4 +#define B_SC_RA_RAM_LOCK_NODVBT__B 3 +#define B_SC_RA_RAM_LOCK_NODVBT__W 1 +#define B_SC_RA_RAM_LOCK_NODVBT__M 0x8 + +#define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C +#define B_SC_RA_RAM_BE_OPT_ENA__W 5 +#define B_SC_RA_RAM_BE_OPT_ENA__M 0x1F +#define B_SC_RA_RAM_BE_OPT_ENA__PRE 0x1E +#define B_SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 +#define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 +#define B_SC_RA_RAM_BE_OPT_ENA_CSI_OPT 0x2 +#define B_SC_RA_RAM_BE_OPT_ENA_CAL_OPT 0x3 +#define B_SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 +#define B_SC_RA_RAM_BE_OPT_ENA_MAX 0x5 + +#define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D +#define B_SC_RA_RAM_BE_OPT_DELAY__W 16 +#define B_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF +#define B_SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 +#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E +#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 +#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF +#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 +#define B_SC_RA_RAM_ECHO_THRES__A 0x82004F +#define B_SC_RA_RAM_ECHO_THRES__W 16 +#define B_SC_RA_RAM_ECHO_THRES__M 0xFFFF +#define B_SC_RA_RAM_ECHO_THRES__PRE 0x2A +#define B_SC_RA_RAM_CONFIG__A 0x820050 +#define B_SC_RA_RAM_CONFIG__W 16 +#define B_SC_RA_RAM_CONFIG__M 0xFFFF +#define B_SC_RA_RAM_CONFIG__PRE 0x14 +#define B_SC_RA_RAM_CONFIG_ID__B 0 +#define B_SC_RA_RAM_CONFIG_ID__W 1 +#define B_SC_RA_RAM_CONFIG_ID__M 0x1 +#define B_SC_RA_RAM_CONFIG_ID_PRO 0x0 +#define B_SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 +#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 +#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 +#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 +#define B_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 +#define B_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 +#define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 +#define B_SC_RA_RAM_CONFIG_MIXMODE__B 3 +#define B_SC_RA_RAM_CONFIG_MIXMODE__W 1 +#define B_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 +#define B_SC_RA_RAM_CONFIG_FREQSCAN__B 4 +#define B_SC_RA_RAM_CONFIG_FREQSCAN__W 1 +#define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 +#define B_SC_RA_RAM_CONFIG_SLAVE__B 5 +#define B_SC_RA_RAM_CONFIG_SLAVE__W 1 +#define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20 +#define B_SC_RA_RAM_CONFIG_FAR_OFF__B 6 +#define B_SC_RA_RAM_CONFIG_FAR_OFF__W 1 +#define B_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 +#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 +#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 +#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 +#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 +#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 +#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 +#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 +#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 +#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 +#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 +#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 +#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 +#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 +#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 +#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 + +#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x820054 +#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 +#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF +#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 + +#define B_SC_RA_RAM_FR_2K_MAN_SH__A 0x820055 +#define B_SC_RA_RAM_FR_2K_MAN_SH__W 16 +#define B_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 +#define B_SC_RA_RAM_FR_2K_TAP_SH__A 0x820056 +#define B_SC_RA_RAM_FR_2K_TAP_SH__W 16 +#define B_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 +#define B_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x820057 +#define B_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 +#define B_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF +#define B_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 +#define B_SC_RA_RAM_FR_2K_LEAK_SH__A 0x820058 +#define B_SC_RA_RAM_FR_2K_LEAK_SH__W 16 +#define B_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 + +#define B_SC_RA_RAM_FR_8K_MAN_SH__A 0x820059 +#define B_SC_RA_RAM_FR_8K_MAN_SH__W 16 +#define B_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 +#define B_SC_RA_RAM_FR_8K_TAP_SH__A 0x82005A +#define B_SC_RA_RAM_FR_8K_TAP_SH__W 16 +#define B_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x4 +#define B_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x82005B +#define B_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 +#define B_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF +#define B_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 +#define B_SC_RA_RAM_FR_8K_LEAK_SH__A 0x82005C +#define B_SC_RA_RAM_FR_8K_LEAK_SH__W 16 +#define B_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF +#define B_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x2 + +#define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D +#define B_SC_RA_RAM_CO_TD_CAL_2K__W 16 +#define B_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF +#define B_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB +#define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E +#define B_SC_RA_RAM_CO_TD_CAL_8K__W 16 +#define B_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF +#define B_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 +#define B_SC_RA_RAM_MOTION_OFFSET__A 0x82005F +#define B_SC_RA_RAM_MOTION_OFFSET__W 16 +#define B_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF +#define B_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 +#define B_SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 +#define B_SC_RA_RAM_STATE_PROC_STOP__XSZ 10 +#define B_SC_RA_RAM_STATE_PROC_STOP__W 16 +#define B_SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF +#define B_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE +#define B_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 +#define B_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_STOP_10__PRE 0xFFFE +#define B_SC_RA_RAM_STATE_PROC_START__AX 0x820070 +#define B_SC_RA_RAM_STATE_PROC_START__XSZ 10 +#define B_SC_RA_RAM_STATE_PROC_START__W 16 +#define B_SC_RA_RAM_STATE_PROC_START__M 0xFFFF +#define B_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 +#define B_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 +#define B_SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 +#define B_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 +#define B_SC_RA_RAM_STATE_PROC_START_5__PRE 0x100 +#define B_SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 +#define B_SC_RA_RAM_STATE_PROC_START_7__PRE 0x40 +#define B_SC_RA_RAM_STATE_PROC_START_8__PRE 0x10 +#define B_SC_RA_RAM_STATE_PROC_START_9__PRE 0x30 +#define B_SC_RA_RAM_STATE_PROC_START_10__PRE 0x0 +#define B_SC_RA_RAM_IF_SAVE__AX 0x82008E +#define B_SC_RA_RAM_IF_SAVE__XSZ 2 +#define B_SC_RA_RAM_IF_SAVE__W 16 +#define B_SC_RA_RAM_IF_SAVE__M 0xFFFF +#define B_SC_RA_RAM_FR_THRES__A 0x82007D +#define B_SC_RA_RAM_FR_THRES__W 16 +#define B_SC_RA_RAM_FR_THRES__M 0xFFFF +#define B_SC_RA_RAM_FR_THRES__PRE 0x1A2C +#define B_SC_RA_RAM_STATUS__A 0x82007E +#define B_SC_RA_RAM_STATUS__W 16 +#define B_SC_RA_RAM_STATUS__M 0xFFFF +#define B_SC_RA_RAM_NF_BORDER_INIT__A 0x82007F +#define B_SC_RA_RAM_NF_BORDER_INIT__W 16 +#define B_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF +#define B_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 +#define B_SC_RA_RAM_TIMER__A 0x820080 +#define B_SC_RA_RAM_TIMER__W 16 +#define B_SC_RA_RAM_TIMER__M 0xFFFF +#define B_SC_RA_RAM_FI_OFFSET__A 0x820081 +#define B_SC_RA_RAM_FI_OFFSET__W 16 +#define B_SC_RA_RAM_FI_OFFSET__M 0xFFFF +#define B_SC_RA_RAM_FI_OFFSET__PRE 0x382 +#define B_SC_RA_RAM_ECHO_GUARD__A 0x820082 +#define B_SC_RA_RAM_ECHO_GUARD__W 16 +#define B_SC_RA_RAM_ECHO_GUARD__M 0xFFFF +#define B_SC_RA_RAM_ECHO_GUARD__PRE 0x18 +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__A 0x8200BA +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__W 16 +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__M 0xFFFF +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__PRE 0x3 +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__A 0x8200BB +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__W 16 +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__M 0xFFFF +#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__PRE 0x0 + +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 + +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF +#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC + +#define B_SC_RA_RAM_IR_FREQ__A 0x8200D0 +#define B_SC_RA_RAM_IR_FREQ__W 16 +#define B_SC_RA_RAM_IR_FREQ__M 0xFFFF +#define B_SC_RA_RAM_IR_FREQ__PRE 0x0 + +#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 +#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 +#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 +#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 +#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 +#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 +#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 +#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 +#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 + +#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 +#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 +#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 +#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 +#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 +#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 +#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 +#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 +#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF +#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 + +#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 +#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 +#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 +#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 +#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 +#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 +#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 +#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 +#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 + +#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA +#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 +#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB +#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB +#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 +#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 +#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC +#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 +#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF +#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 + +#define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD +#define B_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 +#define B_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF +#define B_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 +#define B_SC_RA_RAM_ECHO_SHT_LIM__A 0x8200DE +#define B_SC_RA_RAM_ECHO_SHT_LIM__W 16 +#define B_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF +#define B_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x8200DF +#define B_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF +#define B_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0xCC0 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 +#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 + +#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 +#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 +#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 +#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 +#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 +#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 +#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 +#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 +#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 + +#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 +#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 +#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE +#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 +#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 +#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 +#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 +#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 +#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF +#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 + +#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 +#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 +#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF +#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 +#define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 +#define B_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 +#define B_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF +#define B_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C + +#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA +#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 +#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF +#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 +#define B_SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB +#define B_SC_RA_RAM_TPS_TIMEOUT__W 16 +#define B_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF +#define B_SC_RA_RAM_BAND__A 0x8200EC +#define B_SC_RA_RAM_BAND__W 16 +#define B_SC_RA_RAM_BAND__M 0xFFFF +#define B_SC_RA_RAM_BAND__PRE 0x0 +#define B_SC_RA_RAM_BAND_INTERVAL__B 0 +#define B_SC_RA_RAM_BAND_INTERVAL__W 4 +#define B_SC_RA_RAM_BAND_INTERVAL__M 0xF +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 +#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 +#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 + +#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED +#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 +#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF +#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 +#define B_SC_RA_RAM_REG__AX 0x8200F0 +#define B_SC_RA_RAM_REG__XSZ 2 +#define B_SC_RA_RAM_REG__W 16 +#define B_SC_RA_RAM_REG__M 0xFFFF +#define B_SC_RA_RAM_BREAK__A 0x8200F2 +#define B_SC_RA_RAM_BREAK__W 16 +#define B_SC_RA_RAM_BREAK__M 0xFFFF +#define B_SC_RA_RAM_BOOTCOUNT__A 0x8200F3 +#define B_SC_RA_RAM_BOOTCOUNT__W 16 +#define B_SC_RA_RAM_BOOTCOUNT__M 0xFFFF + +#define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 +#define B_SC_RA_RAM_LC_ABS_2K__W 16 +#define B_SC_RA_RAM_LC_ABS_2K__M 0xFFFF +#define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F +#define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5 +#define B_SC_RA_RAM_LC_ABS_8K__W 16 +#define B_SC_RA_RAM_LC_ABS_8K__M 0xFFFF +#define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F +#define B_SC_RA_RAM_NE_ERR_SELECT__A 0x8200F6 +#define B_SC_RA_RAM_NE_ERR_SELECT__W 16 +#define B_SC_RA_RAM_NE_ERR_SELECT__M 0xFFFF +#define B_SC_RA_RAM_NE_ERR_SELECT__PRE 0x19 +#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x8200F7 +#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 +#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF +#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 +#define B_SC_RA_RAM_RELOCK__A 0x8200FE +#define B_SC_RA_RAM_RELOCK__W 16 +#define B_SC_RA_RAM_RELOCK__M 0xFFFF +#define B_SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF +#define B_SC_RA_RAM_STACKUNDERFLOW__W 16 +#define B_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF + +#define B_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 +#define B_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 +#define B_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF +#define B_SC_RA_RAM_NF_PREPOST__A 0x820149 +#define B_SC_RA_RAM_NF_PREPOST__W 16 +#define B_SC_RA_RAM_NF_PREPOST__M 0xFFFF +#define B_SC_RA_RAM_NF_PREBORDER__A 0x82014A +#define B_SC_RA_RAM_NF_PREBORDER__W 16 +#define B_SC_RA_RAM_NF_PREBORDER__M 0xFFFF +#define B_SC_RA_RAM_NF_START__A 0x82014B +#define B_SC_RA_RAM_NF_START__W 16 +#define B_SC_RA_RAM_NF_START__M 0xFFFF +#define B_SC_RA_RAM_NF_MINISI__AX 0x82014C +#define B_SC_RA_RAM_NF_MINISI__XSZ 2 +#define B_SC_RA_RAM_NF_MINISI__W 16 +#define B_SC_RA_RAM_NF_MINISI__M 0xFFFF +#define B_SC_RA_RAM_NF_MAXECHO__A 0x82014E +#define B_SC_RA_RAM_NF_MAXECHO__W 16 +#define B_SC_RA_RAM_NF_MAXECHO__M 0xFFFF +#define B_SC_RA_RAM_NF_NRECHOES__A 0x82014F +#define B_SC_RA_RAM_NF_NRECHOES__W 16 +#define B_SC_RA_RAM_NF_NRECHOES__M 0xFFFF +#define B_SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 +#define B_SC_RA_RAM_NF_ECHOTABLE__XSZ 16 +#define B_SC_RA_RAM_NF_ECHOTABLE__W 16 +#define B_SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF + +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 + +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 + +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 + +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 + +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 + +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 + +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 + +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF +#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 +#define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE +#define B_SC_RA_RAM_DRIVER_VERSION__XSZ 2 +#define B_SC_RA_RAM_DRIVER_VERSION__W 16 +#define B_SC_RA_RAM_DRIVER_VERSION__M 0xFFFF +#define B_SC_RA_RAM_EVENT0_MIN 0x7 +#define B_SC_RA_RAM_EVENT0_FE_CU 0x7 +#define B_SC_RA_RAM_EVENT0_CE 0xA +#define B_SC_RA_RAM_EVENT0_EQ 0xE +#define B_SC_RA_RAM_EVENT0_MAX 0xF +#define B_SC_RA_RAM_PROC_LOCKTRACK 0x0 +#define B_SC_RA_RAM_PROC_MODE_GUARD 0x1 +#define B_SC_RA_RAM_PROC_PILOTS 0x2 +#define B_SC_RA_RAM_PROC_FESTART_ADJUST 0x3 +#define B_SC_RA_RAM_PROC_ECHO 0x4 +#define B_SC_RA_RAM_PROC_BE_OPT 0x5 +#define B_SC_RA_RAM_PROC_LOCK_MON 0x6 +#define B_SC_RA_RAM_PROC_EQ 0x7 +#define B_SC_RA_RAM_PROC_ECHO_DIVERSITY 0x8 +#define B_SC_RA_RAM_PROC_MAX 0x9 + +#define B_SC_IF_RAM_TRP_RST__AX 0x830000 +#define B_SC_IF_RAM_TRP_RST__XSZ 2 +#define B_SC_IF_RAM_TRP_RST__W 12 +#define B_SC_IF_RAM_TRP_RST__M 0xFFF + +#define B_SC_IF_RAM_TRP_BPT0__AX 0x830002 +#define B_SC_IF_RAM_TRP_BPT0__XSZ 2 +#define B_SC_IF_RAM_TRP_BPT0__W 12 +#define B_SC_IF_RAM_TRP_BPT0__M 0xFFF + +#define B_SC_IF_RAM_TRP_STKU__AX 0x830004 +#define B_SC_IF_RAM_TRP_STKU__XSZ 2 +#define B_SC_IF_RAM_TRP_STKU__W 12 +#define B_SC_IF_RAM_TRP_STKU__M 0xFFF + +#define B_SC_IF_RAM_VERSION_MA_MI__A 0x830FFE +#define B_SC_IF_RAM_VERSION_MA_MI__W 12 +#define B_SC_IF_RAM_VERSION_MA_MI__M 0xFFF + +#define B_SC_IF_RAM_VERSION_PATCH__A 0x830FFF +#define B_SC_IF_RAM_VERSION_PATCH__W 12 +#define B_SC_IF_RAM_VERSION_PATCH__M 0xFFF + +#define B_FE_COMM_EXEC__A 0xC00000 +#define B_FE_COMM_EXEC__W 3 +#define B_FE_COMM_EXEC__M 0x7 +#define B_FE_COMM_EXEC_CTL__B 0 +#define B_FE_COMM_EXEC_CTL__W 3 +#define B_FE_COMM_EXEC_CTL__M 0x7 +#define B_FE_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_COMM_EXEC_CTL_STEP 0x3 +#define B_FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_FE_COMM_STATE__A 0xC00001 +#define B_FE_COMM_STATE__W 16 +#define B_FE_COMM_STATE__M 0xFFFF +#define B_FE_COMM_MB__A 0xC00002 +#define B_FE_COMM_MB__W 16 +#define B_FE_COMM_MB__M 0xFFFF +#define B_FE_COMM_SERVICE0__A 0xC00003 +#define B_FE_COMM_SERVICE0__W 16 +#define B_FE_COMM_SERVICE0__M 0xFFFF +#define B_FE_COMM_SERVICE1__A 0xC00004 +#define B_FE_COMM_SERVICE1__W 16 +#define B_FE_COMM_SERVICE1__M 0xFFFF +#define B_FE_COMM_INT_STA__A 0xC00007 +#define B_FE_COMM_INT_STA__W 16 +#define B_FE_COMM_INT_STA__M 0xFFFF +#define B_FE_COMM_INT_MSK__A 0xC00008 +#define B_FE_COMM_INT_MSK__W 16 +#define B_FE_COMM_INT_MSK__M 0xFFFF + +#define B_FE_AD_SID 0x1 + +#define B_FE_AD_REG_COMM_EXEC__A 0xC10000 +#define B_FE_AD_REG_COMM_EXEC__W 3 +#define B_FE_AD_REG_COMM_EXEC__M 0x7 +#define B_FE_AD_REG_COMM_EXEC_CTL__B 0 +#define B_FE_AD_REG_COMM_EXEC_CTL__W 3 +#define B_FE_AD_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_FE_AD_REG_COMM_MB__A 0xC10002 +#define B_FE_AD_REG_COMM_MB__W 2 +#define B_FE_AD_REG_COMM_MB__M 0x3 +#define B_FE_AD_REG_COMM_MB_CTR__B 0 +#define B_FE_AD_REG_COMM_MB_CTR__W 1 +#define B_FE_AD_REG_COMM_MB_CTR__M 0x1 +#define B_FE_AD_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_AD_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_AD_REG_COMM_MB_OBS__B 1 +#define B_FE_AD_REG_COMM_MB_OBS__W 1 +#define B_FE_AD_REG_COMM_MB_OBS__M 0x2 +#define B_FE_AD_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_AD_REG_COMM_MB_OBS_ON 0x2 + +#define B_FE_AD_REG_COMM_SERVICE0__A 0xC10003 +#define B_FE_AD_REG_COMM_SERVICE0__W 10 +#define B_FE_AD_REG_COMM_SERVICE0__M 0x3FF +#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 +#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 +#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 + +#define B_FE_AD_REG_COMM_SERVICE1__A 0xC10004 +#define B_FE_AD_REG_COMM_SERVICE1__W 11 +#define B_FE_AD_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_AD_REG_COMM_INT_STA__A 0xC10007 +#define B_FE_AD_REG_COMM_INT_STA__W 2 +#define B_FE_AD_REG_COMM_INT_STA__M 0x3 +#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 +#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 +#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 + +#define B_FE_AD_REG_COMM_INT_MSK__A 0xC10008 +#define B_FE_AD_REG_COMM_INT_MSK__W 2 +#define B_FE_AD_REG_COMM_INT_MSK__M 0x3 +#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 +#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 +#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 + +#define B_FE_AD_REG_CUR_SEL__A 0xC10010 +#define B_FE_AD_REG_CUR_SEL__W 2 +#define B_FE_AD_REG_CUR_SEL__M 0x3 +#define B_FE_AD_REG_CUR_SEL_INIT 0x2 + +#define B_FE_AD_REG_OVERFLOW__A 0xC10011 +#define B_FE_AD_REG_OVERFLOW__W 1 +#define B_FE_AD_REG_OVERFLOW__M 0x1 +#define B_FE_AD_REG_OVERFLOW_INIT 0x0 + +#define B_FE_AD_REG_FDB_IN__A 0xC10012 +#define B_FE_AD_REG_FDB_IN__W 1 +#define B_FE_AD_REG_FDB_IN__M 0x1 +#define B_FE_AD_REG_FDB_IN_INIT 0x0 + +#define B_FE_AD_REG_PD__A 0xC10013 +#define B_FE_AD_REG_PD__W 1 +#define B_FE_AD_REG_PD__M 0x1 +#define B_FE_AD_REG_PD_INIT 0x1 + +#define B_FE_AD_REG_INVEXT__A 0xC10014 +#define B_FE_AD_REG_INVEXT__W 1 +#define B_FE_AD_REG_INVEXT__M 0x1 +#define B_FE_AD_REG_INVEXT_INIT 0x0 + +#define B_FE_AD_REG_CLKNEG__A 0xC10015 +#define B_FE_AD_REG_CLKNEG__W 1 +#define B_FE_AD_REG_CLKNEG__M 0x1 +#define B_FE_AD_REG_CLKNEG_INIT 0x0 + +#define B_FE_AD_REG_MON_IN_MUX__A 0xC10016 +#define B_FE_AD_REG_MON_IN_MUX__W 2 +#define B_FE_AD_REG_MON_IN_MUX__M 0x3 +#define B_FE_AD_REG_MON_IN_MUX_INIT 0x0 + +#define B_FE_AD_REG_MON_IN5__A 0xC10017 +#define B_FE_AD_REG_MON_IN5__W 10 +#define B_FE_AD_REG_MON_IN5__M 0x3FF +#define B_FE_AD_REG_MON_IN5_INIT 0x0 + +#define B_FE_AD_REG_MON_IN4__A 0xC10018 +#define B_FE_AD_REG_MON_IN4__W 10 +#define B_FE_AD_REG_MON_IN4__M 0x3FF +#define B_FE_AD_REG_MON_IN4_INIT 0x0 + +#define B_FE_AD_REG_MON_IN3__A 0xC10019 +#define B_FE_AD_REG_MON_IN3__W 10 +#define B_FE_AD_REG_MON_IN3__M 0x3FF +#define B_FE_AD_REG_MON_IN3_INIT 0x0 + +#define B_FE_AD_REG_MON_IN2__A 0xC1001A +#define B_FE_AD_REG_MON_IN2__W 10 +#define B_FE_AD_REG_MON_IN2__M 0x3FF +#define B_FE_AD_REG_MON_IN2_INIT 0x0 + +#define B_FE_AD_REG_MON_IN1__A 0xC1001B +#define B_FE_AD_REG_MON_IN1__W 10 +#define B_FE_AD_REG_MON_IN1__M 0x3FF +#define B_FE_AD_REG_MON_IN1_INIT 0x0 + +#define B_FE_AD_REG_MON_IN0__A 0xC1001C +#define B_FE_AD_REG_MON_IN0__W 10 +#define B_FE_AD_REG_MON_IN0__M 0x3FF +#define B_FE_AD_REG_MON_IN0_INIT 0x0 + +#define B_FE_AD_REG_MON_IN_VAL__A 0xC1001D +#define B_FE_AD_REG_MON_IN_VAL__W 1 +#define B_FE_AD_REG_MON_IN_VAL__M 0x1 +#define B_FE_AD_REG_MON_IN_VAL_INIT 0x0 + +#define B_FE_AD_REG_CTR_CLK_O__A 0xC1001E +#define B_FE_AD_REG_CTR_CLK_O__W 1 +#define B_FE_AD_REG_CTR_CLK_O__M 0x1 +#define B_FE_AD_REG_CTR_CLK_O_INIT 0x0 + +#define B_FE_AD_REG_CTR_CLK_E_O__A 0xC1001F +#define B_FE_AD_REG_CTR_CLK_E_O__W 1 +#define B_FE_AD_REG_CTR_CLK_E_O__M 0x1 +#define B_FE_AD_REG_CTR_CLK_E_O_INIT 0x1 + +#define B_FE_AD_REG_CTR_VAL_O__A 0xC10020 +#define B_FE_AD_REG_CTR_VAL_O__W 1 +#define B_FE_AD_REG_CTR_VAL_O__M 0x1 +#define B_FE_AD_REG_CTR_VAL_O_INIT 0x0 + +#define B_FE_AD_REG_CTR_VAL_E_O__A 0xC10021 +#define B_FE_AD_REG_CTR_VAL_E_O__W 1 +#define B_FE_AD_REG_CTR_VAL_E_O__M 0x1 +#define B_FE_AD_REG_CTR_VAL_E_O_INIT 0x1 + +#define B_FE_AD_REG_CTR_DATA_O__A 0xC10022 +#define B_FE_AD_REG_CTR_DATA_O__W 10 +#define B_FE_AD_REG_CTR_DATA_O__M 0x3FF +#define B_FE_AD_REG_CTR_DATA_O_INIT 0x0 + +#define B_FE_AD_REG_CTR_DATA_E_O__A 0xC10023 +#define B_FE_AD_REG_CTR_DATA_E_O__W 10 +#define B_FE_AD_REG_CTR_DATA_E_O__M 0x3FF +#define B_FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF + +#define B_FE_AG_SID 0x2 + +#define B_FE_AG_REG_COMM_EXEC__A 0xC20000 +#define B_FE_AG_REG_COMM_EXEC__W 3 +#define B_FE_AG_REG_COMM_EXEC__M 0x7 +#define B_FE_AG_REG_COMM_EXEC_CTL__B 0 +#define B_FE_AG_REG_COMM_EXEC_CTL__W 3 +#define B_FE_AG_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_FE_AG_REG_COMM_STATE__A 0xC20001 +#define B_FE_AG_REG_COMM_STATE__W 4 +#define B_FE_AG_REG_COMM_STATE__M 0xF + +#define B_FE_AG_REG_COMM_MB__A 0xC20002 +#define B_FE_AG_REG_COMM_MB__W 4 +#define B_FE_AG_REG_COMM_MB__M 0xF +#define B_FE_AG_REG_COMM_MB_OBS__B 1 +#define B_FE_AG_REG_COMM_MB_OBS__W 1 +#define B_FE_AG_REG_COMM_MB_OBS__M 0x2 +#define B_FE_AG_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_AG_REG_COMM_MB_OBS_ON 0x2 +#define B_FE_AG_REG_COMM_MB_MUX__B 2 +#define B_FE_AG_REG_COMM_MB_MUX__W 2 +#define B_FE_AG_REG_COMM_MB_MUX__M 0xC +#define B_FE_AG_REG_COMM_MB_MUX_DAT 0x0 +#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD2 0x4 +#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD1 0x8 +#define B_FE_AG_REG_COMM_MB_MUX_DAT_IND_PD1 0xC + +#define B_FE_AG_REG_COMM_SERVICE0__A 0xC20003 +#define B_FE_AG_REG_COMM_SERVICE0__W 10 +#define B_FE_AG_REG_COMM_SERVICE0__M 0x3FF + +#define B_FE_AG_REG_COMM_SERVICE1__A 0xC20004 +#define B_FE_AG_REG_COMM_SERVICE1__W 11 +#define B_FE_AG_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_AG_REG_COMM_INT_STA__A 0xC20007 +#define B_FE_AG_REG_COMM_INT_STA__W 8 +#define B_FE_AG_REG_COMM_INT_STA__M 0xFF +#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 +#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 +#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 +#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 +#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 +#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 +#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 +#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 +#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 +#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 +#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 +#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 +#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 +#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 + +#define B_FE_AG_REG_COMM_INT_MSK__A 0xC20008 +#define B_FE_AG_REG_COMM_INT_MSK__W 8 +#define B_FE_AG_REG_COMM_INT_MSK__M 0xFF +#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 +#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 +#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 +#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 +#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 +#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 +#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 +#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 +#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 +#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 +#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 +#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 +#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 +#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 +#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 + +#define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 +#define B_FE_AG_REG_AG_MODE_LOP__W 15 +#define B_FE_AG_REG_AG_MODE_LOP__M 0x7FFF +#define B_FE_AG_REG_AG_MODE_LOP_INIT 0x81E + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 + +#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 + +#define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 +#define B_FE_AG_REG_AG_MODE_HIP__W 5 +#define B_FE_AG_REG_AG_MODE_HIP__M 0x1F +#define B_FE_AG_REG_AG_MODE_HIP_INIT 0x0 + +#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 + +#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 + +#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__B 2 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__W 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__M 0x4 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH1 0x0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH2 0x4 + +#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__B 3 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__W 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8 + +#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__B 4 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__W 1 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__M 0x10 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH1 0x0 +#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH2 0x10 + +#define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 +#define B_FE_AG_REG_AG_PGA_MODE__W 3 +#define B_FE_AG_REG_AG_PGA_MODE__M 0x7 +#define B_FE_AG_REG_AG_PGA_MODE_INIT 0x3 +#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 +#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 +#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 + +#define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 +#define B_FE_AG_REG_AG_AGC_SIO__W 2 +#define B_FE_AG_REG_AG_AGC_SIO__M 0x3 +#define B_FE_AG_REG_AG_AGC_SIO_INIT 0x3 + +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 + +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 +#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 + +#define B_FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 +#define B_FE_AG_REG_AG_AGC_USR_DAT__W 2 +#define B_FE_AG_REG_AG_AGC_USR_DAT__M 0x3 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 +#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 + +#define B_FE_AG_REG_AG_PWD__A 0xC20015 +#define B_FE_AG_REG_AG_PWD__W 5 +#define B_FE_AG_REG_AG_PWD__M 0x1F +#define B_FE_AG_REG_AG_PWD_INIT 0x6 + +#define B_FE_AG_REG_AG_PWD_PWD_PD1__B 0 +#define B_FE_AG_REG_AG_PWD_PWD_PD1__W 1 +#define B_FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 +#define B_FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 +#define B_FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 + +#define B_FE_AG_REG_AG_PWD_PWD_PD2__B 1 +#define B_FE_AG_REG_AG_PWD_PWD_PD2__W 1 +#define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 +#define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 +#define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 + +#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 + +#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 +#define B_FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 + +#define B_FE_AG_REG_AG_PWD_PWD_AAF__B 4 +#define B_FE_AG_REG_AG_PWD_PWD_AAF__W 1 +#define B_FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 +#define B_FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 +#define B_FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 + +#define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 +#define B_FE_AG_REG_DCE_AUR_CNT__W 5 +#define B_FE_AG_REG_DCE_AUR_CNT__M 0x1F +#define B_FE_AG_REG_DCE_AUR_CNT_INIT 0x10 + +#define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 +#define B_FE_AG_REG_DCE_RUR_CNT__W 5 +#define B_FE_AG_REG_DCE_RUR_CNT__M 0x1F +#define B_FE_AG_REG_DCE_RUR_CNT_INIT 0x0 + +#define B_FE_AG_REG_DCE_AVE_DAT__A 0xC20018 +#define B_FE_AG_REG_DCE_AVE_DAT__W 10 +#define B_FE_AG_REG_DCE_AVE_DAT__M 0x3FF + +#define B_FE_AG_REG_DEC_AVE_WRI__A 0xC20019 +#define B_FE_AG_REG_DEC_AVE_WRI__W 10 +#define B_FE_AG_REG_DEC_AVE_WRI__M 0x3FF +#define B_FE_AG_REG_DEC_AVE_WRI_INIT 0x0 + +#define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A +#define B_FE_AG_REG_ACE_AUR_CNT__W 5 +#define B_FE_AG_REG_ACE_AUR_CNT__M 0x1F +#define B_FE_AG_REG_ACE_AUR_CNT_INIT 0xE + +#define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B +#define B_FE_AG_REG_ACE_RUR_CNT__W 5 +#define B_FE_AG_REG_ACE_RUR_CNT__M 0x1F +#define B_FE_AG_REG_ACE_RUR_CNT_INIT 0x0 + +#define B_FE_AG_REG_ACE_AVE_DAT__A 0xC2001C +#define B_FE_AG_REG_ACE_AVE_DAT__W 10 +#define B_FE_AG_REG_ACE_AVE_DAT__M 0x3FF + +#define B_FE_AG_REG_AEC_AVE_INC__A 0xC2001D +#define B_FE_AG_REG_AEC_AVE_INC__W 10 +#define B_FE_AG_REG_AEC_AVE_INC__M 0x3FF +#define B_FE_AG_REG_AEC_AVE_INC_INIT 0x0 + +#define B_FE_AG_REG_AEC_AVE_DAT__A 0xC2001E +#define B_FE_AG_REG_AEC_AVE_DAT__W 10 +#define B_FE_AG_REG_AEC_AVE_DAT__M 0x3FF + +#define B_FE_AG_REG_AEC_CLP_LVL__A 0xC2001F +#define B_FE_AG_REG_AEC_CLP_LVL__W 16 +#define B_FE_AG_REG_AEC_CLP_LVL__M 0xFFFF +#define B_FE_AG_REG_AEC_CLP_LVL_INIT 0x0 + +#define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 +#define B_FE_AG_REG_CDR_RUR_CNT__W 5 +#define B_FE_AG_REG_CDR_RUR_CNT__M 0x1F +#define B_FE_AG_REG_CDR_RUR_CNT_INIT 0x10 + +#define B_FE_AG_REG_CDR_CLP_DAT__A 0xC20021 +#define B_FE_AG_REG_CDR_CLP_DAT__W 16 +#define B_FE_AG_REG_CDR_CLP_DAT__M 0xFFFF + +#define B_FE_AG_REG_CDR_CLP_POS__A 0xC20022 +#define B_FE_AG_REG_CDR_CLP_POS__W 10 +#define B_FE_AG_REG_CDR_CLP_POS__M 0x3FF +#define B_FE_AG_REG_CDR_CLP_POS_INIT 0x16A + +#define B_FE_AG_REG_CDR_CLP_NEG__A 0xC20023 +#define B_FE_AG_REG_CDR_CLP_NEG__W 10 +#define B_FE_AG_REG_CDR_CLP_NEG__M 0x3FF +#define B_FE_AG_REG_CDR_CLP_NEG_INIT 0x296 + +#define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 +#define B_FE_AG_REG_EGC_RUR_CNT__W 5 +#define B_FE_AG_REG_EGC_RUR_CNT__M 0x1F +#define B_FE_AG_REG_EGC_RUR_CNT_INIT 0x0 + +#define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 +#define B_FE_AG_REG_EGC_SET_LVL__W 9 +#define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF +#define B_FE_AG_REG_EGC_SET_LVL_INIT 0x46 + +#define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 +#define B_FE_AG_REG_EGC_FLA_RGN__W 9 +#define B_FE_AG_REG_EGC_FLA_RGN__M 0x1FF +#define B_FE_AG_REG_EGC_FLA_RGN_INIT 0x4 + +#define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 +#define B_FE_AG_REG_EGC_SLO_RGN__W 9 +#define B_FE_AG_REG_EGC_SLO_RGN__M 0x1FF +#define B_FE_AG_REG_EGC_SLO_RGN_INIT 0x1F + +#define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 +#define B_FE_AG_REG_EGC_JMP_PSN__W 4 +#define B_FE_AG_REG_EGC_JMP_PSN__M 0xF +#define B_FE_AG_REG_EGC_JMP_PSN_INIT 0x0 + +#define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 +#define B_FE_AG_REG_EGC_FLA_INC__W 16 +#define B_FE_AG_REG_EGC_FLA_INC__M 0xFFFF +#define B_FE_AG_REG_EGC_FLA_INC_INIT 0x0 + +#define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A +#define B_FE_AG_REG_EGC_FLA_DEC__W 16 +#define B_FE_AG_REG_EGC_FLA_DEC__M 0xFFFF +#define B_FE_AG_REG_EGC_FLA_DEC_INIT 0x0 + +#define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B +#define B_FE_AG_REG_EGC_SLO_INC__W 16 +#define B_FE_AG_REG_EGC_SLO_INC__M 0xFFFF +#define B_FE_AG_REG_EGC_SLO_INC_INIT 0x3 + +#define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C +#define B_FE_AG_REG_EGC_SLO_DEC__W 16 +#define B_FE_AG_REG_EGC_SLO_DEC__M 0xFFFF +#define B_FE_AG_REG_EGC_SLO_DEC_INIT 0x3 + +#define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D +#define B_FE_AG_REG_EGC_FAS_INC__W 16 +#define B_FE_AG_REG_EGC_FAS_INC__M 0xFFFF +#define B_FE_AG_REG_EGC_FAS_INC_INIT 0xE + +#define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E +#define B_FE_AG_REG_EGC_FAS_DEC__W 16 +#define B_FE_AG_REG_EGC_FAS_DEC__M 0xFFFF +#define B_FE_AG_REG_EGC_FAS_DEC_INIT 0xE + +#define B_FE_AG_REG_EGC_MAP_DAT__A 0xC2002F +#define B_FE_AG_REG_EGC_MAP_DAT__W 16 +#define B_FE_AG_REG_EGC_MAP_DAT__M 0xFFFF + +#define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030 +#define B_FE_AG_REG_PM1_AGC_WRI__W 11 +#define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF +#define B_FE_AG_REG_PM1_AGC_WRI_INIT 0x0 + +#define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 +#define B_FE_AG_REG_GC1_AGC_RIC__W 16 +#define B_FE_AG_REG_GC1_AGC_RIC__M 0xFFFF +#define B_FE_AG_REG_GC1_AGC_RIC_INIT 0x64 + +#define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 +#define B_FE_AG_REG_GC1_AGC_OFF__W 16 +#define B_FE_AG_REG_GC1_AGC_OFF__M 0xFFFF +#define B_FE_AG_REG_GC1_AGC_OFF_INIT 0xFEC8 + +#define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 +#define B_FE_AG_REG_GC1_AGC_MAX__W 10 +#define B_FE_AG_REG_GC1_AGC_MAX__M 0x3FF +#define B_FE_AG_REG_GC1_AGC_MAX_INIT 0x1FF + +#define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 +#define B_FE_AG_REG_GC1_AGC_MIN__W 10 +#define B_FE_AG_REG_GC1_AGC_MIN__M 0x3FF +#define B_FE_AG_REG_GC1_AGC_MIN_INIT 0x200 + +#define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 +#define B_FE_AG_REG_GC1_AGC_DAT__W 10 +#define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF + +#define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036 +#define B_FE_AG_REG_PM2_AGC_WRI__W 11 +#define B_FE_AG_REG_PM2_AGC_WRI__M 0x7FF +#define B_FE_AG_REG_PM2_AGC_WRI_INIT 0x0 + +#define B_FE_AG_REG_GC2_AGC_RIC__A 0xC20037 +#define B_FE_AG_REG_GC2_AGC_RIC__W 16 +#define B_FE_AG_REG_GC2_AGC_RIC__M 0xFFFF +#define B_FE_AG_REG_GC2_AGC_RIC_INIT 0x64 + +#define B_FE_AG_REG_GC2_AGC_OFF__A 0xC20038 +#define B_FE_AG_REG_GC2_AGC_OFF__W 16 +#define B_FE_AG_REG_GC2_AGC_OFF__M 0xFFFF +#define B_FE_AG_REG_GC2_AGC_OFF_INIT 0xFEC8 + +#define B_FE_AG_REG_GC2_AGC_MAX__A 0xC20039 +#define B_FE_AG_REG_GC2_AGC_MAX__W 10 +#define B_FE_AG_REG_GC2_AGC_MAX__M 0x3FF +#define B_FE_AG_REG_GC2_AGC_MAX_INIT 0x1FF + +#define B_FE_AG_REG_GC2_AGC_MIN__A 0xC2003A +#define B_FE_AG_REG_GC2_AGC_MIN__W 10 +#define B_FE_AG_REG_GC2_AGC_MIN__M 0x3FF +#define B_FE_AG_REG_GC2_AGC_MIN_INIT 0x200 + +#define B_FE_AG_REG_GC2_AGC_DAT__A 0xC2003B +#define B_FE_AG_REG_GC2_AGC_DAT__W 10 +#define B_FE_AG_REG_GC2_AGC_DAT__M 0x3FF + +#define B_FE_AG_REG_IND_WIN__A 0xC2003C +#define B_FE_AG_REG_IND_WIN__W 5 +#define B_FE_AG_REG_IND_WIN__M 0x1F +#define B_FE_AG_REG_IND_WIN_INIT 0x0 + +#define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D +#define B_FE_AG_REG_IND_THD_LOL__W 6 +#define B_FE_AG_REG_IND_THD_LOL__M 0x3F +#define B_FE_AG_REG_IND_THD_LOL_INIT 0x5 + +#define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E +#define B_FE_AG_REG_IND_THD_HIL__W 6 +#define B_FE_AG_REG_IND_THD_HIL__M 0x3F +#define B_FE_AG_REG_IND_THD_HIL_INIT 0xF + +#define B_FE_AG_REG_IND_DEL__A 0xC2003F +#define B_FE_AG_REG_IND_DEL__W 7 +#define B_FE_AG_REG_IND_DEL__M 0x7F +#define B_FE_AG_REG_IND_DEL_INIT 0x32 + +#define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 +#define B_FE_AG_REG_IND_PD1_WRI__W 6 +#define B_FE_AG_REG_IND_PD1_WRI__M 0x3F +#define B_FE_AG_REG_IND_PD1_WRI_INIT 0x1E + +#define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 +#define B_FE_AG_REG_PDA_AUR_CNT__W 5 +#define B_FE_AG_REG_PDA_AUR_CNT__M 0x1F +#define B_FE_AG_REG_PDA_AUR_CNT_INIT 0x10 + +#define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 +#define B_FE_AG_REG_PDA_RUR_CNT__W 5 +#define B_FE_AG_REG_PDA_RUR_CNT__M 0x1F +#define B_FE_AG_REG_PDA_RUR_CNT_INIT 0x0 + +#define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 +#define B_FE_AG_REG_PDA_AVE_DAT__W 6 +#define B_FE_AG_REG_PDA_AVE_DAT__M 0x3F + +#define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044 +#define B_FE_AG_REG_PDC_RUR_CNT__W 5 +#define B_FE_AG_REG_PDC_RUR_CNT__M 0x1F +#define B_FE_AG_REG_PDC_RUR_CNT_INIT 0x0 + +#define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 +#define B_FE_AG_REG_PDC_SET_LVL__W 6 +#define B_FE_AG_REG_PDC_SET_LVL__M 0x3F +#define B_FE_AG_REG_PDC_SET_LVL_INIT 0x10 + +#define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 +#define B_FE_AG_REG_PDC_FLA_RGN__W 6 +#define B_FE_AG_REG_PDC_FLA_RGN__M 0x3F +#define B_FE_AG_REG_PDC_FLA_RGN_INIT 0x0 + +#define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 +#define B_FE_AG_REG_PDC_JMP_PSN__W 3 +#define B_FE_AG_REG_PDC_JMP_PSN__M 0x7 +#define B_FE_AG_REG_PDC_JMP_PSN_INIT 0x0 + +#define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 +#define B_FE_AG_REG_PDC_FLA_STP__W 16 +#define B_FE_AG_REG_PDC_FLA_STP__M 0xFFFF +#define B_FE_AG_REG_PDC_FLA_STP_INIT 0x0 + +#define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 +#define B_FE_AG_REG_PDC_SLO_STP__W 16 +#define B_FE_AG_REG_PDC_SLO_STP__M 0xFFFF +#define B_FE_AG_REG_PDC_SLO_STP_INIT 0x1 + +#define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A +#define B_FE_AG_REG_PDC_PD2_WRI__W 6 +#define B_FE_AG_REG_PDC_PD2_WRI__M 0x3F +#define B_FE_AG_REG_PDC_PD2_WRI_INIT 0x1F + +#define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B +#define B_FE_AG_REG_PDC_MAP_DAT__W 6 +#define B_FE_AG_REG_PDC_MAP_DAT__M 0x3F + +#define B_FE_AG_REG_PDC_MAX__A 0xC2004C +#define B_FE_AG_REG_PDC_MAX__W 6 +#define B_FE_AG_REG_PDC_MAX__M 0x3F +#define B_FE_AG_REG_PDC_MAX_INIT 0x2 + +#define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D +#define B_FE_AG_REG_TGA_AUR_CNT__W 5 +#define B_FE_AG_REG_TGA_AUR_CNT__M 0x1F +#define B_FE_AG_REG_TGA_AUR_CNT_INIT 0x10 + +#define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E +#define B_FE_AG_REG_TGA_RUR_CNT__W 5 +#define B_FE_AG_REG_TGA_RUR_CNT__M 0x1F +#define B_FE_AG_REG_TGA_RUR_CNT_INIT 0x0 + +#define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F +#define B_FE_AG_REG_TGA_AVE_DAT__W 6 +#define B_FE_AG_REG_TGA_AVE_DAT__M 0x3F + +#define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050 +#define B_FE_AG_REG_TGC_RUR_CNT__W 5 +#define B_FE_AG_REG_TGC_RUR_CNT__M 0x1F +#define B_FE_AG_REG_TGC_RUR_CNT_INIT 0x0 + +#define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 +#define B_FE_AG_REG_TGC_SET_LVL__W 6 +#define B_FE_AG_REG_TGC_SET_LVL__M 0x3F +#define B_FE_AG_REG_TGC_SET_LVL_INIT 0x18 + +#define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 +#define B_FE_AG_REG_TGC_FLA_RGN__W 6 +#define B_FE_AG_REG_TGC_FLA_RGN__M 0x3F +#define B_FE_AG_REG_TGC_FLA_RGN_INIT 0x0 + +#define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 +#define B_FE_AG_REG_TGC_JMP_PSN__W 4 +#define B_FE_AG_REG_TGC_JMP_PSN__M 0xF +#define B_FE_AG_REG_TGC_JMP_PSN_INIT 0x0 + +#define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 +#define B_FE_AG_REG_TGC_FLA_STP__W 16 +#define B_FE_AG_REG_TGC_FLA_STP__M 0xFFFF +#define B_FE_AG_REG_TGC_FLA_STP_INIT 0x0 + +#define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 +#define B_FE_AG_REG_TGC_SLO_STP__W 16 +#define B_FE_AG_REG_TGC_SLO_STP__M 0xFFFF +#define B_FE_AG_REG_TGC_SLO_STP_INIT 0x1 + +#define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 +#define B_FE_AG_REG_TGC_MAP_DAT__W 10 +#define B_FE_AG_REG_TGC_MAP_DAT__M 0x3FF + +#define B_FE_AG_REG_FGM_WRI__A 0xC20061 +#define B_FE_AG_REG_FGM_WRI__W 10 +#define B_FE_AG_REG_FGM_WRI__M 0x3FF +#define B_FE_AG_REG_FGM_WRI_INIT 0x80 + +#define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 +#define B_FE_AG_REG_BGC_FGC_WRI__W 4 +#define B_FE_AG_REG_BGC_FGC_WRI__M 0xF +#define B_FE_AG_REG_BGC_FGC_WRI_INIT 0x0 + +#define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 +#define B_FE_AG_REG_BGC_CGC_WRI__W 2 +#define B_FE_AG_REG_BGC_CGC_WRI__M 0x3 +#define B_FE_AG_REG_BGC_CGC_WRI_INIT 0x0 + +#define B_FE_AG_REG_BGC_THD_LVL__A 0xC2006B +#define B_FE_AG_REG_BGC_THD_LVL__W 4 +#define B_FE_AG_REG_BGC_THD_LVL__M 0xF +#define B_FE_AG_REG_BGC_THD_LVL_INIT 0xF + +#define B_FE_AG_REG_BGC_THD_INC__A 0xC2006C +#define B_FE_AG_REG_BGC_THD_INC__W 4 +#define B_FE_AG_REG_BGC_THD_INC__M 0xF +#define B_FE_AG_REG_BGC_THD_INC_INIT 0x8 + +#define B_FE_AG_REG_BGC_DAT__A 0xC2006D +#define B_FE_AG_REG_BGC_DAT__W 4 +#define B_FE_AG_REG_BGC_DAT__M 0xF + +#define B_FE_AG_REG_IND_PD1_COM__A 0xC2006E +#define B_FE_AG_REG_IND_PD1_COM__W 6 +#define B_FE_AG_REG_IND_PD1_COM__M 0x3F +#define B_FE_AG_REG_IND_PD1_COM_INIT 0x7 + +#define B_FE_AG_REG_AG_AGC_BUF__A 0xC2006F +#define B_FE_AG_REG_AG_AGC_BUF__W 2 +#define B_FE_AG_REG_AG_AGC_BUF__M 0x3 +#define B_FE_AG_REG_AG_AGC_BUF_INIT 0x3 + +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__B 0 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__W 1 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__M 0x1 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_SLOW 0x0 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_FAST 0x1 + +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__B 1 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__W 1 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__M 0x2 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_SLOW 0x0 +#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_FAST 0x2 + +#define B_FE_AG_REG_PMX_SPE__A 0xC20070 +#define B_FE_AG_REG_PMX_SPE__W 3 +#define B_FE_AG_REG_PMX_SPE__M 0x7 +#define B_FE_AG_REG_PMX_SPE_INIT 0x1 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_1 0x0 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_2 0x1 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_3 0x2 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_4 0x3 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_5 0x4 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_6 0x5 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_7 0x6 +#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_8 0x7 + +#define B_FE_FS_SID 0x3 + +#define B_FE_FS_REG_COMM_EXEC__A 0xC30000 +#define B_FE_FS_REG_COMM_EXEC__W 3 +#define B_FE_FS_REG_COMM_EXEC__M 0x7 +#define B_FE_FS_REG_COMM_EXEC_CTL__B 0 +#define B_FE_FS_REG_COMM_EXEC_CTL__W 3 +#define B_FE_FS_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_FE_FS_REG_COMM_STATE__A 0xC30001 +#define B_FE_FS_REG_COMM_STATE__W 4 +#define B_FE_FS_REG_COMM_STATE__M 0xF + +#define B_FE_FS_REG_COMM_MB__A 0xC30002 +#define B_FE_FS_REG_COMM_MB__W 3 +#define B_FE_FS_REG_COMM_MB__M 0x7 +#define B_FE_FS_REG_COMM_MB_CTR__B 0 +#define B_FE_FS_REG_COMM_MB_CTR__W 1 +#define B_FE_FS_REG_COMM_MB_CTR__M 0x1 +#define B_FE_FS_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_FS_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_FS_REG_COMM_MB_OBS__B 1 +#define B_FE_FS_REG_COMM_MB_OBS__W 1 +#define B_FE_FS_REG_COMM_MB_OBS__M 0x2 +#define B_FE_FS_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_FS_REG_COMM_MB_OBS_ON 0x2 +#define B_FE_FS_REG_COMM_MB_MUX__B 2 +#define B_FE_FS_REG_COMM_MB_MUX__W 1 +#define B_FE_FS_REG_COMM_MB_MUX__M 0x4 +#define B_FE_FS_REG_COMM_MB_MUX_REAL 0x0 +#define B_FE_FS_REG_COMM_MB_MUX_IMAG 0x4 + +#define B_FE_FS_REG_COMM_SERVICE0__A 0xC30003 +#define B_FE_FS_REG_COMM_SERVICE0__W 10 +#define B_FE_FS_REG_COMM_SERVICE0__M 0x3FF + +#define B_FE_FS_REG_COMM_SERVICE1__A 0xC30004 +#define B_FE_FS_REG_COMM_SERVICE1__W 11 +#define B_FE_FS_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_FS_REG_COMM_ACT__A 0xC30005 +#define B_FE_FS_REG_COMM_ACT__W 2 +#define B_FE_FS_REG_COMM_ACT__M 0x3 + +#define B_FE_FS_REG_COMM_CNT__A 0xC30006 +#define B_FE_FS_REG_COMM_CNT__W 16 +#define B_FE_FS_REG_COMM_CNT__M 0xFFFF + +#define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010 +#define B_FE_FS_REG_ADD_INC_LOP__W 16 +#define B_FE_FS_REG_ADD_INC_LOP__M 0xFFFF +#define B_FE_FS_REG_ADD_INC_LOP_INIT 0x0 + +#define B_FE_FS_REG_ADD_INC_HIP__A 0xC30011 +#define B_FE_FS_REG_ADD_INC_HIP__W 12 +#define B_FE_FS_REG_ADD_INC_HIP__M 0xFFF +#define B_FE_FS_REG_ADD_INC_HIP_INIT 0xC00 + +#define B_FE_FS_REG_ADD_OFF__A 0xC30012 +#define B_FE_FS_REG_ADD_OFF__W 12 +#define B_FE_FS_REG_ADD_OFF__M 0xFFF +#define B_FE_FS_REG_ADD_OFF_INIT 0x0 + +#define B_FE_FS_REG_ADD_OFF_VAL__A 0xC30013 +#define B_FE_FS_REG_ADD_OFF_VAL__W 1 +#define B_FE_FS_REG_ADD_OFF_VAL__M 0x1 +#define B_FE_FS_REG_ADD_OFF_VAL_INIT 0x0 + +#define B_FE_FD_SID 0x4 + +#define B_FE_FD_REG_COMM_EXEC__A 0xC40000 +#define B_FE_FD_REG_COMM_EXEC__W 3 +#define B_FE_FD_REG_COMM_EXEC__M 0x7 +#define B_FE_FD_REG_COMM_EXEC_CTL__B 0 +#define B_FE_FD_REG_COMM_EXEC_CTL__W 3 +#define B_FE_FD_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_FE_FD_REG_COMM_MB__A 0xC40002 +#define B_FE_FD_REG_COMM_MB__W 3 +#define B_FE_FD_REG_COMM_MB__M 0x7 +#define B_FE_FD_REG_COMM_MB_CTR__B 0 +#define B_FE_FD_REG_COMM_MB_CTR__W 1 +#define B_FE_FD_REG_COMM_MB_CTR__M 0x1 +#define B_FE_FD_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_FD_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_FD_REG_COMM_MB_OBS__B 1 +#define B_FE_FD_REG_COMM_MB_OBS__W 1 +#define B_FE_FD_REG_COMM_MB_OBS__M 0x2 +#define B_FE_FD_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_FD_REG_COMM_MB_OBS_ON 0x2 + +#define B_FE_FD_REG_COMM_SERVICE0__A 0xC40003 +#define B_FE_FD_REG_COMM_SERVICE0__W 10 +#define B_FE_FD_REG_COMM_SERVICE0__M 0x3FF +#define B_FE_FD_REG_COMM_SERVICE1__A 0xC40004 +#define B_FE_FD_REG_COMM_SERVICE1__W 11 +#define B_FE_FD_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_FD_REG_COMM_INT_STA__A 0xC40007 +#define B_FE_FD_REG_COMM_INT_STA__W 1 +#define B_FE_FD_REG_COMM_INT_STA__M 0x1 +#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + +#define B_FE_FD_REG_COMM_INT_MSK__A 0xC40008 +#define B_FE_FD_REG_COMM_INT_MSK__W 1 +#define B_FE_FD_REG_COMM_INT_MSK__M 0x1 +#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + +#define B_FE_FD_REG_SCL__A 0xC40010 +#define B_FE_FD_REG_SCL__W 6 +#define B_FE_FD_REG_SCL__M 0x3F + +#define B_FE_FD_REG_MAX_LEV__A 0xC40011 +#define B_FE_FD_REG_MAX_LEV__W 3 +#define B_FE_FD_REG_MAX_LEV__M 0x7 + +#define B_FE_FD_REG_NR__A 0xC40012 +#define B_FE_FD_REG_NR__W 5 +#define B_FE_FD_REG_NR__M 0x1F + +#define B_FE_FD_REG_MEAS_SEL__A 0xC40013 +#define B_FE_FD_REG_MEAS_SEL__W 1 +#define B_FE_FD_REG_MEAS_SEL__M 0x1 + +#define B_FE_FD_REG_MEAS_VAL__A 0xC40014 +#define B_FE_FD_REG_MEAS_VAL__W 1 +#define B_FE_FD_REG_MEAS_VAL__M 0x1 + +#define B_FE_FD_REG_MAX__A 0xC40015 +#define B_FE_FD_REG_MAX__W 16 +#define B_FE_FD_REG_MAX__M 0xFFFF + +#define B_FE_IF_SID 0x5 + +#define B_FE_IF_REG_COMM_EXEC__A 0xC50000 +#define B_FE_IF_REG_COMM_EXEC__W 3 +#define B_FE_IF_REG_COMM_EXEC__M 0x7 +#define B_FE_IF_REG_COMM_EXEC_CTL__B 0 +#define B_FE_IF_REG_COMM_EXEC_CTL__W 3 +#define B_FE_IF_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_FE_IF_REG_COMM_MB__A 0xC50002 +#define B_FE_IF_REG_COMM_MB__W 3 +#define B_FE_IF_REG_COMM_MB__M 0x7 +#define B_FE_IF_REG_COMM_MB_CTR__B 0 +#define B_FE_IF_REG_COMM_MB_CTR__W 1 +#define B_FE_IF_REG_COMM_MB_CTR__M 0x1 +#define B_FE_IF_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_IF_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_IF_REG_COMM_MB_OBS__B 1 +#define B_FE_IF_REG_COMM_MB_OBS__W 1 +#define B_FE_IF_REG_COMM_MB_OBS__M 0x2 +#define B_FE_IF_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_IF_REG_COMM_MB_OBS_ON 0x2 + +#define B_FE_IF_REG_INCR0__A 0xC50010 +#define B_FE_IF_REG_INCR0__W 16 +#define B_FE_IF_REG_INCR0__M 0xFFFF +#define B_FE_IF_REG_INCR0_INIT 0x0 + +#define B_FE_IF_REG_INCR1__A 0xC50011 +#define B_FE_IF_REG_INCR1__W 8 +#define B_FE_IF_REG_INCR1__M 0xFF +#define B_FE_IF_REG_INCR1_INIT 0x28 + +#define B_FE_CF_SID 0x6 + +#define B_FE_CF_REG_COMM_EXEC__A 0xC60000 +#define B_FE_CF_REG_COMM_EXEC__W 3 +#define B_FE_CF_REG_COMM_EXEC__M 0x7 +#define B_FE_CF_REG_COMM_EXEC_CTL__B 0 +#define B_FE_CF_REG_COMM_EXEC_CTL__W 3 +#define B_FE_CF_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_FE_CF_REG_COMM_MB__A 0xC60002 +#define B_FE_CF_REG_COMM_MB__W 3 +#define B_FE_CF_REG_COMM_MB__M 0x7 +#define B_FE_CF_REG_COMM_MB_CTR__B 0 +#define B_FE_CF_REG_COMM_MB_CTR__W 1 +#define B_FE_CF_REG_COMM_MB_CTR__M 0x1 +#define B_FE_CF_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_CF_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_CF_REG_COMM_MB_OBS__B 1 +#define B_FE_CF_REG_COMM_MB_OBS__W 1 +#define B_FE_CF_REG_COMM_MB_OBS__M 0x2 +#define B_FE_CF_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_CF_REG_COMM_MB_OBS_ON 0x2 + +#define B_FE_CF_REG_COMM_SERVICE0__A 0xC60003 +#define B_FE_CF_REG_COMM_SERVICE0__W 10 +#define B_FE_CF_REG_COMM_SERVICE0__M 0x3FF +#define B_FE_CF_REG_COMM_SERVICE1__A 0xC60004 +#define B_FE_CF_REG_COMM_SERVICE1__W 11 +#define B_FE_CF_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_CF_REG_COMM_INT_STA__A 0xC60007 +#define B_FE_CF_REG_COMM_INT_STA__W 2 +#define B_FE_CF_REG_COMM_INT_STA__M 0x3 +#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + +#define B_FE_CF_REG_COMM_INT_MSK__A 0xC60008 +#define B_FE_CF_REG_COMM_INT_MSK__W 2 +#define B_FE_CF_REG_COMM_INT_MSK__M 0x3 +#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + +#define B_FE_CF_REG_SCL__A 0xC60010 +#define B_FE_CF_REG_SCL__W 9 +#define B_FE_CF_REG_SCL__M 0x1FF + +#define B_FE_CF_REG_MAX_LEV__A 0xC60011 +#define B_FE_CF_REG_MAX_LEV__W 3 +#define B_FE_CF_REG_MAX_LEV__M 0x7 + +#define B_FE_CF_REG_NR__A 0xC60012 +#define B_FE_CF_REG_NR__W 5 +#define B_FE_CF_REG_NR__M 0x1F + +#define B_FE_CF_REG_IMP_VAL__A 0xC60013 +#define B_FE_CF_REG_IMP_VAL__W 1 +#define B_FE_CF_REG_IMP_VAL__M 0x1 + +#define B_FE_CF_REG_MEAS_VAL__A 0xC60014 +#define B_FE_CF_REG_MEAS_VAL__W 1 +#define B_FE_CF_REG_MEAS_VAL__M 0x1 + +#define B_FE_CF_REG_MAX__A 0xC60015 +#define B_FE_CF_REG_MAX__W 16 +#define B_FE_CF_REG_MAX__M 0xFFFF + +#define B_FE_CU_SID 0x7 + +#define B_FE_CU_REG_COMM_EXEC__A 0xC70000 +#define B_FE_CU_REG_COMM_EXEC__W 3 +#define B_FE_CU_REG_COMM_EXEC__M 0x7 +#define B_FE_CU_REG_COMM_EXEC_CTL__B 0 +#define B_FE_CU_REG_COMM_EXEC_CTL__W 3 +#define B_FE_CU_REG_COMM_EXEC_CTL__M 0x7 +#define B_FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_FE_CU_REG_COMM_STATE__A 0xC70001 +#define B_FE_CU_REG_COMM_STATE__W 4 +#define B_FE_CU_REG_COMM_STATE__M 0xF + +#define B_FE_CU_REG_COMM_MB__A 0xC70002 +#define B_FE_CU_REG_COMM_MB__W 3 +#define B_FE_CU_REG_COMM_MB__M 0x7 +#define B_FE_CU_REG_COMM_MB_CTR__B 0 +#define B_FE_CU_REG_COMM_MB_CTR__W 1 +#define B_FE_CU_REG_COMM_MB_CTR__M 0x1 +#define B_FE_CU_REG_COMM_MB_CTR_OFF 0x0 +#define B_FE_CU_REG_COMM_MB_CTR_ON 0x1 +#define B_FE_CU_REG_COMM_MB_OBS__B 1 +#define B_FE_CU_REG_COMM_MB_OBS__W 1 +#define B_FE_CU_REG_COMM_MB_OBS__M 0x2 +#define B_FE_CU_REG_COMM_MB_OBS_OFF 0x0 +#define B_FE_CU_REG_COMM_MB_OBS_ON 0x2 +#define B_FE_CU_REG_COMM_MB_MUX__B 2 +#define B_FE_CU_REG_COMM_MB_MUX__W 1 +#define B_FE_CU_REG_COMM_MB_MUX__M 0x4 +#define B_FE_CU_REG_COMM_MB_MUX_REAL 0x0 +#define B_FE_CU_REG_COMM_MB_MUX_IMAG 0x4 + +#define B_FE_CU_REG_COMM_SERVICE0__A 0xC70003 +#define B_FE_CU_REG_COMM_SERVICE0__W 10 +#define B_FE_CU_REG_COMM_SERVICE0__M 0x3FF + +#define B_FE_CU_REG_COMM_SERVICE1__A 0xC70004 +#define B_FE_CU_REG_COMM_SERVICE1__W 11 +#define B_FE_CU_REG_COMM_SERVICE1__M 0x7FF + +#define B_FE_CU_REG_COMM_ACT__A 0xC70005 +#define B_FE_CU_REG_COMM_ACT__W 2 +#define B_FE_CU_REG_COMM_ACT__M 0x3 + +#define B_FE_CU_REG_COMM_CNT__A 0xC70006 +#define B_FE_CU_REG_COMM_CNT__W 16 +#define B_FE_CU_REG_COMM_CNT__M 0xFFFF + +#define B_FE_CU_REG_COMM_INT_STA__A 0xC70007 +#define B_FE_CU_REG_COMM_INT_STA__W 4 +#define B_FE_CU_REG_COMM_INT_STA__M 0xF +#define B_FE_CU_REG_COMM_INT_STA_FE_START__B 0 +#define B_FE_CU_REG_COMM_INT_STA_FE_START__W 1 +#define B_FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 +#define B_FE_CU_REG_COMM_INT_STA_FT_START__B 1 +#define B_FE_CU_REG_COMM_INT_STA_FT_START__W 1 +#define B_FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 +#define B_FE_CU_REG_COMM_INT_STA_SB_START__B 2 +#define B_FE_CU_REG_COMM_INT_STA_SB_START__W 1 +#define B_FE_CU_REG_COMM_INT_STA_SB_START__M 0x4 +#define B_FE_CU_REG_COMM_INT_STA_NF_READY__B 3 +#define B_FE_CU_REG_COMM_INT_STA_NF_READY__W 1 +#define B_FE_CU_REG_COMM_INT_STA_NF_READY__M 0x8 + +#define B_FE_CU_REG_COMM_INT_MSK__A 0xC70008 +#define B_FE_CU_REG_COMM_INT_MSK__W 4 +#define B_FE_CU_REG_COMM_INT_MSK__M 0xF +#define B_FE_CU_REG_COMM_INT_MSK_FE_START__B 0 +#define B_FE_CU_REG_COMM_INT_MSK_FE_START__W 1 +#define B_FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 +#define B_FE_CU_REG_COMM_INT_MSK_FT_START__B 1 +#define B_FE_CU_REG_COMM_INT_MSK_FT_START__W 1 +#define B_FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 +#define B_FE_CU_REG_COMM_INT_MSK_SB_START__B 2 +#define B_FE_CU_REG_COMM_INT_MSK_SB_START__W 1 +#define B_FE_CU_REG_COMM_INT_MSK_SB_START__M 0x4 +#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__B 3 +#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__W 1 +#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__M 0x8 + +#define B_FE_CU_REG_MODE__A 0xC70010 +#define B_FE_CU_REG_MODE__W 5 +#define B_FE_CU_REG_MODE__M 0x1F +#define B_FE_CU_REG_MODE_INIT 0x0 + +#define B_FE_CU_REG_MODE_FFT__B 0 +#define B_FE_CU_REG_MODE_FFT__W 1 +#define B_FE_CU_REG_MODE_FFT__M 0x1 +#define B_FE_CU_REG_MODE_FFT_M8K 0x0 +#define B_FE_CU_REG_MODE_FFT_M2K 0x1 + +#define B_FE_CU_REG_MODE_COR__B 1 +#define B_FE_CU_REG_MODE_COR__W 1 +#define B_FE_CU_REG_MODE_COR__M 0x2 +#define B_FE_CU_REG_MODE_COR_OFF 0x0 +#define B_FE_CU_REG_MODE_COR_ON 0x2 + +#define B_FE_CU_REG_MODE_IFD__B 2 +#define B_FE_CU_REG_MODE_IFD__W 1 +#define B_FE_CU_REG_MODE_IFD__M 0x4 +#define B_FE_CU_REG_MODE_IFD_ENABLE 0x0 +#define B_FE_CU_REG_MODE_IFD_DISABLE 0x4 + +#define B_FE_CU_REG_MODE_SEL__B 3 +#define B_FE_CU_REG_MODE_SEL__W 1 +#define B_FE_CU_REG_MODE_SEL__M 0x8 +#define B_FE_CU_REG_MODE_SEL_COR 0x0 +#define B_FE_CU_REG_MODE_SEL_COR_NFC 0x8 + +#define B_FE_CU_REG_MODE_FES__B 4 +#define B_FE_CU_REG_MODE_FES__W 1 +#define B_FE_CU_REG_MODE_FES__M 0x10 +#define B_FE_CU_REG_MODE_FES_SEL_RST 0x0 +#define B_FE_CU_REG_MODE_FES_SEL_UPD 0x10 + +#define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 +#define B_FE_CU_REG_FRM_CNT_RST__W 15 +#define B_FE_CU_REG_FRM_CNT_RST__M 0x7FFF +#define B_FE_CU_REG_FRM_CNT_RST_INIT 0x20FF + +#define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 +#define B_FE_CU_REG_FRM_CNT_STR__W 15 +#define B_FE_CU_REG_FRM_CNT_STR__M 0x7FFF +#define B_FE_CU_REG_FRM_CNT_STR_INIT 0x1E + +#define B_FE_CU_REG_FRM_SMP_CNT__A 0xC70013 +#define B_FE_CU_REG_FRM_SMP_CNT__W 15 +#define B_FE_CU_REG_FRM_SMP_CNT__M 0x7FFF + +#define B_FE_CU_REG_FRM_SMB_CNT__A 0xC70014 +#define B_FE_CU_REG_FRM_SMB_CNT__W 16 +#define B_FE_CU_REG_FRM_SMB_CNT__M 0xFFFF + +#define B_FE_CU_REG_CMP_MAX_DAT__A 0xC70015 +#define B_FE_CU_REG_CMP_MAX_DAT__W 12 +#define B_FE_CU_REG_CMP_MAX_DAT__M 0xFFF + +#define B_FE_CU_REG_CMP_MAX_ADR__A 0xC70016 +#define B_FE_CU_REG_CMP_MAX_ADR__W 10 +#define B_FE_CU_REG_CMP_MAX_ADR__M 0x3FF + +#define B_FE_CU_REG_BUF_NFC_DEL__A 0xC7001F +#define B_FE_CU_REG_BUF_NFC_DEL__W 14 +#define B_FE_CU_REG_BUF_NFC_DEL__M 0x3FFF +#define B_FE_CU_REG_BUF_NFC_DEL_INIT 0x0 + +#define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 +#define B_FE_CU_REG_CTR_NFC_ICR__W 5 +#define B_FE_CU_REG_CTR_NFC_ICR__M 0x1F +#define B_FE_CU_REG_CTR_NFC_ICR_INIT 0x0 + +#define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 +#define B_FE_CU_REG_CTR_NFC_OCR__W 15 +#define B_FE_CU_REG_CTR_NFC_OCR__M 0x7FFF +#define B_FE_CU_REG_CTR_NFC_OCR_INIT 0x61A8 + +#define B_FE_CU_REG_CTR_NFC_CNT__A 0xC70022 +#define B_FE_CU_REG_CTR_NFC_CNT__W 15 +#define B_FE_CU_REG_CTR_NFC_CNT__M 0x7FFF + +#define B_FE_CU_REG_CTR_NFC_STS__A 0xC70023 +#define B_FE_CU_REG_CTR_NFC_STS__W 3 +#define B_FE_CU_REG_CTR_NFC_STS__M 0x7 +#define B_FE_CU_REG_CTR_NFC_STS_RUN 0x0 +#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_IMA 0x1 +#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_REA 0x2 +#define B_FE_CU_REG_CTR_NFC_STS_CNT_MAX 0x4 + +#define B_FE_CU_REG_DIV_NFC_REA__A 0xC70024 +#define B_FE_CU_REG_DIV_NFC_REA__W 14 +#define B_FE_CU_REG_DIV_NFC_REA__M 0x3FFF + +#define B_FE_CU_REG_DIV_NFC_IMA__A 0xC70025 +#define B_FE_CU_REG_DIV_NFC_IMA__W 14 +#define B_FE_CU_REG_DIV_NFC_IMA__M 0x3FFF + +#define B_FE_CU_REG_FRM_CNT_UPD__A 0xC70026 +#define B_FE_CU_REG_FRM_CNT_UPD__W 15 +#define B_FE_CU_REG_FRM_CNT_UPD__M 0x7FFF +#define B_FE_CU_REG_FRM_CNT_UPD_INIT 0x20FF + +#define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 +#define B_FE_CU_REG_DIV_NFC_CLP__W 2 +#define B_FE_CU_REG_DIV_NFC_CLP__M 0x3 +#define B_FE_CU_REG_DIV_NFC_CLP_INIT 0x1 +#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S11 0x0 +#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S12 0x1 +#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S13 0x2 +#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S14 0x3 + +#define B_FE_CU_BUF_RAM__A 0xC80000 + +#define B_FE_CU_CMP_RAM__A 0xC90000 + +#define B_FT_SID 0x8 + +#define B_FT_COMM_EXEC__A 0x1000000 +#define B_FT_COMM_EXEC__W 3 +#define B_FT_COMM_EXEC__M 0x7 +#define B_FT_COMM_EXEC_CTL__B 0 +#define B_FT_COMM_EXEC_CTL__W 3 +#define B_FT_COMM_EXEC_CTL__M 0x7 +#define B_FT_COMM_EXEC_CTL_STOP 0x0 +#define B_FT_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FT_COMM_EXEC_CTL_HOLD 0x2 +#define B_FT_COMM_EXEC_CTL_STEP 0x3 +#define B_FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_FT_COMM_STATE__A 0x1000001 +#define B_FT_COMM_STATE__W 16 +#define B_FT_COMM_STATE__M 0xFFFF +#define B_FT_COMM_MB__A 0x1000002 +#define B_FT_COMM_MB__W 16 +#define B_FT_COMM_MB__M 0xFFFF +#define B_FT_COMM_SERVICE0__A 0x1000003 +#define B_FT_COMM_SERVICE0__W 16 +#define B_FT_COMM_SERVICE0__M 0xFFFF +#define B_FT_COMM_SERVICE1__A 0x1000004 +#define B_FT_COMM_SERVICE1__W 16 +#define B_FT_COMM_SERVICE1__M 0xFFFF +#define B_FT_COMM_INT_STA__A 0x1000007 +#define B_FT_COMM_INT_STA__W 16 +#define B_FT_COMM_INT_STA__M 0xFFFF +#define B_FT_COMM_INT_MSK__A 0x1000008 +#define B_FT_COMM_INT_MSK__W 16 +#define B_FT_COMM_INT_MSK__M 0xFFFF + +#define B_FT_REG_COMM_EXEC__A 0x1010000 +#define B_FT_REG_COMM_EXEC__W 3 +#define B_FT_REG_COMM_EXEC__M 0x7 +#define B_FT_REG_COMM_EXEC_CTL__B 0 +#define B_FT_REG_COMM_EXEC_CTL__W 3 +#define B_FT_REG_COMM_EXEC_CTL__M 0x7 +#define B_FT_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_FT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_FT_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_FT_REG_COMM_MB__A 0x1010002 +#define B_FT_REG_COMM_MB__W 3 +#define B_FT_REG_COMM_MB__M 0x7 +#define B_FT_REG_COMM_MB_CTR__B 0 +#define B_FT_REG_COMM_MB_CTR__W 1 +#define B_FT_REG_COMM_MB_CTR__M 0x1 +#define B_FT_REG_COMM_MB_CTR_OFF 0x0 +#define B_FT_REG_COMM_MB_CTR_ON 0x1 +#define B_FT_REG_COMM_MB_OBS__B 1 +#define B_FT_REG_COMM_MB_OBS__W 1 +#define B_FT_REG_COMM_MB_OBS__M 0x2 +#define B_FT_REG_COMM_MB_OBS_OFF 0x0 +#define B_FT_REG_COMM_MB_OBS_ON 0x2 + +#define B_FT_REG_MODE_2K__A 0x1010010 +#define B_FT_REG_MODE_2K__W 1 +#define B_FT_REG_MODE_2K__M 0x1 +#define B_FT_REG_MODE_2K_MODE_8K 0x0 +#define B_FT_REG_MODE_2K_MODE_2K 0x1 +#define B_FT_REG_MODE_2K_INIT 0x0 + +#define B_FT_REG_NORM_OFF__A 0x1010016 +#define B_FT_REG_NORM_OFF__W 4 +#define B_FT_REG_NORM_OFF__M 0xF +#define B_FT_REG_NORM_OFF_INIT 0x2 + +#define B_FT_ST1_RAM__A 0x1020000 + +#define B_FT_ST2_RAM__A 0x1030000 + +#define B_FT_ST3_RAM__A 0x1040000 + +#define B_FT_ST5_RAM__A 0x1050000 + +#define B_FT_ST6_RAM__A 0x1060000 + +#define B_FT_ST8_RAM__A 0x1070000 + +#define B_FT_ST9_RAM__A 0x1080000 + +#define B_CP_SID 0x9 + +#define B_CP_COMM_EXEC__A 0x1400000 +#define B_CP_COMM_EXEC__W 3 +#define B_CP_COMM_EXEC__M 0x7 +#define B_CP_COMM_EXEC_CTL__B 0 +#define B_CP_COMM_EXEC_CTL__W 3 +#define B_CP_COMM_EXEC_CTL__M 0x7 +#define B_CP_COMM_EXEC_CTL_STOP 0x0 +#define B_CP_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CP_COMM_EXEC_CTL_HOLD 0x2 +#define B_CP_COMM_EXEC_CTL_STEP 0x3 +#define B_CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_CP_COMM_STATE__A 0x1400001 +#define B_CP_COMM_STATE__W 16 +#define B_CP_COMM_STATE__M 0xFFFF +#define B_CP_COMM_MB__A 0x1400002 +#define B_CP_COMM_MB__W 16 +#define B_CP_COMM_MB__M 0xFFFF +#define B_CP_COMM_SERVICE0__A 0x1400003 +#define B_CP_COMM_SERVICE0__W 16 +#define B_CP_COMM_SERVICE0__M 0xFFFF +#define B_CP_COMM_SERVICE1__A 0x1400004 +#define B_CP_COMM_SERVICE1__W 16 +#define B_CP_COMM_SERVICE1__M 0xFFFF +#define B_CP_COMM_INT_STA__A 0x1400007 +#define B_CP_COMM_INT_STA__W 16 +#define B_CP_COMM_INT_STA__M 0xFFFF +#define B_CP_COMM_INT_MSK__A 0x1400008 +#define B_CP_COMM_INT_MSK__W 16 +#define B_CP_COMM_INT_MSK__M 0xFFFF + +#define B_CP_REG_COMM_EXEC__A 0x1410000 +#define B_CP_REG_COMM_EXEC__W 3 +#define B_CP_REG_COMM_EXEC__M 0x7 +#define B_CP_REG_COMM_EXEC_CTL__B 0 +#define B_CP_REG_COMM_EXEC_CTL__W 3 +#define B_CP_REG_COMM_EXEC_CTL__M 0x7 +#define B_CP_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CP_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_CP_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_CP_REG_COMM_MB__A 0x1410002 +#define B_CP_REG_COMM_MB__W 3 +#define B_CP_REG_COMM_MB__M 0x7 +#define B_CP_REG_COMM_MB_CTR__B 0 +#define B_CP_REG_COMM_MB_CTR__W 1 +#define B_CP_REG_COMM_MB_CTR__M 0x1 +#define B_CP_REG_COMM_MB_CTR_OFF 0x0 +#define B_CP_REG_COMM_MB_CTR_ON 0x1 +#define B_CP_REG_COMM_MB_OBS__B 1 +#define B_CP_REG_COMM_MB_OBS__W 1 +#define B_CP_REG_COMM_MB_OBS__M 0x2 +#define B_CP_REG_COMM_MB_OBS_OFF 0x0 +#define B_CP_REG_COMM_MB_OBS_ON 0x2 + +#define B_CP_REG_COMM_SERVICE0__A 0x1410003 +#define B_CP_REG_COMM_SERVICE0__W 10 +#define B_CP_REG_COMM_SERVICE0__M 0x3FF +#define B_CP_REG_COMM_SERVICE0_CP__B 9 +#define B_CP_REG_COMM_SERVICE0_CP__W 1 +#define B_CP_REG_COMM_SERVICE0_CP__M 0x200 + +#define B_CP_REG_COMM_SERVICE1__A 0x1410004 +#define B_CP_REG_COMM_SERVICE1__W 11 +#define B_CP_REG_COMM_SERVICE1__M 0x7FF + +#define B_CP_REG_COMM_INT_STA__A 0x1410007 +#define B_CP_REG_COMM_INT_STA__W 2 +#define B_CP_REG_COMM_INT_STA__M 0x3 +#define B_CP_REG_COMM_INT_STA_NEW_MEAS__B 0 +#define B_CP_REG_COMM_INT_STA_NEW_MEAS__W 1 +#define B_CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 + +#define B_CP_REG_COMM_INT_MSK__A 0x1410008 +#define B_CP_REG_COMM_INT_MSK__W 2 +#define B_CP_REG_COMM_INT_MSK__M 0x3 +#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 +#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 +#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 + +#define B_CP_REG_MODE_2K__A 0x1410010 +#define B_CP_REG_MODE_2K__W 1 +#define B_CP_REG_MODE_2K__M 0x1 +#define B_CP_REG_MODE_2K_INIT 0x0 + +#define B_CP_REG_INTERVAL__A 0x1410011 +#define B_CP_REG_INTERVAL__W 4 +#define B_CP_REG_INTERVAL__M 0xF +#define B_CP_REG_INTERVAL_INIT 0x5 + +#define B_CP_REG_DETECT_ENA__A 0x1410012 +#define B_CP_REG_DETECT_ENA__W 2 +#define B_CP_REG_DETECT_ENA__M 0x3 + +#define B_CP_REG_DETECT_ENA_SCATTERED__B 0 +#define B_CP_REG_DETECT_ENA_SCATTERED__W 1 +#define B_CP_REG_DETECT_ENA_SCATTERED__M 0x1 + +#define B_CP_REG_DETECT_ENA_CONTINUOUS__B 1 +#define B_CP_REG_DETECT_ENA_CONTINUOUS__W 1 +#define B_CP_REG_DETECT_ENA_CONTINUOUS__M 0x2 +#define B_CP_REG_DETECT_ENA_INIT 0x0 + +#define B_CP_REG_BR_SMB_NR__A 0x1410021 +#define B_CP_REG_BR_SMB_NR__W 4 +#define B_CP_REG_BR_SMB_NR__M 0xF + +#define B_CP_REG_BR_SMB_NR_SMB__B 0 +#define B_CP_REG_BR_SMB_NR_SMB__W 2 +#define B_CP_REG_BR_SMB_NR_SMB__M 0x3 + +#define B_CP_REG_BR_SMB_NR_VAL__B 2 +#define B_CP_REG_BR_SMB_NR_VAL__W 1 +#define B_CP_REG_BR_SMB_NR_VAL__M 0x4 + +#define B_CP_REG_BR_SMB_NR_OFFSET__B 3 +#define B_CP_REG_BR_SMB_NR_OFFSET__W 1 +#define B_CP_REG_BR_SMB_NR_OFFSET__M 0x8 +#define B_CP_REG_BR_SMB_NR_INIT 0x0 + +#define B_CP_REG_BR_CP_SMB_NR__A 0x1410022 +#define B_CP_REG_BR_CP_SMB_NR__W 2 +#define B_CP_REG_BR_CP_SMB_NR__M 0x3 +#define B_CP_REG_BR_CP_SMB_NR_INIT 0x0 + +#define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 +#define B_CP_REG_BR_SPL_OFFSET__W 3 +#define B_CP_REG_BR_SPL_OFFSET__M 0x7 +#define B_CP_REG_BR_SPL_OFFSET_INIT 0x0 + +#define B_CP_REG_BR_STR_DEL__A 0x1410024 +#define B_CP_REG_BR_STR_DEL__W 10 +#define B_CP_REG_BR_STR_DEL__M 0x3FF +#define B_CP_REG_BR_STR_DEL_INIT 0xA + +#define B_CP_REG_BR_EXP_ADJ__A 0x1410025 +#define B_CP_REG_BR_EXP_ADJ__W 5 +#define B_CP_REG_BR_EXP_ADJ__M 0x1F +#define B_CP_REG_BR_EXP_ADJ_INIT 0x10 + +#define B_CP_REG_RT_ANG_INC0__A 0x1410030 +#define B_CP_REG_RT_ANG_INC0__W 16 +#define B_CP_REG_RT_ANG_INC0__M 0xFFFF +#define B_CP_REG_RT_ANG_INC0_INIT 0x0 + +#define B_CP_REG_RT_ANG_INC1__A 0x1410031 +#define B_CP_REG_RT_ANG_INC1__W 8 +#define B_CP_REG_RT_ANG_INC1__M 0xFF +#define B_CP_REG_RT_ANG_INC1_INIT 0x0 + +#define B_CP_REG_RT_SPD_EXP_MARG__A 0x1410032 +#define B_CP_REG_RT_SPD_EXP_MARG__W 5 +#define B_CP_REG_RT_SPD_EXP_MARG__M 0x1F +#define B_CP_REG_RT_SPD_EXP_MARG_INIT 0x5 + +#define B_CP_REG_RT_DETECT_TRH__A 0x1410033 +#define B_CP_REG_RT_DETECT_TRH__W 2 +#define B_CP_REG_RT_DETECT_TRH__M 0x3 +#define B_CP_REG_RT_DETECT_TRH_INIT 0x3 + +#define B_CP_REG_RT_SPD_RELIABLE__A 0x1410034 +#define B_CP_REG_RT_SPD_RELIABLE__W 3 +#define B_CP_REG_RT_SPD_RELIABLE__M 0x7 +#define B_CP_REG_RT_SPD_RELIABLE_INIT 0x0 + +#define B_CP_REG_RT_SPD_DIRECTION__A 0x1410035 +#define B_CP_REG_RT_SPD_DIRECTION__W 1 +#define B_CP_REG_RT_SPD_DIRECTION__M 0x1 +#define B_CP_REG_RT_SPD_DIRECTION_INIT 0x0 + +#define B_CP_REG_RT_SPD_MOD__A 0x1410036 +#define B_CP_REG_RT_SPD_MOD__W 2 +#define B_CP_REG_RT_SPD_MOD__M 0x3 +#define B_CP_REG_RT_SPD_MOD_INIT 0x0 + +#define B_CP_REG_RT_SPD_SMB__A 0x1410037 +#define B_CP_REG_RT_SPD_SMB__W 2 +#define B_CP_REG_RT_SPD_SMB__M 0x3 +#define B_CP_REG_RT_SPD_SMB_INIT 0x0 + +#define B_CP_REG_RT_CPD_MODE__A 0x1410038 +#define B_CP_REG_RT_CPD_MODE__W 3 +#define B_CP_REG_RT_CPD_MODE__M 0x7 + +#define B_CP_REG_RT_CPD_MODE_MOD3__B 0 +#define B_CP_REG_RT_CPD_MODE_MOD3__W 2 +#define B_CP_REG_RT_CPD_MODE_MOD3__M 0x3 + +#define B_CP_REG_RT_CPD_MODE_ADD__B 2 +#define B_CP_REG_RT_CPD_MODE_ADD__W 1 +#define B_CP_REG_RT_CPD_MODE_ADD__M 0x4 +#define B_CP_REG_RT_CPD_MODE_INIT 0x0 + +#define B_CP_REG_RT_CPD_RELIABLE__A 0x1410039 +#define B_CP_REG_RT_CPD_RELIABLE__W 3 +#define B_CP_REG_RT_CPD_RELIABLE__M 0x7 +#define B_CP_REG_RT_CPD_RELIABLE_INIT 0x0 + +#define B_CP_REG_RT_CPD_BIN__A 0x141003A +#define B_CP_REG_RT_CPD_BIN__W 5 +#define B_CP_REG_RT_CPD_BIN__M 0x1F +#define B_CP_REG_RT_CPD_BIN_INIT 0x0 + +#define B_CP_REG_RT_CPD_MAX__A 0x141003B +#define B_CP_REG_RT_CPD_MAX__W 4 +#define B_CP_REG_RT_CPD_MAX__M 0xF +#define B_CP_REG_RT_CPD_MAX_INIT 0x0 + +#define B_CP_REG_RT_SUPR_VAL__A 0x141003C +#define B_CP_REG_RT_SUPR_VAL__W 2 +#define B_CP_REG_RT_SUPR_VAL__M 0x3 + +#define B_CP_REG_RT_SUPR_VAL_CE__B 0 +#define B_CP_REG_RT_SUPR_VAL_CE__W 1 +#define B_CP_REG_RT_SUPR_VAL_CE__M 0x1 + +#define B_CP_REG_RT_SUPR_VAL_DL__B 1 +#define B_CP_REG_RT_SUPR_VAL_DL__W 1 +#define B_CP_REG_RT_SUPR_VAL_DL__M 0x2 +#define B_CP_REG_RT_SUPR_VAL_INIT 0x0 + +#define B_CP_REG_RT_EXP_AVE__A 0x141003D +#define B_CP_REG_RT_EXP_AVE__W 5 +#define B_CP_REG_RT_EXP_AVE__M 0x1F +#define B_CP_REG_RT_EXP_AVE_INIT 0x0 + +#define B_CP_REG_RT_CPD_EXP_MARG__A 0x141003E +#define B_CP_REG_RT_CPD_EXP_MARG__W 5 +#define B_CP_REG_RT_CPD_EXP_MARG__M 0x1F +#define B_CP_REG_RT_CPD_EXP_MARG_INIT 0x3 + +#define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 +#define B_CP_REG_AC_NEXP_OFFS__W 8 +#define B_CP_REG_AC_NEXP_OFFS__M 0xFF +#define B_CP_REG_AC_NEXP_OFFS_INIT 0x0 + +#define B_CP_REG_AC_AVER_POW__A 0x1410041 +#define B_CP_REG_AC_AVER_POW__W 8 +#define B_CP_REG_AC_AVER_POW__M 0xFF +#define B_CP_REG_AC_AVER_POW_INIT 0x5F + +#define B_CP_REG_AC_MAX_POW__A 0x1410042 +#define B_CP_REG_AC_MAX_POW__W 8 +#define B_CP_REG_AC_MAX_POW__M 0xFF +#define B_CP_REG_AC_MAX_POW_INIT 0x7A + +#define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 +#define B_CP_REG_AC_WEIGHT_MAN__W 6 +#define B_CP_REG_AC_WEIGHT_MAN__M 0x3F +#define B_CP_REG_AC_WEIGHT_MAN_INIT 0x31 + +#define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 +#define B_CP_REG_AC_WEIGHT_EXP__W 5 +#define B_CP_REG_AC_WEIGHT_EXP__M 0x1F +#define B_CP_REG_AC_WEIGHT_EXP_INIT 0x10 + +#define B_CP_REG_AC_GAIN_MAN__A 0x1410045 +#define B_CP_REG_AC_GAIN_MAN__W 16 +#define B_CP_REG_AC_GAIN_MAN__M 0xFFFF +#define B_CP_REG_AC_GAIN_MAN_INIT 0x0 + +#define B_CP_REG_AC_GAIN_EXP__A 0x1410046 +#define B_CP_REG_AC_GAIN_EXP__W 5 +#define B_CP_REG_AC_GAIN_EXP__M 0x1F +#define B_CP_REG_AC_GAIN_EXP_INIT 0x0 + +#define B_CP_REG_AC_AMP_MODE__A 0x1410047 +#define B_CP_REG_AC_AMP_MODE__W 2 +#define B_CP_REG_AC_AMP_MODE__M 0x3 +#define B_CP_REG_AC_AMP_MODE_NEW 0x0 +#define B_CP_REG_AC_AMP_MODE_OLD 0x1 +#define B_CP_REG_AC_AMP_MODE_FIXED 0x2 +#define B_CP_REG_AC_AMP_MODE_INIT 0x2 + +#define B_CP_REG_AC_AMP_FIX__A 0x1410048 +#define B_CP_REG_AC_AMP_FIX__W 14 +#define B_CP_REG_AC_AMP_FIX__M 0x3FFF +#define B_CP_REG_AC_AMP_FIX_INIT 0x1FF + +#define B_CP_REG_AC_AMP_READ__A 0x1410049 +#define B_CP_REG_AC_AMP_READ__W 14 +#define B_CP_REG_AC_AMP_READ__M 0x3FFF +#define B_CP_REG_AC_AMP_READ_INIT 0x0 + +#define B_CP_REG_AC_ANG_MODE__A 0x141004A +#define B_CP_REG_AC_ANG_MODE__W 2 +#define B_CP_REG_AC_ANG_MODE__M 0x3 +#define B_CP_REG_AC_ANG_MODE_NEW 0x0 +#define B_CP_REG_AC_ANG_MODE_OLD 0x1 +#define B_CP_REG_AC_ANG_MODE_NO_INT 0x2 +#define B_CP_REG_AC_ANG_MODE_OFFSET 0x3 +#define B_CP_REG_AC_ANG_MODE_INIT 0x3 + +#define B_CP_REG_AC_ANG_OFFS__A 0x141004B +#define B_CP_REG_AC_ANG_OFFS__W 14 +#define B_CP_REG_AC_ANG_OFFS__M 0x3FFF +#define B_CP_REG_AC_ANG_OFFS_INIT 0x0 + +#define B_CP_REG_AC_ANG_READ__A 0x141004C +#define B_CP_REG_AC_ANG_READ__W 16 +#define B_CP_REG_AC_ANG_READ__M 0xFFFF +#define B_CP_REG_AC_ANG_READ_INIT 0x0 + +#define B_CP_REG_AC_ACCU_REAL0__A 0x1410060 +#define B_CP_REG_AC_ACCU_REAL0__W 8 +#define B_CP_REG_AC_ACCU_REAL0__M 0xFF +#define B_CP_REG_AC_ACCU_REAL0_INIT 0x0 + +#define B_CP_REG_AC_ACCU_IMAG0__A 0x1410061 +#define B_CP_REG_AC_ACCU_IMAG0__W 8 +#define B_CP_REG_AC_ACCU_IMAG0__M 0xFF +#define B_CP_REG_AC_ACCU_IMAG0_INIT 0x0 + +#define B_CP_REG_AC_ACCU_REAL1__A 0x1410062 +#define B_CP_REG_AC_ACCU_REAL1__W 8 +#define B_CP_REG_AC_ACCU_REAL1__M 0xFF +#define B_CP_REG_AC_ACCU_REAL1_INIT 0x0 + +#define B_CP_REG_AC_ACCU_IMAG1__A 0x1410063 +#define B_CP_REG_AC_ACCU_IMAG1__W 8 +#define B_CP_REG_AC_ACCU_IMAG1__M 0xFF +#define B_CP_REG_AC_ACCU_IMAG1_INIT 0x0 + +#define B_CP_REG_DL_MB_WR_ADDR__A 0x1410050 +#define B_CP_REG_DL_MB_WR_ADDR__W 15 +#define B_CP_REG_DL_MB_WR_ADDR__M 0x7FFF +#define B_CP_REG_DL_MB_WR_ADDR_INIT 0x0 + +#define B_CP_REG_DL_MB_WR_CTR__A 0x1410051 +#define B_CP_REG_DL_MB_WR_CTR__W 5 +#define B_CP_REG_DL_MB_WR_CTR__M 0x1F + +#define B_CP_REG_DL_MB_WR_CTR_WORD__B 2 +#define B_CP_REG_DL_MB_WR_CTR_WORD__W 3 +#define B_CP_REG_DL_MB_WR_CTR_WORD__M 0x1C + +#define B_CP_REG_DL_MB_WR_CTR_OBS__B 1 +#define B_CP_REG_DL_MB_WR_CTR_OBS__W 1 +#define B_CP_REG_DL_MB_WR_CTR_OBS__M 0x2 + +#define B_CP_REG_DL_MB_WR_CTR_CTR__B 0 +#define B_CP_REG_DL_MB_WR_CTR_CTR__W 1 +#define B_CP_REG_DL_MB_WR_CTR_CTR__M 0x1 +#define B_CP_REG_DL_MB_WR_CTR_INIT 0x0 + +#define B_CP_REG_DL_MB_RD_ADDR__A 0x1410052 +#define B_CP_REG_DL_MB_RD_ADDR__W 15 +#define B_CP_REG_DL_MB_RD_ADDR__M 0x7FFF +#define B_CP_REG_DL_MB_RD_ADDR_INIT 0x0 + +#define B_CP_REG_DL_MB_RD_CTR__A 0x1410053 +#define B_CP_REG_DL_MB_RD_CTR__W 11 +#define B_CP_REG_DL_MB_RD_CTR__M 0x7FF + +#define B_CP_REG_DL_MB_RD_CTR_TEST__B 10 +#define B_CP_REG_DL_MB_RD_CTR_TEST__W 1 +#define B_CP_REG_DL_MB_RD_CTR_TEST__M 0x400 + +#define B_CP_REG_DL_MB_RD_CTR_OFFSET__B 8 +#define B_CP_REG_DL_MB_RD_CTR_OFFSET__W 2 +#define B_CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 + +#define B_CP_REG_DL_MB_RD_CTR_VALID__B 5 +#define B_CP_REG_DL_MB_RD_CTR_VALID__W 3 +#define B_CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 + +#define B_CP_REG_DL_MB_RD_CTR_WORD__B 2 +#define B_CP_REG_DL_MB_RD_CTR_WORD__W 3 +#define B_CP_REG_DL_MB_RD_CTR_WORD__M 0x1C + +#define B_CP_REG_DL_MB_RD_CTR_OBS__B 1 +#define B_CP_REG_DL_MB_RD_CTR_OBS__W 1 +#define B_CP_REG_DL_MB_RD_CTR_OBS__M 0x2 + +#define B_CP_REG_DL_MB_RD_CTR_CTR__B 0 +#define B_CP_REG_DL_MB_RD_CTR_CTR__W 1 +#define B_CP_REG_DL_MB_RD_CTR_CTR__M 0x1 +#define B_CP_REG_DL_MB_RD_CTR_INIT 0x0 + +#define B_CP_BR_BUF_RAM__A 0x1420000 + +#define B_CP_BR_CPL_RAM__A 0x1430000 + +#define B_CP_PB_DL0_RAM__A 0x1440000 + +#define B_CP_PB_DL1_RAM__A 0x1450000 + +#define B_CP_PB_DL2_RAM__A 0x1460000 + +#define B_CE_SID 0xA + +#define B_CE_COMM_EXEC__A 0x1800000 +#define B_CE_COMM_EXEC__W 3 +#define B_CE_COMM_EXEC__M 0x7 +#define B_CE_COMM_EXEC_CTL__B 0 +#define B_CE_COMM_EXEC_CTL__W 3 +#define B_CE_COMM_EXEC_CTL__M 0x7 +#define B_CE_COMM_EXEC_CTL_STOP 0x0 +#define B_CE_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CE_COMM_EXEC_CTL_HOLD 0x2 +#define B_CE_COMM_EXEC_CTL_STEP 0x3 +#define B_CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_CE_COMM_STATE__A 0x1800001 +#define B_CE_COMM_STATE__W 16 +#define B_CE_COMM_STATE__M 0xFFFF +#define B_CE_COMM_MB__A 0x1800002 +#define B_CE_COMM_MB__W 16 +#define B_CE_COMM_MB__M 0xFFFF +#define B_CE_COMM_SERVICE0__A 0x1800003 +#define B_CE_COMM_SERVICE0__W 16 +#define B_CE_COMM_SERVICE0__M 0xFFFF +#define B_CE_COMM_SERVICE1__A 0x1800004 +#define B_CE_COMM_SERVICE1__W 16 +#define B_CE_COMM_SERVICE1__M 0xFFFF +#define B_CE_COMM_INT_STA__A 0x1800007 +#define B_CE_COMM_INT_STA__W 16 +#define B_CE_COMM_INT_STA__M 0xFFFF +#define B_CE_COMM_INT_MSK__A 0x1800008 +#define B_CE_COMM_INT_MSK__W 16 +#define B_CE_COMM_INT_MSK__M 0xFFFF + +#define B_CE_REG_COMM_EXEC__A 0x1810000 +#define B_CE_REG_COMM_EXEC__W 3 +#define B_CE_REG_COMM_EXEC__M 0x7 +#define B_CE_REG_COMM_EXEC_CTL__B 0 +#define B_CE_REG_COMM_EXEC_CTL__W 3 +#define B_CE_REG_COMM_EXEC_CTL__M 0x7 +#define B_CE_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CE_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_CE_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_CE_REG_COMM_MB__A 0x1810002 +#define B_CE_REG_COMM_MB__W 4 +#define B_CE_REG_COMM_MB__M 0xF +#define B_CE_REG_COMM_MB_CTR__B 0 +#define B_CE_REG_COMM_MB_CTR__W 1 +#define B_CE_REG_COMM_MB_CTR__M 0x1 +#define B_CE_REG_COMM_MB_CTR_OFF 0x0 +#define B_CE_REG_COMM_MB_CTR_ON 0x1 +#define B_CE_REG_COMM_MB_OBS__B 1 +#define B_CE_REG_COMM_MB_OBS__W 1 +#define B_CE_REG_COMM_MB_OBS__M 0x2 +#define B_CE_REG_COMM_MB_OBS_OFF 0x0 +#define B_CE_REG_COMM_MB_OBS_ON 0x2 +#define B_CE_REG_COMM_MB_OBS_SEL__B 2 +#define B_CE_REG_COMM_MB_OBS_SEL__W 2 +#define B_CE_REG_COMM_MB_OBS_SEL__M 0xC +#define B_CE_REG_COMM_MB_OBS_SEL_FI 0x0 +#define B_CE_REG_COMM_MB_OBS_SEL_TP 0x4 +#define B_CE_REG_COMM_MB_OBS_SEL_TI 0x8 +#define B_CE_REG_COMM_MB_OBS_SEL_FR 0x8 + +#define B_CE_REG_COMM_SERVICE0__A 0x1810003 +#define B_CE_REG_COMM_SERVICE0__W 10 +#define B_CE_REG_COMM_SERVICE0__M 0x3FF +#define B_CE_REG_COMM_SERVICE0_FT__B 8 +#define B_CE_REG_COMM_SERVICE0_FT__W 1 +#define B_CE_REG_COMM_SERVICE0_FT__M 0x100 + +#define B_CE_REG_COMM_SERVICE1__A 0x1810004 +#define B_CE_REG_COMM_SERVICE1__W 11 +#define B_CE_REG_COMM_SERVICE1__M 0x7FF + +#define B_CE_REG_COMM_INT_STA__A 0x1810007 +#define B_CE_REG_COMM_INT_STA__W 3 +#define B_CE_REG_COMM_INT_STA__M 0x7 +#define B_CE_REG_COMM_INT_STA_CE_PE__B 0 +#define B_CE_REG_COMM_INT_STA_CE_PE__W 1 +#define B_CE_REG_COMM_INT_STA_CE_PE__M 0x1 +#define B_CE_REG_COMM_INT_STA_CE_IR__B 1 +#define B_CE_REG_COMM_INT_STA_CE_IR__W 1 +#define B_CE_REG_COMM_INT_STA_CE_IR__M 0x2 +#define B_CE_REG_COMM_INT_STA_CE_FI__B 2 +#define B_CE_REG_COMM_INT_STA_CE_FI__W 1 +#define B_CE_REG_COMM_INT_STA_CE_FI__M 0x4 + +#define B_CE_REG_COMM_INT_MSK__A 0x1810008 +#define B_CE_REG_COMM_INT_MSK__W 3 +#define B_CE_REG_COMM_INT_MSK__M 0x7 +#define B_CE_REG_COMM_INT_MSK_CE_PE__B 0 +#define B_CE_REG_COMM_INT_MSK_CE_PE__W 1 +#define B_CE_REG_COMM_INT_MSK_CE_PE__M 0x1 +#define B_CE_REG_COMM_INT_MSK_CE_IR__B 1 +#define B_CE_REG_COMM_INT_MSK_CE_IR__W 1 +#define B_CE_REG_COMM_INT_MSK_CE_IR__M 0x2 +#define B_CE_REG_COMM_INT_MSK_CE_FI__B 2 +#define B_CE_REG_COMM_INT_MSK_CE_FI__W 1 +#define B_CE_REG_COMM_INT_MSK_CE_FI__M 0x4 + +#define B_CE_REG_2K__A 0x1810010 +#define B_CE_REG_2K__W 1 +#define B_CE_REG_2K__M 0x1 +#define B_CE_REG_2K_INIT 0x0 + +#define B_CE_REG_TAPSET__A 0x1810011 +#define B_CE_REG_TAPSET__W 4 +#define B_CE_REG_TAPSET__M 0xF + +#define B_CE_REG_TAPSET_MOTION_INIT 0x0 + +#define B_CE_REG_TAPSET_MOTION_NO 0x0 + +#define B_CE_REG_TAPSET_MOTION_LOW 0x1 + +#define B_CE_REG_TAPSET_MOTION_HIGH 0x2 + +#define B_CE_REG_TAPSET_MOTION_HIGH2 0x4 + +#define B_CE_REG_TAPSET_MOTION_UNDEFINED 0x8 + +#define B_CE_REG_AVG_POW__A 0x1810012 +#define B_CE_REG_AVG_POW__W 8 +#define B_CE_REG_AVG_POW__M 0xFF +#define B_CE_REG_AVG_POW_INIT 0x0 + +#define B_CE_REG_MAX_POW__A 0x1810013 +#define B_CE_REG_MAX_POW__W 8 +#define B_CE_REG_MAX_POW__M 0xFF +#define B_CE_REG_MAX_POW_INIT 0x0 + +#define B_CE_REG_ATT__A 0x1810014 +#define B_CE_REG_ATT__W 8 +#define B_CE_REG_ATT__M 0xFF +#define B_CE_REG_ATT_INIT 0x0 + +#define B_CE_REG_NRED__A 0x1810015 +#define B_CE_REG_NRED__W 6 +#define B_CE_REG_NRED__M 0x3F +#define B_CE_REG_NRED_INIT 0x0 + +#define B_CE_REG_PU_SIGN__A 0x1810020 +#define B_CE_REG_PU_SIGN__W 1 +#define B_CE_REG_PU_SIGN__M 0x1 +#define B_CE_REG_PU_SIGN_INIT 0x0 + +#define B_CE_REG_PU_MIX__A 0x1810021 +#define B_CE_REG_PU_MIX__W 1 +#define B_CE_REG_PU_MIX__M 0x1 +#define B_CE_REG_PU_MIX_INIT 0x0 + +#define B_CE_REG_PB_PILOT_REQ__A 0x1810030 +#define B_CE_REG_PB_PILOT_REQ__W 15 +#define B_CE_REG_PB_PILOT_REQ__M 0x7FFF +#define B_CE_REG_PB_PILOT_REQ_INIT 0x0 +#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 +#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 +#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 +#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 +#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 +#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF + +#define B_CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 +#define B_CE_REG_PB_PILOT_REQ_VALID__W 1 +#define B_CE_REG_PB_PILOT_REQ_VALID__M 0x1 +#define B_CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 + +#define B_CE_REG_PB_FREEZE__A 0x1810032 +#define B_CE_REG_PB_FREEZE__W 1 +#define B_CE_REG_PB_FREEZE__M 0x1 +#define B_CE_REG_PB_FREEZE_INIT 0x0 + +#define B_CE_REG_PB_PILOT_EXP__A 0x1810038 +#define B_CE_REG_PB_PILOT_EXP__W 4 +#define B_CE_REG_PB_PILOT_EXP__M 0xF +#define B_CE_REG_PB_PILOT_EXP_INIT 0x0 + +#define B_CE_REG_PB_PILOT_REAL__A 0x1810039 +#define B_CE_REG_PB_PILOT_REAL__W 10 +#define B_CE_REG_PB_PILOT_REAL__M 0x3FF +#define B_CE_REG_PB_PILOT_REAL_INIT 0x0 + +#define B_CE_REG_PB_PILOT_IMAG__A 0x181003A +#define B_CE_REG_PB_PILOT_IMAG__W 10 +#define B_CE_REG_PB_PILOT_IMAG__M 0x3FF +#define B_CE_REG_PB_PILOT_IMAG_INIT 0x0 + +#define B_CE_REG_PB_SMBNR__A 0x181003B +#define B_CE_REG_PB_SMBNR__W 5 +#define B_CE_REG_PB_SMBNR__M 0x1F +#define B_CE_REG_PB_SMBNR_INIT 0x0 + +#define B_CE_REG_NE_PILOT_REQ__A 0x1810040 +#define B_CE_REG_NE_PILOT_REQ__W 12 +#define B_CE_REG_NE_PILOT_REQ__M 0xFFF +#define B_CE_REG_NE_PILOT_REQ_INIT 0x0 + +#define B_CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 +#define B_CE_REG_NE_PILOT_REQ_VALID__W 2 +#define B_CE_REG_NE_PILOT_REQ_VALID__M 0x3 +#define B_CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 +#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 +#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 +#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 +#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 +#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 +#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 + +#define B_CE_REG_NE_PILOT_DATA__A 0x1810042 +#define B_CE_REG_NE_PILOT_DATA__W 10 +#define B_CE_REG_NE_PILOT_DATA__M 0x3FF +#define B_CE_REG_NE_PILOT_DATA_INIT 0x0 + +#define B_CE_REG_NE_ERR_SELECT__A 0x1810043 +#define B_CE_REG_NE_ERR_SELECT__W 5 +#define B_CE_REG_NE_ERR_SELECT__M 0x1F +#define B_CE_REG_NE_ERR_SELECT_INIT 0x7 + +#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__B 4 +#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__W 1 +#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__M 0x10 + +#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__B 3 +#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__W 1 +#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__M 0x8 + +#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 +#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 +#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 + +#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 +#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 +#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 + +#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 +#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 +#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 + +#define B_CE_REG_NE_TD_CAL__A 0x1810044 +#define B_CE_REG_NE_TD_CAL__W 9 +#define B_CE_REG_NE_TD_CAL__M 0x1FF +#define B_CE_REG_NE_TD_CAL_INIT 0x1E8 + +#define B_CE_REG_NE_FD_CAL__A 0x1810045 +#define B_CE_REG_NE_FD_CAL__W 9 +#define B_CE_REG_NE_FD_CAL__M 0x1FF +#define B_CE_REG_NE_FD_CAL_INIT 0x1D9 + +#define B_CE_REG_NE_MIXAVG__A 0x1810046 +#define B_CE_REG_NE_MIXAVG__W 3 +#define B_CE_REG_NE_MIXAVG__M 0x7 +#define B_CE_REG_NE_MIXAVG_INIT 0x6 + +#define B_CE_REG_NE_NUPD_OFS__A 0x1810047 +#define B_CE_REG_NE_NUPD_OFS__W 4 +#define B_CE_REG_NE_NUPD_OFS__M 0xF +#define B_CE_REG_NE_NUPD_OFS_INIT 0x4 + +#define B_CE_REG_NE_TD_POW__A 0x1810048 +#define B_CE_REG_NE_TD_POW__W 15 +#define B_CE_REG_NE_TD_POW__M 0x7FFF +#define B_CE_REG_NE_TD_POW_INIT 0x0 + +#define B_CE_REG_NE_TD_POW_EXPONENT__B 10 +#define B_CE_REG_NE_TD_POW_EXPONENT__W 5 +#define B_CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 + +#define B_CE_REG_NE_TD_POW_MANTISSA__B 0 +#define B_CE_REG_NE_TD_POW_MANTISSA__W 10 +#define B_CE_REG_NE_TD_POW_MANTISSA__M 0x3FF + +#define B_CE_REG_NE_FD_POW__A 0x1810049 +#define B_CE_REG_NE_FD_POW__W 15 +#define B_CE_REG_NE_FD_POW__M 0x7FFF +#define B_CE_REG_NE_FD_POW_INIT 0x0 + +#define B_CE_REG_NE_FD_POW_EXPONENT__B 10 +#define B_CE_REG_NE_FD_POW_EXPONENT__W 5 +#define B_CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 + +#define B_CE_REG_NE_FD_POW_MANTISSA__B 0 +#define B_CE_REG_NE_FD_POW_MANTISSA__W 10 +#define B_CE_REG_NE_FD_POW_MANTISSA__M 0x3FF + +#define B_CE_REG_NE_NEXP_AVG__A 0x181004A +#define B_CE_REG_NE_NEXP_AVG__W 8 +#define B_CE_REG_NE_NEXP_AVG__M 0xFF +#define B_CE_REG_NE_NEXP_AVG_INIT 0x0 + +#define B_CE_REG_NE_OFFSET__A 0x181004B +#define B_CE_REG_NE_OFFSET__W 9 +#define B_CE_REG_NE_OFFSET__M 0x1FF +#define B_CE_REG_NE_OFFSET_INIT 0x0 + +#define B_CE_REG_NE_NUPD_TRH__A 0x181004C +#define B_CE_REG_NE_NUPD_TRH__W 5 +#define B_CE_REG_NE_NUPD_TRH__M 0x1F +#define B_CE_REG_NE_NUPD_TRH_INIT 0x14 + +#define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 +#define B_CE_REG_PE_NEXP_OFFS__W 8 +#define B_CE_REG_PE_NEXP_OFFS__M 0xFF +#define B_CE_REG_PE_NEXP_OFFS_INIT 0x0 + +#define B_CE_REG_PE_TIMESHIFT__A 0x1810051 +#define B_CE_REG_PE_TIMESHIFT__W 14 +#define B_CE_REG_PE_TIMESHIFT__M 0x3FFF +#define B_CE_REG_PE_TIMESHIFT_INIT 0x0 + +#define B_CE_REG_PE_DIF_REAL_L__A 0x1810052 +#define B_CE_REG_PE_DIF_REAL_L__W 16 +#define B_CE_REG_PE_DIF_REAL_L__M 0xFFFF +#define B_CE_REG_PE_DIF_REAL_L_INIT 0x0 + +#define B_CE_REG_PE_DIF_IMAG_L__A 0x1810053 +#define B_CE_REG_PE_DIF_IMAG_L__W 16 +#define B_CE_REG_PE_DIF_IMAG_L__M 0xFFFF +#define B_CE_REG_PE_DIF_IMAG_L_INIT 0x0 + +#define B_CE_REG_PE_DIF_REAL_R__A 0x1810054 +#define B_CE_REG_PE_DIF_REAL_R__W 16 +#define B_CE_REG_PE_DIF_REAL_R__M 0xFFFF +#define B_CE_REG_PE_DIF_REAL_R_INIT 0x0 + +#define B_CE_REG_PE_DIF_IMAG_R__A 0x1810055 +#define B_CE_REG_PE_DIF_IMAG_R__W 16 +#define B_CE_REG_PE_DIF_IMAG_R__M 0xFFFF +#define B_CE_REG_PE_DIF_IMAG_R_INIT 0x0 + +#define B_CE_REG_PE_ABS_REAL_L__A 0x1810056 +#define B_CE_REG_PE_ABS_REAL_L__W 16 +#define B_CE_REG_PE_ABS_REAL_L__M 0xFFFF +#define B_CE_REG_PE_ABS_REAL_L_INIT 0x0 + +#define B_CE_REG_PE_ABS_IMAG_L__A 0x1810057 +#define B_CE_REG_PE_ABS_IMAG_L__W 16 +#define B_CE_REG_PE_ABS_IMAG_L__M 0xFFFF +#define B_CE_REG_PE_ABS_IMAG_L_INIT 0x0 + +#define B_CE_REG_PE_ABS_REAL_R__A 0x1810058 +#define B_CE_REG_PE_ABS_REAL_R__W 16 +#define B_CE_REG_PE_ABS_REAL_R__M 0xFFFF +#define B_CE_REG_PE_ABS_REAL_R_INIT 0x0 + +#define B_CE_REG_PE_ABS_IMAG_R__A 0x1810059 +#define B_CE_REG_PE_ABS_IMAG_R__W 16 +#define B_CE_REG_PE_ABS_IMAG_R__M 0xFFFF +#define B_CE_REG_PE_ABS_IMAG_R_INIT 0x0 + +#define B_CE_REG_PE_ABS_EXP_L__A 0x181005A +#define B_CE_REG_PE_ABS_EXP_L__W 5 +#define B_CE_REG_PE_ABS_EXP_L__M 0x1F +#define B_CE_REG_PE_ABS_EXP_L_INIT 0x0 + +#define B_CE_REG_PE_ABS_EXP_R__A 0x181005B +#define B_CE_REG_PE_ABS_EXP_R__W 5 +#define B_CE_REG_PE_ABS_EXP_R__M 0x1F +#define B_CE_REG_PE_ABS_EXP_R_INIT 0x0 + +#define B_CE_REG_TP_UPDATE_MODE__A 0x1810060 +#define B_CE_REG_TP_UPDATE_MODE__W 1 +#define B_CE_REG_TP_UPDATE_MODE__M 0x1 +#define B_CE_REG_TP_UPDATE_MODE_INIT 0x0 + +#define B_CE_REG_TP_LMS_TAP_ON__A 0x1810061 +#define B_CE_REG_TP_LMS_TAP_ON__W 1 +#define B_CE_REG_TP_LMS_TAP_ON__M 0x1 + +#define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064 +#define B_CE_REG_TP_A0_TAP_NEW__W 10 +#define B_CE_REG_TP_A0_TAP_NEW__M 0x3FF + +#define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 +#define B_CE_REG_TP_A0_TAP_NEW_VALID__W 1 +#define B_CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 + +#define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 +#define B_CE_REG_TP_A0_MU_LMS_STEP__W 5 +#define B_CE_REG_TP_A0_MU_LMS_STEP__M 0x1F + +#define B_CE_REG_TP_A0_TAP_CURR__A 0x1810067 +#define B_CE_REG_TP_A0_TAP_CURR__W 10 +#define B_CE_REG_TP_A0_TAP_CURR__M 0x3FF + +#define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068 +#define B_CE_REG_TP_A1_TAP_NEW__W 10 +#define B_CE_REG_TP_A1_TAP_NEW__M 0x3FF + +#define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 +#define B_CE_REG_TP_A1_TAP_NEW_VALID__W 1 +#define B_CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 + +#define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A +#define B_CE_REG_TP_A1_MU_LMS_STEP__W 5 +#define B_CE_REG_TP_A1_MU_LMS_STEP__M 0x1F + +#define B_CE_REG_TP_A1_TAP_CURR__A 0x181006B +#define B_CE_REG_TP_A1_TAP_CURR__W 10 +#define B_CE_REG_TP_A1_TAP_CURR__M 0x3FF + +#define B_CE_REG_TP_DOPP_ENERGY__A 0x181006C +#define B_CE_REG_TP_DOPP_ENERGY__W 15 +#define B_CE_REG_TP_DOPP_ENERGY__M 0x7FFF +#define B_CE_REG_TP_DOPP_ENERGY_INIT 0x0 + +#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 +#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 +#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 + +#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 +#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 +#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF + +#define B_CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D +#define B_CE_REG_TP_DOPP_DIFF_ENERGY__W 15 +#define B_CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 + +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 + +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 +#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF + +#define B_CE_REG_TP_A0_TAP_ENERGY__A 0x181006E +#define B_CE_REG_TP_A0_TAP_ENERGY__W 15 +#define B_CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF +#define B_CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 + +#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 +#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 +#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 + +#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 +#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 +#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF + +#define B_CE_REG_TP_A1_TAP_ENERGY__A 0x181006F +#define B_CE_REG_TP_A1_TAP_ENERGY__W 15 +#define B_CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF +#define B_CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 + +#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 +#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 +#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 + +#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 +#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 +#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF + +#define B_CE_REG_TI_SYM_CNT__A 0x1810072 +#define B_CE_REG_TI_SYM_CNT__W 6 +#define B_CE_REG_TI_SYM_CNT__M 0x3F +#define B_CE_REG_TI_SYM_CNT_INIT 0x0 + +#define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 +#define B_CE_REG_TI_PHN_ENABLE__W 1 +#define B_CE_REG_TI_PHN_ENABLE__M 0x1 +#define B_CE_REG_TI_PHN_ENABLE_INIT 0x0 + +#define B_CE_REG_TI_SHIFT__A 0x1810074 +#define B_CE_REG_TI_SHIFT__W 2 +#define B_CE_REG_TI_SHIFT__M 0x3 +#define B_CE_REG_TI_SHIFT_INIT 0x0 + +#define B_CE_REG_TI_SLOW__A 0x1810075 +#define B_CE_REG_TI_SLOW__W 1 +#define B_CE_REG_TI_SLOW__M 0x1 +#define B_CE_REG_TI_SLOW_INIT 0x0 + +#define B_CE_REG_TI_MGAIN__A 0x1810076 +#define B_CE_REG_TI_MGAIN__W 8 +#define B_CE_REG_TI_MGAIN__M 0xFF +#define B_CE_REG_TI_MGAIN_INIT 0x0 + +#define B_CE_REG_TI_ACCU1__A 0x1810077 +#define B_CE_REG_TI_ACCU1__W 8 +#define B_CE_REG_TI_ACCU1__M 0xFF +#define B_CE_REG_TI_ACCU1_INIT 0x0 + +#define B_CE_REG_NI_PER_LEFT__A 0x18100B0 +#define B_CE_REG_NI_PER_LEFT__W 5 +#define B_CE_REG_NI_PER_LEFT__M 0x1F +#define B_CE_REG_NI_PER_LEFT_INIT 0xE + +#define B_CE_REG_NI_PER_RIGHT__A 0x18100B1 +#define B_CE_REG_NI_PER_RIGHT__W 5 +#define B_CE_REG_NI_PER_RIGHT__M 0x1F +#define B_CE_REG_NI_PER_RIGHT_INIT 0x7 + +#define B_CE_REG_NI_POS_LR__A 0x18100B2 +#define B_CE_REG_NI_POS_LR__W 9 +#define B_CE_REG_NI_POS_LR__M 0x1FF +#define B_CE_REG_NI_POS_LR_INIT 0xA0 + +#define B_CE_REG_FI_SHT_INCR__A 0x1810090 +#define B_CE_REG_FI_SHT_INCR__W 7 +#define B_CE_REG_FI_SHT_INCR__M 0x7F +#define B_CE_REG_FI_SHT_INCR_INIT 0x9 + +#define B_CE_REG_FI_EXP_NORM__A 0x1810091 +#define B_CE_REG_FI_EXP_NORM__W 4 +#define B_CE_REG_FI_EXP_NORM__M 0xF +#define B_CE_REG_FI_EXP_NORM_INIT 0x4 + +#define B_CE_REG_FI_SUPR_VAL__A 0x1810092 +#define B_CE_REG_FI_SUPR_VAL__W 1 +#define B_CE_REG_FI_SUPR_VAL__M 0x1 +#define B_CE_REG_FI_SUPR_VAL_INIT 0x1 + +#define B_CE_REG_IR_INPUTSEL__A 0x18100A0 +#define B_CE_REG_IR_INPUTSEL__W 1 +#define B_CE_REG_IR_INPUTSEL__M 0x1 +#define B_CE_REG_IR_INPUTSEL_INIT 0x0 + +#define B_CE_REG_IR_STARTPOS__A 0x18100A1 +#define B_CE_REG_IR_STARTPOS__W 8 +#define B_CE_REG_IR_STARTPOS__M 0xFF +#define B_CE_REG_IR_STARTPOS_INIT 0x0 + +#define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 +#define B_CE_REG_IR_NEXP_THRES__W 8 +#define B_CE_REG_IR_NEXP_THRES__M 0xFF +#define B_CE_REG_IR_NEXP_THRES_INIT 0x0 + +#define B_CE_REG_IR_LENGTH__A 0x18100A3 +#define B_CE_REG_IR_LENGTH__W 4 +#define B_CE_REG_IR_LENGTH__M 0xF +#define B_CE_REG_IR_LENGTH_INIT 0x0 + +#define B_CE_REG_IR_FREQ__A 0x18100A4 +#define B_CE_REG_IR_FREQ__W 11 +#define B_CE_REG_IR_FREQ__M 0x7FF +#define B_CE_REG_IR_FREQ_INIT 0x0 + +#define B_CE_REG_IR_FREQINC__A 0x18100A5 +#define B_CE_REG_IR_FREQINC__W 11 +#define B_CE_REG_IR_FREQINC__M 0x7FF +#define B_CE_REG_IR_FREQINC_INIT 0x0 + +#define B_CE_REG_IR_KAISINC__A 0x18100A6 +#define B_CE_REG_IR_KAISINC__W 15 +#define B_CE_REG_IR_KAISINC__M 0x7FFF +#define B_CE_REG_IR_KAISINC_INIT 0x0 + +#define B_CE_REG_IR_CTL__A 0x18100A7 +#define B_CE_REG_IR_CTL__W 3 +#define B_CE_REG_IR_CTL__M 0x7 +#define B_CE_REG_IR_CTL_INIT 0x0 + +#define B_CE_REG_IR_REAL__A 0x18100A8 +#define B_CE_REG_IR_REAL__W 16 +#define B_CE_REG_IR_REAL__M 0xFFFF +#define B_CE_REG_IR_REAL_INIT 0x0 + +#define B_CE_REG_IR_IMAG__A 0x18100A9 +#define B_CE_REG_IR_IMAG__W 16 +#define B_CE_REG_IR_IMAG__M 0xFFFF +#define B_CE_REG_IR_IMAG_INIT 0x0 + +#define B_CE_REG_IR_INDEX__A 0x18100AA +#define B_CE_REG_IR_INDEX__W 12 +#define B_CE_REG_IR_INDEX__M 0xFFF +#define B_CE_REG_IR_INDEX_INIT 0x0 + +#define B_CE_REG_FR_COMM_EXEC__A 0x1820000 +#define B_CE_REG_FR_COMM_EXEC__W 1 +#define B_CE_REG_FR_COMM_EXEC__M 0x1 + +#define B_CE_REG_FR_TREAL00__A 0x1820010 +#define B_CE_REG_FR_TREAL00__W 11 +#define B_CE_REG_FR_TREAL00__M 0x7FF +#define B_CE_REG_FR_TREAL00_INIT 0x52 + +#define B_CE_REG_FR_TIMAG00__A 0x1820011 +#define B_CE_REG_FR_TIMAG00__W 11 +#define B_CE_REG_FR_TIMAG00__M 0x7FF +#define B_CE_REG_FR_TIMAG00_INIT 0x0 + +#define B_CE_REG_FR_TREAL01__A 0x1820012 +#define B_CE_REG_FR_TREAL01__W 11 +#define B_CE_REG_FR_TREAL01__M 0x7FF +#define B_CE_REG_FR_TREAL01_INIT 0x52 + +#define B_CE_REG_FR_TIMAG01__A 0x1820013 +#define B_CE_REG_FR_TIMAG01__W 11 +#define B_CE_REG_FR_TIMAG01__M 0x7FF +#define B_CE_REG_FR_TIMAG01_INIT 0x0 + +#define B_CE_REG_FR_TREAL02__A 0x1820014 +#define B_CE_REG_FR_TREAL02__W 11 +#define B_CE_REG_FR_TREAL02__M 0x7FF +#define B_CE_REG_FR_TREAL02_INIT 0x52 + +#define B_CE_REG_FR_TIMAG02__A 0x1820015 +#define B_CE_REG_FR_TIMAG02__W 11 +#define B_CE_REG_FR_TIMAG02__M 0x7FF +#define B_CE_REG_FR_TIMAG02_INIT 0x0 + +#define B_CE_REG_FR_TREAL03__A 0x1820016 +#define B_CE_REG_FR_TREAL03__W 11 +#define B_CE_REG_FR_TREAL03__M 0x7FF +#define B_CE_REG_FR_TREAL03_INIT 0x52 + +#define B_CE_REG_FR_TIMAG03__A 0x1820017 +#define B_CE_REG_FR_TIMAG03__W 11 +#define B_CE_REG_FR_TIMAG03__M 0x7FF +#define B_CE_REG_FR_TIMAG03_INIT 0x0 + +#define B_CE_REG_FR_TREAL04__A 0x1820018 +#define B_CE_REG_FR_TREAL04__W 11 +#define B_CE_REG_FR_TREAL04__M 0x7FF +#define B_CE_REG_FR_TREAL04_INIT 0x52 + +#define B_CE_REG_FR_TIMAG04__A 0x1820019 +#define B_CE_REG_FR_TIMAG04__W 11 +#define B_CE_REG_FR_TIMAG04__M 0x7FF +#define B_CE_REG_FR_TIMAG04_INIT 0x0 + +#define B_CE_REG_FR_TREAL05__A 0x182001A +#define B_CE_REG_FR_TREAL05__W 11 +#define B_CE_REG_FR_TREAL05__M 0x7FF +#define B_CE_REG_FR_TREAL05_INIT 0x52 + +#define B_CE_REG_FR_TIMAG05__A 0x182001B +#define B_CE_REG_FR_TIMAG05__W 11 +#define B_CE_REG_FR_TIMAG05__M 0x7FF +#define B_CE_REG_FR_TIMAG05_INIT 0x0 + +#define B_CE_REG_FR_TREAL06__A 0x182001C +#define B_CE_REG_FR_TREAL06__W 11 +#define B_CE_REG_FR_TREAL06__M 0x7FF +#define B_CE_REG_FR_TREAL06_INIT 0x52 + +#define B_CE_REG_FR_TIMAG06__A 0x182001D +#define B_CE_REG_FR_TIMAG06__W 11 +#define B_CE_REG_FR_TIMAG06__M 0x7FF +#define B_CE_REG_FR_TIMAG06_INIT 0x0 + +#define B_CE_REG_FR_TREAL07__A 0x182001E +#define B_CE_REG_FR_TREAL07__W 11 +#define B_CE_REG_FR_TREAL07__M 0x7FF +#define B_CE_REG_FR_TREAL07_INIT 0x52 + +#define B_CE_REG_FR_TIMAG07__A 0x182001F +#define B_CE_REG_FR_TIMAG07__W 11 +#define B_CE_REG_FR_TIMAG07__M 0x7FF +#define B_CE_REG_FR_TIMAG07_INIT 0x0 + +#define B_CE_REG_FR_TREAL08__A 0x1820020 +#define B_CE_REG_FR_TREAL08__W 11 +#define B_CE_REG_FR_TREAL08__M 0x7FF +#define B_CE_REG_FR_TREAL08_INIT 0x52 + +#define B_CE_REG_FR_TIMAG08__A 0x1820021 +#define B_CE_REG_FR_TIMAG08__W 11 +#define B_CE_REG_FR_TIMAG08__M 0x7FF +#define B_CE_REG_FR_TIMAG08_INIT 0x0 + +#define B_CE_REG_FR_TREAL09__A 0x1820022 +#define B_CE_REG_FR_TREAL09__W 11 +#define B_CE_REG_FR_TREAL09__M 0x7FF +#define B_CE_REG_FR_TREAL09_INIT 0x52 + +#define B_CE_REG_FR_TIMAG09__A 0x1820023 +#define B_CE_REG_FR_TIMAG09__W 11 +#define B_CE_REG_FR_TIMAG09__M 0x7FF +#define B_CE_REG_FR_TIMAG09_INIT 0x0 + +#define B_CE_REG_FR_TREAL10__A 0x1820024 +#define B_CE_REG_FR_TREAL10__W 11 +#define B_CE_REG_FR_TREAL10__M 0x7FF +#define B_CE_REG_FR_TREAL10_INIT 0x52 + +#define B_CE_REG_FR_TIMAG10__A 0x1820025 +#define B_CE_REG_FR_TIMAG10__W 11 +#define B_CE_REG_FR_TIMAG10__M 0x7FF +#define B_CE_REG_FR_TIMAG10_INIT 0x0 + +#define B_CE_REG_FR_TREAL11__A 0x1820026 +#define B_CE_REG_FR_TREAL11__W 11 +#define B_CE_REG_FR_TREAL11__M 0x7FF +#define B_CE_REG_FR_TREAL11_INIT 0x52 + +#define B_CE_REG_FR_TIMAG11__A 0x1820027 +#define B_CE_REG_FR_TIMAG11__W 11 +#define B_CE_REG_FR_TIMAG11__M 0x7FF +#define B_CE_REG_FR_TIMAG11_INIT 0x0 + +#define B_CE_REG_FR_MID_TAP__A 0x1820028 +#define B_CE_REG_FR_MID_TAP__W 11 +#define B_CE_REG_FR_MID_TAP__M 0x7FF +#define B_CE_REG_FR_MID_TAP_INIT 0x51 + +#define B_CE_REG_FR_SQS_G00__A 0x1820029 +#define B_CE_REG_FR_SQS_G00__W 8 +#define B_CE_REG_FR_SQS_G00__M 0xFF +#define B_CE_REG_FR_SQS_G00_INIT 0xB + +#define B_CE_REG_FR_SQS_G01__A 0x182002A +#define B_CE_REG_FR_SQS_G01__W 8 +#define B_CE_REG_FR_SQS_G01__M 0xFF +#define B_CE_REG_FR_SQS_G01_INIT 0xB + +#define B_CE_REG_FR_SQS_G02__A 0x182002B +#define B_CE_REG_FR_SQS_G02__W 8 +#define B_CE_REG_FR_SQS_G02__M 0xFF +#define B_CE_REG_FR_SQS_G02_INIT 0xB + +#define B_CE_REG_FR_SQS_G03__A 0x182002C +#define B_CE_REG_FR_SQS_G03__W 8 +#define B_CE_REG_FR_SQS_G03__M 0xFF +#define B_CE_REG_FR_SQS_G03_INIT 0xB + +#define B_CE_REG_FR_SQS_G04__A 0x182002D +#define B_CE_REG_FR_SQS_G04__W 8 +#define B_CE_REG_FR_SQS_G04__M 0xFF +#define B_CE_REG_FR_SQS_G04_INIT 0xB + +#define B_CE_REG_FR_SQS_G05__A 0x182002E +#define B_CE_REG_FR_SQS_G05__W 8 +#define B_CE_REG_FR_SQS_G05__M 0xFF +#define B_CE_REG_FR_SQS_G05_INIT 0xB + +#define B_CE_REG_FR_SQS_G06__A 0x182002F +#define B_CE_REG_FR_SQS_G06__W 8 +#define B_CE_REG_FR_SQS_G06__M 0xFF +#define B_CE_REG_FR_SQS_G06_INIT 0xB + +#define B_CE_REG_FR_SQS_G07__A 0x1820030 +#define B_CE_REG_FR_SQS_G07__W 8 +#define B_CE_REG_FR_SQS_G07__M 0xFF +#define B_CE_REG_FR_SQS_G07_INIT 0xB + +#define B_CE_REG_FR_SQS_G08__A 0x1820031 +#define B_CE_REG_FR_SQS_G08__W 8 +#define B_CE_REG_FR_SQS_G08__M 0xFF +#define B_CE_REG_FR_SQS_G08_INIT 0xB + +#define B_CE_REG_FR_SQS_G09__A 0x1820032 +#define B_CE_REG_FR_SQS_G09__W 8 +#define B_CE_REG_FR_SQS_G09__M 0xFF +#define B_CE_REG_FR_SQS_G09_INIT 0xB + +#define B_CE_REG_FR_SQS_G10__A 0x1820033 +#define B_CE_REG_FR_SQS_G10__W 8 +#define B_CE_REG_FR_SQS_G10__M 0xFF +#define B_CE_REG_FR_SQS_G10_INIT 0xB + +#define B_CE_REG_FR_SQS_G11__A 0x1820034 +#define B_CE_REG_FR_SQS_G11__W 8 +#define B_CE_REG_FR_SQS_G11__M 0xFF +#define B_CE_REG_FR_SQS_G11_INIT 0xB + +#define B_CE_REG_FR_SQS_G12__A 0x1820035 +#define B_CE_REG_FR_SQS_G12__W 8 +#define B_CE_REG_FR_SQS_G12__M 0xFF +#define B_CE_REG_FR_SQS_G12_INIT 0x5 + +#define B_CE_REG_FR_RIO_G00__A 0x1820036 +#define B_CE_REG_FR_RIO_G00__W 9 +#define B_CE_REG_FR_RIO_G00__M 0x1FF +#define B_CE_REG_FR_RIO_G00_INIT 0x1FF + +#define B_CE_REG_FR_RIO_G01__A 0x1820037 +#define B_CE_REG_FR_RIO_G01__W 9 +#define B_CE_REG_FR_RIO_G01__M 0x1FF +#define B_CE_REG_FR_RIO_G01_INIT 0x190 + +#define B_CE_REG_FR_RIO_G02__A 0x1820038 +#define B_CE_REG_FR_RIO_G02__W 9 +#define B_CE_REG_FR_RIO_G02__M 0x1FF +#define B_CE_REG_FR_RIO_G02_INIT 0x10B + +#define B_CE_REG_FR_RIO_G03__A 0x1820039 +#define B_CE_REG_FR_RIO_G03__W 9 +#define B_CE_REG_FR_RIO_G03__M 0x1FF +#define B_CE_REG_FR_RIO_G03_INIT 0xC8 + +#define B_CE_REG_FR_RIO_G04__A 0x182003A +#define B_CE_REG_FR_RIO_G04__W 9 +#define B_CE_REG_FR_RIO_G04__M 0x1FF +#define B_CE_REG_FR_RIO_G04_INIT 0xA0 + +#define B_CE_REG_FR_RIO_G05__A 0x182003B +#define B_CE_REG_FR_RIO_G05__W 9 +#define B_CE_REG_FR_RIO_G05__M 0x1FF +#define B_CE_REG_FR_RIO_G05_INIT 0x85 + +#define B_CE_REG_FR_RIO_G06__A 0x182003C +#define B_CE_REG_FR_RIO_G06__W 9 +#define B_CE_REG_FR_RIO_G06__M 0x1FF +#define B_CE_REG_FR_RIO_G06_INIT 0x72 + +#define B_CE_REG_FR_RIO_G07__A 0x182003D +#define B_CE_REG_FR_RIO_G07__W 9 +#define B_CE_REG_FR_RIO_G07__M 0x1FF +#define B_CE_REG_FR_RIO_G07_INIT 0x64 + +#define B_CE_REG_FR_RIO_G08__A 0x182003E +#define B_CE_REG_FR_RIO_G08__W 9 +#define B_CE_REG_FR_RIO_G08__M 0x1FF +#define B_CE_REG_FR_RIO_G08_INIT 0x59 + +#define B_CE_REG_FR_RIO_G09__A 0x182003F +#define B_CE_REG_FR_RIO_G09__W 9 +#define B_CE_REG_FR_RIO_G09__M 0x1FF +#define B_CE_REG_FR_RIO_G09_INIT 0x50 + +#define B_CE_REG_FR_RIO_G10__A 0x1820040 +#define B_CE_REG_FR_RIO_G10__W 9 +#define B_CE_REG_FR_RIO_G10__M 0x1FF +#define B_CE_REG_FR_RIO_G10_INIT 0x49 + +#define B_CE_REG_FR_MODE__A 0x1820041 +#define B_CE_REG_FR_MODE__W 9 +#define B_CE_REG_FR_MODE__M 0x1FF + +#define B_CE_REG_FR_MODE_UPDATE_ENABLE__B 0 +#define B_CE_REG_FR_MODE_UPDATE_ENABLE__W 1 +#define B_CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 + +#define B_CE_REG_FR_MODE_ERROR_SHIFT__B 1 +#define B_CE_REG_FR_MODE_ERROR_SHIFT__W 1 +#define B_CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 + +#define B_CE_REG_FR_MODE_NEXP_UPDATE__B 2 +#define B_CE_REG_FR_MODE_NEXP_UPDATE__W 1 +#define B_CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 + +#define B_CE_REG_FR_MODE_MANUAL_SHIFT__B 3 +#define B_CE_REG_FR_MODE_MANUAL_SHIFT__W 1 +#define B_CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 + +#define B_CE_REG_FR_MODE_SQUASH_MODE__B 4 +#define B_CE_REG_FR_MODE_SQUASH_MODE__W 1 +#define B_CE_REG_FR_MODE_SQUASH_MODE__M 0x10 + +#define B_CE_REG_FR_MODE_UPDATE_MODE__B 5 +#define B_CE_REG_FR_MODE_UPDATE_MODE__W 1 +#define B_CE_REG_FR_MODE_UPDATE_MODE__M 0x20 + +#define B_CE_REG_FR_MODE_MID_MODE__B 6 +#define B_CE_REG_FR_MODE_MID_MODE__W 1 +#define B_CE_REG_FR_MODE_MID_MODE__M 0x40 + +#define B_CE_REG_FR_MODE_NOISE_MODE__B 7 +#define B_CE_REG_FR_MODE_NOISE_MODE__W 1 +#define B_CE_REG_FR_MODE_NOISE_MODE__M 0x80 + +#define B_CE_REG_FR_MODE_NOTCH_MODE__B 8 +#define B_CE_REG_FR_MODE_NOTCH_MODE__W 1 +#define B_CE_REG_FR_MODE_NOTCH_MODE__M 0x100 +#define B_CE_REG_FR_MODE_INIT 0xDE + +#define B_CE_REG_FR_SQS_TRH__A 0x1820042 +#define B_CE_REG_FR_SQS_TRH__W 8 +#define B_CE_REG_FR_SQS_TRH__M 0xFF +#define B_CE_REG_FR_SQS_TRH_INIT 0x80 + +#define B_CE_REG_FR_RIO_GAIN__A 0x1820043 +#define B_CE_REG_FR_RIO_GAIN__W 3 +#define B_CE_REG_FR_RIO_GAIN__M 0x7 +#define B_CE_REG_FR_RIO_GAIN_INIT 0x2 + +#define B_CE_REG_FR_BYPASS__A 0x1820044 +#define B_CE_REG_FR_BYPASS__W 10 +#define B_CE_REG_FR_BYPASS__M 0x3FF + +#define B_CE_REG_FR_BYPASS_RUN_IN__B 0 +#define B_CE_REG_FR_BYPASS_RUN_IN__W 4 +#define B_CE_REG_FR_BYPASS_RUN_IN__M 0xF + +#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 +#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 +#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 + +#define B_CE_REG_FR_BYPASS_TOTAL__B 9 +#define B_CE_REG_FR_BYPASS_TOTAL__W 1 +#define B_CE_REG_FR_BYPASS_TOTAL__M 0x200 +#define B_CE_REG_FR_BYPASS_INIT 0x13B + +#define B_CE_REG_FR_PM_SET__A 0x1820045 +#define B_CE_REG_FR_PM_SET__W 4 +#define B_CE_REG_FR_PM_SET__M 0xF +#define B_CE_REG_FR_PM_SET_INIT 0x4 + +#define B_CE_REG_FR_ERR_SH__A 0x1820046 +#define B_CE_REG_FR_ERR_SH__W 4 +#define B_CE_REG_FR_ERR_SH__M 0xF +#define B_CE_REG_FR_ERR_SH_INIT 0x4 + +#define B_CE_REG_FR_MAN_SH__A 0x1820047 +#define B_CE_REG_FR_MAN_SH__W 4 +#define B_CE_REG_FR_MAN_SH__M 0xF +#define B_CE_REG_FR_MAN_SH_INIT 0x7 + +#define B_CE_REG_FR_TAP_SH__A 0x1820048 +#define B_CE_REG_FR_TAP_SH__W 3 +#define B_CE_REG_FR_TAP_SH__M 0x7 +#define B_CE_REG_FR_TAP_SH_INIT 0x3 + +#define B_CE_REG_FR_CLIP__A 0x1820049 +#define B_CE_REG_FR_CLIP__W 9 +#define B_CE_REG_FR_CLIP__M 0x1FF +#define B_CE_REG_FR_CLIP_INIT 0x49 + +#define B_CE_REG_FR_LEAK_UPD__A 0x182004A +#define B_CE_REG_FR_LEAK_UPD__W 3 +#define B_CE_REG_FR_LEAK_UPD__M 0x7 +#define B_CE_REG_FR_LEAK_UPD_INIT 0x1 + +#define B_CE_REG_FR_LEAK_SH__A 0x182004B +#define B_CE_REG_FR_LEAK_SH__W 3 +#define B_CE_REG_FR_LEAK_SH__M 0x7 +#define B_CE_REG_FR_LEAK_SH_INIT 0x1 + +#define B_CE_PB_RAM__A 0x1830000 + +#define B_CE_NE_RAM__A 0x1840000 + +#define B_EQ_SID 0xE + +#define B_EQ_COMM_EXEC__A 0x1C00000 +#define B_EQ_COMM_EXEC__W 3 +#define B_EQ_COMM_EXEC__M 0x7 +#define B_EQ_COMM_EXEC_CTL__B 0 +#define B_EQ_COMM_EXEC_CTL__W 3 +#define B_EQ_COMM_EXEC_CTL__M 0x7 +#define B_EQ_COMM_EXEC_CTL_STOP 0x0 +#define B_EQ_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EQ_COMM_EXEC_CTL_HOLD 0x2 +#define B_EQ_COMM_EXEC_CTL_STEP 0x3 +#define B_EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_EQ_COMM_STATE__A 0x1C00001 +#define B_EQ_COMM_STATE__W 16 +#define B_EQ_COMM_STATE__M 0xFFFF +#define B_EQ_COMM_MB__A 0x1C00002 +#define B_EQ_COMM_MB__W 16 +#define B_EQ_COMM_MB__M 0xFFFF +#define B_EQ_COMM_SERVICE0__A 0x1C00003 +#define B_EQ_COMM_SERVICE0__W 16 +#define B_EQ_COMM_SERVICE0__M 0xFFFF +#define B_EQ_COMM_SERVICE1__A 0x1C00004 +#define B_EQ_COMM_SERVICE1__W 16 +#define B_EQ_COMM_SERVICE1__M 0xFFFF +#define B_EQ_COMM_INT_STA__A 0x1C00007 +#define B_EQ_COMM_INT_STA__W 16 +#define B_EQ_COMM_INT_STA__M 0xFFFF +#define B_EQ_COMM_INT_MSK__A 0x1C00008 +#define B_EQ_COMM_INT_MSK__W 16 +#define B_EQ_COMM_INT_MSK__M 0xFFFF + +#define B_EQ_REG_COMM_EXEC__A 0x1C10000 +#define B_EQ_REG_COMM_EXEC__W 3 +#define B_EQ_REG_COMM_EXEC__M 0x7 +#define B_EQ_REG_COMM_EXEC_CTL__B 0 +#define B_EQ_REG_COMM_EXEC_CTL__W 3 +#define B_EQ_REG_COMM_EXEC_CTL__M 0x7 +#define B_EQ_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EQ_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_EQ_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_EQ_REG_COMM_STATE__A 0x1C10001 +#define B_EQ_REG_COMM_STATE__W 4 +#define B_EQ_REG_COMM_STATE__M 0xF + +#define B_EQ_REG_COMM_MB__A 0x1C10002 +#define B_EQ_REG_COMM_MB__W 6 +#define B_EQ_REG_COMM_MB__M 0x3F +#define B_EQ_REG_COMM_MB_CTR__B 0 +#define B_EQ_REG_COMM_MB_CTR__W 1 +#define B_EQ_REG_COMM_MB_CTR__M 0x1 +#define B_EQ_REG_COMM_MB_CTR_OFF 0x0 +#define B_EQ_REG_COMM_MB_CTR_ON 0x1 +#define B_EQ_REG_COMM_MB_OBS__B 1 +#define B_EQ_REG_COMM_MB_OBS__W 1 +#define B_EQ_REG_COMM_MB_OBS__M 0x2 +#define B_EQ_REG_COMM_MB_OBS_OFF 0x0 +#define B_EQ_REG_COMM_MB_OBS_ON 0x2 +#define B_EQ_REG_COMM_MB_CTR_MUX__B 2 +#define B_EQ_REG_COMM_MB_CTR_MUX__W 2 +#define B_EQ_REG_COMM_MB_CTR_MUX__M 0xC +#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 +#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 +#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 +#define B_EQ_REG_COMM_MB_OBS_MUX__B 4 +#define B_EQ_REG_COMM_MB_OBS_MUX__W 2 +#define B_EQ_REG_COMM_MB_OBS_MUX__M 0x30 +#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 +#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 +#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 +#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 + +#define B_EQ_REG_COMM_SERVICE0__A 0x1C10003 +#define B_EQ_REG_COMM_SERVICE0__W 10 +#define B_EQ_REG_COMM_SERVICE0__M 0x3FF + +#define B_EQ_REG_COMM_SERVICE1__A 0x1C10004 +#define B_EQ_REG_COMM_SERVICE1__W 11 +#define B_EQ_REG_COMM_SERVICE1__M 0x7FF + +#define B_EQ_REG_COMM_INT_STA__A 0x1C10007 +#define B_EQ_REG_COMM_INT_STA__W 2 +#define B_EQ_REG_COMM_INT_STA__M 0x3 +#define B_EQ_REG_COMM_INT_STA_TPS_RDY__B 0 +#define B_EQ_REG_COMM_INT_STA_TPS_RDY__W 1 +#define B_EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 +#define B_EQ_REG_COMM_INT_STA_ERR_RDY__B 1 +#define B_EQ_REG_COMM_INT_STA_ERR_RDY__W 1 +#define B_EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 + +#define B_EQ_REG_COMM_INT_MSK__A 0x1C10008 +#define B_EQ_REG_COMM_INT_MSK__W 2 +#define B_EQ_REG_COMM_INT_MSK__M 0x3 +#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 +#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 +#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 +#define B_EQ_REG_COMM_INT_MSK_MER_RDY__B 1 +#define B_EQ_REG_COMM_INT_MSK_MER_RDY__W 1 +#define B_EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 + +#define B_EQ_REG_IS_MODE__A 0x1C10014 +#define B_EQ_REG_IS_MODE__W 4 +#define B_EQ_REG_IS_MODE__M 0xF +#define B_EQ_REG_IS_MODE_INIT 0x0 + +#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 +#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 +#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 +#define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 +#define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 + +#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 +#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 +#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 +#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 +#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 + +#define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 +#define B_EQ_REG_IS_GAIN_MAN__W 10 +#define B_EQ_REG_IS_GAIN_MAN__M 0x3FF +#define B_EQ_REG_IS_GAIN_MAN_INIT 0x114 + +#define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 +#define B_EQ_REG_IS_GAIN_EXP__W 5 +#define B_EQ_REG_IS_GAIN_EXP__M 0x1F +#define B_EQ_REG_IS_GAIN_EXP_INIT 0x5 + +#define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 +#define B_EQ_REG_IS_CLIP_EXP__W 5 +#define B_EQ_REG_IS_CLIP_EXP__M 0x1F +#define B_EQ_REG_IS_CLIP_EXP_INIT 0x10 + +#define B_EQ_REG_DV_MODE__A 0x1C1001E +#define B_EQ_REG_DV_MODE__W 4 +#define B_EQ_REG_DV_MODE__M 0xF +#define B_EQ_REG_DV_MODE_INIT 0xF + +#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 + +#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 +#define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 + +#define B_EQ_REG_DV_MODE_CLP_REA_ENA__B 2 +#define B_EQ_REG_DV_MODE_CLP_REA_ENA__W 1 +#define B_EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 +#define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 +#define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 + +#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 +#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 +#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 +#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 +#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 + +#define B_EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F +#define B_EQ_REG_DV_POS_CLIP_DAT__W 16 +#define B_EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF + +#define B_EQ_REG_SN_MODE__A 0x1C10028 +#define B_EQ_REG_SN_MODE__W 8 +#define B_EQ_REG_SN_MODE__M 0xFF +#define B_EQ_REG_SN_MODE_INIT 0x18 + +#define B_EQ_REG_SN_MODE_MODE_0__B 0 +#define B_EQ_REG_SN_MODE_MODE_0__W 1 +#define B_EQ_REG_SN_MODE_MODE_0__M 0x1 +#define B_EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 + +#define B_EQ_REG_SN_MODE_MODE_1__B 1 +#define B_EQ_REG_SN_MODE_MODE_1__W 1 +#define B_EQ_REG_SN_MODE_MODE_1__M 0x2 +#define B_EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 + +#define B_EQ_REG_SN_MODE_MODE_2__B 2 +#define B_EQ_REG_SN_MODE_MODE_2__W 1 +#define B_EQ_REG_SN_MODE_MODE_2__M 0x4 +#define B_EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 + +#define B_EQ_REG_SN_MODE_MODE_3__B 3 +#define B_EQ_REG_SN_MODE_MODE_3__W 1 +#define B_EQ_REG_SN_MODE_MODE_3__M 0x8 +#define B_EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 + +#define B_EQ_REG_SN_MODE_MODE_4__B 4 +#define B_EQ_REG_SN_MODE_MODE_4__W 1 +#define B_EQ_REG_SN_MODE_MODE_4__M 0x10 +#define B_EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 + +#define B_EQ_REG_SN_MODE_MODE_5__B 5 +#define B_EQ_REG_SN_MODE_MODE_5__W 1 +#define B_EQ_REG_SN_MODE_MODE_5__M 0x20 +#define B_EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 +#define B_EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 + +#define B_EQ_REG_SN_MODE_MODE_6__B 6 +#define B_EQ_REG_SN_MODE_MODE_6__W 1 +#define B_EQ_REG_SN_MODE_MODE_6__M 0x40 +#define B_EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 +#define B_EQ_REG_SN_MODE_MODE_6_STATIC 0x40 + +#define B_EQ_REG_SN_MODE_MODE_7__B 7 +#define B_EQ_REG_SN_MODE_MODE_7__W 1 +#define B_EQ_REG_SN_MODE_MODE_7__M 0x80 +#define B_EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 +#define B_EQ_REG_SN_MODE_MODE_7_STATIC 0x80 + +#define B_EQ_REG_SN_PFIX__A 0x1C10029 +#define B_EQ_REG_SN_PFIX__W 8 +#define B_EQ_REG_SN_PFIX__M 0xFF +#define B_EQ_REG_SN_PFIX_INIT 0x0 + +#define B_EQ_REG_SN_CEGAIN__A 0x1C1002A +#define B_EQ_REG_SN_CEGAIN__W 8 +#define B_EQ_REG_SN_CEGAIN__M 0xFF +#define B_EQ_REG_SN_CEGAIN_INIT 0x30 + +#define B_EQ_REG_SN_OFFSET__A 0x1C1002B +#define B_EQ_REG_SN_OFFSET__W 6 +#define B_EQ_REG_SN_OFFSET__M 0x3F +#define B_EQ_REG_SN_OFFSET_INIT 0x39 + +#define B_EQ_REG_SN_NULLIFY__A 0x1C1002C +#define B_EQ_REG_SN_NULLIFY__W 6 +#define B_EQ_REG_SN_NULLIFY__M 0x3F +#define B_EQ_REG_SN_NULLIFY_INIT 0x0 + +#define B_EQ_REG_SN_SQUASH__A 0x1C1002D +#define B_EQ_REG_SN_SQUASH__W 10 +#define B_EQ_REG_SN_SQUASH__M 0x3FF +#define B_EQ_REG_SN_SQUASH_INIT 0x7 + +#define B_EQ_REG_SN_SQUASH_MAN__B 0 +#define B_EQ_REG_SN_SQUASH_MAN__W 6 +#define B_EQ_REG_SN_SQUASH_MAN__M 0x3F + +#define B_EQ_REG_SN_SQUASH_EXP__B 6 +#define B_EQ_REG_SN_SQUASH_EXP__W 4 +#define B_EQ_REG_SN_SQUASH_EXP__M 0x3C0 + +#define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 +#define B_EQ_REG_RC_SEL_CAR__W 8 +#define B_EQ_REG_RC_SEL_CAR__M 0xFF +#define B_EQ_REG_RC_SEL_CAR_INIT 0x2 +#define B_EQ_REG_RC_SEL_CAR_DIV__B 0 +#define B_EQ_REG_RC_SEL_CAR_DIV__W 1 +#define B_EQ_REG_RC_SEL_CAR_DIV__M 0x1 +#define B_EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 +#define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1 + +#define B_EQ_REG_RC_SEL_CAR_PASS__B 1 +#define B_EQ_REG_RC_SEL_CAR_PASS__W 2 +#define B_EQ_REG_RC_SEL_CAR_PASS__M 0x6 +#define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 +#define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 +#define B_EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 +#define B_EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 + +#define B_EQ_REG_RC_SEL_CAR_LOCAL__B 3 +#define B_EQ_REG_RC_SEL_CAR_LOCAL__W 2 +#define B_EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 +#define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 +#define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 +#define B_EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 +#define B_EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 + +#define B_EQ_REG_RC_SEL_CAR_MEAS__B 5 +#define B_EQ_REG_RC_SEL_CAR_MEAS__W 2 +#define B_EQ_REG_RC_SEL_CAR_MEAS__M 0x60 +#define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 +#define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 +#define B_EQ_REG_RC_SEL_CAR_MEAS_C_DRI 0x40 +#define B_EQ_REG_RC_SEL_CAR_MEAS_D_CC 0x60 + +#define B_EQ_REG_RC_SEL_CAR_FFTMODE__B 7 +#define B_EQ_REG_RC_SEL_CAR_FFTMODE__W 1 +#define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80 +#define B_EQ_REG_RC_SEL_CAR_FFTMODE_2K 0x0 +#define B_EQ_REG_RC_SEL_CAR_FFTMODE_8K 0x80 + +#define B_EQ_REG_RC_STS__A 0x1C10033 +#define B_EQ_REG_RC_STS__W 14 +#define B_EQ_REG_RC_STS__M 0x3FFF + +#define B_EQ_REG_RC_STS_DIFF__B 0 +#define B_EQ_REG_RC_STS_DIFF__W 9 +#define B_EQ_REG_RC_STS_DIFF__M 0x1FF + +#define B_EQ_REG_RC_STS_FIRST__B 9 +#define B_EQ_REG_RC_STS_FIRST__W 1 +#define B_EQ_REG_RC_STS_FIRST__M 0x200 +#define B_EQ_REG_RC_STS_FIRST_A_CE 0x0 +#define B_EQ_REG_RC_STS_FIRST_B_DRI 0x200 + +#define B_EQ_REG_RC_STS_SELEC__B 10 +#define B_EQ_REG_RC_STS_SELEC__W 1 +#define B_EQ_REG_RC_STS_SELEC__M 0x400 +#define B_EQ_REG_RC_STS_SELEC_A_CE 0x0 +#define B_EQ_REG_RC_STS_SELEC_B_DRI 0x400 + +#define B_EQ_REG_RC_STS_OVERFLOW__B 11 +#define B_EQ_REG_RC_STS_OVERFLOW__W 1 +#define B_EQ_REG_RC_STS_OVERFLOW__M 0x800 +#define B_EQ_REG_RC_STS_OVERFLOW_NO 0x0 +#define B_EQ_REG_RC_STS_OVERFLOW_YES 0x800 + +#define B_EQ_REG_RC_STS_LOC_PRS__B 12 +#define B_EQ_REG_RC_STS_LOC_PRS__W 1 +#define B_EQ_REG_RC_STS_LOC_PRS__M 0x1000 +#define B_EQ_REG_RC_STS_LOC_PRS_NO 0x0 +#define B_EQ_REG_RC_STS_LOC_PRS_YES 0x1000 + +#define B_EQ_REG_RC_STS_DRI_PRS__B 13 +#define B_EQ_REG_RC_STS_DRI_PRS__W 1 +#define B_EQ_REG_RC_STS_DRI_PRS__M 0x2000 +#define B_EQ_REG_RC_STS_DRI_PRS_NO 0x0 +#define B_EQ_REG_RC_STS_DRI_PRS_YES 0x2000 + +#define B_EQ_REG_OT_CONST__A 0x1C10046 +#define B_EQ_REG_OT_CONST__W 2 +#define B_EQ_REG_OT_CONST__M 0x3 +#define B_EQ_REG_OT_CONST_INIT 0x2 + +#define B_EQ_REG_OT_ALPHA__A 0x1C10047 +#define B_EQ_REG_OT_ALPHA__W 2 +#define B_EQ_REG_OT_ALPHA__M 0x3 +#define B_EQ_REG_OT_ALPHA_INIT 0x0 + +#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 +#define B_EQ_REG_OT_QNT_THRES0__W 5 +#define B_EQ_REG_OT_QNT_THRES0__M 0x1F +#define B_EQ_REG_OT_QNT_THRES0_INIT 0x1E + +#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 +#define B_EQ_REG_OT_QNT_THRES1__W 5 +#define B_EQ_REG_OT_QNT_THRES1__M 0x1F +#define B_EQ_REG_OT_QNT_THRES1_INIT 0x1F + +#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A +#define B_EQ_REG_OT_CSI_STEP__W 4 +#define B_EQ_REG_OT_CSI_STEP__M 0xF +#define B_EQ_REG_OT_CSI_STEP_INIT 0x5 + +#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B +#define B_EQ_REG_OT_CSI_OFFSET__W 7 +#define B_EQ_REG_OT_CSI_OFFSET__M 0x7F +#define B_EQ_REG_OT_CSI_OFFSET_INIT 0x5 + +#define B_EQ_REG_OT_CSI_GAIN__A 0x1C1004C +#define B_EQ_REG_OT_CSI_GAIN__W 8 +#define B_EQ_REG_OT_CSI_GAIN__M 0xFF +#define B_EQ_REG_OT_CSI_GAIN_INIT 0x2B + +#define B_EQ_REG_OT_CSI_MEAN__A 0x1C1004D +#define B_EQ_REG_OT_CSI_MEAN__W 7 +#define B_EQ_REG_OT_CSI_MEAN__M 0x7F + +#define B_EQ_REG_OT_CSI_VARIANCE__A 0x1C1004E +#define B_EQ_REG_OT_CSI_VARIANCE__W 7 +#define B_EQ_REG_OT_CSI_VARIANCE__M 0x7F + +#define B_EQ_REG_TD_TPS_INIT__A 0x1C10050 +#define B_EQ_REG_TD_TPS_INIT__W 1 +#define B_EQ_REG_TD_TPS_INIT__M 0x1 +#define B_EQ_REG_TD_TPS_INIT_INIT 0x0 +#define B_EQ_REG_TD_TPS_INIT_POS 0x0 +#define B_EQ_REG_TD_TPS_INIT_NEG 0x1 + +#define B_EQ_REG_TD_TPS_SYNC__A 0x1C10051 +#define B_EQ_REG_TD_TPS_SYNC__W 16 +#define B_EQ_REG_TD_TPS_SYNC__M 0xFFFF +#define B_EQ_REG_TD_TPS_SYNC_INIT 0x0 +#define B_EQ_REG_TD_TPS_SYNC_ODD 0x35EE +#define B_EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 + +#define B_EQ_REG_TD_TPS_LEN__A 0x1C10052 +#define B_EQ_REG_TD_TPS_LEN__W 6 +#define B_EQ_REG_TD_TPS_LEN__M 0x3F +#define B_EQ_REG_TD_TPS_LEN_INIT 0x0 +#define B_EQ_REG_TD_TPS_LEN_DEF 0x17 +#define B_EQ_REG_TD_TPS_LEN_ID_SUP 0x1F + +#define B_EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 +#define B_EQ_REG_TD_TPS_FRM_NMB__W 2 +#define B_EQ_REG_TD_TPS_FRM_NMB__M 0x3 +#define B_EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 +#define B_EQ_REG_TD_TPS_FRM_NMB_1 0x0 +#define B_EQ_REG_TD_TPS_FRM_NMB_2 0x1 +#define B_EQ_REG_TD_TPS_FRM_NMB_3 0x2 +#define B_EQ_REG_TD_TPS_FRM_NMB_4 0x3 + +#define B_EQ_REG_TD_TPS_CONST__A 0x1C10054 +#define B_EQ_REG_TD_TPS_CONST__W 2 +#define B_EQ_REG_TD_TPS_CONST__M 0x3 +#define B_EQ_REG_TD_TPS_CONST_INIT 0x0 +#define B_EQ_REG_TD_TPS_CONST_QPSK 0x0 +#define B_EQ_REG_TD_TPS_CONST_16QAM 0x1 +#define B_EQ_REG_TD_TPS_CONST_64QAM 0x2 + +#define B_EQ_REG_TD_TPS_HINFO__A 0x1C10055 +#define B_EQ_REG_TD_TPS_HINFO__W 3 +#define B_EQ_REG_TD_TPS_HINFO__M 0x7 +#define B_EQ_REG_TD_TPS_HINFO_INIT 0x0 +#define B_EQ_REG_TD_TPS_HINFO_NH 0x0 +#define B_EQ_REG_TD_TPS_HINFO_H1 0x1 +#define B_EQ_REG_TD_TPS_HINFO_H2 0x2 +#define B_EQ_REG_TD_TPS_HINFO_H4 0x3 + +#define B_EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 +#define B_EQ_REG_TD_TPS_CODE_HP__W 3 +#define B_EQ_REG_TD_TPS_CODE_HP__M 0x7 +#define B_EQ_REG_TD_TPS_CODE_HP_INIT 0x0 +#define B_EQ_REG_TD_TPS_CODE_HP_1_2 0x0 +#define B_EQ_REG_TD_TPS_CODE_HP_2_3 0x1 +#define B_EQ_REG_TD_TPS_CODE_HP_3_4 0x2 +#define B_EQ_REG_TD_TPS_CODE_HP_5_6 0x3 +#define B_EQ_REG_TD_TPS_CODE_HP_7_8 0x4 + +#define B_EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 +#define B_EQ_REG_TD_TPS_CODE_LP__W 3 +#define B_EQ_REG_TD_TPS_CODE_LP__M 0x7 +#define B_EQ_REG_TD_TPS_CODE_LP_INIT 0x0 +#define B_EQ_REG_TD_TPS_CODE_LP_1_2 0x0 +#define B_EQ_REG_TD_TPS_CODE_LP_2_3 0x1 +#define B_EQ_REG_TD_TPS_CODE_LP_3_4 0x2 +#define B_EQ_REG_TD_TPS_CODE_LP_5_6 0x3 +#define B_EQ_REG_TD_TPS_CODE_LP_7_8 0x4 + +#define B_EQ_REG_TD_TPS_GUARD__A 0x1C10058 +#define B_EQ_REG_TD_TPS_GUARD__W 2 +#define B_EQ_REG_TD_TPS_GUARD__M 0x3 +#define B_EQ_REG_TD_TPS_GUARD_INIT 0x0 +#define B_EQ_REG_TD_TPS_GUARD_32 0x0 +#define B_EQ_REG_TD_TPS_GUARD_16 0x1 +#define B_EQ_REG_TD_TPS_GUARD_08 0x2 +#define B_EQ_REG_TD_TPS_GUARD_04 0x3 + +#define B_EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 +#define B_EQ_REG_TD_TPS_TR_MODE__W 2 +#define B_EQ_REG_TD_TPS_TR_MODE__M 0x3 +#define B_EQ_REG_TD_TPS_TR_MODE_INIT 0x0 +#define B_EQ_REG_TD_TPS_TR_MODE_2K 0x0 +#define B_EQ_REG_TD_TPS_TR_MODE_8K 0x1 + +#define B_EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A +#define B_EQ_REG_TD_TPS_CELL_ID_HI__W 8 +#define B_EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF +#define B_EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 + +#define B_EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B +#define B_EQ_REG_TD_TPS_CELL_ID_LO__W 8 +#define B_EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF +#define B_EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 + +#define B_EQ_REG_TD_TPS_RSV__A 0x1C1005C +#define B_EQ_REG_TD_TPS_RSV__W 6 +#define B_EQ_REG_TD_TPS_RSV__M 0x3F +#define B_EQ_REG_TD_TPS_RSV_INIT 0x0 + +#define B_EQ_REG_TD_TPS_BCH__A 0x1C1005D +#define B_EQ_REG_TD_TPS_BCH__W 14 +#define B_EQ_REG_TD_TPS_BCH__M 0x3FFF +#define B_EQ_REG_TD_TPS_BCH_INIT 0x0 + +#define B_EQ_REG_TD_SQR_ERR_I__A 0x1C1005E +#define B_EQ_REG_TD_SQR_ERR_I__W 16 +#define B_EQ_REG_TD_SQR_ERR_I__M 0xFFFF +#define B_EQ_REG_TD_SQR_ERR_I_INIT 0x0 + +#define B_EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F +#define B_EQ_REG_TD_SQR_ERR_Q__W 16 +#define B_EQ_REG_TD_SQR_ERR_Q__M 0xFFFF +#define B_EQ_REG_TD_SQR_ERR_Q_INIT 0x0 + +#define B_EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 +#define B_EQ_REG_TD_SQR_ERR_EXP__W 4 +#define B_EQ_REG_TD_SQR_ERR_EXP__M 0xF +#define B_EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 + +#define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 +#define B_EQ_REG_TD_REQ_SMB_CNT__W 16 +#define B_EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF +#define B_EQ_REG_TD_REQ_SMB_CNT_INIT 0x200 + +#define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 +#define B_EQ_REG_TD_TPS_PWR_OFS__W 16 +#define B_EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF +#define B_EQ_REG_TD_TPS_PWR_OFS_INIT 0x19F + +#define B_EC_COMM_EXEC__A 0x2000000 +#define B_EC_COMM_EXEC__W 3 +#define B_EC_COMM_EXEC__M 0x7 +#define B_EC_COMM_EXEC_CTL__B 0 +#define B_EC_COMM_EXEC_CTL__W 3 +#define B_EC_COMM_EXEC_CTL__M 0x7 +#define B_EC_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_COMM_EXEC_CTL_HOLD 0x2 +#define B_EC_COMM_EXEC_CTL_STEP 0x3 +#define B_EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_EC_COMM_STATE__A 0x2000001 +#define B_EC_COMM_STATE__W 16 +#define B_EC_COMM_STATE__M 0xFFFF +#define B_EC_COMM_MB__A 0x2000002 +#define B_EC_COMM_MB__W 16 +#define B_EC_COMM_MB__M 0xFFFF +#define B_EC_COMM_SERVICE0__A 0x2000003 +#define B_EC_COMM_SERVICE0__W 16 +#define B_EC_COMM_SERVICE0__M 0xFFFF +#define B_EC_COMM_SERVICE1__A 0x2000004 +#define B_EC_COMM_SERVICE1__W 16 +#define B_EC_COMM_SERVICE1__M 0xFFFF +#define B_EC_COMM_INT_STA__A 0x2000007 +#define B_EC_COMM_INT_STA__W 16 +#define B_EC_COMM_INT_STA__M 0xFFFF +#define B_EC_COMM_INT_MSK__A 0x2000008 +#define B_EC_COMM_INT_MSK__W 16 +#define B_EC_COMM_INT_MSK__M 0xFFFF + +#define B_EC_SB_SID 0x16 + +#define B_EC_SB_REG_COMM_EXEC__A 0x2010000 +#define B_EC_SB_REG_COMM_EXEC__W 3 +#define B_EC_SB_REG_COMM_EXEC__M 0x7 +#define B_EC_SB_REG_COMM_EXEC_CTL__B 0 +#define B_EC_SB_REG_COMM_EXEC_CTL__W 3 +#define B_EC_SB_REG_COMM_EXEC_CTL__M 0x7 +#define B_EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define B_EC_SB_REG_COMM_STATE__A 0x2010001 +#define B_EC_SB_REG_COMM_STATE__W 4 +#define B_EC_SB_REG_COMM_STATE__M 0xF +#define B_EC_SB_REG_COMM_MB__A 0x2010002 +#define B_EC_SB_REG_COMM_MB__W 2 +#define B_EC_SB_REG_COMM_MB__M 0x3 +#define B_EC_SB_REG_COMM_MB_CTR__B 0 +#define B_EC_SB_REG_COMM_MB_CTR__W 1 +#define B_EC_SB_REG_COMM_MB_CTR__M 0x1 +#define B_EC_SB_REG_COMM_MB_CTR_OFF 0x0 +#define B_EC_SB_REG_COMM_MB_CTR_ON 0x1 +#define B_EC_SB_REG_COMM_MB_OBS__B 1 +#define B_EC_SB_REG_COMM_MB_OBS__W 1 +#define B_EC_SB_REG_COMM_MB_OBS__M 0x2 +#define B_EC_SB_REG_COMM_MB_OBS_OFF 0x0 +#define B_EC_SB_REG_COMM_MB_OBS_ON 0x2 + +#define B_EC_SB_REG_TR_MODE__A 0x2010010 +#define B_EC_SB_REG_TR_MODE__W 1 +#define B_EC_SB_REG_TR_MODE__M 0x1 +#define B_EC_SB_REG_TR_MODE_INIT 0x0 +#define B_EC_SB_REG_TR_MODE_8K 0x0 +#define B_EC_SB_REG_TR_MODE_2K 0x1 + +#define B_EC_SB_REG_CONST__A 0x2010011 +#define B_EC_SB_REG_CONST__W 2 +#define B_EC_SB_REG_CONST__M 0x3 +#define B_EC_SB_REG_CONST_INIT 0x2 +#define B_EC_SB_REG_CONST_QPSK 0x0 +#define B_EC_SB_REG_CONST_16QAM 0x1 +#define B_EC_SB_REG_CONST_64QAM 0x2 + +#define B_EC_SB_REG_ALPHA__A 0x2010012 +#define B_EC_SB_REG_ALPHA__W 3 +#define B_EC_SB_REG_ALPHA__M 0x7 + +#define B_EC_SB_REG_ALPHA_INIT 0x0 + +#define B_EC_SB_REG_ALPHA_NH 0x0 + +#define B_EC_SB_REG_ALPHA_H1 0x1 + +#define B_EC_SB_REG_ALPHA_H2 0x2 + +#define B_EC_SB_REG_ALPHA_H4 0x3 + +#define B_EC_SB_REG_PRIOR__A 0x2010013 +#define B_EC_SB_REG_PRIOR__W 1 +#define B_EC_SB_REG_PRIOR__M 0x1 +#define B_EC_SB_REG_PRIOR_INIT 0x0 +#define B_EC_SB_REG_PRIOR_HI 0x0 +#define B_EC_SB_REG_PRIOR_LO 0x1 + +#define B_EC_SB_REG_CSI_HI__A 0x2010014 +#define B_EC_SB_REG_CSI_HI__W 5 +#define B_EC_SB_REG_CSI_HI__M 0x1F +#define B_EC_SB_REG_CSI_HI_INIT 0x1F +#define B_EC_SB_REG_CSI_HI_MAX 0x1F +#define B_EC_SB_REG_CSI_HI_MIN 0x0 +#define B_EC_SB_REG_CSI_HI_TAG 0x0 + +#define B_EC_SB_REG_CSI_LO__A 0x2010015 +#define B_EC_SB_REG_CSI_LO__W 5 +#define B_EC_SB_REG_CSI_LO__M 0x1F +#define B_EC_SB_REG_CSI_LO_INIT 0x1E +#define B_EC_SB_REG_CSI_LO_MAX 0x1F +#define B_EC_SB_REG_CSI_LO_MIN 0x0 +#define B_EC_SB_REG_CSI_LO_TAG 0x0 + +#define B_EC_SB_REG_SMB_TGL__A 0x2010016 +#define B_EC_SB_REG_SMB_TGL__W 1 +#define B_EC_SB_REG_SMB_TGL__M 0x1 +#define B_EC_SB_REG_SMB_TGL_OFF 0x0 +#define B_EC_SB_REG_SMB_TGL_ON 0x1 +#define B_EC_SB_REG_SMB_TGL_INIT 0x1 + +#define B_EC_SB_REG_SNR_HI__A 0x2010017 +#define B_EC_SB_REG_SNR_HI__W 8 +#define B_EC_SB_REG_SNR_HI__M 0xFF +#define B_EC_SB_REG_SNR_HI_INIT 0x6E +#define B_EC_SB_REG_SNR_HI_MAX 0xFF +#define B_EC_SB_REG_SNR_HI_MIN 0x0 +#define B_EC_SB_REG_SNR_HI_TAG 0x0 + +#define B_EC_SB_REG_SNR_MID__A 0x2010018 +#define B_EC_SB_REG_SNR_MID__W 8 +#define B_EC_SB_REG_SNR_MID__M 0xFF +#define B_EC_SB_REG_SNR_MID_INIT 0x6C +#define B_EC_SB_REG_SNR_MID_MAX 0xFF +#define B_EC_SB_REG_SNR_MID_MIN 0x0 +#define B_EC_SB_REG_SNR_MID_TAG 0x0 + +#define B_EC_SB_REG_SNR_LO__A 0x2010019 +#define B_EC_SB_REG_SNR_LO__W 8 +#define B_EC_SB_REG_SNR_LO__M 0xFF +#define B_EC_SB_REG_SNR_LO_INIT 0x68 +#define B_EC_SB_REG_SNR_LO_MAX 0xFF +#define B_EC_SB_REG_SNR_LO_MIN 0x0 +#define B_EC_SB_REG_SNR_LO_TAG 0x0 + +#define B_EC_SB_REG_SCALE_MSB__A 0x201001A +#define B_EC_SB_REG_SCALE_MSB__W 6 +#define B_EC_SB_REG_SCALE_MSB__M 0x3F +#define B_EC_SB_REG_SCALE_MSB_INIT 0x30 +#define B_EC_SB_REG_SCALE_MSB_MAX 0x3F + +#define B_EC_SB_REG_SCALE_BIT2__A 0x201001B +#define B_EC_SB_REG_SCALE_BIT2__W 6 +#define B_EC_SB_REG_SCALE_BIT2__M 0x3F +#define B_EC_SB_REG_SCALE_BIT2_INIT 0xC +#define B_EC_SB_REG_SCALE_BIT2_MAX 0x3F + +#define B_EC_SB_REG_SCALE_LSB__A 0x201001C +#define B_EC_SB_REG_SCALE_LSB__W 6 +#define B_EC_SB_REG_SCALE_LSB__M 0x3F +#define B_EC_SB_REG_SCALE_LSB_INIT 0x3 +#define B_EC_SB_REG_SCALE_LSB_MAX 0x3F + +#define B_EC_SB_REG_CSI_OFS0__A 0x201001D +#define B_EC_SB_REG_CSI_OFS0__W 4 +#define B_EC_SB_REG_CSI_OFS0__M 0xF +#define B_EC_SB_REG_CSI_OFS0_INIT 0x4 + +#define B_EC_SB_REG_CSI_OFS1__A 0x201001E +#define B_EC_SB_REG_CSI_OFS1__W 4 +#define B_EC_SB_REG_CSI_OFS1__M 0xF +#define B_EC_SB_REG_CSI_OFS1_INIT 0x1 + +#define B_EC_SB_REG_CSI_OFS2__A 0x201001F +#define B_EC_SB_REG_CSI_OFS2__W 4 +#define B_EC_SB_REG_CSI_OFS2__M 0xF +#define B_EC_SB_REG_CSI_OFS2_INIT 0x2 + +#define B_EC_SB_REG_MAX0__A 0x2010020 +#define B_EC_SB_REG_MAX0__W 6 +#define B_EC_SB_REG_MAX0__M 0x3F +#define B_EC_SB_REG_MAX0_INIT 0x3F + +#define B_EC_SB_REG_MAX1__A 0x2010021 +#define B_EC_SB_REG_MAX1__W 6 +#define B_EC_SB_REG_MAX1__M 0x3F +#define B_EC_SB_REG_MAX1_INIT 0x3F + +#define B_EC_SB_REG_MAX2__A 0x2010022 +#define B_EC_SB_REG_MAX2__W 6 +#define B_EC_SB_REG_MAX2__M 0x3F +#define B_EC_SB_REG_MAX2_INIT 0x3F + +#define B_EC_SB_REG_CSI_DIS__A 0x2010023 +#define B_EC_SB_REG_CSI_DIS__W 1 +#define B_EC_SB_REG_CSI_DIS__M 0x1 +#define B_EC_SB_REG_CSI_DIS_INIT 0x0 + +#define B_EC_SB_SD_RAM__A 0x2020000 + +#define B_EC_SB_BD0_RAM__A 0x2030000 + +#define B_EC_SB_BD1_RAM__A 0x2040000 + +#define B_EC_VD_SID 0x17 + +#define B_EC_VD_REG_COMM_EXEC__A 0x2090000 +#define B_EC_VD_REG_COMM_EXEC__W 3 +#define B_EC_VD_REG_COMM_EXEC__M 0x7 +#define B_EC_VD_REG_COMM_EXEC_CTL__B 0 +#define B_EC_VD_REG_COMM_EXEC_CTL__W 3 +#define B_EC_VD_REG_COMM_EXEC_CTL__M 0x7 +#define B_EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define B_EC_VD_REG_COMM_STATE__A 0x2090001 +#define B_EC_VD_REG_COMM_STATE__W 4 +#define B_EC_VD_REG_COMM_STATE__M 0xF +#define B_EC_VD_REG_COMM_MB__A 0x2090002 +#define B_EC_VD_REG_COMM_MB__W 2 +#define B_EC_VD_REG_COMM_MB__M 0x3 +#define B_EC_VD_REG_COMM_MB_CTR__B 0 +#define B_EC_VD_REG_COMM_MB_CTR__W 1 +#define B_EC_VD_REG_COMM_MB_CTR__M 0x1 +#define B_EC_VD_REG_COMM_MB_CTR_OFF 0x0 +#define B_EC_VD_REG_COMM_MB_CTR_ON 0x1 +#define B_EC_VD_REG_COMM_MB_OBS__B 1 +#define B_EC_VD_REG_COMM_MB_OBS__W 1 +#define B_EC_VD_REG_COMM_MB_OBS__M 0x2 +#define B_EC_VD_REG_COMM_MB_OBS_OFF 0x0 +#define B_EC_VD_REG_COMM_MB_OBS_ON 0x2 + +#define B_EC_VD_REG_COMM_SERVICE0__A 0x2090003 +#define B_EC_VD_REG_COMM_SERVICE0__W 16 +#define B_EC_VD_REG_COMM_SERVICE0__M 0xFFFF +#define B_EC_VD_REG_COMM_SERVICE1__A 0x2090004 +#define B_EC_VD_REG_COMM_SERVICE1__W 16 +#define B_EC_VD_REG_COMM_SERVICE1__M 0xFFFF +#define B_EC_VD_REG_COMM_INT_STA__A 0x2090007 +#define B_EC_VD_REG_COMM_INT_STA__W 1 +#define B_EC_VD_REG_COMM_INT_STA__M 0x1 +#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 +#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 +#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 + +#define B_EC_VD_REG_COMM_INT_MSK__A 0x2090008 +#define B_EC_VD_REG_COMM_INT_MSK__W 1 +#define B_EC_VD_REG_COMM_INT_MSK__M 0x1 +#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 +#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 +#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 + +#define B_EC_VD_REG_FORCE__A 0x2090010 +#define B_EC_VD_REG_FORCE__W 2 +#define B_EC_VD_REG_FORCE__M 0x3 +#define B_EC_VD_REG_FORCE_INIT 0x2 +#define B_EC_VD_REG_FORCE_FREE 0x0 +#define B_EC_VD_REG_FORCE_PROP 0x1 +#define B_EC_VD_REG_FORCE_FORCED 0x2 +#define B_EC_VD_REG_FORCE_FIXED 0x3 + +#define B_EC_VD_REG_SET_CODERATE__A 0x2090011 +#define B_EC_VD_REG_SET_CODERATE__W 3 +#define B_EC_VD_REG_SET_CODERATE__M 0x7 +#define B_EC_VD_REG_SET_CODERATE_INIT 0x1 +#define B_EC_VD_REG_SET_CODERATE_C1_2 0x0 +#define B_EC_VD_REG_SET_CODERATE_C2_3 0x1 +#define B_EC_VD_REG_SET_CODERATE_C3_4 0x2 +#define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 +#define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 + +#define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 +#define B_EC_VD_REG_REQ_SMB_CNT__W 16 +#define B_EC_VD_REG_REQ_SMB_CNT__M 0xFFFF +#define B_EC_VD_REG_REQ_SMB_CNT_INIT 0x1 + +#define B_EC_VD_REG_REQ_BIT_CNT__A 0x2090013 +#define B_EC_VD_REG_REQ_BIT_CNT__W 16 +#define B_EC_VD_REG_REQ_BIT_CNT__M 0xFFFF +#define B_EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF + +#define B_EC_VD_REG_RLK_ENA__A 0x2090014 +#define B_EC_VD_REG_RLK_ENA__W 1 +#define B_EC_VD_REG_RLK_ENA__M 0x1 +#define B_EC_VD_REG_RLK_ENA_INIT 0x1 +#define B_EC_VD_REG_RLK_ENA_OFF 0x0 +#define B_EC_VD_REG_RLK_ENA_ON 0x1 + +#define B_EC_VD_REG_VAL__A 0x2090015 +#define B_EC_VD_REG_VAL__W 2 +#define B_EC_VD_REG_VAL__M 0x3 +#define B_EC_VD_REG_VAL_INIT 0x0 +#define B_EC_VD_REG_VAL_CODE 0x1 +#define B_EC_VD_REG_VAL_CNT 0x2 + +#define B_EC_VD_REG_GET_CODERATE__A 0x2090016 +#define B_EC_VD_REG_GET_CODERATE__W 3 +#define B_EC_VD_REG_GET_CODERATE__M 0x7 +#define B_EC_VD_REG_GET_CODERATE_INIT 0x0 +#define B_EC_VD_REG_GET_CODERATE_C1_2 0x0 +#define B_EC_VD_REG_GET_CODERATE_C2_3 0x1 +#define B_EC_VD_REG_GET_CODERATE_C3_4 0x2 +#define B_EC_VD_REG_GET_CODERATE_C5_6 0x3 +#define B_EC_VD_REG_GET_CODERATE_C7_8 0x4 + +#define B_EC_VD_REG_ERR_BIT_CNT__A 0x2090017 +#define B_EC_VD_REG_ERR_BIT_CNT__W 16 +#define B_EC_VD_REG_ERR_BIT_CNT__M 0xFFFF +#define B_EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF + +#define B_EC_VD_REG_IN_BIT_CNT__A 0x2090018 +#define B_EC_VD_REG_IN_BIT_CNT__W 16 +#define B_EC_VD_REG_IN_BIT_CNT__M 0xFFFF +#define B_EC_VD_REG_IN_BIT_CNT_INIT 0x0 + +#define B_EC_VD_REG_STS__A 0x2090019 +#define B_EC_VD_REG_STS__W 1 +#define B_EC_VD_REG_STS__M 0x1 +#define B_EC_VD_REG_STS_INIT 0x0 +#define B_EC_VD_REG_STS_NO_LOCK 0x0 +#define B_EC_VD_REG_STS_IN_LOCK 0x1 + +#define B_EC_VD_REG_RLK_CNT__A 0x209001A +#define B_EC_VD_REG_RLK_CNT__W 16 +#define B_EC_VD_REG_RLK_CNT__M 0xFFFF +#define B_EC_VD_REG_RLK_CNT_INIT 0x0 + +#define B_EC_VD_TB0_RAM__A 0x20A0000 + +#define B_EC_VD_TB1_RAM__A 0x20B0000 + +#define B_EC_VD_TB2_RAM__A 0x20C0000 + +#define B_EC_VD_TB3_RAM__A 0x20D0000 + +#define B_EC_VD_RE_RAM__A 0x2100000 + +#define B_EC_OD_SID 0x18 + +#define B_EC_OD_REG_COMM_EXEC__A 0x2110000 +#define B_EC_OD_REG_COMM_EXEC__W 3 +#define B_EC_OD_REG_COMM_EXEC__M 0x7 +#define B_EC_OD_REG_COMM_EXEC_CTL__B 0 +#define B_EC_OD_REG_COMM_EXEC_CTL__W 3 +#define B_EC_OD_REG_COMM_EXEC_CTL__M 0x7 +#define B_EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_EC_OD_REG_COMM_STATE__A 0x2110001 +#define B_EC_OD_REG_COMM_STATE__W 1 +#define B_EC_OD_REG_COMM_STATE__M 0x1 +#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__B 0 +#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__W 1 +#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__M 0x1 + +#define B_EC_OD_REG_COMM_MB__A 0x2110002 +#define B_EC_OD_REG_COMM_MB__W 3 +#define B_EC_OD_REG_COMM_MB__M 0x7 +#define B_EC_OD_REG_COMM_MB_CTR__B 0 +#define B_EC_OD_REG_COMM_MB_CTR__W 1 +#define B_EC_OD_REG_COMM_MB_CTR__M 0x1 +#define B_EC_OD_REG_COMM_MB_CTR_OFF 0x0 +#define B_EC_OD_REG_COMM_MB_CTR_ON 0x1 +#define B_EC_OD_REG_COMM_MB_OBS__B 1 +#define B_EC_OD_REG_COMM_MB_OBS__W 1 +#define B_EC_OD_REG_COMM_MB_OBS__M 0x2 +#define B_EC_OD_REG_COMM_MB_OBS_OFF 0x0 +#define B_EC_OD_REG_COMM_MB_OBS_ON 0x2 + +#define B_EC_OD_REG_COMM_SERVICE0__A 0x2110003 +#define B_EC_OD_REG_COMM_SERVICE0__W 10 +#define B_EC_OD_REG_COMM_SERVICE0__M 0x3FF +#define B_EC_OD_REG_COMM_SERVICE1__A 0x2110004 +#define B_EC_OD_REG_COMM_SERVICE1__W 11 +#define B_EC_OD_REG_COMM_SERVICE1__M 0x7FF + +#define B_EC_OD_REG_COMM_ACTIVATE__A 0x2110005 +#define B_EC_OD_REG_COMM_ACTIVATE__W 2 +#define B_EC_OD_REG_COMM_ACTIVATE__M 0x3 + +#define B_EC_OD_REG_COMM_COUNT__A 0x2110006 +#define B_EC_OD_REG_COMM_COUNT__W 16 +#define B_EC_OD_REG_COMM_COUNT__M 0xFFFF + +#define B_EC_OD_REG_COMM_INT_STA__A 0x2110007 +#define B_EC_OD_REG_COMM_INT_STA__W 2 +#define B_EC_OD_REG_COMM_INT_STA__M 0x3 +#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 +#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 +#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 +#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 +#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 +#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 + +#define B_EC_OD_REG_COMM_INT_MSK__A 0x2110008 +#define B_EC_OD_REG_COMM_INT_MSK__W 2 +#define B_EC_OD_REG_COMM_INT_MSK__M 0x3 +#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 +#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 +#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 +#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 +#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 +#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 + +#define B_EC_OD_REG_SYNC__A 0x2110664 +#define B_EC_OD_REG_SYNC__W 12 +#define B_EC_OD_REG_SYNC__M 0xFFF +#define B_EC_OD_REG_SYNC_NR_SYNC__B 0 +#define B_EC_OD_REG_SYNC_NR_SYNC__W 5 +#define B_EC_OD_REG_SYNC_NR_SYNC__M 0x1F +#define B_EC_OD_REG_SYNC_IN_SYNC__B 5 +#define B_EC_OD_REG_SYNC_IN_SYNC__W 4 +#define B_EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 +#define B_EC_OD_REG_SYNC_OUT_SYNC__B 9 +#define B_EC_OD_REG_SYNC_OUT_SYNC__W 3 +#define B_EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 + +#define B_EC_OD_REG_NOSYNC__A 0x2110004 +#define B_EC_OD_REG_NOSYNC__W 8 +#define B_EC_OD_REG_NOSYNC__M 0xFF + +#define B_EC_OD_DEINT_RAM__A 0x2120000 + +#define B_EC_RS_SID 0x19 + +#define B_EC_RS_REG_COMM_EXEC__A 0x2130000 +#define B_EC_RS_REG_COMM_EXEC__W 3 +#define B_EC_RS_REG_COMM_EXEC__M 0x7 +#define B_EC_RS_REG_COMM_EXEC_CTL__B 0 +#define B_EC_RS_REG_COMM_EXEC_CTL__W 3 +#define B_EC_RS_REG_COMM_EXEC_CTL__M 0x7 +#define B_EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 + +#define B_EC_RS_REG_COMM_STATE__A 0x2130001 +#define B_EC_RS_REG_COMM_STATE__W 4 +#define B_EC_RS_REG_COMM_STATE__M 0xF +#define B_EC_RS_REG_COMM_MB__A 0x2130002 +#define B_EC_RS_REG_COMM_MB__W 2 +#define B_EC_RS_REG_COMM_MB__M 0x3 +#define B_EC_RS_REG_COMM_MB_CTR__B 0 +#define B_EC_RS_REG_COMM_MB_CTR__W 1 +#define B_EC_RS_REG_COMM_MB_CTR__M 0x1 +#define B_EC_RS_REG_COMM_MB_CTR_OFF 0x0 +#define B_EC_RS_REG_COMM_MB_CTR_ON 0x1 +#define B_EC_RS_REG_COMM_MB_OBS__B 1 +#define B_EC_RS_REG_COMM_MB_OBS__W 1 +#define B_EC_RS_REG_COMM_MB_OBS__M 0x2 +#define B_EC_RS_REG_COMM_MB_OBS_OFF 0x0 +#define B_EC_RS_REG_COMM_MB_OBS_ON 0x2 + +#define B_EC_RS_REG_COMM_SERVICE0__A 0x2130003 +#define B_EC_RS_REG_COMM_SERVICE0__W 16 +#define B_EC_RS_REG_COMM_SERVICE0__M 0xFFFF +#define B_EC_RS_REG_COMM_SERVICE1__A 0x2130004 +#define B_EC_RS_REG_COMM_SERVICE1__W 16 +#define B_EC_RS_REG_COMM_SERVICE1__M 0xFFFF +#define B_EC_RS_REG_COMM_INT_STA__A 0x2130007 +#define B_EC_RS_REG_COMM_INT_STA__W 1 +#define B_EC_RS_REG_COMM_INT_STA__M 0x1 +#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 +#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 +#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 + +#define B_EC_RS_REG_COMM_INT_MSK__A 0x2130008 +#define B_EC_RS_REG_COMM_INT_MSK__W 1 +#define B_EC_RS_REG_COMM_INT_MSK__M 0x1 +#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 +#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 +#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 + +#define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 +#define B_EC_RS_REG_REQ_PCK_CNT__W 16 +#define B_EC_RS_REG_REQ_PCK_CNT__M 0xFFFF +#define B_EC_RS_REG_REQ_PCK_CNT_INIT 0x200 + +#define B_EC_RS_REG_VAL__A 0x2130011 +#define B_EC_RS_REG_VAL__W 1 +#define B_EC_RS_REG_VAL__M 0x1 +#define B_EC_RS_REG_VAL_INIT 0x0 +#define B_EC_RS_REG_VAL_PCK 0x1 + +#define B_EC_RS_REG_ERR_PCK_CNT__A 0x2130012 +#define B_EC_RS_REG_ERR_PCK_CNT__W 16 +#define B_EC_RS_REG_ERR_PCK_CNT__M 0xFFFF +#define B_EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF + +#define B_EC_RS_REG_ERR_SMB_CNT__A 0x2130013 +#define B_EC_RS_REG_ERR_SMB_CNT__W 16 +#define B_EC_RS_REG_ERR_SMB_CNT__M 0xFFFF +#define B_EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF + +#define B_EC_RS_REG_ERR_BIT_CNT__A 0x2130014 +#define B_EC_RS_REG_ERR_BIT_CNT__W 16 +#define B_EC_RS_REG_ERR_BIT_CNT__M 0xFFFF +#define B_EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF + +#define B_EC_RS_REG_IN_PCK_CNT__A 0x2130015 +#define B_EC_RS_REG_IN_PCK_CNT__W 16 +#define B_EC_RS_REG_IN_PCK_CNT__M 0xFFFF +#define B_EC_RS_REG_IN_PCK_CNT_INIT 0x0 + +#define B_EC_RS_EC_RAM__A 0x2140000 + +#define B_EC_OC_SID 0x1A + +#define B_EC_OC_REG_COMM_EXEC__A 0x2150000 +#define B_EC_OC_REG_COMM_EXEC__W 3 +#define B_EC_OC_REG_COMM_EXEC__M 0x7 +#define B_EC_OC_REG_COMM_EXEC_CTL__B 0 +#define B_EC_OC_REG_COMM_EXEC_CTL__W 3 +#define B_EC_OC_REG_COMM_EXEC_CTL__M 0x7 +#define B_EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_EC_OC_REG_COMM_STATE__A 0x2150001 +#define B_EC_OC_REG_COMM_STATE__W 4 +#define B_EC_OC_REG_COMM_STATE__M 0xF + +#define B_EC_OC_REG_COMM_MB__A 0x2150002 +#define B_EC_OC_REG_COMM_MB__W 2 +#define B_EC_OC_REG_COMM_MB__M 0x3 +#define B_EC_OC_REG_COMM_MB_CTR__B 0 +#define B_EC_OC_REG_COMM_MB_CTR__W 1 +#define B_EC_OC_REG_COMM_MB_CTR__M 0x1 +#define B_EC_OC_REG_COMM_MB_CTR_OFF 0x0 +#define B_EC_OC_REG_COMM_MB_CTR_ON 0x1 +#define B_EC_OC_REG_COMM_MB_OBS__B 1 +#define B_EC_OC_REG_COMM_MB_OBS__W 1 +#define B_EC_OC_REG_COMM_MB_OBS__M 0x2 +#define B_EC_OC_REG_COMM_MB_OBS_OFF 0x0 +#define B_EC_OC_REG_COMM_MB_OBS_ON 0x2 + +#define B_EC_OC_REG_COMM_SERVICE0__A 0x2150003 +#define B_EC_OC_REG_COMM_SERVICE0__W 10 +#define B_EC_OC_REG_COMM_SERVICE0__M 0x3FF + +#define B_EC_OC_REG_COMM_SERVICE1__A 0x2150004 +#define B_EC_OC_REG_COMM_SERVICE1__W 11 +#define B_EC_OC_REG_COMM_SERVICE1__M 0x7FF + +#define B_EC_OC_REG_COMM_INT_STA__A 0x2150007 +#define B_EC_OC_REG_COMM_INT_STA__W 6 +#define B_EC_OC_REG_COMM_INT_STA__M 0x3F +#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 +#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 +#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 +#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 +#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 +#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 +#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 +#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 +#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 +#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 +#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 +#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 +#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 +#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 +#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 + +#define B_EC_OC_REG_COMM_INT_MSK__A 0x2150008 +#define B_EC_OC_REG_COMM_INT_MSK__W 6 +#define B_EC_OC_REG_COMM_INT_MSK__M 0x3F +#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 +#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 +#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 +#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 +#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 +#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 +#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 + +#define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 +#define B_EC_OC_REG_OC_MODE_LOP__W 16 +#define B_EC_OC_REG_OC_MODE_LOP__M 0xFFFF +#define B_EC_OC_REG_OC_MODE_LOP_INIT 0x0 + +#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 +#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 +#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 + +#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 +#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 +#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 + +#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 +#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 +#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 + +#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 +#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 +#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 + +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 + +#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 +#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 +#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 +#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 + +#define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 +#define B_EC_OC_REG_OC_MODE_HIP__W 15 +#define B_EC_OC_REG_OC_MODE_HIP__M 0x7FFF +#define B_EC_OC_REG_OC_MODE_HIP_INIT 0x5 + +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 + +#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 +#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 +#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 + +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 + +#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 +#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 +#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 + +#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 +#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 +#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 + +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 + +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 + +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 + +#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__B 14 +#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__W 1 +#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__M 0x4000 +#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_ZER 0x0 +#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_CLC 0x4000 + +#define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 +#define B_EC_OC_REG_OC_MPG_SIO__W 12 +#define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF +#define B_EC_OC_REG_OC_MPG_SIO_INIT 0xFFF + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 + +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 +#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 + +#define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 +#define B_EC_OC_REG_DTO_INC_LOP__W 16 +#define B_EC_OC_REG_DTO_INC_LOP__M 0xFFFF +#define B_EC_OC_REG_DTO_INC_LOP_INIT 0x0 + +#define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 +#define B_EC_OC_REG_DTO_INC_HIP__W 8 +#define B_EC_OC_REG_DTO_INC_HIP__M 0xFF +#define B_EC_OC_REG_DTO_INC_HIP_INIT 0xC0 + +#define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 +#define B_EC_OC_REG_SNC_ISC_LVL__W 12 +#define B_EC_OC_REG_SNC_ISC_LVL__M 0xFFF +#define B_EC_OC_REG_SNC_ISC_LVL_INIT 0x422 + +#define B_EC_OC_REG_SNC_ISC_LVL_ISC__B 0 +#define B_EC_OC_REG_SNC_ISC_LVL_ISC__W 4 +#define B_EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF + +#define B_EC_OC_REG_SNC_ISC_LVL_OSC__B 4 +#define B_EC_OC_REG_SNC_ISC_LVL_OSC__W 4 +#define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 + +#define B_EC_OC_REG_SNC_ISC_LVL_NSC__B 8 +#define B_EC_OC_REG_SNC_ISC_LVL_NSC__W 4 +#define B_EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 + +#define B_EC_OC_REG_SNC_NSC_LVL__A 0x2150017 +#define B_EC_OC_REG_SNC_NSC_LVL__W 8 +#define B_EC_OC_REG_SNC_NSC_LVL__M 0xFF +#define B_EC_OC_REG_SNC_NSC_LVL_INIT 0x0 + +#define B_EC_OC_REG_SNC_SNC_MODE__A 0x2150019 +#define B_EC_OC_REG_SNC_SNC_MODE__W 2 +#define B_EC_OC_REG_SNC_SNC_MODE__M 0x3 +#define B_EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 +#define B_EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 +#define B_EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 + +#define B_EC_OC_REG_SNC_PCK_NMB__A 0x215001A +#define B_EC_OC_REG_SNC_PCK_NMB__W 16 +#define B_EC_OC_REG_SNC_PCK_NMB__M 0xFFFF + +#define B_EC_OC_REG_SNC_PCK_CNT__A 0x215001B +#define B_EC_OC_REG_SNC_PCK_CNT__W 16 +#define B_EC_OC_REG_SNC_PCK_CNT__M 0xFFFF + +#define B_EC_OC_REG_SNC_PCK_ERR__A 0x215001C +#define B_EC_OC_REG_SNC_PCK_ERR__W 16 +#define B_EC_OC_REG_SNC_PCK_ERR__M 0xFFFF + +#define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D +#define B_EC_OC_REG_TMD_TOP_MODE__W 2 +#define B_EC_OC_REG_TMD_TOP_MODE__M 0x3 +#define B_EC_OC_REG_TMD_TOP_MODE_INIT 0x3 +#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 +#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 +#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 +#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 + +#define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E +#define B_EC_OC_REG_TMD_TOP_CNT__W 10 +#define B_EC_OC_REG_TMD_TOP_CNT__M 0x3FF +#define B_EC_OC_REG_TMD_TOP_CNT_INIT 0x1F4 + +#define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F +#define B_EC_OC_REG_TMD_HIL_MAR__W 10 +#define B_EC_OC_REG_TMD_HIL_MAR__M 0x3FF +#define B_EC_OC_REG_TMD_HIL_MAR_INIT 0x3C0 + +#define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 +#define B_EC_OC_REG_TMD_LOL_MAR__W 10 +#define B_EC_OC_REG_TMD_LOL_MAR__M 0x3FF +#define B_EC_OC_REG_TMD_LOL_MAR_INIT 0x40 + +#define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 +#define B_EC_OC_REG_TMD_CUR_CNT__W 4 +#define B_EC_OC_REG_TMD_CUR_CNT__M 0xF +#define B_EC_OC_REG_TMD_CUR_CNT_INIT 0x3 + +#define B_EC_OC_REG_TMD_IUR_CNT__A 0x2150022 +#define B_EC_OC_REG_TMD_IUR_CNT__W 4 +#define B_EC_OC_REG_TMD_IUR_CNT__M 0xF +#define B_EC_OC_REG_TMD_IUR_CNT_INIT 0x0 + +#define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 +#define B_EC_OC_REG_AVR_ASH_CNT__W 4 +#define B_EC_OC_REG_AVR_ASH_CNT__M 0xF +#define B_EC_OC_REG_AVR_ASH_CNT_INIT 0x6 + +#define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 +#define B_EC_OC_REG_AVR_BSH_CNT__W 4 +#define B_EC_OC_REG_AVR_BSH_CNT__M 0xF +#define B_EC_OC_REG_AVR_BSH_CNT_INIT 0x2 + +#define B_EC_OC_REG_AVR_AVE_LOP__A 0x2150025 +#define B_EC_OC_REG_AVR_AVE_LOP__W 16 +#define B_EC_OC_REG_AVR_AVE_LOP__M 0xFFFF + +#define B_EC_OC_REG_AVR_AVE_HIP__A 0x2150026 +#define B_EC_OC_REG_AVR_AVE_HIP__W 5 +#define B_EC_OC_REG_AVR_AVE_HIP__M 0x1F + +#define B_EC_OC_REG_RCN_MODE__A 0x2150027 +#define B_EC_OC_REG_RCN_MODE__W 3 +#define B_EC_OC_REG_RCN_MODE__M 0x7 +#define B_EC_OC_REG_RCN_MODE_INIT 0x7 + +#define B_EC_OC_REG_RCN_MODE_MODE_0__B 0 +#define B_EC_OC_REG_RCN_MODE_MODE_0__W 1 +#define B_EC_OC_REG_RCN_MODE_MODE_0__M 0x1 +#define B_EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 +#define B_EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 + +#define B_EC_OC_REG_RCN_MODE_MODE_1__B 1 +#define B_EC_OC_REG_RCN_MODE_MODE_1__W 1 +#define B_EC_OC_REG_RCN_MODE_MODE_1__M 0x2 +#define B_EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 +#define B_EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 + +#define B_EC_OC_REG_RCN_MODE_MODE_2__B 2 +#define B_EC_OC_REG_RCN_MODE_MODE_2__W 1 +#define B_EC_OC_REG_RCN_MODE_MODE_2__M 0x4 +#define B_EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 +#define B_EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 + +#define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 +#define B_EC_OC_REG_RCN_CRA_LOP__W 16 +#define B_EC_OC_REG_RCN_CRA_LOP__M 0xFFFF +#define B_EC_OC_REG_RCN_CRA_LOP_INIT 0x0 + +#define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 +#define B_EC_OC_REG_RCN_CRA_HIP__W 8 +#define B_EC_OC_REG_RCN_CRA_HIP__M 0xFF +#define B_EC_OC_REG_RCN_CRA_HIP_INIT 0xC0 + +#define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A +#define B_EC_OC_REG_RCN_CST_LOP__W 16 +#define B_EC_OC_REG_RCN_CST_LOP__M 0xFFFF +#define B_EC_OC_REG_RCN_CST_LOP_INIT 0x1000 + +#define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B +#define B_EC_OC_REG_RCN_CST_HIP__W 8 +#define B_EC_OC_REG_RCN_CST_HIP__M 0xFF +#define B_EC_OC_REG_RCN_CST_HIP_INIT 0x0 + +#define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C +#define B_EC_OC_REG_RCN_SET_LVL__W 9 +#define B_EC_OC_REG_RCN_SET_LVL__M 0x1FF +#define B_EC_OC_REG_RCN_SET_LVL_INIT 0x1FF + +#define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D +#define B_EC_OC_REG_RCN_GAI_LVL__W 4 +#define B_EC_OC_REG_RCN_GAI_LVL__M 0xF +#define B_EC_OC_REG_RCN_GAI_LVL_INIT 0xA + +#define B_EC_OC_REG_RCN_DRA_LOP__A 0x215002E +#define B_EC_OC_REG_RCN_DRA_LOP__W 16 +#define B_EC_OC_REG_RCN_DRA_LOP__M 0xFFFF + +#define B_EC_OC_REG_RCN_DRA_HIP__A 0x215002F +#define B_EC_OC_REG_RCN_DRA_HIP__W 8 +#define B_EC_OC_REG_RCN_DRA_HIP__M 0xFF + +#define B_EC_OC_REG_RCN_DOF_LOP__A 0x2150030 +#define B_EC_OC_REG_RCN_DOF_LOP__W 16 +#define B_EC_OC_REG_RCN_DOF_LOP__M 0xFFFF + +#define B_EC_OC_REG_RCN_DOF_HIP__A 0x2150031 +#define B_EC_OC_REG_RCN_DOF_HIP__W 8 +#define B_EC_OC_REG_RCN_DOF_HIP__M 0xFF + +#define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032 +#define B_EC_OC_REG_RCN_CLP_LOP__W 16 +#define B_EC_OC_REG_RCN_CLP_LOP__M 0xFFFF +#define B_EC_OC_REG_RCN_CLP_LOP_INIT 0x0 + +#define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 +#define B_EC_OC_REG_RCN_CLP_HIP__W 8 +#define B_EC_OC_REG_RCN_CLP_HIP__M 0xFF +#define B_EC_OC_REG_RCN_CLP_HIP_INIT 0xC0 + +#define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 +#define B_EC_OC_REG_RCN_MAP_LOP__W 16 +#define B_EC_OC_REG_RCN_MAP_LOP__M 0xFFFF + +#define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035 +#define B_EC_OC_REG_RCN_MAP_HIP__W 8 +#define B_EC_OC_REG_RCN_MAP_HIP__M 0xFF + +#define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036 +#define B_EC_OC_REG_OCR_MPG_UOS__W 12 +#define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF +#define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 + +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 + +#define B_EC_OC_REG_OCR_MPG_UOS_ERR__B 8 +#define B_EC_OC_REG_OCR_MPG_UOS_ERR__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 +#define B_EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 + +#define B_EC_OC_REG_OCR_MPG_UOS_STR__B 9 +#define B_EC_OC_REG_OCR_MPG_UOS_STR__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 +#define B_EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 + +#define B_EC_OC_REG_OCR_MPG_UOS_VAL__B 10 +#define B_EC_OC_REG_OCR_MPG_UOS_VAL__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 +#define B_EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 + +#define B_EC_OC_REG_OCR_MPG_UOS_CLK__B 11 +#define B_EC_OC_REG_OCR_MPG_UOS_CLK__W 1 +#define B_EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 +#define B_EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 + +#define B_EC_OC_REG_OCR_MPG_WRI__A 0x2150037 +#define B_EC_OC_REG_OCR_MPG_WRI__W 12 +#define B_EC_OC_REG_OCR_MPG_WRI__M 0xFFF +#define B_EC_OC_REG_OCR_MPG_WRI_INIT 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 +#define B_EC_OC_REG_OCR_MPG_WRI_ERR__B 8 +#define B_EC_OC_REG_OCR_MPG_WRI_ERR__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 +#define B_EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 +#define B_EC_OC_REG_OCR_MPG_WRI_STR__B 9 +#define B_EC_OC_REG_OCR_MPG_WRI_STR__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 +#define B_EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 +#define B_EC_OC_REG_OCR_MPG_WRI_VAL__B 10 +#define B_EC_OC_REG_OCR_MPG_WRI_VAL__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 +#define B_EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 +#define B_EC_OC_REG_OCR_MPG_WRI_CLK__B 11 +#define B_EC_OC_REG_OCR_MPG_WRI_CLK__W 1 +#define B_EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 +#define B_EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 +#define B_EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 + +#define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 +#define B_EC_OC_REG_OCR_MPG_USR_DAT__W 12 +#define B_EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF + +#define B_EC_OC_REG_OCR_MON_CNT__A 0x215003C +#define B_EC_OC_REG_OCR_MON_CNT__W 14 +#define B_EC_OC_REG_OCR_MON_CNT__M 0x3FFF +#define B_EC_OC_REG_OCR_MON_CNT_INIT 0x0 + +#define B_EC_OC_REG_OCR_MON_RDX__A 0x215003D +#define B_EC_OC_REG_OCR_MON_RDX__W 1 +#define B_EC_OC_REG_OCR_MON_RDX__M 0x1 +#define B_EC_OC_REG_OCR_MON_RDX_INIT 0x0 + +#define B_EC_OC_REG_OCR_MON_RD0__A 0x215003E +#define B_EC_OC_REG_OCR_MON_RD0__W 10 +#define B_EC_OC_REG_OCR_MON_RD0__M 0x3FF + +#define B_EC_OC_REG_OCR_MON_RD1__A 0x215003F +#define B_EC_OC_REG_OCR_MON_RD1__W 10 +#define B_EC_OC_REG_OCR_MON_RD1__M 0x3FF + +#define B_EC_OC_REG_OCR_MON_RD2__A 0x2150040 +#define B_EC_OC_REG_OCR_MON_RD2__W 10 +#define B_EC_OC_REG_OCR_MON_RD2__M 0x3FF + +#define B_EC_OC_REG_OCR_MON_RD3__A 0x2150041 +#define B_EC_OC_REG_OCR_MON_RD3__W 10 +#define B_EC_OC_REG_OCR_MON_RD3__M 0x3FF + +#define B_EC_OC_REG_OCR_MON_RD4__A 0x2150042 +#define B_EC_OC_REG_OCR_MON_RD4__W 10 +#define B_EC_OC_REG_OCR_MON_RD4__M 0x3FF + +#define B_EC_OC_REG_OCR_MON_RD5__A 0x2150043 +#define B_EC_OC_REG_OCR_MON_RD5__W 10 +#define B_EC_OC_REG_OCR_MON_RD5__M 0x3FF + +#define B_EC_OC_REG_OCR_INV_MON__A 0x2150044 +#define B_EC_OC_REG_OCR_INV_MON__W 12 +#define B_EC_OC_REG_OCR_INV_MON__M 0xFFF +#define B_EC_OC_REG_OCR_INV_MON_INIT 0x0 + +#define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 +#define B_EC_OC_REG_IPR_INV_MPG__W 12 +#define B_EC_OC_REG_IPR_INV_MPG__M 0xFFF +#define B_EC_OC_REG_IPR_INV_MPG_INIT 0x0 + +#define B_EC_OC_REG_IPR_MSR_SNC__A 0x2150046 +#define B_EC_OC_REG_IPR_MSR_SNC__W 6 +#define B_EC_OC_REG_IPR_MSR_SNC__M 0x3F +#define B_EC_OC_REG_IPR_MSR_SNC_INIT 0x0 + +#define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 +#define B_EC_OC_REG_DTO_CLKMODE__W 2 +#define B_EC_OC_REG_DTO_CLKMODE__M 0x3 +#define B_EC_OC_REG_DTO_CLKMODE_INIT 0x2 + +#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__B 0 +#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__W 1 +#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__M 0x1 +#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_EVEN_ODD 0x0 +#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_ODD_EVEN 0x1 + +#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__B 1 +#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__W 1 +#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__M 0x2 +#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_SERIAL_MODE 0x0 +#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_PARALLEL_MODE 0x2 + +#define B_EC_OC_REG_DTO_PER__A 0x2150048 +#define B_EC_OC_REG_DTO_PER__W 8 +#define B_EC_OC_REG_DTO_PER__M 0xFF +#define B_EC_OC_REG_DTO_PER_INIT 0x6 + +#define B_EC_OC_REG_DTO_BUR__A 0x2150049 +#define B_EC_OC_REG_DTO_BUR__W 2 +#define B_EC_OC_REG_DTO_BUR__M 0x3 +#define B_EC_OC_REG_DTO_BUR_INIT 0x1 +#define B_EC_OC_REG_DTO_BUR_SELECT_1 0x0 +#define B_EC_OC_REG_DTO_BUR_SELECT_188 0x1 +#define B_EC_OC_REG_DTO_BUR_SELECT_204 0x2 +#define B_EC_OC_REG_DTO_BUR_SELECT_47 0x3 + +#define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A +#define B_EC_OC_REG_RCR_CLKMODE__W 3 +#define B_EC_OC_REG_RCR_CLKMODE__M 0x7 +#define B_EC_OC_REG_RCR_CLKMODE_INIT 0x0 + +#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__B 0 +#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__W 1 +#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__M 0x1 +#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_FRACIONAL 0x0 +#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_RATIONAL 0x1 + +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__B 1 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__W 1 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__M 0x2 #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_FRACTIONAL 0x0 #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_RATIONAL 0x2 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__B 2 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__W 1 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__M 0x4 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FIFO 0x0 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__B 2 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__W 1 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__M 0x4 +#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FIFO 0x0 #define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FEEDBACKLOOP 0x4 -#define B_EC_OC_RAM__A 0x2160000 - -#define B_CC_SID 0x1B - -#define B_CC_COMM_EXEC__A 0x2400000 -#define B_CC_COMM_EXEC__W 3 -#define B_CC_COMM_EXEC__M 0x7 -#define B_CC_COMM_EXEC_CTL__B 0 -#define B_CC_COMM_EXEC_CTL__W 3 -#define B_CC_COMM_EXEC_CTL__M 0x7 -#define B_CC_COMM_EXEC_CTL_STOP 0x0 -#define B_CC_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CC_COMM_EXEC_CTL_HOLD 0x2 -#define B_CC_COMM_EXEC_CTL_STEP 0x3 -#define B_CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_CC_COMM_STATE__A 0x2400001 -#define B_CC_COMM_STATE__W 16 -#define B_CC_COMM_STATE__M 0xFFFF -#define B_CC_COMM_MB__A 0x2400002 -#define B_CC_COMM_MB__W 16 -#define B_CC_COMM_MB__M 0xFFFF -#define B_CC_COMM_SERVICE0__A 0x2400003 -#define B_CC_COMM_SERVICE0__W 16 -#define B_CC_COMM_SERVICE0__M 0xFFFF -#define B_CC_COMM_SERVICE1__A 0x2400004 -#define B_CC_COMM_SERVICE1__W 16 -#define B_CC_COMM_SERVICE1__M 0xFFFF -#define B_CC_COMM_INT_STA__A 0x2400007 -#define B_CC_COMM_INT_STA__W 16 -#define B_CC_COMM_INT_STA__M 0xFFFF -#define B_CC_COMM_INT_MSK__A 0x2400008 -#define B_CC_COMM_INT_MSK__W 16 -#define B_CC_COMM_INT_MSK__M 0xFFFF - -#define B_CC_REG_COMM_EXEC__A 0x2410000 -#define B_CC_REG_COMM_EXEC__W 3 -#define B_CC_REG_COMM_EXEC__M 0x7 -#define B_CC_REG_COMM_EXEC_CTL__B 0 -#define B_CC_REG_COMM_EXEC_CTL__W 3 -#define B_CC_REG_COMM_EXEC_CTL__M 0x7 -#define B_CC_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CC_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_CC_REG_COMM_EXEC_CTL_STEP 0x3 -#define B_CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_CC_REG_COMM_STATE__A 0x2410001 -#define B_CC_REG_COMM_STATE__W 16 -#define B_CC_REG_COMM_STATE__M 0xFFFF -#define B_CC_REG_COMM_MB__A 0x2410002 -#define B_CC_REG_COMM_MB__W 16 -#define B_CC_REG_COMM_MB__M 0xFFFF -#define B_CC_REG_COMM_SERVICE0__A 0x2410003 -#define B_CC_REG_COMM_SERVICE0__W 16 -#define B_CC_REG_COMM_SERVICE0__M 0xFFFF -#define B_CC_REG_COMM_SERVICE1__A 0x2410004 -#define B_CC_REG_COMM_SERVICE1__W 16 -#define B_CC_REG_COMM_SERVICE1__M 0xFFFF -#define B_CC_REG_COMM_INT_STA__A 0x2410007 -#define B_CC_REG_COMM_INT_STA__W 16 -#define B_CC_REG_COMM_INT_STA__M 0xFFFF -#define B_CC_REG_COMM_INT_MSK__A 0x2410008 -#define B_CC_REG_COMM_INT_MSK__W 16 -#define B_CC_REG_COMM_INT_MSK__M 0xFFFF - -#define B_CC_REG_OSC_MODE__A 0x2410010 -#define B_CC_REG_OSC_MODE__W 2 -#define B_CC_REG_OSC_MODE__M 0x3 -#define B_CC_REG_OSC_MODE_OHW 0x0 -#define B_CC_REG_OSC_MODE_M20 0x1 -#define B_CC_REG_OSC_MODE_M48 0x2 - -#define B_CC_REG_PLL_MODE__A 0x2410011 -#define B_CC_REG_PLL_MODE__W 6 -#define B_CC_REG_PLL_MODE__M 0x3F -#define B_CC_REG_PLL_MODE_INIT 0xC -#define B_CC_REG_PLL_MODE_BYPASS__B 0 -#define B_CC_REG_PLL_MODE_BYPASS__W 2 -#define B_CC_REG_PLL_MODE_BYPASS__M 0x3 -#define B_CC_REG_PLL_MODE_BYPASS_OHW 0x0 -#define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1 -#define B_CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 -#define B_CC_REG_PLL_MODE_PUMP__B 2 -#define B_CC_REG_PLL_MODE_PUMP__W 3 -#define B_CC_REG_PLL_MODE_PUMP__M 0x1C -#define B_CC_REG_PLL_MODE_PUMP_OFF 0x0 -#define B_CC_REG_PLL_MODE_PUMP_CUR_08 0x4 -#define B_CC_REG_PLL_MODE_PUMP_CUR_09 0x8 -#define B_CC_REG_PLL_MODE_PUMP_CUR_10 0xC -#define B_CC_REG_PLL_MODE_PUMP_CUR_11 0x10 -#define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14 -#define B_CC_REG_PLL_MODE_OUT_EN__B 5 -#define B_CC_REG_PLL_MODE_OUT_EN__W 1 -#define B_CC_REG_PLL_MODE_OUT_EN__M 0x20 -#define B_CC_REG_PLL_MODE_OUT_EN_OFF 0x0 -#define B_CC_REG_PLL_MODE_OUT_EN_ON 0x20 - -#define B_CC_REG_REF_DIVIDE__A 0x2410012 -#define B_CC_REG_REF_DIVIDE__W 4 -#define B_CC_REG_REF_DIVIDE__M 0xF -#define B_CC_REG_REF_DIVIDE_INIT 0xA -#define B_CC_REG_REF_DIVIDE_OHW 0x0 -#define B_CC_REG_REF_DIVIDE_D01 0x1 -#define B_CC_REG_REF_DIVIDE_D02 0x2 -#define B_CC_REG_REF_DIVIDE_D03 0x3 -#define B_CC_REG_REF_DIVIDE_D04 0x4 -#define B_CC_REG_REF_DIVIDE_D05 0x5 -#define B_CC_REG_REF_DIVIDE_D06 0x6 -#define B_CC_REG_REF_DIVIDE_D07 0x7 -#define B_CC_REG_REF_DIVIDE_D08 0x8 -#define B_CC_REG_REF_DIVIDE_D09 0x9 -#define B_CC_REG_REF_DIVIDE_D10 0xA - -#define B_CC_REG_REF_DELAY__A 0x2410013 -#define B_CC_REG_REF_DELAY__W 3 -#define B_CC_REG_REF_DELAY__M 0x7 -#define B_CC_REG_REF_DELAY_EDGE__B 0 -#define B_CC_REG_REF_DELAY_EDGE__W 1 -#define B_CC_REG_REF_DELAY_EDGE__M 0x1 -#define B_CC_REG_REF_DELAY_EDGE_POS 0x0 -#define B_CC_REG_REF_DELAY_EDGE_NEG 0x1 -#define B_CC_REG_REF_DELAY_DELAY__B 1 -#define B_CC_REG_REF_DELAY_DELAY__W 2 -#define B_CC_REG_REF_DELAY_DELAY__M 0x6 -#define B_CC_REG_REF_DELAY_DELAY_DEL_0 0x0 -#define B_CC_REG_REF_DELAY_DELAY_DEL_3 0x2 -#define B_CC_REG_REF_DELAY_DELAY_DEL_6 0x4 -#define B_CC_REG_REF_DELAY_DELAY_DEL_9 0x6 - -#define B_CC_REG_CLK_DELAY__A 0x2410014 -#define B_CC_REG_CLK_DELAY__W 5 -#define B_CC_REG_CLK_DELAY__M 0x1F -#define B_CC_REG_CLK_DELAY_DELAY__B 0 -#define B_CC_REG_CLK_DELAY_DELAY__W 4 -#define B_CC_REG_CLK_DELAY_DELAY__M 0xF -#define B_CC_REG_CLK_DELAY_DELAY_DEL_00 0x0 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_05 0x1 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_10 0x2 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_15 0x3 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_20 0x4 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_25 0x5 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_30 0x6 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_35 0x7 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_40 0x8 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_45 0x9 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_50 0xA -#define B_CC_REG_CLK_DELAY_DELAY_DEL_55 0xB -#define B_CC_REG_CLK_DELAY_DELAY_DEL_60 0xC -#define B_CC_REG_CLK_DELAY_DELAY_DEL_65 0xD -#define B_CC_REG_CLK_DELAY_DELAY_DEL_70 0xE -#define B_CC_REG_CLK_DELAY_DELAY_DEL_75 0xF -#define B_CC_REG_CLK_DELAY_EDGE__B 4 -#define B_CC_REG_CLK_DELAY_EDGE__W 1 -#define B_CC_REG_CLK_DELAY_EDGE__M 0x10 -#define B_CC_REG_CLK_DELAY_EDGE_POS 0x0 -#define B_CC_REG_CLK_DELAY_EDGE_NEG 0x10 - -#define B_CC_REG_PWD_MODE__A 0x2410015 -#define B_CC_REG_PWD_MODE__W 2 -#define B_CC_REG_PWD_MODE__M 0x3 -#define B_CC_REG_PWD_MODE_UP 0x0 -#define B_CC_REG_PWD_MODE_DOWN_CLK 0x1 -#define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 -#define B_CC_REG_PWD_MODE_DOWN_OSC 0x3 - -#define B_CC_REG_SOFT_RST__A 0x2410016 -#define B_CC_REG_SOFT_RST__W 2 -#define B_CC_REG_SOFT_RST__M 0x3 -#define B_CC_REG_SOFT_RST_SYS__B 0 -#define B_CC_REG_SOFT_RST_SYS__W 1 -#define B_CC_REG_SOFT_RST_SYS__M 0x1 -#define B_CC_REG_SOFT_RST_OSC__B 1 -#define B_CC_REG_SOFT_RST_OSC__W 1 -#define B_CC_REG_SOFT_RST_OSC__M 0x2 - -#define B_CC_REG_UPDATE__A 0x2410017 -#define B_CC_REG_UPDATE__W 16 -#define B_CC_REG_UPDATE__M 0xFFFF -#define B_CC_REG_UPDATE_KEY 0x3973 - -#define B_CC_REG_PLL_LOCK__A 0x2410018 -#define B_CC_REG_PLL_LOCK__W 1 -#define B_CC_REG_PLL_LOCK__M 0x1 -#define B_CC_REG_PLL_LOCK_LOCK 0x1 - -#define B_CC_REG_JTAGID_L__A 0x2410019 -#define B_CC_REG_JTAGID_L__W 16 -#define B_CC_REG_JTAGID_L__M 0xFFFF -#define B_CC_REG_JTAGID_L_INIT 0x0 - -#define B_CC_REG_JTAGID_H__A 0x241001A -#define B_CC_REG_JTAGID_H__W 16 -#define B_CC_REG_JTAGID_H__M 0xFFFF -#define B_CC_REG_JTAGID_H_INIT 0x0 - -#define B_CC_REG_DIVERSITY__A 0x241001B -#define B_CC_REG_DIVERSITY__W 1 -#define B_CC_REG_DIVERSITY__M 0x1 -#define B_CC_REG_DIVERSITY_INIT 0x0 - -#define B_CC_REG_BACKUP3V__A 0x241001C -#define B_CC_REG_BACKUP3V__W 1 -#define B_CC_REG_BACKUP3V__M 0x1 -#define B_CC_REG_BACKUP3V_INIT 0x0 - -#define B_CC_REG_DRV_IO__A 0x241001D -#define B_CC_REG_DRV_IO__W 3 -#define B_CC_REG_DRV_IO__M 0x7 -#define B_CC_REG_DRV_IO_INIT 0x2 - -#define B_CC_REG_DRV_MPG__A 0x241001E -#define B_CC_REG_DRV_MPG__W 3 -#define B_CC_REG_DRV_MPG__M 0x7 -#define B_CC_REG_DRV_MPG_INIT 0x2 - -#define B_CC_REG_DRV_I2C1__A 0x241001F -#define B_CC_REG_DRV_I2C1__W 3 -#define B_CC_REG_DRV_I2C1__M 0x7 -#define B_CC_REG_DRV_I2C1_INIT 0x2 - -#define B_CC_REG_DRV_I2C2__A 0x2410020 -#define B_CC_REG_DRV_I2C2__W 1 -#define B_CC_REG_DRV_I2C2__M 0x1 -#define B_CC_REG_DRV_I2C2_INIT 0x0 - -#define B_LC_SID 0x1C - -#define B_LC_COMM_EXEC__A 0x2800000 -#define B_LC_COMM_EXEC__W 3 -#define B_LC_COMM_EXEC__M 0x7 -#define B_LC_COMM_EXEC_CTL__B 0 -#define B_LC_COMM_EXEC_CTL__W 3 -#define B_LC_COMM_EXEC_CTL__M 0x7 -#define B_LC_COMM_EXEC_CTL_STOP 0x0 -#define B_LC_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_LC_COMM_EXEC_CTL_HOLD 0x2 -#define B_LC_COMM_EXEC_CTL_STEP 0x3 -#define B_LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_LC_COMM_STATE__A 0x2800001 -#define B_LC_COMM_STATE__W 16 -#define B_LC_COMM_STATE__M 0xFFFF -#define B_LC_COMM_MB__A 0x2800002 -#define B_LC_COMM_MB__W 16 -#define B_LC_COMM_MB__M 0xFFFF -#define B_LC_COMM_SERVICE0__A 0x2800003 -#define B_LC_COMM_SERVICE0__W 16 -#define B_LC_COMM_SERVICE0__M 0xFFFF -#define B_LC_COMM_SERVICE1__A 0x2800004 -#define B_LC_COMM_SERVICE1__W 16 -#define B_LC_COMM_SERVICE1__M 0xFFFF -#define B_LC_COMM_INT_STA__A 0x2800007 -#define B_LC_COMM_INT_STA__W 16 -#define B_LC_COMM_INT_STA__M 0xFFFF -#define B_LC_COMM_INT_MSK__A 0x2800008 -#define B_LC_COMM_INT_MSK__W 16 -#define B_LC_COMM_INT_MSK__M 0xFFFF - -#define B_LC_CT_REG_COMM_EXEC__A 0x2810000 -#define B_LC_CT_REG_COMM_EXEC__W 3 -#define B_LC_CT_REG_COMM_EXEC__M 0x7 -#define B_LC_CT_REG_COMM_EXEC_CTL__B 0 -#define B_LC_CT_REG_COMM_EXEC_CTL__W 3 -#define B_LC_CT_REG_COMM_EXEC_CTL__M 0x7 -#define B_LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_LC_CT_REG_COMM_STATE__A 0x2810001 -#define B_LC_CT_REG_COMM_STATE__W 10 -#define B_LC_CT_REG_COMM_STATE__M 0x3FF -#define B_LC_CT_REG_COMM_SERVICE0__A 0x2810003 -#define B_LC_CT_REG_COMM_SERVICE0__W 16 -#define B_LC_CT_REG_COMM_SERVICE0__M 0xFFFF -#define B_LC_CT_REG_COMM_SERVICE1__A 0x2810004 -#define B_LC_CT_REG_COMM_SERVICE1__W 16 -#define B_LC_CT_REG_COMM_SERVICE1__M 0xFFFF -#define B_LC_CT_REG_COMM_SERVICE1_LC__B 12 -#define B_LC_CT_REG_COMM_SERVICE1_LC__W 1 -#define B_LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 - -#define B_LC_CT_REG_COMM_INT_STA__A 0x2810007 -#define B_LC_CT_REG_COMM_INT_STA__W 1 -#define B_LC_CT_REG_COMM_INT_STA__M 0x1 -#define B_LC_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define B_LC_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define B_LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define B_LC_CT_REG_COMM_INT_MSK__A 0x2810008 -#define B_LC_CT_REG_COMM_INT_MSK__W 1 -#define B_LC_CT_REG_COMM_INT_MSK__M 0x1 -#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define B_LC_CT_REG_CTL_STK__AX 0x2810010 -#define B_LC_CT_REG_CTL_STK__XSZ 4 -#define B_LC_CT_REG_CTL_STK__W 10 -#define B_LC_CT_REG_CTL_STK__M 0x3FF - -#define B_LC_CT_REG_CTL_BPT_IDX__A 0x281001F -#define B_LC_CT_REG_CTL_BPT_IDX__W 1 -#define B_LC_CT_REG_CTL_BPT_IDX__M 0x1 - -#define B_LC_CT_REG_CTL_BPT__A 0x2810020 -#define B_LC_CT_REG_CTL_BPT__W 10 -#define B_LC_CT_REG_CTL_BPT__M 0x3FF - -#define B_LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 -#define B_LC_RA_RAM_PROC_DELAY_IF__W 16 -#define B_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF -#define B_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 -#define B_LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 -#define B_LC_RA_RAM_PROC_DELAY_FS__W 16 -#define B_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF -#define B_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 -#define B_LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 -#define B_LC_RA_RAM_LOCK_TH_CRMM__W 16 -#define B_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF -#define B_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 -#define B_LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 -#define B_LC_RA_RAM_LOCK_TH_SRMM__W 16 -#define B_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF -#define B_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 -#define B_LC_RA_RAM_LOCK_COUNT__A 0x282000A -#define B_LC_RA_RAM_LOCK_COUNT__W 16 -#define B_LC_RA_RAM_LOCK_COUNT__M 0xFFFF -#define B_LC_RA_RAM_CPRTOFS_NOM__A 0x282000B -#define B_LC_RA_RAM_CPRTOFS_NOM__W 16 -#define B_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF -#define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C -#define B_LC_RA_RAM_IFINCR_NOM_L__W 16 -#define B_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF -#define B_LC_RA_RAM_IFINCR_NOM_H__A 0x282000D -#define B_LC_RA_RAM_IFINCR_NOM_H__W 16 -#define B_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF -#define B_LC_RA_RAM_FSINCR_NOM_L__A 0x282000E -#define B_LC_RA_RAM_FSINCR_NOM_L__W 16 -#define B_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF -#define B_LC_RA_RAM_FSINCR_NOM_H__A 0x282000F -#define B_LC_RA_RAM_FSINCR_NOM_H__W 16 -#define B_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF -#define B_LC_RA_RAM_MODE_2K__A 0x2820010 -#define B_LC_RA_RAM_MODE_2K__W 16 -#define B_LC_RA_RAM_MODE_2K__M 0xFFFF -#define B_LC_RA_RAM_MODE_GUARD__A 0x2820011 -#define B_LC_RA_RAM_MODE_GUARD__W 16 -#define B_LC_RA_RAM_MODE_GUARD__M 0xFFFF -#define B_LC_RA_RAM_MODE_GUARD_32 0x0 -#define B_LC_RA_RAM_MODE_GUARD_16 0x1 -#define B_LC_RA_RAM_MODE_GUARD_8 0x2 -#define B_LC_RA_RAM_MODE_GUARD_4 0x3 - -#define B_LC_RA_RAM_MODE_ADJUST__A 0x2820012 -#define B_LC_RA_RAM_MODE_ADJUST__W 16 -#define B_LC_RA_RAM_MODE_ADJUST__M 0xFFFF -#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 -#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 -#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 -#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 -#define B_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 -#define B_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 -#define B_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 -#define B_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 -#define B_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 -#define B_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 -#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 -#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 -#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 -#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 -#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 -#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 -#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 -#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 -#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 -#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 - -#define B_LC_RA_RAM_RC_STS__A 0x2820014 -#define B_LC_RA_RAM_RC_STS__W 16 -#define B_LC_RA_RAM_RC_STS__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x2820018 -#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 -#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x2820019 -#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 -#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF -#define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A -#define B_LC_RA_RAM_FILTER_SYM_SET__W 16 -#define B_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF -#define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 -#define B_LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B -#define B_LC_RA_RAM_FILTER_SYM_CUR__W 16 -#define B_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF -#define B_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 -#define B_LC_RA_RAM_DIVERSITY_DELAY__A 0x282001C -#define B_LC_RA_RAM_DIVERSITY_DELAY__W 16 -#define B_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF -#define B_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 -#define B_LC_RA_RAM_MAX_ABS_EXP__A 0x282001D -#define B_LC_RA_RAM_MAX_ABS_EXP__W 16 -#define B_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF -#define B_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 -#define B_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F -#define B_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 -#define B_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 -#define B_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 -#define B_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 -#define B_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 -#define B_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 -#define B_LC_RA_RAM_ACTUAL_PHASE__W 16 -#define B_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 -#define B_LC_RA_RAM_ACTUAL_DELAY__W 16 -#define B_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF -#define B_LC_RA_RAM_ADJUST_CRMM__A 0x2820024 -#define B_LC_RA_RAM_ADJUST_CRMM__W 16 -#define B_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF -#define B_LC_RA_RAM_ADJUST_SRMM__A 0x2820025 -#define B_LC_RA_RAM_ADJUST_SRMM__W 16 -#define B_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF -#define B_LC_RA_RAM_ADJUST_PHASE__A 0x2820026 -#define B_LC_RA_RAM_ADJUST_PHASE__W 16 -#define B_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF -#define B_LC_RA_RAM_ADJUST_DELAY__A 0x2820027 -#define B_LC_RA_RAM_ADJUST_DELAY__W 16 -#define B_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF - -#define B_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 -#define B_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 -#define B_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A -#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B -#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C -#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D -#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF - -#define B_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 -#define B_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 -#define B_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 -#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 -#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 -#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 -#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF - -#define B_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 -#define B_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 -#define B_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A -#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B -#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C -#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D -#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF - -#define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 -#define B_LC_RA_RAM_FILTER_CRMM_A__W 16 -#define B_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF -#define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 -#define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 -#define B_LC_RA_RAM_FILTER_CRMM_B__W 16 -#define B_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF -#define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 -#define B_LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 -#define B_LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 -#define B_LC_RA_RAM_FILTER_CRMM_Z1__W 16 -#define B_LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF -#define B_LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 -#define B_LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 -#define B_LC_RA_RAM_FILTER_CRMM_Z2__W 16 -#define B_LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF -#define B_LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 -#define B_LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 -#define B_LC_RA_RAM_FILTER_CRMM_TMP__W 16 -#define B_LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF - -#define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 -#define B_LC_RA_RAM_FILTER_SRMM_A__W 16 -#define B_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF -#define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 -#define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 -#define B_LC_RA_RAM_FILTER_SRMM_B__W 16 -#define B_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF -#define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 -#define B_LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A -#define B_LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 -#define B_LC_RA_RAM_FILTER_SRMM_Z1__W 16 -#define B_LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF -#define B_LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C -#define B_LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 -#define B_LC_RA_RAM_FILTER_SRMM_Z2__W 16 -#define B_LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF -#define B_LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E -#define B_LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 -#define B_LC_RA_RAM_FILTER_SRMM_TMP__W 16 -#define B_LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF - -#define B_LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 -#define B_LC_RA_RAM_FILTER_PHASE_A__W 16 -#define B_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF -#define B_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 -#define B_LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 -#define B_LC_RA_RAM_FILTER_PHASE_B__W 16 -#define B_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF -#define B_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 -#define B_LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 -#define B_LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 -#define B_LC_RA_RAM_FILTER_PHASE_Z1__W 16 -#define B_LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF -#define B_LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 -#define B_LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 -#define B_LC_RA_RAM_FILTER_PHASE_Z2__W 16 -#define B_LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF -#define B_LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 -#define B_LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 -#define B_LC_RA_RAM_FILTER_PHASE_TMP__W 16 -#define B_LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF - -#define B_LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 -#define B_LC_RA_RAM_FILTER_DELAY_A__W 16 -#define B_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF -#define B_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 -#define B_LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 -#define B_LC_RA_RAM_FILTER_DELAY_B__W 16 -#define B_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF -#define B_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 -#define B_LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A -#define B_LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 -#define B_LC_RA_RAM_FILTER_DELAY_Z1__W 16 -#define B_LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF -#define B_LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C -#define B_LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 -#define B_LC_RA_RAM_FILTER_DELAY_Z2__W 16 -#define B_LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF -#define B_LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E -#define B_LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 -#define B_LC_RA_RAM_FILTER_DELAY_TMP__W 16 -#define B_LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF - -#define B_LC_IF_RAM_TRP_BPT0__AX 0x2830000 -#define B_LC_IF_RAM_TRP_BPT0__XSZ 2 -#define B_LC_IF_RAM_TRP_BPT0__W 12 -#define B_LC_IF_RAM_TRP_BPT0__M 0xFFF - -#define B_LC_IF_RAM_TRP_STKU__AX 0x2830002 -#define B_LC_IF_RAM_TRP_STKU__XSZ 2 -#define B_LC_IF_RAM_TRP_STKU__W 12 -#define B_LC_IF_RAM_TRP_STKU__M 0xFFF - -#define B_LC_IF_RAM_TRP_WARM__AX 0x2830006 -#define B_LC_IF_RAM_TRP_WARM__XSZ 2 -#define B_LC_IF_RAM_TRP_WARM__W 12 -#define B_LC_IF_RAM_TRP_WARM__M 0xFFF +#define B_EC_OC_RAM__A 0x2160000 + +#define B_CC_SID 0x1B + +#define B_CC_COMM_EXEC__A 0x2400000 +#define B_CC_COMM_EXEC__W 3 +#define B_CC_COMM_EXEC__M 0x7 +#define B_CC_COMM_EXEC_CTL__B 0 +#define B_CC_COMM_EXEC_CTL__W 3 +#define B_CC_COMM_EXEC_CTL__M 0x7 +#define B_CC_COMM_EXEC_CTL_STOP 0x0 +#define B_CC_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CC_COMM_EXEC_CTL_HOLD 0x2 +#define B_CC_COMM_EXEC_CTL_STEP 0x3 +#define B_CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_CC_COMM_STATE__A 0x2400001 +#define B_CC_COMM_STATE__W 16 +#define B_CC_COMM_STATE__M 0xFFFF +#define B_CC_COMM_MB__A 0x2400002 +#define B_CC_COMM_MB__W 16 +#define B_CC_COMM_MB__M 0xFFFF +#define B_CC_COMM_SERVICE0__A 0x2400003 +#define B_CC_COMM_SERVICE0__W 16 +#define B_CC_COMM_SERVICE0__M 0xFFFF +#define B_CC_COMM_SERVICE1__A 0x2400004 +#define B_CC_COMM_SERVICE1__W 16 +#define B_CC_COMM_SERVICE1__M 0xFFFF +#define B_CC_COMM_INT_STA__A 0x2400007 +#define B_CC_COMM_INT_STA__W 16 +#define B_CC_COMM_INT_STA__M 0xFFFF +#define B_CC_COMM_INT_MSK__A 0x2400008 +#define B_CC_COMM_INT_MSK__W 16 +#define B_CC_COMM_INT_MSK__M 0xFFFF + +#define B_CC_REG_COMM_EXEC__A 0x2410000 +#define B_CC_REG_COMM_EXEC__W 3 +#define B_CC_REG_COMM_EXEC__M 0x7 +#define B_CC_REG_COMM_EXEC_CTL__B 0 +#define B_CC_REG_COMM_EXEC_CTL__W 3 +#define B_CC_REG_COMM_EXEC_CTL__M 0x7 +#define B_CC_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_CC_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_CC_REG_COMM_EXEC_CTL_STEP 0x3 +#define B_CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_CC_REG_COMM_STATE__A 0x2410001 +#define B_CC_REG_COMM_STATE__W 16 +#define B_CC_REG_COMM_STATE__M 0xFFFF +#define B_CC_REG_COMM_MB__A 0x2410002 +#define B_CC_REG_COMM_MB__W 16 +#define B_CC_REG_COMM_MB__M 0xFFFF +#define B_CC_REG_COMM_SERVICE0__A 0x2410003 +#define B_CC_REG_COMM_SERVICE0__W 16 +#define B_CC_REG_COMM_SERVICE0__M 0xFFFF +#define B_CC_REG_COMM_SERVICE1__A 0x2410004 +#define B_CC_REG_COMM_SERVICE1__W 16 +#define B_CC_REG_COMM_SERVICE1__M 0xFFFF +#define B_CC_REG_COMM_INT_STA__A 0x2410007 +#define B_CC_REG_COMM_INT_STA__W 16 +#define B_CC_REG_COMM_INT_STA__M 0xFFFF +#define B_CC_REG_COMM_INT_MSK__A 0x2410008 +#define B_CC_REG_COMM_INT_MSK__W 16 +#define B_CC_REG_COMM_INT_MSK__M 0xFFFF + +#define B_CC_REG_OSC_MODE__A 0x2410010 +#define B_CC_REG_OSC_MODE__W 2 +#define B_CC_REG_OSC_MODE__M 0x3 +#define B_CC_REG_OSC_MODE_OHW 0x0 +#define B_CC_REG_OSC_MODE_M20 0x1 +#define B_CC_REG_OSC_MODE_M48 0x2 + +#define B_CC_REG_PLL_MODE__A 0x2410011 +#define B_CC_REG_PLL_MODE__W 6 +#define B_CC_REG_PLL_MODE__M 0x3F +#define B_CC_REG_PLL_MODE_INIT 0xC +#define B_CC_REG_PLL_MODE_BYPASS__B 0 +#define B_CC_REG_PLL_MODE_BYPASS__W 2 +#define B_CC_REG_PLL_MODE_BYPASS__M 0x3 +#define B_CC_REG_PLL_MODE_BYPASS_OHW 0x0 +#define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1 +#define B_CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 +#define B_CC_REG_PLL_MODE_PUMP__B 2 +#define B_CC_REG_PLL_MODE_PUMP__W 3 +#define B_CC_REG_PLL_MODE_PUMP__M 0x1C +#define B_CC_REG_PLL_MODE_PUMP_OFF 0x0 +#define B_CC_REG_PLL_MODE_PUMP_CUR_08 0x4 +#define B_CC_REG_PLL_MODE_PUMP_CUR_09 0x8 +#define B_CC_REG_PLL_MODE_PUMP_CUR_10 0xC +#define B_CC_REG_PLL_MODE_PUMP_CUR_11 0x10 +#define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14 +#define B_CC_REG_PLL_MODE_OUT_EN__B 5 +#define B_CC_REG_PLL_MODE_OUT_EN__W 1 +#define B_CC_REG_PLL_MODE_OUT_EN__M 0x20 +#define B_CC_REG_PLL_MODE_OUT_EN_OFF 0x0 +#define B_CC_REG_PLL_MODE_OUT_EN_ON 0x20 + +#define B_CC_REG_REF_DIVIDE__A 0x2410012 +#define B_CC_REG_REF_DIVIDE__W 4 +#define B_CC_REG_REF_DIVIDE__M 0xF +#define B_CC_REG_REF_DIVIDE_INIT 0xA +#define B_CC_REG_REF_DIVIDE_OHW 0x0 +#define B_CC_REG_REF_DIVIDE_D01 0x1 +#define B_CC_REG_REF_DIVIDE_D02 0x2 +#define B_CC_REG_REF_DIVIDE_D03 0x3 +#define B_CC_REG_REF_DIVIDE_D04 0x4 +#define B_CC_REG_REF_DIVIDE_D05 0x5 +#define B_CC_REG_REF_DIVIDE_D06 0x6 +#define B_CC_REG_REF_DIVIDE_D07 0x7 +#define B_CC_REG_REF_DIVIDE_D08 0x8 +#define B_CC_REG_REF_DIVIDE_D09 0x9 +#define B_CC_REG_REF_DIVIDE_D10 0xA + +#define B_CC_REG_REF_DELAY__A 0x2410013 +#define B_CC_REG_REF_DELAY__W 3 +#define B_CC_REG_REF_DELAY__M 0x7 +#define B_CC_REG_REF_DELAY_EDGE__B 0 +#define B_CC_REG_REF_DELAY_EDGE__W 1 +#define B_CC_REG_REF_DELAY_EDGE__M 0x1 +#define B_CC_REG_REF_DELAY_EDGE_POS 0x0 +#define B_CC_REG_REF_DELAY_EDGE_NEG 0x1 +#define B_CC_REG_REF_DELAY_DELAY__B 1 +#define B_CC_REG_REF_DELAY_DELAY__W 2 +#define B_CC_REG_REF_DELAY_DELAY__M 0x6 +#define B_CC_REG_REF_DELAY_DELAY_DEL_0 0x0 +#define B_CC_REG_REF_DELAY_DELAY_DEL_3 0x2 +#define B_CC_REG_REF_DELAY_DELAY_DEL_6 0x4 +#define B_CC_REG_REF_DELAY_DELAY_DEL_9 0x6 + +#define B_CC_REG_CLK_DELAY__A 0x2410014 +#define B_CC_REG_CLK_DELAY__W 5 +#define B_CC_REG_CLK_DELAY__M 0x1F +#define B_CC_REG_CLK_DELAY_DELAY__B 0 +#define B_CC_REG_CLK_DELAY_DELAY__W 4 +#define B_CC_REG_CLK_DELAY_DELAY__M 0xF +#define B_CC_REG_CLK_DELAY_DELAY_DEL_00 0x0 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_05 0x1 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_10 0x2 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_15 0x3 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_20 0x4 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_25 0x5 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_30 0x6 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_35 0x7 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_40 0x8 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_45 0x9 +#define B_CC_REG_CLK_DELAY_DELAY_DEL_50 0xA +#define B_CC_REG_CLK_DELAY_DELAY_DEL_55 0xB +#define B_CC_REG_CLK_DELAY_DELAY_DEL_60 0xC +#define B_CC_REG_CLK_DELAY_DELAY_DEL_65 0xD +#define B_CC_REG_CLK_DELAY_DELAY_DEL_70 0xE +#define B_CC_REG_CLK_DELAY_DELAY_DEL_75 0xF +#define B_CC_REG_CLK_DELAY_EDGE__B 4 +#define B_CC_REG_CLK_DELAY_EDGE__W 1 +#define B_CC_REG_CLK_DELAY_EDGE__M 0x10 +#define B_CC_REG_CLK_DELAY_EDGE_POS 0x0 +#define B_CC_REG_CLK_DELAY_EDGE_NEG 0x10 + +#define B_CC_REG_PWD_MODE__A 0x2410015 +#define B_CC_REG_PWD_MODE__W 2 +#define B_CC_REG_PWD_MODE__M 0x3 +#define B_CC_REG_PWD_MODE_UP 0x0 +#define B_CC_REG_PWD_MODE_DOWN_CLK 0x1 +#define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 +#define B_CC_REG_PWD_MODE_DOWN_OSC 0x3 + +#define B_CC_REG_SOFT_RST__A 0x2410016 +#define B_CC_REG_SOFT_RST__W 2 +#define B_CC_REG_SOFT_RST__M 0x3 +#define B_CC_REG_SOFT_RST_SYS__B 0 +#define B_CC_REG_SOFT_RST_SYS__W 1 +#define B_CC_REG_SOFT_RST_SYS__M 0x1 +#define B_CC_REG_SOFT_RST_OSC__B 1 +#define B_CC_REG_SOFT_RST_OSC__W 1 +#define B_CC_REG_SOFT_RST_OSC__M 0x2 + +#define B_CC_REG_UPDATE__A 0x2410017 +#define B_CC_REG_UPDATE__W 16 +#define B_CC_REG_UPDATE__M 0xFFFF +#define B_CC_REG_UPDATE_KEY 0x3973 + +#define B_CC_REG_PLL_LOCK__A 0x2410018 +#define B_CC_REG_PLL_LOCK__W 1 +#define B_CC_REG_PLL_LOCK__M 0x1 +#define B_CC_REG_PLL_LOCK_LOCK 0x1 + +#define B_CC_REG_JTAGID_L__A 0x2410019 +#define B_CC_REG_JTAGID_L__W 16 +#define B_CC_REG_JTAGID_L__M 0xFFFF +#define B_CC_REG_JTAGID_L_INIT 0x0 + +#define B_CC_REG_JTAGID_H__A 0x241001A +#define B_CC_REG_JTAGID_H__W 16 +#define B_CC_REG_JTAGID_H__M 0xFFFF +#define B_CC_REG_JTAGID_H_INIT 0x0 + +#define B_CC_REG_DIVERSITY__A 0x241001B +#define B_CC_REG_DIVERSITY__W 1 +#define B_CC_REG_DIVERSITY__M 0x1 +#define B_CC_REG_DIVERSITY_INIT 0x0 + +#define B_CC_REG_BACKUP3V__A 0x241001C +#define B_CC_REG_BACKUP3V__W 1 +#define B_CC_REG_BACKUP3V__M 0x1 +#define B_CC_REG_BACKUP3V_INIT 0x0 + +#define B_CC_REG_DRV_IO__A 0x241001D +#define B_CC_REG_DRV_IO__W 3 +#define B_CC_REG_DRV_IO__M 0x7 +#define B_CC_REG_DRV_IO_INIT 0x2 + +#define B_CC_REG_DRV_MPG__A 0x241001E +#define B_CC_REG_DRV_MPG__W 3 +#define B_CC_REG_DRV_MPG__M 0x7 +#define B_CC_REG_DRV_MPG_INIT 0x2 + +#define B_CC_REG_DRV_I2C1__A 0x241001F +#define B_CC_REG_DRV_I2C1__W 3 +#define B_CC_REG_DRV_I2C1__M 0x7 +#define B_CC_REG_DRV_I2C1_INIT 0x2 + +#define B_CC_REG_DRV_I2C2__A 0x2410020 +#define B_CC_REG_DRV_I2C2__W 1 +#define B_CC_REG_DRV_I2C2__M 0x1 +#define B_CC_REG_DRV_I2C2_INIT 0x0 + +#define B_LC_SID 0x1C + +#define B_LC_COMM_EXEC__A 0x2800000 +#define B_LC_COMM_EXEC__W 3 +#define B_LC_COMM_EXEC__M 0x7 +#define B_LC_COMM_EXEC_CTL__B 0 +#define B_LC_COMM_EXEC_CTL__W 3 +#define B_LC_COMM_EXEC_CTL__M 0x7 +#define B_LC_COMM_EXEC_CTL_STOP 0x0 +#define B_LC_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_LC_COMM_EXEC_CTL_HOLD 0x2 +#define B_LC_COMM_EXEC_CTL_STEP 0x3 +#define B_LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 +#define B_LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 + +#define B_LC_COMM_STATE__A 0x2800001 +#define B_LC_COMM_STATE__W 16 +#define B_LC_COMM_STATE__M 0xFFFF +#define B_LC_COMM_MB__A 0x2800002 +#define B_LC_COMM_MB__W 16 +#define B_LC_COMM_MB__M 0xFFFF +#define B_LC_COMM_SERVICE0__A 0x2800003 +#define B_LC_COMM_SERVICE0__W 16 +#define B_LC_COMM_SERVICE0__M 0xFFFF +#define B_LC_COMM_SERVICE1__A 0x2800004 +#define B_LC_COMM_SERVICE1__W 16 +#define B_LC_COMM_SERVICE1__M 0xFFFF +#define B_LC_COMM_INT_STA__A 0x2800007 +#define B_LC_COMM_INT_STA__W 16 +#define B_LC_COMM_INT_STA__M 0xFFFF +#define B_LC_COMM_INT_MSK__A 0x2800008 +#define B_LC_COMM_INT_MSK__W 16 +#define B_LC_COMM_INT_MSK__M 0xFFFF + +#define B_LC_CT_REG_COMM_EXEC__A 0x2810000 +#define B_LC_CT_REG_COMM_EXEC__W 3 +#define B_LC_CT_REG_COMM_EXEC__M 0x7 +#define B_LC_CT_REG_COMM_EXEC_CTL__B 0 +#define B_LC_CT_REG_COMM_EXEC_CTL__W 3 +#define B_LC_CT_REG_COMM_EXEC_CTL__M 0x7 +#define B_LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 +#define B_LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 +#define B_LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 +#define B_LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 + +#define B_LC_CT_REG_COMM_STATE__A 0x2810001 +#define B_LC_CT_REG_COMM_STATE__W 10 +#define B_LC_CT_REG_COMM_STATE__M 0x3FF +#define B_LC_CT_REG_COMM_SERVICE0__A 0x2810003 +#define B_LC_CT_REG_COMM_SERVICE0__W 16 +#define B_LC_CT_REG_COMM_SERVICE0__M 0xFFFF +#define B_LC_CT_REG_COMM_SERVICE1__A 0x2810004 +#define B_LC_CT_REG_COMM_SERVICE1__W 16 +#define B_LC_CT_REG_COMM_SERVICE1__M 0xFFFF +#define B_LC_CT_REG_COMM_SERVICE1_LC__B 12 +#define B_LC_CT_REG_COMM_SERVICE1_LC__W 1 +#define B_LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 + +#define B_LC_CT_REG_COMM_INT_STA__A 0x2810007 +#define B_LC_CT_REG_COMM_INT_STA__W 1 +#define B_LC_CT_REG_COMM_INT_STA__M 0x1 +#define B_LC_CT_REG_COMM_INT_STA_REQUEST__B 0 +#define B_LC_CT_REG_COMM_INT_STA_REQUEST__W 1 +#define B_LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 + +#define B_LC_CT_REG_COMM_INT_MSK__A 0x2810008 +#define B_LC_CT_REG_COMM_INT_MSK__W 1 +#define B_LC_CT_REG_COMM_INT_MSK__M 0x1 +#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 +#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 +#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 + +#define B_LC_CT_REG_CTL_STK__AX 0x2810010 +#define B_LC_CT_REG_CTL_STK__XSZ 4 +#define B_LC_CT_REG_CTL_STK__W 10 +#define B_LC_CT_REG_CTL_STK__M 0x3FF + +#define B_LC_CT_REG_CTL_BPT_IDX__A 0x281001F +#define B_LC_CT_REG_CTL_BPT_IDX__W 1 +#define B_LC_CT_REG_CTL_BPT_IDX__M 0x1 + +#define B_LC_CT_REG_CTL_BPT__A 0x2810020 +#define B_LC_CT_REG_CTL_BPT__W 10 +#define B_LC_CT_REG_CTL_BPT__M 0x3FF + +#define B_LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 +#define B_LC_RA_RAM_PROC_DELAY_IF__W 16 +#define B_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF +#define B_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 +#define B_LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 +#define B_LC_RA_RAM_PROC_DELAY_FS__W 16 +#define B_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF +#define B_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 +#define B_LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 +#define B_LC_RA_RAM_LOCK_TH_CRMM__W 16 +#define B_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF +#define B_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 +#define B_LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 +#define B_LC_RA_RAM_LOCK_TH_SRMM__W 16 +#define B_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF +#define B_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 +#define B_LC_RA_RAM_LOCK_COUNT__A 0x282000A +#define B_LC_RA_RAM_LOCK_COUNT__W 16 +#define B_LC_RA_RAM_LOCK_COUNT__M 0xFFFF +#define B_LC_RA_RAM_CPRTOFS_NOM__A 0x282000B +#define B_LC_RA_RAM_CPRTOFS_NOM__W 16 +#define B_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF +#define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C +#define B_LC_RA_RAM_IFINCR_NOM_L__W 16 +#define B_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF +#define B_LC_RA_RAM_IFINCR_NOM_H__A 0x282000D +#define B_LC_RA_RAM_IFINCR_NOM_H__W 16 +#define B_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF +#define B_LC_RA_RAM_FSINCR_NOM_L__A 0x282000E +#define B_LC_RA_RAM_FSINCR_NOM_L__W 16 +#define B_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF +#define B_LC_RA_RAM_FSINCR_NOM_H__A 0x282000F +#define B_LC_RA_RAM_FSINCR_NOM_H__W 16 +#define B_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF +#define B_LC_RA_RAM_MODE_2K__A 0x2820010 +#define B_LC_RA_RAM_MODE_2K__W 16 +#define B_LC_RA_RAM_MODE_2K__M 0xFFFF +#define B_LC_RA_RAM_MODE_GUARD__A 0x2820011 +#define B_LC_RA_RAM_MODE_GUARD__W 16 +#define B_LC_RA_RAM_MODE_GUARD__M 0xFFFF +#define B_LC_RA_RAM_MODE_GUARD_32 0x0 +#define B_LC_RA_RAM_MODE_GUARD_16 0x1 +#define B_LC_RA_RAM_MODE_GUARD_8 0x2 +#define B_LC_RA_RAM_MODE_GUARD_4 0x3 + +#define B_LC_RA_RAM_MODE_ADJUST__A 0x2820012 +#define B_LC_RA_RAM_MODE_ADJUST__W 16 +#define B_LC_RA_RAM_MODE_ADJUST__M 0xFFFF +#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 +#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 +#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 +#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 +#define B_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 +#define B_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 +#define B_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 +#define B_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 +#define B_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 +#define B_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 +#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 +#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 +#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 +#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 +#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 +#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 +#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 +#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 +#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 +#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 +#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 + +#define B_LC_RA_RAM_RC_STS__A 0x2820014 +#define B_LC_RA_RAM_RC_STS__W 16 +#define B_LC_RA_RAM_RC_STS__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x2820018 +#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 +#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x2820019 +#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 +#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A +#define B_LC_RA_RAM_FILTER_SYM_SET__W 16 +#define B_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 +#define B_LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B +#define B_LC_RA_RAM_FILTER_SYM_CUR__W 16 +#define B_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 +#define B_LC_RA_RAM_DIVERSITY_DELAY__A 0x282001C +#define B_LC_RA_RAM_DIVERSITY_DELAY__W 16 +#define B_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF +#define B_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 +#define B_LC_RA_RAM_MAX_ABS_EXP__A 0x282001D +#define B_LC_RA_RAM_MAX_ABS_EXP__W 16 +#define B_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF +#define B_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 +#define B_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F +#define B_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 +#define B_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 +#define B_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 +#define B_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 +#define B_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 +#define B_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 +#define B_LC_RA_RAM_ACTUAL_PHASE__W 16 +#define B_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF +#define B_LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 +#define B_LC_RA_RAM_ACTUAL_DELAY__W 16 +#define B_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF +#define B_LC_RA_RAM_ADJUST_CRMM__A 0x2820024 +#define B_LC_RA_RAM_ADJUST_CRMM__W 16 +#define B_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF +#define B_LC_RA_RAM_ADJUST_SRMM__A 0x2820025 +#define B_LC_RA_RAM_ADJUST_SRMM__W 16 +#define B_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF +#define B_LC_RA_RAM_ADJUST_PHASE__A 0x2820026 +#define B_LC_RA_RAM_ADJUST_PHASE__W 16 +#define B_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF +#define B_LC_RA_RAM_ADJUST_DELAY__A 0x2820027 +#define B_LC_RA_RAM_ADJUST_DELAY__W 16 +#define B_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF + +#define B_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 +#define B_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 +#define B_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A +#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B +#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C +#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D +#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 +#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF + +#define B_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 +#define B_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 +#define B_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 +#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 +#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 +#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 +#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 +#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF + +#define B_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 +#define B_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 +#define B_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A +#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B +#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C +#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF +#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D +#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 +#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF + +#define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 +#define B_LC_RA_RAM_FILTER_CRMM_A__W 16 +#define B_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF +#define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 +#define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 +#define B_LC_RA_RAM_FILTER_CRMM_B__W 16 +#define B_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF +#define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 +#define B_LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 +#define B_LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 +#define B_LC_RA_RAM_FILTER_CRMM_Z1__W 16 +#define B_LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF +#define B_LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 +#define B_LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 +#define B_LC_RA_RAM_FILTER_CRMM_Z2__W 16 +#define B_LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF +#define B_LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 +#define B_LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 +#define B_LC_RA_RAM_FILTER_CRMM_TMP__W 16 +#define B_LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF + +#define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 +#define B_LC_RA_RAM_FILTER_SRMM_A__W 16 +#define B_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 +#define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 +#define B_LC_RA_RAM_FILTER_SRMM_B__W 16 +#define B_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 +#define B_LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A +#define B_LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 +#define B_LC_RA_RAM_FILTER_SRMM_Z1__W 16 +#define B_LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C +#define B_LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 +#define B_LC_RA_RAM_FILTER_SRMM_Z2__W 16 +#define B_LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF +#define B_LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E +#define B_LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 +#define B_LC_RA_RAM_FILTER_SRMM_TMP__W 16 +#define B_LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF + +#define B_LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 +#define B_LC_RA_RAM_FILTER_PHASE_A__W 16 +#define B_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF +#define B_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 +#define B_LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 +#define B_LC_RA_RAM_FILTER_PHASE_B__W 16 +#define B_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF +#define B_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 +#define B_LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 +#define B_LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 +#define B_LC_RA_RAM_FILTER_PHASE_Z1__W 16 +#define B_LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF +#define B_LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 +#define B_LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 +#define B_LC_RA_RAM_FILTER_PHASE_Z2__W 16 +#define B_LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF +#define B_LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 +#define B_LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 +#define B_LC_RA_RAM_FILTER_PHASE_TMP__W 16 +#define B_LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF + +#define B_LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 +#define B_LC_RA_RAM_FILTER_DELAY_A__W 16 +#define B_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF +#define B_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 +#define B_LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 +#define B_LC_RA_RAM_FILTER_DELAY_B__W 16 +#define B_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF +#define B_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 +#define B_LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A +#define B_LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 +#define B_LC_RA_RAM_FILTER_DELAY_Z1__W 16 +#define B_LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF +#define B_LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C +#define B_LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 +#define B_LC_RA_RAM_FILTER_DELAY_Z2__W 16 +#define B_LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF +#define B_LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E +#define B_LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 +#define B_LC_RA_RAM_FILTER_DELAY_TMP__W 16 +#define B_LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF + +#define B_LC_IF_RAM_TRP_BPT0__AX 0x2830000 +#define B_LC_IF_RAM_TRP_BPT0__XSZ 2 +#define B_LC_IF_RAM_TRP_BPT0__W 12 +#define B_LC_IF_RAM_TRP_BPT0__M 0xFFF + +#define B_LC_IF_RAM_TRP_STKU__AX 0x2830002 +#define B_LC_IF_RAM_TRP_STKU__XSZ 2 +#define B_LC_IF_RAM_TRP_STKU__W 12 +#define B_LC_IF_RAM_TRP_STKU__M 0xFFF + +#define B_LC_IF_RAM_TRP_WARM__AX 0x2830006 +#define B_LC_IF_RAM_TRP_WARM__XSZ 2 +#define B_LC_IF_RAM_TRP_WARM__W 12 +#define B_LC_IF_RAM_TRP_WARM__M 0xFFF #endif -- cgit v1.2.3 From 935c630c2cf402419342d66acd04804da8c0704a Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab <mchehab@redhat.com> Date: Fri, 25 Mar 2011 10:21:31 -0300 Subject: [media] drxd_map_firm.h: Remove unused lines This file is big. It has 12000+ lines! Most of the defined stuff aren't used anyware inside the driver, so we can just remove most of the lines and still keep everything that have any interest for the driver. If anyone ever need the other devices, it will be stored at git logs, so it is easy to recover. The diff result is impressive: 1 files changed, 1013 insertions(+), 12694 deletions(-) rewrite drivers/media/dvb/frontends/drxd_map_firm.h (90%) As a sideback effect, drxd driver will likely compile faster, and checkpatch.pl can run on this file without taking (literally) hours. The code cleanup was done using this small script: $ for i in `perl -ne 'print "$1\n" if (m/define\s+([^\s+]+)/)' drxd_map_firm.h`; do if [ "`grep $i drivers/media/dvb/frontends/drxd*.[ch]`" != "" ] ; then echo $i; fi; done|sort|uniq >used_symbols $ grep -f used_symbols drxd_map_firm.h >defines And then deleting the old #define lines, replacing by "defines" file content. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd_map_firm.h | 11725 +------------------------- 1 file changed, 22 insertions(+), 11703 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd_map_firm.h b/drivers/media/dvb/frontends/drxd_map_firm.h index 160323a4f932..6bc553abf215 100644 --- a/drivers/media/dvb/frontends/drxd_map_firm.h +++ b/drivers/media/dvb/frontends/drxd_map_firm.h @@ -24,12671 +24,990 @@ #ifndef __DRX3973D_MAP__H__ #define __DRX3973D_MAP__H__ -#define HI_SID 0x10 +/* + * Note: originally, this file contained 12000+ lines of data + * Probably a few lines for every firwmare assembler instruction. However, + * only a few defines were actually used. So, removed all uneeded lines. + * If ever needed, the other lines can be easily obtained via git history. + */ #define HI_COMM_EXEC__A 0x400000 -#define HI_COMM_EXEC__W 3 -#define HI_COMM_EXEC__M 0x7 -#define HI_COMM_EXEC_CTL__B 0 -#define HI_COMM_EXEC_CTL__W 3 -#define HI_COMM_EXEC_CTL__M 0x7 -#define HI_COMM_EXEC_CTL_STOP 0x0 -#define HI_COMM_EXEC_CTL_ACTIVE 0x1 -#define HI_COMM_EXEC_CTL_HOLD 0x2 -#define HI_COMM_EXEC_CTL_STEP 0x3 -#define HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define HI_COMM_STATE__A 0x400001 -#define HI_COMM_STATE__W 16 -#define HI_COMM_STATE__M 0xFFFF #define HI_COMM_MB__A 0x400002 -#define HI_COMM_MB__W 16 -#define HI_COMM_MB__M 0xFFFF -#define HI_COMM_SERVICE0__A 0x400003 -#define HI_COMM_SERVICE0__W 16 -#define HI_COMM_SERVICE0__M 0xFFFF -#define HI_COMM_SERVICE1__A 0x400004 -#define HI_COMM_SERVICE1__W 16 -#define HI_COMM_SERVICE1__M 0xFFFF -#define HI_COMM_INT_STA__A 0x400007 -#define HI_COMM_INT_STA__W 16 -#define HI_COMM_INT_STA__M 0xFFFF -#define HI_COMM_INT_MSK__A 0x400008 -#define HI_COMM_INT_MSK__W 16 -#define HI_COMM_INT_MSK__M 0xFFFF - -#define HI_CT_REG_COMM_EXEC__A 0x410000 -#define HI_CT_REG_COMM_EXEC__W 3 -#define HI_CT_REG_COMM_EXEC__M 0x7 -#define HI_CT_REG_COMM_EXEC_CTL__B 0 -#define HI_CT_REG_COMM_EXEC_CTL__W 3 -#define HI_CT_REG_COMM_EXEC_CTL__M 0x7 -#define HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 - #define HI_CT_REG_COMM_STATE__A 0x410001 -#define HI_CT_REG_COMM_STATE__W 10 -#define HI_CT_REG_COMM_STATE__M 0x3FF -#define HI_CT_REG_COMM_SERVICE0__A 0x410003 -#define HI_CT_REG_COMM_SERVICE0__W 16 -#define HI_CT_REG_COMM_SERVICE0__M 0xFFFF -#define HI_CT_REG_COMM_SERVICE1__A 0x410004 -#define HI_CT_REG_COMM_SERVICE1__W 16 -#define HI_CT_REG_COMM_SERVICE1__M 0xFFFF -#define HI_CT_REG_COMM_SERVICE1_HI__B 0 -#define HI_CT_REG_COMM_SERVICE1_HI__W 1 -#define HI_CT_REG_COMM_SERVICE1_HI__M 0x1 - -#define HI_CT_REG_COMM_INT_STA__A 0x410007 -#define HI_CT_REG_COMM_INT_STA__W 1 -#define HI_CT_REG_COMM_INT_STA__M 0x1 -#define HI_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define HI_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define HI_CT_REG_COMM_INT_MSK__A 0x410008 -#define HI_CT_REG_COMM_INT_MSK__W 1 -#define HI_CT_REG_COMM_INT_MSK__M 0x1 -#define HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define HI_CT_REG_CTL_STK__AX 0x410010 -#define HI_CT_REG_CTL_STK__XSZ 4 -#define HI_CT_REG_CTL_STK__W 10 -#define HI_CT_REG_CTL_STK__M 0x3FF - -#define HI_CT_REG_CTL_BPT_IDX__A 0x41001F -#define HI_CT_REG_CTL_BPT_IDX__W 1 -#define HI_CT_REG_CTL_BPT_IDX__M 0x1 - -#define HI_CT_REG_CTL_BPT__A 0x410020 -#define HI_CT_REG_CTL_BPT__W 10 -#define HI_CT_REG_CTL_BPT__M 0x3FF - -#define HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 -#define HI_RA_RAM_SLV0_FLG_SMM__W 1 -#define HI_RA_RAM_SLV0_FLG_SMM__M 0x1 -#define HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 -#define HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 - -#define HI_RA_RAM_SLV0_DEV_ID__A 0x420011 -#define HI_RA_RAM_SLV0_DEV_ID__W 7 -#define HI_RA_RAM_SLV0_DEV_ID__M 0x7F - -#define HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 -#define HI_RA_RAM_SLV0_FLG_CRC__W 1 -#define HI_RA_RAM_SLV0_FLG_CRC__M 0x1 -#define HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 -#define HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 - -#define HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 -#define HI_RA_RAM_SLV0_FLG_ACC__W 3 -#define HI_RA_RAM_SLV0_FLG_ACC__M 0x7 -#define HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 -#define HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 -#define HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 -#define HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 -#define HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 -#define HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 -#define HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 -#define HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 -#define HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 -#define HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 - -#define HI_RA_RAM_SLV0_STATE__A 0x420014 -#define HI_RA_RAM_SLV0_STATE__W 1 -#define HI_RA_RAM_SLV0_STATE__M 0x1 -#define HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 -#define HI_RA_RAM_SLV0_STATE_DATA 0x1 - -#define HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 -#define HI_RA_RAM_SLV0_BLK_BNK__W 12 -#define HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF -#define HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 -#define HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 -#define HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F -#define HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 -#define HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 -#define HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 - -#define HI_RA_RAM_SLV0_ADDR__A 0x420016 -#define HI_RA_RAM_SLV0_ADDR__W 16 -#define HI_RA_RAM_SLV0_ADDR__M 0xFFFF - -#define HI_RA_RAM_SLV0_CRC__A 0x420017 -#define HI_RA_RAM_SLV0_CRC__W 16 -#define HI_RA_RAM_SLV0_CRC__M 0xFFFF - -#define HI_RA_RAM_SLV0_READBACK__A 0x420018 -#define HI_RA_RAM_SLV0_READBACK__W 16 -#define HI_RA_RAM_SLV0_READBACK__M 0xFFFF - -#define HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 -#define HI_RA_RAM_SLV1_FLG_SMM__W 1 -#define HI_RA_RAM_SLV1_FLG_SMM__M 0x1 -#define HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 -#define HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 - -#define HI_RA_RAM_SLV1_DEV_ID__A 0x420021 -#define HI_RA_RAM_SLV1_DEV_ID__W 7 -#define HI_RA_RAM_SLV1_DEV_ID__M 0x7F - -#define HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 -#define HI_RA_RAM_SLV1_FLG_CRC__W 1 -#define HI_RA_RAM_SLV1_FLG_CRC__M 0x1 -#define HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 -#define HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 - -#define HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 -#define HI_RA_RAM_SLV1_FLG_ACC__W 3 -#define HI_RA_RAM_SLV1_FLG_ACC__M 0x7 -#define HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 -#define HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 -#define HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 -#define HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 -#define HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 -#define HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 -#define HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 -#define HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 -#define HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 -#define HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 - -#define HI_RA_RAM_SLV1_STATE__A 0x420024 -#define HI_RA_RAM_SLV1_STATE__W 1 -#define HI_RA_RAM_SLV1_STATE__M 0x1 -#define HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 -#define HI_RA_RAM_SLV1_STATE_DATA 0x1 - -#define HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 -#define HI_RA_RAM_SLV1_BLK_BNK__W 12 -#define HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF -#define HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 -#define HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 -#define HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F -#define HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 -#define HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 -#define HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 - -#define HI_RA_RAM_SLV1_ADDR__A 0x420026 -#define HI_RA_RAM_SLV1_ADDR__W 16 -#define HI_RA_RAM_SLV1_ADDR__M 0xFFFF - -#define HI_RA_RAM_SLV1_CRC__A 0x420027 -#define HI_RA_RAM_SLV1_CRC__W 16 -#define HI_RA_RAM_SLV1_CRC__M 0xFFFF - -#define HI_RA_RAM_SLV1_READBACK__A 0x420028 -#define HI_RA_RAM_SLV1_READBACK__W 16 -#define HI_RA_RAM_SLV1_READBACK__M 0xFFFF - -#define HI_RA_RAM_SRV_SEM__A 0x420030 -#define HI_RA_RAM_SRV_SEM__W 1 -#define HI_RA_RAM_SRV_SEM__M 0x1 -#define HI_RA_RAM_SRV_SEM_FREE 0x0 -#define HI_RA_RAM_SRV_SEM_CLAIMED 0x1 - #define HI_RA_RAM_SRV_RES__A 0x420031 -#define HI_RA_RAM_SRV_RES__W 3 -#define HI_RA_RAM_SRV_RES__M 0x7 -#define HI_RA_RAM_SRV_RES_OK 0x0 -#define HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 -#define HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 -#define HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 -#define HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 - #define HI_RA_RAM_SRV_CMD__A 0x420032 -#define HI_RA_RAM_SRV_CMD__W 3 -#define HI_RA_RAM_SRV_CMD__M 0x7 -#define HI_RA_RAM_SRV_CMD_NULL 0x0 -#define HI_RA_RAM_SRV_CMD_UIO 0x1 #define HI_RA_RAM_SRV_CMD_RESET 0x2 #define HI_RA_RAM_SRV_CMD_CONFIG 0x3 -#define HI_RA_RAM_SRV_CMD_COPY 0x4 -#define HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 - -#define HI_RA_RAM_SRV_PAR__AX 0x420033 -#define HI_RA_RAM_SRV_PAR__XSZ 5 -#define HI_RA_RAM_SRV_PAR__W 16 -#define HI_RA_RAM_SRV_PAR__M 0xFFFF - -#define HI_RA_RAM_SRV_NOP_RES__A 0x420031 -#define HI_RA_RAM_SRV_NOP_RES__W 3 -#define HI_RA_RAM_SRV_NOP_RES__M 0x7 -#define HI_RA_RAM_SRV_NOP_RES_OK 0x0 -#define HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 - -#define HI_RA_RAM_SRV_UIO_RES__A 0x420031 -#define HI_RA_RAM_SRV_UIO_RES__W 3 -#define HI_RA_RAM_SRV_UIO_RES__M 0x7 -#define HI_RA_RAM_SRV_UIO_RES_LO 0x0 -#define HI_RA_RAM_SRV_UIO_RES_HI 0x1 - -#define HI_RA_RAM_SRV_UIO_KEY__A 0x420033 -#define HI_RA_RAM_SRV_UIO_KEY__W 16 -#define HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF -#define HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 - -#define HI_RA_RAM_SRV_UIO_SEL__A 0x420034 -#define HI_RA_RAM_SRV_UIO_SEL__W 2 -#define HI_RA_RAM_SRV_UIO_SEL__M 0x3 -#define HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 -#define HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 - -#define HI_RA_RAM_SRV_UIO_SET__A 0x420035 -#define HI_RA_RAM_SRV_UIO_SET__W 2 -#define HI_RA_RAM_SRV_UIO_SET__M 0x3 -#define HI_RA_RAM_SRV_UIO_SET_OUT__B 0 -#define HI_RA_RAM_SRV_UIO_SET_OUT__W 1 -#define HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 -#define HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 -#define HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 -#define HI_RA_RAM_SRV_UIO_SET_DIR__B 1 -#define HI_RA_RAM_SRV_UIO_SET_DIR__W 1 -#define HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 -#define HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 -#define HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 - -#define HI_RA_RAM_SRV_RST_RES__A 0x420031 -#define HI_RA_RAM_SRV_RST_RES__W 1 -#define HI_RA_RAM_SRV_RST_RES__M 0x1 -#define HI_RA_RAM_SRV_RST_RES_OK 0x0 -#define HI_RA_RAM_SRV_RST_RES_ERROR 0x1 - #define HI_RA_RAM_SRV_RST_KEY__A 0x420033 -#define HI_RA_RAM_SRV_RST_KEY__W 16 -#define HI_RA_RAM_SRV_RST_KEY__M 0xFFFF #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 - -#define HI_RA_RAM_SRV_CFG_RES__A 0x420031 -#define HI_RA_RAM_SRV_CFG_RES__W 1 -#define HI_RA_RAM_SRV_CFG_RES__M 0x1 -#define HI_RA_RAM_SRV_CFG_RES_OK 0x0 -#define HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 - #define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 -#define HI_RA_RAM_SRV_CFG_KEY__W 16 -#define HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF -#define HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 - #define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 -#define HI_RA_RAM_SRV_CFG_DIV__W 5 -#define HI_RA_RAM_SRV_CFG_DIV__M 0x1F - #define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 -#define HI_RA_RAM_SRV_CFG_BDL__W 6 -#define HI_RA_RAM_SRV_CFG_BDL__M 0x3F - #define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 -#define HI_RA_RAM_SRV_CFG_WUP__W 8 -#define HI_RA_RAM_SRV_CFG_WUP__M 0xFF - #define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 -#define HI_RA_RAM_SRV_CFG_ACT__W 4 -#define HI_RA_RAM_SRV_CFG_ACT__M 0xF -#define HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 -#define HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 -#define HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 -#define HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 #define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 -#define HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 -#define HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 -#define HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 -#define HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 -#define HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 -#define HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 -#define HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 #define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 #define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 #define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 -#define HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 -#define HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 -#define HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 -#define HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 #define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 - -#define HI_RA_RAM_SRV_CPY_RES__A 0x420031 -#define HI_RA_RAM_SRV_CPY_RES__W 1 -#define HI_RA_RAM_SRV_CPY_RES__M 0x1 -#define HI_RA_RAM_SRV_CPY_RES_OK 0x0 -#define HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 - -#define HI_RA_RAM_SRV_CPY_SBB__A 0x420033 -#define HI_RA_RAM_SRV_CPY_SBB__W 12 -#define HI_RA_RAM_SRV_CPY_SBB__M 0xFFF -#define HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 -#define HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 -#define HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F -#define HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 -#define HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 -#define HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 - -#define HI_RA_RAM_SRV_CPY_SAD__A 0x420034 -#define HI_RA_RAM_SRV_CPY_SAD__W 16 -#define HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF - -#define HI_RA_RAM_SRV_CPY_LEN__A 0x420035 -#define HI_RA_RAM_SRV_CPY_LEN__W 16 -#define HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF - -#define HI_RA_RAM_SRV_CPY_DBB__A 0x420033 -#define HI_RA_RAM_SRV_CPY_DBB__W 12 -#define HI_RA_RAM_SRV_CPY_DBB__M 0xFFF -#define HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 -#define HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 -#define HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F -#define HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 -#define HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 -#define HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 - -#define HI_RA_RAM_SRV_CPY_DAD__A 0x420034 -#define HI_RA_RAM_SRV_CPY_DAD__W 16 -#define HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF - -#define HI_RA_RAM_SRV_TRM_RES__A 0x420031 -#define HI_RA_RAM_SRV_TRM_RES__W 2 -#define HI_RA_RAM_SRV_TRM_RES__M 0x3 -#define HI_RA_RAM_SRV_TRM_RES_OK 0x0 -#define HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 -#define HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 - -#define HI_RA_RAM_SRV_TRM_MST__A 0x420033 -#define HI_RA_RAM_SRV_TRM_MST__W 12 -#define HI_RA_RAM_SRV_TRM_MST__M 0xFFF - -#define HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 -#define HI_RA_RAM_SRV_TRM_SEQ__W 7 -#define HI_RA_RAM_SRV_TRM_SEQ__M 0x7F - -#define HI_RA_RAM_SRV_TRM_TRM__A 0x420035 -#define HI_RA_RAM_SRV_TRM_TRM__W 15 -#define HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF -#define HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 -#define HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 -#define HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF - -#define HI_RA_RAM_SRV_TRM_DBB__A 0x420033 -#define HI_RA_RAM_SRV_TRM_DBB__W 12 -#define HI_RA_RAM_SRV_TRM_DBB__M 0xFFF -#define HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 -#define HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 -#define HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F -#define HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 -#define HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 -#define HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 - -#define HI_RA_RAM_SRV_TRM_DAD__A 0x420034 -#define HI_RA_RAM_SRV_TRM_DAD__W 16 -#define HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF - #define HI_RA_RAM_USR_BEGIN__A 0x420040 -#define HI_RA_RAM_USR_BEGIN__W 16 -#define HI_RA_RAM_USR_BEGIN__M 0xFFFF - -#define HI_RA_RAM_USR_END__A 0x42007F -#define HI_RA_RAM_USR_END__W 16 -#define HI_RA_RAM_USR_END__M 0xFFFF - #define HI_IF_RAM_TRP_BPT0__AX 0x430000 -#define HI_IF_RAM_TRP_BPT0__XSZ 2 -#define HI_IF_RAM_TRP_BPT0__W 12 -#define HI_IF_RAM_TRP_BPT0__M 0xFFF - -#define HI_IF_RAM_TRP_STKU__AX 0x430002 -#define HI_IF_RAM_TRP_STKU__XSZ 2 -#define HI_IF_RAM_TRP_STKU__W 12 -#define HI_IF_RAM_TRP_STKU__M 0xFFF - #define HI_IF_RAM_USR_BEGIN__A 0x430200 -#define HI_IF_RAM_USR_BEGIN__W 12 -#define HI_IF_RAM_USR_BEGIN__M 0xFFF - -#define HI_IF_RAM_USR_END__A 0x4303FF -#define HI_IF_RAM_USR_END__W 12 -#define HI_IF_RAM_USR_END__M 0xFFF - -#define SC_SID 0x11 - #define SC_COMM_EXEC__A 0x800000 -#define SC_COMM_EXEC__W 3 -#define SC_COMM_EXEC__M 0x7 -#define SC_COMM_EXEC_CTL__B 0 -#define SC_COMM_EXEC_CTL__W 3 -#define SC_COMM_EXEC_CTL__M 0x7 #define SC_COMM_EXEC_CTL_STOP 0x0 -#define SC_COMM_EXEC_CTL_ACTIVE 0x1 -#define SC_COMM_EXEC_CTL_HOLD 0x2 -#define SC_COMM_EXEC_CTL_STEP 0x3 -#define SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - #define SC_COMM_STATE__A 0x800001 -#define SC_COMM_STATE__W 16 -#define SC_COMM_STATE__M 0xFFFF -#define SC_COMM_MB__A 0x800002 -#define SC_COMM_MB__W 16 -#define SC_COMM_MB__M 0xFFFF -#define SC_COMM_SERVICE0__A 0x800003 -#define SC_COMM_SERVICE0__W 16 -#define SC_COMM_SERVICE0__M 0xFFFF -#define SC_COMM_SERVICE1__A 0x800004 -#define SC_COMM_SERVICE1__W 16 -#define SC_COMM_SERVICE1__M 0xFFFF -#define SC_COMM_INT_STA__A 0x800007 -#define SC_COMM_INT_STA__W 16 -#define SC_COMM_INT_STA__M 0xFFFF -#define SC_COMM_INT_MSK__A 0x800008 -#define SC_COMM_INT_MSK__W 16 -#define SC_COMM_INT_MSK__M 0xFFFF - -#define SC_CT_REG_COMM_EXEC__A 0x810000 -#define SC_CT_REG_COMM_EXEC__W 3 -#define SC_CT_REG_COMM_EXEC__M 0x7 -#define SC_CT_REG_COMM_EXEC_CTL__B 0 -#define SC_CT_REG_COMM_EXEC_CTL__W 3 -#define SC_CT_REG_COMM_EXEC_CTL__M 0x7 -#define SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define SC_CT_REG_COMM_STATE__A 0x810001 -#define SC_CT_REG_COMM_STATE__W 10 -#define SC_CT_REG_COMM_STATE__M 0x3FF -#define SC_CT_REG_COMM_SERVICE0__A 0x810003 -#define SC_CT_REG_COMM_SERVICE0__W 16 -#define SC_CT_REG_COMM_SERVICE0__M 0xFFFF -#define SC_CT_REG_COMM_SERVICE1__A 0x810004 -#define SC_CT_REG_COMM_SERVICE1__W 16 -#define SC_CT_REG_COMM_SERVICE1__M 0xFFFF -#define SC_CT_REG_COMM_SERVICE1_SC__B 1 -#define SC_CT_REG_COMM_SERVICE1_SC__W 1 -#define SC_CT_REG_COMM_SERVICE1_SC__M 0x2 - -#define SC_CT_REG_COMM_INT_STA__A 0x810007 -#define SC_CT_REG_COMM_INT_STA__W 1 -#define SC_CT_REG_COMM_INT_STA__M 0x1 -#define SC_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define SC_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define SC_CT_REG_COMM_INT_MSK__A 0x810008 -#define SC_CT_REG_COMM_INT_MSK__W 1 -#define SC_CT_REG_COMM_INT_MSK__M 0x1 -#define SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define SC_CT_REG_CTL_STK__AX 0x810010 -#define SC_CT_REG_CTL_STK__XSZ 4 -#define SC_CT_REG_CTL_STK__W 10 -#define SC_CT_REG_CTL_STK__M 0x3FF - -#define SC_CT_REG_CTL_BPT_IDX__A 0x81001F -#define SC_CT_REG_CTL_BPT_IDX__W 1 -#define SC_CT_REG_CTL_BPT_IDX__M 0x1 - -#define SC_CT_REG_CTL_BPT__A 0x810020 -#define SC_CT_REG_CTL_BPT__W 10 -#define SC_CT_REG_CTL_BPT__M 0x3FF - #define SC_RA_RAM_PARAM0__A 0x820040 -#define SC_RA_RAM_PARAM0__W 16 -#define SC_RA_RAM_PARAM0__M 0xFFFF #define SC_RA_RAM_PARAM1__A 0x820041 -#define SC_RA_RAM_PARAM1__W 16 -#define SC_RA_RAM_PARAM1__M 0xFFFF #define SC_RA_RAM_CMD_ADDR__A 0x820042 -#define SC_RA_RAM_CMD_ADDR__W 16 -#define SC_RA_RAM_CMD_ADDR__M 0xFFFF #define SC_RA_RAM_CMD__A 0x820043 -#define SC_RA_RAM_CMD__W 16 -#define SC_RA_RAM_CMD__M 0xFFFF -#define SC_RA_RAM_CMD_NULL 0x0 #define SC_RA_RAM_CMD_PROC_START 0x1 -#define SC_RA_RAM_CMD_PROC_TRIGGER 0x2 #define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 -#define SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 #define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 -#define SC_RA_RAM_CMD_USER_IO 0x6 -#define SC_RA_RAM_CMD_SET_TIMER 0x7 -#define SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 -#define SC_RA_RAM_CMD_MAX 0x8 -#define SC_RA_RAM_CMDBLOCK__C 0x4 - -#define SC_RA_RAM_PROC_ACTIVATE__A 0x820044 -#define SC_RA_RAM_PROC_ACTIVATE__W 16 -#define SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF -#define SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF -#define SC_RA_RAM_PROC_TERMINATED__A 0x820045 -#define SC_RA_RAM_PROC_TERMINATED__W 16 -#define SC_RA_RAM_PROC_TERMINATED__M 0xFFFF -#define SC_RA_RAM_SW_EVENT__A 0x820046 -#define SC_RA_RAM_SW_EVENT__W 14 -#define SC_RA_RAM_SW_EVENT__M 0x3FFF -#define SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 -#define SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 #define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 -#define SC_RA_RAM_SW_EVENT_RUN__B 1 -#define SC_RA_RAM_SW_EVENT_RUN__W 1 -#define SC_RA_RAM_SW_EVENT_RUN__M 0x2 -#define SC_RA_RAM_SW_EVENT_TERMINATE__B 2 -#define SC_RA_RAM_SW_EVENT_TERMINATE__W 1 -#define SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 -#define SC_RA_RAM_SW_EVENT_FT_START__B 3 -#define SC_RA_RAM_SW_EVENT_FT_START__W 1 -#define SC_RA_RAM_SW_EVENT_FT_START__M 0x8 -#define SC_RA_RAM_SW_EVENT_FI_START__B 4 -#define SC_RA_RAM_SW_EVENT_FI_START__W 1 -#define SC_RA_RAM_SW_EVENT_FI_START__M 0x10 -#define SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 -#define SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 -#define SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 -#define SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 -#define SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 -#define SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 -#define SC_RA_RAM_SW_EVENT_CE_IR__B 7 -#define SC_RA_RAM_SW_EVENT_CE_IR__W 1 -#define SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 -#define SC_RA_RAM_SW_EVENT_FE_FD__B 8 -#define SC_RA_RAM_SW_EVENT_FE_FD__W 1 -#define SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 -#define SC_RA_RAM_SW_EVENT_FE_CF__B 9 -#define SC_RA_RAM_SW_EVENT_FE_CF__W 1 -#define SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__B 10 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__W 1 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__M 0x400 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__B 11 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__W 1 -#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__M 0x800 - -#define SC_RA_RAM_LOCKTRACK__A 0x820047 -#define SC_RA_RAM_LOCKTRACK__W 16 -#define SC_RA_RAM_LOCKTRACK__M 0xFFFF -#define SC_RA_RAM_LOCKTRACK_NULL 0x0 #define SC_RA_RAM_LOCKTRACK_MIN 0x1 -#define SC_RA_RAM_LOCKTRACK_RESET 0x1 -#define SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 -#define SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 -#define SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 -#define SC_RA_RAM_LOCKTRACK_P_DETECT_MIRROR 0x5 -#define SC_RA_RAM_LOCKTRACK_LC 0x6 -#define SC_RA_RAM_LOCKTRACK_P_ECHO 0x7 -#define SC_RA_RAM_LOCKTRACK_NE_INIT 0x8 -#define SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x9 -#define SC_RA_RAM_LOCKTRACK_TRACK 0xA -#define SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xB -#define SC_RA_RAM_LOCKTRACK_SR_SCANNING 0xC -#define SC_RA_RAM_LOCKTRACK_MAX 0xD - -#define SC_RA_RAM_OP_PARAM__A 0x820048 -#define SC_RA_RAM_OP_PARAM__W 13 -#define SC_RA_RAM_OP_PARAM__M 0x1FFF -#define SC_RA_RAM_OP_PARAM_MODE__B 0 -#define SC_RA_RAM_OP_PARAM_MODE__W 2 -#define SC_RA_RAM_OP_PARAM_MODE__M 0x3 #define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 #define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 -#define SC_RA_RAM_OP_PARAM_GUARD__B 2 -#define SC_RA_RAM_OP_PARAM_GUARD__W 2 -#define SC_RA_RAM_OP_PARAM_GUARD__M 0xC #define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 #define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 #define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 #define SC_RA_RAM_OP_PARAM_GUARD_4 0xC -#define SC_RA_RAM_OP_PARAM_CONST__B 4 -#define SC_RA_RAM_OP_PARAM_CONST__W 2 -#define SC_RA_RAM_OP_PARAM_CONST__M 0x30 #define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 #define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 #define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 -#define SC_RA_RAM_OP_PARAM_HIER__B 6 -#define SC_RA_RAM_OP_PARAM_HIER__W 3 -#define SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 #define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 #define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 #define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 #define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 -#define SC_RA_RAM_OP_PARAM_RATE__B 9 -#define SC_RA_RAM_OP_PARAM_RATE__W 3 -#define SC_RA_RAM_OP_PARAM_RATE__M 0xE00 #define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 #define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 #define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 #define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 #define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 -#define SC_RA_RAM_OP_PARAM_PRIO__B 12 -#define SC_RA_RAM_OP_PARAM_PRIO__W 1 -#define SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 #define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 #define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 - -#define SC_RA_RAM_OP_AUTO__A 0x820049 -#define SC_RA_RAM_OP_AUTO__W 6 -#define SC_RA_RAM_OP_AUTO__M 0x3F -#define SC_RA_RAM_OP_AUTO__PRE 0x1F -#define SC_RA_RAM_OP_AUTO_MODE__B 0 -#define SC_RA_RAM_OP_AUTO_MODE__W 1 #define SC_RA_RAM_OP_AUTO_MODE__M 0x1 -#define SC_RA_RAM_OP_AUTO_GUARD__B 1 -#define SC_RA_RAM_OP_AUTO_GUARD__W 1 #define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 -#define SC_RA_RAM_OP_AUTO_CONST__B 2 -#define SC_RA_RAM_OP_AUTO_CONST__W 1 #define SC_RA_RAM_OP_AUTO_CONST__M 0x4 -#define SC_RA_RAM_OP_AUTO_HIER__B 3 -#define SC_RA_RAM_OP_AUTO_HIER__W 1 #define SC_RA_RAM_OP_AUTO_HIER__M 0x8 -#define SC_RA_RAM_OP_AUTO_RATE__B 4 -#define SC_RA_RAM_OP_AUTO_RATE__W 1 #define SC_RA_RAM_OP_AUTO_RATE__M 0x10 -#define SC_RA_RAM_OP_AUTO_PRIO__B 5 -#define SC_RA_RAM_OP_AUTO_PRIO__W 1 -#define SC_RA_RAM_OP_AUTO_PRIO__M 0x20 - -#define SC_RA_RAM_PILOT_STATUS__A 0x82004A -#define SC_RA_RAM_PILOT_STATUS__W 16 -#define SC_RA_RAM_PILOT_STATUS__M 0xFFFF -#define SC_RA_RAM_PILOT_STATUS_OK 0x0 -#define SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 -#define SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 - #define SC_RA_RAM_LOCK__A 0x82004B -#define SC_RA_RAM_LOCK__W 4 -#define SC_RA_RAM_LOCK__M 0xF -#define SC_RA_RAM_LOCK_DEMOD__B 0 -#define SC_RA_RAM_LOCK_DEMOD__W 1 #define SC_RA_RAM_LOCK_DEMOD__M 0x1 -#define SC_RA_RAM_LOCK_FEC__B 1 -#define SC_RA_RAM_LOCK_FEC__W 1 #define SC_RA_RAM_LOCK_FEC__M 0x2 -#define SC_RA_RAM_LOCK_MPEG__B 2 -#define SC_RA_RAM_LOCK_MPEG__W 1 #define SC_RA_RAM_LOCK_MPEG__M 0x4 -#define SC_RA_RAM_LOCK_NODVBT__B 3 -#define SC_RA_RAM_LOCK_NODVBT__W 1 -#define SC_RA_RAM_LOCK_NODVBT__M 0x8 - #define SC_RA_RAM_BE_OPT_ENA__A 0x82004C -#define SC_RA_RAM_BE_OPT_ENA__W 5 -#define SC_RA_RAM_BE_OPT_ENA__M 0x1F -#define SC_RA_RAM_BE_OPT_ENA__PRE 0x14 -#define SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 #define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 -#define SC_RA_RAM_BE_OPT_ENA_COCHANNEL 0x2 -#define SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 -#define SC_RA_RAM_BE_OPT_ENA_MAX 0x5 - #define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D -#define SC_RA_RAM_BE_OPT_DELAY__W 16 -#define SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF -#define SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 -#define SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E -#define SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 -#define SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF -#define SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 -#define SC_RA_RAM_ECHO_THRES__A 0x82004F -#define SC_RA_RAM_ECHO_THRES__W 16 -#define SC_RA_RAM_ECHO_THRES__M 0xFFFF -#define SC_RA_RAM_ECHO_THRES__PRE 0x2A #define SC_RA_RAM_CONFIG__A 0x820050 -#define SC_RA_RAM_CONFIG__W 16 -#define SC_RA_RAM_CONFIG__M 0xFFFF -#define SC_RA_RAM_CONFIG__PRE 0x54 -#define SC_RA_RAM_CONFIG_ID__B 0 -#define SC_RA_RAM_CONFIG_ID__W 1 -#define SC_RA_RAM_CONFIG_ID__M 0x1 -#define SC_RA_RAM_CONFIG_ID_PRO 0x0 -#define SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 -#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 -#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 -#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 -#define SC_RA_RAM_CONFIG_FR_ENABLE__B 2 -#define SC_RA_RAM_CONFIG_FR_ENABLE__W 1 #define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 -#define SC_RA_RAM_CONFIG_MIXMODE__B 3 -#define SC_RA_RAM_CONFIG_MIXMODE__W 1 -#define SC_RA_RAM_CONFIG_MIXMODE__M 0x8 -#define SC_RA_RAM_CONFIG_FREQSCAN__B 4 -#define SC_RA_RAM_CONFIG_FREQSCAN__W 1 #define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 -#define SC_RA_RAM_CONFIG_SLAVE__B 5 -#define SC_RA_RAM_CONFIG_SLAVE__W 1 #define SC_RA_RAM_CONFIG_SLAVE__M 0x20 -#define SC_RA_RAM_CONFIG_FAR_OFF__B 6 -#define SC_RA_RAM_CONFIG_FAR_OFF__W 1 -#define SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 -#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 -#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 -#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 -#define SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 -#define SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 -#define SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 -#define SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 -#define SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 -#define SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 - -#define SC_RA_RAM_PILOT_THRES_SPD__A 0x820051 -#define SC_RA_RAM_PILOT_THRES_SPD__W 16 -#define SC_RA_RAM_PILOT_THRES_SPD__M 0xFFFF -#define SC_RA_RAM_PILOT_THRES_SPD__PRE 0x4 -#define SC_RA_RAM_PILOT_THRES_CPD__A 0x820052 -#define SC_RA_RAM_PILOT_THRES_CPD__W 16 -#define SC_RA_RAM_PILOT_THRES_CPD__M 0xFFFF -#define SC_RA_RAM_PILOT_THRES_CPD__PRE 0x4 -#define SC_RA_RAM_PILOT_THRES_FREQSCAN__A 0x820053 -#define SC_RA_RAM_PILOT_THRES_FREQSCAN__W 16 -#define SC_RA_RAM_PILOT_THRES_FREQSCAN__M 0xFFFF -#define SC_RA_RAM_PILOT_THRES_FREQSCAN__PRE 0x406 - -#define SC_RA_RAM_CO_THRES_8K__A 0x820055 -#define SC_RA_RAM_CO_THRES_8K__W 16 -#define SC_RA_RAM_CO_THRES_8K__M 0xFFFF -#define SC_RA_RAM_CO_THRES_8K__PRE 0x10E -#define SC_RA_RAM_CO_THRES_2K__A 0x820056 -#define SC_RA_RAM_CO_THRES_2K__W 16 -#define SC_RA_RAM_CO_THRES_2K__M 0xFFFF -#define SC_RA_RAM_CO_THRES_2K__PRE 0x208 -#define SC_RA_RAM_CO_LEVEL__A 0x820057 -#define SC_RA_RAM_CO_LEVEL__W 16 -#define SC_RA_RAM_CO_LEVEL__M 0xFFFF -#define SC_RA_RAM_CO_DETECT__A 0x820058 -#define SC_RA_RAM_CO_DETECT__W 16 -#define SC_RA_RAM_CO_DETECT__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__A 0x820059 -#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__PRE 0xFFDB -#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__A 0x82005A -#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__PRE 0xFFEB -#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__A 0x82005B -#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__PRE 0xFFFB -#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__A 0x82005C -#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__PRE 0xFFDD -#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__A 0x82005D -#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__PRE 0xFFED -#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__A 0x82005E -#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__W 16 -#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__M 0xFFFF -#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__PRE 0xFFFD -#define SC_RA_RAM_MOTION_OFFSET__A 0x82005F -#define SC_RA_RAM_MOTION_OFFSET__W 16 -#define SC_RA_RAM_MOTION_OFFSET__M 0xFFFF -#define SC_RA_RAM_MOTION_OFFSET__PRE 0x2 -#define SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 -#define SC_RA_RAM_STATE_PROC_STOP__XSZ 12 -#define SC_RA_RAM_STATE_PROC_STOP__W 16 -#define SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF -#define SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE -#define SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 -#define SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_10__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_STOP_11__PRE 0xFFFE -#define SC_RA_RAM_STATE_PROC_STOP_12__PRE 0xFFFE -#define SC_RA_RAM_STATE_PROC_START__AX 0x820070 -#define SC_RA_RAM_STATE_PROC_START__XSZ 12 -#define SC_RA_RAM_STATE_PROC_START__W 16 -#define SC_RA_RAM_STATE_PROC_START__M 0xFFFF -#define SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 -#define SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 -#define SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 -#define SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 -#define SC_RA_RAM_STATE_PROC_START_5__PRE 0x4 -#define SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_START_7__PRE 0x10 -#define SC_RA_RAM_STATE_PROC_START_8__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_START_9__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_START_10__PRE 0x30 -#define SC_RA_RAM_STATE_PROC_START_11__PRE 0x0 -#define SC_RA_RAM_STATE_PROC_START_12__PRE 0x0 #define SC_RA_RAM_IF_SAVE__AX 0x82008E -#define SC_RA_RAM_IF_SAVE__XSZ 2 -#define SC_RA_RAM_IF_SAVE__W 16 -#define SC_RA_RAM_IF_SAVE__M 0xFFFF -#define SC_RA_RAM_FR_THRES__A 0x82007D -#define SC_RA_RAM_FR_THRES__W 16 -#define SC_RA_RAM_FR_THRES__M 0xFFFF -#define SC_RA_RAM_FR_THRES__PRE 0x1A2C -#define SC_RA_RAM_STATUS__A 0x82007E -#define SC_RA_RAM_STATUS__W 16 -#define SC_RA_RAM_STATUS__M 0xFFFF -#define SC_RA_RAM_NF_BORDER_INIT__A 0x82007F -#define SC_RA_RAM_NF_BORDER_INIT__W 16 -#define SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF -#define SC_RA_RAM_NF_BORDER_INIT__PRE 0x500 -#define SC_RA_RAM_TIMER__A 0x820080 -#define SC_RA_RAM_TIMER__W 16 -#define SC_RA_RAM_TIMER__M 0xFFFF -#define SC_RA_RAM_FI_OFFSET__A 0x820081 -#define SC_RA_RAM_FI_OFFSET__W 16 -#define SC_RA_RAM_FI_OFFSET__M 0xFFFF -#define SC_RA_RAM_FI_OFFSET__PRE 0x382 -#define SC_RA_RAM_ECHO_GUARD__A 0x820082 -#define SC_RA_RAM_ECHO_GUARD__W 16 -#define SC_RA_RAM_ECHO_GUARD__M 0xFFFF -#define SC_RA_RAM_ECHO_GUARD__PRE 0x18 - -#define SC_RA_RAM_IR_FREQ__A 0x8200D0 -#define SC_RA_RAM_IR_FREQ__W 16 -#define SC_RA_RAM_IR_FREQ__M 0xFFFF -#define SC_RA_RAM_IR_FREQ__PRE 0x0 - #define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 -#define SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 -#define SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF #define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 #define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 -#define SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 -#define SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF #define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 #define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 -#define SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 -#define SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF #define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 - #define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 -#define SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 -#define SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF #define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 #define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 -#define SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 -#define SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF #define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 #define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 -#define SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 -#define SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF #define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 - #define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 -#define SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 -#define SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF #define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 #define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 -#define SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 -#define SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF #define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 #define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 -#define SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 -#define SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF #define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 - #define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA -#define SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 -#define SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF #define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB #define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB -#define SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 -#define SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF #define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 #define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC -#define SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 -#define SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF #define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 - #define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD -#define SC_RA_RAM_ECHO_SHIFT_LIM__W 16 -#define SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF -#define SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0xFFFF -#define SC_RA_RAM_ECHO_AGE__A 0x8200DE -#define SC_RA_RAM_ECHO_AGE__W 16 -#define SC_RA_RAM_ECHO_AGE__M 0xFFFF -#define SC_RA_RAM_ECHO_AGE__PRE 0xFFFF -#define SC_RA_RAM_ECHO_FILTER__A 0x8200DF -#define SC_RA_RAM_ECHO_FILTER__W 16 -#define SC_RA_RAM_ECHO_FILTER__M 0xFFFF -#define SC_RA_RAM_ECHO_FILTER__PRE 0x2 - -#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 -#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 -#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF -#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 -#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 -#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 -#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF -#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 -#define SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 -#define SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 -#define SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF -#define SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 - -#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 -#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 -#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF -#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE -#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 -#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 -#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF -#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 -#define SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 -#define SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 -#define SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF -#define SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 - #define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 -#define SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 -#define SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF -#define SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x10 #define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 -#define SC_RA_RAM_SAMPLE_RATE_STEP__W 16 -#define SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF -#define SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x113 - -#define SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA -#define SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 -#define SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF -#define SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 -#define SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB -#define SC_RA_RAM_TPS_TIMEOUT__W 16 -#define SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF #define SC_RA_RAM_BAND__A 0x8200EC -#define SC_RA_RAM_BAND__W 16 -#define SC_RA_RAM_BAND__M 0xFFFF -#define SC_RA_RAM_BAND__PRE 0x0 -#define SC_RA_RAM_BAND_INTERVAL__B 0 -#define SC_RA_RAM_BAND_INTERVAL__W 4 -#define SC_RA_RAM_BAND_INTERVAL__M 0xF -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 -#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 -#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 - -#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED -#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 -#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF -#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 -#define SC_RA_RAM_REG__AX 0x8200F0 -#define SC_RA_RAM_REG__XSZ 2 -#define SC_RA_RAM_REG__W 16 -#define SC_RA_RAM_REG__M 0xFFFF -#define SC_RA_RAM_BREAK__A 0x8200F2 -#define SC_RA_RAM_BREAK__W 16 -#define SC_RA_RAM_BREAK__M 0xFFFF -#define SC_RA_RAM_BOOTCOUNT__A 0x8200F3 -#define SC_RA_RAM_BOOTCOUNT__W 16 -#define SC_RA_RAM_BOOTCOUNT__M 0xFFFF - #define SC_RA_RAM_LC_ABS_2K__A 0x8200F4 -#define SC_RA_RAM_LC_ABS_2K__W 16 -#define SC_RA_RAM_LC_ABS_2K__M 0xFFFF #define SC_RA_RAM_LC_ABS_2K__PRE 0x1F #define SC_RA_RAM_LC_ABS_8K__A 0x8200F5 -#define SC_RA_RAM_LC_ABS_8K__W 16 -#define SC_RA_RAM_LC_ABS_8K__M 0xFFFF #define SC_RA_RAM_LC_ABS_8K__PRE 0x1F - -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__A 0x8200F6 -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__W 16 -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__M 0xFFFF -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__PRE 0x1 -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__A 0x8200F7 -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__W 16 -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__M 0xFFFF -#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__PRE 0x0 - -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__A 0x8200F8 -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__W 16 -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__M 0xFFFF -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__PRE 0x3 -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__A 0x8200F9 -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__W 16 -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__M 0xFFFF -#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__PRE 0x2 -#define SC_RA_RAM_RELOCK__A 0x8200FE -#define SC_RA_RAM_RELOCK__W 16 -#define SC_RA_RAM_RELOCK__M 0xFFFF -#define SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF -#define SC_RA_RAM_STACKUNDERFLOW__W 16 -#define SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF - -#define SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 -#define SC_RA_RAM_NF_MAXECHOTOKEN__W 16 -#define SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF -#define SC_RA_RAM_NF_PREPOST__A 0x820149 -#define SC_RA_RAM_NF_PREPOST__W 16 -#define SC_RA_RAM_NF_PREPOST__M 0xFFFF -#define SC_RA_RAM_NF_PREBORDER__A 0x82014A -#define SC_RA_RAM_NF_PREBORDER__W 16 -#define SC_RA_RAM_NF_PREBORDER__M 0xFFFF -#define SC_RA_RAM_NF_START__A 0x82014B -#define SC_RA_RAM_NF_START__W 16 -#define SC_RA_RAM_NF_START__M 0xFFFF -#define SC_RA_RAM_NF_MINISI__AX 0x82014C -#define SC_RA_RAM_NF_MINISI__XSZ 2 -#define SC_RA_RAM_NF_MINISI__W 16 -#define SC_RA_RAM_NF_MINISI__M 0xFFFF -#define SC_RA_RAM_NF_MAXECHO__A 0x82014E -#define SC_RA_RAM_NF_MAXECHO__W 16 -#define SC_RA_RAM_NF_MAXECHO__M 0xFFFF -#define SC_RA_RAM_NF_NRECHOES__A 0x82014F -#define SC_RA_RAM_NF_NRECHOES__W 16 -#define SC_RA_RAM_NF_NRECHOES__M 0xFFFF -#define SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 -#define SC_RA_RAM_NF_ECHOTABLE__XSZ 16 -#define SC_RA_RAM_NF_ECHOTABLE__W 16 -#define SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF - -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6 -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 - -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5 - -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 - -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5 - -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6 - -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 - -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5 - -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 -#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF #define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5 #define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE -#define SC_RA_RAM_DRIVER_VERSION__XSZ 2 -#define SC_RA_RAM_DRIVER_VERSION__W 16 -#define SC_RA_RAM_DRIVER_VERSION__M 0xFFFF -#define SC_RA_RAM_EVENT0_MIN 0x7 -#define SC_RA_RAM_EVENT0_FE_CU 0x7 -#define SC_RA_RAM_EVENT0_CE 0xA -#define SC_RA_RAM_EVENT0_EQ 0xE -#define SC_RA_RAM_EVENT0_MAX 0xF -#define SC_RA_RAM_EVENT1_MIN 0x8 -#define SC_RA_RAM_EVENT1_EC_OD 0x8 -#define SC_RA_RAM_EVENT1_LC 0xC -#define SC_RA_RAM_EVENT1_MAX 0xD #define SC_RA_RAM_PROC_LOCKTRACK 0x0 -#define SC_RA_RAM_PROC_MODE_GUARD 0x1 -#define SC_RA_RAM_PROC_PILOTS 0x2 -#define SC_RA_RAM_PROC_FESTART_ADJUST 0x3 -#define SC_RA_RAM_PROC_ECHO 0x4 -#define SC_RA_RAM_PROC_BE_OPT 0x5 -#define SC_RA_RAM_PROC_EQ 0x7 -#define SC_RA_RAM_PROC_MAX 0x8 - -#define SC_IF_RAM_TRP_RST__AX 0x830000 -#define SC_IF_RAM_TRP_RST__XSZ 2 -#define SC_IF_RAM_TRP_RST__W 12 -#define SC_IF_RAM_TRP_RST__M 0xFFF - -#define SC_IF_RAM_TRP_BPT0__AX 0x830002 -#define SC_IF_RAM_TRP_BPT0__XSZ 2 -#define SC_IF_RAM_TRP_BPT0__W 12 -#define SC_IF_RAM_TRP_BPT0__M 0xFFF - -#define SC_IF_RAM_TRP_STKU__AX 0x830004 -#define SC_IF_RAM_TRP_STKU__XSZ 2 -#define SC_IF_RAM_TRP_STKU__W 12 -#define SC_IF_RAM_TRP_STKU__M 0xFFF - -#define SC_IF_RAM_VERSION_MA_MI__A 0x830FFE -#define SC_IF_RAM_VERSION_MA_MI__W 12 -#define SC_IF_RAM_VERSION_MA_MI__M 0xFFF - -#define SC_IF_RAM_VERSION_PATCH__A 0x830FFF -#define SC_IF_RAM_VERSION_PATCH__W 12 -#define SC_IF_RAM_VERSION_PATCH__M 0xFFF - #define FE_COMM_EXEC__A 0xC00000 -#define FE_COMM_EXEC__W 3 -#define FE_COMM_EXEC__M 0x7 -#define FE_COMM_EXEC_CTL__B 0 -#define FE_COMM_EXEC_CTL__W 3 -#define FE_COMM_EXEC_CTL__M 0x7 -#define FE_COMM_EXEC_CTL_STOP 0x0 -#define FE_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_COMM_EXEC_CTL_HOLD 0x2 -#define FE_COMM_EXEC_CTL_STEP 0x3 -#define FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define FE_COMM_STATE__A 0xC00001 -#define FE_COMM_STATE__W 16 -#define FE_COMM_STATE__M 0xFFFF -#define FE_COMM_MB__A 0xC00002 -#define FE_COMM_MB__W 16 -#define FE_COMM_MB__M 0xFFFF -#define FE_COMM_SERVICE0__A 0xC00003 -#define FE_COMM_SERVICE0__W 16 -#define FE_COMM_SERVICE0__M 0xFFFF -#define FE_COMM_SERVICE1__A 0xC00004 -#define FE_COMM_SERVICE1__W 16 -#define FE_COMM_SERVICE1__M 0xFFFF -#define FE_COMM_INT_STA__A 0xC00007 -#define FE_COMM_INT_STA__W 16 -#define FE_COMM_INT_STA__M 0xFFFF -#define FE_COMM_INT_MSK__A 0xC00008 -#define FE_COMM_INT_MSK__W 16 -#define FE_COMM_INT_MSK__M 0xFFFF - -#define FE_AD_SID 0x1 - #define FE_AD_REG_COMM_EXEC__A 0xC10000 -#define FE_AD_REG_COMM_EXEC__W 3 -#define FE_AD_REG_COMM_EXEC__M 0x7 -#define FE_AD_REG_COMM_EXEC_CTL__B 0 -#define FE_AD_REG_COMM_EXEC_CTL__W 3 -#define FE_AD_REG_COMM_EXEC_CTL__M 0x7 -#define FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_AD_REG_COMM_MB__A 0xC10002 -#define FE_AD_REG_COMM_MB__W 2 -#define FE_AD_REG_COMM_MB__M 0x3 -#define FE_AD_REG_COMM_MB_CTR__B 0 -#define FE_AD_REG_COMM_MB_CTR__W 1 -#define FE_AD_REG_COMM_MB_CTR__M 0x1 -#define FE_AD_REG_COMM_MB_CTR_OFF 0x0 -#define FE_AD_REG_COMM_MB_CTR_ON 0x1 -#define FE_AD_REG_COMM_MB_OBS__B 1 -#define FE_AD_REG_COMM_MB_OBS__W 1 -#define FE_AD_REG_COMM_MB_OBS__M 0x2 -#define FE_AD_REG_COMM_MB_OBS_OFF 0x0 -#define FE_AD_REG_COMM_MB_OBS_ON 0x2 - -#define FE_AD_REG_COMM_SERVICE0__A 0xC10003 -#define FE_AD_REG_COMM_SERVICE0__W 10 -#define FE_AD_REG_COMM_SERVICE0__M 0x3FF -#define FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 -#define FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 -#define FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 - -#define FE_AD_REG_COMM_SERVICE1__A 0xC10004 -#define FE_AD_REG_COMM_SERVICE1__W 11 -#define FE_AD_REG_COMM_SERVICE1__M 0x7FF - -#define FE_AD_REG_COMM_INT_STA__A 0xC10007 -#define FE_AD_REG_COMM_INT_STA__W 2 -#define FE_AD_REG_COMM_INT_STA__M 0x3 -#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 -#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 -#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 - -#define FE_AD_REG_COMM_INT_MSK__A 0xC10008 -#define FE_AD_REG_COMM_INT_MSK__W 2 -#define FE_AD_REG_COMM_INT_MSK__M 0x3 -#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 -#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 -#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 - -#define FE_AD_REG_CUR_SEL__A 0xC10010 -#define FE_AD_REG_CUR_SEL__W 2 -#define FE_AD_REG_CUR_SEL__M 0x3 -#define FE_AD_REG_CUR_SEL_INIT 0x2 - -#define FE_AD_REG_OVERFLOW__A 0xC10011 -#define FE_AD_REG_OVERFLOW__W 1 -#define FE_AD_REG_OVERFLOW__M 0x1 -#define FE_AD_REG_OVERFLOW_INIT 0x0 - #define FE_AD_REG_FDB_IN__A 0xC10012 -#define FE_AD_REG_FDB_IN__W 1 -#define FE_AD_REG_FDB_IN__M 0x1 -#define FE_AD_REG_FDB_IN_INIT 0x0 - #define FE_AD_REG_PD__A 0xC10013 -#define FE_AD_REG_PD__W 1 -#define FE_AD_REG_PD__M 0x1 -#define FE_AD_REG_PD_INIT 0x1 - #define FE_AD_REG_INVEXT__A 0xC10014 -#define FE_AD_REG_INVEXT__W 1 -#define FE_AD_REG_INVEXT__M 0x1 -#define FE_AD_REG_INVEXT_INIT 0x0 - #define FE_AD_REG_CLKNEG__A 0xC10015 -#define FE_AD_REG_CLKNEG__W 1 -#define FE_AD_REG_CLKNEG__M 0x1 -#define FE_AD_REG_CLKNEG_INIT 0x0 - -#define FE_AD_REG_MON_IN_MUX__A 0xC10016 -#define FE_AD_REG_MON_IN_MUX__W 2 -#define FE_AD_REG_MON_IN_MUX__M 0x3 -#define FE_AD_REG_MON_IN_MUX_INIT 0x0 - -#define FE_AD_REG_MON_IN5__A 0xC10017 -#define FE_AD_REG_MON_IN5__W 10 -#define FE_AD_REG_MON_IN5__M 0x3FF -#define FE_AD_REG_MON_IN5_INIT 0x0 - -#define FE_AD_REG_MON_IN4__A 0xC10018 -#define FE_AD_REG_MON_IN4__W 10 -#define FE_AD_REG_MON_IN4__M 0x3FF -#define FE_AD_REG_MON_IN4_INIT 0x0 - -#define FE_AD_REG_MON_IN3__A 0xC10019 -#define FE_AD_REG_MON_IN3__W 10 -#define FE_AD_REG_MON_IN3__M 0x3FF -#define FE_AD_REG_MON_IN3_INIT 0x0 - -#define FE_AD_REG_MON_IN2__A 0xC1001A -#define FE_AD_REG_MON_IN2__W 10 -#define FE_AD_REG_MON_IN2__M 0x3FF -#define FE_AD_REG_MON_IN2_INIT 0x0 - -#define FE_AD_REG_MON_IN1__A 0xC1001B -#define FE_AD_REG_MON_IN1__W 10 -#define FE_AD_REG_MON_IN1__M 0x3FF -#define FE_AD_REG_MON_IN1_INIT 0x0 - -#define FE_AD_REG_MON_IN0__A 0xC1001C -#define FE_AD_REG_MON_IN0__W 10 -#define FE_AD_REG_MON_IN0__M 0x3FF -#define FE_AD_REG_MON_IN0_INIT 0x0 - -#define FE_AD_REG_MON_IN_VAL__A 0xC1001D -#define FE_AD_REG_MON_IN_VAL__W 1 -#define FE_AD_REG_MON_IN_VAL__M 0x1 -#define FE_AD_REG_MON_IN_VAL_INIT 0x0 - -#define FE_AD_REG_CTR_CLK_O__A 0xC1001E -#define FE_AD_REG_CTR_CLK_O__W 1 -#define FE_AD_REG_CTR_CLK_O__M 0x1 -#define FE_AD_REG_CTR_CLK_O_INIT 0x0 - -#define FE_AD_REG_CTR_CLK_E_O__A 0xC1001F -#define FE_AD_REG_CTR_CLK_E_O__W 1 -#define FE_AD_REG_CTR_CLK_E_O__M 0x1 -#define FE_AD_REG_CTR_CLK_E_O_INIT 0x1 - -#define FE_AD_REG_CTR_VAL_O__A 0xC10020 -#define FE_AD_REG_CTR_VAL_O__W 1 -#define FE_AD_REG_CTR_VAL_O__M 0x1 -#define FE_AD_REG_CTR_VAL_O_INIT 0x0 - -#define FE_AD_REG_CTR_VAL_E_O__A 0xC10021 -#define FE_AD_REG_CTR_VAL_E_O__W 1 -#define FE_AD_REG_CTR_VAL_E_O__M 0x1 -#define FE_AD_REG_CTR_VAL_E_O_INIT 0x1 - -#define FE_AD_REG_CTR_DATA_O__A 0xC10022 -#define FE_AD_REG_CTR_DATA_O__W 10 -#define FE_AD_REG_CTR_DATA_O__M 0x3FF -#define FE_AD_REG_CTR_DATA_O_INIT 0x0 - -#define FE_AD_REG_CTR_DATA_E_O__A 0xC10023 -#define FE_AD_REG_CTR_DATA_E_O__W 10 -#define FE_AD_REG_CTR_DATA_E_O__M 0x3FF -#define FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF - -#define FE_AG_SID 0x2 - #define FE_AG_REG_COMM_EXEC__A 0xC20000 -#define FE_AG_REG_COMM_EXEC__W 3 -#define FE_AG_REG_COMM_EXEC__M 0x7 -#define FE_AG_REG_COMM_EXEC_CTL__B 0 -#define FE_AG_REG_COMM_EXEC_CTL__W 3 -#define FE_AG_REG_COMM_EXEC_CTL__M 0x7 -#define FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_AG_REG_COMM_STATE__A 0xC20001 -#define FE_AG_REG_COMM_STATE__W 4 -#define FE_AG_REG_COMM_STATE__M 0xF - -#define FE_AG_REG_COMM_MB__A 0xC20002 -#define FE_AG_REG_COMM_MB__W 2 -#define FE_AG_REG_COMM_MB__M 0x3 -#define FE_AG_REG_COMM_MB_CTR__B 0 -#define FE_AG_REG_COMM_MB_CTR__W 1 -#define FE_AG_REG_COMM_MB_CTR__M 0x1 -#define FE_AG_REG_COMM_MB_CTR_OFF 0x0 -#define FE_AG_REG_COMM_MB_CTR_ON 0x1 -#define FE_AG_REG_COMM_MB_OBS__B 1 -#define FE_AG_REG_COMM_MB_OBS__W 1 -#define FE_AG_REG_COMM_MB_OBS__M 0x2 -#define FE_AG_REG_COMM_MB_OBS_OFF 0x0 -#define FE_AG_REG_COMM_MB_OBS_ON 0x2 - -#define FE_AG_REG_COMM_SERVICE0__A 0xC20003 -#define FE_AG_REG_COMM_SERVICE0__W 10 -#define FE_AG_REG_COMM_SERVICE0__M 0x3FF - -#define FE_AG_REG_COMM_SERVICE1__A 0xC20004 -#define FE_AG_REG_COMM_SERVICE1__W 11 -#define FE_AG_REG_COMM_SERVICE1__M 0x7FF - -#define FE_AG_REG_COMM_INT_STA__A 0xC20007 -#define FE_AG_REG_COMM_INT_STA__W 8 -#define FE_AG_REG_COMM_INT_STA__M 0xFF -#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 -#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 -#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 -#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 -#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 -#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 -#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 -#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 -#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 -#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 -#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 -#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 -#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__B 6 -#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__M 0x40 -#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 -#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 -#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 - -#define FE_AG_REG_COMM_INT_MSK__A 0xC20008 -#define FE_AG_REG_COMM_INT_MSK__W 8 -#define FE_AG_REG_COMM_INT_MSK__M 0xFF -#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 -#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 -#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 -#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 -#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 -#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 -#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 -#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 -#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 -#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 -#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 -#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 -#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__B 6 -#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__M 0x40 -#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 -#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 -#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 - #define FE_AG_REG_AG_MODE_LOP__A 0xC20010 -#define FE_AG_REG_AG_MODE_LOP__W 16 -#define FE_AG_REG_AG_MODE_LOP__M 0xFFFF -#define FE_AG_REG_AG_MODE_LOP_INIT 0x0 - -#define FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 -#define FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 -#define FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 - -#define FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 -#define FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 - -#define FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 -#define FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 -#define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 - -#define FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 -#define FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 -#define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 - -#define FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 -#define FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 #define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 #define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 #define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 - -#define FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 -#define FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 #define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 #define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 - -#define FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 -#define FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 -#define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 - -#define FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 -#define FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 -#define FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 - -#define FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 -#define FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 -#define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 - -#define FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 -#define FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 -#define FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 - -#define FE_AG_REG_AG_MODE_LOP_MODE_A__B 10 -#define FE_AG_REG_AG_MODE_LOP_MODE_A__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_A__M 0x400 -#define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_B 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_CB 0x400 - -#define FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 -#define FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 -#define FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 - -#define FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 -#define FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 #define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 #define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 #define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 - -#define FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 -#define FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 -#define FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 - -#define FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 -#define FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 #define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 #define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 #define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 - -#define FE_AG_REG_AG_MODE_LOP_MODE_F__B 15 -#define FE_AG_REG_AG_MODE_LOP_MODE_F__W 1 -#define FE_AG_REG_AG_MODE_LOP_MODE_F__M 0x8000 -#define FE_AG_REG_AG_MODE_LOP_MODE_F_DISABLE 0x0 -#define FE_AG_REG_AG_MODE_LOP_MODE_F_ENABLE 0x8000 - #define FE_AG_REG_AG_MODE_HIP__A 0xC20011 -#define FE_AG_REG_AG_MODE_HIP__W 2 -#define FE_AG_REG_AG_MODE_HIP__M 0x3 -#define FE_AG_REG_AG_MODE_HIP_INIT 0x0 - -#define FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 -#define FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 -#define FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 -#define FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 -#define FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 - -#define FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 -#define FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 -#define FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 -#define FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 -#define FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 - #define FE_AG_REG_AG_PGA_MODE__A 0xC20012 -#define FE_AG_REG_AG_PGA_MODE__W 3 -#define FE_AG_REG_AG_PGA_MODE__M 0x7 -#define FE_AG_REG_AG_PGA_MODE_INIT 0x0 #define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 #define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 -#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 -#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 -#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 -#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 -#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 -#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 - #define FE_AG_REG_AG_AGC_SIO__A 0xC20013 -#define FE_AG_REG_AG_AGC_SIO__W 2 -#define FE_AG_REG_AG_AGC_SIO__M 0x3 -#define FE_AG_REG_AG_AGC_SIO_INIT 0x3 - -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 - -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 -#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 #define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 - -#define FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 -#define FE_AG_REG_AG_AGC_USR_DAT__W 2 -#define FE_AG_REG_AG_AGC_USR_DAT__M 0x3 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 -#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 - #define FE_AG_REG_AG_PWD__A 0xC20015 -#define FE_AG_REG_AG_PWD__W 5 -#define FE_AG_REG_AG_PWD__M 0x1F -#define FE_AG_REG_AG_PWD_INIT 0x1F - -#define FE_AG_REG_AG_PWD_PWD_PD1__B 0 -#define FE_AG_REG_AG_PWD_PWD_PD1__W 1 -#define FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 -#define FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 -#define FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 - -#define FE_AG_REG_AG_PWD_PWD_PD2__B 1 -#define FE_AG_REG_AG_PWD_PWD_PD2__W 1 #define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 #define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 #define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 - -#define FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 -#define FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 -#define FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 -#define FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 -#define FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 - -#define FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 -#define FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 -#define FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 -#define FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 -#define FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 - -#define FE_AG_REG_AG_PWD_PWD_AAF__B 4 -#define FE_AG_REG_AG_PWD_PWD_AAF__W 1 -#define FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 -#define FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 -#define FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 - #define FE_AG_REG_DCE_AUR_CNT__A 0xC20016 -#define FE_AG_REG_DCE_AUR_CNT__W 5 -#define FE_AG_REG_DCE_AUR_CNT__M 0x1F -#define FE_AG_REG_DCE_AUR_CNT_INIT 0x0 - #define FE_AG_REG_DCE_RUR_CNT__A 0xC20017 -#define FE_AG_REG_DCE_RUR_CNT__W 5 -#define FE_AG_REG_DCE_RUR_CNT__M 0x1F -#define FE_AG_REG_DCE_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_DCE_AVE_DAT__A 0xC20018 -#define FE_AG_REG_DCE_AVE_DAT__W 10 -#define FE_AG_REG_DCE_AVE_DAT__M 0x3FF - -#define FE_AG_REG_DEC_AVE_WRI__A 0xC20019 -#define FE_AG_REG_DEC_AVE_WRI__W 10 -#define FE_AG_REG_DEC_AVE_WRI__M 0x3FF -#define FE_AG_REG_DEC_AVE_WRI_INIT 0x0 - #define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A -#define FE_AG_REG_ACE_AUR_CNT__W 5 -#define FE_AG_REG_ACE_AUR_CNT__M 0x1F -#define FE_AG_REG_ACE_AUR_CNT_INIT 0x0 - #define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B -#define FE_AG_REG_ACE_RUR_CNT__W 5 -#define FE_AG_REG_ACE_RUR_CNT__M 0x1F -#define FE_AG_REG_ACE_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_ACE_AVE_DAT__A 0xC2001C -#define FE_AG_REG_ACE_AVE_DAT__W 10 -#define FE_AG_REG_ACE_AVE_DAT__M 0x3FF - -#define FE_AG_REG_AEC_AVE_INC__A 0xC2001D -#define FE_AG_REG_AEC_AVE_INC__W 10 -#define FE_AG_REG_AEC_AVE_INC__M 0x3FF -#define FE_AG_REG_AEC_AVE_INC_INIT 0x0 - -#define FE_AG_REG_AEC_AVE_DAT__A 0xC2001E -#define FE_AG_REG_AEC_AVE_DAT__W 10 -#define FE_AG_REG_AEC_AVE_DAT__M 0x3FF - -#define FE_AG_REG_AEC_CLP_LVL__A 0xC2001F -#define FE_AG_REG_AEC_CLP_LVL__W 16 -#define FE_AG_REG_AEC_CLP_LVL__M 0xFFFF -#define FE_AG_REG_AEC_CLP_LVL_INIT 0x0 - #define FE_AG_REG_CDR_RUR_CNT__A 0xC20020 -#define FE_AG_REG_CDR_RUR_CNT__W 5 -#define FE_AG_REG_CDR_RUR_CNT__M 0x1F -#define FE_AG_REG_CDR_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_CDR_CLP_DAT__A 0xC20021 -#define FE_AG_REG_CDR_CLP_DAT__W 16 -#define FE_AG_REG_CDR_CLP_DAT__M 0xFFFF - -#define FE_AG_REG_CDR_CLP_POS__A 0xC20022 -#define FE_AG_REG_CDR_CLP_POS__W 10 -#define FE_AG_REG_CDR_CLP_POS__M 0x3FF -#define FE_AG_REG_CDR_CLP_POS_INIT 0x0 - -#define FE_AG_REG_CDR_CLP_NEG__A 0xC20023 -#define FE_AG_REG_CDR_CLP_NEG__W 10 -#define FE_AG_REG_CDR_CLP_NEG__M 0x3FF -#define FE_AG_REG_CDR_CLP_NEG_INIT 0x0 - #define FE_AG_REG_EGC_RUR_CNT__A 0xC20024 -#define FE_AG_REG_EGC_RUR_CNT__W 5 -#define FE_AG_REG_EGC_RUR_CNT__M 0x1F -#define FE_AG_REG_EGC_RUR_CNT_INIT 0x0 - #define FE_AG_REG_EGC_SET_LVL__A 0xC20025 -#define FE_AG_REG_EGC_SET_LVL__W 9 #define FE_AG_REG_EGC_SET_LVL__M 0x1FF -#define FE_AG_REG_EGC_SET_LVL_INIT 0x0 - #define FE_AG_REG_EGC_FLA_RGN__A 0xC20026 -#define FE_AG_REG_EGC_FLA_RGN__W 9 -#define FE_AG_REG_EGC_FLA_RGN__M 0x1FF -#define FE_AG_REG_EGC_FLA_RGN_INIT 0x0 - #define FE_AG_REG_EGC_SLO_RGN__A 0xC20027 -#define FE_AG_REG_EGC_SLO_RGN__W 9 -#define FE_AG_REG_EGC_SLO_RGN__M 0x1FF -#define FE_AG_REG_EGC_SLO_RGN_INIT 0x0 - #define FE_AG_REG_EGC_JMP_PSN__A 0xC20028 -#define FE_AG_REG_EGC_JMP_PSN__W 4 -#define FE_AG_REG_EGC_JMP_PSN__M 0xF -#define FE_AG_REG_EGC_JMP_PSN_INIT 0x0 - #define FE_AG_REG_EGC_FLA_INC__A 0xC20029 -#define FE_AG_REG_EGC_FLA_INC__W 16 -#define FE_AG_REG_EGC_FLA_INC__M 0xFFFF -#define FE_AG_REG_EGC_FLA_INC_INIT 0x0 - #define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A -#define FE_AG_REG_EGC_FLA_DEC__W 16 -#define FE_AG_REG_EGC_FLA_DEC__M 0xFFFF -#define FE_AG_REG_EGC_FLA_DEC_INIT 0x0 - #define FE_AG_REG_EGC_SLO_INC__A 0xC2002B -#define FE_AG_REG_EGC_SLO_INC__W 16 -#define FE_AG_REG_EGC_SLO_INC__M 0xFFFF -#define FE_AG_REG_EGC_SLO_INC_INIT 0x0 - #define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C -#define FE_AG_REG_EGC_SLO_DEC__W 16 -#define FE_AG_REG_EGC_SLO_DEC__M 0xFFFF -#define FE_AG_REG_EGC_SLO_DEC_INIT 0x0 - #define FE_AG_REG_EGC_FAS_INC__A 0xC2002D -#define FE_AG_REG_EGC_FAS_INC__W 16 -#define FE_AG_REG_EGC_FAS_INC__M 0xFFFF -#define FE_AG_REG_EGC_FAS_INC_INIT 0x0 - #define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E -#define FE_AG_REG_EGC_FAS_DEC__W 16 -#define FE_AG_REG_EGC_FAS_DEC__M 0xFFFF -#define FE_AG_REG_EGC_FAS_DEC_INIT 0x0 - -#define FE_AG_REG_EGC_MAP_DAT__A 0xC2002F -#define FE_AG_REG_EGC_MAP_DAT__W 16 -#define FE_AG_REG_EGC_MAP_DAT__M 0xFFFF - #define FE_AG_REG_PM1_AGC_WRI__A 0xC20030 -#define FE_AG_REG_PM1_AGC_WRI__W 11 #define FE_AG_REG_PM1_AGC_WRI__M 0x7FF -#define FE_AG_REG_PM1_AGC_WRI_INIT 0x0 - #define FE_AG_REG_GC1_AGC_RIC__A 0xC20031 -#define FE_AG_REG_GC1_AGC_RIC__W 16 -#define FE_AG_REG_GC1_AGC_RIC__M 0xFFFF -#define FE_AG_REG_GC1_AGC_RIC_INIT 0x0 - #define FE_AG_REG_GC1_AGC_OFF__A 0xC20032 -#define FE_AG_REG_GC1_AGC_OFF__W 16 -#define FE_AG_REG_GC1_AGC_OFF__M 0xFFFF -#define FE_AG_REG_GC1_AGC_OFF_INIT 0x0 - #define FE_AG_REG_GC1_AGC_MAX__A 0xC20033 -#define FE_AG_REG_GC1_AGC_MAX__W 10 -#define FE_AG_REG_GC1_AGC_MAX__M 0x3FF -#define FE_AG_REG_GC1_AGC_MAX_INIT 0x0 - #define FE_AG_REG_GC1_AGC_MIN__A 0xC20034 -#define FE_AG_REG_GC1_AGC_MIN__W 10 -#define FE_AG_REG_GC1_AGC_MIN__M 0x3FF -#define FE_AG_REG_GC1_AGC_MIN_INIT 0x0 - #define FE_AG_REG_GC1_AGC_DAT__A 0xC20035 -#define FE_AG_REG_GC1_AGC_DAT__W 10 #define FE_AG_REG_GC1_AGC_DAT__M 0x3FF - #define FE_AG_REG_PM2_AGC_WRI__A 0xC20036 -#define FE_AG_REG_PM2_AGC_WRI__W 11 -#define FE_AG_REG_PM2_AGC_WRI__M 0x7FF -#define FE_AG_REG_PM2_AGC_WRI_INIT 0x0 - -#define FE_AG_REG_GC2_AGC_RIC__A 0xC20037 -#define FE_AG_REG_GC2_AGC_RIC__W 16 -#define FE_AG_REG_GC2_AGC_RIC__M 0xFFFF -#define FE_AG_REG_GC2_AGC_RIC_INIT 0x0 - -#define FE_AG_REG_GC2_AGC_OFF__A 0xC20038 -#define FE_AG_REG_GC2_AGC_OFF__W 16 -#define FE_AG_REG_GC2_AGC_OFF__M 0xFFFF -#define FE_AG_REG_GC2_AGC_OFF_INIT 0x0 - -#define FE_AG_REG_GC2_AGC_MAX__A 0xC20039 -#define FE_AG_REG_GC2_AGC_MAX__W 10 -#define FE_AG_REG_GC2_AGC_MAX__M 0x3FF -#define FE_AG_REG_GC2_AGC_MAX_INIT 0x0 - -#define FE_AG_REG_GC2_AGC_MIN__A 0xC2003A -#define FE_AG_REG_GC2_AGC_MIN__W 10 -#define FE_AG_REG_GC2_AGC_MIN__M 0x3FF -#define FE_AG_REG_GC2_AGC_MIN_INIT 0x0 - -#define FE_AG_REG_GC2_AGC_DAT__A 0xC2003B -#define FE_AG_REG_GC2_AGC_DAT__W 10 -#define FE_AG_REG_GC2_AGC_DAT__M 0x3FF - #define FE_AG_REG_IND_WIN__A 0xC2003C -#define FE_AG_REG_IND_WIN__W 5 -#define FE_AG_REG_IND_WIN__M 0x1F -#define FE_AG_REG_IND_WIN_INIT 0x0 - #define FE_AG_REG_IND_THD_LOL__A 0xC2003D -#define FE_AG_REG_IND_THD_LOL__W 6 -#define FE_AG_REG_IND_THD_LOL__M 0x3F -#define FE_AG_REG_IND_THD_LOL_INIT 0x0 - #define FE_AG_REG_IND_THD_HIL__A 0xC2003E -#define FE_AG_REG_IND_THD_HIL__W 6 -#define FE_AG_REG_IND_THD_HIL__M 0x3F -#define FE_AG_REG_IND_THD_HIL_INIT 0x0 - #define FE_AG_REG_IND_DEL__A 0xC2003F -#define FE_AG_REG_IND_DEL__W 7 -#define FE_AG_REG_IND_DEL__M 0x7F -#define FE_AG_REG_IND_DEL_INIT 0x0 - #define FE_AG_REG_IND_PD1_WRI__A 0xC20040 -#define FE_AG_REG_IND_PD1_WRI__W 6 -#define FE_AG_REG_IND_PD1_WRI__M 0x3F -#define FE_AG_REG_IND_PD1_WRI_INIT 0x1F - #define FE_AG_REG_PDA_AUR_CNT__A 0xC20041 -#define FE_AG_REG_PDA_AUR_CNT__W 5 -#define FE_AG_REG_PDA_AUR_CNT__M 0x1F -#define FE_AG_REG_PDA_AUR_CNT_INIT 0x0 - #define FE_AG_REG_PDA_RUR_CNT__A 0xC20042 -#define FE_AG_REG_PDA_RUR_CNT__W 5 -#define FE_AG_REG_PDA_RUR_CNT__M 0x1F -#define FE_AG_REG_PDA_RUR_CNT_INIT 0x0 - #define FE_AG_REG_PDA_AVE_DAT__A 0xC20043 -#define FE_AG_REG_PDA_AVE_DAT__W 6 -#define FE_AG_REG_PDA_AVE_DAT__M 0x3F - #define FE_AG_REG_PDC_RUR_CNT__A 0xC20044 -#define FE_AG_REG_PDC_RUR_CNT__W 5 -#define FE_AG_REG_PDC_RUR_CNT__M 0x1F -#define FE_AG_REG_PDC_RUR_CNT_INIT 0x0 - #define FE_AG_REG_PDC_SET_LVL__A 0xC20045 -#define FE_AG_REG_PDC_SET_LVL__W 6 -#define FE_AG_REG_PDC_SET_LVL__M 0x3F -#define FE_AG_REG_PDC_SET_LVL_INIT 0x10 - #define FE_AG_REG_PDC_FLA_RGN__A 0xC20046 -#define FE_AG_REG_PDC_FLA_RGN__W 6 -#define FE_AG_REG_PDC_FLA_RGN__M 0x3F -#define FE_AG_REG_PDC_FLA_RGN_INIT 0x0 - #define FE_AG_REG_PDC_JMP_PSN__A 0xC20047 -#define FE_AG_REG_PDC_JMP_PSN__W 3 -#define FE_AG_REG_PDC_JMP_PSN__M 0x7 -#define FE_AG_REG_PDC_JMP_PSN_INIT 0x0 - #define FE_AG_REG_PDC_FLA_STP__A 0xC20048 -#define FE_AG_REG_PDC_FLA_STP__W 16 -#define FE_AG_REG_PDC_FLA_STP__M 0xFFFF -#define FE_AG_REG_PDC_FLA_STP_INIT 0x0 - #define FE_AG_REG_PDC_SLO_STP__A 0xC20049 -#define FE_AG_REG_PDC_SLO_STP__W 16 -#define FE_AG_REG_PDC_SLO_STP__M 0xFFFF -#define FE_AG_REG_PDC_SLO_STP_INIT 0x0 - #define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A -#define FE_AG_REG_PDC_PD2_WRI__W 6 -#define FE_AG_REG_PDC_PD2_WRI__M 0x3F -#define FE_AG_REG_PDC_PD2_WRI_INIT 0x0 - #define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B -#define FE_AG_REG_PDC_MAP_DAT__W 6 -#define FE_AG_REG_PDC_MAP_DAT__M 0x3F - #define FE_AG_REG_PDC_MAX__A 0xC2004C -#define FE_AG_REG_PDC_MAX__W 6 -#define FE_AG_REG_PDC_MAX__M 0x3F -#define FE_AG_REG_PDC_MAX_INIT 0x2 - #define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D -#define FE_AG_REG_TGA_AUR_CNT__W 5 -#define FE_AG_REG_TGA_AUR_CNT__M 0x1F -#define FE_AG_REG_TGA_AUR_CNT_INIT 0x0 - #define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E -#define FE_AG_REG_TGA_RUR_CNT__W 5 -#define FE_AG_REG_TGA_RUR_CNT__M 0x1F -#define FE_AG_REG_TGA_RUR_CNT_INIT 0x0 - #define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F -#define FE_AG_REG_TGA_AVE_DAT__W 6 -#define FE_AG_REG_TGA_AVE_DAT__M 0x3F - #define FE_AG_REG_TGC_RUR_CNT__A 0xC20050 -#define FE_AG_REG_TGC_RUR_CNT__W 5 -#define FE_AG_REG_TGC_RUR_CNT__M 0x1F -#define FE_AG_REG_TGC_RUR_CNT_INIT 0x0 - #define FE_AG_REG_TGC_SET_LVL__A 0xC20051 -#define FE_AG_REG_TGC_SET_LVL__W 6 #define FE_AG_REG_TGC_SET_LVL__M 0x3F -#define FE_AG_REG_TGC_SET_LVL_INIT 0x0 - #define FE_AG_REG_TGC_FLA_RGN__A 0xC20052 -#define FE_AG_REG_TGC_FLA_RGN__W 6 -#define FE_AG_REG_TGC_FLA_RGN__M 0x3F -#define FE_AG_REG_TGC_FLA_RGN_INIT 0x0 - #define FE_AG_REG_TGC_JMP_PSN__A 0xC20053 -#define FE_AG_REG_TGC_JMP_PSN__W 4 -#define FE_AG_REG_TGC_JMP_PSN__M 0xF -#define FE_AG_REG_TGC_JMP_PSN_INIT 0x0 - #define FE_AG_REG_TGC_FLA_STP__A 0xC20054 -#define FE_AG_REG_TGC_FLA_STP__W 16 -#define FE_AG_REG_TGC_FLA_STP__M 0xFFFF -#define FE_AG_REG_TGC_FLA_STP_INIT 0x0 - #define FE_AG_REG_TGC_SLO_STP__A 0xC20055 -#define FE_AG_REG_TGC_SLO_STP__W 16 -#define FE_AG_REG_TGC_SLO_STP__M 0xFFFF -#define FE_AG_REG_TGC_SLO_STP_INIT 0x0 - #define FE_AG_REG_TGC_MAP_DAT__A 0xC20056 -#define FE_AG_REG_TGC_MAP_DAT__W 10 -#define FE_AG_REG_TGC_MAP_DAT__M 0x3FF - #define FE_AG_REG_FGA_AUR_CNT__A 0xC20057 -#define FE_AG_REG_FGA_AUR_CNT__W 5 -#define FE_AG_REG_FGA_AUR_CNT__M 0x1F -#define FE_AG_REG_FGA_AUR_CNT_INIT 0x0 - #define FE_AG_REG_FGA_RUR_CNT__A 0xC20058 -#define FE_AG_REG_FGA_RUR_CNT__W 5 -#define FE_AG_REG_FGA_RUR_CNT__M 0x1F -#define FE_AG_REG_FGA_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_FGA_AVE_DAT__A 0xC20059 -#define FE_AG_REG_FGA_AVE_DAT__W 10 -#define FE_AG_REG_FGA_AVE_DAT__M 0x3FF - -#define FE_AG_REG_FGC_RUR_CNT__A 0xC2005A -#define FE_AG_REG_FGC_RUR_CNT__W 5 -#define FE_AG_REG_FGC_RUR_CNT__M 0x1F -#define FE_AG_REG_FGC_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_FGC_SET_LVL__A 0xC2005B -#define FE_AG_REG_FGC_SET_LVL__W 9 -#define FE_AG_REG_FGC_SET_LVL__M 0x1FF -#define FE_AG_REG_FGC_SET_LVL_INIT 0x0 - -#define FE_AG_REG_FGC_FLA_RGN__A 0xC2005C -#define FE_AG_REG_FGC_FLA_RGN__W 9 -#define FE_AG_REG_FGC_FLA_RGN__M 0x1FF -#define FE_AG_REG_FGC_FLA_RGN_INIT 0x0 - -#define FE_AG_REG_FGC_JMP_PSN__A 0xC2005D -#define FE_AG_REG_FGC_JMP_PSN__W 4 -#define FE_AG_REG_FGC_JMP_PSN__M 0xF -#define FE_AG_REG_FGC_JMP_PSN_INIT 0x0 - -#define FE_AG_REG_FGC_FLA_STP__A 0xC2005E -#define FE_AG_REG_FGC_FLA_STP__W 16 -#define FE_AG_REG_FGC_FLA_STP__M 0xFFFF -#define FE_AG_REG_FGC_FLA_STP_INIT 0x0 - -#define FE_AG_REG_FGC_SLO_STP__A 0xC2005F -#define FE_AG_REG_FGC_SLO_STP__W 16 -#define FE_AG_REG_FGC_SLO_STP__M 0xFFFF -#define FE_AG_REG_FGC_SLO_STP_INIT 0x0 - -#define FE_AG_REG_FGC_MAP_DAT__A 0xC20060 -#define FE_AG_REG_FGC_MAP_DAT__W 10 -#define FE_AG_REG_FGC_MAP_DAT__M 0x3FF - #define FE_AG_REG_FGM_WRI__A 0xC20061 -#define FE_AG_REG_FGM_WRI__W 10 -#define FE_AG_REG_FGM_WRI__M 0x3FF -#define FE_AG_REG_FGM_WRI_INIT 0x20 - -#define FE_AG_REG_BGC_RUR_CNT__A 0xC20062 -#define FE_AG_REG_BGC_RUR_CNT__W 5 -#define FE_AG_REG_BGC_RUR_CNT__M 0x1F -#define FE_AG_REG_BGC_RUR_CNT_INIT 0x0 - -#define FE_AG_REG_BGC_SET_LVL__A 0xC20063 -#define FE_AG_REG_BGC_SET_LVL__W 9 -#define FE_AG_REG_BGC_SET_LVL__M 0x1FF -#define FE_AG_REG_BGC_SET_LVL_INIT 0x0 - -#define FE_AG_REG_BGC_FLA_RGN__A 0xC20064 -#define FE_AG_REG_BGC_FLA_RGN__W 9 -#define FE_AG_REG_BGC_FLA_RGN__M 0x1FF -#define FE_AG_REG_BGC_FLA_RGN_INIT 0x0 - -#define FE_AG_REG_BGC_JMP_PSN__A 0xC20065 -#define FE_AG_REG_BGC_JMP_PSN__W 4 -#define FE_AG_REG_BGC_JMP_PSN__M 0xF -#define FE_AG_REG_BGC_JMP_PSN_INIT 0x0 - -#define FE_AG_REG_BGC_FLA_STP__A 0xC20066 -#define FE_AG_REG_BGC_FLA_STP__W 16 -#define FE_AG_REG_BGC_FLA_STP__M 0xFFFF -#define FE_AG_REG_BGC_FLA_STP_INIT 0x0 - -#define FE_AG_REG_BGC_SLO_STP__A 0xC20067 -#define FE_AG_REG_BGC_SLO_STP__W 16 -#define FE_AG_REG_BGC_SLO_STP__M 0xFFFF -#define FE_AG_REG_BGC_SLO_STP_INIT 0x0 - #define FE_AG_REG_BGC_FGC_WRI__A 0xC20068 -#define FE_AG_REG_BGC_FGC_WRI__W 4 -#define FE_AG_REG_BGC_FGC_WRI__M 0xF -#define FE_AG_REG_BGC_FGC_WRI_INIT 0x7 - #define FE_AG_REG_BGC_CGC_WRI__A 0xC20069 -#define FE_AG_REG_BGC_CGC_WRI__W 2 -#define FE_AG_REG_BGC_CGC_WRI__M 0x3 -#define FE_AG_REG_BGC_CGC_WRI_INIT 0x1 - -#define FE_AG_REG_BGC_FGC_DAT__A 0xC2006A -#define FE_AG_REG_BGC_FGC_DAT__W 4 -#define FE_AG_REG_BGC_FGC_DAT__M 0xF - -#define FE_FS_SID 0x3 - #define FE_FS_REG_COMM_EXEC__A 0xC30000 -#define FE_FS_REG_COMM_EXEC__W 3 -#define FE_FS_REG_COMM_EXEC__M 0x7 -#define FE_FS_REG_COMM_EXEC_CTL__B 0 -#define FE_FS_REG_COMM_EXEC_CTL__W 3 -#define FE_FS_REG_COMM_EXEC_CTL__M 0x7 -#define FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_FS_REG_COMM_STATE__A 0xC30001 -#define FE_FS_REG_COMM_STATE__W 4 -#define FE_FS_REG_COMM_STATE__M 0xF - -#define FE_FS_REG_COMM_MB__A 0xC30002 -#define FE_FS_REG_COMM_MB__W 3 -#define FE_FS_REG_COMM_MB__M 0x7 -#define FE_FS_REG_COMM_MB_CTR__B 0 -#define FE_FS_REG_COMM_MB_CTR__W 1 -#define FE_FS_REG_COMM_MB_CTR__M 0x1 -#define FE_FS_REG_COMM_MB_CTR_OFF 0x0 -#define FE_FS_REG_COMM_MB_CTR_ON 0x1 -#define FE_FS_REG_COMM_MB_OBS__B 1 -#define FE_FS_REG_COMM_MB_OBS__W 1 -#define FE_FS_REG_COMM_MB_OBS__M 0x2 -#define FE_FS_REG_COMM_MB_OBS_OFF 0x0 -#define FE_FS_REG_COMM_MB_OBS_ON 0x2 -#define FE_FS_REG_COMM_MB_MUX__B 2 -#define FE_FS_REG_COMM_MB_MUX__W 1 -#define FE_FS_REG_COMM_MB_MUX__M 0x4 -#define FE_FS_REG_COMM_MB_MUX_REAL 0x0 -#define FE_FS_REG_COMM_MB_MUX_IMAG 0x4 - -#define FE_FS_REG_COMM_SERVICE0__A 0xC30003 -#define FE_FS_REG_COMM_SERVICE0__W 10 -#define FE_FS_REG_COMM_SERVICE0__M 0x3FF - -#define FE_FS_REG_COMM_SERVICE1__A 0xC30004 -#define FE_FS_REG_COMM_SERVICE1__W 11 -#define FE_FS_REG_COMM_SERVICE1__M 0x7FF - -#define FE_FS_REG_COMM_ACT__A 0xC30005 -#define FE_FS_REG_COMM_ACT__W 2 -#define FE_FS_REG_COMM_ACT__M 0x3 - -#define FE_FS_REG_COMM_CNT__A 0xC30006 -#define FE_FS_REG_COMM_CNT__W 16 -#define FE_FS_REG_COMM_CNT__M 0xFFFF - #define FE_FS_REG_ADD_INC_LOP__A 0xC30010 -#define FE_FS_REG_ADD_INC_LOP__W 16 -#define FE_FS_REG_ADD_INC_LOP__M 0xFFFF -#define FE_FS_REG_ADD_INC_LOP_INIT 0x0 - -#define FE_FS_REG_ADD_INC_HIP__A 0xC30011 -#define FE_FS_REG_ADD_INC_HIP__W 12 -#define FE_FS_REG_ADD_INC_HIP__M 0xFFF -#define FE_FS_REG_ADD_INC_HIP_INIT 0x0 - -#define FE_FS_REG_ADD_OFF__A 0xC30012 -#define FE_FS_REG_ADD_OFF__W 12 -#define FE_FS_REG_ADD_OFF__M 0xFFF -#define FE_FS_REG_ADD_OFF_INIT 0x0 - -#define FE_FS_REG_ADD_OFF_VAL__A 0xC30013 -#define FE_FS_REG_ADD_OFF_VAL__W 1 -#define FE_FS_REG_ADD_OFF_VAL__M 0x1 -#define FE_FS_REG_ADD_OFF_VAL_INIT 0x0 - -#define FE_FD_SID 0x4 - #define FE_FD_REG_COMM_EXEC__A 0xC40000 -#define FE_FD_REG_COMM_EXEC__W 3 -#define FE_FD_REG_COMM_EXEC__M 0x7 -#define FE_FD_REG_COMM_EXEC_CTL__B 0 -#define FE_FD_REG_COMM_EXEC_CTL__W 3 -#define FE_FD_REG_COMM_EXEC_CTL__M 0x7 -#define FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_FD_REG_COMM_MB__A 0xC40002 -#define FE_FD_REG_COMM_MB__W 3 -#define FE_FD_REG_COMM_MB__M 0x7 -#define FE_FD_REG_COMM_MB_CTR__B 0 -#define FE_FD_REG_COMM_MB_CTR__W 1 -#define FE_FD_REG_COMM_MB_CTR__M 0x1 -#define FE_FD_REG_COMM_MB_CTR_OFF 0x0 -#define FE_FD_REG_COMM_MB_CTR_ON 0x1 -#define FE_FD_REG_COMM_MB_OBS__B 1 -#define FE_FD_REG_COMM_MB_OBS__W 1 -#define FE_FD_REG_COMM_MB_OBS__M 0x2 -#define FE_FD_REG_COMM_MB_OBS_OFF 0x0 -#define FE_FD_REG_COMM_MB_OBS_ON 0x2 - -#define FE_FD_REG_COMM_SERVICE0__A 0xC40003 -#define FE_FD_REG_COMM_SERVICE0__W 10 -#define FE_FD_REG_COMM_SERVICE0__M 0x3FF -#define FE_FD_REG_COMM_SERVICE1__A 0xC40004 -#define FE_FD_REG_COMM_SERVICE1__W 11 -#define FE_FD_REG_COMM_SERVICE1__M 0x7FF - -#define FE_FD_REG_COMM_INT_STA__A 0xC40007 -#define FE_FD_REG_COMM_INT_STA__W 1 -#define FE_FD_REG_COMM_INT_STA__M 0x1 -#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define FE_FD_REG_COMM_INT_MSK__A 0xC40008 -#define FE_FD_REG_COMM_INT_MSK__W 1 -#define FE_FD_REG_COMM_INT_MSK__M 0x1 -#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - #define FE_FD_REG_SCL__A 0xC40010 -#define FE_FD_REG_SCL__W 6 -#define FE_FD_REG_SCL__M 0x3F - #define FE_FD_REG_MAX_LEV__A 0xC40011 -#define FE_FD_REG_MAX_LEV__W 3 -#define FE_FD_REG_MAX_LEV__M 0x7 - #define FE_FD_REG_NR__A 0xC40012 -#define FE_FD_REG_NR__W 5 -#define FE_FD_REG_NR__M 0x1F - -#define FE_FD_REG_MEAS_SEL__A 0xC40013 -#define FE_FD_REG_MEAS_SEL__W 1 -#define FE_FD_REG_MEAS_SEL__M 0x1 - #define FE_FD_REG_MEAS_VAL__A 0xC40014 -#define FE_FD_REG_MEAS_VAL__W 1 -#define FE_FD_REG_MEAS_VAL__M 0x1 - -#define FE_FD_REG_MAX__A 0xC40015 -#define FE_FD_REG_MAX__W 16 -#define FE_FD_REG_MAX__M 0xFFFF - -#define FE_FD_REG_POWER__A 0xC40016 -#define FE_FD_REG_POWER__W 10 -#define FE_FD_REG_POWER__M 0x3FF - -#define FE_IF_SID 0x5 - #define FE_IF_REG_COMM_EXEC__A 0xC50000 -#define FE_IF_REG_COMM_EXEC__W 3 -#define FE_IF_REG_COMM_EXEC__M 0x7 -#define FE_IF_REG_COMM_EXEC_CTL__B 0 -#define FE_IF_REG_COMM_EXEC_CTL__W 3 -#define FE_IF_REG_COMM_EXEC_CTL__M 0x7 -#define FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_IF_REG_COMM_MB__A 0xC50002 -#define FE_IF_REG_COMM_MB__W 3 -#define FE_IF_REG_COMM_MB__M 0x7 -#define FE_IF_REG_COMM_MB_CTR__B 0 -#define FE_IF_REG_COMM_MB_CTR__W 1 -#define FE_IF_REG_COMM_MB_CTR__M 0x1 -#define FE_IF_REG_COMM_MB_CTR_OFF 0x0 -#define FE_IF_REG_COMM_MB_CTR_ON 0x1 -#define FE_IF_REG_COMM_MB_OBS__B 1 -#define FE_IF_REG_COMM_MB_OBS__W 1 -#define FE_IF_REG_COMM_MB_OBS__M 0x2 -#define FE_IF_REG_COMM_MB_OBS_OFF 0x0 -#define FE_IF_REG_COMM_MB_OBS_ON 0x2 - #define FE_IF_REG_INCR0__A 0xC50010 #define FE_IF_REG_INCR0__W 16 #define FE_IF_REG_INCR0__M 0xFFFF -#define FE_IF_REG_INCR0_INIT 0x0 - #define FE_IF_REG_INCR1__A 0xC50011 -#define FE_IF_REG_INCR1__W 8 #define FE_IF_REG_INCR1__M 0xFF -#define FE_IF_REG_INCR1_INIT 0x28 - -#define FE_CF_SID 0x6 - #define FE_CF_REG_COMM_EXEC__A 0xC60000 -#define FE_CF_REG_COMM_EXEC__W 3 -#define FE_CF_REG_COMM_EXEC__M 0x7 -#define FE_CF_REG_COMM_EXEC_CTL__B 0 -#define FE_CF_REG_COMM_EXEC_CTL__W 3 -#define FE_CF_REG_COMM_EXEC_CTL__M 0x7 -#define FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_CF_REG_COMM_MB__A 0xC60002 -#define FE_CF_REG_COMM_MB__W 3 -#define FE_CF_REG_COMM_MB__M 0x7 -#define FE_CF_REG_COMM_MB_CTR__B 0 -#define FE_CF_REG_COMM_MB_CTR__W 1 -#define FE_CF_REG_COMM_MB_CTR__M 0x1 -#define FE_CF_REG_COMM_MB_CTR_OFF 0x0 -#define FE_CF_REG_COMM_MB_CTR_ON 0x1 -#define FE_CF_REG_COMM_MB_OBS__B 1 -#define FE_CF_REG_COMM_MB_OBS__W 1 -#define FE_CF_REG_COMM_MB_OBS__M 0x2 -#define FE_CF_REG_COMM_MB_OBS_OFF 0x0 -#define FE_CF_REG_COMM_MB_OBS_ON 0x2 - -#define FE_CF_REG_COMM_SERVICE0__A 0xC60003 -#define FE_CF_REG_COMM_SERVICE0__W 10 -#define FE_CF_REG_COMM_SERVICE0__M 0x3FF -#define FE_CF_REG_COMM_SERVICE1__A 0xC60004 -#define FE_CF_REG_COMM_SERVICE1__W 11 -#define FE_CF_REG_COMM_SERVICE1__M 0x7FF - -#define FE_CF_REG_COMM_INT_STA__A 0xC60007 -#define FE_CF_REG_COMM_INT_STA__W 2 -#define FE_CF_REG_COMM_INT_STA__M 0x3 -#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define FE_CF_REG_COMM_INT_MSK__A 0xC60008 -#define FE_CF_REG_COMM_INT_MSK__W 2 -#define FE_CF_REG_COMM_INT_MSK__M 0x3 -#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - #define FE_CF_REG_SCL__A 0xC60010 -#define FE_CF_REG_SCL__W 9 -#define FE_CF_REG_SCL__M 0x1FF - #define FE_CF_REG_MAX_LEV__A 0xC60011 -#define FE_CF_REG_MAX_LEV__W 3 -#define FE_CF_REG_MAX_LEV__M 0x7 - #define FE_CF_REG_NR__A 0xC60012 -#define FE_CF_REG_NR__W 5 -#define FE_CF_REG_NR__M 0x1F - #define FE_CF_REG_IMP_VAL__A 0xC60013 -#define FE_CF_REG_IMP_VAL__W 1 -#define FE_CF_REG_IMP_VAL__M 0x1 - #define FE_CF_REG_MEAS_VAL__A 0xC60014 -#define FE_CF_REG_MEAS_VAL__W 1 -#define FE_CF_REG_MEAS_VAL__M 0x1 - -#define FE_CF_REG_MAX__A 0xC60015 -#define FE_CF_REG_MAX__W 16 -#define FE_CF_REG_MAX__M 0xFFFF - -#define FE_CF_REG_POWER__A 0xC60016 -#define FE_CF_REG_POWER__W 10 -#define FE_CF_REG_POWER__M 0x3FF - -#define FE_CU_SID 0x7 - #define FE_CU_REG_COMM_EXEC__A 0xC70000 -#define FE_CU_REG_COMM_EXEC__W 3 -#define FE_CU_REG_COMM_EXEC__M 0x7 -#define FE_CU_REG_COMM_EXEC_CTL__B 0 -#define FE_CU_REG_COMM_EXEC_CTL__W 3 -#define FE_CU_REG_COMM_EXEC_CTL__M 0x7 -#define FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 -#define FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FE_CU_REG_COMM_STATE__A 0xC70001 -#define FE_CU_REG_COMM_STATE__W 4 -#define FE_CU_REG_COMM_STATE__M 0xF - -#define FE_CU_REG_COMM_MB__A 0xC70002 -#define FE_CU_REG_COMM_MB__W 3 -#define FE_CU_REG_COMM_MB__M 0x7 -#define FE_CU_REG_COMM_MB_CTR__B 0 -#define FE_CU_REG_COMM_MB_CTR__W 1 -#define FE_CU_REG_COMM_MB_CTR__M 0x1 -#define FE_CU_REG_COMM_MB_CTR_OFF 0x0 -#define FE_CU_REG_COMM_MB_CTR_ON 0x1 -#define FE_CU_REG_COMM_MB_OBS__B 1 -#define FE_CU_REG_COMM_MB_OBS__W 1 -#define FE_CU_REG_COMM_MB_OBS__M 0x2 -#define FE_CU_REG_COMM_MB_OBS_OFF 0x0 -#define FE_CU_REG_COMM_MB_OBS_ON 0x2 -#define FE_CU_REG_COMM_MB_MUX__B 2 -#define FE_CU_REG_COMM_MB_MUX__W 1 -#define FE_CU_REG_COMM_MB_MUX__M 0x4 -#define FE_CU_REG_COMM_MB_MUX_REAL 0x0 -#define FE_CU_REG_COMM_MB_MUX_IMAG 0x4 - -#define FE_CU_REG_COMM_SERVICE0__A 0xC70003 -#define FE_CU_REG_COMM_SERVICE0__W 10 -#define FE_CU_REG_COMM_SERVICE0__M 0x3FF - -#define FE_CU_REG_COMM_SERVICE1__A 0xC70004 -#define FE_CU_REG_COMM_SERVICE1__W 11 -#define FE_CU_REG_COMM_SERVICE1__M 0x7FF - -#define FE_CU_REG_COMM_ACT__A 0xC70005 -#define FE_CU_REG_COMM_ACT__W 2 -#define FE_CU_REG_COMM_ACT__M 0x3 - -#define FE_CU_REG_COMM_CNT__A 0xC70006 -#define FE_CU_REG_COMM_CNT__W 16 -#define FE_CU_REG_COMM_CNT__M 0xFFFF - -#define FE_CU_REG_COMM_INT_STA__A 0xC70007 -#define FE_CU_REG_COMM_INT_STA__W 2 -#define FE_CU_REG_COMM_INT_STA__M 0x3 -#define FE_CU_REG_COMM_INT_STA_FE_START__B 0 -#define FE_CU_REG_COMM_INT_STA_FE_START__W 1 -#define FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 -#define FE_CU_REG_COMM_INT_STA_FT_START__B 1 -#define FE_CU_REG_COMM_INT_STA_FT_START__W 1 -#define FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 - -#define FE_CU_REG_COMM_INT_MSK__A 0xC70008 -#define FE_CU_REG_COMM_INT_MSK__W 2 -#define FE_CU_REG_COMM_INT_MSK__M 0x3 -#define FE_CU_REG_COMM_INT_MSK_FE_START__B 0 -#define FE_CU_REG_COMM_INT_MSK_FE_START__W 1 -#define FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 -#define FE_CU_REG_COMM_INT_MSK_FT_START__B 1 -#define FE_CU_REG_COMM_INT_MSK_FT_START__W 1 -#define FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 - -#define FE_CU_REG_MODE__A 0xC70010 -#define FE_CU_REG_MODE__W 3 -#define FE_CU_REG_MODE__M 0x7 -#define FE_CU_REG_MODE_INIT 0x0 - -#define FE_CU_REG_MODE_FFT__B 0 -#define FE_CU_REG_MODE_FFT__W 1 -#define FE_CU_REG_MODE_FFT__M 0x1 -#define FE_CU_REG_MODE_FFT_M8K 0x0 -#define FE_CU_REG_MODE_FFT_M2K 0x1 - -#define FE_CU_REG_MODE_COR__B 1 -#define FE_CU_REG_MODE_COR__W 1 -#define FE_CU_REG_MODE_COR__M 0x2 -#define FE_CU_REG_MODE_COR_OFF 0x0 -#define FE_CU_REG_MODE_COR_ON 0x2 - -#define FE_CU_REG_MODE_IFD__B 2 -#define FE_CU_REG_MODE_IFD__W 1 -#define FE_CU_REG_MODE_IFD__M 0x4 -#define FE_CU_REG_MODE_IFD_ENABLE 0x0 -#define FE_CU_REG_MODE_IFD_DISABLE 0x4 - #define FE_CU_REG_FRM_CNT_RST__A 0xC70011 -#define FE_CU_REG_FRM_CNT_RST__W 15 -#define FE_CU_REG_FRM_CNT_RST__M 0x7FFF -#define FE_CU_REG_FRM_CNT_RST_INIT 0x0 - #define FE_CU_REG_FRM_CNT_STR__A 0xC70012 -#define FE_CU_REG_FRM_CNT_STR__W 15 -#define FE_CU_REG_FRM_CNT_STR__M 0x7FFF -#define FE_CU_REG_FRM_CNT_STR_INIT 0x0 - -#define FE_CU_REG_FRM_SMP_CNT__A 0xC70013 -#define FE_CU_REG_FRM_SMP_CNT__W 15 -#define FE_CU_REG_FRM_SMP_CNT__M 0x7FFF - -#define FE_CU_REG_FRM_SMB_CNT__A 0xC70014 -#define FE_CU_REG_FRM_SMB_CNT__W 16 -#define FE_CU_REG_FRM_SMB_CNT__M 0xFFFF - -#define FE_CU_REG_CMP_MAX_DAT__A 0xC70015 -#define FE_CU_REG_CMP_MAX_DAT__W 12 -#define FE_CU_REG_CMP_MAX_DAT__M 0xFFF - -#define FE_CU_REG_CMP_MAX_ADR__A 0xC70016 -#define FE_CU_REG_CMP_MAX_ADR__W 10 -#define FE_CU_REG_CMP_MAX_ADR__M 0x3FF - -#define FE_CU_REG_CTR_NF1_WLO__A 0xC70017 -#define FE_CU_REG_CTR_NF1_WLO__W 15 -#define FE_CU_REG_CTR_NF1_WLO__M 0x7FFF -#define FE_CU_REG_CTR_NF1_WLO_INIT 0x0 - -#define FE_CU_REG_CTR_NF1_WHI__A 0xC70018 -#define FE_CU_REG_CTR_NF1_WHI__W 15 -#define FE_CU_REG_CTR_NF1_WHI__M 0x7FFF -#define FE_CU_REG_CTR_NF1_WHI_INIT 0x0 - -#define FE_CU_REG_CTR_NF2_WLO__A 0xC70019 -#define FE_CU_REG_CTR_NF2_WLO__W 15 -#define FE_CU_REG_CTR_NF2_WLO__M 0x7FFF -#define FE_CU_REG_CTR_NF2_WLO_INIT 0x0 - -#define FE_CU_REG_CTR_NF2_WHI__A 0xC7001A -#define FE_CU_REG_CTR_NF2_WHI__W 15 -#define FE_CU_REG_CTR_NF2_WHI__M 0x7FFF -#define FE_CU_REG_CTR_NF2_WHI_INIT 0x0 - -#define FE_CU_REG_DIV_NF1_REA__A 0xC7001B -#define FE_CU_REG_DIV_NF1_REA__W 12 -#define FE_CU_REG_DIV_NF1_REA__M 0xFFF - -#define FE_CU_REG_DIV_NF1_IMA__A 0xC7001C -#define FE_CU_REG_DIV_NF1_IMA__W 12 -#define FE_CU_REG_DIV_NF1_IMA__M 0xFFF - -#define FE_CU_REG_DIV_NF2_REA__A 0xC7001D -#define FE_CU_REG_DIV_NF2_REA__W 12 -#define FE_CU_REG_DIV_NF2_REA__M 0xFFF - -#define FE_CU_REG_DIV_NF2_IMA__A 0xC7001E -#define FE_CU_REG_DIV_NF2_IMA__W 12 -#define FE_CU_REG_DIV_NF2_IMA__M 0xFFF - -#define FE_CU_BUF_RAM__A 0xC80000 - -#define FE_CU_CMP_RAM__A 0xC90000 - -#define FT_SID 0x8 - #define FT_COMM_EXEC__A 0x1000000 -#define FT_COMM_EXEC__W 3 -#define FT_COMM_EXEC__M 0x7 -#define FT_COMM_EXEC_CTL__B 0 -#define FT_COMM_EXEC_CTL__W 3 -#define FT_COMM_EXEC_CTL__M 0x7 -#define FT_COMM_EXEC_CTL_STOP 0x0 -#define FT_COMM_EXEC_CTL_ACTIVE 0x1 -#define FT_COMM_EXEC_CTL_HOLD 0x2 -#define FT_COMM_EXEC_CTL_STEP 0x3 -#define FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define FT_COMM_STATE__A 0x1000001 -#define FT_COMM_STATE__W 16 -#define FT_COMM_STATE__M 0xFFFF -#define FT_COMM_MB__A 0x1000002 -#define FT_COMM_MB__W 16 -#define FT_COMM_MB__M 0xFFFF -#define FT_COMM_SERVICE0__A 0x1000003 -#define FT_COMM_SERVICE0__W 16 -#define FT_COMM_SERVICE0__M 0xFFFF -#define FT_COMM_SERVICE1__A 0x1000004 -#define FT_COMM_SERVICE1__W 16 -#define FT_COMM_SERVICE1__M 0xFFFF -#define FT_COMM_INT_STA__A 0x1000007 -#define FT_COMM_INT_STA__W 16 -#define FT_COMM_INT_STA__M 0xFFFF -#define FT_COMM_INT_MSK__A 0x1000008 -#define FT_COMM_INT_MSK__W 16 -#define FT_COMM_INT_MSK__M 0xFFFF - #define FT_REG_COMM_EXEC__A 0x1010000 -#define FT_REG_COMM_EXEC__W 3 -#define FT_REG_COMM_EXEC__M 0x7 -#define FT_REG_COMM_EXEC_CTL__B 0 -#define FT_REG_COMM_EXEC_CTL__W 3 -#define FT_REG_COMM_EXEC_CTL__M 0x7 -#define FT_REG_COMM_EXEC_CTL_STOP 0x0 -#define FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define FT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define FT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define FT_REG_COMM_MB__A 0x1010002 -#define FT_REG_COMM_MB__W 3 -#define FT_REG_COMM_MB__M 0x7 -#define FT_REG_COMM_MB_CTR__B 0 -#define FT_REG_COMM_MB_CTR__W 1 -#define FT_REG_COMM_MB_CTR__M 0x1 -#define FT_REG_COMM_MB_CTR_OFF 0x0 -#define FT_REG_COMM_MB_CTR_ON 0x1 -#define FT_REG_COMM_MB_OBS__B 1 -#define FT_REG_COMM_MB_OBS__W 1 -#define FT_REG_COMM_MB_OBS__M 0x2 -#define FT_REG_COMM_MB_OBS_OFF 0x0 -#define FT_REG_COMM_MB_OBS_ON 0x2 - -#define FT_REG_COMM_SERVICE0__A 0x1010003 -#define FT_REG_COMM_SERVICE0__W 10 -#define FT_REG_COMM_SERVICE0__M 0x3FF -#define FT_REG_COMM_SERVICE0_FT__B 8 -#define FT_REG_COMM_SERVICE0_FT__W 1 -#define FT_REG_COMM_SERVICE0_FT__M 0x100 - -#define FT_REG_COMM_SERVICE1__A 0x1010004 -#define FT_REG_COMM_SERVICE1__W 11 -#define FT_REG_COMM_SERVICE1__M 0x7FF - -#define FT_REG_COMM_INT_STA__A 0x1010007 -#define FT_REG_COMM_INT_STA__W 2 -#define FT_REG_COMM_INT_STA__M 0x3 -#define FT_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define FT_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define FT_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define FT_REG_COMM_INT_MSK__A 0x1010008 -#define FT_REG_COMM_INT_MSK__W 2 -#define FT_REG_COMM_INT_MSK__M 0x3 -#define FT_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define FT_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define FT_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - -#define FT_REG_MODE_2K__A 0x1010010 -#define FT_REG_MODE_2K__W 1 -#define FT_REG_MODE_2K__M 0x1 -#define FT_REG_MODE_2K_MODE_8K 0x0 -#define FT_REG_MODE_2K_MODE_2K 0x1 -#define FT_REG_MODE_2K_INIT 0x0 - -#define FT_REG_BUS_MOD__A 0x1010011 -#define FT_REG_BUS_MOD__W 1 -#define FT_REG_BUS_MOD__M 0x1 -#define FT_REG_BUS_MOD_INPUT 0x0 -#define FT_REG_BUS_MOD_PILOT 0x1 -#define FT_REG_BUS_MOD_INIT 0x0 - -#define FT_REG_BUS_REAL__A 0x1010012 -#define FT_REG_BUS_REAL__W 10 -#define FT_REG_BUS_REAL__M 0x3FF -#define FT_REG_BUS_REAL_INIT 0x0 - -#define FT_REG_BUS_IMAG__A 0x1010013 -#define FT_REG_BUS_IMAG__W 10 -#define FT_REG_BUS_IMAG__M 0x3FF -#define FT_REG_BUS_IMAG_INIT 0x0 - -#define FT_REG_BUS_VAL__A 0x1010014 -#define FT_REG_BUS_VAL__W 1 -#define FT_REG_BUS_VAL__M 0x1 -#define FT_REG_BUS_VAL_INIT 0x0 - -#define FT_REG_PEAK__A 0x1010015 -#define FT_REG_PEAK__W 11 -#define FT_REG_PEAK__M 0x7FF -#define FT_REG_PEAK_INIT 0x0 - -#define FT_REG_NORM_OFF__A 0x1010016 -#define FT_REG_NORM_OFF__W 4 -#define FT_REG_NORM_OFF__M 0xF -#define FT_REG_NORM_OFF_INIT 0x2 - -#define FT_ST1_RAM__A 0x1020000 - -#define FT_ST2_RAM__A 0x1030000 - -#define FT_ST3_RAM__A 0x1040000 - -#define FT_ST5_RAM__A 0x1050000 - -#define FT_ST6_RAM__A 0x1060000 - -#define FT_ST8_RAM__A 0x1070000 - -#define FT_ST9_RAM__A 0x1080000 - -#define CP_SID 0x9 - #define CP_COMM_EXEC__A 0x1400000 -#define CP_COMM_EXEC__W 3 -#define CP_COMM_EXEC__M 0x7 -#define CP_COMM_EXEC_CTL__B 0 -#define CP_COMM_EXEC_CTL__W 3 -#define CP_COMM_EXEC_CTL__M 0x7 -#define CP_COMM_EXEC_CTL_STOP 0x0 -#define CP_COMM_EXEC_CTL_ACTIVE 0x1 -#define CP_COMM_EXEC_CTL_HOLD 0x2 -#define CP_COMM_EXEC_CTL_STEP 0x3 -#define CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define CP_COMM_STATE__A 0x1400001 -#define CP_COMM_STATE__W 16 -#define CP_COMM_STATE__M 0xFFFF -#define CP_COMM_MB__A 0x1400002 -#define CP_COMM_MB__W 16 -#define CP_COMM_MB__M 0xFFFF -#define CP_COMM_SERVICE0__A 0x1400003 -#define CP_COMM_SERVICE0__W 16 -#define CP_COMM_SERVICE0__M 0xFFFF -#define CP_COMM_SERVICE1__A 0x1400004 -#define CP_COMM_SERVICE1__W 16 -#define CP_COMM_SERVICE1__M 0xFFFF -#define CP_COMM_INT_STA__A 0x1400007 -#define CP_COMM_INT_STA__W 16 -#define CP_COMM_INT_STA__M 0xFFFF -#define CP_COMM_INT_MSK__A 0x1400008 -#define CP_COMM_INT_MSK__W 16 -#define CP_COMM_INT_MSK__M 0xFFFF - #define CP_REG_COMM_EXEC__A 0x1410000 -#define CP_REG_COMM_EXEC__W 3 -#define CP_REG_COMM_EXEC__M 0x7 -#define CP_REG_COMM_EXEC_CTL__B 0 -#define CP_REG_COMM_EXEC_CTL__W 3 -#define CP_REG_COMM_EXEC_CTL__M 0x7 -#define CP_REG_COMM_EXEC_CTL_STOP 0x0 -#define CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define CP_REG_COMM_EXEC_CTL_HOLD 0x2 -#define CP_REG_COMM_EXEC_CTL_STEP 0x3 - -#define CP_REG_COMM_MB__A 0x1410002 -#define CP_REG_COMM_MB__W 3 -#define CP_REG_COMM_MB__M 0x7 -#define CP_REG_COMM_MB_CTR__B 0 -#define CP_REG_COMM_MB_CTR__W 1 -#define CP_REG_COMM_MB_CTR__M 0x1 -#define CP_REG_COMM_MB_CTR_OFF 0x0 -#define CP_REG_COMM_MB_CTR_ON 0x1 -#define CP_REG_COMM_MB_OBS__B 1 -#define CP_REG_COMM_MB_OBS__W 1 -#define CP_REG_COMM_MB_OBS__M 0x2 -#define CP_REG_COMM_MB_OBS_OFF 0x0 -#define CP_REG_COMM_MB_OBS_ON 0x2 - -#define CP_REG_COMM_SERVICE0__A 0x1410003 -#define CP_REG_COMM_SERVICE0__W 10 -#define CP_REG_COMM_SERVICE0__M 0x3FF -#define CP_REG_COMM_SERVICE0_CP__B 9 -#define CP_REG_COMM_SERVICE0_CP__W 1 -#define CP_REG_COMM_SERVICE0_CP__M 0x200 - -#define CP_REG_COMM_SERVICE1__A 0x1410004 -#define CP_REG_COMM_SERVICE1__W 11 -#define CP_REG_COMM_SERVICE1__M 0x7FF - -#define CP_REG_COMM_INT_STA__A 0x1410007 -#define CP_REG_COMM_INT_STA__W 2 -#define CP_REG_COMM_INT_STA__M 0x3 -#define CP_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define CP_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define CP_REG_COMM_INT_MSK__A 0x1410008 -#define CP_REG_COMM_INT_MSK__W 2 -#define CP_REG_COMM_INT_MSK__M 0x3 -#define CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - -#define CP_REG_MODE_2K__A 0x1410010 -#define CP_REG_MODE_2K__W 1 -#define CP_REG_MODE_2K__M 0x1 -#define CP_REG_MODE_2K_INIT 0x0 - #define CP_REG_INTERVAL__A 0x1410011 -#define CP_REG_INTERVAL__W 4 -#define CP_REG_INTERVAL__M 0xF -#define CP_REG_INTERVAL_INIT 0x5 - -#define CP_REG_SKIP_START0__A 0x1410012 -#define CP_REG_SKIP_START0__W 13 -#define CP_REG_SKIP_START0__M 0x1FFF -#define CP_REG_SKIP_START0_INIT 0x0 - -#define CP_REG_SKIP_STOP0__A 0x1410013 -#define CP_REG_SKIP_STOP0__W 13 -#define CP_REG_SKIP_STOP0__M 0x1FFF -#define CP_REG_SKIP_STOP0_INIT 0x0 - -#define CP_REG_SKIP_START1__A 0x1410014 -#define CP_REG_SKIP_START1__W 13 -#define CP_REG_SKIP_START1__M 0x1FFF -#define CP_REG_SKIP_START1_INIT 0x0 - -#define CP_REG_SKIP_STOP1__A 0x1410015 -#define CP_REG_SKIP_STOP1__W 13 -#define CP_REG_SKIP_STOP1__M 0x1FFF -#define CP_REG_SKIP_STOP1_INIT 0x0 - -#define CP_REG_SKIP_START2__A 0x1410016 -#define CP_REG_SKIP_START2__W 13 -#define CP_REG_SKIP_START2__M 0x1FFF -#define CP_REG_SKIP_START2_INIT 0x0 - -#define CP_REG_SKIP_STOP2__A 0x1410017 -#define CP_REG_SKIP_STOP2__W 13 -#define CP_REG_SKIP_STOP2__M 0x1FFF -#define CP_REG_SKIP_STOP2_INIT 0x0 - -#define CP_REG_SKIP_ENA__A 0x1410018 -#define CP_REG_SKIP_ENA__W 3 -#define CP_REG_SKIP_ENA__M 0x7 - -#define CP_REG_SKIP_ENA_CPL__B 0 -#define CP_REG_SKIP_ENA_CPL__W 1 -#define CP_REG_SKIP_ENA_CPL__M 0x1 - -#define CP_REG_SKIP_ENA_SPD__B 1 -#define CP_REG_SKIP_ENA_SPD__W 1 -#define CP_REG_SKIP_ENA_SPD__M 0x2 - -#define CP_REG_SKIP_ENA_CPD__B 2 -#define CP_REG_SKIP_ENA_CPD__W 1 -#define CP_REG_SKIP_ENA_CPD__M 0x4 -#define CP_REG_SKIP_ENA_INIT 0x0 - -#define CP_REG_BR_MODE_MIX__A 0x1410020 -#define CP_REG_BR_MODE_MIX__W 1 -#define CP_REG_BR_MODE_MIX__M 0x1 -#define CP_REG_BR_MODE_MIX_INIT 0x0 - -#define CP_REG_BR_SMB_NR__A 0x1410021 -#define CP_REG_BR_SMB_NR__W 3 -#define CP_REG_BR_SMB_NR__M 0x7 - -#define CP_REG_BR_SMB_NR_SMB__B 0 -#define CP_REG_BR_SMB_NR_SMB__W 2 -#define CP_REG_BR_SMB_NR_SMB__M 0x3 - -#define CP_REG_BR_SMB_NR_VAL__B 2 -#define CP_REG_BR_SMB_NR_VAL__W 1 -#define CP_REG_BR_SMB_NR_VAL__M 0x4 -#define CP_REG_BR_SMB_NR_INIT 0x0 - -#define CP_REG_BR_CP_SMB_NR__A 0x1410022 -#define CP_REG_BR_CP_SMB_NR__W 2 -#define CP_REG_BR_CP_SMB_NR__M 0x3 -#define CP_REG_BR_CP_SMB_NR_INIT 0x0 - #define CP_REG_BR_SPL_OFFSET__A 0x1410023 -#define CP_REG_BR_SPL_OFFSET__W 3 -#define CP_REG_BR_SPL_OFFSET__M 0x7 -#define CP_REG_BR_SPL_OFFSET_INIT 0x0 - #define CP_REG_BR_STR_DEL__A 0x1410024 -#define CP_REG_BR_STR_DEL__W 10 -#define CP_REG_BR_STR_DEL__M 0x3FF -#define CP_REG_BR_STR_DEL_INIT 0xA - #define CP_REG_RT_ANG_INC0__A 0x1410030 -#define CP_REG_RT_ANG_INC0__W 16 -#define CP_REG_RT_ANG_INC0__M 0xFFFF -#define CP_REG_RT_ANG_INC0_INIT 0x0 - #define CP_REG_RT_ANG_INC1__A 0x1410031 -#define CP_REG_RT_ANG_INC1__W 8 -#define CP_REG_RT_ANG_INC1__M 0xFF -#define CP_REG_RT_ANG_INC1_INIT 0x0 - #define CP_REG_RT_DETECT_ENA__A 0x1410032 -#define CP_REG_RT_DETECT_ENA__W 2 -#define CP_REG_RT_DETECT_ENA__M 0x3 - -#define CP_REG_RT_DETECT_ENA_SCATTERED__B 0 -#define CP_REG_RT_DETECT_ENA_SCATTERED__W 1 -#define CP_REG_RT_DETECT_ENA_SCATTERED__M 0x1 - -#define CP_REG_RT_DETECT_ENA_CONTINUOUS__B 1 -#define CP_REG_RT_DETECT_ENA_CONTINUOUS__W 1 -#define CP_REG_RT_DETECT_ENA_CONTINUOUS__M 0x2 -#define CP_REG_RT_DETECT_ENA_INIT 0x0 - #define CP_REG_RT_DETECT_TRH__A 0x1410033 -#define CP_REG_RT_DETECT_TRH__W 2 -#define CP_REG_RT_DETECT_TRH__M 0x3 -#define CP_REG_RT_DETECT_TRH_INIT 0x3 - -#define CP_REG_RT_SPD_RELIABLE__A 0x1410034 -#define CP_REG_RT_SPD_RELIABLE__W 3 -#define CP_REG_RT_SPD_RELIABLE__M 0x7 -#define CP_REG_RT_SPD_RELIABLE_INIT 0x0 - -#define CP_REG_RT_SPD_DIRECTION__A 0x1410035 -#define CP_REG_RT_SPD_DIRECTION__W 1 -#define CP_REG_RT_SPD_DIRECTION__M 0x1 -#define CP_REG_RT_SPD_DIRECTION_INIT 0x0 - -#define CP_REG_RT_SPD_MOD__A 0x1410036 -#define CP_REG_RT_SPD_MOD__W 2 -#define CP_REG_RT_SPD_MOD__M 0x3 -#define CP_REG_RT_SPD_MOD_INIT 0x0 - -#define CP_REG_RT_SPD_SMB__A 0x1410037 -#define CP_REG_RT_SPD_SMB__W 2 -#define CP_REG_RT_SPD_SMB__M 0x3 -#define CP_REG_RT_SPD_SMB_INIT 0x0 - -#define CP_REG_RT_CPD_MODE__A 0x1410038 -#define CP_REG_RT_CPD_MODE__W 3 -#define CP_REG_RT_CPD_MODE__M 0x7 - -#define CP_REG_RT_CPD_MODE_MOD3__B 0 -#define CP_REG_RT_CPD_MODE_MOD3__W 2 -#define CP_REG_RT_CPD_MODE_MOD3__M 0x3 - -#define CP_REG_RT_CPD_MODE_ADD__B 2 -#define CP_REG_RT_CPD_MODE_ADD__W 1 -#define CP_REG_RT_CPD_MODE_ADD__M 0x4 -#define CP_REG_RT_CPD_MODE_INIT 0x0 - -#define CP_REG_RT_CPD_RELIABLE__A 0x1410039 -#define CP_REG_RT_CPD_RELIABLE__W 3 -#define CP_REG_RT_CPD_RELIABLE__M 0x7 -#define CP_REG_RT_CPD_RELIABLE_INIT 0x0 - -#define CP_REG_RT_CPD_BIN__A 0x141003A -#define CP_REG_RT_CPD_BIN__W 5 -#define CP_REG_RT_CPD_BIN__M 0x1F -#define CP_REG_RT_CPD_BIN_INIT 0x0 - -#define CP_REG_RT_CPD_MAX__A 0x141003B -#define CP_REG_RT_CPD_MAX__W 4 -#define CP_REG_RT_CPD_MAX__M 0xF -#define CP_REG_RT_CPD_MAX_INIT 0x0 - -#define CP_REG_RT_SUPR_VAL__A 0x141003C -#define CP_REG_RT_SUPR_VAL__W 2 -#define CP_REG_RT_SUPR_VAL__M 0x3 - -#define CP_REG_RT_SUPR_VAL_CE__B 0 -#define CP_REG_RT_SUPR_VAL_CE__W 1 -#define CP_REG_RT_SUPR_VAL_CE__M 0x1 - -#define CP_REG_RT_SUPR_VAL_DL__B 1 -#define CP_REG_RT_SUPR_VAL_DL__W 1 -#define CP_REG_RT_SUPR_VAL_DL__M 0x2 -#define CP_REG_RT_SUPR_VAL_INIT 0x0 - -#define CP_REG_RT_EXP_AVE__A 0x141003D -#define CP_REG_RT_EXP_AVE__W 5 -#define CP_REG_RT_EXP_AVE__M 0x1F -#define CP_REG_RT_EXP_AVE_INIT 0x0 - #define CP_REG_RT_EXP_MARG__A 0x141003E -#define CP_REG_RT_EXP_MARG__W 5 -#define CP_REG_RT_EXP_MARG__M 0x1F -#define CP_REG_RT_EXP_MARG_INIT 0x0 - #define CP_REG_AC_NEXP_OFFS__A 0x1410040 -#define CP_REG_AC_NEXP_OFFS__W 8 -#define CP_REG_AC_NEXP_OFFS__M 0xFF -#define CP_REG_AC_NEXP_OFFS_INIT 0x0 - #define CP_REG_AC_AVER_POW__A 0x1410041 -#define CP_REG_AC_AVER_POW__W 8 -#define CP_REG_AC_AVER_POW__M 0xFF -#define CP_REG_AC_AVER_POW_INIT 0x5F - #define CP_REG_AC_MAX_POW__A 0x1410042 -#define CP_REG_AC_MAX_POW__W 8 -#define CP_REG_AC_MAX_POW__M 0xFF -#define CP_REG_AC_MAX_POW_INIT 0x7A - #define CP_REG_AC_WEIGHT_MAN__A 0x1410043 -#define CP_REG_AC_WEIGHT_MAN__W 6 -#define CP_REG_AC_WEIGHT_MAN__M 0x3F -#define CP_REG_AC_WEIGHT_MAN_INIT 0x31 - #define CP_REG_AC_WEIGHT_EXP__A 0x1410044 -#define CP_REG_AC_WEIGHT_EXP__W 5 -#define CP_REG_AC_WEIGHT_EXP__M 0x1F -#define CP_REG_AC_WEIGHT_EXP_INIT 0x10 - -#define CP_REG_AC_GAIN_MAN__A 0x1410045 -#define CP_REG_AC_GAIN_MAN__W 16 -#define CP_REG_AC_GAIN_MAN__M 0xFFFF -#define CP_REG_AC_GAIN_MAN_INIT 0x0 - -#define CP_REG_AC_GAIN_EXP__A 0x1410046 -#define CP_REG_AC_GAIN_EXP__W 5 -#define CP_REG_AC_GAIN_EXP__M 0x1F -#define CP_REG_AC_GAIN_EXP_INIT 0x0 - #define CP_REG_AC_AMP_MODE__A 0x1410047 -#define CP_REG_AC_AMP_MODE__W 2 -#define CP_REG_AC_AMP_MODE__M 0x3 -#define CP_REG_AC_AMP_MODE_NEW 0x0 -#define CP_REG_AC_AMP_MODE_OLD 0x1 -#define CP_REG_AC_AMP_MODE_FIXED 0x2 -#define CP_REG_AC_AMP_MODE_INIT 0x2 - #define CP_REG_AC_AMP_FIX__A 0x1410048 -#define CP_REG_AC_AMP_FIX__W 14 -#define CP_REG_AC_AMP_FIX__M 0x3FFF -#define CP_REG_AC_AMP_FIX_INIT 0x1FF - -#define CP_REG_AC_AMP_READ__A 0x1410049 -#define CP_REG_AC_AMP_READ__W 14 -#define CP_REG_AC_AMP_READ__M 0x3FFF -#define CP_REG_AC_AMP_READ_INIT 0x0 - #define CP_REG_AC_ANG_MODE__A 0x141004A -#define CP_REG_AC_ANG_MODE__W 2 -#define CP_REG_AC_ANG_MODE__M 0x3 -#define CP_REG_AC_ANG_MODE_NEW 0x0 -#define CP_REG_AC_ANG_MODE_OLD 0x1 -#define CP_REG_AC_ANG_MODE_NO_INT 0x2 -#define CP_REG_AC_ANG_MODE_OFFSET 0x3 -#define CP_REG_AC_ANG_MODE_INIT 0x3 - -#define CP_REG_AC_ANG_OFFS__A 0x141004B -#define CP_REG_AC_ANG_OFFS__W 14 -#define CP_REG_AC_ANG_OFFS__M 0x3FFF -#define CP_REG_AC_ANG_OFFS_INIT 0x0 - -#define CP_REG_AC_ANG_READ__A 0x141004C -#define CP_REG_AC_ANG_READ__W 16 -#define CP_REG_AC_ANG_READ__M 0xFFFF -#define CP_REG_AC_ANG_READ_INIT 0x0 - -#define CP_REG_DL_MB_WR_ADDR__A 0x1410050 -#define CP_REG_DL_MB_WR_ADDR__W 15 -#define CP_REG_DL_MB_WR_ADDR__M 0x7FFF -#define CP_REG_DL_MB_WR_ADDR_INIT 0x0 - -#define CP_REG_DL_MB_WR_CTR__A 0x1410051 -#define CP_REG_DL_MB_WR_CTR__W 5 -#define CP_REG_DL_MB_WR_CTR__M 0x1F - -#define CP_REG_DL_MB_WR_CTR_WORD__B 2 -#define CP_REG_DL_MB_WR_CTR_WORD__W 3 -#define CP_REG_DL_MB_WR_CTR_WORD__M 0x1C - -#define CP_REG_DL_MB_WR_CTR_OBS__B 1 -#define CP_REG_DL_MB_WR_CTR_OBS__W 1 -#define CP_REG_DL_MB_WR_CTR_OBS__M 0x2 - -#define CP_REG_DL_MB_WR_CTR_CTR__B 0 -#define CP_REG_DL_MB_WR_CTR_CTR__W 1 -#define CP_REG_DL_MB_WR_CTR_CTR__M 0x1 -#define CP_REG_DL_MB_WR_CTR_INIT 0x0 - -#define CP_REG_DL_MB_RD_ADDR__A 0x1410052 -#define CP_REG_DL_MB_RD_ADDR__W 15 -#define CP_REG_DL_MB_RD_ADDR__M 0x7FFF -#define CP_REG_DL_MB_RD_ADDR_INIT 0x0 - -#define CP_REG_DL_MB_RD_CTR__A 0x1410053 -#define CP_REG_DL_MB_RD_CTR__W 11 -#define CP_REG_DL_MB_RD_CTR__M 0x7FF - -#define CP_REG_DL_MB_RD_CTR_TEST__B 10 -#define CP_REG_DL_MB_RD_CTR_TEST__W 1 -#define CP_REG_DL_MB_RD_CTR_TEST__M 0x400 - -#define CP_REG_DL_MB_RD_CTR_OFFSET__B 8 -#define CP_REG_DL_MB_RD_CTR_OFFSET__W 2 -#define CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 - -#define CP_REG_DL_MB_RD_CTR_VALID__B 5 -#define CP_REG_DL_MB_RD_CTR_VALID__W 3 -#define CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 - -#define CP_REG_DL_MB_RD_CTR_WORD__B 2 -#define CP_REG_DL_MB_RD_CTR_WORD__W 3 -#define CP_REG_DL_MB_RD_CTR_WORD__M 0x1C - -#define CP_REG_DL_MB_RD_CTR_OBS__B 1 -#define CP_REG_DL_MB_RD_CTR_OBS__W 1 -#define CP_REG_DL_MB_RD_CTR_OBS__M 0x2 - -#define CP_REG_DL_MB_RD_CTR_CTR__B 0 -#define CP_REG_DL_MB_RD_CTR_CTR__W 1 -#define CP_REG_DL_MB_RD_CTR_CTR__M 0x1 -#define CP_REG_DL_MB_RD_CTR_INIT 0x0 - -#define CP_BR_BUF_RAM__A 0x1420000 - -#define CP_BR_CPL_RAM__A 0x1430000 - -#define CP_PB_DL0_RAM__A 0x1440000 - -#define CP_PB_DL1_RAM__A 0x1450000 - -#define CP_PB_DL2_RAM__A 0x1460000 - -#define CE_SID 0xA - #define CE_COMM_EXEC__A 0x1800000 -#define CE_COMM_EXEC__W 3 -#define CE_COMM_EXEC__M 0x7 -#define CE_COMM_EXEC_CTL__B 0 -#define CE_COMM_EXEC_CTL__W 3 -#define CE_COMM_EXEC_CTL__M 0x7 -#define CE_COMM_EXEC_CTL_STOP 0x0 -#define CE_COMM_EXEC_CTL_ACTIVE 0x1 -#define CE_COMM_EXEC_CTL_HOLD 0x2 -#define CE_COMM_EXEC_CTL_STEP 0x3 -#define CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define CE_COMM_STATE__A 0x1800001 -#define CE_COMM_STATE__W 16 -#define CE_COMM_STATE__M 0xFFFF -#define CE_COMM_MB__A 0x1800002 -#define CE_COMM_MB__W 16 -#define CE_COMM_MB__M 0xFFFF -#define CE_COMM_SERVICE0__A 0x1800003 -#define CE_COMM_SERVICE0__W 16 -#define CE_COMM_SERVICE0__M 0xFFFF -#define CE_COMM_SERVICE1__A 0x1800004 -#define CE_COMM_SERVICE1__W 16 -#define CE_COMM_SERVICE1__M 0xFFFF -#define CE_COMM_INT_STA__A 0x1800007 -#define CE_COMM_INT_STA__W 16 -#define CE_COMM_INT_STA__M 0xFFFF -#define CE_COMM_INT_MSK__A 0x1800008 -#define CE_COMM_INT_MSK__W 16 -#define CE_COMM_INT_MSK__M 0xFFFF - #define CE_REG_COMM_EXEC__A 0x1810000 -#define CE_REG_COMM_EXEC__W 3 -#define CE_REG_COMM_EXEC__M 0x7 -#define CE_REG_COMM_EXEC_CTL__B 0 -#define CE_REG_COMM_EXEC_CTL__W 3 -#define CE_REG_COMM_EXEC_CTL__M 0x7 -#define CE_REG_COMM_EXEC_CTL_STOP 0x0 -#define CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define CE_REG_COMM_EXEC_CTL_HOLD 0x2 -#define CE_REG_COMM_EXEC_CTL_STEP 0x3 - -#define CE_REG_COMM_MB__A 0x1810002 -#define CE_REG_COMM_MB__W 4 -#define CE_REG_COMM_MB__M 0xF -#define CE_REG_COMM_MB_CTR__B 0 -#define CE_REG_COMM_MB_CTR__W 1 -#define CE_REG_COMM_MB_CTR__M 0x1 -#define CE_REG_COMM_MB_CTR_OFF 0x0 -#define CE_REG_COMM_MB_CTR_ON 0x1 -#define CE_REG_COMM_MB_OBS__B 1 -#define CE_REG_COMM_MB_OBS__W 1 -#define CE_REG_COMM_MB_OBS__M 0x2 -#define CE_REG_COMM_MB_OBS_OFF 0x0 -#define CE_REG_COMM_MB_OBS_ON 0x2 -#define CE_REG_COMM_MB_OBS_SEL__B 2 -#define CE_REG_COMM_MB_OBS_SEL__W 2 -#define CE_REG_COMM_MB_OBS_SEL__M 0xC -#define CE_REG_COMM_MB_OBS_SEL_FI 0x0 -#define CE_REG_COMM_MB_OBS_SEL_TP 0x4 -#define CE_REG_COMM_MB_OBS_SEL_TI 0x8 -#define CE_REG_COMM_MB_OBS_SEL_FR 0x8 - -#define CE_REG_COMM_SERVICE0__A 0x1810003 -#define CE_REG_COMM_SERVICE0__W 10 -#define CE_REG_COMM_SERVICE0__M 0x3FF -#define CE_REG_COMM_SERVICE0_FT__B 8 -#define CE_REG_COMM_SERVICE0_FT__W 1 -#define CE_REG_COMM_SERVICE0_FT__M 0x100 - -#define CE_REG_COMM_SERVICE1__A 0x1810004 -#define CE_REG_COMM_SERVICE1__W 11 -#define CE_REG_COMM_SERVICE1__M 0x7FF - -#define CE_REG_COMM_INT_STA__A 0x1810007 -#define CE_REG_COMM_INT_STA__W 3 -#define CE_REG_COMM_INT_STA__M 0x7 -#define CE_REG_COMM_INT_STA_CE_PE__B 0 -#define CE_REG_COMM_INT_STA_CE_PE__W 1 -#define CE_REG_COMM_INT_STA_CE_PE__M 0x1 -#define CE_REG_COMM_INT_STA_CE_IR__B 1 -#define CE_REG_COMM_INT_STA_CE_IR__W 1 -#define CE_REG_COMM_INT_STA_CE_IR__M 0x2 -#define CE_REG_COMM_INT_STA_CE_FI__B 2 -#define CE_REG_COMM_INT_STA_CE_FI__W 1 -#define CE_REG_COMM_INT_STA_CE_FI__M 0x4 - -#define CE_REG_COMM_INT_MSK__A 0x1810008 -#define CE_REG_COMM_INT_MSK__W 3 -#define CE_REG_COMM_INT_MSK__M 0x7 -#define CE_REG_COMM_INT_MSK_CE_PE__B 0 -#define CE_REG_COMM_INT_MSK_CE_PE__W 1 -#define CE_REG_COMM_INT_MSK_CE_PE__M 0x1 -#define CE_REG_COMM_INT_MSK_CE_IR__B 1 -#define CE_REG_COMM_INT_MSK_CE_IR__W 1 -#define CE_REG_COMM_INT_MSK_CE_IR__M 0x2 -#define CE_REG_COMM_INT_MSK_CE_FI__B 2 -#define CE_REG_COMM_INT_MSK_CE_FI__W 1 -#define CE_REG_COMM_INT_MSK_CE_FI__M 0x4 - -#define CE_REG_2K__A 0x1810010 -#define CE_REG_2K__W 1 -#define CE_REG_2K__M 0x1 -#define CE_REG_2K_INIT 0x0 - #define CE_REG_TAPSET__A 0x1810011 -#define CE_REG_TAPSET__W 2 -#define CE_REG_TAPSET__M 0x3 - -#define CE_REG_TAPSET_MOTION_INIT 0x0 - -#define CE_REG_TAPSET_MOTION_NO 0x0 - -#define CE_REG_TAPSET_MOTION_LOW 0x1 - -#define CE_REG_TAPSET_MOTION_HIGH 0x2 - -#define CE_REG_TAPSET_MOTION_UNDEFINED 0x3 - #define CE_REG_AVG_POW__A 0x1810012 -#define CE_REG_AVG_POW__W 8 -#define CE_REG_AVG_POW__M 0xFF -#define CE_REG_AVG_POW_INIT 0x0 - #define CE_REG_MAX_POW__A 0x1810013 -#define CE_REG_MAX_POW__W 8 -#define CE_REG_MAX_POW__M 0xFF -#define CE_REG_MAX_POW_INIT 0x0 - #define CE_REG_ATT__A 0x1810014 -#define CE_REG_ATT__W 8 -#define CE_REG_ATT__M 0xFF -#define CE_REG_ATT_INIT 0x0 - #define CE_REG_NRED__A 0x1810015 -#define CE_REG_NRED__W 6 -#define CE_REG_NRED__M 0x3F -#define CE_REG_NRED_INIT 0x0 - -#define CE_REG_PU_SIGN__A 0x1810020 -#define CE_REG_PU_SIGN__W 1 -#define CE_REG_PU_SIGN__M 0x1 -#define CE_REG_PU_SIGN_INIT 0x0 - -#define CE_REG_PU_MIX__A 0x1810021 -#define CE_REG_PU_MIX__W 7 -#define CE_REG_PU_MIX__M 0x7F -#define CE_REG_PU_MIX_INIT 0x0 - -#define CE_REG_PB_PILOT_REQ__A 0x1810030 -#define CE_REG_PB_PILOT_REQ__W 15 -#define CE_REG_PB_PILOT_REQ__M 0x7FFF -#define CE_REG_PB_PILOT_REQ_INIT 0x0 -#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 -#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 -#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 -#define CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 -#define CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 -#define CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF - -#define CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 -#define CE_REG_PB_PILOT_REQ_VALID__W 1 -#define CE_REG_PB_PILOT_REQ_VALID__M 0x1 -#define CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 - -#define CE_REG_PB_FREEZE__A 0x1810032 -#define CE_REG_PB_FREEZE__W 1 -#define CE_REG_PB_FREEZE__M 0x1 -#define CE_REG_PB_FREEZE_INIT 0x0 - -#define CE_REG_PB_PILOT_EXP__A 0x1810038 -#define CE_REG_PB_PILOT_EXP__W 4 -#define CE_REG_PB_PILOT_EXP__M 0xF -#define CE_REG_PB_PILOT_EXP_INIT 0x0 - -#define CE_REG_PB_PILOT_REAL__A 0x1810039 -#define CE_REG_PB_PILOT_REAL__W 10 -#define CE_REG_PB_PILOT_REAL__M 0x3FF -#define CE_REG_PB_PILOT_REAL_INIT 0x0 - -#define CE_REG_PB_PILOT_IMAG__A 0x181003A -#define CE_REG_PB_PILOT_IMAG__W 10 -#define CE_REG_PB_PILOT_IMAG__M 0x3FF -#define CE_REG_PB_PILOT_IMAG_INIT 0x0 - -#define CE_REG_PB_SMBNR__A 0x181003B -#define CE_REG_PB_SMBNR__W 5 -#define CE_REG_PB_SMBNR__M 0x1F -#define CE_REG_PB_SMBNR_INIT 0x0 - -#define CE_REG_NE_PILOT_REQ__A 0x1810040 -#define CE_REG_NE_PILOT_REQ__W 12 -#define CE_REG_NE_PILOT_REQ__M 0xFFF -#define CE_REG_NE_PILOT_REQ_INIT 0x0 - -#define CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 -#define CE_REG_NE_PILOT_REQ_VALID__W 2 -#define CE_REG_NE_PILOT_REQ_VALID__M 0x3 -#define CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 -#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 -#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 -#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 -#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 -#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 -#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 - -#define CE_REG_NE_PILOT_DATA__A 0x1810042 -#define CE_REG_NE_PILOT_DATA__W 10 -#define CE_REG_NE_PILOT_DATA__M 0x3FF -#define CE_REG_NE_PILOT_DATA_INIT 0x0 - #define CE_REG_NE_ERR_SELECT__A 0x1810043 -#define CE_REG_NE_ERR_SELECT__W 3 -#define CE_REG_NE_ERR_SELECT__M 0x7 -#define CE_REG_NE_ERR_SELECT_INIT 0x0 - -#define CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 -#define CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 -#define CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 - -#define CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 -#define CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 -#define CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 - -#define CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 -#define CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 -#define CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 - #define CE_REG_NE_TD_CAL__A 0x1810044 -#define CE_REG_NE_TD_CAL__W 9 -#define CE_REG_NE_TD_CAL__M 0x1FF -#define CE_REG_NE_TD_CAL_INIT 0x0 - -#define CE_REG_NE_FD_CAL__A 0x1810045 -#define CE_REG_NE_FD_CAL__W 9 -#define CE_REG_NE_FD_CAL__M 0x1FF -#define CE_REG_NE_FD_CAL_INIT 0x0 - #define CE_REG_NE_MIXAVG__A 0x1810046 -#define CE_REG_NE_MIXAVG__W 3 -#define CE_REG_NE_MIXAVG__M 0x7 -#define CE_REG_NE_MIXAVG_INIT 0x0 - #define CE_REG_NE_NUPD_OFS__A 0x1810047 -#define CE_REG_NE_NUPD_OFS__W 7 -#define CE_REG_NE_NUPD_OFS__M 0x7F -#define CE_REG_NE_NUPD_OFS_INIT 0x0 - -#define CE_REG_NE_TD_POW__A 0x1810048 -#define CE_REG_NE_TD_POW__W 15 -#define CE_REG_NE_TD_POW__M 0x7FFF -#define CE_REG_NE_TD_POW_INIT 0x0 - -#define CE_REG_NE_TD_POW_EXPONENT__B 10 -#define CE_REG_NE_TD_POW_EXPONENT__W 5 -#define CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 - -#define CE_REG_NE_TD_POW_MANTISSA__B 0 -#define CE_REG_NE_TD_POW_MANTISSA__W 10 -#define CE_REG_NE_TD_POW_MANTISSA__M 0x3FF - -#define CE_REG_NE_FD_POW__A 0x1810049 -#define CE_REG_NE_FD_POW__W 15 -#define CE_REG_NE_FD_POW__M 0x7FFF -#define CE_REG_NE_FD_POW_INIT 0x0 - -#define CE_REG_NE_FD_POW_EXPONENT__B 10 -#define CE_REG_NE_FD_POW_EXPONENT__W 5 -#define CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 - -#define CE_REG_NE_FD_POW_MANTISSA__B 0 -#define CE_REG_NE_FD_POW_MANTISSA__W 10 -#define CE_REG_NE_FD_POW_MANTISSA__M 0x3FF - -#define CE_REG_NE_NEXP_AVG__A 0x181004A -#define CE_REG_NE_NEXP_AVG__W 8 -#define CE_REG_NE_NEXP_AVG__M 0xFF -#define CE_REG_NE_NEXP_AVG_INIT 0x0 - -#define CE_REG_NE_OFFSET__A 0x181004B -#define CE_REG_NE_OFFSET__W 9 -#define CE_REG_NE_OFFSET__M 0x1FF -#define CE_REG_NE_OFFSET_INIT 0x0 - #define CE_REG_PE_NEXP_OFFS__A 0x1810050 -#define CE_REG_PE_NEXP_OFFS__W 8 -#define CE_REG_PE_NEXP_OFFS__M 0xFF -#define CE_REG_PE_NEXP_OFFS_INIT 0x0 - #define CE_REG_PE_TIMESHIFT__A 0x1810051 -#define CE_REG_PE_TIMESHIFT__W 14 -#define CE_REG_PE_TIMESHIFT__M 0x3FFF -#define CE_REG_PE_TIMESHIFT_INIT 0x0 - -#define CE_REG_PE_DIF_REAL_L__A 0x1810052 -#define CE_REG_PE_DIF_REAL_L__W 16 -#define CE_REG_PE_DIF_REAL_L__M 0xFFFF -#define CE_REG_PE_DIF_REAL_L_INIT 0x0 - -#define CE_REG_PE_DIF_IMAG_L__A 0x1810053 -#define CE_REG_PE_DIF_IMAG_L__W 16 -#define CE_REG_PE_DIF_IMAG_L__M 0xFFFF -#define CE_REG_PE_DIF_IMAG_L_INIT 0x0 - -#define CE_REG_PE_DIF_REAL_R__A 0x1810054 -#define CE_REG_PE_DIF_REAL_R__W 16 -#define CE_REG_PE_DIF_REAL_R__M 0xFFFF -#define CE_REG_PE_DIF_REAL_R_INIT 0x0 - -#define CE_REG_PE_DIF_IMAG_R__A 0x1810055 -#define CE_REG_PE_DIF_IMAG_R__W 16 -#define CE_REG_PE_DIF_IMAG_R__M 0xFFFF -#define CE_REG_PE_DIF_IMAG_R_INIT 0x0 - -#define CE_REG_PE_ABS_REAL_L__A 0x1810056 -#define CE_REG_PE_ABS_REAL_L__W 16 -#define CE_REG_PE_ABS_REAL_L__M 0xFFFF -#define CE_REG_PE_ABS_REAL_L_INIT 0x0 - -#define CE_REG_PE_ABS_IMAG_L__A 0x1810057 -#define CE_REG_PE_ABS_IMAG_L__W 16 -#define CE_REG_PE_ABS_IMAG_L__M 0xFFFF -#define CE_REG_PE_ABS_IMAG_L_INIT 0x0 - -#define CE_REG_PE_ABS_REAL_R__A 0x1810058 -#define CE_REG_PE_ABS_REAL_R__W 16 -#define CE_REG_PE_ABS_REAL_R__M 0xFFFF -#define CE_REG_PE_ABS_REAL_R_INIT 0x0 - -#define CE_REG_PE_ABS_IMAG_R__A 0x1810059 -#define CE_REG_PE_ABS_IMAG_R__W 16 -#define CE_REG_PE_ABS_IMAG_R__M 0xFFFF -#define CE_REG_PE_ABS_IMAG_R_INIT 0x0 - -#define CE_REG_PE_ABS_EXP_L__A 0x181005A -#define CE_REG_PE_ABS_EXP_L__W 5 -#define CE_REG_PE_ABS_EXP_L__M 0x1F -#define CE_REG_PE_ABS_EXP_L_INIT 0x0 - -#define CE_REG_PE_ABS_EXP_R__A 0x181005B -#define CE_REG_PE_ABS_EXP_R__W 5 -#define CE_REG_PE_ABS_EXP_R__M 0x1F -#define CE_REG_PE_ABS_EXP_R_INIT 0x0 - -#define CE_REG_TP_UPDATE_MODE__A 0x1810060 -#define CE_REG_TP_UPDATE_MODE__W 1 -#define CE_REG_TP_UPDATE_MODE__M 0x1 -#define CE_REG_TP_UPDATE_MODE_INIT 0x0 - -#define CE_REG_TP_LMS_TAP_ON__A 0x1810061 -#define CE_REG_TP_LMS_TAP_ON__W 1 -#define CE_REG_TP_LMS_TAP_ON__M 0x1 - #define CE_REG_TP_A0_TAP_NEW__A 0x1810064 -#define CE_REG_TP_A0_TAP_NEW__W 10 -#define CE_REG_TP_A0_TAP_NEW__M 0x3FF - #define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 -#define CE_REG_TP_A0_TAP_NEW_VALID__W 1 -#define CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 - #define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 -#define CE_REG_TP_A0_MU_LMS_STEP__W 5 -#define CE_REG_TP_A0_MU_LMS_STEP__M 0x1F - -#define CE_REG_TP_A0_TAP_CURR__A 0x1810067 -#define CE_REG_TP_A0_TAP_CURR__W 10 -#define CE_REG_TP_A0_TAP_CURR__M 0x3FF - #define CE_REG_TP_A1_TAP_NEW__A 0x1810068 -#define CE_REG_TP_A1_TAP_NEW__W 10 -#define CE_REG_TP_A1_TAP_NEW__M 0x3FF - #define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 -#define CE_REG_TP_A1_TAP_NEW_VALID__W 1 -#define CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 - #define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A -#define CE_REG_TP_A1_MU_LMS_STEP__W 5 -#define CE_REG_TP_A1_MU_LMS_STEP__M 0x1F - -#define CE_REG_TP_A1_TAP_CURR__A 0x181006B -#define CE_REG_TP_A1_TAP_CURR__W 10 -#define CE_REG_TP_A1_TAP_CURR__M 0x3FF - -#define CE_REG_TP_DOPP_ENERGY__A 0x181006C -#define CE_REG_TP_DOPP_ENERGY__W 15 -#define CE_REG_TP_DOPP_ENERGY__M 0x7FFF -#define CE_REG_TP_DOPP_ENERGY_INIT 0x0 - -#define CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 -#define CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 -#define CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 - -#define CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 -#define CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 -#define CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF - -#define CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D -#define CE_REG_TP_DOPP_DIFF_ENERGY__W 15 -#define CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF -#define CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 - -#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 -#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 -#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 - -#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 -#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 -#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF - -#define CE_REG_TP_A0_TAP_ENERGY__A 0x181006E -#define CE_REG_TP_A0_TAP_ENERGY__W 15 -#define CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF -#define CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 - -#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 -#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 -#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 - -#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 -#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 -#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF - -#define CE_REG_TP_A1_TAP_ENERGY__A 0x181006F -#define CE_REG_TP_A1_TAP_ENERGY__W 15 -#define CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF -#define CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 - -#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 -#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 -#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 - -#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 -#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 -#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF - #define CE_REG_TI_NEXP_OFFS__A 0x1810070 -#define CE_REG_TI_NEXP_OFFS__W 8 -#define CE_REG_TI_NEXP_OFFS__M 0xFF -#define CE_REG_TI_NEXP_OFFS_INIT 0x0 - -#define CE_REG_TI_PEAK__A 0x1810071 -#define CE_REG_TI_PEAK__W 8 -#define CE_REG_TI_PEAK__M 0xFF -#define CE_REG_TI_PEAK_INIT 0x0 - #define CE_REG_FI_SHT_INCR__A 0x1810090 -#define CE_REG_FI_SHT_INCR__W 7 -#define CE_REG_FI_SHT_INCR__M 0x7F -#define CE_REG_FI_SHT_INCR_INIT 0x9 - #define CE_REG_FI_EXP_NORM__A 0x1810091 -#define CE_REG_FI_EXP_NORM__W 4 -#define CE_REG_FI_EXP_NORM__M 0xF -#define CE_REG_FI_EXP_NORM_INIT 0x4 - -#define CE_REG_FI_SUPR_VAL__A 0x1810092 -#define CE_REG_FI_SUPR_VAL__W 1 -#define CE_REG_FI_SUPR_VAL__M 0x1 -#define CE_REG_FI_SUPR_VAL_INIT 0x1 - #define CE_REG_IR_INPUTSEL__A 0x18100A0 -#define CE_REG_IR_INPUTSEL__W 1 -#define CE_REG_IR_INPUTSEL__M 0x1 -#define CE_REG_IR_INPUTSEL_INIT 0x0 - #define CE_REG_IR_STARTPOS__A 0x18100A1 -#define CE_REG_IR_STARTPOS__W 8 -#define CE_REG_IR_STARTPOS__M 0xFF -#define CE_REG_IR_STARTPOS_INIT 0x0 - #define CE_REG_IR_NEXP_THRES__A 0x18100A2 -#define CE_REG_IR_NEXP_THRES__W 8 -#define CE_REG_IR_NEXP_THRES__M 0xFF -#define CE_REG_IR_NEXP_THRES_INIT 0x0 - -#define CE_REG_IR_LENGTH__A 0x18100A3 -#define CE_REG_IR_LENGTH__W 4 -#define CE_REG_IR_LENGTH__M 0xF -#define CE_REG_IR_LENGTH_INIT 0x0 - -#define CE_REG_IR_FREQ__A 0x18100A4 -#define CE_REG_IR_FREQ__W 11 -#define CE_REG_IR_FREQ__M 0x7FF -#define CE_REG_IR_FREQ_INIT 0x0 - -#define CE_REG_IR_FREQINC__A 0x18100A5 -#define CE_REG_IR_FREQINC__W 11 -#define CE_REG_IR_FREQINC__M 0x7FF -#define CE_REG_IR_FREQINC_INIT 0x0 - -#define CE_REG_IR_KAISINC__A 0x18100A6 -#define CE_REG_IR_KAISINC__W 15 -#define CE_REG_IR_KAISINC__M 0x7FFF -#define CE_REG_IR_KAISINC_INIT 0x0 - -#define CE_REG_IR_CTL__A 0x18100A7 -#define CE_REG_IR_CTL__W 3 -#define CE_REG_IR_CTL__M 0x7 -#define CE_REG_IR_CTL_INIT 0x0 - -#define CE_REG_IR_REAL__A 0x18100A8 -#define CE_REG_IR_REAL__W 16 -#define CE_REG_IR_REAL__M 0xFFFF -#define CE_REG_IR_REAL_INIT 0x0 - -#define CE_REG_IR_IMAG__A 0x18100A9 -#define CE_REG_IR_IMAG__W 16 -#define CE_REG_IR_IMAG__M 0xFFFF -#define CE_REG_IR_IMAG_INIT 0x0 - -#define CE_REG_IR_INDEX__A 0x18100AA -#define CE_REG_IR_INDEX__W 12 -#define CE_REG_IR_INDEX__M 0xFFF -#define CE_REG_IR_INDEX_INIT 0x0 - #define CE_REG_FR_TREAL00__A 0x1820010 -#define CE_REG_FR_TREAL00__W 11 -#define CE_REG_FR_TREAL00__M 0x7FF -#define CE_REG_FR_TREAL00_INIT 0x52 - #define CE_REG_FR_TIMAG00__A 0x1820011 -#define CE_REG_FR_TIMAG00__W 11 -#define CE_REG_FR_TIMAG00__M 0x7FF -#define CE_REG_FR_TIMAG00_INIT 0x0 - #define CE_REG_FR_TREAL01__A 0x1820012 -#define CE_REG_FR_TREAL01__W 11 -#define CE_REG_FR_TREAL01__M 0x7FF -#define CE_REG_FR_TREAL01_INIT 0x52 - #define CE_REG_FR_TIMAG01__A 0x1820013 -#define CE_REG_FR_TIMAG01__W 11 -#define CE_REG_FR_TIMAG01__M 0x7FF -#define CE_REG_FR_TIMAG01_INIT 0x0 - #define CE_REG_FR_TREAL02__A 0x1820014 -#define CE_REG_FR_TREAL02__W 11 -#define CE_REG_FR_TREAL02__M 0x7FF -#define CE_REG_FR_TREAL02_INIT 0x52 - #define CE_REG_FR_TIMAG02__A 0x1820015 -#define CE_REG_FR_TIMAG02__W 11 -#define CE_REG_FR_TIMAG02__M 0x7FF -#define CE_REG_FR_TIMAG02_INIT 0x0 - #define CE_REG_FR_TREAL03__A 0x1820016 -#define CE_REG_FR_TREAL03__W 11 -#define CE_REG_FR_TREAL03__M 0x7FF -#define CE_REG_FR_TREAL03_INIT 0x52 - #define CE_REG_FR_TIMAG03__A 0x1820017 -#define CE_REG_FR_TIMAG03__W 11 -#define CE_REG_FR_TIMAG03__M 0x7FF -#define CE_REG_FR_TIMAG03_INIT 0x0 - #define CE_REG_FR_TREAL04__A 0x1820018 -#define CE_REG_FR_TREAL04__W 11 -#define CE_REG_FR_TREAL04__M 0x7FF -#define CE_REG_FR_TREAL04_INIT 0x52 - #define CE_REG_FR_TIMAG04__A 0x1820019 -#define CE_REG_FR_TIMAG04__W 11 -#define CE_REG_FR_TIMAG04__M 0x7FF -#define CE_REG_FR_TIMAG04_INIT 0x0 - #define CE_REG_FR_TREAL05__A 0x182001A -#define CE_REG_FR_TREAL05__W 11 -#define CE_REG_FR_TREAL05__M 0x7FF -#define CE_REG_FR_TREAL05_INIT 0x52 - #define CE_REG_FR_TIMAG05__A 0x182001B -#define CE_REG_FR_TIMAG05__W 11 -#define CE_REG_FR_TIMAG05__M 0x7FF -#define CE_REG_FR_TIMAG05_INIT 0x0 - #define CE_REG_FR_TREAL06__A 0x182001C -#define CE_REG_FR_TREAL06__W 11 -#define CE_REG_FR_TREAL06__M 0x7FF -#define CE_REG_FR_TREAL06_INIT 0x52 - #define CE_REG_FR_TIMAG06__A 0x182001D -#define CE_REG_FR_TIMAG06__W 11 -#define CE_REG_FR_TIMAG06__M 0x7FF -#define CE_REG_FR_TIMAG06_INIT 0x0 - #define CE_REG_FR_TREAL07__A 0x182001E -#define CE_REG_FR_TREAL07__W 11 -#define CE_REG_FR_TREAL07__M 0x7FF -#define CE_REG_FR_TREAL07_INIT 0x52 - #define CE_REG_FR_TIMAG07__A 0x182001F -#define CE_REG_FR_TIMAG07__W 11 -#define CE_REG_FR_TIMAG07__M 0x7FF -#define CE_REG_FR_TIMAG07_INIT 0x0 - #define CE_REG_FR_TREAL08__A 0x1820020 -#define CE_REG_FR_TREAL08__W 11 -#define CE_REG_FR_TREAL08__M 0x7FF -#define CE_REG_FR_TREAL08_INIT 0x52 - #define CE_REG_FR_TIMAG08__A 0x1820021 -#define CE_REG_FR_TIMAG08__W 11 -#define CE_REG_FR_TIMAG08__M 0x7FF -#define CE_REG_FR_TIMAG08_INIT 0x0 - #define CE_REG_FR_TREAL09__A 0x1820022 -#define CE_REG_FR_TREAL09__W 11 -#define CE_REG_FR_TREAL09__M 0x7FF -#define CE_REG_FR_TREAL09_INIT 0x52 - #define CE_REG_FR_TIMAG09__A 0x1820023 -#define CE_REG_FR_TIMAG09__W 11 -#define CE_REG_FR_TIMAG09__M 0x7FF -#define CE_REG_FR_TIMAG09_INIT 0x0 - #define CE_REG_FR_TREAL10__A 0x1820024 -#define CE_REG_FR_TREAL10__W 11 -#define CE_REG_FR_TREAL10__M 0x7FF -#define CE_REG_FR_TREAL10_INIT 0x52 - #define CE_REG_FR_TIMAG10__A 0x1820025 -#define CE_REG_FR_TIMAG10__W 11 -#define CE_REG_FR_TIMAG10__M 0x7FF -#define CE_REG_FR_TIMAG10_INIT 0x0 - #define CE_REG_FR_TREAL11__A 0x1820026 -#define CE_REG_FR_TREAL11__W 11 -#define CE_REG_FR_TREAL11__M 0x7FF -#define CE_REG_FR_TREAL11_INIT 0x52 - #define CE_REG_FR_TIMAG11__A 0x1820027 -#define CE_REG_FR_TIMAG11__W 11 -#define CE_REG_FR_TIMAG11__M 0x7FF -#define CE_REG_FR_TIMAG11_INIT 0x0 - #define CE_REG_FR_MID_TAP__A 0x1820028 -#define CE_REG_FR_MID_TAP__W 11 -#define CE_REG_FR_MID_TAP__M 0x7FF -#define CE_REG_FR_MID_TAP_INIT 0x51 - #define CE_REG_FR_SQS_G00__A 0x1820029 -#define CE_REG_FR_SQS_G00__W 8 -#define CE_REG_FR_SQS_G00__M 0xFF -#define CE_REG_FR_SQS_G00_INIT 0xB - #define CE_REG_FR_SQS_G01__A 0x182002A -#define CE_REG_FR_SQS_G01__W 8 -#define CE_REG_FR_SQS_G01__M 0xFF -#define CE_REG_FR_SQS_G01_INIT 0xB - #define CE_REG_FR_SQS_G02__A 0x182002B -#define CE_REG_FR_SQS_G02__W 8 -#define CE_REG_FR_SQS_G02__M 0xFF -#define CE_REG_FR_SQS_G02_INIT 0xB - #define CE_REG_FR_SQS_G03__A 0x182002C -#define CE_REG_FR_SQS_G03__W 8 -#define CE_REG_FR_SQS_G03__M 0xFF -#define CE_REG_FR_SQS_G03_INIT 0xB - #define CE_REG_FR_SQS_G04__A 0x182002D -#define CE_REG_FR_SQS_G04__W 8 -#define CE_REG_FR_SQS_G04__M 0xFF -#define CE_REG_FR_SQS_G04_INIT 0xB - #define CE_REG_FR_SQS_G05__A 0x182002E -#define CE_REG_FR_SQS_G05__W 8 -#define CE_REG_FR_SQS_G05__M 0xFF -#define CE_REG_FR_SQS_G05_INIT 0xB - #define CE_REG_FR_SQS_G06__A 0x182002F -#define CE_REG_FR_SQS_G06__W 8 -#define CE_REG_FR_SQS_G06__M 0xFF -#define CE_REG_FR_SQS_G06_INIT 0xB - #define CE_REG_FR_SQS_G07__A 0x1820030 -#define CE_REG_FR_SQS_G07__W 8 -#define CE_REG_FR_SQS_G07__M 0xFF -#define CE_REG_FR_SQS_G07_INIT 0xB - #define CE_REG_FR_SQS_G08__A 0x1820031 -#define CE_REG_FR_SQS_G08__W 8 -#define CE_REG_FR_SQS_G08__M 0xFF -#define CE_REG_FR_SQS_G08_INIT 0xB - #define CE_REG_FR_SQS_G09__A 0x1820032 -#define CE_REG_FR_SQS_G09__W 8 -#define CE_REG_FR_SQS_G09__M 0xFF -#define CE_REG_FR_SQS_G09_INIT 0xB - #define CE_REG_FR_SQS_G10__A 0x1820033 -#define CE_REG_FR_SQS_G10__W 8 -#define CE_REG_FR_SQS_G10__M 0xFF -#define CE_REG_FR_SQS_G10_INIT 0xB - #define CE_REG_FR_SQS_G11__A 0x1820034 -#define CE_REG_FR_SQS_G11__W 8 -#define CE_REG_FR_SQS_G11__M 0xFF -#define CE_REG_FR_SQS_G11_INIT 0xB - #define CE_REG_FR_SQS_G12__A 0x1820035 -#define CE_REG_FR_SQS_G12__W 8 -#define CE_REG_FR_SQS_G12__M 0xFF -#define CE_REG_FR_SQS_G12_INIT 0x5 - #define CE_REG_FR_RIO_G00__A 0x1820036 -#define CE_REG_FR_RIO_G00__W 9 -#define CE_REG_FR_RIO_G00__M 0x1FF -#define CE_REG_FR_RIO_G00_INIT 0x1FF - #define CE_REG_FR_RIO_G01__A 0x1820037 -#define CE_REG_FR_RIO_G01__W 9 -#define CE_REG_FR_RIO_G01__M 0x1FF -#define CE_REG_FR_RIO_G01_INIT 0x190 - #define CE_REG_FR_RIO_G02__A 0x1820038 -#define CE_REG_FR_RIO_G02__W 9 -#define CE_REG_FR_RIO_G02__M 0x1FF -#define CE_REG_FR_RIO_G02_INIT 0x10B - #define CE_REG_FR_RIO_G03__A 0x1820039 -#define CE_REG_FR_RIO_G03__W 9 -#define CE_REG_FR_RIO_G03__M 0x1FF -#define CE_REG_FR_RIO_G03_INIT 0xC8 - #define CE_REG_FR_RIO_G04__A 0x182003A -#define CE_REG_FR_RIO_G04__W 9 -#define CE_REG_FR_RIO_G04__M 0x1FF -#define CE_REG_FR_RIO_G04_INIT 0xA0 - #define CE_REG_FR_RIO_G05__A 0x182003B -#define CE_REG_FR_RIO_G05__W 9 -#define CE_REG_FR_RIO_G05__M 0x1FF -#define CE_REG_FR_RIO_G05_INIT 0x85 - #define CE_REG_FR_RIO_G06__A 0x182003C -#define CE_REG_FR_RIO_G06__W 9 -#define CE_REG_FR_RIO_G06__M 0x1FF -#define CE_REG_FR_RIO_G06_INIT 0x72 - #define CE_REG_FR_RIO_G07__A 0x182003D -#define CE_REG_FR_RIO_G07__W 9 -#define CE_REG_FR_RIO_G07__M 0x1FF -#define CE_REG_FR_RIO_G07_INIT 0x64 - #define CE_REG_FR_RIO_G08__A 0x182003E -#define CE_REG_FR_RIO_G08__W 9 -#define CE_REG_FR_RIO_G08__M 0x1FF -#define CE_REG_FR_RIO_G08_INIT 0x59 - #define CE_REG_FR_RIO_G09__A 0x182003F -#define CE_REG_FR_RIO_G09__W 9 -#define CE_REG_FR_RIO_G09__M 0x1FF -#define CE_REG_FR_RIO_G09_INIT 0x50 - #define CE_REG_FR_RIO_G10__A 0x1820040 -#define CE_REG_FR_RIO_G10__W 9 -#define CE_REG_FR_RIO_G10__M 0x1FF -#define CE_REG_FR_RIO_G10_INIT 0x49 - #define CE_REG_FR_MODE__A 0x1820041 -#define CE_REG_FR_MODE__W 6 -#define CE_REG_FR_MODE__M 0x3F - -#define CE_REG_FR_MODE_UPDATE_ENABLE__B 0 -#define CE_REG_FR_MODE_UPDATE_ENABLE__W 1 -#define CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 - -#define CE_REG_FR_MODE_ERROR_SHIFT__B 1 -#define CE_REG_FR_MODE_ERROR_SHIFT__W 1 -#define CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 - -#define CE_REG_FR_MODE_NEXP_UPDATE__B 2 -#define CE_REG_FR_MODE_NEXP_UPDATE__W 1 -#define CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 - -#define CE_REG_FR_MODE_MANUAL_SHIFT__B 3 -#define CE_REG_FR_MODE_MANUAL_SHIFT__W 1 -#define CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 - -#define CE_REG_FR_MODE_SQUASH_MODE__B 4 -#define CE_REG_FR_MODE_SQUASH_MODE__W 1 -#define CE_REG_FR_MODE_SQUASH_MODE__M 0x10 - -#define CE_REG_FR_MODE_UPDATE_MODE__B 5 -#define CE_REG_FR_MODE_UPDATE_MODE__W 1 -#define CE_REG_FR_MODE_UPDATE_MODE__M 0x20 -#define CE_REG_FR_MODE_INIT 0x3E - #define CE_REG_FR_SQS_TRH__A 0x1820042 -#define CE_REG_FR_SQS_TRH__W 8 -#define CE_REG_FR_SQS_TRH__M 0xFF -#define CE_REG_FR_SQS_TRH_INIT 0x80 - #define CE_REG_FR_RIO_GAIN__A 0x1820043 -#define CE_REG_FR_RIO_GAIN__W 3 -#define CE_REG_FR_RIO_GAIN__M 0x7 -#define CE_REG_FR_RIO_GAIN_INIT 0x2 - #define CE_REG_FR_BYPASS__A 0x1820044 -#define CE_REG_FR_BYPASS__W 10 -#define CE_REG_FR_BYPASS__M 0x3FF - -#define CE_REG_FR_BYPASS_RUN_IN__B 0 -#define CE_REG_FR_BYPASS_RUN_IN__W 4 -#define CE_REG_FR_BYPASS_RUN_IN__M 0xF - -#define CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 -#define CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 -#define CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 - -#define CE_REG_FR_BYPASS_TOTAL__B 9 -#define CE_REG_FR_BYPASS_TOTAL__W 1 -#define CE_REG_FR_BYPASS_TOTAL__M 0x200 -#define CE_REG_FR_BYPASS_INIT 0x13B - #define CE_REG_FR_PM_SET__A 0x1820045 -#define CE_REG_FR_PM_SET__W 4 -#define CE_REG_FR_PM_SET__M 0xF -#define CE_REG_FR_PM_SET_INIT 0x4 - #define CE_REG_FR_ERR_SH__A 0x1820046 -#define CE_REG_FR_ERR_SH__W 4 -#define CE_REG_FR_ERR_SH__M 0xF -#define CE_REG_FR_ERR_SH_INIT 0x4 - #define CE_REG_FR_MAN_SH__A 0x1820047 -#define CE_REG_FR_MAN_SH__W 4 -#define CE_REG_FR_MAN_SH__M 0xF -#define CE_REG_FR_MAN_SH_INIT 0x7 - #define CE_REG_FR_TAP_SH__A 0x1820048 -#define CE_REG_FR_TAP_SH__W 3 -#define CE_REG_FR_TAP_SH__M 0x7 -#define CE_REG_FR_TAP_SH_INIT 0x3 - -#define CE_REG_FR_CLIP__A 0x1820049 -#define CE_REG_FR_CLIP__W 9 -#define CE_REG_FR_CLIP__M 0x1FF -#define CE_REG_FR_CLIP_INIT 0x49 - -#define CE_PB_RAM__A 0x1830000 - -#define CE_NE_RAM__A 0x1840000 - -#define EQ_SID 0xE - #define EQ_COMM_EXEC__A 0x1C00000 -#define EQ_COMM_EXEC__W 3 -#define EQ_COMM_EXEC__M 0x7 -#define EQ_COMM_EXEC_CTL__B 0 -#define EQ_COMM_EXEC_CTL__W 3 -#define EQ_COMM_EXEC_CTL__M 0x7 -#define EQ_COMM_EXEC_CTL_STOP 0x0 -#define EQ_COMM_EXEC_CTL_ACTIVE 0x1 -#define EQ_COMM_EXEC_CTL_HOLD 0x2 -#define EQ_COMM_EXEC_CTL_STEP 0x3 -#define EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define EQ_COMM_STATE__A 0x1C00001 -#define EQ_COMM_STATE__W 16 -#define EQ_COMM_STATE__M 0xFFFF -#define EQ_COMM_MB__A 0x1C00002 -#define EQ_COMM_MB__W 16 -#define EQ_COMM_MB__M 0xFFFF -#define EQ_COMM_SERVICE0__A 0x1C00003 -#define EQ_COMM_SERVICE0__W 16 -#define EQ_COMM_SERVICE0__M 0xFFFF -#define EQ_COMM_SERVICE1__A 0x1C00004 -#define EQ_COMM_SERVICE1__W 16 -#define EQ_COMM_SERVICE1__M 0xFFFF -#define EQ_COMM_INT_STA__A 0x1C00007 -#define EQ_COMM_INT_STA__W 16 -#define EQ_COMM_INT_STA__M 0xFFFF -#define EQ_COMM_INT_MSK__A 0x1C00008 -#define EQ_COMM_INT_MSK__W 16 -#define EQ_COMM_INT_MSK__M 0xFFFF - #define EQ_REG_COMM_EXEC__A 0x1C10000 -#define EQ_REG_COMM_EXEC__W 3 -#define EQ_REG_COMM_EXEC__M 0x7 -#define EQ_REG_COMM_EXEC_CTL__B 0 -#define EQ_REG_COMM_EXEC_CTL__W 3 -#define EQ_REG_COMM_EXEC_CTL__M 0x7 -#define EQ_REG_COMM_EXEC_CTL_STOP 0x0 -#define EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define EQ_REG_COMM_EXEC_CTL_HOLD 0x2 -#define EQ_REG_COMM_EXEC_CTL_STEP 0x3 - -#define EQ_REG_COMM_STATE__A 0x1C10001 -#define EQ_REG_COMM_STATE__W 4 -#define EQ_REG_COMM_STATE__M 0xF - #define EQ_REG_COMM_MB__A 0x1C10002 -#define EQ_REG_COMM_MB__W 6 -#define EQ_REG_COMM_MB__M 0x3F -#define EQ_REG_COMM_MB_CTR__B 0 -#define EQ_REG_COMM_MB_CTR__W 1 -#define EQ_REG_COMM_MB_CTR__M 0x1 -#define EQ_REG_COMM_MB_CTR_OFF 0x0 -#define EQ_REG_COMM_MB_CTR_ON 0x1 -#define EQ_REG_COMM_MB_OBS__B 1 -#define EQ_REG_COMM_MB_OBS__W 1 -#define EQ_REG_COMM_MB_OBS__M 0x2 -#define EQ_REG_COMM_MB_OBS_OFF 0x0 -#define EQ_REG_COMM_MB_OBS_ON 0x2 -#define EQ_REG_COMM_MB_CTR_MUX__B 2 -#define EQ_REG_COMM_MB_CTR_MUX__W 2 -#define EQ_REG_COMM_MB_CTR_MUX__M 0xC -#define EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 -#define EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 -#define EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 -#define EQ_REG_COMM_MB_OBS_MUX__B 4 -#define EQ_REG_COMM_MB_OBS_MUX__W 2 -#define EQ_REG_COMM_MB_OBS_MUX__M 0x30 -#define EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 -#define EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 -#define EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 -#define EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 - -#define EQ_REG_COMM_SERVICE0__A 0x1C10003 -#define EQ_REG_COMM_SERVICE0__W 10 -#define EQ_REG_COMM_SERVICE0__M 0x3FF - -#define EQ_REG_COMM_SERVICE1__A 0x1C10004 -#define EQ_REG_COMM_SERVICE1__W 11 -#define EQ_REG_COMM_SERVICE1__M 0x7FF - -#define EQ_REG_COMM_INT_STA__A 0x1C10007 -#define EQ_REG_COMM_INT_STA__W 2 -#define EQ_REG_COMM_INT_STA__M 0x3 -#define EQ_REG_COMM_INT_STA_TPS_RDY__B 0 -#define EQ_REG_COMM_INT_STA_TPS_RDY__W 1 -#define EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 -#define EQ_REG_COMM_INT_STA_ERR_RDY__B 1 -#define EQ_REG_COMM_INT_STA_ERR_RDY__W 1 -#define EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 - -#define EQ_REG_COMM_INT_MSK__A 0x1C10008 -#define EQ_REG_COMM_INT_MSK__W 2 -#define EQ_REG_COMM_INT_MSK__M 0x3 -#define EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 -#define EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 -#define EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 -#define EQ_REG_COMM_INT_MSK_MER_RDY__B 1 -#define EQ_REG_COMM_INT_MSK_MER_RDY__W 1 -#define EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 - -#define EQ_REG_IS_MODE__A 0x1C10014 -#define EQ_REG_IS_MODE__W 4 -#define EQ_REG_IS_MODE__M 0xF -#define EQ_REG_IS_MODE_INIT 0x0 - -#define EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 -#define EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 -#define EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 -#define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 -#define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 - -#define EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 -#define EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 -#define EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 -#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 -#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 - #define EQ_REG_IS_GAIN_MAN__A 0x1C10015 -#define EQ_REG_IS_GAIN_MAN__W 10 -#define EQ_REG_IS_GAIN_MAN__M 0x3FF -#define EQ_REG_IS_GAIN_MAN_INIT 0x0 - #define EQ_REG_IS_GAIN_EXP__A 0x1C10016 -#define EQ_REG_IS_GAIN_EXP__W 5 -#define EQ_REG_IS_GAIN_EXP__M 0x1F -#define EQ_REG_IS_GAIN_EXP_INIT 0x0 - #define EQ_REG_IS_CLIP_EXP__A 0x1C10017 -#define EQ_REG_IS_CLIP_EXP__W 5 -#define EQ_REG_IS_CLIP_EXP__M 0x1F -#define EQ_REG_IS_CLIP_EXP_INIT 0x0 - -#define EQ_REG_DV_MODE__A 0x1C1001E -#define EQ_REG_DV_MODE__W 4 -#define EQ_REG_DV_MODE__M 0xF -#define EQ_REG_DV_MODE_INIT 0x0 - -#define EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 -#define EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 -#define EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 -#define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 -#define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 - -#define EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 -#define EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 -#define EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 -#define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 -#define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 - -#define EQ_REG_DV_MODE_CLP_REA_ENA__B 2 -#define EQ_REG_DV_MODE_CLP_REA_ENA__W 1 -#define EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 -#define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 -#define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 - -#define EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 -#define EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 -#define EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 -#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 -#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 - -#define EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F -#define EQ_REG_DV_POS_CLIP_DAT__W 16 -#define EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF - -#define EQ_REG_SN_MODE__A 0x1C10028 -#define EQ_REG_SN_MODE__W 8 -#define EQ_REG_SN_MODE__M 0xFF -#define EQ_REG_SN_MODE_INIT 0x0 - -#define EQ_REG_SN_MODE_MODE_0__B 0 -#define EQ_REG_SN_MODE_MODE_0__W 1 -#define EQ_REG_SN_MODE_MODE_0__M 0x1 -#define EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 - -#define EQ_REG_SN_MODE_MODE_1__B 1 -#define EQ_REG_SN_MODE_MODE_1__W 1 -#define EQ_REG_SN_MODE_MODE_1__M 0x2 -#define EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 - -#define EQ_REG_SN_MODE_MODE_2__B 2 -#define EQ_REG_SN_MODE_MODE_2__W 1 -#define EQ_REG_SN_MODE_MODE_2__M 0x4 -#define EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 - -#define EQ_REG_SN_MODE_MODE_3__B 3 -#define EQ_REG_SN_MODE_MODE_3__W 1 -#define EQ_REG_SN_MODE_MODE_3__M 0x8 -#define EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 - -#define EQ_REG_SN_MODE_MODE_4__B 4 -#define EQ_REG_SN_MODE_MODE_4__W 1 -#define EQ_REG_SN_MODE_MODE_4__M 0x10 -#define EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 - -#define EQ_REG_SN_MODE_MODE_5__B 5 -#define EQ_REG_SN_MODE_MODE_5__W 1 -#define EQ_REG_SN_MODE_MODE_5__M 0x20 -#define EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 -#define EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 - -#define EQ_REG_SN_MODE_MODE_6__B 6 -#define EQ_REG_SN_MODE_MODE_6__W 1 -#define EQ_REG_SN_MODE_MODE_6__M 0x40 -#define EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 -#define EQ_REG_SN_MODE_MODE_6_STATIC 0x40 - -#define EQ_REG_SN_MODE_MODE_7__B 7 -#define EQ_REG_SN_MODE_MODE_7__W 1 -#define EQ_REG_SN_MODE_MODE_7__M 0x80 -#define EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 -#define EQ_REG_SN_MODE_MODE_7_STATIC 0x80 - -#define EQ_REG_SN_PFIX__A 0x1C10029 -#define EQ_REG_SN_PFIX__W 8 -#define EQ_REG_SN_PFIX__M 0xFF -#define EQ_REG_SN_PFIX_INIT 0x0 - #define EQ_REG_SN_CEGAIN__A 0x1C1002A -#define EQ_REG_SN_CEGAIN__W 8 -#define EQ_REG_SN_CEGAIN__M 0xFF -#define EQ_REG_SN_CEGAIN_INIT 0x0 - #define EQ_REG_SN_OFFSET__A 0x1C1002B -#define EQ_REG_SN_OFFSET__W 6 -#define EQ_REG_SN_OFFSET__M 0x3F -#define EQ_REG_SN_OFFSET_INIT 0x0 - -#define EQ_REG_SN_NULLIFY__A 0x1C1002C -#define EQ_REG_SN_NULLIFY__W 6 -#define EQ_REG_SN_NULLIFY__M 0x3F -#define EQ_REG_SN_NULLIFY_INIT 0x0 - -#define EQ_REG_SN_SQUASH__A 0x1C1002D -#define EQ_REG_SN_SQUASH__W 10 -#define EQ_REG_SN_SQUASH__M 0x3FF -#define EQ_REG_SN_SQUASH_INIT 0x0 - -#define EQ_REG_SN_SQUASH_MAN__B 0 -#define EQ_REG_SN_SQUASH_MAN__W 6 -#define EQ_REG_SN_SQUASH_MAN__M 0x3F - -#define EQ_REG_SN_SQUASH_EXP__B 6 -#define EQ_REG_SN_SQUASH_EXP__W 4 -#define EQ_REG_SN_SQUASH_EXP__M 0x3C0 - #define EQ_REG_RC_SEL_CAR__A 0x1C10032 -#define EQ_REG_RC_SEL_CAR__W 6 -#define EQ_REG_RC_SEL_CAR__M 0x3F #define EQ_REG_RC_SEL_CAR_INIT 0x0 -#define EQ_REG_RC_SEL_CAR_DIV__B 0 -#define EQ_REG_RC_SEL_CAR_DIV__W 1 -#define EQ_REG_RC_SEL_CAR_DIV__M 0x1 -#define EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 #define EQ_REG_RC_SEL_CAR_DIV_ON 0x1 - -#define EQ_REG_RC_SEL_CAR_PASS__B 1 -#define EQ_REG_RC_SEL_CAR_PASS__W 2 -#define EQ_REG_RC_SEL_CAR_PASS__M 0x6 #define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 #define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 -#define EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 -#define EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 - -#define EQ_REG_RC_SEL_CAR_LOCAL__B 3 -#define EQ_REG_RC_SEL_CAR_LOCAL__W 2 -#define EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 #define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 #define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 -#define EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 -#define EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 - -#define EQ_REG_RC_SEL_CAR_MEAS__B 5 -#define EQ_REG_RC_SEL_CAR_MEAS__W 1 -#define EQ_REG_RC_SEL_CAR_MEAS__M 0x20 #define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 #define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 - -#define EQ_REG_RC_STS__A 0x1C10033 -#define EQ_REG_RC_STS__W 12 -#define EQ_REG_RC_STS__M 0xFFF - -#define EQ_REG_RC_STS_DIFF__B 0 -#define EQ_REG_RC_STS_DIFF__W 9 -#define EQ_REG_RC_STS_DIFF__M 0x1FF - -#define EQ_REG_RC_STS_FIRST__B 9 -#define EQ_REG_RC_STS_FIRST__W 1 -#define EQ_REG_RC_STS_FIRST__M 0x200 -#define EQ_REG_RC_STS_FIRST_A_CE 0x0 -#define EQ_REG_RC_STS_FIRST_B_DRI 0x200 - -#define EQ_REG_RC_STS_SELEC__B 10 -#define EQ_REG_RC_STS_SELEC__W 1 -#define EQ_REG_RC_STS_SELEC__M 0x400 -#define EQ_REG_RC_STS_SELEC_A_CE 0x0 -#define EQ_REG_RC_STS_SELEC_B_DRI 0x400 - -#define EQ_REG_RC_STS_OVERFLOW__B 11 -#define EQ_REG_RC_STS_OVERFLOW__W 1 -#define EQ_REG_RC_STS_OVERFLOW__M 0x800 -#define EQ_REG_RC_STS_OVERFLOW_NO 0x0 -#define EQ_REG_RC_STS_OVERFLOW_YES 0x800 - #define EQ_REG_OT_CONST__A 0x1C10046 -#define EQ_REG_OT_CONST__W 2 -#define EQ_REG_OT_CONST__M 0x3 -#define EQ_REG_OT_CONST_INIT 0x0 - #define EQ_REG_OT_ALPHA__A 0x1C10047 -#define EQ_REG_OT_ALPHA__W 2 -#define EQ_REG_OT_ALPHA__M 0x3 -#define EQ_REG_OT_ALPHA_INIT 0x0 - #define EQ_REG_OT_QNT_THRES0__A 0x1C10048 -#define EQ_REG_OT_QNT_THRES0__W 5 -#define EQ_REG_OT_QNT_THRES0__M 0x1F -#define EQ_REG_OT_QNT_THRES0_INIT 0x0 - #define EQ_REG_OT_QNT_THRES1__A 0x1C10049 -#define EQ_REG_OT_QNT_THRES1__W 5 -#define EQ_REG_OT_QNT_THRES1__M 0x1F -#define EQ_REG_OT_QNT_THRES1_INIT 0x0 - #define EQ_REG_OT_CSI_STEP__A 0x1C1004A -#define EQ_REG_OT_CSI_STEP__W 4 -#define EQ_REG_OT_CSI_STEP__M 0xF -#define EQ_REG_OT_CSI_STEP_INIT 0x0 - #define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B -#define EQ_REG_OT_CSI_OFFSET__W 7 -#define EQ_REG_OT_CSI_OFFSET__M 0x7F -#define EQ_REG_OT_CSI_OFFSET_INIT 0x0 - -#define EQ_REG_TD_TPS_INIT__A 0x1C10050 -#define EQ_REG_TD_TPS_INIT__W 1 -#define EQ_REG_TD_TPS_INIT__M 0x1 -#define EQ_REG_TD_TPS_INIT_INIT 0x0 -#define EQ_REG_TD_TPS_INIT_POS 0x0 -#define EQ_REG_TD_TPS_INIT_NEG 0x1 - -#define EQ_REG_TD_TPS_SYNC__A 0x1C10051 -#define EQ_REG_TD_TPS_SYNC__W 16 -#define EQ_REG_TD_TPS_SYNC__M 0xFFFF -#define EQ_REG_TD_TPS_SYNC_INIT 0x0 -#define EQ_REG_TD_TPS_SYNC_ODD 0x35EE -#define EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 - -#define EQ_REG_TD_TPS_LEN__A 0x1C10052 -#define EQ_REG_TD_TPS_LEN__W 6 -#define EQ_REG_TD_TPS_LEN__M 0x3F -#define EQ_REG_TD_TPS_LEN_INIT 0x0 -#define EQ_REG_TD_TPS_LEN_DEF 0x17 -#define EQ_REG_TD_TPS_LEN_ID_SUP 0x1F - -#define EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 -#define EQ_REG_TD_TPS_FRM_NMB__W 2 -#define EQ_REG_TD_TPS_FRM_NMB__M 0x3 -#define EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 -#define EQ_REG_TD_TPS_FRM_NMB_1 0x0 -#define EQ_REG_TD_TPS_FRM_NMB_2 0x1 -#define EQ_REG_TD_TPS_FRM_NMB_3 0x2 -#define EQ_REG_TD_TPS_FRM_NMB_4 0x3 - -#define EQ_REG_TD_TPS_CONST__A 0x1C10054 -#define EQ_REG_TD_TPS_CONST__W 2 -#define EQ_REG_TD_TPS_CONST__M 0x3 -#define EQ_REG_TD_TPS_CONST_INIT 0x0 -#define EQ_REG_TD_TPS_CONST_QPSK 0x0 -#define EQ_REG_TD_TPS_CONST_16QAM 0x1 -#define EQ_REG_TD_TPS_CONST_64QAM 0x2 - -#define EQ_REG_TD_TPS_HINFO__A 0x1C10055 -#define EQ_REG_TD_TPS_HINFO__W 3 -#define EQ_REG_TD_TPS_HINFO__M 0x7 -#define EQ_REG_TD_TPS_HINFO_INIT 0x0 -#define EQ_REG_TD_TPS_HINFO_NH 0x0 -#define EQ_REG_TD_TPS_HINFO_H1 0x1 -#define EQ_REG_TD_TPS_HINFO_H2 0x2 -#define EQ_REG_TD_TPS_HINFO_H4 0x3 - -#define EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 -#define EQ_REG_TD_TPS_CODE_HP__W 3 -#define EQ_REG_TD_TPS_CODE_HP__M 0x7 -#define EQ_REG_TD_TPS_CODE_HP_INIT 0x0 -#define EQ_REG_TD_TPS_CODE_HP_1_2 0x0 -#define EQ_REG_TD_TPS_CODE_HP_2_3 0x1 -#define EQ_REG_TD_TPS_CODE_HP_3_4 0x2 -#define EQ_REG_TD_TPS_CODE_HP_5_6 0x3 -#define EQ_REG_TD_TPS_CODE_HP_7_8 0x4 - -#define EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 -#define EQ_REG_TD_TPS_CODE_LP__W 3 -#define EQ_REG_TD_TPS_CODE_LP__M 0x7 -#define EQ_REG_TD_TPS_CODE_LP_INIT 0x0 -#define EQ_REG_TD_TPS_CODE_LP_1_2 0x0 -#define EQ_REG_TD_TPS_CODE_LP_2_3 0x1 -#define EQ_REG_TD_TPS_CODE_LP_3_4 0x2 -#define EQ_REG_TD_TPS_CODE_LP_5_6 0x3 -#define EQ_REG_TD_TPS_CODE_LP_7_8 0x4 - -#define EQ_REG_TD_TPS_GUARD__A 0x1C10058 -#define EQ_REG_TD_TPS_GUARD__W 2 -#define EQ_REG_TD_TPS_GUARD__M 0x3 -#define EQ_REG_TD_TPS_GUARD_INIT 0x0 -#define EQ_REG_TD_TPS_GUARD_32 0x0 -#define EQ_REG_TD_TPS_GUARD_16 0x1 -#define EQ_REG_TD_TPS_GUARD_08 0x2 -#define EQ_REG_TD_TPS_GUARD_04 0x3 - -#define EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 -#define EQ_REG_TD_TPS_TR_MODE__W 2 -#define EQ_REG_TD_TPS_TR_MODE__M 0x3 -#define EQ_REG_TD_TPS_TR_MODE_INIT 0x0 -#define EQ_REG_TD_TPS_TR_MODE_2K 0x0 -#define EQ_REG_TD_TPS_TR_MODE_8K 0x1 - -#define EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A -#define EQ_REG_TD_TPS_CELL_ID_HI__W 8 -#define EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF -#define EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 - -#define EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B -#define EQ_REG_TD_TPS_CELL_ID_LO__W 8 -#define EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF -#define EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 - -#define EQ_REG_TD_TPS_RSV__A 0x1C1005C -#define EQ_REG_TD_TPS_RSV__W 6 -#define EQ_REG_TD_TPS_RSV__M 0x3F -#define EQ_REG_TD_TPS_RSV_INIT 0x0 - -#define EQ_REG_TD_TPS_BCH__A 0x1C1005D -#define EQ_REG_TD_TPS_BCH__W 14 -#define EQ_REG_TD_TPS_BCH__M 0x3FFF -#define EQ_REG_TD_TPS_BCH_INIT 0x0 - -#define EQ_REG_TD_SQR_ERR_I__A 0x1C1005E -#define EQ_REG_TD_SQR_ERR_I__W 16 -#define EQ_REG_TD_SQR_ERR_I__M 0xFFFF -#define EQ_REG_TD_SQR_ERR_I_INIT 0x0 - -#define EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F -#define EQ_REG_TD_SQR_ERR_Q__W 16 -#define EQ_REG_TD_SQR_ERR_Q__M 0xFFFF -#define EQ_REG_TD_SQR_ERR_Q_INIT 0x0 - -#define EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 -#define EQ_REG_TD_SQR_ERR_EXP__W 4 -#define EQ_REG_TD_SQR_ERR_EXP__M 0xF -#define EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 - #define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 -#define EQ_REG_TD_REQ_SMB_CNT__W 16 -#define EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF -#define EQ_REG_TD_REQ_SMB_CNT_INIT 0x0 - #define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 -#define EQ_REG_TD_TPS_PWR_OFS__W 16 -#define EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF -#define EQ_REG_TD_TPS_PWR_OFS_INIT 0x0 - -#define EC_COMM_EXEC__A 0x2000000 -#define EC_COMM_EXEC__W 3 -#define EC_COMM_EXEC__M 0x7 -#define EC_COMM_EXEC_CTL__B 0 -#define EC_COMM_EXEC_CTL__W 3 -#define EC_COMM_EXEC_CTL__M 0x7 -#define EC_COMM_EXEC_CTL_STOP 0x0 -#define EC_COMM_EXEC_CTL_ACTIVE 0x1 -#define EC_COMM_EXEC_CTL_HOLD 0x2 -#define EC_COMM_EXEC_CTL_STEP 0x3 -#define EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define EC_COMM_STATE__A 0x2000001 -#define EC_COMM_STATE__W 16 -#define EC_COMM_STATE__M 0xFFFF -#define EC_COMM_MB__A 0x2000002 -#define EC_COMM_MB__W 16 -#define EC_COMM_MB__M 0xFFFF -#define EC_COMM_SERVICE0__A 0x2000003 -#define EC_COMM_SERVICE0__W 16 -#define EC_COMM_SERVICE0__M 0xFFFF -#define EC_COMM_SERVICE1__A 0x2000004 -#define EC_COMM_SERVICE1__W 16 -#define EC_COMM_SERVICE1__M 0xFFFF -#define EC_COMM_INT_STA__A 0x2000007 -#define EC_COMM_INT_STA__W 16 -#define EC_COMM_INT_STA__M 0xFFFF -#define EC_COMM_INT_MSK__A 0x2000008 -#define EC_COMM_INT_MSK__W 16 -#define EC_COMM_INT_MSK__M 0xFFFF - -#define EC_SB_SID 0x16 - #define EC_SB_REG_COMM_EXEC__A 0x2010000 -#define EC_SB_REG_COMM_EXEC__W 3 -#define EC_SB_REG_COMM_EXEC__M 0x7 -#define EC_SB_REG_COMM_EXEC_CTL__B 0 -#define EC_SB_REG_COMM_EXEC_CTL__W 3 -#define EC_SB_REG_COMM_EXEC_CTL__M 0x7 -#define EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 -#define EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define EC_SB_REG_COMM_STATE__A 0x2010001 -#define EC_SB_REG_COMM_STATE__W 4 -#define EC_SB_REG_COMM_STATE__M 0xF -#define EC_SB_REG_COMM_MB__A 0x2010002 -#define EC_SB_REG_COMM_MB__W 2 -#define EC_SB_REG_COMM_MB__M 0x3 -#define EC_SB_REG_COMM_MB_CTR__B 0 -#define EC_SB_REG_COMM_MB_CTR__W 1 -#define EC_SB_REG_COMM_MB_CTR__M 0x1 -#define EC_SB_REG_COMM_MB_CTR_OFF 0x0 -#define EC_SB_REG_COMM_MB_CTR_ON 0x1 -#define EC_SB_REG_COMM_MB_OBS__B 1 -#define EC_SB_REG_COMM_MB_OBS__W 1 -#define EC_SB_REG_COMM_MB_OBS__M 0x2 -#define EC_SB_REG_COMM_MB_OBS_OFF 0x0 -#define EC_SB_REG_COMM_MB_OBS_ON 0x2 - #define EC_SB_REG_TR_MODE__A 0x2010010 -#define EC_SB_REG_TR_MODE__W 1 -#define EC_SB_REG_TR_MODE__M 0x1 -#define EC_SB_REG_TR_MODE_INIT 0x0 #define EC_SB_REG_TR_MODE_8K 0x0 #define EC_SB_REG_TR_MODE_2K 0x1 - #define EC_SB_REG_CONST__A 0x2010011 -#define EC_SB_REG_CONST__W 2 -#define EC_SB_REG_CONST__M 0x3 -#define EC_SB_REG_CONST_INIT 0x2 #define EC_SB_REG_CONST_QPSK 0x0 #define EC_SB_REG_CONST_16QAM 0x1 #define EC_SB_REG_CONST_64QAM 0x2 - #define EC_SB_REG_ALPHA__A 0x2010012 -#define EC_SB_REG_ALPHA__W 3 -#define EC_SB_REG_ALPHA__M 0x7 - -#define EC_SB_REG_ALPHA_INIT 0x0 - -#define EC_SB_REG_ALPHA_NH 0x0 - -#define EC_SB_REG_ALPHA_H1 0x1 - -#define EC_SB_REG_ALPHA_H2 0x2 - -#define EC_SB_REG_ALPHA_H4 0x3 - #define EC_SB_REG_PRIOR__A 0x2010013 -#define EC_SB_REG_PRIOR__W 1 -#define EC_SB_REG_PRIOR__M 0x1 -#define EC_SB_REG_PRIOR_INIT 0x0 #define EC_SB_REG_PRIOR_HI 0x0 #define EC_SB_REG_PRIOR_LO 0x1 - #define EC_SB_REG_CSI_HI__A 0x2010014 -#define EC_SB_REG_CSI_HI__W 5 -#define EC_SB_REG_CSI_HI__M 0x1F -#define EC_SB_REG_CSI_HI_INIT 0x1F -#define EC_SB_REG_CSI_HI_MAX 0x1F -#define EC_SB_REG_CSI_HI_MIN 0x0 -#define EC_SB_REG_CSI_HI_TAG 0x0 - #define EC_SB_REG_CSI_LO__A 0x2010015 -#define EC_SB_REG_CSI_LO__W 5 -#define EC_SB_REG_CSI_LO__M 0x1F -#define EC_SB_REG_CSI_LO_INIT 0x1F -#define EC_SB_REG_CSI_LO_MAX 0x1F -#define EC_SB_REG_CSI_LO_MIN 0x0 -#define EC_SB_REG_CSI_LO_TAG 0x0 - #define EC_SB_REG_SMB_TGL__A 0x2010016 -#define EC_SB_REG_SMB_TGL__W 1 -#define EC_SB_REG_SMB_TGL__M 0x1 -#define EC_SB_REG_SMB_TGL_OFF 0x0 -#define EC_SB_REG_SMB_TGL_ON 0x1 - #define EC_SB_REG_SNR_HI__A 0x2010017 -#define EC_SB_REG_SNR_HI__W 8 -#define EC_SB_REG_SNR_HI__M 0xFF -#define EC_SB_REG_SNR_HI_INIT 0xFF -#define EC_SB_REG_SNR_HI_MAX 0xFF -#define EC_SB_REG_SNR_HI_MIN 0x0 -#define EC_SB_REG_SNR_HI_TAG 0x0 - #define EC_SB_REG_SNR_MID__A 0x2010018 -#define EC_SB_REG_SNR_MID__W 8 -#define EC_SB_REG_SNR_MID__M 0xFF -#define EC_SB_REG_SNR_MID_INIT 0xFF -#define EC_SB_REG_SNR_MID_MAX 0xFF -#define EC_SB_REG_SNR_MID_MIN 0x0 -#define EC_SB_REG_SNR_MID_TAG 0x0 - #define EC_SB_REG_SNR_LO__A 0x2010019 -#define EC_SB_REG_SNR_LO__W 8 -#define EC_SB_REG_SNR_LO__M 0xFF -#define EC_SB_REG_SNR_LO_INIT 0xFF -#define EC_SB_REG_SNR_LO_MAX 0xFF -#define EC_SB_REG_SNR_LO_MIN 0x0 -#define EC_SB_REG_SNR_LO_TAG 0x0 - #define EC_SB_REG_SCALE_MSB__A 0x201001A -#define EC_SB_REG_SCALE_MSB__W 6 -#define EC_SB_REG_SCALE_MSB__M 0x3F -#define EC_SB_REG_SCALE_MSB_INIT 0x30 -#define EC_SB_REG_SCALE_MSB_MAX 0x3F - #define EC_SB_REG_SCALE_BIT2__A 0x201001B -#define EC_SB_REG_SCALE_BIT2__W 6 -#define EC_SB_REG_SCALE_BIT2__M 0x3F -#define EC_SB_REG_SCALE_BIT2_INIT 0x20 -#define EC_SB_REG_SCALE_BIT2_MAX 0x3F - #define EC_SB_REG_SCALE_LSB__A 0x201001C -#define EC_SB_REG_SCALE_LSB__W 6 -#define EC_SB_REG_SCALE_LSB__M 0x3F -#define EC_SB_REG_SCALE_LSB_INIT 0x10 -#define EC_SB_REG_SCALE_LSB_MAX 0x3F - #define EC_SB_REG_CSI_OFS__A 0x201001D -#define EC_SB_REG_CSI_OFS__W 4 -#define EC_SB_REG_CSI_OFS__M 0xF -#define EC_SB_REG_CSI_OFS_INIT 0x1 -#define EC_SB_REG_CSI_OFS_ADD__B 0 -#define EC_SB_REG_CSI_OFS_ADD__W 3 -#define EC_SB_REG_CSI_OFS_ADD__M 0x7 -#define EC_SB_REG_CSI_OFS_DIS__B 3 -#define EC_SB_REG_CSI_OFS_DIS__W 1 -#define EC_SB_REG_CSI_OFS_DIS__M 0x8 -#define EC_SB_REG_CSI_OFS_DIS_ENA 0x0 -#define EC_SB_REG_CSI_OFS_DIS_DIS 0x8 - -#define EC_SB_SD_RAM__A 0x2020000 - -#define EC_SB_BD0_RAM__A 0x2030000 - -#define EC_SB_BD1_RAM__A 0x2040000 - -#define EC_VD_SID 0x17 - #define EC_VD_REG_COMM_EXEC__A 0x2090000 -#define EC_VD_REG_COMM_EXEC__W 3 -#define EC_VD_REG_COMM_EXEC__M 0x7 -#define EC_VD_REG_COMM_EXEC_CTL__B 0 -#define EC_VD_REG_COMM_EXEC_CTL__W 3 -#define EC_VD_REG_COMM_EXEC_CTL__M 0x7 -#define EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 -#define EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define EC_VD_REG_COMM_STATE__A 0x2090001 -#define EC_VD_REG_COMM_STATE__W 4 -#define EC_VD_REG_COMM_STATE__M 0xF -#define EC_VD_REG_COMM_MB__A 0x2090002 -#define EC_VD_REG_COMM_MB__W 2 -#define EC_VD_REG_COMM_MB__M 0x3 -#define EC_VD_REG_COMM_MB_CTR__B 0 -#define EC_VD_REG_COMM_MB_CTR__W 1 -#define EC_VD_REG_COMM_MB_CTR__M 0x1 -#define EC_VD_REG_COMM_MB_CTR_OFF 0x0 -#define EC_VD_REG_COMM_MB_CTR_ON 0x1 -#define EC_VD_REG_COMM_MB_OBS__B 1 -#define EC_VD_REG_COMM_MB_OBS__W 1 -#define EC_VD_REG_COMM_MB_OBS__M 0x2 -#define EC_VD_REG_COMM_MB_OBS_OFF 0x0 -#define EC_VD_REG_COMM_MB_OBS_ON 0x2 - -#define EC_VD_REG_COMM_SERVICE0__A 0x2090003 -#define EC_VD_REG_COMM_SERVICE0__W 16 -#define EC_VD_REG_COMM_SERVICE0__M 0xFFFF -#define EC_VD_REG_COMM_SERVICE1__A 0x2090004 -#define EC_VD_REG_COMM_SERVICE1__W 16 -#define EC_VD_REG_COMM_SERVICE1__M 0xFFFF -#define EC_VD_REG_COMM_INT_STA__A 0x2090007 -#define EC_VD_REG_COMM_INT_STA__W 1 -#define EC_VD_REG_COMM_INT_STA__M 0x1 -#define EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 -#define EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 -#define EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 - -#define EC_VD_REG_COMM_INT_MSK__A 0x2090008 -#define EC_VD_REG_COMM_INT_MSK__W 1 -#define EC_VD_REG_COMM_INT_MSK__M 0x1 -#define EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 -#define EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 -#define EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 - #define EC_VD_REG_FORCE__A 0x2090010 -#define EC_VD_REG_FORCE__W 2 -#define EC_VD_REG_FORCE__M 0x3 -#define EC_VD_REG_FORCE_INIT 0x0 -#define EC_VD_REG_FORCE_FREE 0x0 -#define EC_VD_REG_FORCE_PROP 0x1 -#define EC_VD_REG_FORCE_FORCED 0x2 -#define EC_VD_REG_FORCE_FIXED 0x3 - #define EC_VD_REG_SET_CODERATE__A 0x2090011 -#define EC_VD_REG_SET_CODERATE__W 3 -#define EC_VD_REG_SET_CODERATE__M 0x7 -#define EC_VD_REG_SET_CODERATE_INIT 0x0 #define EC_VD_REG_SET_CODERATE_C1_2 0x0 #define EC_VD_REG_SET_CODERATE_C2_3 0x1 #define EC_VD_REG_SET_CODERATE_C3_4 0x2 #define EC_VD_REG_SET_CODERATE_C5_6 0x3 #define EC_VD_REG_SET_CODERATE_C7_8 0x4 - #define EC_VD_REG_REQ_SMB_CNT__A 0x2090012 -#define EC_VD_REG_REQ_SMB_CNT__W 16 -#define EC_VD_REG_REQ_SMB_CNT__M 0xFFFF -#define EC_VD_REG_REQ_SMB_CNT_INIT 0x0 - -#define EC_VD_REG_REQ_BIT_CNT__A 0x2090013 -#define EC_VD_REG_REQ_BIT_CNT__W 16 -#define EC_VD_REG_REQ_BIT_CNT__M 0xFFFF -#define EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF - #define EC_VD_REG_RLK_ENA__A 0x2090014 -#define EC_VD_REG_RLK_ENA__W 1 -#define EC_VD_REG_RLK_ENA__M 0x1 -#define EC_VD_REG_RLK_ENA_INIT 0x0 -#define EC_VD_REG_RLK_ENA_OFF 0x0 -#define EC_VD_REG_RLK_ENA_ON 0x1 - -#define EC_VD_REG_VAL__A 0x2090015 -#define EC_VD_REG_VAL__W 2 -#define EC_VD_REG_VAL__M 0x3 -#define EC_VD_REG_VAL_INIT 0x0 -#define EC_VD_REG_VAL_CODE 0x1 -#define EC_VD_REG_VAL_CNT 0x2 - -#define EC_VD_REG_GET_CODERATE__A 0x2090016 -#define EC_VD_REG_GET_CODERATE__W 3 -#define EC_VD_REG_GET_CODERATE__M 0x7 -#define EC_VD_REG_GET_CODERATE_INIT 0x0 -#define EC_VD_REG_GET_CODERATE_C1_2 0x0 -#define EC_VD_REG_GET_CODERATE_C2_3 0x1 -#define EC_VD_REG_GET_CODERATE_C3_4 0x2 -#define EC_VD_REG_GET_CODERATE_C5_6 0x3 -#define EC_VD_REG_GET_CODERATE_C7_8 0x4 - -#define EC_VD_REG_ERR_BIT_CNT__A 0x2090017 -#define EC_VD_REG_ERR_BIT_CNT__W 16 -#define EC_VD_REG_ERR_BIT_CNT__M 0xFFFF -#define EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF - -#define EC_VD_REG_IN_BIT_CNT__A 0x2090018 -#define EC_VD_REG_IN_BIT_CNT__W 16 -#define EC_VD_REG_IN_BIT_CNT__M 0xFFFF -#define EC_VD_REG_IN_BIT_CNT_INIT 0x0 - -#define EC_VD_REG_STS__A 0x2090019 -#define EC_VD_REG_STS__W 1 -#define EC_VD_REG_STS__M 0x1 -#define EC_VD_REG_STS_INIT 0x0 -#define EC_VD_REG_STS_NO_LOCK 0x0 -#define EC_VD_REG_STS_IN_LOCK 0x1 - -#define EC_VD_REG_RLK_CNT__A 0x209001A -#define EC_VD_REG_RLK_CNT__W 16 -#define EC_VD_REG_RLK_CNT__M 0xFFFF -#define EC_VD_REG_RLK_CNT_INIT 0x0 - -#define EC_VD_TB0_RAM__A 0x20A0000 - -#define EC_VD_TB1_RAM__A 0x20B0000 - -#define EC_VD_TB2_RAM__A 0x20C0000 - -#define EC_VD_TB3_RAM__A 0x20D0000 - -#define EC_VD_RE_RAM__A 0x2100000 - -#define EC_OD_SID 0x18 - #define EC_OD_REG_COMM_EXEC__A 0x2110000 -#define EC_OD_REG_COMM_EXEC__W 3 -#define EC_OD_REG_COMM_EXEC__M 0x7 -#define EC_OD_REG_COMM_EXEC_CTL__B 0 -#define EC_OD_REG_COMM_EXEC_CTL__W 3 -#define EC_OD_REG_COMM_EXEC_CTL__M 0x7 -#define EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 -#define EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define EC_OD_REG_COMM_MB__A 0x2110002 -#define EC_OD_REG_COMM_MB__W 3 -#define EC_OD_REG_COMM_MB__M 0x7 -#define EC_OD_REG_COMM_MB_CTR__B 0 -#define EC_OD_REG_COMM_MB_CTR__W 1 -#define EC_OD_REG_COMM_MB_CTR__M 0x1 -#define EC_OD_REG_COMM_MB_CTR_OFF 0x0 -#define EC_OD_REG_COMM_MB_CTR_ON 0x1 -#define EC_OD_REG_COMM_MB_OBS__B 1 -#define EC_OD_REG_COMM_MB_OBS__W 1 -#define EC_OD_REG_COMM_MB_OBS__M 0x2 -#define EC_OD_REG_COMM_MB_OBS_OFF 0x0 -#define EC_OD_REG_COMM_MB_OBS_ON 0x2 - -#define EC_OD_REG_COMM_SERVICE0__A 0x2110003 -#define EC_OD_REG_COMM_SERVICE0__W 10 -#define EC_OD_REG_COMM_SERVICE0__M 0x3FF -#define EC_OD_REG_COMM_SERVICE1__A 0x2110004 -#define EC_OD_REG_COMM_SERVICE1__W 11 -#define EC_OD_REG_COMM_SERVICE1__M 0x7FF - -#define EC_OD_REG_COMM_ACTIVATE__A 0x2110005 -#define EC_OD_REG_COMM_ACTIVATE__W 2 -#define EC_OD_REG_COMM_ACTIVATE__M 0x3 - -#define EC_OD_REG_COMM_COUNT__A 0x2110006 -#define EC_OD_REG_COMM_COUNT__W 16 -#define EC_OD_REG_COMM_COUNT__M 0xFFFF - -#define EC_OD_REG_COMM_INT_STA__A 0x2110007 -#define EC_OD_REG_COMM_INT_STA__W 2 -#define EC_OD_REG_COMM_INT_STA__M 0x3 -#define EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 -#define EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 -#define EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 -#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 -#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 -#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 - -#define EC_OD_REG_COMM_INT_MSK__A 0x2110008 -#define EC_OD_REG_COMM_INT_MSK__W 2 -#define EC_OD_REG_COMM_INT_MSK__M 0x3 -#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 -#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 -#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 -#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 -#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 -#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 - #define EC_OD_REG_SYNC__A 0x2110010 -#define EC_OD_REG_SYNC__W 12 -#define EC_OD_REG_SYNC__M 0xFFF -#define EC_OD_REG_SYNC_NR_SYNC__B 0 -#define EC_OD_REG_SYNC_NR_SYNC__W 5 -#define EC_OD_REG_SYNC_NR_SYNC__M 0x1F -#define EC_OD_REG_SYNC_IN_SYNC__B 5 -#define EC_OD_REG_SYNC_IN_SYNC__W 4 -#define EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 -#define EC_OD_REG_SYNC_OUT_SYNC__B 9 -#define EC_OD_REG_SYNC_OUT_SYNC__W 3 -#define EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 - -#define EC_OD_REG_NOSYNC__A 0x2110011 -#define EC_OD_REG_NOSYNC__W 8 -#define EC_OD_REG_NOSYNC__M 0xFF - #define EC_OD_DEINT_RAM__A 0x2120000 - -#define EC_RS_SID 0x19 - #define EC_RS_REG_COMM_EXEC__A 0x2130000 -#define EC_RS_REG_COMM_EXEC__W 3 -#define EC_RS_REG_COMM_EXEC__M 0x7 -#define EC_RS_REG_COMM_EXEC_CTL__B 0 -#define EC_RS_REG_COMM_EXEC_CTL__W 3 -#define EC_RS_REG_COMM_EXEC_CTL__M 0x7 -#define EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 -#define EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define EC_RS_REG_COMM_STATE__A 0x2130001 -#define EC_RS_REG_COMM_STATE__W 4 -#define EC_RS_REG_COMM_STATE__M 0xF -#define EC_RS_REG_COMM_MB__A 0x2130002 -#define EC_RS_REG_COMM_MB__W 2 -#define EC_RS_REG_COMM_MB__M 0x3 -#define EC_RS_REG_COMM_MB_CTR__B 0 -#define EC_RS_REG_COMM_MB_CTR__W 1 -#define EC_RS_REG_COMM_MB_CTR__M 0x1 -#define EC_RS_REG_COMM_MB_CTR_OFF 0x0 -#define EC_RS_REG_COMM_MB_CTR_ON 0x1 -#define EC_RS_REG_COMM_MB_OBS__B 1 -#define EC_RS_REG_COMM_MB_OBS__W 1 -#define EC_RS_REG_COMM_MB_OBS__M 0x2 -#define EC_RS_REG_COMM_MB_OBS_OFF 0x0 -#define EC_RS_REG_COMM_MB_OBS_ON 0x2 - -#define EC_RS_REG_COMM_SERVICE0__A 0x2130003 -#define EC_RS_REG_COMM_SERVICE0__W 16 -#define EC_RS_REG_COMM_SERVICE0__M 0xFFFF -#define EC_RS_REG_COMM_SERVICE1__A 0x2130004 -#define EC_RS_REG_COMM_SERVICE1__W 16 -#define EC_RS_REG_COMM_SERVICE1__M 0xFFFF -#define EC_RS_REG_COMM_INT_STA__A 0x2130007 -#define EC_RS_REG_COMM_INT_STA__W 1 -#define EC_RS_REG_COMM_INT_STA__M 0x1 -#define EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 -#define EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 -#define EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 - -#define EC_RS_REG_COMM_INT_MSK__A 0x2130008 -#define EC_RS_REG_COMM_INT_MSK__W 1 -#define EC_RS_REG_COMM_INT_MSK__M 0x1 -#define EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 -#define EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 -#define EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 - #define EC_RS_REG_REQ_PCK_CNT__A 0x2130010 -#define EC_RS_REG_REQ_PCK_CNT__W 16 -#define EC_RS_REG_REQ_PCK_CNT__M 0xFFFF -#define EC_RS_REG_REQ_PCK_CNT_INIT 0xFF - #define EC_RS_REG_VAL__A 0x2130011 -#define EC_RS_REG_VAL__W 1 -#define EC_RS_REG_VAL__M 0x1 -#define EC_RS_REG_VAL_INIT 0x0 #define EC_RS_REG_VAL_PCK 0x1 - -#define EC_RS_REG_ERR_PCK_CNT__A 0x2130012 -#define EC_RS_REG_ERR_PCK_CNT__W 16 -#define EC_RS_REG_ERR_PCK_CNT__M 0xFFFF -#define EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF - -#define EC_RS_REG_ERR_SMB_CNT__A 0x2130013 -#define EC_RS_REG_ERR_SMB_CNT__W 16 -#define EC_RS_REG_ERR_SMB_CNT__M 0xFFFF -#define EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF - -#define EC_RS_REG_ERR_BIT_CNT__A 0x2130014 -#define EC_RS_REG_ERR_BIT_CNT__W 16 -#define EC_RS_REG_ERR_BIT_CNT__M 0xFFFF -#define EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF - -#define EC_RS_REG_IN_PCK_CNT__A 0x2130015 -#define EC_RS_REG_IN_PCK_CNT__W 16 -#define EC_RS_REG_IN_PCK_CNT__M 0xFFFF -#define EC_RS_REG_IN_PCK_CNT_INIT 0x0 - #define EC_RS_EC_RAM__A 0x2140000 - -#define EC_OC_SID 0x1A - #define EC_OC_REG_COMM_EXEC__A 0x2150000 -#define EC_OC_REG_COMM_EXEC__W 3 -#define EC_OC_REG_COMM_EXEC__M 0x7 -#define EC_OC_REG_COMM_EXEC_CTL__B 0 -#define EC_OC_REG_COMM_EXEC_CTL__W 3 -#define EC_OC_REG_COMM_EXEC_CTL__M 0x7 -#define EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 #define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 #define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 -#define EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 - -#define EC_OC_REG_COMM_STATE__A 0x2150001 -#define EC_OC_REG_COMM_STATE__W 4 -#define EC_OC_REG_COMM_STATE__M 0xF - -#define EC_OC_REG_COMM_MB__A 0x2150002 -#define EC_OC_REG_COMM_MB__W 2 -#define EC_OC_REG_COMM_MB__M 0x3 -#define EC_OC_REG_COMM_MB_CTR__B 0 -#define EC_OC_REG_COMM_MB_CTR__W 1 -#define EC_OC_REG_COMM_MB_CTR__M 0x1 -#define EC_OC_REG_COMM_MB_CTR_OFF 0x0 -#define EC_OC_REG_COMM_MB_CTR_ON 0x1 -#define EC_OC_REG_COMM_MB_OBS__B 1 -#define EC_OC_REG_COMM_MB_OBS__W 1 -#define EC_OC_REG_COMM_MB_OBS__M 0x2 -#define EC_OC_REG_COMM_MB_OBS_OFF 0x0 -#define EC_OC_REG_COMM_MB_OBS_ON 0x2 - -#define EC_OC_REG_COMM_SERVICE0__A 0x2150003 -#define EC_OC_REG_COMM_SERVICE0__W 10 -#define EC_OC_REG_COMM_SERVICE0__M 0x3FF - -#define EC_OC_REG_COMM_SERVICE1__A 0x2150004 -#define EC_OC_REG_COMM_SERVICE1__W 11 -#define EC_OC_REG_COMM_SERVICE1__M 0x7FF - #define EC_OC_REG_COMM_INT_STA__A 0x2150007 -#define EC_OC_REG_COMM_INT_STA__W 6 -#define EC_OC_REG_COMM_INT_STA__M 0x3F -#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 -#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 -#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 -#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 -#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 -#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 -#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 -#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 -#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 -#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 -#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 -#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 -#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 -#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 -#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 -#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 -#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 -#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 - -#define EC_OC_REG_COMM_INT_MSK__A 0x2150008 -#define EC_OC_REG_COMM_INT_MSK__W 6 -#define EC_OC_REG_COMM_INT_MSK__M 0x3F -#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 -#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 -#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 -#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 -#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 -#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 -#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 -#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 -#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 -#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 -#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 -#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 -#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 -#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 -#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 -#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 -#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 -#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 - #define EC_OC_REG_OC_MODE_LOP__A 0x2150010 -#define EC_OC_REG_OC_MODE_LOP__W 16 -#define EC_OC_REG_OC_MODE_LOP__M 0xFFFF -#define EC_OC_REG_OC_MODE_LOP_INIT 0x0 - -#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 -#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 #define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 #define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 - -#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 -#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 #define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 -#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 - -#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 -#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 -#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 -#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 - -#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 -#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 -#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 -#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 - -#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 -#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 -#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 - -#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 -#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 -#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 #define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 - -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 - -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 - -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 - -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 - -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 - -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 - -#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 -#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 -#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 -#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 - -#define EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 -#define EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 -#define EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 -#define EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 - #define EC_OC_REG_OC_MODE_HIP__A 0x2150011 -#define EC_OC_REG_OC_MODE_HIP__W 14 -#define EC_OC_REG_OC_MODE_HIP__M 0x3FFF -#define EC_OC_REG_OC_MODE_HIP_INIT 0x0 - -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 - -#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 -#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 - -#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 -#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 -#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 -#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 - -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 -#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 - -#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 -#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 -#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 #define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 - -#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 -#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 -#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 -#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 - -#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 -#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 -#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 -#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 - -#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 -#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 -#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 - -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 - -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 #define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 - -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 - -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 -#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 - -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 - -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 -#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 - #define EC_OC_REG_OC_MPG_SIO__A 0x2150012 -#define EC_OC_REG_OC_MPG_SIO__W 12 #define EC_OC_REG_OC_MPG_SIO__M 0xFFF -#define EC_OC_REG_OC_MPG_SIO_INIT 0xFFF - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 - -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 -#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 - #define EC_OC_REG_OC_MON_SIO__A 0x2150013 -#define EC_OC_REG_OC_MON_SIO__W 12 -#define EC_OC_REG_OC_MON_SIO__M 0xFFF -#define EC_OC_REG_OC_MON_SIO_INIT 0xFFF - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__B 0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__M 0x1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_0_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_0_INPUT 0x1 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__B 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__M 0x2 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_1_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_1_INPUT 0x2 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__B 2 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__M 0x4 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_2_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_2_INPUT 0x4 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__B 3 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__M 0x8 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_3_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_3_INPUT 0x8 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__B 4 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__M 0x10 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_4_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_4_INPUT 0x10 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__B 5 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__M 0x20 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_5_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_5_INPUT 0x20 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__B 6 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__M 0x40 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_6_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_6_INPUT 0x40 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__B 7 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__M 0x80 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_7_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_7_INPUT 0x80 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__B 8 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__M 0x100 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_8_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_8_INPUT 0x100 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__B 9 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__M 0x200 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_9_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_9_INPUT 0x200 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__B 10 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__M 0x400 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_10_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_10_INPUT 0x400 - -#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__B 11 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__W 1 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__M 0x800 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_OUTPUT 0x0 -#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_INPUT 0x800 - #define EC_OC_REG_DTO_INC_LOP__A 0x2150014 -#define EC_OC_REG_DTO_INC_LOP__W 16 -#define EC_OC_REG_DTO_INC_LOP__M 0xFFFF -#define EC_OC_REG_DTO_INC_LOP_INIT 0x0 - #define EC_OC_REG_DTO_INC_HIP__A 0x2150015 -#define EC_OC_REG_DTO_INC_HIP__W 8 -#define EC_OC_REG_DTO_INC_HIP__M 0xFF -#define EC_OC_REG_DTO_INC_HIP_INIT 0x0 - #define EC_OC_REG_SNC_ISC_LVL__A 0x2150016 -#define EC_OC_REG_SNC_ISC_LVL__W 12 -#define EC_OC_REG_SNC_ISC_LVL__M 0xFFF -#define EC_OC_REG_SNC_ISC_LVL_INIT 0x0 - -#define EC_OC_REG_SNC_ISC_LVL_ISC__B 0 -#define EC_OC_REG_SNC_ISC_LVL_ISC__W 4 -#define EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF - -#define EC_OC_REG_SNC_ISC_LVL_OSC__B 4 -#define EC_OC_REG_SNC_ISC_LVL_OSC__W 4 #define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 - -#define EC_OC_REG_SNC_ISC_LVL_NSC__B 8 -#define EC_OC_REG_SNC_ISC_LVL_NSC__W 4 -#define EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 - -#define EC_OC_REG_SNC_NSC_LVL__A 0x2150017 -#define EC_OC_REG_SNC_NSC_LVL__W 8 -#define EC_OC_REG_SNC_NSC_LVL__M 0xFF -#define EC_OC_REG_SNC_NSC_LVL_INIT 0x0 - -#define EC_OC_REG_SNC_SNC_MODE__A 0x2150019 -#define EC_OC_REG_SNC_SNC_MODE__W 2 -#define EC_OC_REG_SNC_SNC_MODE__M 0x3 -#define EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 -#define EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 -#define EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 - -#define EC_OC_REG_SNC_PCK_NMB__A 0x215001A -#define EC_OC_REG_SNC_PCK_NMB__W 16 -#define EC_OC_REG_SNC_PCK_NMB__M 0xFFFF - -#define EC_OC_REG_SNC_PCK_CNT__A 0x215001B -#define EC_OC_REG_SNC_PCK_CNT__W 16 -#define EC_OC_REG_SNC_PCK_CNT__M 0xFFFF - -#define EC_OC_REG_SNC_PCK_ERR__A 0x215001C -#define EC_OC_REG_SNC_PCK_ERR__W 16 -#define EC_OC_REG_SNC_PCK_ERR__M 0xFFFF - #define EC_OC_REG_TMD_TOP_MODE__A 0x215001D -#define EC_OC_REG_TMD_TOP_MODE__W 2 -#define EC_OC_REG_TMD_TOP_MODE__M 0x3 -#define EC_OC_REG_TMD_TOP_MODE_INIT 0x0 -#define EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 -#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 -#define EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 -#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 - #define EC_OC_REG_TMD_TOP_CNT__A 0x215001E -#define EC_OC_REG_TMD_TOP_CNT__W 10 -#define EC_OC_REG_TMD_TOP_CNT__M 0x3FF -#define EC_OC_REG_TMD_TOP_CNT_INIT 0x0 - #define EC_OC_REG_TMD_HIL_MAR__A 0x215001F -#define EC_OC_REG_TMD_HIL_MAR__W 10 -#define EC_OC_REG_TMD_HIL_MAR__M 0x3FF -#define EC_OC_REG_TMD_HIL_MAR_INIT 0x0 - #define EC_OC_REG_TMD_LOL_MAR__A 0x2150020 -#define EC_OC_REG_TMD_LOL_MAR__W 10 -#define EC_OC_REG_TMD_LOL_MAR__M 0x3FF -#define EC_OC_REG_TMD_LOL_MAR_INIT 0x0 - #define EC_OC_REG_TMD_CUR_CNT__A 0x2150021 -#define EC_OC_REG_TMD_CUR_CNT__W 4 -#define EC_OC_REG_TMD_CUR_CNT__M 0xF -#define EC_OC_REG_TMD_CUR_CNT_INIT 0x0 - -#define EC_OC_REG_TMD_IUR_CNT__A 0x2150022 -#define EC_OC_REG_TMD_IUR_CNT__W 4 -#define EC_OC_REG_TMD_IUR_CNT__M 0xF -#define EC_OC_REG_TMD_IUR_CNT_INIT 0x0 - #define EC_OC_REG_AVR_ASH_CNT__A 0x2150023 -#define EC_OC_REG_AVR_ASH_CNT__W 4 -#define EC_OC_REG_AVR_ASH_CNT__M 0xF -#define EC_OC_REG_AVR_ASH_CNT_INIT 0x0 - #define EC_OC_REG_AVR_BSH_CNT__A 0x2150024 -#define EC_OC_REG_AVR_BSH_CNT__W 4 -#define EC_OC_REG_AVR_BSH_CNT__M 0xF -#define EC_OC_REG_AVR_BSH_CNT_INIT 0x0 - -#define EC_OC_REG_AVR_AVE_LOP__A 0x2150025 -#define EC_OC_REG_AVR_AVE_LOP__W 16 -#define EC_OC_REG_AVR_AVE_LOP__M 0xFFFF - -#define EC_OC_REG_AVR_AVE_HIP__A 0x2150026 -#define EC_OC_REG_AVR_AVE_HIP__W 5 -#define EC_OC_REG_AVR_AVE_HIP__M 0x1F - #define EC_OC_REG_RCN_MODE__A 0x2150027 -#define EC_OC_REG_RCN_MODE__W 3 -#define EC_OC_REG_RCN_MODE__M 0x7 -#define EC_OC_REG_RCN_MODE_INIT 0x0 - -#define EC_OC_REG_RCN_MODE_MODE_0__B 0 -#define EC_OC_REG_RCN_MODE_MODE_0__W 1 -#define EC_OC_REG_RCN_MODE_MODE_0__M 0x1 -#define EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 -#define EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 - -#define EC_OC_REG_RCN_MODE_MODE_1__B 1 -#define EC_OC_REG_RCN_MODE_MODE_1__W 1 -#define EC_OC_REG_RCN_MODE_MODE_1__M 0x2 -#define EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 -#define EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 - -#define EC_OC_REG_RCN_MODE_MODE_2__B 2 -#define EC_OC_REG_RCN_MODE_MODE_2__W 1 -#define EC_OC_REG_RCN_MODE_MODE_2__M 0x4 -#define EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 -#define EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 - #define EC_OC_REG_RCN_CRA_LOP__A 0x2150028 -#define EC_OC_REG_RCN_CRA_LOP__W 16 -#define EC_OC_REG_RCN_CRA_LOP__M 0xFFFF -#define EC_OC_REG_RCN_CRA_LOP_INIT 0x0 - #define EC_OC_REG_RCN_CRA_HIP__A 0x2150029 -#define EC_OC_REG_RCN_CRA_HIP__W 8 -#define EC_OC_REG_RCN_CRA_HIP__M 0xFF -#define EC_OC_REG_RCN_CRA_HIP_INIT 0x0 - #define EC_OC_REG_RCN_CST_LOP__A 0x215002A -#define EC_OC_REG_RCN_CST_LOP__W 16 -#define EC_OC_REG_RCN_CST_LOP__M 0xFFFF -#define EC_OC_REG_RCN_CST_LOP_INIT 0x0 - #define EC_OC_REG_RCN_CST_HIP__A 0x215002B -#define EC_OC_REG_RCN_CST_HIP__W 8 -#define EC_OC_REG_RCN_CST_HIP__M 0xFF -#define EC_OC_REG_RCN_CST_HIP_INIT 0x0 - -#define EC_OC_REG_RCN_SET_LVL__A 0x215002C -#define EC_OC_REG_RCN_SET_LVL__W 9 -#define EC_OC_REG_RCN_SET_LVL__M 0x1FF -#define EC_OC_REG_RCN_SET_LVL_INIT 0x0 - -#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D -#define EC_OC_REG_RCN_GAI_LVL__W 4 -#define EC_OC_REG_RCN_GAI_LVL__M 0xF -#define EC_OC_REG_RCN_GAI_LVL_INIT 0x0 - -#define EC_OC_REG_RCN_DRA_LOP__A 0x215002E -#define EC_OC_REG_RCN_DRA_LOP__W 16 -#define EC_OC_REG_RCN_DRA_LOP__M 0xFFFF - -#define EC_OC_REG_RCN_DRA_HIP__A 0x215002F -#define EC_OC_REG_RCN_DRA_HIP__W 8 -#define EC_OC_REG_RCN_DRA_HIP__M 0xFF - -#define EC_OC_REG_RCN_DOF_LOP__A 0x2150030 -#define EC_OC_REG_RCN_DOF_LOP__W 16 -#define EC_OC_REG_RCN_DOF_LOP__M 0xFFFF - -#define EC_OC_REG_RCN_DOF_HIP__A 0x2150031 -#define EC_OC_REG_RCN_DOF_HIP__W 8 -#define EC_OC_REG_RCN_DOF_HIP__M 0xFF - -#define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 -#define EC_OC_REG_RCN_CLP_LOP__W 16 -#define EC_OC_REG_RCN_CLP_LOP__M 0xFFFF -#define EC_OC_REG_RCN_CLP_LOP_INIT 0xFFFF - -#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 -#define EC_OC_REG_RCN_CLP_HIP__W 8 -#define EC_OC_REG_RCN_CLP_HIP__M 0xFF -#define EC_OC_REG_RCN_CLP_HIP_INIT 0xFF - -#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 -#define EC_OC_REG_RCN_MAP_LOP__W 16 -#define EC_OC_REG_RCN_MAP_LOP__M 0xFFFF - -#define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 -#define EC_OC_REG_RCN_MAP_HIP__W 8 -#define EC_OC_REG_RCN_MAP_HIP__M 0xFF - -#define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 -#define EC_OC_REG_OCR_MPG_UOS__W 12 -#define EC_OC_REG_OCR_MPG_UOS__M 0xFFF -#define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 -#define EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 -#define EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 -#define EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 -#define EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 -#define EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 -#define EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 -#define EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 -#define EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 -#define EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 -#define EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 -#define EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 - -#define EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 -#define EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 -#define EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 -#define EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 - -#define EC_OC_REG_OCR_MPG_UOS_ERR__B 8 -#define EC_OC_REG_OCR_MPG_UOS_ERR__W 1 -#define EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 -#define EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 - -#define EC_OC_REG_OCR_MPG_UOS_STR__B 9 -#define EC_OC_REG_OCR_MPG_UOS_STR__W 1 -#define EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 -#define EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 - -#define EC_OC_REG_OCR_MPG_UOS_VAL__B 10 -#define EC_OC_REG_OCR_MPG_UOS_VAL__W 1 -#define EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 -#define EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 - -#define EC_OC_REG_OCR_MPG_UOS_CLK__B 11 -#define EC_OC_REG_OCR_MPG_UOS_CLK__W 1 -#define EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 -#define EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 - -#define EC_OC_REG_OCR_MPG_WRI__A 0x2150037 -#define EC_OC_REG_OCR_MPG_WRI__W 12 -#define EC_OC_REG_OCR_MPG_WRI__M 0xFFF -#define EC_OC_REG_OCR_MPG_WRI_INIT 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 -#define EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 -#define EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 -#define EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 -#define EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 -#define EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 -#define EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 -#define EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 -#define EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 -#define EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 -#define EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 -#define EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 -#define EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 -#define EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 -#define EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 -#define EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 -#define EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 -#define EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 -#define EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 -#define EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 -#define EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 -#define EC_OC_REG_OCR_MPG_WRI_ERR__B 8 -#define EC_OC_REG_OCR_MPG_WRI_ERR__W 1 -#define EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 -#define EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 -#define EC_OC_REG_OCR_MPG_WRI_STR__B 9 -#define EC_OC_REG_OCR_MPG_WRI_STR__W 1 -#define EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 -#define EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 -#define EC_OC_REG_OCR_MPG_WRI_VAL__B 10 -#define EC_OC_REG_OCR_MPG_WRI_VAL__W 1 -#define EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 -#define EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 -#define EC_OC_REG_OCR_MPG_WRI_CLK__B 11 -#define EC_OC_REG_OCR_MPG_WRI_CLK__W 1 -#define EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 -#define EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 -#define EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 - +#define EC_OC_REG_RCN_SET_LVL__A 0x215002C +#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D +#define EC_OC_REG_RCN_CLP_LOP__A 0x2150032 +#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033 +#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034 +#define EC_OC_REG_RCN_MAP_HIP__A 0x2150035 +#define EC_OC_REG_OCR_MPG_UOS__A 0x2150036 +#define EC_OC_REG_OCR_MPG_UOS__M 0xFFF +#define EC_OC_REG_OCR_MPG_UOS_INIT 0x0 #define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 -#define EC_OC_REG_OCR_MPG_USR_DAT__W 12 -#define EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF - #define EC_OC_REG_OCR_MON_UOS__A 0x2150039 -#define EC_OC_REG_OCR_MON_UOS__W 12 -#define EC_OC_REG_OCR_MON_UOS__M 0xFFF -#define EC_OC_REG_OCR_MON_UOS_INIT 0x0 - -#define EC_OC_REG_OCR_MON_UOS_DAT_0__B 0 -#define EC_OC_REG_OCR_MON_UOS_DAT_0__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_0__M 0x1 -#define EC_OC_REG_OCR_MON_UOS_DAT_0_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1 - -#define EC_OC_REG_OCR_MON_UOS_DAT_1__B 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_1__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_1__M 0x2 -#define EC_OC_REG_OCR_MON_UOS_DAT_1_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2 - -#define EC_OC_REG_OCR_MON_UOS_DAT_2__B 2 -#define EC_OC_REG_OCR_MON_UOS_DAT_2__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_2__M 0x4 -#define EC_OC_REG_OCR_MON_UOS_DAT_2_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4 - -#define EC_OC_REG_OCR_MON_UOS_DAT_3__B 3 -#define EC_OC_REG_OCR_MON_UOS_DAT_3__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_3__M 0x8 -#define EC_OC_REG_OCR_MON_UOS_DAT_3_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8 - -#define EC_OC_REG_OCR_MON_UOS_DAT_4__B 4 -#define EC_OC_REG_OCR_MON_UOS_DAT_4__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_4__M 0x10 -#define EC_OC_REG_OCR_MON_UOS_DAT_4_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10 - -#define EC_OC_REG_OCR_MON_UOS_DAT_5__B 5 -#define EC_OC_REG_OCR_MON_UOS_DAT_5__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_5__M 0x20 -#define EC_OC_REG_OCR_MON_UOS_DAT_5_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20 - -#define EC_OC_REG_OCR_MON_UOS_DAT_6__B 6 -#define EC_OC_REG_OCR_MON_UOS_DAT_6__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_6__M 0x40 -#define EC_OC_REG_OCR_MON_UOS_DAT_6_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40 - -#define EC_OC_REG_OCR_MON_UOS_DAT_7__B 7 -#define EC_OC_REG_OCR_MON_UOS_DAT_7__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_7__M 0x80 -#define EC_OC_REG_OCR_MON_UOS_DAT_7_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80 - -#define EC_OC_REG_OCR_MON_UOS_DAT_8__B 8 -#define EC_OC_REG_OCR_MON_UOS_DAT_8__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_8__M 0x100 -#define EC_OC_REG_OCR_MON_UOS_DAT_8_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100 - -#define EC_OC_REG_OCR_MON_UOS_DAT_9__B 9 -#define EC_OC_REG_OCR_MON_UOS_DAT_9__W 1 -#define EC_OC_REG_OCR_MON_UOS_DAT_9__M 0x200 -#define EC_OC_REG_OCR_MON_UOS_DAT_9_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200 - -#define EC_OC_REG_OCR_MON_UOS_VAL__B 10 -#define EC_OC_REG_OCR_MON_UOS_VAL__W 1 -#define EC_OC_REG_OCR_MON_UOS_VAL__M 0x400 -#define EC_OC_REG_OCR_MON_UOS_VAL_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400 - -#define EC_OC_REG_OCR_MON_UOS_CLK__B 11 -#define EC_OC_REG_OCR_MON_UOS_CLK__W 1 -#define EC_OC_REG_OCR_MON_UOS_CLK__M 0x800 -#define EC_OC_REG_OCR_MON_UOS_CLK_DISABLE 0x0 #define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800 - #define EC_OC_REG_OCR_MON_WRI__A 0x215003A -#define EC_OC_REG_OCR_MON_WRI__W 12 -#define EC_OC_REG_OCR_MON_WRI__M 0xFFF #define EC_OC_REG_OCR_MON_WRI_INIT 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_0__B 0 -#define EC_OC_REG_OCR_MON_WRI_DAT_0__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_0__M 0x1 -#define EC_OC_REG_OCR_MON_WRI_DAT_0_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_0_ENABLE 0x1 -#define EC_OC_REG_OCR_MON_WRI_DAT_1__B 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_1__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_1__M 0x2 -#define EC_OC_REG_OCR_MON_WRI_DAT_1_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_1_ENABLE 0x2 -#define EC_OC_REG_OCR_MON_WRI_DAT_2__B 2 -#define EC_OC_REG_OCR_MON_WRI_DAT_2__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_2__M 0x4 -#define EC_OC_REG_OCR_MON_WRI_DAT_2_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_2_ENABLE 0x4 -#define EC_OC_REG_OCR_MON_WRI_DAT_3__B 3 -#define EC_OC_REG_OCR_MON_WRI_DAT_3__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_3__M 0x8 -#define EC_OC_REG_OCR_MON_WRI_DAT_3_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_3_ENABLE 0x8 -#define EC_OC_REG_OCR_MON_WRI_DAT_4__B 4 -#define EC_OC_REG_OCR_MON_WRI_DAT_4__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_4__M 0x10 -#define EC_OC_REG_OCR_MON_WRI_DAT_4_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_4_ENABLE 0x10 -#define EC_OC_REG_OCR_MON_WRI_DAT_5__B 5 -#define EC_OC_REG_OCR_MON_WRI_DAT_5__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_5__M 0x20 -#define EC_OC_REG_OCR_MON_WRI_DAT_5_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_5_ENABLE 0x20 -#define EC_OC_REG_OCR_MON_WRI_DAT_6__B 6 -#define EC_OC_REG_OCR_MON_WRI_DAT_6__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_6__M 0x40 -#define EC_OC_REG_OCR_MON_WRI_DAT_6_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_6_ENABLE 0x40 -#define EC_OC_REG_OCR_MON_WRI_DAT_7__B 7 -#define EC_OC_REG_OCR_MON_WRI_DAT_7__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_7__M 0x80 -#define EC_OC_REG_OCR_MON_WRI_DAT_7_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_7_ENABLE 0x80 -#define EC_OC_REG_OCR_MON_WRI_DAT_8__B 8 -#define EC_OC_REG_OCR_MON_WRI_DAT_8__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_8__M 0x100 -#define EC_OC_REG_OCR_MON_WRI_DAT_8_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_8_ENABLE 0x100 -#define EC_OC_REG_OCR_MON_WRI_DAT_9__B 9 -#define EC_OC_REG_OCR_MON_WRI_DAT_9__W 1 -#define EC_OC_REG_OCR_MON_WRI_DAT_9__M 0x200 -#define EC_OC_REG_OCR_MON_WRI_DAT_9_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_DAT_9_ENABLE 0x200 -#define EC_OC_REG_OCR_MON_WRI_VAL__B 10 -#define EC_OC_REG_OCR_MON_WRI_VAL__W 1 -#define EC_OC_REG_OCR_MON_WRI_VAL__M 0x400 -#define EC_OC_REG_OCR_MON_WRI_VAL_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_VAL_ENABLE 0x400 -#define EC_OC_REG_OCR_MON_WRI_CLK__B 11 -#define EC_OC_REG_OCR_MON_WRI_CLK__W 1 -#define EC_OC_REG_OCR_MON_WRI_CLK__M 0x800 -#define EC_OC_REG_OCR_MON_WRI_CLK_DISABLE 0x0 -#define EC_OC_REG_OCR_MON_WRI_CLK_ENABLE 0x800 - -#define EC_OC_REG_OCR_MON_USR_DAT__A 0x215003B -#define EC_OC_REG_OCR_MON_USR_DAT__W 12 -#define EC_OC_REG_OCR_MON_USR_DAT__M 0xFFF - -#define EC_OC_REG_OCR_MON_CNT__A 0x215003C -#define EC_OC_REG_OCR_MON_CNT__W 14 -#define EC_OC_REG_OCR_MON_CNT__M 0x3FFF -#define EC_OC_REG_OCR_MON_CNT_INIT 0x0 - -#define EC_OC_REG_OCR_MON_RDX__A 0x215003D -#define EC_OC_REG_OCR_MON_RDX__W 1 -#define EC_OC_REG_OCR_MON_RDX__M 0x1 -#define EC_OC_REG_OCR_MON_RDX_INIT 0x0 - -#define EC_OC_REG_OCR_MON_RD0__A 0x215003E -#define EC_OC_REG_OCR_MON_RD0__W 10 -#define EC_OC_REG_OCR_MON_RD0__M 0x3FF - -#define EC_OC_REG_OCR_MON_RD1__A 0x215003F -#define EC_OC_REG_OCR_MON_RD1__W 10 -#define EC_OC_REG_OCR_MON_RD1__M 0x3FF - -#define EC_OC_REG_OCR_MON_RD2__A 0x2150040 -#define EC_OC_REG_OCR_MON_RD2__W 10 -#define EC_OC_REG_OCR_MON_RD2__M 0x3FF - -#define EC_OC_REG_OCR_MON_RD3__A 0x2150041 -#define EC_OC_REG_OCR_MON_RD3__W 10 -#define EC_OC_REG_OCR_MON_RD3__M 0x3FF - -#define EC_OC_REG_OCR_MON_RD4__A 0x2150042 -#define EC_OC_REG_OCR_MON_RD4__W 10 -#define EC_OC_REG_OCR_MON_RD4__M 0x3FF - -#define EC_OC_REG_OCR_MON_RD5__A 0x2150043 -#define EC_OC_REG_OCR_MON_RD5__W 10 -#define EC_OC_REG_OCR_MON_RD5__M 0x3FF - -#define EC_OC_REG_OCR_INV_MON__A 0x2150044 -#define EC_OC_REG_OCR_INV_MON__W 12 -#define EC_OC_REG_OCR_INV_MON__M 0xFFF -#define EC_OC_REG_OCR_INV_MON_INIT 0x0 - #define EC_OC_REG_IPR_INV_MPG__A 0x2150045 -#define EC_OC_REG_IPR_INV_MPG__W 12 -#define EC_OC_REG_IPR_INV_MPG__M 0xFFF -#define EC_OC_REG_IPR_INV_MPG_INIT 0x0 - -#define EC_OC_REG_IPR_MSR_SNC__A 0x2150046 -#define EC_OC_REG_IPR_MSR_SNC__W 6 -#define EC_OC_REG_IPR_MSR_SNC__M 0x3F -#define EC_OC_REG_IPR_MSR_SNC_INIT 0x0 - -#define EC_OC_RAM__A 0x2160000 - -#define CC_SID 0x1B - -#define CC_COMM_EXEC__A 0x2400000 -#define CC_COMM_EXEC__W 3 -#define CC_COMM_EXEC__M 0x7 -#define CC_COMM_EXEC_CTL__B 0 -#define CC_COMM_EXEC_CTL__W 3 -#define CC_COMM_EXEC_CTL__M 0x7 -#define CC_COMM_EXEC_CTL_STOP 0x0 -#define CC_COMM_EXEC_CTL_ACTIVE 0x1 -#define CC_COMM_EXEC_CTL_HOLD 0x2 -#define CC_COMM_EXEC_CTL_STEP 0x3 -#define CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define CC_COMM_STATE__A 0x2400001 -#define CC_COMM_STATE__W 16 -#define CC_COMM_STATE__M 0xFFFF -#define CC_COMM_MB__A 0x2400002 -#define CC_COMM_MB__W 16 -#define CC_COMM_MB__M 0xFFFF -#define CC_COMM_SERVICE0__A 0x2400003 -#define CC_COMM_SERVICE0__W 16 -#define CC_COMM_SERVICE0__M 0xFFFF -#define CC_COMM_SERVICE1__A 0x2400004 -#define CC_COMM_SERVICE1__W 16 -#define CC_COMM_SERVICE1__M 0xFFFF -#define CC_COMM_INT_STA__A 0x2400007 -#define CC_COMM_INT_STA__W 16 -#define CC_COMM_INT_STA__M 0xFFFF -#define CC_COMM_INT_MSK__A 0x2400008 -#define CC_COMM_INT_MSK__W 16 -#define CC_COMM_INT_MSK__M 0xFFFF - -#define CC_REG_COMM_EXEC__A 0x2410000 -#define CC_REG_COMM_EXEC__W 3 -#define CC_REG_COMM_EXEC__M 0x7 -#define CC_REG_COMM_EXEC_CTL__B 0 -#define CC_REG_COMM_EXEC_CTL__W 3 -#define CC_REG_COMM_EXEC_CTL__M 0x7 -#define CC_REG_COMM_EXEC_CTL_STOP 0x0 -#define CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define CC_REG_COMM_EXEC_CTL_HOLD 0x2 -#define CC_REG_COMM_EXEC_CTL_STEP 0x3 -#define CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define CC_REG_COMM_STATE__A 0x2410001 -#define CC_REG_COMM_STATE__W 16 -#define CC_REG_COMM_STATE__M 0xFFFF -#define CC_REG_COMM_MB__A 0x2410002 -#define CC_REG_COMM_MB__W 16 -#define CC_REG_COMM_MB__M 0xFFFF -#define CC_REG_COMM_SERVICE0__A 0x2410003 -#define CC_REG_COMM_SERVICE0__W 16 -#define CC_REG_COMM_SERVICE0__M 0xFFFF -#define CC_REG_COMM_SERVICE1__A 0x2410004 -#define CC_REG_COMM_SERVICE1__W 16 -#define CC_REG_COMM_SERVICE1__M 0xFFFF -#define CC_REG_COMM_INT_STA__A 0x2410007 -#define CC_REG_COMM_INT_STA__W 16 -#define CC_REG_COMM_INT_STA__M 0xFFFF -#define CC_REG_COMM_INT_MSK__A 0x2410008 -#define CC_REG_COMM_INT_MSK__W 16 -#define CC_REG_COMM_INT_MSK__M 0xFFFF - #define CC_REG_OSC_MODE__A 0x2410010 -#define CC_REG_OSC_MODE__W 2 -#define CC_REG_OSC_MODE__M 0x3 -#define CC_REG_OSC_MODE_OHW 0x0 #define CC_REG_OSC_MODE_M20 0x1 -#define CC_REG_OSC_MODE_M48 0x2 - #define CC_REG_PLL_MODE__A 0x2410011 -#define CC_REG_PLL_MODE__W 6 -#define CC_REG_PLL_MODE__M 0x3F -#define CC_REG_PLL_MODE_INIT 0xC -#define CC_REG_PLL_MODE_BYPASS__B 0 -#define CC_REG_PLL_MODE_BYPASS__W 2 -#define CC_REG_PLL_MODE_BYPASS__M 0x3 -#define CC_REG_PLL_MODE_BYPASS_OHW 0x0 #define CC_REG_PLL_MODE_BYPASS_PLL 0x1 -#define CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 -#define CC_REG_PLL_MODE_PUMP__B 2 -#define CC_REG_PLL_MODE_PUMP__W 3 -#define CC_REG_PLL_MODE_PUMP__M 0x1C -#define CC_REG_PLL_MODE_PUMP_OFF 0x0 -#define CC_REG_PLL_MODE_PUMP_CUR_08 0x4 -#define CC_REG_PLL_MODE_PUMP_CUR_09 0x8 -#define CC_REG_PLL_MODE_PUMP_CUR_10 0xC -#define CC_REG_PLL_MODE_PUMP_CUR_11 0x10 #define CC_REG_PLL_MODE_PUMP_CUR_12 0x14 -#define CC_REG_PLL_MODE_OUT_EN__B 5 -#define CC_REG_PLL_MODE_OUT_EN__W 1 -#define CC_REG_PLL_MODE_OUT_EN__M 0x20 -#define CC_REG_PLL_MODE_OUT_EN_OFF 0x0 -#define CC_REG_PLL_MODE_OUT_EN_ON 0x20 - #define CC_REG_REF_DIVIDE__A 0x2410012 -#define CC_REG_REF_DIVIDE__W 4 -#define CC_REG_REF_DIVIDE__M 0xF -#define CC_REG_REF_DIVIDE_INIT 0xA -#define CC_REG_REF_DIVIDE_OHW 0x0 -#define CC_REG_REF_DIVIDE_D01 0x1 -#define CC_REG_REF_DIVIDE_D02 0x2 -#define CC_REG_REF_DIVIDE_D03 0x3 -#define CC_REG_REF_DIVIDE_D04 0x4 -#define CC_REG_REF_DIVIDE_D05 0x5 -#define CC_REG_REF_DIVIDE_D06 0x6 -#define CC_REG_REF_DIVIDE_D07 0x7 -#define CC_REG_REF_DIVIDE_D08 0x8 -#define CC_REG_REF_DIVIDE_D09 0x9 -#define CC_REG_REF_DIVIDE_D10 0xA - -#define CC_REG_REF_DELAY__A 0x2410013 -#define CC_REG_REF_DELAY__W 3 -#define CC_REG_REF_DELAY__M 0x7 -#define CC_REG_REF_DELAY_EDGE__B 0 -#define CC_REG_REF_DELAY_EDGE__W 1 -#define CC_REG_REF_DELAY_EDGE__M 0x1 -#define CC_REG_REF_DELAY_EDGE_POS 0x0 -#define CC_REG_REF_DELAY_EDGE_NEG 0x1 -#define CC_REG_REF_DELAY_DELAY__B 1 -#define CC_REG_REF_DELAY_DELAY__W 2 -#define CC_REG_REF_DELAY_DELAY__M 0x6 -#define CC_REG_REF_DELAY_DELAY_DEL_0 0x0 -#define CC_REG_REF_DELAY_DELAY_DEL_3 0x2 -#define CC_REG_REF_DELAY_DELAY_DEL_6 0x4 -#define CC_REG_REF_DELAY_DELAY_DEL_9 0x6 - -#define CC_REG_CLK_DELAY__A 0x2410014 -#define CC_REG_CLK_DELAY__W 4 -#define CC_REG_CLK_DELAY__M 0xF -#define CC_REG_CLK_DELAY_OFF 0x0 - #define CC_REG_PWD_MODE__A 0x2410015 -#define CC_REG_PWD_MODE__W 2 -#define CC_REG_PWD_MODE__M 0x3 -#define CC_REG_PWD_MODE_UP 0x0 -#define CC_REG_PWD_MODE_DOWN_CLK 0x1 #define CC_REG_PWD_MODE_DOWN_PLL 0x2 -#define CC_REG_PWD_MODE_DOWN_OSC 0x3 - -#define CC_REG_SOFT_RST__A 0x2410016 -#define CC_REG_SOFT_RST__W 2 -#define CC_REG_SOFT_RST__M 0x3 -#define CC_REG_SOFT_RST_SYS__B 0 -#define CC_REG_SOFT_RST_SYS__W 1 -#define CC_REG_SOFT_RST_SYS__M 0x1 -#define CC_REG_SOFT_RST_OSC__B 1 -#define CC_REG_SOFT_RST_OSC__W 1 -#define CC_REG_SOFT_RST_OSC__M 0x2 - #define CC_REG_UPDATE__A 0x2410017 -#define CC_REG_UPDATE__W 16 -#define CC_REG_UPDATE__M 0xFFFF #define CC_REG_UPDATE_KEY 0x3973 - -#define CC_REG_PLL_LOCK__A 0x2410018 -#define CC_REG_PLL_LOCK__W 1 -#define CC_REG_PLL_LOCK__M 0x1 -#define CC_REG_PLL_LOCK_LOCK 0x1 - #define CC_REG_JTAGID_L__A 0x2410019 -#define CC_REG_JTAGID_L__W 16 -#define CC_REG_JTAGID_L__M 0xFFFF -#define CC_REG_JTAGID_L_INIT 0x0 - -#define CC_REG_JTAGID_H__A 0x241001A -#define CC_REG_JTAGID_H__W 16 -#define CC_REG_JTAGID_H__M 0xFFFF -#define CC_REG_JTAGID_H_INIT 0x0 - -#define LC_SID 0x1C - #define LC_COMM_EXEC__A 0x2800000 -#define LC_COMM_EXEC__W 3 -#define LC_COMM_EXEC__M 0x7 -#define LC_COMM_EXEC_CTL__B 0 -#define LC_COMM_EXEC_CTL__W 3 -#define LC_COMM_EXEC_CTL__M 0x7 -#define LC_COMM_EXEC_CTL_STOP 0x0 -#define LC_COMM_EXEC_CTL_ACTIVE 0x1 -#define LC_COMM_EXEC_CTL_HOLD 0x2 -#define LC_COMM_EXEC_CTL_STEP 0x3 -#define LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define LC_COMM_STATE__A 0x2800001 -#define LC_COMM_STATE__W 16 -#define LC_COMM_STATE__M 0xFFFF -#define LC_COMM_MB__A 0x2800002 -#define LC_COMM_MB__W 16 -#define LC_COMM_MB__M 0xFFFF -#define LC_COMM_SERVICE0__A 0x2800003 -#define LC_COMM_SERVICE0__W 16 -#define LC_COMM_SERVICE0__M 0xFFFF -#define LC_COMM_SERVICE1__A 0x2800004 -#define LC_COMM_SERVICE1__W 16 -#define LC_COMM_SERVICE1__M 0xFFFF -#define LC_COMM_INT_STA__A 0x2800007 -#define LC_COMM_INT_STA__W 16 -#define LC_COMM_INT_STA__M 0xFFFF -#define LC_COMM_INT_MSK__A 0x2800008 -#define LC_COMM_INT_MSK__W 16 -#define LC_COMM_INT_MSK__M 0xFFFF - -#define LC_CT_REG_COMM_EXEC__A 0x2810000 -#define LC_CT_REG_COMM_EXEC__W 3 -#define LC_CT_REG_COMM_EXEC__M 0x7 -#define LC_CT_REG_COMM_EXEC_CTL__B 0 -#define LC_CT_REG_COMM_EXEC_CTL__W 3 -#define LC_CT_REG_COMM_EXEC_CTL__M 0x7 -#define LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define LC_CT_REG_COMM_STATE__A 0x2810001 -#define LC_CT_REG_COMM_STATE__W 10 -#define LC_CT_REG_COMM_STATE__M 0x3FF -#define LC_CT_REG_COMM_SERVICE0__A 0x2810003 -#define LC_CT_REG_COMM_SERVICE0__W 16 -#define LC_CT_REG_COMM_SERVICE0__M 0xFFFF -#define LC_CT_REG_COMM_SERVICE1__A 0x2810004 -#define LC_CT_REG_COMM_SERVICE1__W 16 -#define LC_CT_REG_COMM_SERVICE1__M 0xFFFF -#define LC_CT_REG_COMM_SERVICE1_LC__B 12 -#define LC_CT_REG_COMM_SERVICE1_LC__W 1 -#define LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 - -#define LC_CT_REG_COMM_INT_STA__A 0x2810007 -#define LC_CT_REG_COMM_INT_STA__W 1 -#define LC_CT_REG_COMM_INT_STA__M 0x1 -#define LC_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define LC_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define LC_CT_REG_COMM_INT_MSK__A 0x2810008 -#define LC_CT_REG_COMM_INT_MSK__W 1 -#define LC_CT_REG_COMM_INT_MSK__M 0x1 -#define LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define LC_CT_REG_CTL_STK__AX 0x2810010 -#define LC_CT_REG_CTL_STK__XSZ 4 -#define LC_CT_REG_CTL_STK__W 10 -#define LC_CT_REG_CTL_STK__M 0x3FF - -#define LC_CT_REG_CTL_BPT_IDX__A 0x281001F -#define LC_CT_REG_CTL_BPT_IDX__W 1 -#define LC_CT_REG_CTL_BPT_IDX__M 0x1 - -#define LC_CT_REG_CTL_BPT__A 0x2810020 -#define LC_CT_REG_CTL_BPT__W 10 -#define LC_CT_REG_CTL_BPT__M 0x3FF - -#define LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 -#define LC_RA_RAM_PROC_DELAY_IF__W 16 -#define LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF -#define LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 -#define LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 -#define LC_RA_RAM_PROC_DELAY_FS__W 16 -#define LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF -#define LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 -#define LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 -#define LC_RA_RAM_LOCK_TH_CRMM__W 16 -#define LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF -#define LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 -#define LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 -#define LC_RA_RAM_LOCK_TH_SRMM__W 16 -#define LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF -#define LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 -#define LC_RA_RAM_LOCK_COUNT__A 0x282000A -#define LC_RA_RAM_LOCK_COUNT__W 16 -#define LC_RA_RAM_LOCK_COUNT__M 0xFFFF -#define LC_RA_RAM_CPRTOFS_NOM__A 0x282000B -#define LC_RA_RAM_CPRTOFS_NOM__W 16 -#define LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF #define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C -#define LC_RA_RAM_IFINCR_NOM_L__W 16 -#define LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF -#define LC_RA_RAM_IFINCR_NOM_H__A 0x282000D -#define LC_RA_RAM_IFINCR_NOM_H__W 16 -#define LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF -#define LC_RA_RAM_FSINCR_NOM_L__A 0x282000E -#define LC_RA_RAM_FSINCR_NOM_L__W 16 -#define LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF -#define LC_RA_RAM_FSINCR_NOM_H__A 0x282000F -#define LC_RA_RAM_FSINCR_NOM_H__W 16 -#define LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF -#define LC_RA_RAM_MODE_2K__A 0x2820010 -#define LC_RA_RAM_MODE_2K__W 16 -#define LC_RA_RAM_MODE_2K__M 0xFFFF -#define LC_RA_RAM_MODE_GUARD__A 0x2820011 -#define LC_RA_RAM_MODE_GUARD__W 16 -#define LC_RA_RAM_MODE_GUARD__M 0xFFFF -#define LC_RA_RAM_MODE_GUARD_32 0x0 -#define LC_RA_RAM_MODE_GUARD_16 0x1 -#define LC_RA_RAM_MODE_GUARD_8 0x2 -#define LC_RA_RAM_MODE_GUARD_4 0x3 - -#define LC_RA_RAM_MODE_ADJUST__A 0x2820012 -#define LC_RA_RAM_MODE_ADJUST__W 16 -#define LC_RA_RAM_MODE_ADJUST__M 0xFFFF -#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 -#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 -#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 -#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 -#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 -#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 -#define LC_RA_RAM_MODE_ADJUST_SRMM__B 2 -#define LC_RA_RAM_MODE_ADJUST_SRMM__W 1 -#define LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 -#define LC_RA_RAM_MODE_ADJUST_PHASE__B 3 -#define LC_RA_RAM_MODE_ADJUST_PHASE__W 1 -#define LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 -#define LC_RA_RAM_MODE_ADJUST_DELAY__B 4 -#define LC_RA_RAM_MODE_ADJUST_DELAY__W 1 -#define LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 -#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 -#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 -#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 -#define LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 -#define LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 -#define LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 -#define LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 -#define LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 -#define LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 -#define LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 -#define LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 -#define LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 -#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 -#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 -#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 - #define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A -#define LC_RA_RAM_FILTER_SYM_SET__W 16 -#define LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF #define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 -#define LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B -#define LC_RA_RAM_FILTER_SYM_CUR__W 16 -#define LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF -#define LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 -#define LC_RA_RAM_MAX_ABS_EXP__A 0x282001D -#define LC_RA_RAM_MAX_ABS_EXP__W 16 -#define LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF -#define LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 -#define LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F -#define LC_RA_RAM_ACTUAL_CP_CRMM__W 16 -#define LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF -#define LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 -#define LC_RA_RAM_ACTUAL_CE_CRMM__W 16 -#define LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF -#define LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 -#define LC_RA_RAM_ACTUAL_CE_SRMM__W 16 -#define LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF -#define LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 -#define LC_RA_RAM_ACTUAL_PHASE__W 16 -#define LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF -#define LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 -#define LC_RA_RAM_ACTUAL_DELAY__W 16 -#define LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF -#define LC_RA_RAM_ADJUST_CRMM__A 0x2820024 -#define LC_RA_RAM_ADJUST_CRMM__W 16 -#define LC_RA_RAM_ADJUST_CRMM__M 0xFFFF -#define LC_RA_RAM_ADJUST_SRMM__A 0x2820025 -#define LC_RA_RAM_ADJUST_SRMM__W 16 -#define LC_RA_RAM_ADJUST_SRMM__M 0xFFFF -#define LC_RA_RAM_ADJUST_PHASE__A 0x2820026 -#define LC_RA_RAM_ADJUST_PHASE__W 16 -#define LC_RA_RAM_ADJUST_PHASE__M 0xFFFF -#define LC_RA_RAM_ADJUST_DELAY__A 0x2820027 -#define LC_RA_RAM_ADJUST_DELAY__W 16 -#define LC_RA_RAM_ADJUST_DELAY__M 0xFFFF - -#define LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 -#define LC_RA_RAM_PIPE_CP_PHASE_0__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 -#define LC_RA_RAM_PIPE_CP_PHASE_1__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A -#define LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B -#define LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C -#define LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D -#define LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 -#define LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF - -#define LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 -#define LC_RA_RAM_PIPE_CP_CRMM_0__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 -#define LC_RA_RAM_PIPE_CP_CRMM_1__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 -#define LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 -#define LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 -#define LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 -#define LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 -#define LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF - -#define LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 -#define LC_RA_RAM_PIPE_CP_SRMM_0__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 -#define LC_RA_RAM_PIPE_CP_SRMM_1__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A -#define LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B -#define LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C -#define LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF -#define LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D -#define LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 -#define LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF - #define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 -#define LC_RA_RAM_FILTER_CRMM_A__W 16 -#define LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF #define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 #define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 -#define LC_RA_RAM_FILTER_CRMM_B__W 16 -#define LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF #define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 -#define LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 -#define LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 -#define LC_RA_RAM_FILTER_CRMM_Z1__W 16 -#define LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF -#define LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 -#define LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 -#define LC_RA_RAM_FILTER_CRMM_Z2__W 16 -#define LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF -#define LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 -#define LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 -#define LC_RA_RAM_FILTER_CRMM_TMP__W 16 -#define LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF - #define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 -#define LC_RA_RAM_FILTER_SRMM_A__W 16 -#define LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF #define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 #define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 -#define LC_RA_RAM_FILTER_SRMM_B__W 16 -#define LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF #define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 -#define LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A -#define LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 -#define LC_RA_RAM_FILTER_SRMM_Z1__W 16 -#define LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF -#define LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C -#define LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 -#define LC_RA_RAM_FILTER_SRMM_Z2__W 16 -#define LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF -#define LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E -#define LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 -#define LC_RA_RAM_FILTER_SRMM_TMP__W 16 -#define LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF - -#define LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 -#define LC_RA_RAM_FILTER_PHASE_A__W 16 -#define LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF -#define LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 -#define LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 -#define LC_RA_RAM_FILTER_PHASE_B__W 16 -#define LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF -#define LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 -#define LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 -#define LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 -#define LC_RA_RAM_FILTER_PHASE_Z1__W 16 -#define LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF -#define LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 -#define LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 -#define LC_RA_RAM_FILTER_PHASE_Z2__W 16 -#define LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF -#define LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 -#define LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 -#define LC_RA_RAM_FILTER_PHASE_TMP__W 16 -#define LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF - -#define LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 -#define LC_RA_RAM_FILTER_DELAY_A__W 16 -#define LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF -#define LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 -#define LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 -#define LC_RA_RAM_FILTER_DELAY_B__W 16 -#define LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF -#define LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 -#define LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A -#define LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 -#define LC_RA_RAM_FILTER_DELAY_Z1__W 16 -#define LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF -#define LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C -#define LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 -#define LC_RA_RAM_FILTER_DELAY_Z2__W 16 -#define LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF -#define LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E -#define LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 -#define LC_RA_RAM_FILTER_DELAY_TMP__W 16 -#define LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF - -#define LC_IF_RAM_TRP_BPT0__AX 0x2830000 -#define LC_IF_RAM_TRP_BPT0__XSZ 2 -#define LC_IF_RAM_TRP_BPT0__W 12 -#define LC_IF_RAM_TRP_BPT0__M 0xFFF - -#define LC_IF_RAM_TRP_STKU__AX 0x2830002 -#define LC_IF_RAM_TRP_STKU__XSZ 2 -#define LC_IF_RAM_TRP_STKU__W 12 -#define LC_IF_RAM_TRP_STKU__M 0xFFF - -#define LC_IF_RAM_TRP_WARM__AX 0x2830006 -#define LC_IF_RAM_TRP_WARM__XSZ 2 -#define LC_IF_RAM_TRP_WARM__W 12 -#define LC_IF_RAM_TRP_WARM__M 0xFFF - -#define B_HI_SID 0x10 - #define B_HI_COMM_EXEC__A 0x400000 -#define B_HI_COMM_EXEC__W 3 -#define B_HI_COMM_EXEC__M 0x7 -#define B_HI_COMM_EXEC_CTL__B 0 -#define B_HI_COMM_EXEC_CTL__W 3 -#define B_HI_COMM_EXEC_CTL__M 0x7 -#define B_HI_COMM_EXEC_CTL_STOP 0x0 -#define B_HI_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_HI_COMM_EXEC_CTL_HOLD 0x2 -#define B_HI_COMM_EXEC_CTL_STEP 0x3 -#define B_HI_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_HI_COMM_STATE__A 0x400001 -#define B_HI_COMM_STATE__W 16 -#define B_HI_COMM_STATE__M 0xFFFF #define B_HI_COMM_MB__A 0x400002 -#define B_HI_COMM_MB__W 16 -#define B_HI_COMM_MB__M 0xFFFF -#define B_HI_COMM_SERVICE0__A 0x400003 -#define B_HI_COMM_SERVICE0__W 16 -#define B_HI_COMM_SERVICE0__M 0xFFFF -#define B_HI_COMM_SERVICE1__A 0x400004 -#define B_HI_COMM_SERVICE1__W 16 -#define B_HI_COMM_SERVICE1__M 0xFFFF -#define B_HI_COMM_INT_STA__A 0x400007 -#define B_HI_COMM_INT_STA__W 16 -#define B_HI_COMM_INT_STA__M 0xFFFF -#define B_HI_COMM_INT_MSK__A 0x400008 -#define B_HI_COMM_INT_MSK__W 16 -#define B_HI_COMM_INT_MSK__M 0xFFFF - -#define B_HI_CT_REG_COMM_EXEC__A 0x410000 -#define B_HI_CT_REG_COMM_EXEC__W 3 -#define B_HI_CT_REG_COMM_EXEC__M 0x7 -#define B_HI_CT_REG_COMM_EXEC_CTL__B 0 -#define B_HI_CT_REG_COMM_EXEC_CTL__W 3 -#define B_HI_CT_REG_COMM_EXEC_CTL__M 0x7 -#define B_HI_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_HI_CT_REG_COMM_EXEC_CTL_STEP 0x3 - #define B_HI_CT_REG_COMM_STATE__A 0x410001 -#define B_HI_CT_REG_COMM_STATE__W 10 -#define B_HI_CT_REG_COMM_STATE__M 0x3FF -#define B_HI_CT_REG_COMM_SERVICE0__A 0x410003 -#define B_HI_CT_REG_COMM_SERVICE0__W 16 -#define B_HI_CT_REG_COMM_SERVICE0__M 0xFFFF -#define B_HI_CT_REG_COMM_SERVICE1__A 0x410004 -#define B_HI_CT_REG_COMM_SERVICE1__W 16 -#define B_HI_CT_REG_COMM_SERVICE1__M 0xFFFF -#define B_HI_CT_REG_COMM_SERVICE1_HI__B 0 -#define B_HI_CT_REG_COMM_SERVICE1_HI__W 1 -#define B_HI_CT_REG_COMM_SERVICE1_HI__M 0x1 - -#define B_HI_CT_REG_COMM_INT_STA__A 0x410007 -#define B_HI_CT_REG_COMM_INT_STA__W 1 -#define B_HI_CT_REG_COMM_INT_STA__M 0x1 -#define B_HI_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define B_HI_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define B_HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define B_HI_CT_REG_COMM_INT_MSK__A 0x410008 -#define B_HI_CT_REG_COMM_INT_MSK__W 1 -#define B_HI_CT_REG_COMM_INT_MSK__M 0x1 -#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define B_HI_CT_REG_CTL_STK__AX 0x410010 -#define B_HI_CT_REG_CTL_STK__XSZ 4 -#define B_HI_CT_REG_CTL_STK__W 10 -#define B_HI_CT_REG_CTL_STK__M 0x3FF - -#define B_HI_CT_REG_CTL_BPT_IDX__A 0x41001F -#define B_HI_CT_REG_CTL_BPT_IDX__W 1 -#define B_HI_CT_REG_CTL_BPT_IDX__M 0x1 - -#define B_HI_CT_REG_CTL_BPT__A 0x410020 -#define B_HI_CT_REG_CTL_BPT__W 10 -#define B_HI_CT_REG_CTL_BPT__M 0x3FF - -#define B_HI_RA_RAM_SLV0_FLG_SMM__A 0x420010 -#define B_HI_RA_RAM_SLV0_FLG_SMM__W 1 -#define B_HI_RA_RAM_SLV0_FLG_SMM__M 0x1 -#define B_HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0 -#define B_HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1 - -#define B_HI_RA_RAM_SLV0_DEV_ID__A 0x420011 -#define B_HI_RA_RAM_SLV0_DEV_ID__W 7 -#define B_HI_RA_RAM_SLV0_DEV_ID__M 0x7F - -#define B_HI_RA_RAM_SLV0_FLG_CRC__A 0x420012 -#define B_HI_RA_RAM_SLV0_FLG_CRC__W 1 -#define B_HI_RA_RAM_SLV0_FLG_CRC__M 0x1 -#define B_HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0 -#define B_HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1 - -#define B_HI_RA_RAM_SLV0_FLG_ACC__A 0x420013 -#define B_HI_RA_RAM_SLV0_FLG_ACC__W 3 -#define B_HI_RA_RAM_SLV0_FLG_ACC__M 0x7 -#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0 -#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2 -#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3 -#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0 -#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3 -#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2 -#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1 -#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4 -#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0 -#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4 - -#define B_HI_RA_RAM_SLV0_STATE__A 0x420014 -#define B_HI_RA_RAM_SLV0_STATE__W 1 -#define B_HI_RA_RAM_SLV0_STATE__M 0x1 -#define B_HI_RA_RAM_SLV0_STATE_ADDRESS 0x0 -#define B_HI_RA_RAM_SLV0_STATE_DATA 0x1 - -#define B_HI_RA_RAM_SLV0_BLK_BNK__A 0x420015 -#define B_HI_RA_RAM_SLV0_BLK_BNK__W 12 -#define B_HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF -#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0 -#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6 -#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F -#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6 -#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6 -#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0 - -#define B_HI_RA_RAM_SLV0_ADDR__A 0x420016 -#define B_HI_RA_RAM_SLV0_ADDR__W 16 -#define B_HI_RA_RAM_SLV0_ADDR__M 0xFFFF - -#define B_HI_RA_RAM_SLV0_CRC__A 0x420017 -#define B_HI_RA_RAM_SLV0_CRC__W 16 -#define B_HI_RA_RAM_SLV0_CRC__M 0xFFFF - -#define B_HI_RA_RAM_SLV0_READBACK__A 0x420018 -#define B_HI_RA_RAM_SLV0_READBACK__W 16 -#define B_HI_RA_RAM_SLV0_READBACK__M 0xFFFF - -#define B_HI_RA_RAM_SLV1_FLG_SMM__A 0x420020 -#define B_HI_RA_RAM_SLV1_FLG_SMM__W 1 -#define B_HI_RA_RAM_SLV1_FLG_SMM__M 0x1 -#define B_HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0 -#define B_HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1 - -#define B_HI_RA_RAM_SLV1_DEV_ID__A 0x420021 -#define B_HI_RA_RAM_SLV1_DEV_ID__W 7 -#define B_HI_RA_RAM_SLV1_DEV_ID__M 0x7F - -#define B_HI_RA_RAM_SLV1_FLG_CRC__A 0x420022 -#define B_HI_RA_RAM_SLV1_FLG_CRC__W 1 -#define B_HI_RA_RAM_SLV1_FLG_CRC__M 0x1 -#define B_HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0 -#define B_HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1 - -#define B_HI_RA_RAM_SLV1_FLG_ACC__A 0x420023 -#define B_HI_RA_RAM_SLV1_FLG_ACC__W 3 -#define B_HI_RA_RAM_SLV1_FLG_ACC__M 0x7 -#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0 -#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2 -#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3 -#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0 -#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3 -#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2 -#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1 -#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4 -#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0 -#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4 - -#define B_HI_RA_RAM_SLV1_STATE__A 0x420024 -#define B_HI_RA_RAM_SLV1_STATE__W 1 -#define B_HI_RA_RAM_SLV1_STATE__M 0x1 -#define B_HI_RA_RAM_SLV1_STATE_ADDRESS 0x0 -#define B_HI_RA_RAM_SLV1_STATE_DATA 0x1 - -#define B_HI_RA_RAM_SLV1_BLK_BNK__A 0x420025 -#define B_HI_RA_RAM_SLV1_BLK_BNK__W 12 -#define B_HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF -#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0 -#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6 -#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F -#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6 -#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6 -#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0 - -#define B_HI_RA_RAM_SLV1_ADDR__A 0x420026 -#define B_HI_RA_RAM_SLV1_ADDR__W 16 -#define B_HI_RA_RAM_SLV1_ADDR__M 0xFFFF - -#define B_HI_RA_RAM_SLV1_CRC__A 0x420027 -#define B_HI_RA_RAM_SLV1_CRC__W 16 -#define B_HI_RA_RAM_SLV1_CRC__M 0xFFFF - -#define B_HI_RA_RAM_SLV1_READBACK__A 0x420028 -#define B_HI_RA_RAM_SLV1_READBACK__W 16 -#define B_HI_RA_RAM_SLV1_READBACK__M 0xFFFF - -#define B_HI_RA_RAM_SRV_SEM__A 0x420030 -#define B_HI_RA_RAM_SRV_SEM__W 1 -#define B_HI_RA_RAM_SRV_SEM__M 0x1 -#define B_HI_RA_RAM_SRV_SEM_FREE 0x0 -#define B_HI_RA_RAM_SRV_SEM_CLAIMED 0x1 - #define B_HI_RA_RAM_SRV_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_RES__W 3 -#define B_HI_RA_RAM_SRV_RES__M 0x7 -#define B_HI_RA_RAM_SRV_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1 -#define B_HI_RA_RAM_SRV_RES_STOP_FOUND 0x2 -#define B_HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3 -#define B_HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4 - #define B_HI_RA_RAM_SRV_CMD__A 0x420032 -#define B_HI_RA_RAM_SRV_CMD__W 3 -#define B_HI_RA_RAM_SRV_CMD__M 0x7 -#define B_HI_RA_RAM_SRV_CMD_NULL 0x0 -#define B_HI_RA_RAM_SRV_CMD_UIO 0x1 #define B_HI_RA_RAM_SRV_CMD_RESET 0x2 #define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3 -#define B_HI_RA_RAM_SRV_CMD_COPY 0x4 -#define B_HI_RA_RAM_SRV_CMD_TRANSMIT 0x5 #define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6 - -#define B_HI_RA_RAM_SRV_PAR__AX 0x420033 -#define B_HI_RA_RAM_SRV_PAR__XSZ 5 -#define B_HI_RA_RAM_SRV_PAR__W 16 -#define B_HI_RA_RAM_SRV_PAR__M 0xFFFF - -#define B_HI_RA_RAM_SRV_NOP_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_NOP_RES__W 3 -#define B_HI_RA_RAM_SRV_NOP_RES__M 0x7 -#define B_HI_RA_RAM_SRV_NOP_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4 - -#define B_HI_RA_RAM_SRV_UIO_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_UIO_RES__W 3 -#define B_HI_RA_RAM_SRV_UIO_RES__M 0x7 -#define B_HI_RA_RAM_SRV_UIO_RES_LO 0x0 -#define B_HI_RA_RAM_SRV_UIO_RES_HI 0x1 - -#define B_HI_RA_RAM_SRV_UIO_KEY__A 0x420033 -#define B_HI_RA_RAM_SRV_UIO_KEY__W 16 -#define B_HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF -#define B_HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973 - -#define B_HI_RA_RAM_SRV_UIO_SEL__A 0x420034 -#define B_HI_RA_RAM_SRV_UIO_SEL__W 2 -#define B_HI_RA_RAM_SRV_UIO_SEL__M 0x3 -#define B_HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0 -#define B_HI_RA_RAM_SRV_UIO_SEL_UIO 0x1 - -#define B_HI_RA_RAM_SRV_UIO_SET__A 0x420035 -#define B_HI_RA_RAM_SRV_UIO_SET__W 2 -#define B_HI_RA_RAM_SRV_UIO_SET__M 0x3 -#define B_HI_RA_RAM_SRV_UIO_SET_OUT__B 0 -#define B_HI_RA_RAM_SRV_UIO_SET_OUT__W 1 -#define B_HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1 -#define B_HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0 -#define B_HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1 -#define B_HI_RA_RAM_SRV_UIO_SET_DIR__B 1 -#define B_HI_RA_RAM_SRV_UIO_SET_DIR__W 1 -#define B_HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2 -#define B_HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0 -#define B_HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2 - -#define B_HI_RA_RAM_SRV_RST_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_RST_RES__W 1 -#define B_HI_RA_RAM_SRV_RST_RES__M 0x1 -#define B_HI_RA_RAM_SRV_RST_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_RST_RES_ERROR 0x1 - #define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033 -#define B_HI_RA_RAM_SRV_RST_KEY__W 16 -#define B_HI_RA_RAM_SRV_RST_KEY__M 0xFFFF #define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 - -#define B_HI_RA_RAM_SRV_CFG_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_CFG_RES__W 1 -#define B_HI_RA_RAM_SRV_CFG_RES__M 0x1 -#define B_HI_RA_RAM_SRV_CFG_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_CFG_RES_ERROR 0x1 - #define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033 -#define B_HI_RA_RAM_SRV_CFG_KEY__W 16 -#define B_HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF -#define B_HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973 - #define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034 -#define B_HI_RA_RAM_SRV_CFG_DIV__W 5 -#define B_HI_RA_RAM_SRV_CFG_DIV__M 0x1F - #define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035 -#define B_HI_RA_RAM_SRV_CFG_BDL__W 6 -#define B_HI_RA_RAM_SRV_CFG_BDL__M 0x3F - #define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036 -#define B_HI_RA_RAM_SRV_CFG_WUP__W 8 -#define B_HI_RA_RAM_SRV_CFG_WUP__M 0xFF - #define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037 -#define B_HI_RA_RAM_SRV_CFG_ACT__W 4 -#define B_HI_RA_RAM_SRV_CFG_ACT__M 0xF -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0 #define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0 -#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2 -#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__B 2 -#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__W 1 #define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 #define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 -#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__B 3 -#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__W 1 -#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8 -#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0 #define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 - -#define B_HI_RA_RAM_SRV_CPY_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_CPY_RES__W 1 -#define B_HI_RA_RAM_SRV_CPY_RES__M 0x1 -#define B_HI_RA_RAM_SRV_CPY_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_CPY_RES_ERROR 0x1 - -#define B_HI_RA_RAM_SRV_CPY_SBB__A 0x420033 -#define B_HI_RA_RAM_SRV_CPY_SBB__W 12 -#define B_HI_RA_RAM_SRV_CPY_SBB__M 0xFFF -#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__B 0 -#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__W 6 -#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F -#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__B 6 -#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__W 6 -#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0 - -#define B_HI_RA_RAM_SRV_CPY_SAD__A 0x420034 -#define B_HI_RA_RAM_SRV_CPY_SAD__W 16 -#define B_HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF - -#define B_HI_RA_RAM_SRV_CPY_LEN__A 0x420035 -#define B_HI_RA_RAM_SRV_CPY_LEN__W 16 -#define B_HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF - -#define B_HI_RA_RAM_SRV_CPY_DBB__A 0x420033 -#define B_HI_RA_RAM_SRV_CPY_DBB__W 12 -#define B_HI_RA_RAM_SRV_CPY_DBB__M 0xFFF -#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__B 0 -#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__W 6 -#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F -#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__B 6 -#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__W 6 -#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0 - -#define B_HI_RA_RAM_SRV_CPY_DAD__A 0x420034 -#define B_HI_RA_RAM_SRV_CPY_DAD__W 16 -#define B_HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF - -#define B_HI_RA_RAM_SRV_TRM_RES__A 0x420031 -#define B_HI_RA_RAM_SRV_TRM_RES__W 2 -#define B_HI_RA_RAM_SRV_TRM_RES__M 0x3 -#define B_HI_RA_RAM_SRV_TRM_RES_OK 0x0 -#define B_HI_RA_RAM_SRV_TRM_RES_ERROR 0x1 -#define B_HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3 - -#define B_HI_RA_RAM_SRV_TRM_MST__A 0x420033 -#define B_HI_RA_RAM_SRV_TRM_MST__W 12 -#define B_HI_RA_RAM_SRV_TRM_MST__M 0xFFF - -#define B_HI_RA_RAM_SRV_TRM_SEQ__A 0x420034 -#define B_HI_RA_RAM_SRV_TRM_SEQ__W 7 -#define B_HI_RA_RAM_SRV_TRM_SEQ__M 0x7F - -#define B_HI_RA_RAM_SRV_TRM_TRM__A 0x420035 -#define B_HI_RA_RAM_SRV_TRM_TRM__W 15 -#define B_HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF -#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__B 0 -#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__W 8 -#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF - -#define B_HI_RA_RAM_SRV_TRM_DBB__A 0x420033 -#define B_HI_RA_RAM_SRV_TRM_DBB__W 12 -#define B_HI_RA_RAM_SRV_TRM_DBB__M 0xFFF -#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__B 0 -#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__W 6 -#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F -#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__B 6 -#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__W 6 -#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0 - -#define B_HI_RA_RAM_SRV_TRM_DAD__A 0x420034 -#define B_HI_RA_RAM_SRV_TRM_DAD__W 16 -#define B_HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF - #define B_HI_RA_RAM_USR_BEGIN__A 0x420040 -#define B_HI_RA_RAM_USR_BEGIN__W 16 -#define B_HI_RA_RAM_USR_BEGIN__M 0xFFFF - -#define B_HI_RA_RAM_USR_END__A 0x42007F -#define B_HI_RA_RAM_USR_END__W 16 -#define B_HI_RA_RAM_USR_END__M 0xFFFF - #define B_HI_IF_RAM_TRP_BPT0__AX 0x430000 -#define B_HI_IF_RAM_TRP_BPT0__XSZ 2 -#define B_HI_IF_RAM_TRP_BPT0__W 12 -#define B_HI_IF_RAM_TRP_BPT0__M 0xFFF - -#define B_HI_IF_RAM_TRP_STKU__AX 0x430002 -#define B_HI_IF_RAM_TRP_STKU__XSZ 2 -#define B_HI_IF_RAM_TRP_STKU__W 12 -#define B_HI_IF_RAM_TRP_STKU__M 0xFFF - #define B_HI_IF_RAM_USR_BEGIN__A 0x430200 -#define B_HI_IF_RAM_USR_BEGIN__W 12 -#define B_HI_IF_RAM_USR_BEGIN__M 0xFFF - -#define B_HI_IF_RAM_USR_END__A 0x4303FF -#define B_HI_IF_RAM_USR_END__W 12 -#define B_HI_IF_RAM_USR_END__M 0xFFF - -#define B_SC_SID 0x11 - #define B_SC_COMM_EXEC__A 0x800000 -#define B_SC_COMM_EXEC__W 3 -#define B_SC_COMM_EXEC__M 0x7 -#define B_SC_COMM_EXEC_CTL__B 0 -#define B_SC_COMM_EXEC_CTL__W 3 -#define B_SC_COMM_EXEC_CTL__M 0x7 #define B_SC_COMM_EXEC_CTL_STOP 0x0 -#define B_SC_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_SC_COMM_EXEC_CTL_HOLD 0x2 -#define B_SC_COMM_EXEC_CTL_STEP 0x3 -#define B_SC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - #define B_SC_COMM_STATE__A 0x800001 -#define B_SC_COMM_STATE__W 16 -#define B_SC_COMM_STATE__M 0xFFFF -#define B_SC_COMM_MB__A 0x800002 -#define B_SC_COMM_MB__W 16 -#define B_SC_COMM_MB__M 0xFFFF -#define B_SC_COMM_SERVICE0__A 0x800003 -#define B_SC_COMM_SERVICE0__W 16 -#define B_SC_COMM_SERVICE0__M 0xFFFF -#define B_SC_COMM_SERVICE1__A 0x800004 -#define B_SC_COMM_SERVICE1__W 16 -#define B_SC_COMM_SERVICE1__M 0xFFFF -#define B_SC_COMM_INT_STA__A 0x800007 -#define B_SC_COMM_INT_STA__W 16 -#define B_SC_COMM_INT_STA__M 0xFFFF -#define B_SC_COMM_INT_MSK__A 0x800008 -#define B_SC_COMM_INT_MSK__W 16 -#define B_SC_COMM_INT_MSK__M 0xFFFF - -#define B_SC_CT_REG_COMM_EXEC__A 0x810000 -#define B_SC_CT_REG_COMM_EXEC__W 3 -#define B_SC_CT_REG_COMM_EXEC__M 0x7 -#define B_SC_CT_REG_COMM_EXEC_CTL__B 0 -#define B_SC_CT_REG_COMM_EXEC_CTL__W 3 -#define B_SC_CT_REG_COMM_EXEC_CTL__M 0x7 -#define B_SC_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_SC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_SC_CT_REG_COMM_STATE__A 0x810001 -#define B_SC_CT_REG_COMM_STATE__W 10 -#define B_SC_CT_REG_COMM_STATE__M 0x3FF -#define B_SC_CT_REG_COMM_SERVICE0__A 0x810003 -#define B_SC_CT_REG_COMM_SERVICE0__W 16 -#define B_SC_CT_REG_COMM_SERVICE0__M 0xFFFF -#define B_SC_CT_REG_COMM_SERVICE1__A 0x810004 -#define B_SC_CT_REG_COMM_SERVICE1__W 16 -#define B_SC_CT_REG_COMM_SERVICE1__M 0xFFFF -#define B_SC_CT_REG_COMM_SERVICE1_SC__B 1 -#define B_SC_CT_REG_COMM_SERVICE1_SC__W 1 -#define B_SC_CT_REG_COMM_SERVICE1_SC__M 0x2 - -#define B_SC_CT_REG_COMM_INT_STA__A 0x810007 -#define B_SC_CT_REG_COMM_INT_STA__W 1 -#define B_SC_CT_REG_COMM_INT_STA__M 0x1 -#define B_SC_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define B_SC_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define B_SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define B_SC_CT_REG_COMM_INT_MSK__A 0x810008 -#define B_SC_CT_REG_COMM_INT_MSK__W 1 -#define B_SC_CT_REG_COMM_INT_MSK__M 0x1 -#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define B_SC_CT_REG_CTL_STK__AX 0x810010 -#define B_SC_CT_REG_CTL_STK__XSZ 4 -#define B_SC_CT_REG_CTL_STK__W 10 -#define B_SC_CT_REG_CTL_STK__M 0x3FF - -#define B_SC_CT_REG_CTL_BPT_IDX__A 0x81001F -#define B_SC_CT_REG_CTL_BPT_IDX__W 1 -#define B_SC_CT_REG_CTL_BPT_IDX__M 0x1 - -#define B_SC_CT_REG_CTL_BPT__A 0x810020 -#define B_SC_CT_REG_CTL_BPT__W 10 -#define B_SC_CT_REG_CTL_BPT__M 0x3FF - #define B_SC_RA_RAM_PARAM0__A 0x820040 -#define B_SC_RA_RAM_PARAM0__W 16 -#define B_SC_RA_RAM_PARAM0__M 0xFFFF #define B_SC_RA_RAM_PARAM1__A 0x820041 -#define B_SC_RA_RAM_PARAM1__W 16 -#define B_SC_RA_RAM_PARAM1__M 0xFFFF #define B_SC_RA_RAM_CMD_ADDR__A 0x820042 -#define B_SC_RA_RAM_CMD_ADDR__W 16 -#define B_SC_RA_RAM_CMD_ADDR__M 0xFFFF #define B_SC_RA_RAM_CMD__A 0x820043 -#define B_SC_RA_RAM_CMD__W 16 -#define B_SC_RA_RAM_CMD__M 0xFFFF -#define B_SC_RA_RAM_CMD_NULL 0x0 #define B_SC_RA_RAM_CMD_PROC_START 0x1 -#define B_SC_RA_RAM_CMD_PROC_TRIGGER 0x2 #define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 -#define B_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4 #define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5 -#define B_SC_RA_RAM_CMD_USER_IO 0x6 -#define B_SC_RA_RAM_CMD_SET_TIMER 0x7 -#define B_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8 -#define B_SC_RA_RAM_CMD_MAX 0x9 -#define B_SC_RA_RAM_CMDBLOCK__C 0x4 - -#define B_SC_RA_RAM_PROC_ACTIVATE__A 0x820044 -#define B_SC_RA_RAM_PROC_ACTIVATE__W 16 -#define B_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF -#define B_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF -#define B_SC_RA_RAM_PROC_TERMINATED__A 0x820045 -#define B_SC_RA_RAM_PROC_TERMINATED__W 16 -#define B_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF -#define B_SC_RA_RAM_SW_EVENT__A 0x820046 -#define B_SC_RA_RAM_SW_EVENT__W 14 -#define B_SC_RA_RAM_SW_EVENT__M 0x3FFF -#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0 -#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1 #define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 -#define B_SC_RA_RAM_SW_EVENT_RUN__B 1 -#define B_SC_RA_RAM_SW_EVENT_RUN__W 1 -#define B_SC_RA_RAM_SW_EVENT_RUN__M 0x2 -#define B_SC_RA_RAM_SW_EVENT_TERMINATE__B 2 -#define B_SC_RA_RAM_SW_EVENT_TERMINATE__W 1 -#define B_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4 -#define B_SC_RA_RAM_SW_EVENT_FT_START__B 3 -#define B_SC_RA_RAM_SW_EVENT_FT_START__W 1 -#define B_SC_RA_RAM_SW_EVENT_FT_START__M 0x8 -#define B_SC_RA_RAM_SW_EVENT_FI_START__B 4 -#define B_SC_RA_RAM_SW_EVENT_FI_START__W 1 -#define B_SC_RA_RAM_SW_EVENT_FI_START__M 0x10 -#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5 -#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1 -#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20 -#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6 -#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1 -#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40 -#define B_SC_RA_RAM_SW_EVENT_CE_IR__B 7 -#define B_SC_RA_RAM_SW_EVENT_CE_IR__W 1 -#define B_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80 -#define B_SC_RA_RAM_SW_EVENT_FE_FD__B 8 -#define B_SC_RA_RAM_SW_EVENT_FE_FD__W 1 -#define B_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100 -#define B_SC_RA_RAM_SW_EVENT_FE_CF__B 9 -#define B_SC_RA_RAM_SW_EVENT_FE_CF__W 1 -#define B_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200 -#define B_SC_RA_RAM_SW_EVENT_NF_READY__B 12 -#define B_SC_RA_RAM_SW_EVENT_NF_READY__W 1 -#define B_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000 - -#define B_SC_RA_RAM_LOCKTRACK__A 0x820047 -#define B_SC_RA_RAM_LOCKTRACK__W 16 -#define B_SC_RA_RAM_LOCKTRACK__M 0xFFFF -#define B_SC_RA_RAM_LOCKTRACK_NULL 0x0 #define B_SC_RA_RAM_LOCKTRACK_MIN 0x1 -#define B_SC_RA_RAM_LOCKTRACK_RESET 0x1 -#define B_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2 -#define B_SC_RA_RAM_LOCKTRACK_P_DETECT 0x3 -#define B_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4 -#define B_SC_RA_RAM_LOCKTRACK_LC 0x5 -#define B_SC_RA_RAM_LOCKTRACK_P_ECHO 0x6 -#define B_SC_RA_RAM_LOCKTRACK_NE_INIT 0x7 -#define B_SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x8 -#define B_SC_RA_RAM_LOCKTRACK_TRACK 0x9 -#define B_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xA -#define B_SC_RA_RAM_LOCKTRACK_MAX 0xB - -#define B_SC_RA_RAM_OP_PARAM__A 0x820048 -#define B_SC_RA_RAM_OP_PARAM__W 13 -#define B_SC_RA_RAM_OP_PARAM__M 0x1FFF -#define B_SC_RA_RAM_OP_PARAM_MODE__B 0 -#define B_SC_RA_RAM_OP_PARAM_MODE__W 2 -#define B_SC_RA_RAM_OP_PARAM_MODE__M 0x3 #define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0 #define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1 -#define B_SC_RA_RAM_OP_PARAM_GUARD__B 2 -#define B_SC_RA_RAM_OP_PARAM_GUARD__W 2 -#define B_SC_RA_RAM_OP_PARAM_GUARD__M 0xC #define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0 #define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4 #define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8 #define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC -#define B_SC_RA_RAM_OP_PARAM_CONST__B 4 -#define B_SC_RA_RAM_OP_PARAM_CONST__W 2 -#define B_SC_RA_RAM_OP_PARAM_CONST__M 0x30 #define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 #define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 #define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 -#define B_SC_RA_RAM_OP_PARAM_HIER__B 6 -#define B_SC_RA_RAM_OP_PARAM_HIER__W 3 -#define B_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0 #define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0 #define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40 #define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80 #define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 -#define B_SC_RA_RAM_OP_PARAM_RATE__B 9 -#define B_SC_RA_RAM_OP_PARAM_RATE__W 3 -#define B_SC_RA_RAM_OP_PARAM_RATE__M 0xE00 #define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 #define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 #define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 #define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 #define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 -#define B_SC_RA_RAM_OP_PARAM_PRIO__B 12 -#define B_SC_RA_RAM_OP_PARAM_PRIO__W 1 -#define B_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000 #define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 #define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 - -#define B_SC_RA_RAM_OP_AUTO__A 0x820049 -#define B_SC_RA_RAM_OP_AUTO__W 6 -#define B_SC_RA_RAM_OP_AUTO__M 0x3F -#define B_SC_RA_RAM_OP_AUTO__PRE 0x1F -#define B_SC_RA_RAM_OP_AUTO_MODE__B 0 -#define B_SC_RA_RAM_OP_AUTO_MODE__W 1 #define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1 -#define B_SC_RA_RAM_OP_AUTO_GUARD__B 1 -#define B_SC_RA_RAM_OP_AUTO_GUARD__W 1 #define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2 -#define B_SC_RA_RAM_OP_AUTO_CONST__B 2 -#define B_SC_RA_RAM_OP_AUTO_CONST__W 1 #define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4 -#define B_SC_RA_RAM_OP_AUTO_HIER__B 3 -#define B_SC_RA_RAM_OP_AUTO_HIER__W 1 #define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8 -#define B_SC_RA_RAM_OP_AUTO_RATE__B 4 -#define B_SC_RA_RAM_OP_AUTO_RATE__W 1 #define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10 -#define B_SC_RA_RAM_OP_AUTO_PRIO__B 5 -#define B_SC_RA_RAM_OP_AUTO_PRIO__W 1 -#define B_SC_RA_RAM_OP_AUTO_PRIO__M 0x20 - -#define B_SC_RA_RAM_PILOT_STATUS__A 0x82004A -#define B_SC_RA_RAM_PILOT_STATUS__W 16 -#define B_SC_RA_RAM_PILOT_STATUS__M 0xFFFF -#define B_SC_RA_RAM_PILOT_STATUS_OK 0x0 -#define B_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1 -#define B_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2 -#define B_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3 - #define B_SC_RA_RAM_LOCK__A 0x82004B -#define B_SC_RA_RAM_LOCK__W 4 -#define B_SC_RA_RAM_LOCK__M 0xF -#define B_SC_RA_RAM_LOCK_DEMOD__B 0 -#define B_SC_RA_RAM_LOCK_DEMOD__W 1 #define B_SC_RA_RAM_LOCK_DEMOD__M 0x1 -#define B_SC_RA_RAM_LOCK_FEC__B 1 -#define B_SC_RA_RAM_LOCK_FEC__W 1 #define B_SC_RA_RAM_LOCK_FEC__M 0x2 -#define B_SC_RA_RAM_LOCK_MPEG__B 2 -#define B_SC_RA_RAM_LOCK_MPEG__W 1 #define B_SC_RA_RAM_LOCK_MPEG__M 0x4 -#define B_SC_RA_RAM_LOCK_NODVBT__B 3 -#define B_SC_RA_RAM_LOCK_NODVBT__W 1 -#define B_SC_RA_RAM_LOCK_NODVBT__M 0x8 - #define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C -#define B_SC_RA_RAM_BE_OPT_ENA__W 5 -#define B_SC_RA_RAM_BE_OPT_ENA__M 0x1F -#define B_SC_RA_RAM_BE_OPT_ENA__PRE 0x1E -#define B_SC_RA_RAM_BE_OPT_ENA_MOTION 0x0 #define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 -#define B_SC_RA_RAM_BE_OPT_ENA_CSI_OPT 0x2 -#define B_SC_RA_RAM_BE_OPT_ENA_CAL_OPT 0x3 -#define B_SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4 -#define B_SC_RA_RAM_BE_OPT_ENA_MAX 0x5 - #define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D -#define B_SC_RA_RAM_BE_OPT_DELAY__W 16 -#define B_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF -#define B_SC_RA_RAM_BE_OPT_DELAY__PRE 0x200 -#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E -#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16 -#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF -#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400 -#define B_SC_RA_RAM_ECHO_THRES__A 0x82004F -#define B_SC_RA_RAM_ECHO_THRES__W 16 -#define B_SC_RA_RAM_ECHO_THRES__M 0xFFFF -#define B_SC_RA_RAM_ECHO_THRES__PRE 0x2A #define B_SC_RA_RAM_CONFIG__A 0x820050 -#define B_SC_RA_RAM_CONFIG__W 16 -#define B_SC_RA_RAM_CONFIG__M 0xFFFF -#define B_SC_RA_RAM_CONFIG__PRE 0x14 -#define B_SC_RA_RAM_CONFIG_ID__B 0 -#define B_SC_RA_RAM_CONFIG_ID__W 1 -#define B_SC_RA_RAM_CONFIG_ID__M 0x1 -#define B_SC_RA_RAM_CONFIG_ID_PRO 0x0 -#define B_SC_RA_RAM_CONFIG_ID_CONSUMER 0x1 -#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1 -#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1 -#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2 -#define B_SC_RA_RAM_CONFIG_FR_ENABLE__B 2 -#define B_SC_RA_RAM_CONFIG_FR_ENABLE__W 1 #define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 -#define B_SC_RA_RAM_CONFIG_MIXMODE__B 3 -#define B_SC_RA_RAM_CONFIG_MIXMODE__W 1 -#define B_SC_RA_RAM_CONFIG_MIXMODE__M 0x8 -#define B_SC_RA_RAM_CONFIG_FREQSCAN__B 4 -#define B_SC_RA_RAM_CONFIG_FREQSCAN__W 1 #define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 -#define B_SC_RA_RAM_CONFIG_SLAVE__B 5 -#define B_SC_RA_RAM_CONFIG_SLAVE__W 1 #define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20 -#define B_SC_RA_RAM_CONFIG_FAR_OFF__B 6 -#define B_SC_RA_RAM_CONFIG_FAR_OFF__W 1 -#define B_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40 -#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7 -#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1 -#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80 -#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8 -#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1 -#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100 -#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9 -#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1 #define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200 -#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10 -#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1 #define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400 -#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15 -#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1 -#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000 - -#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x820054 -#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16 -#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF -#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0 - -#define B_SC_RA_RAM_FR_2K_MAN_SH__A 0x820055 -#define B_SC_RA_RAM_FR_2K_MAN_SH__W 16 -#define B_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7 -#define B_SC_RA_RAM_FR_2K_TAP_SH__A 0x820056 -#define B_SC_RA_RAM_FR_2K_TAP_SH__W 16 -#define B_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3 -#define B_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x820057 -#define B_SC_RA_RAM_FR_2K_LEAK_UPD__W 16 -#define B_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF -#define B_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2 -#define B_SC_RA_RAM_FR_2K_LEAK_SH__A 0x820058 -#define B_SC_RA_RAM_FR_2K_LEAK_SH__W 16 -#define B_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2 - -#define B_SC_RA_RAM_FR_8K_MAN_SH__A 0x820059 -#define B_SC_RA_RAM_FR_8K_MAN_SH__W 16 -#define B_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7 -#define B_SC_RA_RAM_FR_8K_TAP_SH__A 0x82005A -#define B_SC_RA_RAM_FR_8K_TAP_SH__W 16 -#define B_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x4 -#define B_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x82005B -#define B_SC_RA_RAM_FR_8K_LEAK_UPD__W 16 -#define B_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF -#define B_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2 -#define B_SC_RA_RAM_FR_8K_LEAK_SH__A 0x82005C -#define B_SC_RA_RAM_FR_8K_LEAK_SH__W 16 -#define B_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF -#define B_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x2 - #define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D -#define B_SC_RA_RAM_CO_TD_CAL_2K__W 16 -#define B_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF -#define B_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB #define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E -#define B_SC_RA_RAM_CO_TD_CAL_8K__W 16 -#define B_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF -#define B_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8 -#define B_SC_RA_RAM_MOTION_OFFSET__A 0x82005F -#define B_SC_RA_RAM_MOTION_OFFSET__W 16 -#define B_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF -#define B_SC_RA_RAM_MOTION_OFFSET__PRE 0x2 -#define B_SC_RA_RAM_STATE_PROC_STOP__AX 0x820060 -#define B_SC_RA_RAM_STATE_PROC_STOP__XSZ 10 -#define B_SC_RA_RAM_STATE_PROC_STOP__W 16 -#define B_SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF -#define B_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE -#define B_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4 -#define B_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_STOP_10__PRE 0xFFFE -#define B_SC_RA_RAM_STATE_PROC_START__AX 0x820070 -#define B_SC_RA_RAM_STATE_PROC_START__XSZ 10 -#define B_SC_RA_RAM_STATE_PROC_START__W 16 -#define B_SC_RA_RAM_STATE_PROC_START__M 0xFFFF -#define B_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80 -#define B_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2 -#define B_SC_RA_RAM_STATE_PROC_START_3__PRE 0x4 -#define B_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4 -#define B_SC_RA_RAM_STATE_PROC_START_5__PRE 0x100 -#define B_SC_RA_RAM_STATE_PROC_START_6__PRE 0x0 -#define B_SC_RA_RAM_STATE_PROC_START_7__PRE 0x40 -#define B_SC_RA_RAM_STATE_PROC_START_8__PRE 0x10 -#define B_SC_RA_RAM_STATE_PROC_START_9__PRE 0x30 -#define B_SC_RA_RAM_STATE_PROC_START_10__PRE 0x0 #define B_SC_RA_RAM_IF_SAVE__AX 0x82008E -#define B_SC_RA_RAM_IF_SAVE__XSZ 2 -#define B_SC_RA_RAM_IF_SAVE__W 16 -#define B_SC_RA_RAM_IF_SAVE__M 0xFFFF -#define B_SC_RA_RAM_FR_THRES__A 0x82007D -#define B_SC_RA_RAM_FR_THRES__W 16 -#define B_SC_RA_RAM_FR_THRES__M 0xFFFF -#define B_SC_RA_RAM_FR_THRES__PRE 0x1A2C -#define B_SC_RA_RAM_STATUS__A 0x82007E -#define B_SC_RA_RAM_STATUS__W 16 -#define B_SC_RA_RAM_STATUS__M 0xFFFF -#define B_SC_RA_RAM_NF_BORDER_INIT__A 0x82007F -#define B_SC_RA_RAM_NF_BORDER_INIT__W 16 -#define B_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF -#define B_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708 -#define B_SC_RA_RAM_TIMER__A 0x820080 -#define B_SC_RA_RAM_TIMER__W 16 -#define B_SC_RA_RAM_TIMER__M 0xFFFF -#define B_SC_RA_RAM_FI_OFFSET__A 0x820081 -#define B_SC_RA_RAM_FI_OFFSET__W 16 -#define B_SC_RA_RAM_FI_OFFSET__M 0xFFFF -#define B_SC_RA_RAM_FI_OFFSET__PRE 0x382 -#define B_SC_RA_RAM_ECHO_GUARD__A 0x820082 -#define B_SC_RA_RAM_ECHO_GUARD__W 16 -#define B_SC_RA_RAM_ECHO_GUARD__M 0xFFFF -#define B_SC_RA_RAM_ECHO_GUARD__PRE 0x18 -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__A 0x8200BA -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__W 16 -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__M 0xFFFF -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__PRE 0x3 -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__A 0x8200BB -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__W 16 -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__M 0xFFFF -#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__PRE 0x0 - #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258 #define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258 - #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC #define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16 -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF -#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC - -#define B_SC_RA_RAM_IR_FREQ__A 0x8200D0 -#define B_SC_RA_RAM_IR_FREQ__W 16 -#define B_SC_RA_RAM_IR_FREQ__M 0xFFFF -#define B_SC_RA_RAM_IR_FREQ__PRE 0x0 - #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 -#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16 -#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF #define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 -#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16 -#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF #define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 -#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16 -#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF #define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 - #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 -#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16 -#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF #define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 -#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16 -#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF #define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 -#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16 -#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF #define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 - #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 -#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16 -#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF #define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 -#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16 -#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF #define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 -#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16 -#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF #define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 - #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA -#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16 -#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF #define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB -#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16 -#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF #define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1 #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC -#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16 -#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF #define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40 - #define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD -#define B_SC_RA_RAM_ECHO_SHIFT_LIM__W 16 -#define B_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF -#define B_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18 -#define B_SC_RA_RAM_ECHO_SHT_LIM__A 0x8200DE -#define B_SC_RA_RAM_ECHO_SHT_LIM__W 16 -#define B_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF -#define B_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x8200DF -#define B_SC_RA_RAM_ECHO_SHIFT_TERM__W 16 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF -#define B_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0xCC0 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6 -#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00 - -#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0 -#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16 -#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7 -#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1 -#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16 -#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1 -#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2 -#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16 -#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8 - -#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3 -#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16 -#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE -#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4 -#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16 -#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7 -#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5 -#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16 -#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF -#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0 - #define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8 -#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16 -#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF -#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2 #define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9 -#define B_SC_RA_RAM_SAMPLE_RATE_STEP__W 16 -#define B_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF -#define B_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C - -#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA -#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16 -#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF -#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8 -#define B_SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB -#define B_SC_RA_RAM_TPS_TIMEOUT__W 16 -#define B_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF #define B_SC_RA_RAM_BAND__A 0x8200EC -#define B_SC_RA_RAM_BAND__W 16 -#define B_SC_RA_RAM_BAND__M 0xFFFF -#define B_SC_RA_RAM_BAND__PRE 0x0 -#define B_SC_RA_RAM_BAND_INTERVAL__B 0 -#define B_SC_RA_RAM_BAND_INTERVAL__W 4 -#define B_SC_RA_RAM_BAND_INTERVAL__M 0xF -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1 -#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1 -#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000 - -#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED -#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16 -#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF -#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0 -#define B_SC_RA_RAM_REG__AX 0x8200F0 -#define B_SC_RA_RAM_REG__XSZ 2 -#define B_SC_RA_RAM_REG__W 16 -#define B_SC_RA_RAM_REG__M 0xFFFF -#define B_SC_RA_RAM_BREAK__A 0x8200F2 -#define B_SC_RA_RAM_BREAK__W 16 -#define B_SC_RA_RAM_BREAK__M 0xFFFF -#define B_SC_RA_RAM_BOOTCOUNT__A 0x8200F3 -#define B_SC_RA_RAM_BOOTCOUNT__W 16 -#define B_SC_RA_RAM_BOOTCOUNT__M 0xFFFF - #define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4 -#define B_SC_RA_RAM_LC_ABS_2K__W 16 -#define B_SC_RA_RAM_LC_ABS_2K__M 0xFFFF #define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F #define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5 -#define B_SC_RA_RAM_LC_ABS_8K__W 16 -#define B_SC_RA_RAM_LC_ABS_8K__M 0xFFFF #define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F -#define B_SC_RA_RAM_NE_ERR_SELECT__A 0x8200F6 -#define B_SC_RA_RAM_NE_ERR_SELECT__W 16 -#define B_SC_RA_RAM_NE_ERR_SELECT__M 0xFFFF -#define B_SC_RA_RAM_NE_ERR_SELECT__PRE 0x19 -#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x8200F7 -#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16 -#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF -#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14 -#define B_SC_RA_RAM_RELOCK__A 0x8200FE -#define B_SC_RA_RAM_RELOCK__W 16 -#define B_SC_RA_RAM_RELOCK__M 0xFFFF -#define B_SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF -#define B_SC_RA_RAM_STACKUNDERFLOW__W 16 -#define B_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF - -#define B_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148 -#define B_SC_RA_RAM_NF_MAXECHOTOKEN__W 16 -#define B_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF -#define B_SC_RA_RAM_NF_PREPOST__A 0x820149 -#define B_SC_RA_RAM_NF_PREPOST__W 16 -#define B_SC_RA_RAM_NF_PREPOST__M 0xFFFF -#define B_SC_RA_RAM_NF_PREBORDER__A 0x82014A -#define B_SC_RA_RAM_NF_PREBORDER__W 16 -#define B_SC_RA_RAM_NF_PREBORDER__M 0xFFFF -#define B_SC_RA_RAM_NF_START__A 0x82014B -#define B_SC_RA_RAM_NF_START__W 16 -#define B_SC_RA_RAM_NF_START__M 0xFFFF -#define B_SC_RA_RAM_NF_MINISI__AX 0x82014C -#define B_SC_RA_RAM_NF_MINISI__XSZ 2 -#define B_SC_RA_RAM_NF_MINISI__W 16 -#define B_SC_RA_RAM_NF_MINISI__M 0xFFFF -#define B_SC_RA_RAM_NF_MAXECHO__A 0x82014E -#define B_SC_RA_RAM_NF_MAXECHO__W 16 -#define B_SC_RA_RAM_NF_MAXECHO__M 0xFFFF -#define B_SC_RA_RAM_NF_NRECHOES__A 0x82014F -#define B_SC_RA_RAM_NF_NRECHOES__W 16 -#define B_SC_RA_RAM_NF_NRECHOES__M 0xFFFF -#define B_SC_RA_RAM_NF_ECHOTABLE__AX 0x820150 -#define B_SC_RA_RAM_NF_ECHOTABLE__XSZ 16 -#define B_SC_RA_RAM_NF_ECHOTABLE__W 16 -#define B_SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF - -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0 -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100 -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1 -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4 - -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2 -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2 -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3 -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4 - -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5 - -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4 - -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5 - -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5 - -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4 - -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16 -#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF #define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4 #define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE -#define B_SC_RA_RAM_DRIVER_VERSION__XSZ 2 -#define B_SC_RA_RAM_DRIVER_VERSION__W 16 -#define B_SC_RA_RAM_DRIVER_VERSION__M 0xFFFF -#define B_SC_RA_RAM_EVENT0_MIN 0x7 -#define B_SC_RA_RAM_EVENT0_FE_CU 0x7 -#define B_SC_RA_RAM_EVENT0_CE 0xA -#define B_SC_RA_RAM_EVENT0_EQ 0xE -#define B_SC_RA_RAM_EVENT0_MAX 0xF #define B_SC_RA_RAM_PROC_LOCKTRACK 0x0 -#define B_SC_RA_RAM_PROC_MODE_GUARD 0x1 -#define B_SC_RA_RAM_PROC_PILOTS 0x2 -#define B_SC_RA_RAM_PROC_FESTART_ADJUST 0x3 -#define B_SC_RA_RAM_PROC_ECHO 0x4 -#define B_SC_RA_RAM_PROC_BE_OPT 0x5 -#define B_SC_RA_RAM_PROC_LOCK_MON 0x6 -#define B_SC_RA_RAM_PROC_EQ 0x7 -#define B_SC_RA_RAM_PROC_ECHO_DIVERSITY 0x8 -#define B_SC_RA_RAM_PROC_MAX 0x9 - -#define B_SC_IF_RAM_TRP_RST__AX 0x830000 -#define B_SC_IF_RAM_TRP_RST__XSZ 2 -#define B_SC_IF_RAM_TRP_RST__W 12 -#define B_SC_IF_RAM_TRP_RST__M 0xFFF - -#define B_SC_IF_RAM_TRP_BPT0__AX 0x830002 -#define B_SC_IF_RAM_TRP_BPT0__XSZ 2 -#define B_SC_IF_RAM_TRP_BPT0__W 12 -#define B_SC_IF_RAM_TRP_BPT0__M 0xFFF - -#define B_SC_IF_RAM_TRP_STKU__AX 0x830004 -#define B_SC_IF_RAM_TRP_STKU__XSZ 2 -#define B_SC_IF_RAM_TRP_STKU__W 12 -#define B_SC_IF_RAM_TRP_STKU__M 0xFFF - -#define B_SC_IF_RAM_VERSION_MA_MI__A 0x830FFE -#define B_SC_IF_RAM_VERSION_MA_MI__W 12 -#define B_SC_IF_RAM_VERSION_MA_MI__M 0xFFF - -#define B_SC_IF_RAM_VERSION_PATCH__A 0x830FFF -#define B_SC_IF_RAM_VERSION_PATCH__W 12 -#define B_SC_IF_RAM_VERSION_PATCH__M 0xFFF - #define B_FE_COMM_EXEC__A 0xC00000 -#define B_FE_COMM_EXEC__W 3 -#define B_FE_COMM_EXEC__M 0x7 -#define B_FE_COMM_EXEC_CTL__B 0 -#define B_FE_COMM_EXEC_CTL__W 3 -#define B_FE_COMM_EXEC_CTL__M 0x7 -#define B_FE_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_COMM_EXEC_CTL_STEP 0x3 -#define B_FE_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_FE_COMM_STATE__A 0xC00001 -#define B_FE_COMM_STATE__W 16 -#define B_FE_COMM_STATE__M 0xFFFF -#define B_FE_COMM_MB__A 0xC00002 -#define B_FE_COMM_MB__W 16 -#define B_FE_COMM_MB__M 0xFFFF -#define B_FE_COMM_SERVICE0__A 0xC00003 -#define B_FE_COMM_SERVICE0__W 16 -#define B_FE_COMM_SERVICE0__M 0xFFFF -#define B_FE_COMM_SERVICE1__A 0xC00004 -#define B_FE_COMM_SERVICE1__W 16 -#define B_FE_COMM_SERVICE1__M 0xFFFF -#define B_FE_COMM_INT_STA__A 0xC00007 -#define B_FE_COMM_INT_STA__W 16 -#define B_FE_COMM_INT_STA__M 0xFFFF -#define B_FE_COMM_INT_MSK__A 0xC00008 -#define B_FE_COMM_INT_MSK__W 16 -#define B_FE_COMM_INT_MSK__M 0xFFFF - -#define B_FE_AD_SID 0x1 - #define B_FE_AD_REG_COMM_EXEC__A 0xC10000 -#define B_FE_AD_REG_COMM_EXEC__W 3 -#define B_FE_AD_REG_COMM_EXEC__M 0x7 -#define B_FE_AD_REG_COMM_EXEC_CTL__B 0 -#define B_FE_AD_REG_COMM_EXEC_CTL__W 3 -#define B_FE_AD_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_AD_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_AD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_AD_REG_COMM_MB__A 0xC10002 -#define B_FE_AD_REG_COMM_MB__W 2 -#define B_FE_AD_REG_COMM_MB__M 0x3 -#define B_FE_AD_REG_COMM_MB_CTR__B 0 -#define B_FE_AD_REG_COMM_MB_CTR__W 1 -#define B_FE_AD_REG_COMM_MB_CTR__M 0x1 -#define B_FE_AD_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_AD_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_AD_REG_COMM_MB_OBS__B 1 -#define B_FE_AD_REG_COMM_MB_OBS__W 1 -#define B_FE_AD_REG_COMM_MB_OBS__M 0x2 -#define B_FE_AD_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_AD_REG_COMM_MB_OBS_ON 0x2 - -#define B_FE_AD_REG_COMM_SERVICE0__A 0xC10003 -#define B_FE_AD_REG_COMM_SERVICE0__W 10 -#define B_FE_AD_REG_COMM_SERVICE0__M 0x3FF -#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__B 0 -#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__W 1 -#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1 - -#define B_FE_AD_REG_COMM_SERVICE1__A 0xC10004 -#define B_FE_AD_REG_COMM_SERVICE1__W 11 -#define B_FE_AD_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_AD_REG_COMM_INT_STA__A 0xC10007 -#define B_FE_AD_REG_COMM_INT_STA__W 2 -#define B_FE_AD_REG_COMM_INT_STA__M 0x3 -#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0 -#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1 -#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1 - -#define B_FE_AD_REG_COMM_INT_MSK__A 0xC10008 -#define B_FE_AD_REG_COMM_INT_MSK__W 2 -#define B_FE_AD_REG_COMM_INT_MSK__M 0x3 -#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0 -#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1 -#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1 - -#define B_FE_AD_REG_CUR_SEL__A 0xC10010 -#define B_FE_AD_REG_CUR_SEL__W 2 -#define B_FE_AD_REG_CUR_SEL__M 0x3 -#define B_FE_AD_REG_CUR_SEL_INIT 0x2 - -#define B_FE_AD_REG_OVERFLOW__A 0xC10011 -#define B_FE_AD_REG_OVERFLOW__W 1 -#define B_FE_AD_REG_OVERFLOW__M 0x1 -#define B_FE_AD_REG_OVERFLOW_INIT 0x0 - #define B_FE_AD_REG_FDB_IN__A 0xC10012 -#define B_FE_AD_REG_FDB_IN__W 1 -#define B_FE_AD_REG_FDB_IN__M 0x1 -#define B_FE_AD_REG_FDB_IN_INIT 0x0 - #define B_FE_AD_REG_PD__A 0xC10013 -#define B_FE_AD_REG_PD__W 1 -#define B_FE_AD_REG_PD__M 0x1 -#define B_FE_AD_REG_PD_INIT 0x1 - #define B_FE_AD_REG_INVEXT__A 0xC10014 -#define B_FE_AD_REG_INVEXT__W 1 -#define B_FE_AD_REG_INVEXT__M 0x1 -#define B_FE_AD_REG_INVEXT_INIT 0x0 - #define B_FE_AD_REG_CLKNEG__A 0xC10015 -#define B_FE_AD_REG_CLKNEG__W 1 -#define B_FE_AD_REG_CLKNEG__M 0x1 -#define B_FE_AD_REG_CLKNEG_INIT 0x0 - -#define B_FE_AD_REG_MON_IN_MUX__A 0xC10016 -#define B_FE_AD_REG_MON_IN_MUX__W 2 -#define B_FE_AD_REG_MON_IN_MUX__M 0x3 -#define B_FE_AD_REG_MON_IN_MUX_INIT 0x0 - -#define B_FE_AD_REG_MON_IN5__A 0xC10017 -#define B_FE_AD_REG_MON_IN5__W 10 -#define B_FE_AD_REG_MON_IN5__M 0x3FF -#define B_FE_AD_REG_MON_IN5_INIT 0x0 - -#define B_FE_AD_REG_MON_IN4__A 0xC10018 -#define B_FE_AD_REG_MON_IN4__W 10 -#define B_FE_AD_REG_MON_IN4__M 0x3FF -#define B_FE_AD_REG_MON_IN4_INIT 0x0 - -#define B_FE_AD_REG_MON_IN3__A 0xC10019 -#define B_FE_AD_REG_MON_IN3__W 10 -#define B_FE_AD_REG_MON_IN3__M 0x3FF -#define B_FE_AD_REG_MON_IN3_INIT 0x0 - -#define B_FE_AD_REG_MON_IN2__A 0xC1001A -#define B_FE_AD_REG_MON_IN2__W 10 -#define B_FE_AD_REG_MON_IN2__M 0x3FF -#define B_FE_AD_REG_MON_IN2_INIT 0x0 - -#define B_FE_AD_REG_MON_IN1__A 0xC1001B -#define B_FE_AD_REG_MON_IN1__W 10 -#define B_FE_AD_REG_MON_IN1__M 0x3FF -#define B_FE_AD_REG_MON_IN1_INIT 0x0 - -#define B_FE_AD_REG_MON_IN0__A 0xC1001C -#define B_FE_AD_REG_MON_IN0__W 10 -#define B_FE_AD_REG_MON_IN0__M 0x3FF -#define B_FE_AD_REG_MON_IN0_INIT 0x0 - -#define B_FE_AD_REG_MON_IN_VAL__A 0xC1001D -#define B_FE_AD_REG_MON_IN_VAL__W 1 -#define B_FE_AD_REG_MON_IN_VAL__M 0x1 -#define B_FE_AD_REG_MON_IN_VAL_INIT 0x0 - -#define B_FE_AD_REG_CTR_CLK_O__A 0xC1001E -#define B_FE_AD_REG_CTR_CLK_O__W 1 -#define B_FE_AD_REG_CTR_CLK_O__M 0x1 -#define B_FE_AD_REG_CTR_CLK_O_INIT 0x0 - -#define B_FE_AD_REG_CTR_CLK_E_O__A 0xC1001F -#define B_FE_AD_REG_CTR_CLK_E_O__W 1 -#define B_FE_AD_REG_CTR_CLK_E_O__M 0x1 -#define B_FE_AD_REG_CTR_CLK_E_O_INIT 0x1 - -#define B_FE_AD_REG_CTR_VAL_O__A 0xC10020 -#define B_FE_AD_REG_CTR_VAL_O__W 1 -#define B_FE_AD_REG_CTR_VAL_O__M 0x1 -#define B_FE_AD_REG_CTR_VAL_O_INIT 0x0 - -#define B_FE_AD_REG_CTR_VAL_E_O__A 0xC10021 -#define B_FE_AD_REG_CTR_VAL_E_O__W 1 -#define B_FE_AD_REG_CTR_VAL_E_O__M 0x1 -#define B_FE_AD_REG_CTR_VAL_E_O_INIT 0x1 - -#define B_FE_AD_REG_CTR_DATA_O__A 0xC10022 -#define B_FE_AD_REG_CTR_DATA_O__W 10 -#define B_FE_AD_REG_CTR_DATA_O__M 0x3FF -#define B_FE_AD_REG_CTR_DATA_O_INIT 0x0 - -#define B_FE_AD_REG_CTR_DATA_E_O__A 0xC10023 -#define B_FE_AD_REG_CTR_DATA_E_O__W 10 -#define B_FE_AD_REG_CTR_DATA_E_O__M 0x3FF -#define B_FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF - -#define B_FE_AG_SID 0x2 - #define B_FE_AG_REG_COMM_EXEC__A 0xC20000 -#define B_FE_AG_REG_COMM_EXEC__W 3 -#define B_FE_AG_REG_COMM_EXEC__M 0x7 -#define B_FE_AG_REG_COMM_EXEC_CTL__B 0 -#define B_FE_AG_REG_COMM_EXEC_CTL__W 3 -#define B_FE_AG_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_AG_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_AG_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_AG_REG_COMM_STATE__A 0xC20001 -#define B_FE_AG_REG_COMM_STATE__W 4 -#define B_FE_AG_REG_COMM_STATE__M 0xF - -#define B_FE_AG_REG_COMM_MB__A 0xC20002 -#define B_FE_AG_REG_COMM_MB__W 4 -#define B_FE_AG_REG_COMM_MB__M 0xF -#define B_FE_AG_REG_COMM_MB_OBS__B 1 -#define B_FE_AG_REG_COMM_MB_OBS__W 1 -#define B_FE_AG_REG_COMM_MB_OBS__M 0x2 -#define B_FE_AG_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_AG_REG_COMM_MB_OBS_ON 0x2 -#define B_FE_AG_REG_COMM_MB_MUX__B 2 -#define B_FE_AG_REG_COMM_MB_MUX__W 2 -#define B_FE_AG_REG_COMM_MB_MUX__M 0xC -#define B_FE_AG_REG_COMM_MB_MUX_DAT 0x0 -#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD2 0x4 -#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD1 0x8 -#define B_FE_AG_REG_COMM_MB_MUX_DAT_IND_PD1 0xC - -#define B_FE_AG_REG_COMM_SERVICE0__A 0xC20003 -#define B_FE_AG_REG_COMM_SERVICE0__W 10 -#define B_FE_AG_REG_COMM_SERVICE0__M 0x3FF - -#define B_FE_AG_REG_COMM_SERVICE1__A 0xC20004 -#define B_FE_AG_REG_COMM_SERVICE1__W 11 -#define B_FE_AG_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_AG_REG_COMM_INT_STA__A 0xC20007 -#define B_FE_AG_REG_COMM_INT_STA__W 8 -#define B_FE_AG_REG_COMM_INT_STA__M 0xFF -#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0 -#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1 -#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1 -#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2 -#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2 -#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4 -#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3 -#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8 -#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4 -#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10 -#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5 -#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20 -#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7 -#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80 - -#define B_FE_AG_REG_COMM_INT_MSK__A 0xC20008 -#define B_FE_AG_REG_COMM_INT_MSK__W 8 -#define B_FE_AG_REG_COMM_INT_MSK__M 0xFF -#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0 -#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1 -#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1 -#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2 -#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2 -#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4 -#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3 -#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8 -#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4 -#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10 -#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5 -#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20 -#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7 -#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1 -#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80 - #define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010 -#define B_FE_AG_REG_AG_MODE_LOP__W 15 -#define B_FE_AG_REG_AG_MODE_LOP__M 0x7FFF -#define B_FE_AG_REG_AG_MODE_LOP_INIT 0x81E - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__B 0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__B 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__B 2 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__B 3 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__B 4 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__W 1 #define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10 #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0 #define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__B 5 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__W 1 #define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20 #define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__B 6 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__B 7 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__B 8 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__B 11 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__B 9 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__B 12 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__W 1 #define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000 #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0 #define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__B 13 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__W 1 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000 - -#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__B 14 -#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__W 1 #define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000 #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0 #define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000 - #define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011 -#define B_FE_AG_REG_AG_MODE_HIP__W 5 -#define B_FE_AG_REG_AG_MODE_HIP__M 0x1F -#define B_FE_AG_REG_AG_MODE_HIP_INIT 0x0 - -#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__B 0 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__W 1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1 - -#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__B 1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__W 1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2 - -#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__B 2 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__W 1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__M 0x4 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH1 0x0 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH2 0x4 - -#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__B 3 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__W 1 #define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8 #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0 #define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8 - -#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__B 4 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__W 1 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__M 0x10 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH1 0x0 -#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH2 0x10 - #define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012 -#define B_FE_AG_REG_AG_PGA_MODE__W 3 -#define B_FE_AG_REG_AG_PGA_MODE__M 0x7 -#define B_FE_AG_REG_AG_PGA_MODE_INIT 0x3 #define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0 #define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1 -#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2 -#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3 -#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4 -#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5 -#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6 -#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7 - #define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013 -#define B_FE_AG_REG_AG_AGC_SIO__W 2 -#define B_FE_AG_REG_AG_AGC_SIO__M 0x3 -#define B_FE_AG_REG_AG_AGC_SIO_INIT 0x3 - -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1 - -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1 -#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1 #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2 #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0 #define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2 - -#define B_FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014 -#define B_FE_AG_REG_AG_AGC_USR_DAT__W 2 -#define B_FE_AG_REG_AG_AGC_USR_DAT__M 0x3 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1 -#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2 - -#define B_FE_AG_REG_AG_PWD__A 0xC20015 -#define B_FE_AG_REG_AG_PWD__W 5 -#define B_FE_AG_REG_AG_PWD__M 0x1F -#define B_FE_AG_REG_AG_PWD_INIT 0x6 - -#define B_FE_AG_REG_AG_PWD_PWD_PD1__B 0 -#define B_FE_AG_REG_AG_PWD_PWD_PD1__W 1 -#define B_FE_AG_REG_AG_PWD_PWD_PD1__M 0x1 -#define B_FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0 -#define B_FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1 - -#define B_FE_AG_REG_AG_PWD_PWD_PD2__B 1 -#define B_FE_AG_REG_AG_PWD_PWD_PD2__W 1 +#define B_FE_AG_REG_AG_PWD__A 0xC20015 #define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2 #define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0 #define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2 - -#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__B 2 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__W 1 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4 - -#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__B 3 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__W 1 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0 -#define B_FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8 - -#define B_FE_AG_REG_AG_PWD_PWD_AAF__B 4 -#define B_FE_AG_REG_AG_PWD_PWD_AAF__W 1 -#define B_FE_AG_REG_AG_PWD_PWD_AAF__M 0x10 -#define B_FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0 -#define B_FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10 - #define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016 -#define B_FE_AG_REG_DCE_AUR_CNT__W 5 -#define B_FE_AG_REG_DCE_AUR_CNT__M 0x1F -#define B_FE_AG_REG_DCE_AUR_CNT_INIT 0x10 - #define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017 -#define B_FE_AG_REG_DCE_RUR_CNT__W 5 -#define B_FE_AG_REG_DCE_RUR_CNT__M 0x1F -#define B_FE_AG_REG_DCE_RUR_CNT_INIT 0x0 - -#define B_FE_AG_REG_DCE_AVE_DAT__A 0xC20018 -#define B_FE_AG_REG_DCE_AVE_DAT__W 10 -#define B_FE_AG_REG_DCE_AVE_DAT__M 0x3FF - -#define B_FE_AG_REG_DEC_AVE_WRI__A 0xC20019 -#define B_FE_AG_REG_DEC_AVE_WRI__W 10 -#define B_FE_AG_REG_DEC_AVE_WRI__M 0x3FF -#define B_FE_AG_REG_DEC_AVE_WRI_INIT 0x0 - #define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A -#define B_FE_AG_REG_ACE_AUR_CNT__W 5 -#define B_FE_AG_REG_ACE_AUR_CNT__M 0x1F -#define B_FE_AG_REG_ACE_AUR_CNT_INIT 0xE - #define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B -#define B_FE_AG_REG_ACE_RUR_CNT__W 5 -#define B_FE_AG_REG_ACE_RUR_CNT__M 0x1F -#define B_FE_AG_REG_ACE_RUR_CNT_INIT 0x0 - -#define B_FE_AG_REG_ACE_AVE_DAT__A 0xC2001C -#define B_FE_AG_REG_ACE_AVE_DAT__W 10 -#define B_FE_AG_REG_ACE_AVE_DAT__M 0x3FF - -#define B_FE_AG_REG_AEC_AVE_INC__A 0xC2001D -#define B_FE_AG_REG_AEC_AVE_INC__W 10 -#define B_FE_AG_REG_AEC_AVE_INC__M 0x3FF -#define B_FE_AG_REG_AEC_AVE_INC_INIT 0x0 - -#define B_FE_AG_REG_AEC_AVE_DAT__A 0xC2001E -#define B_FE_AG_REG_AEC_AVE_DAT__W 10 -#define B_FE_AG_REG_AEC_AVE_DAT__M 0x3FF - -#define B_FE_AG_REG_AEC_CLP_LVL__A 0xC2001F -#define B_FE_AG_REG_AEC_CLP_LVL__W 16 -#define B_FE_AG_REG_AEC_CLP_LVL__M 0xFFFF -#define B_FE_AG_REG_AEC_CLP_LVL_INIT 0x0 - #define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020 -#define B_FE_AG_REG_CDR_RUR_CNT__W 5 -#define B_FE_AG_REG_CDR_RUR_CNT__M 0x1F -#define B_FE_AG_REG_CDR_RUR_CNT_INIT 0x10 - -#define B_FE_AG_REG_CDR_CLP_DAT__A 0xC20021 -#define B_FE_AG_REG_CDR_CLP_DAT__W 16 -#define B_FE_AG_REG_CDR_CLP_DAT__M 0xFFFF - -#define B_FE_AG_REG_CDR_CLP_POS__A 0xC20022 -#define B_FE_AG_REG_CDR_CLP_POS__W 10 -#define B_FE_AG_REG_CDR_CLP_POS__M 0x3FF -#define B_FE_AG_REG_CDR_CLP_POS_INIT 0x16A - -#define B_FE_AG_REG_CDR_CLP_NEG__A 0xC20023 -#define B_FE_AG_REG_CDR_CLP_NEG__W 10 -#define B_FE_AG_REG_CDR_CLP_NEG__M 0x3FF -#define B_FE_AG_REG_CDR_CLP_NEG_INIT 0x296 - #define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024 -#define B_FE_AG_REG_EGC_RUR_CNT__W 5 -#define B_FE_AG_REG_EGC_RUR_CNT__M 0x1F -#define B_FE_AG_REG_EGC_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025 -#define B_FE_AG_REG_EGC_SET_LVL__W 9 #define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF -#define B_FE_AG_REG_EGC_SET_LVL_INIT 0x46 - #define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026 -#define B_FE_AG_REG_EGC_FLA_RGN__W 9 -#define B_FE_AG_REG_EGC_FLA_RGN__M 0x1FF -#define B_FE_AG_REG_EGC_FLA_RGN_INIT 0x4 - #define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027 -#define B_FE_AG_REG_EGC_SLO_RGN__W 9 -#define B_FE_AG_REG_EGC_SLO_RGN__M 0x1FF -#define B_FE_AG_REG_EGC_SLO_RGN_INIT 0x1F - #define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028 -#define B_FE_AG_REG_EGC_JMP_PSN__W 4 -#define B_FE_AG_REG_EGC_JMP_PSN__M 0xF -#define B_FE_AG_REG_EGC_JMP_PSN_INIT 0x0 - #define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029 -#define B_FE_AG_REG_EGC_FLA_INC__W 16 -#define B_FE_AG_REG_EGC_FLA_INC__M 0xFFFF -#define B_FE_AG_REG_EGC_FLA_INC_INIT 0x0 - #define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A -#define B_FE_AG_REG_EGC_FLA_DEC__W 16 -#define B_FE_AG_REG_EGC_FLA_DEC__M 0xFFFF -#define B_FE_AG_REG_EGC_FLA_DEC_INIT 0x0 - #define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B -#define B_FE_AG_REG_EGC_SLO_INC__W 16 -#define B_FE_AG_REG_EGC_SLO_INC__M 0xFFFF -#define B_FE_AG_REG_EGC_SLO_INC_INIT 0x3 - #define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C -#define B_FE_AG_REG_EGC_SLO_DEC__W 16 -#define B_FE_AG_REG_EGC_SLO_DEC__M 0xFFFF -#define B_FE_AG_REG_EGC_SLO_DEC_INIT 0x3 - #define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D -#define B_FE_AG_REG_EGC_FAS_INC__W 16 -#define B_FE_AG_REG_EGC_FAS_INC__M 0xFFFF -#define B_FE_AG_REG_EGC_FAS_INC_INIT 0xE - #define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E -#define B_FE_AG_REG_EGC_FAS_DEC__W 16 -#define B_FE_AG_REG_EGC_FAS_DEC__M 0xFFFF -#define B_FE_AG_REG_EGC_FAS_DEC_INIT 0xE - -#define B_FE_AG_REG_EGC_MAP_DAT__A 0xC2002F -#define B_FE_AG_REG_EGC_MAP_DAT__W 16 -#define B_FE_AG_REG_EGC_MAP_DAT__M 0xFFFF - #define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030 -#define B_FE_AG_REG_PM1_AGC_WRI__W 11 #define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF -#define B_FE_AG_REG_PM1_AGC_WRI_INIT 0x0 - #define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031 -#define B_FE_AG_REG_GC1_AGC_RIC__W 16 -#define B_FE_AG_REG_GC1_AGC_RIC__M 0xFFFF -#define B_FE_AG_REG_GC1_AGC_RIC_INIT 0x64 - #define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032 -#define B_FE_AG_REG_GC1_AGC_OFF__W 16 -#define B_FE_AG_REG_GC1_AGC_OFF__M 0xFFFF -#define B_FE_AG_REG_GC1_AGC_OFF_INIT 0xFEC8 - #define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033 -#define B_FE_AG_REG_GC1_AGC_MAX__W 10 -#define B_FE_AG_REG_GC1_AGC_MAX__M 0x3FF -#define B_FE_AG_REG_GC1_AGC_MAX_INIT 0x1FF - #define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034 -#define B_FE_AG_REG_GC1_AGC_MIN__W 10 -#define B_FE_AG_REG_GC1_AGC_MIN__M 0x3FF -#define B_FE_AG_REG_GC1_AGC_MIN_INIT 0x200 - #define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035 -#define B_FE_AG_REG_GC1_AGC_DAT__W 10 #define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF - #define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036 -#define B_FE_AG_REG_PM2_AGC_WRI__W 11 -#define B_FE_AG_REG_PM2_AGC_WRI__M 0x7FF -#define B_FE_AG_REG_PM2_AGC_WRI_INIT 0x0 - -#define B_FE_AG_REG_GC2_AGC_RIC__A 0xC20037 -#define B_FE_AG_REG_GC2_AGC_RIC__W 16 -#define B_FE_AG_REG_GC2_AGC_RIC__M 0xFFFF -#define B_FE_AG_REG_GC2_AGC_RIC_INIT 0x64 - -#define B_FE_AG_REG_GC2_AGC_OFF__A 0xC20038 -#define B_FE_AG_REG_GC2_AGC_OFF__W 16 -#define B_FE_AG_REG_GC2_AGC_OFF__M 0xFFFF -#define B_FE_AG_REG_GC2_AGC_OFF_INIT 0xFEC8 - -#define B_FE_AG_REG_GC2_AGC_MAX__A 0xC20039 -#define B_FE_AG_REG_GC2_AGC_MAX__W 10 -#define B_FE_AG_REG_GC2_AGC_MAX__M 0x3FF -#define B_FE_AG_REG_GC2_AGC_MAX_INIT 0x1FF - -#define B_FE_AG_REG_GC2_AGC_MIN__A 0xC2003A -#define B_FE_AG_REG_GC2_AGC_MIN__W 10 -#define B_FE_AG_REG_GC2_AGC_MIN__M 0x3FF -#define B_FE_AG_REG_GC2_AGC_MIN_INIT 0x200 - -#define B_FE_AG_REG_GC2_AGC_DAT__A 0xC2003B -#define B_FE_AG_REG_GC2_AGC_DAT__W 10 -#define B_FE_AG_REG_GC2_AGC_DAT__M 0x3FF - #define B_FE_AG_REG_IND_WIN__A 0xC2003C -#define B_FE_AG_REG_IND_WIN__W 5 -#define B_FE_AG_REG_IND_WIN__M 0x1F -#define B_FE_AG_REG_IND_WIN_INIT 0x0 - #define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D -#define B_FE_AG_REG_IND_THD_LOL__W 6 -#define B_FE_AG_REG_IND_THD_LOL__M 0x3F -#define B_FE_AG_REG_IND_THD_LOL_INIT 0x5 - #define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E -#define B_FE_AG_REG_IND_THD_HIL__W 6 -#define B_FE_AG_REG_IND_THD_HIL__M 0x3F -#define B_FE_AG_REG_IND_THD_HIL_INIT 0xF - #define B_FE_AG_REG_IND_DEL__A 0xC2003F -#define B_FE_AG_REG_IND_DEL__W 7 -#define B_FE_AG_REG_IND_DEL__M 0x7F -#define B_FE_AG_REG_IND_DEL_INIT 0x32 - #define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040 -#define B_FE_AG_REG_IND_PD1_WRI__W 6 -#define B_FE_AG_REG_IND_PD1_WRI__M 0x3F -#define B_FE_AG_REG_IND_PD1_WRI_INIT 0x1E - #define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041 -#define B_FE_AG_REG_PDA_AUR_CNT__W 5 -#define B_FE_AG_REG_PDA_AUR_CNT__M 0x1F -#define B_FE_AG_REG_PDA_AUR_CNT_INIT 0x10 - #define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042 -#define B_FE_AG_REG_PDA_RUR_CNT__W 5 -#define B_FE_AG_REG_PDA_RUR_CNT__M 0x1F -#define B_FE_AG_REG_PDA_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043 -#define B_FE_AG_REG_PDA_AVE_DAT__W 6 -#define B_FE_AG_REG_PDA_AVE_DAT__M 0x3F - #define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044 -#define B_FE_AG_REG_PDC_RUR_CNT__W 5 -#define B_FE_AG_REG_PDC_RUR_CNT__M 0x1F -#define B_FE_AG_REG_PDC_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045 -#define B_FE_AG_REG_PDC_SET_LVL__W 6 -#define B_FE_AG_REG_PDC_SET_LVL__M 0x3F -#define B_FE_AG_REG_PDC_SET_LVL_INIT 0x10 - #define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046 -#define B_FE_AG_REG_PDC_FLA_RGN__W 6 -#define B_FE_AG_REG_PDC_FLA_RGN__M 0x3F -#define B_FE_AG_REG_PDC_FLA_RGN_INIT 0x0 - #define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047 -#define B_FE_AG_REG_PDC_JMP_PSN__W 3 -#define B_FE_AG_REG_PDC_JMP_PSN__M 0x7 -#define B_FE_AG_REG_PDC_JMP_PSN_INIT 0x0 - #define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048 -#define B_FE_AG_REG_PDC_FLA_STP__W 16 -#define B_FE_AG_REG_PDC_FLA_STP__M 0xFFFF -#define B_FE_AG_REG_PDC_FLA_STP_INIT 0x0 - #define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049 -#define B_FE_AG_REG_PDC_SLO_STP__W 16 -#define B_FE_AG_REG_PDC_SLO_STP__M 0xFFFF -#define B_FE_AG_REG_PDC_SLO_STP_INIT 0x1 - #define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A -#define B_FE_AG_REG_PDC_PD2_WRI__W 6 -#define B_FE_AG_REG_PDC_PD2_WRI__M 0x3F -#define B_FE_AG_REG_PDC_PD2_WRI_INIT 0x1F - #define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B -#define B_FE_AG_REG_PDC_MAP_DAT__W 6 -#define B_FE_AG_REG_PDC_MAP_DAT__M 0x3F - #define B_FE_AG_REG_PDC_MAX__A 0xC2004C -#define B_FE_AG_REG_PDC_MAX__W 6 -#define B_FE_AG_REG_PDC_MAX__M 0x3F -#define B_FE_AG_REG_PDC_MAX_INIT 0x2 - #define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D -#define B_FE_AG_REG_TGA_AUR_CNT__W 5 -#define B_FE_AG_REG_TGA_AUR_CNT__M 0x1F -#define B_FE_AG_REG_TGA_AUR_CNT_INIT 0x10 - #define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E -#define B_FE_AG_REG_TGA_RUR_CNT__W 5 -#define B_FE_AG_REG_TGA_RUR_CNT__M 0x1F -#define B_FE_AG_REG_TGA_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F -#define B_FE_AG_REG_TGA_AVE_DAT__W 6 -#define B_FE_AG_REG_TGA_AVE_DAT__M 0x3F - #define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050 -#define B_FE_AG_REG_TGC_RUR_CNT__W 5 -#define B_FE_AG_REG_TGC_RUR_CNT__M 0x1F -#define B_FE_AG_REG_TGC_RUR_CNT_INIT 0x0 - #define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051 -#define B_FE_AG_REG_TGC_SET_LVL__W 6 #define B_FE_AG_REG_TGC_SET_LVL__M 0x3F -#define B_FE_AG_REG_TGC_SET_LVL_INIT 0x18 - #define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052 -#define B_FE_AG_REG_TGC_FLA_RGN__W 6 -#define B_FE_AG_REG_TGC_FLA_RGN__M 0x3F -#define B_FE_AG_REG_TGC_FLA_RGN_INIT 0x0 - #define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053 -#define B_FE_AG_REG_TGC_JMP_PSN__W 4 -#define B_FE_AG_REG_TGC_JMP_PSN__M 0xF -#define B_FE_AG_REG_TGC_JMP_PSN_INIT 0x0 - #define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054 -#define B_FE_AG_REG_TGC_FLA_STP__W 16 -#define B_FE_AG_REG_TGC_FLA_STP__M 0xFFFF -#define B_FE_AG_REG_TGC_FLA_STP_INIT 0x0 - #define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055 -#define B_FE_AG_REG_TGC_SLO_STP__W 16 -#define B_FE_AG_REG_TGC_SLO_STP__M 0xFFFF -#define B_FE_AG_REG_TGC_SLO_STP_INIT 0x1 - #define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056 -#define B_FE_AG_REG_TGC_MAP_DAT__W 10 -#define B_FE_AG_REG_TGC_MAP_DAT__M 0x3FF - #define B_FE_AG_REG_FGM_WRI__A 0xC20061 -#define B_FE_AG_REG_FGM_WRI__W 10 -#define B_FE_AG_REG_FGM_WRI__M 0x3FF -#define B_FE_AG_REG_FGM_WRI_INIT 0x80 - #define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068 -#define B_FE_AG_REG_BGC_FGC_WRI__W 4 -#define B_FE_AG_REG_BGC_FGC_WRI__M 0xF -#define B_FE_AG_REG_BGC_FGC_WRI_INIT 0x0 - #define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069 -#define B_FE_AG_REG_BGC_CGC_WRI__W 2 -#define B_FE_AG_REG_BGC_CGC_WRI__M 0x3 -#define B_FE_AG_REG_BGC_CGC_WRI_INIT 0x0 - -#define B_FE_AG_REG_BGC_THD_LVL__A 0xC2006B -#define B_FE_AG_REG_BGC_THD_LVL__W 4 -#define B_FE_AG_REG_BGC_THD_LVL__M 0xF -#define B_FE_AG_REG_BGC_THD_LVL_INIT 0xF - -#define B_FE_AG_REG_BGC_THD_INC__A 0xC2006C -#define B_FE_AG_REG_BGC_THD_INC__W 4 -#define B_FE_AG_REG_BGC_THD_INC__M 0xF -#define B_FE_AG_REG_BGC_THD_INC_INIT 0x8 - -#define B_FE_AG_REG_BGC_DAT__A 0xC2006D -#define B_FE_AG_REG_BGC_DAT__W 4 -#define B_FE_AG_REG_BGC_DAT__M 0xF - -#define B_FE_AG_REG_IND_PD1_COM__A 0xC2006E -#define B_FE_AG_REG_IND_PD1_COM__W 6 -#define B_FE_AG_REG_IND_PD1_COM__M 0x3F -#define B_FE_AG_REG_IND_PD1_COM_INIT 0x7 - -#define B_FE_AG_REG_AG_AGC_BUF__A 0xC2006F -#define B_FE_AG_REG_AG_AGC_BUF__W 2 -#define B_FE_AG_REG_AG_AGC_BUF__M 0x3 -#define B_FE_AG_REG_AG_AGC_BUF_INIT 0x3 - -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__B 0 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__W 1 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__M 0x1 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_SLOW 0x0 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_FAST 0x1 - -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__B 1 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__W 1 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__M 0x2 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_SLOW 0x0 -#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_FAST 0x2 - -#define B_FE_AG_REG_PMX_SPE__A 0xC20070 -#define B_FE_AG_REG_PMX_SPE__W 3 -#define B_FE_AG_REG_PMX_SPE__M 0x7 -#define B_FE_AG_REG_PMX_SPE_INIT 0x1 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_1 0x0 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_2 0x1 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_3 0x2 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_4 0x3 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_5 0x4 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_6 0x5 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_7 0x6 -#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_8 0x7 - -#define B_FE_FS_SID 0x3 - #define B_FE_FS_REG_COMM_EXEC__A 0xC30000 -#define B_FE_FS_REG_COMM_EXEC__W 3 -#define B_FE_FS_REG_COMM_EXEC__M 0x7 -#define B_FE_FS_REG_COMM_EXEC_CTL__B 0 -#define B_FE_FS_REG_COMM_EXEC_CTL__W 3 -#define B_FE_FS_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_FS_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_FS_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_FS_REG_COMM_STATE__A 0xC30001 -#define B_FE_FS_REG_COMM_STATE__W 4 -#define B_FE_FS_REG_COMM_STATE__M 0xF - -#define B_FE_FS_REG_COMM_MB__A 0xC30002 -#define B_FE_FS_REG_COMM_MB__W 3 -#define B_FE_FS_REG_COMM_MB__M 0x7 -#define B_FE_FS_REG_COMM_MB_CTR__B 0 -#define B_FE_FS_REG_COMM_MB_CTR__W 1 -#define B_FE_FS_REG_COMM_MB_CTR__M 0x1 -#define B_FE_FS_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_FS_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_FS_REG_COMM_MB_OBS__B 1 -#define B_FE_FS_REG_COMM_MB_OBS__W 1 -#define B_FE_FS_REG_COMM_MB_OBS__M 0x2 -#define B_FE_FS_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_FS_REG_COMM_MB_OBS_ON 0x2 -#define B_FE_FS_REG_COMM_MB_MUX__B 2 -#define B_FE_FS_REG_COMM_MB_MUX__W 1 -#define B_FE_FS_REG_COMM_MB_MUX__M 0x4 -#define B_FE_FS_REG_COMM_MB_MUX_REAL 0x0 -#define B_FE_FS_REG_COMM_MB_MUX_IMAG 0x4 - -#define B_FE_FS_REG_COMM_SERVICE0__A 0xC30003 -#define B_FE_FS_REG_COMM_SERVICE0__W 10 -#define B_FE_FS_REG_COMM_SERVICE0__M 0x3FF - -#define B_FE_FS_REG_COMM_SERVICE1__A 0xC30004 -#define B_FE_FS_REG_COMM_SERVICE1__W 11 -#define B_FE_FS_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_FS_REG_COMM_ACT__A 0xC30005 -#define B_FE_FS_REG_COMM_ACT__W 2 -#define B_FE_FS_REG_COMM_ACT__M 0x3 - -#define B_FE_FS_REG_COMM_CNT__A 0xC30006 -#define B_FE_FS_REG_COMM_CNT__W 16 -#define B_FE_FS_REG_COMM_CNT__M 0xFFFF - #define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010 -#define B_FE_FS_REG_ADD_INC_LOP__W 16 -#define B_FE_FS_REG_ADD_INC_LOP__M 0xFFFF -#define B_FE_FS_REG_ADD_INC_LOP_INIT 0x0 - -#define B_FE_FS_REG_ADD_INC_HIP__A 0xC30011 -#define B_FE_FS_REG_ADD_INC_HIP__W 12 -#define B_FE_FS_REG_ADD_INC_HIP__M 0xFFF -#define B_FE_FS_REG_ADD_INC_HIP_INIT 0xC00 - -#define B_FE_FS_REG_ADD_OFF__A 0xC30012 -#define B_FE_FS_REG_ADD_OFF__W 12 -#define B_FE_FS_REG_ADD_OFF__M 0xFFF -#define B_FE_FS_REG_ADD_OFF_INIT 0x0 - -#define B_FE_FS_REG_ADD_OFF_VAL__A 0xC30013 -#define B_FE_FS_REG_ADD_OFF_VAL__W 1 -#define B_FE_FS_REG_ADD_OFF_VAL__M 0x1 -#define B_FE_FS_REG_ADD_OFF_VAL_INIT 0x0 - -#define B_FE_FD_SID 0x4 - #define B_FE_FD_REG_COMM_EXEC__A 0xC40000 -#define B_FE_FD_REG_COMM_EXEC__W 3 -#define B_FE_FD_REG_COMM_EXEC__M 0x7 -#define B_FE_FD_REG_COMM_EXEC_CTL__B 0 -#define B_FE_FD_REG_COMM_EXEC_CTL__W 3 -#define B_FE_FD_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_FD_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_FD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_FD_REG_COMM_MB__A 0xC40002 -#define B_FE_FD_REG_COMM_MB__W 3 -#define B_FE_FD_REG_COMM_MB__M 0x7 -#define B_FE_FD_REG_COMM_MB_CTR__B 0 -#define B_FE_FD_REG_COMM_MB_CTR__W 1 -#define B_FE_FD_REG_COMM_MB_CTR__M 0x1 -#define B_FE_FD_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_FD_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_FD_REG_COMM_MB_OBS__B 1 -#define B_FE_FD_REG_COMM_MB_OBS__W 1 -#define B_FE_FD_REG_COMM_MB_OBS__M 0x2 -#define B_FE_FD_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_FD_REG_COMM_MB_OBS_ON 0x2 - -#define B_FE_FD_REG_COMM_SERVICE0__A 0xC40003 -#define B_FE_FD_REG_COMM_SERVICE0__W 10 -#define B_FE_FD_REG_COMM_SERVICE0__M 0x3FF -#define B_FE_FD_REG_COMM_SERVICE1__A 0xC40004 -#define B_FE_FD_REG_COMM_SERVICE1__W 11 -#define B_FE_FD_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_FD_REG_COMM_INT_STA__A 0xC40007 -#define B_FE_FD_REG_COMM_INT_STA__W 1 -#define B_FE_FD_REG_COMM_INT_STA__M 0x1 -#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define B_FE_FD_REG_COMM_INT_MSK__A 0xC40008 -#define B_FE_FD_REG_COMM_INT_MSK__W 1 -#define B_FE_FD_REG_COMM_INT_MSK__M 0x1 -#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - #define B_FE_FD_REG_SCL__A 0xC40010 -#define B_FE_FD_REG_SCL__W 6 -#define B_FE_FD_REG_SCL__M 0x3F - #define B_FE_FD_REG_MAX_LEV__A 0xC40011 -#define B_FE_FD_REG_MAX_LEV__W 3 -#define B_FE_FD_REG_MAX_LEV__M 0x7 - #define B_FE_FD_REG_NR__A 0xC40012 -#define B_FE_FD_REG_NR__W 5 -#define B_FE_FD_REG_NR__M 0x1F - -#define B_FE_FD_REG_MEAS_SEL__A 0xC40013 -#define B_FE_FD_REG_MEAS_SEL__W 1 -#define B_FE_FD_REG_MEAS_SEL__M 0x1 - #define B_FE_FD_REG_MEAS_VAL__A 0xC40014 -#define B_FE_FD_REG_MEAS_VAL__W 1 -#define B_FE_FD_REG_MEAS_VAL__M 0x1 - -#define B_FE_FD_REG_MAX__A 0xC40015 -#define B_FE_FD_REG_MAX__W 16 -#define B_FE_FD_REG_MAX__M 0xFFFF - -#define B_FE_IF_SID 0x5 - #define B_FE_IF_REG_COMM_EXEC__A 0xC50000 -#define B_FE_IF_REG_COMM_EXEC__W 3 -#define B_FE_IF_REG_COMM_EXEC__M 0x7 -#define B_FE_IF_REG_COMM_EXEC_CTL__B 0 -#define B_FE_IF_REG_COMM_EXEC_CTL__W 3 -#define B_FE_IF_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_IF_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_IF_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_IF_REG_COMM_MB__A 0xC50002 -#define B_FE_IF_REG_COMM_MB__W 3 -#define B_FE_IF_REG_COMM_MB__M 0x7 -#define B_FE_IF_REG_COMM_MB_CTR__B 0 -#define B_FE_IF_REG_COMM_MB_CTR__W 1 -#define B_FE_IF_REG_COMM_MB_CTR__M 0x1 -#define B_FE_IF_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_IF_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_IF_REG_COMM_MB_OBS__B 1 -#define B_FE_IF_REG_COMM_MB_OBS__W 1 -#define B_FE_IF_REG_COMM_MB_OBS__M 0x2 -#define B_FE_IF_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_IF_REG_COMM_MB_OBS_ON 0x2 - #define B_FE_IF_REG_INCR0__A 0xC50010 #define B_FE_IF_REG_INCR0__W 16 #define B_FE_IF_REG_INCR0__M 0xFFFF -#define B_FE_IF_REG_INCR0_INIT 0x0 - #define B_FE_IF_REG_INCR1__A 0xC50011 -#define B_FE_IF_REG_INCR1__W 8 #define B_FE_IF_REG_INCR1__M 0xFF -#define B_FE_IF_REG_INCR1_INIT 0x28 - -#define B_FE_CF_SID 0x6 - #define B_FE_CF_REG_COMM_EXEC__A 0xC60000 -#define B_FE_CF_REG_COMM_EXEC__W 3 -#define B_FE_CF_REG_COMM_EXEC__M 0x7 -#define B_FE_CF_REG_COMM_EXEC_CTL__B 0 -#define B_FE_CF_REG_COMM_EXEC_CTL__W 3 -#define B_FE_CF_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_CF_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_CF_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_CF_REG_COMM_MB__A 0xC60002 -#define B_FE_CF_REG_COMM_MB__W 3 -#define B_FE_CF_REG_COMM_MB__M 0x7 -#define B_FE_CF_REG_COMM_MB_CTR__B 0 -#define B_FE_CF_REG_COMM_MB_CTR__W 1 -#define B_FE_CF_REG_COMM_MB_CTR__M 0x1 -#define B_FE_CF_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_CF_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_CF_REG_COMM_MB_OBS__B 1 -#define B_FE_CF_REG_COMM_MB_OBS__W 1 -#define B_FE_CF_REG_COMM_MB_OBS__M 0x2 -#define B_FE_CF_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_CF_REG_COMM_MB_OBS_ON 0x2 - -#define B_FE_CF_REG_COMM_SERVICE0__A 0xC60003 -#define B_FE_CF_REG_COMM_SERVICE0__W 10 -#define B_FE_CF_REG_COMM_SERVICE0__M 0x3FF -#define B_FE_CF_REG_COMM_SERVICE1__A 0xC60004 -#define B_FE_CF_REG_COMM_SERVICE1__W 11 -#define B_FE_CF_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_CF_REG_COMM_INT_STA__A 0xC60007 -#define B_FE_CF_REG_COMM_INT_STA__W 2 -#define B_FE_CF_REG_COMM_INT_STA__M 0x3 -#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define B_FE_CF_REG_COMM_INT_MSK__A 0xC60008 -#define B_FE_CF_REG_COMM_INT_MSK__W 2 -#define B_FE_CF_REG_COMM_INT_MSK__M 0x3 -#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - #define B_FE_CF_REG_SCL__A 0xC60010 -#define B_FE_CF_REG_SCL__W 9 -#define B_FE_CF_REG_SCL__M 0x1FF - #define B_FE_CF_REG_MAX_LEV__A 0xC60011 -#define B_FE_CF_REG_MAX_LEV__W 3 -#define B_FE_CF_REG_MAX_LEV__M 0x7 - #define B_FE_CF_REG_NR__A 0xC60012 -#define B_FE_CF_REG_NR__W 5 -#define B_FE_CF_REG_NR__M 0x1F - #define B_FE_CF_REG_IMP_VAL__A 0xC60013 -#define B_FE_CF_REG_IMP_VAL__W 1 -#define B_FE_CF_REG_IMP_VAL__M 0x1 - #define B_FE_CF_REG_MEAS_VAL__A 0xC60014 -#define B_FE_CF_REG_MEAS_VAL__W 1 -#define B_FE_CF_REG_MEAS_VAL__M 0x1 - -#define B_FE_CF_REG_MAX__A 0xC60015 -#define B_FE_CF_REG_MAX__W 16 -#define B_FE_CF_REG_MAX__M 0xFFFF - -#define B_FE_CU_SID 0x7 - #define B_FE_CU_REG_COMM_EXEC__A 0xC70000 -#define B_FE_CU_REG_COMM_EXEC__W 3 -#define B_FE_CU_REG_COMM_EXEC__M 0x7 -#define B_FE_CU_REG_COMM_EXEC_CTL__B 0 -#define B_FE_CU_REG_COMM_EXEC_CTL__W 3 -#define B_FE_CU_REG_COMM_EXEC_CTL__M 0x7 -#define B_FE_CU_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FE_CU_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FE_CU_REG_COMM_STATE__A 0xC70001 -#define B_FE_CU_REG_COMM_STATE__W 4 -#define B_FE_CU_REG_COMM_STATE__M 0xF - -#define B_FE_CU_REG_COMM_MB__A 0xC70002 -#define B_FE_CU_REG_COMM_MB__W 3 -#define B_FE_CU_REG_COMM_MB__M 0x7 -#define B_FE_CU_REG_COMM_MB_CTR__B 0 -#define B_FE_CU_REG_COMM_MB_CTR__W 1 -#define B_FE_CU_REG_COMM_MB_CTR__M 0x1 -#define B_FE_CU_REG_COMM_MB_CTR_OFF 0x0 -#define B_FE_CU_REG_COMM_MB_CTR_ON 0x1 -#define B_FE_CU_REG_COMM_MB_OBS__B 1 -#define B_FE_CU_REG_COMM_MB_OBS__W 1 -#define B_FE_CU_REG_COMM_MB_OBS__M 0x2 -#define B_FE_CU_REG_COMM_MB_OBS_OFF 0x0 -#define B_FE_CU_REG_COMM_MB_OBS_ON 0x2 -#define B_FE_CU_REG_COMM_MB_MUX__B 2 -#define B_FE_CU_REG_COMM_MB_MUX__W 1 -#define B_FE_CU_REG_COMM_MB_MUX__M 0x4 -#define B_FE_CU_REG_COMM_MB_MUX_REAL 0x0 -#define B_FE_CU_REG_COMM_MB_MUX_IMAG 0x4 - -#define B_FE_CU_REG_COMM_SERVICE0__A 0xC70003 -#define B_FE_CU_REG_COMM_SERVICE0__W 10 -#define B_FE_CU_REG_COMM_SERVICE0__M 0x3FF - -#define B_FE_CU_REG_COMM_SERVICE1__A 0xC70004 -#define B_FE_CU_REG_COMM_SERVICE1__W 11 -#define B_FE_CU_REG_COMM_SERVICE1__M 0x7FF - -#define B_FE_CU_REG_COMM_ACT__A 0xC70005 -#define B_FE_CU_REG_COMM_ACT__W 2 -#define B_FE_CU_REG_COMM_ACT__M 0x3 - -#define B_FE_CU_REG_COMM_CNT__A 0xC70006 -#define B_FE_CU_REG_COMM_CNT__W 16 -#define B_FE_CU_REG_COMM_CNT__M 0xFFFF - -#define B_FE_CU_REG_COMM_INT_STA__A 0xC70007 -#define B_FE_CU_REG_COMM_INT_STA__W 4 -#define B_FE_CU_REG_COMM_INT_STA__M 0xF -#define B_FE_CU_REG_COMM_INT_STA_FE_START__B 0 -#define B_FE_CU_REG_COMM_INT_STA_FE_START__W 1 -#define B_FE_CU_REG_COMM_INT_STA_FE_START__M 0x1 -#define B_FE_CU_REG_COMM_INT_STA_FT_START__B 1 -#define B_FE_CU_REG_COMM_INT_STA_FT_START__W 1 -#define B_FE_CU_REG_COMM_INT_STA_FT_START__M 0x2 -#define B_FE_CU_REG_COMM_INT_STA_SB_START__B 2 -#define B_FE_CU_REG_COMM_INT_STA_SB_START__W 1 -#define B_FE_CU_REG_COMM_INT_STA_SB_START__M 0x4 -#define B_FE_CU_REG_COMM_INT_STA_NF_READY__B 3 -#define B_FE_CU_REG_COMM_INT_STA_NF_READY__W 1 -#define B_FE_CU_REG_COMM_INT_STA_NF_READY__M 0x8 - -#define B_FE_CU_REG_COMM_INT_MSK__A 0xC70008 -#define B_FE_CU_REG_COMM_INT_MSK__W 4 -#define B_FE_CU_REG_COMM_INT_MSK__M 0xF -#define B_FE_CU_REG_COMM_INT_MSK_FE_START__B 0 -#define B_FE_CU_REG_COMM_INT_MSK_FE_START__W 1 -#define B_FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1 -#define B_FE_CU_REG_COMM_INT_MSK_FT_START__B 1 -#define B_FE_CU_REG_COMM_INT_MSK_FT_START__W 1 -#define B_FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2 -#define B_FE_CU_REG_COMM_INT_MSK_SB_START__B 2 -#define B_FE_CU_REG_COMM_INT_MSK_SB_START__W 1 -#define B_FE_CU_REG_COMM_INT_MSK_SB_START__M 0x4 -#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__B 3 -#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__W 1 -#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__M 0x8 - -#define B_FE_CU_REG_MODE__A 0xC70010 -#define B_FE_CU_REG_MODE__W 5 -#define B_FE_CU_REG_MODE__M 0x1F -#define B_FE_CU_REG_MODE_INIT 0x0 - -#define B_FE_CU_REG_MODE_FFT__B 0 -#define B_FE_CU_REG_MODE_FFT__W 1 -#define B_FE_CU_REG_MODE_FFT__M 0x1 -#define B_FE_CU_REG_MODE_FFT_M8K 0x0 -#define B_FE_CU_REG_MODE_FFT_M2K 0x1 - -#define B_FE_CU_REG_MODE_COR__B 1 -#define B_FE_CU_REG_MODE_COR__W 1 -#define B_FE_CU_REG_MODE_COR__M 0x2 -#define B_FE_CU_REG_MODE_COR_OFF 0x0 -#define B_FE_CU_REG_MODE_COR_ON 0x2 - -#define B_FE_CU_REG_MODE_IFD__B 2 -#define B_FE_CU_REG_MODE_IFD__W 1 -#define B_FE_CU_REG_MODE_IFD__M 0x4 -#define B_FE_CU_REG_MODE_IFD_ENABLE 0x0 -#define B_FE_CU_REG_MODE_IFD_DISABLE 0x4 - -#define B_FE_CU_REG_MODE_SEL__B 3 -#define B_FE_CU_REG_MODE_SEL__W 1 -#define B_FE_CU_REG_MODE_SEL__M 0x8 -#define B_FE_CU_REG_MODE_SEL_COR 0x0 -#define B_FE_CU_REG_MODE_SEL_COR_NFC 0x8 - -#define B_FE_CU_REG_MODE_FES__B 4 -#define B_FE_CU_REG_MODE_FES__W 1 -#define B_FE_CU_REG_MODE_FES__M 0x10 -#define B_FE_CU_REG_MODE_FES_SEL_RST 0x0 -#define B_FE_CU_REG_MODE_FES_SEL_UPD 0x10 - #define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011 -#define B_FE_CU_REG_FRM_CNT_RST__W 15 -#define B_FE_CU_REG_FRM_CNT_RST__M 0x7FFF -#define B_FE_CU_REG_FRM_CNT_RST_INIT 0x20FF - #define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012 -#define B_FE_CU_REG_FRM_CNT_STR__W 15 -#define B_FE_CU_REG_FRM_CNT_STR__M 0x7FFF -#define B_FE_CU_REG_FRM_CNT_STR_INIT 0x1E - -#define B_FE_CU_REG_FRM_SMP_CNT__A 0xC70013 -#define B_FE_CU_REG_FRM_SMP_CNT__W 15 -#define B_FE_CU_REG_FRM_SMP_CNT__M 0x7FFF - -#define B_FE_CU_REG_FRM_SMB_CNT__A 0xC70014 -#define B_FE_CU_REG_FRM_SMB_CNT__W 16 -#define B_FE_CU_REG_FRM_SMB_CNT__M 0xFFFF - -#define B_FE_CU_REG_CMP_MAX_DAT__A 0xC70015 -#define B_FE_CU_REG_CMP_MAX_DAT__W 12 -#define B_FE_CU_REG_CMP_MAX_DAT__M 0xFFF - -#define B_FE_CU_REG_CMP_MAX_ADR__A 0xC70016 -#define B_FE_CU_REG_CMP_MAX_ADR__W 10 -#define B_FE_CU_REG_CMP_MAX_ADR__M 0x3FF - -#define B_FE_CU_REG_BUF_NFC_DEL__A 0xC7001F -#define B_FE_CU_REG_BUF_NFC_DEL__W 14 -#define B_FE_CU_REG_BUF_NFC_DEL__M 0x3FFF -#define B_FE_CU_REG_BUF_NFC_DEL_INIT 0x0 - #define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020 -#define B_FE_CU_REG_CTR_NFC_ICR__W 5 -#define B_FE_CU_REG_CTR_NFC_ICR__M 0x1F -#define B_FE_CU_REG_CTR_NFC_ICR_INIT 0x0 - #define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021 -#define B_FE_CU_REG_CTR_NFC_OCR__W 15 -#define B_FE_CU_REG_CTR_NFC_OCR__M 0x7FFF -#define B_FE_CU_REG_CTR_NFC_OCR_INIT 0x61A8 - -#define B_FE_CU_REG_CTR_NFC_CNT__A 0xC70022 -#define B_FE_CU_REG_CTR_NFC_CNT__W 15 -#define B_FE_CU_REG_CTR_NFC_CNT__M 0x7FFF - -#define B_FE_CU_REG_CTR_NFC_STS__A 0xC70023 -#define B_FE_CU_REG_CTR_NFC_STS__W 3 -#define B_FE_CU_REG_CTR_NFC_STS__M 0x7 -#define B_FE_CU_REG_CTR_NFC_STS_RUN 0x0 -#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_IMA 0x1 -#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_REA 0x2 -#define B_FE_CU_REG_CTR_NFC_STS_CNT_MAX 0x4 - -#define B_FE_CU_REG_DIV_NFC_REA__A 0xC70024 -#define B_FE_CU_REG_DIV_NFC_REA__W 14 -#define B_FE_CU_REG_DIV_NFC_REA__M 0x3FFF - -#define B_FE_CU_REG_DIV_NFC_IMA__A 0xC70025 -#define B_FE_CU_REG_DIV_NFC_IMA__W 14 -#define B_FE_CU_REG_DIV_NFC_IMA__M 0x3FFF - -#define B_FE_CU_REG_FRM_CNT_UPD__A 0xC70026 -#define B_FE_CU_REG_FRM_CNT_UPD__W 15 -#define B_FE_CU_REG_FRM_CNT_UPD__M 0x7FFF -#define B_FE_CU_REG_FRM_CNT_UPD_INIT 0x20FF - #define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027 -#define B_FE_CU_REG_DIV_NFC_CLP__W 2 -#define B_FE_CU_REG_DIV_NFC_CLP__M 0x3 -#define B_FE_CU_REG_DIV_NFC_CLP_INIT 0x1 -#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S11 0x0 -#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S12 0x1 -#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S13 0x2 -#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S14 0x3 - -#define B_FE_CU_BUF_RAM__A 0xC80000 - -#define B_FE_CU_CMP_RAM__A 0xC90000 - -#define B_FT_SID 0x8 - #define B_FT_COMM_EXEC__A 0x1000000 -#define B_FT_COMM_EXEC__W 3 -#define B_FT_COMM_EXEC__M 0x7 -#define B_FT_COMM_EXEC_CTL__B 0 -#define B_FT_COMM_EXEC_CTL__W 3 -#define B_FT_COMM_EXEC_CTL__M 0x7 -#define B_FT_COMM_EXEC_CTL_STOP 0x0 -#define B_FT_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FT_COMM_EXEC_CTL_HOLD 0x2 -#define B_FT_COMM_EXEC_CTL_STEP 0x3 -#define B_FT_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_FT_COMM_STATE__A 0x1000001 -#define B_FT_COMM_STATE__W 16 -#define B_FT_COMM_STATE__M 0xFFFF -#define B_FT_COMM_MB__A 0x1000002 -#define B_FT_COMM_MB__W 16 -#define B_FT_COMM_MB__M 0xFFFF -#define B_FT_COMM_SERVICE0__A 0x1000003 -#define B_FT_COMM_SERVICE0__W 16 -#define B_FT_COMM_SERVICE0__M 0xFFFF -#define B_FT_COMM_SERVICE1__A 0x1000004 -#define B_FT_COMM_SERVICE1__W 16 -#define B_FT_COMM_SERVICE1__M 0xFFFF -#define B_FT_COMM_INT_STA__A 0x1000007 -#define B_FT_COMM_INT_STA__W 16 -#define B_FT_COMM_INT_STA__M 0xFFFF -#define B_FT_COMM_INT_MSK__A 0x1000008 -#define B_FT_COMM_INT_MSK__W 16 -#define B_FT_COMM_INT_MSK__M 0xFFFF - #define B_FT_REG_COMM_EXEC__A 0x1010000 -#define B_FT_REG_COMM_EXEC__W 3 -#define B_FT_REG_COMM_EXEC__M 0x7 -#define B_FT_REG_COMM_EXEC_CTL__B 0 -#define B_FT_REG_COMM_EXEC_CTL__W 3 -#define B_FT_REG_COMM_EXEC_CTL__M 0x7 -#define B_FT_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_FT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_FT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_FT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_FT_REG_COMM_MB__A 0x1010002 -#define B_FT_REG_COMM_MB__W 3 -#define B_FT_REG_COMM_MB__M 0x7 -#define B_FT_REG_COMM_MB_CTR__B 0 -#define B_FT_REG_COMM_MB_CTR__W 1 -#define B_FT_REG_COMM_MB_CTR__M 0x1 -#define B_FT_REG_COMM_MB_CTR_OFF 0x0 -#define B_FT_REG_COMM_MB_CTR_ON 0x1 -#define B_FT_REG_COMM_MB_OBS__B 1 -#define B_FT_REG_COMM_MB_OBS__W 1 -#define B_FT_REG_COMM_MB_OBS__M 0x2 -#define B_FT_REG_COMM_MB_OBS_OFF 0x0 -#define B_FT_REG_COMM_MB_OBS_ON 0x2 - -#define B_FT_REG_MODE_2K__A 0x1010010 -#define B_FT_REG_MODE_2K__W 1 -#define B_FT_REG_MODE_2K__M 0x1 -#define B_FT_REG_MODE_2K_MODE_8K 0x0 -#define B_FT_REG_MODE_2K_MODE_2K 0x1 -#define B_FT_REG_MODE_2K_INIT 0x0 - -#define B_FT_REG_NORM_OFF__A 0x1010016 -#define B_FT_REG_NORM_OFF__W 4 -#define B_FT_REG_NORM_OFF__M 0xF -#define B_FT_REG_NORM_OFF_INIT 0x2 - -#define B_FT_ST1_RAM__A 0x1020000 - -#define B_FT_ST2_RAM__A 0x1030000 - -#define B_FT_ST3_RAM__A 0x1040000 - -#define B_FT_ST5_RAM__A 0x1050000 - -#define B_FT_ST6_RAM__A 0x1060000 - -#define B_FT_ST8_RAM__A 0x1070000 - -#define B_FT_ST9_RAM__A 0x1080000 - -#define B_CP_SID 0x9 - #define B_CP_COMM_EXEC__A 0x1400000 -#define B_CP_COMM_EXEC__W 3 -#define B_CP_COMM_EXEC__M 0x7 -#define B_CP_COMM_EXEC_CTL__B 0 -#define B_CP_COMM_EXEC_CTL__W 3 -#define B_CP_COMM_EXEC_CTL__M 0x7 -#define B_CP_COMM_EXEC_CTL_STOP 0x0 -#define B_CP_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CP_COMM_EXEC_CTL_HOLD 0x2 -#define B_CP_COMM_EXEC_CTL_STEP 0x3 -#define B_CP_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_CP_COMM_STATE__A 0x1400001 -#define B_CP_COMM_STATE__W 16 -#define B_CP_COMM_STATE__M 0xFFFF -#define B_CP_COMM_MB__A 0x1400002 -#define B_CP_COMM_MB__W 16 -#define B_CP_COMM_MB__M 0xFFFF -#define B_CP_COMM_SERVICE0__A 0x1400003 -#define B_CP_COMM_SERVICE0__W 16 -#define B_CP_COMM_SERVICE0__M 0xFFFF -#define B_CP_COMM_SERVICE1__A 0x1400004 -#define B_CP_COMM_SERVICE1__W 16 -#define B_CP_COMM_SERVICE1__M 0xFFFF -#define B_CP_COMM_INT_STA__A 0x1400007 -#define B_CP_COMM_INT_STA__W 16 -#define B_CP_COMM_INT_STA__M 0xFFFF -#define B_CP_COMM_INT_MSK__A 0x1400008 -#define B_CP_COMM_INT_MSK__W 16 -#define B_CP_COMM_INT_MSK__M 0xFFFF - #define B_CP_REG_COMM_EXEC__A 0x1410000 -#define B_CP_REG_COMM_EXEC__W 3 -#define B_CP_REG_COMM_EXEC__M 0x7 -#define B_CP_REG_COMM_EXEC_CTL__B 0 -#define B_CP_REG_COMM_EXEC_CTL__W 3 -#define B_CP_REG_COMM_EXEC_CTL__M 0x7 -#define B_CP_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_CP_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CP_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_CP_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_CP_REG_COMM_MB__A 0x1410002 -#define B_CP_REG_COMM_MB__W 3 -#define B_CP_REG_COMM_MB__M 0x7 -#define B_CP_REG_COMM_MB_CTR__B 0 -#define B_CP_REG_COMM_MB_CTR__W 1 -#define B_CP_REG_COMM_MB_CTR__M 0x1 -#define B_CP_REG_COMM_MB_CTR_OFF 0x0 -#define B_CP_REG_COMM_MB_CTR_ON 0x1 -#define B_CP_REG_COMM_MB_OBS__B 1 -#define B_CP_REG_COMM_MB_OBS__W 1 -#define B_CP_REG_COMM_MB_OBS__M 0x2 -#define B_CP_REG_COMM_MB_OBS_OFF 0x0 -#define B_CP_REG_COMM_MB_OBS_ON 0x2 - -#define B_CP_REG_COMM_SERVICE0__A 0x1410003 -#define B_CP_REG_COMM_SERVICE0__W 10 -#define B_CP_REG_COMM_SERVICE0__M 0x3FF -#define B_CP_REG_COMM_SERVICE0_CP__B 9 -#define B_CP_REG_COMM_SERVICE0_CP__W 1 -#define B_CP_REG_COMM_SERVICE0_CP__M 0x200 - -#define B_CP_REG_COMM_SERVICE1__A 0x1410004 -#define B_CP_REG_COMM_SERVICE1__W 11 -#define B_CP_REG_COMM_SERVICE1__M 0x7FF - -#define B_CP_REG_COMM_INT_STA__A 0x1410007 -#define B_CP_REG_COMM_INT_STA__W 2 -#define B_CP_REG_COMM_INT_STA__M 0x3 -#define B_CP_REG_COMM_INT_STA_NEW_MEAS__B 0 -#define B_CP_REG_COMM_INT_STA_NEW_MEAS__W 1 -#define B_CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1 - -#define B_CP_REG_COMM_INT_MSK__A 0x1410008 -#define B_CP_REG_COMM_INT_MSK__W 2 -#define B_CP_REG_COMM_INT_MSK__M 0x3 -#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__B 0 -#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__W 1 -#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1 - -#define B_CP_REG_MODE_2K__A 0x1410010 -#define B_CP_REG_MODE_2K__W 1 -#define B_CP_REG_MODE_2K__M 0x1 -#define B_CP_REG_MODE_2K_INIT 0x0 - #define B_CP_REG_INTERVAL__A 0x1410011 -#define B_CP_REG_INTERVAL__W 4 -#define B_CP_REG_INTERVAL__M 0xF -#define B_CP_REG_INTERVAL_INIT 0x5 - -#define B_CP_REG_DETECT_ENA__A 0x1410012 -#define B_CP_REG_DETECT_ENA__W 2 -#define B_CP_REG_DETECT_ENA__M 0x3 - -#define B_CP_REG_DETECT_ENA_SCATTERED__B 0 -#define B_CP_REG_DETECT_ENA_SCATTERED__W 1 -#define B_CP_REG_DETECT_ENA_SCATTERED__M 0x1 - -#define B_CP_REG_DETECT_ENA_CONTINUOUS__B 1 -#define B_CP_REG_DETECT_ENA_CONTINUOUS__W 1 -#define B_CP_REG_DETECT_ENA_CONTINUOUS__M 0x2 -#define B_CP_REG_DETECT_ENA_INIT 0x0 - -#define B_CP_REG_BR_SMB_NR__A 0x1410021 -#define B_CP_REG_BR_SMB_NR__W 4 -#define B_CP_REG_BR_SMB_NR__M 0xF - -#define B_CP_REG_BR_SMB_NR_SMB__B 0 -#define B_CP_REG_BR_SMB_NR_SMB__W 2 -#define B_CP_REG_BR_SMB_NR_SMB__M 0x3 - -#define B_CP_REG_BR_SMB_NR_VAL__B 2 -#define B_CP_REG_BR_SMB_NR_VAL__W 1 -#define B_CP_REG_BR_SMB_NR_VAL__M 0x4 - -#define B_CP_REG_BR_SMB_NR_OFFSET__B 3 -#define B_CP_REG_BR_SMB_NR_OFFSET__W 1 -#define B_CP_REG_BR_SMB_NR_OFFSET__M 0x8 -#define B_CP_REG_BR_SMB_NR_INIT 0x0 - -#define B_CP_REG_BR_CP_SMB_NR__A 0x1410022 -#define B_CP_REG_BR_CP_SMB_NR__W 2 -#define B_CP_REG_BR_CP_SMB_NR__M 0x3 -#define B_CP_REG_BR_CP_SMB_NR_INIT 0x0 - #define B_CP_REG_BR_SPL_OFFSET__A 0x1410023 -#define B_CP_REG_BR_SPL_OFFSET__W 3 -#define B_CP_REG_BR_SPL_OFFSET__M 0x7 -#define B_CP_REG_BR_SPL_OFFSET_INIT 0x0 - #define B_CP_REG_BR_STR_DEL__A 0x1410024 -#define B_CP_REG_BR_STR_DEL__W 10 -#define B_CP_REG_BR_STR_DEL__M 0x3FF -#define B_CP_REG_BR_STR_DEL_INIT 0xA - -#define B_CP_REG_BR_EXP_ADJ__A 0x1410025 -#define B_CP_REG_BR_EXP_ADJ__W 5 -#define B_CP_REG_BR_EXP_ADJ__M 0x1F -#define B_CP_REG_BR_EXP_ADJ_INIT 0x10 - #define B_CP_REG_RT_ANG_INC0__A 0x1410030 -#define B_CP_REG_RT_ANG_INC0__W 16 -#define B_CP_REG_RT_ANG_INC0__M 0xFFFF -#define B_CP_REG_RT_ANG_INC0_INIT 0x0 - #define B_CP_REG_RT_ANG_INC1__A 0x1410031 -#define B_CP_REG_RT_ANG_INC1__W 8 -#define B_CP_REG_RT_ANG_INC1__M 0xFF -#define B_CP_REG_RT_ANG_INC1_INIT 0x0 - -#define B_CP_REG_RT_SPD_EXP_MARG__A 0x1410032 -#define B_CP_REG_RT_SPD_EXP_MARG__W 5 -#define B_CP_REG_RT_SPD_EXP_MARG__M 0x1F -#define B_CP_REG_RT_SPD_EXP_MARG_INIT 0x5 - #define B_CP_REG_RT_DETECT_TRH__A 0x1410033 -#define B_CP_REG_RT_DETECT_TRH__W 2 -#define B_CP_REG_RT_DETECT_TRH__M 0x3 -#define B_CP_REG_RT_DETECT_TRH_INIT 0x3 - -#define B_CP_REG_RT_SPD_RELIABLE__A 0x1410034 -#define B_CP_REG_RT_SPD_RELIABLE__W 3 -#define B_CP_REG_RT_SPD_RELIABLE__M 0x7 -#define B_CP_REG_RT_SPD_RELIABLE_INIT 0x0 - -#define B_CP_REG_RT_SPD_DIRECTION__A 0x1410035 -#define B_CP_REG_RT_SPD_DIRECTION__W 1 -#define B_CP_REG_RT_SPD_DIRECTION__M 0x1 -#define B_CP_REG_RT_SPD_DIRECTION_INIT 0x0 - -#define B_CP_REG_RT_SPD_MOD__A 0x1410036 -#define B_CP_REG_RT_SPD_MOD__W 2 -#define B_CP_REG_RT_SPD_MOD__M 0x3 -#define B_CP_REG_RT_SPD_MOD_INIT 0x0 - -#define B_CP_REG_RT_SPD_SMB__A 0x1410037 -#define B_CP_REG_RT_SPD_SMB__W 2 -#define B_CP_REG_RT_SPD_SMB__M 0x3 -#define B_CP_REG_RT_SPD_SMB_INIT 0x0 - -#define B_CP_REG_RT_CPD_MODE__A 0x1410038 -#define B_CP_REG_RT_CPD_MODE__W 3 -#define B_CP_REG_RT_CPD_MODE__M 0x7 - -#define B_CP_REG_RT_CPD_MODE_MOD3__B 0 -#define B_CP_REG_RT_CPD_MODE_MOD3__W 2 -#define B_CP_REG_RT_CPD_MODE_MOD3__M 0x3 - -#define B_CP_REG_RT_CPD_MODE_ADD__B 2 -#define B_CP_REG_RT_CPD_MODE_ADD__W 1 -#define B_CP_REG_RT_CPD_MODE_ADD__M 0x4 -#define B_CP_REG_RT_CPD_MODE_INIT 0x0 - -#define B_CP_REG_RT_CPD_RELIABLE__A 0x1410039 -#define B_CP_REG_RT_CPD_RELIABLE__W 3 -#define B_CP_REG_RT_CPD_RELIABLE__M 0x7 -#define B_CP_REG_RT_CPD_RELIABLE_INIT 0x0 - -#define B_CP_REG_RT_CPD_BIN__A 0x141003A -#define B_CP_REG_RT_CPD_BIN__W 5 -#define B_CP_REG_RT_CPD_BIN__M 0x1F -#define B_CP_REG_RT_CPD_BIN_INIT 0x0 - -#define B_CP_REG_RT_CPD_MAX__A 0x141003B -#define B_CP_REG_RT_CPD_MAX__W 4 -#define B_CP_REG_RT_CPD_MAX__M 0xF -#define B_CP_REG_RT_CPD_MAX_INIT 0x0 - -#define B_CP_REG_RT_SUPR_VAL__A 0x141003C -#define B_CP_REG_RT_SUPR_VAL__W 2 -#define B_CP_REG_RT_SUPR_VAL__M 0x3 - -#define B_CP_REG_RT_SUPR_VAL_CE__B 0 -#define B_CP_REG_RT_SUPR_VAL_CE__W 1 -#define B_CP_REG_RT_SUPR_VAL_CE__M 0x1 - -#define B_CP_REG_RT_SUPR_VAL_DL__B 1 -#define B_CP_REG_RT_SUPR_VAL_DL__W 1 -#define B_CP_REG_RT_SUPR_VAL_DL__M 0x2 -#define B_CP_REG_RT_SUPR_VAL_INIT 0x0 - -#define B_CP_REG_RT_EXP_AVE__A 0x141003D -#define B_CP_REG_RT_EXP_AVE__W 5 -#define B_CP_REG_RT_EXP_AVE__M 0x1F -#define B_CP_REG_RT_EXP_AVE_INIT 0x0 - -#define B_CP_REG_RT_CPD_EXP_MARG__A 0x141003E -#define B_CP_REG_RT_CPD_EXP_MARG__W 5 -#define B_CP_REG_RT_CPD_EXP_MARG__M 0x1F -#define B_CP_REG_RT_CPD_EXP_MARG_INIT 0x3 - #define B_CP_REG_AC_NEXP_OFFS__A 0x1410040 -#define B_CP_REG_AC_NEXP_OFFS__W 8 -#define B_CP_REG_AC_NEXP_OFFS__M 0xFF -#define B_CP_REG_AC_NEXP_OFFS_INIT 0x0 - #define B_CP_REG_AC_AVER_POW__A 0x1410041 -#define B_CP_REG_AC_AVER_POW__W 8 -#define B_CP_REG_AC_AVER_POW__M 0xFF -#define B_CP_REG_AC_AVER_POW_INIT 0x5F - #define B_CP_REG_AC_MAX_POW__A 0x1410042 -#define B_CP_REG_AC_MAX_POW__W 8 -#define B_CP_REG_AC_MAX_POW__M 0xFF -#define B_CP_REG_AC_MAX_POW_INIT 0x7A - #define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043 -#define B_CP_REG_AC_WEIGHT_MAN__W 6 -#define B_CP_REG_AC_WEIGHT_MAN__M 0x3F -#define B_CP_REG_AC_WEIGHT_MAN_INIT 0x31 - #define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044 -#define B_CP_REG_AC_WEIGHT_EXP__W 5 -#define B_CP_REG_AC_WEIGHT_EXP__M 0x1F -#define B_CP_REG_AC_WEIGHT_EXP_INIT 0x10 - -#define B_CP_REG_AC_GAIN_MAN__A 0x1410045 -#define B_CP_REG_AC_GAIN_MAN__W 16 -#define B_CP_REG_AC_GAIN_MAN__M 0xFFFF -#define B_CP_REG_AC_GAIN_MAN_INIT 0x0 - -#define B_CP_REG_AC_GAIN_EXP__A 0x1410046 -#define B_CP_REG_AC_GAIN_EXP__W 5 -#define B_CP_REG_AC_GAIN_EXP__M 0x1F -#define B_CP_REG_AC_GAIN_EXP_INIT 0x0 - #define B_CP_REG_AC_AMP_MODE__A 0x1410047 -#define B_CP_REG_AC_AMP_MODE__W 2 -#define B_CP_REG_AC_AMP_MODE__M 0x3 -#define B_CP_REG_AC_AMP_MODE_NEW 0x0 -#define B_CP_REG_AC_AMP_MODE_OLD 0x1 -#define B_CP_REG_AC_AMP_MODE_FIXED 0x2 -#define B_CP_REG_AC_AMP_MODE_INIT 0x2 - #define B_CP_REG_AC_AMP_FIX__A 0x1410048 -#define B_CP_REG_AC_AMP_FIX__W 14 -#define B_CP_REG_AC_AMP_FIX__M 0x3FFF -#define B_CP_REG_AC_AMP_FIX_INIT 0x1FF - -#define B_CP_REG_AC_AMP_READ__A 0x1410049 -#define B_CP_REG_AC_AMP_READ__W 14 -#define B_CP_REG_AC_AMP_READ__M 0x3FFF -#define B_CP_REG_AC_AMP_READ_INIT 0x0 - #define B_CP_REG_AC_ANG_MODE__A 0x141004A -#define B_CP_REG_AC_ANG_MODE__W 2 -#define B_CP_REG_AC_ANG_MODE__M 0x3 -#define B_CP_REG_AC_ANG_MODE_NEW 0x0 -#define B_CP_REG_AC_ANG_MODE_OLD 0x1 -#define B_CP_REG_AC_ANG_MODE_NO_INT 0x2 -#define B_CP_REG_AC_ANG_MODE_OFFSET 0x3 -#define B_CP_REG_AC_ANG_MODE_INIT 0x3 - -#define B_CP_REG_AC_ANG_OFFS__A 0x141004B -#define B_CP_REG_AC_ANG_OFFS__W 14 -#define B_CP_REG_AC_ANG_OFFS__M 0x3FFF -#define B_CP_REG_AC_ANG_OFFS_INIT 0x0 - -#define B_CP_REG_AC_ANG_READ__A 0x141004C -#define B_CP_REG_AC_ANG_READ__W 16 -#define B_CP_REG_AC_ANG_READ__M 0xFFFF -#define B_CP_REG_AC_ANG_READ_INIT 0x0 - -#define B_CP_REG_AC_ACCU_REAL0__A 0x1410060 -#define B_CP_REG_AC_ACCU_REAL0__W 8 -#define B_CP_REG_AC_ACCU_REAL0__M 0xFF -#define B_CP_REG_AC_ACCU_REAL0_INIT 0x0 - -#define B_CP_REG_AC_ACCU_IMAG0__A 0x1410061 -#define B_CP_REG_AC_ACCU_IMAG0__W 8 -#define B_CP_REG_AC_ACCU_IMAG0__M 0xFF -#define B_CP_REG_AC_ACCU_IMAG0_INIT 0x0 - -#define B_CP_REG_AC_ACCU_REAL1__A 0x1410062 -#define B_CP_REG_AC_ACCU_REAL1__W 8 -#define B_CP_REG_AC_ACCU_REAL1__M 0xFF -#define B_CP_REG_AC_ACCU_REAL1_INIT 0x0 - -#define B_CP_REG_AC_ACCU_IMAG1__A 0x1410063 -#define B_CP_REG_AC_ACCU_IMAG1__W 8 -#define B_CP_REG_AC_ACCU_IMAG1__M 0xFF -#define B_CP_REG_AC_ACCU_IMAG1_INIT 0x0 - -#define B_CP_REG_DL_MB_WR_ADDR__A 0x1410050 -#define B_CP_REG_DL_MB_WR_ADDR__W 15 -#define B_CP_REG_DL_MB_WR_ADDR__M 0x7FFF -#define B_CP_REG_DL_MB_WR_ADDR_INIT 0x0 - -#define B_CP_REG_DL_MB_WR_CTR__A 0x1410051 -#define B_CP_REG_DL_MB_WR_CTR__W 5 -#define B_CP_REG_DL_MB_WR_CTR__M 0x1F - -#define B_CP_REG_DL_MB_WR_CTR_WORD__B 2 -#define B_CP_REG_DL_MB_WR_CTR_WORD__W 3 -#define B_CP_REG_DL_MB_WR_CTR_WORD__M 0x1C - -#define B_CP_REG_DL_MB_WR_CTR_OBS__B 1 -#define B_CP_REG_DL_MB_WR_CTR_OBS__W 1 -#define B_CP_REG_DL_MB_WR_CTR_OBS__M 0x2 - -#define B_CP_REG_DL_MB_WR_CTR_CTR__B 0 -#define B_CP_REG_DL_MB_WR_CTR_CTR__W 1 -#define B_CP_REG_DL_MB_WR_CTR_CTR__M 0x1 -#define B_CP_REG_DL_MB_WR_CTR_INIT 0x0 - -#define B_CP_REG_DL_MB_RD_ADDR__A 0x1410052 -#define B_CP_REG_DL_MB_RD_ADDR__W 15 -#define B_CP_REG_DL_MB_RD_ADDR__M 0x7FFF -#define B_CP_REG_DL_MB_RD_ADDR_INIT 0x0 - -#define B_CP_REG_DL_MB_RD_CTR__A 0x1410053 -#define B_CP_REG_DL_MB_RD_CTR__W 11 -#define B_CP_REG_DL_MB_RD_CTR__M 0x7FF - -#define B_CP_REG_DL_MB_RD_CTR_TEST__B 10 -#define B_CP_REG_DL_MB_RD_CTR_TEST__W 1 -#define B_CP_REG_DL_MB_RD_CTR_TEST__M 0x400 - -#define B_CP_REG_DL_MB_RD_CTR_OFFSET__B 8 -#define B_CP_REG_DL_MB_RD_CTR_OFFSET__W 2 -#define B_CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300 - -#define B_CP_REG_DL_MB_RD_CTR_VALID__B 5 -#define B_CP_REG_DL_MB_RD_CTR_VALID__W 3 -#define B_CP_REG_DL_MB_RD_CTR_VALID__M 0xE0 - -#define B_CP_REG_DL_MB_RD_CTR_WORD__B 2 -#define B_CP_REG_DL_MB_RD_CTR_WORD__W 3 -#define B_CP_REG_DL_MB_RD_CTR_WORD__M 0x1C - -#define B_CP_REG_DL_MB_RD_CTR_OBS__B 1 -#define B_CP_REG_DL_MB_RD_CTR_OBS__W 1 -#define B_CP_REG_DL_MB_RD_CTR_OBS__M 0x2 - -#define B_CP_REG_DL_MB_RD_CTR_CTR__B 0 -#define B_CP_REG_DL_MB_RD_CTR_CTR__W 1 -#define B_CP_REG_DL_MB_RD_CTR_CTR__M 0x1 -#define B_CP_REG_DL_MB_RD_CTR_INIT 0x0 - -#define B_CP_BR_BUF_RAM__A 0x1420000 - -#define B_CP_BR_CPL_RAM__A 0x1430000 - -#define B_CP_PB_DL0_RAM__A 0x1440000 - -#define B_CP_PB_DL1_RAM__A 0x1450000 - -#define B_CP_PB_DL2_RAM__A 0x1460000 - -#define B_CE_SID 0xA - #define B_CE_COMM_EXEC__A 0x1800000 -#define B_CE_COMM_EXEC__W 3 -#define B_CE_COMM_EXEC__M 0x7 -#define B_CE_COMM_EXEC_CTL__B 0 -#define B_CE_COMM_EXEC_CTL__W 3 -#define B_CE_COMM_EXEC_CTL__M 0x7 -#define B_CE_COMM_EXEC_CTL_STOP 0x0 -#define B_CE_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CE_COMM_EXEC_CTL_HOLD 0x2 -#define B_CE_COMM_EXEC_CTL_STEP 0x3 -#define B_CE_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_CE_COMM_STATE__A 0x1800001 -#define B_CE_COMM_STATE__W 16 -#define B_CE_COMM_STATE__M 0xFFFF -#define B_CE_COMM_MB__A 0x1800002 -#define B_CE_COMM_MB__W 16 -#define B_CE_COMM_MB__M 0xFFFF -#define B_CE_COMM_SERVICE0__A 0x1800003 -#define B_CE_COMM_SERVICE0__W 16 -#define B_CE_COMM_SERVICE0__M 0xFFFF -#define B_CE_COMM_SERVICE1__A 0x1800004 -#define B_CE_COMM_SERVICE1__W 16 -#define B_CE_COMM_SERVICE1__M 0xFFFF -#define B_CE_COMM_INT_STA__A 0x1800007 -#define B_CE_COMM_INT_STA__W 16 -#define B_CE_COMM_INT_STA__M 0xFFFF -#define B_CE_COMM_INT_MSK__A 0x1800008 -#define B_CE_COMM_INT_MSK__W 16 -#define B_CE_COMM_INT_MSK__M 0xFFFF - -#define B_CE_REG_COMM_EXEC__A 0x1810000 -#define B_CE_REG_COMM_EXEC__W 3 -#define B_CE_REG_COMM_EXEC__M 0x7 -#define B_CE_REG_COMM_EXEC_CTL__B 0 -#define B_CE_REG_COMM_EXEC_CTL__W 3 -#define B_CE_REG_COMM_EXEC_CTL__M 0x7 -#define B_CE_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_CE_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CE_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_CE_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_CE_REG_COMM_MB__A 0x1810002 -#define B_CE_REG_COMM_MB__W 4 -#define B_CE_REG_COMM_MB__M 0xF -#define B_CE_REG_COMM_MB_CTR__B 0 -#define B_CE_REG_COMM_MB_CTR__W 1 -#define B_CE_REG_COMM_MB_CTR__M 0x1 -#define B_CE_REG_COMM_MB_CTR_OFF 0x0 -#define B_CE_REG_COMM_MB_CTR_ON 0x1 -#define B_CE_REG_COMM_MB_OBS__B 1 -#define B_CE_REG_COMM_MB_OBS__W 1 -#define B_CE_REG_COMM_MB_OBS__M 0x2 -#define B_CE_REG_COMM_MB_OBS_OFF 0x0 -#define B_CE_REG_COMM_MB_OBS_ON 0x2 -#define B_CE_REG_COMM_MB_OBS_SEL__B 2 -#define B_CE_REG_COMM_MB_OBS_SEL__W 2 -#define B_CE_REG_COMM_MB_OBS_SEL__M 0xC -#define B_CE_REG_COMM_MB_OBS_SEL_FI 0x0 -#define B_CE_REG_COMM_MB_OBS_SEL_TP 0x4 -#define B_CE_REG_COMM_MB_OBS_SEL_TI 0x8 -#define B_CE_REG_COMM_MB_OBS_SEL_FR 0x8 - -#define B_CE_REG_COMM_SERVICE0__A 0x1810003 -#define B_CE_REG_COMM_SERVICE0__W 10 -#define B_CE_REG_COMM_SERVICE0__M 0x3FF -#define B_CE_REG_COMM_SERVICE0_FT__B 8 -#define B_CE_REG_COMM_SERVICE0_FT__W 1 -#define B_CE_REG_COMM_SERVICE0_FT__M 0x100 - -#define B_CE_REG_COMM_SERVICE1__A 0x1810004 -#define B_CE_REG_COMM_SERVICE1__W 11 -#define B_CE_REG_COMM_SERVICE1__M 0x7FF - -#define B_CE_REG_COMM_INT_STA__A 0x1810007 -#define B_CE_REG_COMM_INT_STA__W 3 -#define B_CE_REG_COMM_INT_STA__M 0x7 -#define B_CE_REG_COMM_INT_STA_CE_PE__B 0 -#define B_CE_REG_COMM_INT_STA_CE_PE__W 1 -#define B_CE_REG_COMM_INT_STA_CE_PE__M 0x1 -#define B_CE_REG_COMM_INT_STA_CE_IR__B 1 -#define B_CE_REG_COMM_INT_STA_CE_IR__W 1 -#define B_CE_REG_COMM_INT_STA_CE_IR__M 0x2 -#define B_CE_REG_COMM_INT_STA_CE_FI__B 2 -#define B_CE_REG_COMM_INT_STA_CE_FI__W 1 -#define B_CE_REG_COMM_INT_STA_CE_FI__M 0x4 - -#define B_CE_REG_COMM_INT_MSK__A 0x1810008 -#define B_CE_REG_COMM_INT_MSK__W 3 -#define B_CE_REG_COMM_INT_MSK__M 0x7 -#define B_CE_REG_COMM_INT_MSK_CE_PE__B 0 -#define B_CE_REG_COMM_INT_MSK_CE_PE__W 1 -#define B_CE_REG_COMM_INT_MSK_CE_PE__M 0x1 -#define B_CE_REG_COMM_INT_MSK_CE_IR__B 1 -#define B_CE_REG_COMM_INT_MSK_CE_IR__W 1 -#define B_CE_REG_COMM_INT_MSK_CE_IR__M 0x2 -#define B_CE_REG_COMM_INT_MSK_CE_FI__B 2 -#define B_CE_REG_COMM_INT_MSK_CE_FI__W 1 -#define B_CE_REG_COMM_INT_MSK_CE_FI__M 0x4 - -#define B_CE_REG_2K__A 0x1810010 -#define B_CE_REG_2K__W 1 -#define B_CE_REG_2K__M 0x1 -#define B_CE_REG_2K_INIT 0x0 - +#define B_CE_REG_COMM_EXEC__A 0x1810000 #define B_CE_REG_TAPSET__A 0x1810011 -#define B_CE_REG_TAPSET__W 4 -#define B_CE_REG_TAPSET__M 0xF - -#define B_CE_REG_TAPSET_MOTION_INIT 0x0 - -#define B_CE_REG_TAPSET_MOTION_NO 0x0 - -#define B_CE_REG_TAPSET_MOTION_LOW 0x1 - -#define B_CE_REG_TAPSET_MOTION_HIGH 0x2 - -#define B_CE_REG_TAPSET_MOTION_HIGH2 0x4 - -#define B_CE_REG_TAPSET_MOTION_UNDEFINED 0x8 - #define B_CE_REG_AVG_POW__A 0x1810012 -#define B_CE_REG_AVG_POW__W 8 -#define B_CE_REG_AVG_POW__M 0xFF -#define B_CE_REG_AVG_POW_INIT 0x0 - #define B_CE_REG_MAX_POW__A 0x1810013 -#define B_CE_REG_MAX_POW__W 8 -#define B_CE_REG_MAX_POW__M 0xFF -#define B_CE_REG_MAX_POW_INIT 0x0 - #define B_CE_REG_ATT__A 0x1810014 -#define B_CE_REG_ATT__W 8 -#define B_CE_REG_ATT__M 0xFF -#define B_CE_REG_ATT_INIT 0x0 - #define B_CE_REG_NRED__A 0x1810015 -#define B_CE_REG_NRED__W 6 -#define B_CE_REG_NRED__M 0x3F -#define B_CE_REG_NRED_INIT 0x0 - -#define B_CE_REG_PU_SIGN__A 0x1810020 -#define B_CE_REG_PU_SIGN__W 1 -#define B_CE_REG_PU_SIGN__M 0x1 -#define B_CE_REG_PU_SIGN_INIT 0x0 - -#define B_CE_REG_PU_MIX__A 0x1810021 -#define B_CE_REG_PU_MIX__W 1 -#define B_CE_REG_PU_MIX__M 0x1 -#define B_CE_REG_PU_MIX_INIT 0x0 - -#define B_CE_REG_PB_PILOT_REQ__A 0x1810030 -#define B_CE_REG_PB_PILOT_REQ__W 15 -#define B_CE_REG_PB_PILOT_REQ__M 0x7FFF -#define B_CE_REG_PB_PILOT_REQ_INIT 0x0 -#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12 -#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3 -#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000 -#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0 -#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12 -#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF - -#define B_CE_REG_PB_PILOT_REQ_VALID__A 0x1810031 -#define B_CE_REG_PB_PILOT_REQ_VALID__W 1 -#define B_CE_REG_PB_PILOT_REQ_VALID__M 0x1 -#define B_CE_REG_PB_PILOT_REQ_VALID_INIT 0x0 - -#define B_CE_REG_PB_FREEZE__A 0x1810032 -#define B_CE_REG_PB_FREEZE__W 1 -#define B_CE_REG_PB_FREEZE__M 0x1 -#define B_CE_REG_PB_FREEZE_INIT 0x0 - -#define B_CE_REG_PB_PILOT_EXP__A 0x1810038 -#define B_CE_REG_PB_PILOT_EXP__W 4 -#define B_CE_REG_PB_PILOT_EXP__M 0xF -#define B_CE_REG_PB_PILOT_EXP_INIT 0x0 - -#define B_CE_REG_PB_PILOT_REAL__A 0x1810039 -#define B_CE_REG_PB_PILOT_REAL__W 10 -#define B_CE_REG_PB_PILOT_REAL__M 0x3FF -#define B_CE_REG_PB_PILOT_REAL_INIT 0x0 - -#define B_CE_REG_PB_PILOT_IMAG__A 0x181003A -#define B_CE_REG_PB_PILOT_IMAG__W 10 -#define B_CE_REG_PB_PILOT_IMAG__M 0x3FF -#define B_CE_REG_PB_PILOT_IMAG_INIT 0x0 - -#define B_CE_REG_PB_SMBNR__A 0x181003B -#define B_CE_REG_PB_SMBNR__W 5 -#define B_CE_REG_PB_SMBNR__M 0x1F -#define B_CE_REG_PB_SMBNR_INIT 0x0 - -#define B_CE_REG_NE_PILOT_REQ__A 0x1810040 -#define B_CE_REG_NE_PILOT_REQ__W 12 -#define B_CE_REG_NE_PILOT_REQ__M 0xFFF -#define B_CE_REG_NE_PILOT_REQ_INIT 0x0 - -#define B_CE_REG_NE_PILOT_REQ_VALID__A 0x1810041 -#define B_CE_REG_NE_PILOT_REQ_VALID__W 2 -#define B_CE_REG_NE_PILOT_REQ_VALID__M 0x3 -#define B_CE_REG_NE_PILOT_REQ_VALID_INIT 0x0 -#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1 -#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1 -#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2 -#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0 -#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1 -#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1 - -#define B_CE_REG_NE_PILOT_DATA__A 0x1810042 -#define B_CE_REG_NE_PILOT_DATA__W 10 -#define B_CE_REG_NE_PILOT_DATA__M 0x3FF -#define B_CE_REG_NE_PILOT_DATA_INIT 0x0 - #define B_CE_REG_NE_ERR_SELECT__A 0x1810043 -#define B_CE_REG_NE_ERR_SELECT__W 5 -#define B_CE_REG_NE_ERR_SELECT__M 0x1F -#define B_CE_REG_NE_ERR_SELECT_INIT 0x7 - -#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__B 4 -#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__W 1 -#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__M 0x10 - -#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__B 3 -#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__W 1 -#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__M 0x8 - -#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__B 2 -#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__W 1 -#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4 - -#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1 -#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1 -#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2 - -#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0 -#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1 -#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1 - #define B_CE_REG_NE_TD_CAL__A 0x1810044 -#define B_CE_REG_NE_TD_CAL__W 9 -#define B_CE_REG_NE_TD_CAL__M 0x1FF -#define B_CE_REG_NE_TD_CAL_INIT 0x1E8 - -#define B_CE_REG_NE_FD_CAL__A 0x1810045 -#define B_CE_REG_NE_FD_CAL__W 9 -#define B_CE_REG_NE_FD_CAL__M 0x1FF -#define B_CE_REG_NE_FD_CAL_INIT 0x1D9 - #define B_CE_REG_NE_MIXAVG__A 0x1810046 -#define B_CE_REG_NE_MIXAVG__W 3 -#define B_CE_REG_NE_MIXAVG__M 0x7 -#define B_CE_REG_NE_MIXAVG_INIT 0x6 - #define B_CE_REG_NE_NUPD_OFS__A 0x1810047 -#define B_CE_REG_NE_NUPD_OFS__W 4 -#define B_CE_REG_NE_NUPD_OFS__M 0xF -#define B_CE_REG_NE_NUPD_OFS_INIT 0x4 - -#define B_CE_REG_NE_TD_POW__A 0x1810048 -#define B_CE_REG_NE_TD_POW__W 15 -#define B_CE_REG_NE_TD_POW__M 0x7FFF -#define B_CE_REG_NE_TD_POW_INIT 0x0 - -#define B_CE_REG_NE_TD_POW_EXPONENT__B 10 -#define B_CE_REG_NE_TD_POW_EXPONENT__W 5 -#define B_CE_REG_NE_TD_POW_EXPONENT__M 0x7C00 - -#define B_CE_REG_NE_TD_POW_MANTISSA__B 0 -#define B_CE_REG_NE_TD_POW_MANTISSA__W 10 -#define B_CE_REG_NE_TD_POW_MANTISSA__M 0x3FF - -#define B_CE_REG_NE_FD_POW__A 0x1810049 -#define B_CE_REG_NE_FD_POW__W 15 -#define B_CE_REG_NE_FD_POW__M 0x7FFF -#define B_CE_REG_NE_FD_POW_INIT 0x0 - -#define B_CE_REG_NE_FD_POW_EXPONENT__B 10 -#define B_CE_REG_NE_FD_POW_EXPONENT__W 5 -#define B_CE_REG_NE_FD_POW_EXPONENT__M 0x7C00 - -#define B_CE_REG_NE_FD_POW_MANTISSA__B 0 -#define B_CE_REG_NE_FD_POW_MANTISSA__W 10 -#define B_CE_REG_NE_FD_POW_MANTISSA__M 0x3FF - -#define B_CE_REG_NE_NEXP_AVG__A 0x181004A -#define B_CE_REG_NE_NEXP_AVG__W 8 -#define B_CE_REG_NE_NEXP_AVG__M 0xFF -#define B_CE_REG_NE_NEXP_AVG_INIT 0x0 - -#define B_CE_REG_NE_OFFSET__A 0x181004B -#define B_CE_REG_NE_OFFSET__W 9 -#define B_CE_REG_NE_OFFSET__M 0x1FF -#define B_CE_REG_NE_OFFSET_INIT 0x0 - -#define B_CE_REG_NE_NUPD_TRH__A 0x181004C -#define B_CE_REG_NE_NUPD_TRH__W 5 -#define B_CE_REG_NE_NUPD_TRH__M 0x1F -#define B_CE_REG_NE_NUPD_TRH_INIT 0x14 - #define B_CE_REG_PE_NEXP_OFFS__A 0x1810050 -#define B_CE_REG_PE_NEXP_OFFS__W 8 -#define B_CE_REG_PE_NEXP_OFFS__M 0xFF -#define B_CE_REG_PE_NEXP_OFFS_INIT 0x0 - #define B_CE_REG_PE_TIMESHIFT__A 0x1810051 -#define B_CE_REG_PE_TIMESHIFT__W 14 -#define B_CE_REG_PE_TIMESHIFT__M 0x3FFF -#define B_CE_REG_PE_TIMESHIFT_INIT 0x0 - -#define B_CE_REG_PE_DIF_REAL_L__A 0x1810052 -#define B_CE_REG_PE_DIF_REAL_L__W 16 -#define B_CE_REG_PE_DIF_REAL_L__M 0xFFFF -#define B_CE_REG_PE_DIF_REAL_L_INIT 0x0 - -#define B_CE_REG_PE_DIF_IMAG_L__A 0x1810053 -#define B_CE_REG_PE_DIF_IMAG_L__W 16 -#define B_CE_REG_PE_DIF_IMAG_L__M 0xFFFF -#define B_CE_REG_PE_DIF_IMAG_L_INIT 0x0 - -#define B_CE_REG_PE_DIF_REAL_R__A 0x1810054 -#define B_CE_REG_PE_DIF_REAL_R__W 16 -#define B_CE_REG_PE_DIF_REAL_R__M 0xFFFF -#define B_CE_REG_PE_DIF_REAL_R_INIT 0x0 - -#define B_CE_REG_PE_DIF_IMAG_R__A 0x1810055 -#define B_CE_REG_PE_DIF_IMAG_R__W 16 -#define B_CE_REG_PE_DIF_IMAG_R__M 0xFFFF -#define B_CE_REG_PE_DIF_IMAG_R_INIT 0x0 - -#define B_CE_REG_PE_ABS_REAL_L__A 0x1810056 -#define B_CE_REG_PE_ABS_REAL_L__W 16 -#define B_CE_REG_PE_ABS_REAL_L__M 0xFFFF -#define B_CE_REG_PE_ABS_REAL_L_INIT 0x0 - -#define B_CE_REG_PE_ABS_IMAG_L__A 0x1810057 -#define B_CE_REG_PE_ABS_IMAG_L__W 16 -#define B_CE_REG_PE_ABS_IMAG_L__M 0xFFFF -#define B_CE_REG_PE_ABS_IMAG_L_INIT 0x0 - -#define B_CE_REG_PE_ABS_REAL_R__A 0x1810058 -#define B_CE_REG_PE_ABS_REAL_R__W 16 -#define B_CE_REG_PE_ABS_REAL_R__M 0xFFFF -#define B_CE_REG_PE_ABS_REAL_R_INIT 0x0 - -#define B_CE_REG_PE_ABS_IMAG_R__A 0x1810059 -#define B_CE_REG_PE_ABS_IMAG_R__W 16 -#define B_CE_REG_PE_ABS_IMAG_R__M 0xFFFF -#define B_CE_REG_PE_ABS_IMAG_R_INIT 0x0 - -#define B_CE_REG_PE_ABS_EXP_L__A 0x181005A -#define B_CE_REG_PE_ABS_EXP_L__W 5 -#define B_CE_REG_PE_ABS_EXP_L__M 0x1F -#define B_CE_REG_PE_ABS_EXP_L_INIT 0x0 - -#define B_CE_REG_PE_ABS_EXP_R__A 0x181005B -#define B_CE_REG_PE_ABS_EXP_R__W 5 -#define B_CE_REG_PE_ABS_EXP_R__M 0x1F -#define B_CE_REG_PE_ABS_EXP_R_INIT 0x0 - -#define B_CE_REG_TP_UPDATE_MODE__A 0x1810060 -#define B_CE_REG_TP_UPDATE_MODE__W 1 -#define B_CE_REG_TP_UPDATE_MODE__M 0x1 -#define B_CE_REG_TP_UPDATE_MODE_INIT 0x0 - -#define B_CE_REG_TP_LMS_TAP_ON__A 0x1810061 -#define B_CE_REG_TP_LMS_TAP_ON__W 1 -#define B_CE_REG_TP_LMS_TAP_ON__M 0x1 - #define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064 -#define B_CE_REG_TP_A0_TAP_NEW__W 10 -#define B_CE_REG_TP_A0_TAP_NEW__M 0x3FF - #define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065 -#define B_CE_REG_TP_A0_TAP_NEW_VALID__W 1 -#define B_CE_REG_TP_A0_TAP_NEW_VALID__M 0x1 - #define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066 -#define B_CE_REG_TP_A0_MU_LMS_STEP__W 5 -#define B_CE_REG_TP_A0_MU_LMS_STEP__M 0x1F - -#define B_CE_REG_TP_A0_TAP_CURR__A 0x1810067 -#define B_CE_REG_TP_A0_TAP_CURR__W 10 -#define B_CE_REG_TP_A0_TAP_CURR__M 0x3FF - #define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068 -#define B_CE_REG_TP_A1_TAP_NEW__W 10 -#define B_CE_REG_TP_A1_TAP_NEW__M 0x3FF - #define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069 -#define B_CE_REG_TP_A1_TAP_NEW_VALID__W 1 -#define B_CE_REG_TP_A1_TAP_NEW_VALID__M 0x1 - #define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A -#define B_CE_REG_TP_A1_MU_LMS_STEP__W 5 -#define B_CE_REG_TP_A1_MU_LMS_STEP__M 0x1F - -#define B_CE_REG_TP_A1_TAP_CURR__A 0x181006B -#define B_CE_REG_TP_A1_TAP_CURR__W 10 -#define B_CE_REG_TP_A1_TAP_CURR__M 0x3FF - -#define B_CE_REG_TP_DOPP_ENERGY__A 0x181006C -#define B_CE_REG_TP_DOPP_ENERGY__W 15 -#define B_CE_REG_TP_DOPP_ENERGY__M 0x7FFF -#define B_CE_REG_TP_DOPP_ENERGY_INIT 0x0 - -#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10 -#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5 -#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00 - -#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0 -#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10 -#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF - -#define B_CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D -#define B_CE_REG_TP_DOPP_DIFF_ENERGY__W 15 -#define B_CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0 - -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10 -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5 -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00 - -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0 -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10 -#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF - -#define B_CE_REG_TP_A0_TAP_ENERGY__A 0x181006E -#define B_CE_REG_TP_A0_TAP_ENERGY__W 15 -#define B_CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF -#define B_CE_REG_TP_A0_TAP_ENERGY_INIT 0x0 - -#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10 -#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5 -#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00 - -#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0 -#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10 -#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF - -#define B_CE_REG_TP_A1_TAP_ENERGY__A 0x181006F -#define B_CE_REG_TP_A1_TAP_ENERGY__W 15 -#define B_CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF -#define B_CE_REG_TP_A1_TAP_ENERGY_INIT 0x0 - -#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10 -#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5 -#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00 - -#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0 -#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10 -#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF - -#define B_CE_REG_TI_SYM_CNT__A 0x1810072 -#define B_CE_REG_TI_SYM_CNT__W 6 -#define B_CE_REG_TI_SYM_CNT__M 0x3F -#define B_CE_REG_TI_SYM_CNT_INIT 0x0 - #define B_CE_REG_TI_PHN_ENABLE__A 0x1810073 -#define B_CE_REG_TI_PHN_ENABLE__W 1 -#define B_CE_REG_TI_PHN_ENABLE__M 0x1 -#define B_CE_REG_TI_PHN_ENABLE_INIT 0x0 - -#define B_CE_REG_TI_SHIFT__A 0x1810074 -#define B_CE_REG_TI_SHIFT__W 2 -#define B_CE_REG_TI_SHIFT__M 0x3 -#define B_CE_REG_TI_SHIFT_INIT 0x0 - -#define B_CE_REG_TI_SLOW__A 0x1810075 -#define B_CE_REG_TI_SLOW__W 1 -#define B_CE_REG_TI_SLOW__M 0x1 -#define B_CE_REG_TI_SLOW_INIT 0x0 - -#define B_CE_REG_TI_MGAIN__A 0x1810076 -#define B_CE_REG_TI_MGAIN__W 8 -#define B_CE_REG_TI_MGAIN__M 0xFF -#define B_CE_REG_TI_MGAIN_INIT 0x0 - -#define B_CE_REG_TI_ACCU1__A 0x1810077 -#define B_CE_REG_TI_ACCU1__W 8 -#define B_CE_REG_TI_ACCU1__M 0xFF -#define B_CE_REG_TI_ACCU1_INIT 0x0 - -#define B_CE_REG_NI_PER_LEFT__A 0x18100B0 -#define B_CE_REG_NI_PER_LEFT__W 5 -#define B_CE_REG_NI_PER_LEFT__M 0x1F -#define B_CE_REG_NI_PER_LEFT_INIT 0xE - -#define B_CE_REG_NI_PER_RIGHT__A 0x18100B1 -#define B_CE_REG_NI_PER_RIGHT__W 5 -#define B_CE_REG_NI_PER_RIGHT__M 0x1F -#define B_CE_REG_NI_PER_RIGHT_INIT 0x7 - -#define B_CE_REG_NI_POS_LR__A 0x18100B2 -#define B_CE_REG_NI_POS_LR__W 9 -#define B_CE_REG_NI_POS_LR__M 0x1FF -#define B_CE_REG_NI_POS_LR_INIT 0xA0 - #define B_CE_REG_FI_SHT_INCR__A 0x1810090 -#define B_CE_REG_FI_SHT_INCR__W 7 -#define B_CE_REG_FI_SHT_INCR__M 0x7F -#define B_CE_REG_FI_SHT_INCR_INIT 0x9 - #define B_CE_REG_FI_EXP_NORM__A 0x1810091 -#define B_CE_REG_FI_EXP_NORM__W 4 -#define B_CE_REG_FI_EXP_NORM__M 0xF -#define B_CE_REG_FI_EXP_NORM_INIT 0x4 - -#define B_CE_REG_FI_SUPR_VAL__A 0x1810092 -#define B_CE_REG_FI_SUPR_VAL__W 1 -#define B_CE_REG_FI_SUPR_VAL__M 0x1 -#define B_CE_REG_FI_SUPR_VAL_INIT 0x1 - #define B_CE_REG_IR_INPUTSEL__A 0x18100A0 -#define B_CE_REG_IR_INPUTSEL__W 1 -#define B_CE_REG_IR_INPUTSEL__M 0x1 -#define B_CE_REG_IR_INPUTSEL_INIT 0x0 - #define B_CE_REG_IR_STARTPOS__A 0x18100A1 -#define B_CE_REG_IR_STARTPOS__W 8 -#define B_CE_REG_IR_STARTPOS__M 0xFF -#define B_CE_REG_IR_STARTPOS_INIT 0x0 - #define B_CE_REG_IR_NEXP_THRES__A 0x18100A2 -#define B_CE_REG_IR_NEXP_THRES__W 8 -#define B_CE_REG_IR_NEXP_THRES__M 0xFF -#define B_CE_REG_IR_NEXP_THRES_INIT 0x0 - -#define B_CE_REG_IR_LENGTH__A 0x18100A3 -#define B_CE_REG_IR_LENGTH__W 4 -#define B_CE_REG_IR_LENGTH__M 0xF -#define B_CE_REG_IR_LENGTH_INIT 0x0 - -#define B_CE_REG_IR_FREQ__A 0x18100A4 -#define B_CE_REG_IR_FREQ__W 11 -#define B_CE_REG_IR_FREQ__M 0x7FF -#define B_CE_REG_IR_FREQ_INIT 0x0 - -#define B_CE_REG_IR_FREQINC__A 0x18100A5 -#define B_CE_REG_IR_FREQINC__W 11 -#define B_CE_REG_IR_FREQINC__M 0x7FF -#define B_CE_REG_IR_FREQINC_INIT 0x0 - -#define B_CE_REG_IR_KAISINC__A 0x18100A6 -#define B_CE_REG_IR_KAISINC__W 15 -#define B_CE_REG_IR_KAISINC__M 0x7FFF -#define B_CE_REG_IR_KAISINC_INIT 0x0 - -#define B_CE_REG_IR_CTL__A 0x18100A7 -#define B_CE_REG_IR_CTL__W 3 -#define B_CE_REG_IR_CTL__M 0x7 -#define B_CE_REG_IR_CTL_INIT 0x0 - -#define B_CE_REG_IR_REAL__A 0x18100A8 -#define B_CE_REG_IR_REAL__W 16 -#define B_CE_REG_IR_REAL__M 0xFFFF -#define B_CE_REG_IR_REAL_INIT 0x0 - -#define B_CE_REG_IR_IMAG__A 0x18100A9 -#define B_CE_REG_IR_IMAG__W 16 -#define B_CE_REG_IR_IMAG__M 0xFFFF -#define B_CE_REG_IR_IMAG_INIT 0x0 - -#define B_CE_REG_IR_INDEX__A 0x18100AA -#define B_CE_REG_IR_INDEX__W 12 -#define B_CE_REG_IR_INDEX__M 0xFFF -#define B_CE_REG_IR_INDEX_INIT 0x0 - -#define B_CE_REG_FR_COMM_EXEC__A 0x1820000 -#define B_CE_REG_FR_COMM_EXEC__W 1 -#define B_CE_REG_FR_COMM_EXEC__M 0x1 - #define B_CE_REG_FR_TREAL00__A 0x1820010 -#define B_CE_REG_FR_TREAL00__W 11 -#define B_CE_REG_FR_TREAL00__M 0x7FF -#define B_CE_REG_FR_TREAL00_INIT 0x52 - #define B_CE_REG_FR_TIMAG00__A 0x1820011 -#define B_CE_REG_FR_TIMAG00__W 11 -#define B_CE_REG_FR_TIMAG00__M 0x7FF -#define B_CE_REG_FR_TIMAG00_INIT 0x0 - #define B_CE_REG_FR_TREAL01__A 0x1820012 -#define B_CE_REG_FR_TREAL01__W 11 -#define B_CE_REG_FR_TREAL01__M 0x7FF -#define B_CE_REG_FR_TREAL01_INIT 0x52 - #define B_CE_REG_FR_TIMAG01__A 0x1820013 -#define B_CE_REG_FR_TIMAG01__W 11 -#define B_CE_REG_FR_TIMAG01__M 0x7FF -#define B_CE_REG_FR_TIMAG01_INIT 0x0 - #define B_CE_REG_FR_TREAL02__A 0x1820014 -#define B_CE_REG_FR_TREAL02__W 11 -#define B_CE_REG_FR_TREAL02__M 0x7FF -#define B_CE_REG_FR_TREAL02_INIT 0x52 - #define B_CE_REG_FR_TIMAG02__A 0x1820015 -#define B_CE_REG_FR_TIMAG02__W 11 -#define B_CE_REG_FR_TIMAG02__M 0x7FF -#define B_CE_REG_FR_TIMAG02_INIT 0x0 - #define B_CE_REG_FR_TREAL03__A 0x1820016 -#define B_CE_REG_FR_TREAL03__W 11 -#define B_CE_REG_FR_TREAL03__M 0x7FF -#define B_CE_REG_FR_TREAL03_INIT 0x52 - #define B_CE_REG_FR_TIMAG03__A 0x1820017 -#define B_CE_REG_FR_TIMAG03__W 11 -#define B_CE_REG_FR_TIMAG03__M 0x7FF -#define B_CE_REG_FR_TIMAG03_INIT 0x0 - #define B_CE_REG_FR_TREAL04__A 0x1820018 -#define B_CE_REG_FR_TREAL04__W 11 -#define B_CE_REG_FR_TREAL04__M 0x7FF -#define B_CE_REG_FR_TREAL04_INIT 0x52 - #define B_CE_REG_FR_TIMAG04__A 0x1820019 -#define B_CE_REG_FR_TIMAG04__W 11 -#define B_CE_REG_FR_TIMAG04__M 0x7FF -#define B_CE_REG_FR_TIMAG04_INIT 0x0 - #define B_CE_REG_FR_TREAL05__A 0x182001A -#define B_CE_REG_FR_TREAL05__W 11 -#define B_CE_REG_FR_TREAL05__M 0x7FF -#define B_CE_REG_FR_TREAL05_INIT 0x52 - #define B_CE_REG_FR_TIMAG05__A 0x182001B -#define B_CE_REG_FR_TIMAG05__W 11 -#define B_CE_REG_FR_TIMAG05__M 0x7FF -#define B_CE_REG_FR_TIMAG05_INIT 0x0 - #define B_CE_REG_FR_TREAL06__A 0x182001C -#define B_CE_REG_FR_TREAL06__W 11 -#define B_CE_REG_FR_TREAL06__M 0x7FF -#define B_CE_REG_FR_TREAL06_INIT 0x52 - #define B_CE_REG_FR_TIMAG06__A 0x182001D -#define B_CE_REG_FR_TIMAG06__W 11 -#define B_CE_REG_FR_TIMAG06__M 0x7FF -#define B_CE_REG_FR_TIMAG06_INIT 0x0 - #define B_CE_REG_FR_TREAL07__A 0x182001E -#define B_CE_REG_FR_TREAL07__W 11 -#define B_CE_REG_FR_TREAL07__M 0x7FF -#define B_CE_REG_FR_TREAL07_INIT 0x52 - #define B_CE_REG_FR_TIMAG07__A 0x182001F -#define B_CE_REG_FR_TIMAG07__W 11 -#define B_CE_REG_FR_TIMAG07__M 0x7FF -#define B_CE_REG_FR_TIMAG07_INIT 0x0 - #define B_CE_REG_FR_TREAL08__A 0x1820020 -#define B_CE_REG_FR_TREAL08__W 11 -#define B_CE_REG_FR_TREAL08__M 0x7FF -#define B_CE_REG_FR_TREAL08_INIT 0x52 - #define B_CE_REG_FR_TIMAG08__A 0x1820021 -#define B_CE_REG_FR_TIMAG08__W 11 -#define B_CE_REG_FR_TIMAG08__M 0x7FF -#define B_CE_REG_FR_TIMAG08_INIT 0x0 - #define B_CE_REG_FR_TREAL09__A 0x1820022 -#define B_CE_REG_FR_TREAL09__W 11 -#define B_CE_REG_FR_TREAL09__M 0x7FF -#define B_CE_REG_FR_TREAL09_INIT 0x52 - #define B_CE_REG_FR_TIMAG09__A 0x1820023 -#define B_CE_REG_FR_TIMAG09__W 11 -#define B_CE_REG_FR_TIMAG09__M 0x7FF -#define B_CE_REG_FR_TIMAG09_INIT 0x0 - #define B_CE_REG_FR_TREAL10__A 0x1820024 -#define B_CE_REG_FR_TREAL10__W 11 -#define B_CE_REG_FR_TREAL10__M 0x7FF -#define B_CE_REG_FR_TREAL10_INIT 0x52 - #define B_CE_REG_FR_TIMAG10__A 0x1820025 -#define B_CE_REG_FR_TIMAG10__W 11 -#define B_CE_REG_FR_TIMAG10__M 0x7FF -#define B_CE_REG_FR_TIMAG10_INIT 0x0 - #define B_CE_REG_FR_TREAL11__A 0x1820026 -#define B_CE_REG_FR_TREAL11__W 11 -#define B_CE_REG_FR_TREAL11__M 0x7FF -#define B_CE_REG_FR_TREAL11_INIT 0x52 - #define B_CE_REG_FR_TIMAG11__A 0x1820027 -#define B_CE_REG_FR_TIMAG11__W 11 -#define B_CE_REG_FR_TIMAG11__M 0x7FF -#define B_CE_REG_FR_TIMAG11_INIT 0x0 - #define B_CE_REG_FR_MID_TAP__A 0x1820028 -#define B_CE_REG_FR_MID_TAP__W 11 -#define B_CE_REG_FR_MID_TAP__M 0x7FF -#define B_CE_REG_FR_MID_TAP_INIT 0x51 - #define B_CE_REG_FR_SQS_G00__A 0x1820029 -#define B_CE_REG_FR_SQS_G00__W 8 -#define B_CE_REG_FR_SQS_G00__M 0xFF -#define B_CE_REG_FR_SQS_G00_INIT 0xB - #define B_CE_REG_FR_SQS_G01__A 0x182002A -#define B_CE_REG_FR_SQS_G01__W 8 -#define B_CE_REG_FR_SQS_G01__M 0xFF -#define B_CE_REG_FR_SQS_G01_INIT 0xB - #define B_CE_REG_FR_SQS_G02__A 0x182002B -#define B_CE_REG_FR_SQS_G02__W 8 -#define B_CE_REG_FR_SQS_G02__M 0xFF -#define B_CE_REG_FR_SQS_G02_INIT 0xB - #define B_CE_REG_FR_SQS_G03__A 0x182002C -#define B_CE_REG_FR_SQS_G03__W 8 -#define B_CE_REG_FR_SQS_G03__M 0xFF -#define B_CE_REG_FR_SQS_G03_INIT 0xB - #define B_CE_REG_FR_SQS_G04__A 0x182002D -#define B_CE_REG_FR_SQS_G04__W 8 -#define B_CE_REG_FR_SQS_G04__M 0xFF -#define B_CE_REG_FR_SQS_G04_INIT 0xB - #define B_CE_REG_FR_SQS_G05__A 0x182002E -#define B_CE_REG_FR_SQS_G05__W 8 -#define B_CE_REG_FR_SQS_G05__M 0xFF -#define B_CE_REG_FR_SQS_G05_INIT 0xB - #define B_CE_REG_FR_SQS_G06__A 0x182002F -#define B_CE_REG_FR_SQS_G06__W 8 -#define B_CE_REG_FR_SQS_G06__M 0xFF -#define B_CE_REG_FR_SQS_G06_INIT 0xB - #define B_CE_REG_FR_SQS_G07__A 0x1820030 -#define B_CE_REG_FR_SQS_G07__W 8 -#define B_CE_REG_FR_SQS_G07__M 0xFF -#define B_CE_REG_FR_SQS_G07_INIT 0xB - #define B_CE_REG_FR_SQS_G08__A 0x1820031 -#define B_CE_REG_FR_SQS_G08__W 8 -#define B_CE_REG_FR_SQS_G08__M 0xFF -#define B_CE_REG_FR_SQS_G08_INIT 0xB - #define B_CE_REG_FR_SQS_G09__A 0x1820032 -#define B_CE_REG_FR_SQS_G09__W 8 -#define B_CE_REG_FR_SQS_G09__M 0xFF -#define B_CE_REG_FR_SQS_G09_INIT 0xB - #define B_CE_REG_FR_SQS_G10__A 0x1820033 -#define B_CE_REG_FR_SQS_G10__W 8 -#define B_CE_REG_FR_SQS_G10__M 0xFF -#define B_CE_REG_FR_SQS_G10_INIT 0xB - #define B_CE_REG_FR_SQS_G11__A 0x1820034 -#define B_CE_REG_FR_SQS_G11__W 8 -#define B_CE_REG_FR_SQS_G11__M 0xFF -#define B_CE_REG_FR_SQS_G11_INIT 0xB - #define B_CE_REG_FR_SQS_G12__A 0x1820035 -#define B_CE_REG_FR_SQS_G12__W 8 -#define B_CE_REG_FR_SQS_G12__M 0xFF -#define B_CE_REG_FR_SQS_G12_INIT 0x5 - #define B_CE_REG_FR_RIO_G00__A 0x1820036 -#define B_CE_REG_FR_RIO_G00__W 9 -#define B_CE_REG_FR_RIO_G00__M 0x1FF -#define B_CE_REG_FR_RIO_G00_INIT 0x1FF - #define B_CE_REG_FR_RIO_G01__A 0x1820037 -#define B_CE_REG_FR_RIO_G01__W 9 -#define B_CE_REG_FR_RIO_G01__M 0x1FF -#define B_CE_REG_FR_RIO_G01_INIT 0x190 - #define B_CE_REG_FR_RIO_G02__A 0x1820038 -#define B_CE_REG_FR_RIO_G02__W 9 -#define B_CE_REG_FR_RIO_G02__M 0x1FF -#define B_CE_REG_FR_RIO_G02_INIT 0x10B - #define B_CE_REG_FR_RIO_G03__A 0x1820039 -#define B_CE_REG_FR_RIO_G03__W 9 -#define B_CE_REG_FR_RIO_G03__M 0x1FF -#define B_CE_REG_FR_RIO_G03_INIT 0xC8 - #define B_CE_REG_FR_RIO_G04__A 0x182003A -#define B_CE_REG_FR_RIO_G04__W 9 -#define B_CE_REG_FR_RIO_G04__M 0x1FF -#define B_CE_REG_FR_RIO_G04_INIT 0xA0 - #define B_CE_REG_FR_RIO_G05__A 0x182003B -#define B_CE_REG_FR_RIO_G05__W 9 -#define B_CE_REG_FR_RIO_G05__M 0x1FF -#define B_CE_REG_FR_RIO_G05_INIT 0x85 - #define B_CE_REG_FR_RIO_G06__A 0x182003C -#define B_CE_REG_FR_RIO_G06__W 9 -#define B_CE_REG_FR_RIO_G06__M 0x1FF -#define B_CE_REG_FR_RIO_G06_INIT 0x72 - #define B_CE_REG_FR_RIO_G07__A 0x182003D -#define B_CE_REG_FR_RIO_G07__W 9 -#define B_CE_REG_FR_RIO_G07__M 0x1FF -#define B_CE_REG_FR_RIO_G07_INIT 0x64 - #define B_CE_REG_FR_RIO_G08__A 0x182003E -#define B_CE_REG_FR_RIO_G08__W 9 -#define B_CE_REG_FR_RIO_G08__M 0x1FF -#define B_CE_REG_FR_RIO_G08_INIT 0x59 - #define B_CE_REG_FR_RIO_G09__A 0x182003F -#define B_CE_REG_FR_RIO_G09__W 9 -#define B_CE_REG_FR_RIO_G09__M 0x1FF -#define B_CE_REG_FR_RIO_G09_INIT 0x50 - #define B_CE_REG_FR_RIO_G10__A 0x1820040 -#define B_CE_REG_FR_RIO_G10__W 9 -#define B_CE_REG_FR_RIO_G10__M 0x1FF -#define B_CE_REG_FR_RIO_G10_INIT 0x49 - #define B_CE_REG_FR_MODE__A 0x1820041 -#define B_CE_REG_FR_MODE__W 9 -#define B_CE_REG_FR_MODE__M 0x1FF - -#define B_CE_REG_FR_MODE_UPDATE_ENABLE__B 0 -#define B_CE_REG_FR_MODE_UPDATE_ENABLE__W 1 -#define B_CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1 - -#define B_CE_REG_FR_MODE_ERROR_SHIFT__B 1 -#define B_CE_REG_FR_MODE_ERROR_SHIFT__W 1 -#define B_CE_REG_FR_MODE_ERROR_SHIFT__M 0x2 - -#define B_CE_REG_FR_MODE_NEXP_UPDATE__B 2 -#define B_CE_REG_FR_MODE_NEXP_UPDATE__W 1 -#define B_CE_REG_FR_MODE_NEXP_UPDATE__M 0x4 - -#define B_CE_REG_FR_MODE_MANUAL_SHIFT__B 3 -#define B_CE_REG_FR_MODE_MANUAL_SHIFT__W 1 -#define B_CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8 - -#define B_CE_REG_FR_MODE_SQUASH_MODE__B 4 -#define B_CE_REG_FR_MODE_SQUASH_MODE__W 1 -#define B_CE_REG_FR_MODE_SQUASH_MODE__M 0x10 - -#define B_CE_REG_FR_MODE_UPDATE_MODE__B 5 -#define B_CE_REG_FR_MODE_UPDATE_MODE__W 1 -#define B_CE_REG_FR_MODE_UPDATE_MODE__M 0x20 - -#define B_CE_REG_FR_MODE_MID_MODE__B 6 -#define B_CE_REG_FR_MODE_MID_MODE__W 1 -#define B_CE_REG_FR_MODE_MID_MODE__M 0x40 - -#define B_CE_REG_FR_MODE_NOISE_MODE__B 7 -#define B_CE_REG_FR_MODE_NOISE_MODE__W 1 -#define B_CE_REG_FR_MODE_NOISE_MODE__M 0x80 - -#define B_CE_REG_FR_MODE_NOTCH_MODE__B 8 -#define B_CE_REG_FR_MODE_NOTCH_MODE__W 1 -#define B_CE_REG_FR_MODE_NOTCH_MODE__M 0x100 -#define B_CE_REG_FR_MODE_INIT 0xDE - #define B_CE_REG_FR_SQS_TRH__A 0x1820042 -#define B_CE_REG_FR_SQS_TRH__W 8 -#define B_CE_REG_FR_SQS_TRH__M 0xFF -#define B_CE_REG_FR_SQS_TRH_INIT 0x80 - #define B_CE_REG_FR_RIO_GAIN__A 0x1820043 -#define B_CE_REG_FR_RIO_GAIN__W 3 -#define B_CE_REG_FR_RIO_GAIN__M 0x7 -#define B_CE_REG_FR_RIO_GAIN_INIT 0x2 - #define B_CE_REG_FR_BYPASS__A 0x1820044 -#define B_CE_REG_FR_BYPASS__W 10 -#define B_CE_REG_FR_BYPASS__M 0x3FF - -#define B_CE_REG_FR_BYPASS_RUN_IN__B 0 -#define B_CE_REG_FR_BYPASS_RUN_IN__W 4 -#define B_CE_REG_FR_BYPASS_RUN_IN__M 0xF - -#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4 -#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5 -#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0 - -#define B_CE_REG_FR_BYPASS_TOTAL__B 9 -#define B_CE_REG_FR_BYPASS_TOTAL__W 1 -#define B_CE_REG_FR_BYPASS_TOTAL__M 0x200 -#define B_CE_REG_FR_BYPASS_INIT 0x13B - #define B_CE_REG_FR_PM_SET__A 0x1820045 -#define B_CE_REG_FR_PM_SET__W 4 -#define B_CE_REG_FR_PM_SET__M 0xF -#define B_CE_REG_FR_PM_SET_INIT 0x4 - #define B_CE_REG_FR_ERR_SH__A 0x1820046 -#define B_CE_REG_FR_ERR_SH__W 4 -#define B_CE_REG_FR_ERR_SH__M 0xF -#define B_CE_REG_FR_ERR_SH_INIT 0x4 - #define B_CE_REG_FR_MAN_SH__A 0x1820047 -#define B_CE_REG_FR_MAN_SH__W 4 -#define B_CE_REG_FR_MAN_SH__M 0xF -#define B_CE_REG_FR_MAN_SH_INIT 0x7 - #define B_CE_REG_FR_TAP_SH__A 0x1820048 -#define B_CE_REG_FR_TAP_SH__W 3 -#define B_CE_REG_FR_TAP_SH__M 0x7 -#define B_CE_REG_FR_TAP_SH_INIT 0x3 - -#define B_CE_REG_FR_CLIP__A 0x1820049 -#define B_CE_REG_FR_CLIP__W 9 -#define B_CE_REG_FR_CLIP__M 0x1FF -#define B_CE_REG_FR_CLIP_INIT 0x49 - -#define B_CE_REG_FR_LEAK_UPD__A 0x182004A -#define B_CE_REG_FR_LEAK_UPD__W 3 -#define B_CE_REG_FR_LEAK_UPD__M 0x7 -#define B_CE_REG_FR_LEAK_UPD_INIT 0x1 - -#define B_CE_REG_FR_LEAK_SH__A 0x182004B -#define B_CE_REG_FR_LEAK_SH__W 3 -#define B_CE_REG_FR_LEAK_SH__M 0x7 -#define B_CE_REG_FR_LEAK_SH_INIT 0x1 - -#define B_CE_PB_RAM__A 0x1830000 - -#define B_CE_NE_RAM__A 0x1840000 - -#define B_EQ_SID 0xE - #define B_EQ_COMM_EXEC__A 0x1C00000 -#define B_EQ_COMM_EXEC__W 3 -#define B_EQ_COMM_EXEC__M 0x7 -#define B_EQ_COMM_EXEC_CTL__B 0 -#define B_EQ_COMM_EXEC_CTL__W 3 -#define B_EQ_COMM_EXEC_CTL__M 0x7 -#define B_EQ_COMM_EXEC_CTL_STOP 0x0 -#define B_EQ_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EQ_COMM_EXEC_CTL_HOLD 0x2 -#define B_EQ_COMM_EXEC_CTL_STEP 0x3 -#define B_EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_EQ_COMM_STATE__A 0x1C00001 -#define B_EQ_COMM_STATE__W 16 -#define B_EQ_COMM_STATE__M 0xFFFF -#define B_EQ_COMM_MB__A 0x1C00002 -#define B_EQ_COMM_MB__W 16 -#define B_EQ_COMM_MB__M 0xFFFF -#define B_EQ_COMM_SERVICE0__A 0x1C00003 -#define B_EQ_COMM_SERVICE0__W 16 -#define B_EQ_COMM_SERVICE0__M 0xFFFF -#define B_EQ_COMM_SERVICE1__A 0x1C00004 -#define B_EQ_COMM_SERVICE1__W 16 -#define B_EQ_COMM_SERVICE1__M 0xFFFF -#define B_EQ_COMM_INT_STA__A 0x1C00007 -#define B_EQ_COMM_INT_STA__W 16 -#define B_EQ_COMM_INT_STA__M 0xFFFF -#define B_EQ_COMM_INT_MSK__A 0x1C00008 -#define B_EQ_COMM_INT_MSK__W 16 -#define B_EQ_COMM_INT_MSK__M 0xFFFF - #define B_EQ_REG_COMM_EXEC__A 0x1C10000 -#define B_EQ_REG_COMM_EXEC__W 3 -#define B_EQ_REG_COMM_EXEC__M 0x7 -#define B_EQ_REG_COMM_EXEC_CTL__B 0 -#define B_EQ_REG_COMM_EXEC_CTL__W 3 -#define B_EQ_REG_COMM_EXEC_CTL__M 0x7 -#define B_EQ_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EQ_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_EQ_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_EQ_REG_COMM_STATE__A 0x1C10001 -#define B_EQ_REG_COMM_STATE__W 4 -#define B_EQ_REG_COMM_STATE__M 0xF - #define B_EQ_REG_COMM_MB__A 0x1C10002 -#define B_EQ_REG_COMM_MB__W 6 -#define B_EQ_REG_COMM_MB__M 0x3F -#define B_EQ_REG_COMM_MB_CTR__B 0 -#define B_EQ_REG_COMM_MB_CTR__W 1 -#define B_EQ_REG_COMM_MB_CTR__M 0x1 -#define B_EQ_REG_COMM_MB_CTR_OFF 0x0 -#define B_EQ_REG_COMM_MB_CTR_ON 0x1 -#define B_EQ_REG_COMM_MB_OBS__B 1 -#define B_EQ_REG_COMM_MB_OBS__W 1 -#define B_EQ_REG_COMM_MB_OBS__M 0x2 -#define B_EQ_REG_COMM_MB_OBS_OFF 0x0 -#define B_EQ_REG_COMM_MB_OBS_ON 0x2 -#define B_EQ_REG_COMM_MB_CTR_MUX__B 2 -#define B_EQ_REG_COMM_MB_CTR_MUX__W 2 -#define B_EQ_REG_COMM_MB_CTR_MUX__M 0xC -#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0 -#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4 -#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8 -#define B_EQ_REG_COMM_MB_OBS_MUX__B 4 -#define B_EQ_REG_COMM_MB_OBS_MUX__W 2 -#define B_EQ_REG_COMM_MB_OBS_MUX__M 0x30 -#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0 -#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10 -#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20 -#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30 - -#define B_EQ_REG_COMM_SERVICE0__A 0x1C10003 -#define B_EQ_REG_COMM_SERVICE0__W 10 -#define B_EQ_REG_COMM_SERVICE0__M 0x3FF - -#define B_EQ_REG_COMM_SERVICE1__A 0x1C10004 -#define B_EQ_REG_COMM_SERVICE1__W 11 -#define B_EQ_REG_COMM_SERVICE1__M 0x7FF - -#define B_EQ_REG_COMM_INT_STA__A 0x1C10007 -#define B_EQ_REG_COMM_INT_STA__W 2 -#define B_EQ_REG_COMM_INT_STA__M 0x3 -#define B_EQ_REG_COMM_INT_STA_TPS_RDY__B 0 -#define B_EQ_REG_COMM_INT_STA_TPS_RDY__W 1 -#define B_EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1 -#define B_EQ_REG_COMM_INT_STA_ERR_RDY__B 1 -#define B_EQ_REG_COMM_INT_STA_ERR_RDY__W 1 -#define B_EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2 - -#define B_EQ_REG_COMM_INT_MSK__A 0x1C10008 -#define B_EQ_REG_COMM_INT_MSK__W 2 -#define B_EQ_REG_COMM_INT_MSK__M 0x3 -#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__B 0 -#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__W 1 -#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1 -#define B_EQ_REG_COMM_INT_MSK_MER_RDY__B 1 -#define B_EQ_REG_COMM_INT_MSK_MER_RDY__W 1 -#define B_EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2 - -#define B_EQ_REG_IS_MODE__A 0x1C10014 -#define B_EQ_REG_IS_MODE__W 4 -#define B_EQ_REG_IS_MODE__M 0xF -#define B_EQ_REG_IS_MODE_INIT 0x0 - -#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__B 0 -#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__W 1 -#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1 -#define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0 -#define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1 - -#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__B 1 -#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__W 1 -#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2 -#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0 -#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2 - #define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015 -#define B_EQ_REG_IS_GAIN_MAN__W 10 -#define B_EQ_REG_IS_GAIN_MAN__M 0x3FF -#define B_EQ_REG_IS_GAIN_MAN_INIT 0x114 - #define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016 -#define B_EQ_REG_IS_GAIN_EXP__W 5 -#define B_EQ_REG_IS_GAIN_EXP__M 0x1F -#define B_EQ_REG_IS_GAIN_EXP_INIT 0x5 - #define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017 -#define B_EQ_REG_IS_CLIP_EXP__W 5 -#define B_EQ_REG_IS_CLIP_EXP__M 0x1F -#define B_EQ_REG_IS_CLIP_EXP_INIT 0x10 - -#define B_EQ_REG_DV_MODE__A 0x1C1001E -#define B_EQ_REG_DV_MODE__W 4 -#define B_EQ_REG_DV_MODE__M 0xF -#define B_EQ_REG_DV_MODE_INIT 0xF - -#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__B 0 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__W 1 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1 - -#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__B 1 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__W 1 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0 -#define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2 - -#define B_EQ_REG_DV_MODE_CLP_REA_ENA__B 2 -#define B_EQ_REG_DV_MODE_CLP_REA_ENA__W 1 -#define B_EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4 -#define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0 -#define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4 - -#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__B 3 -#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__W 1 -#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8 -#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0 -#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8 - -#define B_EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F -#define B_EQ_REG_DV_POS_CLIP_DAT__W 16 -#define B_EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF - -#define B_EQ_REG_SN_MODE__A 0x1C10028 -#define B_EQ_REG_SN_MODE__W 8 -#define B_EQ_REG_SN_MODE__M 0xFF -#define B_EQ_REG_SN_MODE_INIT 0x18 - -#define B_EQ_REG_SN_MODE_MODE_0__B 0 -#define B_EQ_REG_SN_MODE_MODE_0__W 1 -#define B_EQ_REG_SN_MODE_MODE_0__M 0x1 -#define B_EQ_REG_SN_MODE_MODE_0_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_0_ENABLE 0x1 - -#define B_EQ_REG_SN_MODE_MODE_1__B 1 -#define B_EQ_REG_SN_MODE_MODE_1__W 1 -#define B_EQ_REG_SN_MODE_MODE_1__M 0x2 -#define B_EQ_REG_SN_MODE_MODE_1_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_1_ENABLE 0x2 - -#define B_EQ_REG_SN_MODE_MODE_2__B 2 -#define B_EQ_REG_SN_MODE_MODE_2__W 1 -#define B_EQ_REG_SN_MODE_MODE_2__M 0x4 -#define B_EQ_REG_SN_MODE_MODE_2_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_2_ENABLE 0x4 - -#define B_EQ_REG_SN_MODE_MODE_3__B 3 -#define B_EQ_REG_SN_MODE_MODE_3__W 1 -#define B_EQ_REG_SN_MODE_MODE_3__M 0x8 -#define B_EQ_REG_SN_MODE_MODE_3_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_3_ENABLE 0x8 - -#define B_EQ_REG_SN_MODE_MODE_4__B 4 -#define B_EQ_REG_SN_MODE_MODE_4__W 1 -#define B_EQ_REG_SN_MODE_MODE_4__M 0x10 -#define B_EQ_REG_SN_MODE_MODE_4_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_4_ENABLE 0x10 - -#define B_EQ_REG_SN_MODE_MODE_5__B 5 -#define B_EQ_REG_SN_MODE_MODE_5__W 1 -#define B_EQ_REG_SN_MODE_MODE_5__M 0x20 -#define B_EQ_REG_SN_MODE_MODE_5_DISABLE 0x0 -#define B_EQ_REG_SN_MODE_MODE_5_ENABLE 0x20 - -#define B_EQ_REG_SN_MODE_MODE_6__B 6 -#define B_EQ_REG_SN_MODE_MODE_6__W 1 -#define B_EQ_REG_SN_MODE_MODE_6__M 0x40 -#define B_EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0 -#define B_EQ_REG_SN_MODE_MODE_6_STATIC 0x40 - -#define B_EQ_REG_SN_MODE_MODE_7__B 7 -#define B_EQ_REG_SN_MODE_MODE_7__W 1 -#define B_EQ_REG_SN_MODE_MODE_7__M 0x80 -#define B_EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0 -#define B_EQ_REG_SN_MODE_MODE_7_STATIC 0x80 - -#define B_EQ_REG_SN_PFIX__A 0x1C10029 -#define B_EQ_REG_SN_PFIX__W 8 -#define B_EQ_REG_SN_PFIX__M 0xFF -#define B_EQ_REG_SN_PFIX_INIT 0x0 - #define B_EQ_REG_SN_CEGAIN__A 0x1C1002A -#define B_EQ_REG_SN_CEGAIN__W 8 -#define B_EQ_REG_SN_CEGAIN__M 0xFF -#define B_EQ_REG_SN_CEGAIN_INIT 0x30 - #define B_EQ_REG_SN_OFFSET__A 0x1C1002B -#define B_EQ_REG_SN_OFFSET__W 6 -#define B_EQ_REG_SN_OFFSET__M 0x3F -#define B_EQ_REG_SN_OFFSET_INIT 0x39 - -#define B_EQ_REG_SN_NULLIFY__A 0x1C1002C -#define B_EQ_REG_SN_NULLIFY__W 6 -#define B_EQ_REG_SN_NULLIFY__M 0x3F -#define B_EQ_REG_SN_NULLIFY_INIT 0x0 - -#define B_EQ_REG_SN_SQUASH__A 0x1C1002D -#define B_EQ_REG_SN_SQUASH__W 10 -#define B_EQ_REG_SN_SQUASH__M 0x3FF -#define B_EQ_REG_SN_SQUASH_INIT 0x7 - -#define B_EQ_REG_SN_SQUASH_MAN__B 0 -#define B_EQ_REG_SN_SQUASH_MAN__W 6 -#define B_EQ_REG_SN_SQUASH_MAN__M 0x3F - -#define B_EQ_REG_SN_SQUASH_EXP__B 6 -#define B_EQ_REG_SN_SQUASH_EXP__W 4 -#define B_EQ_REG_SN_SQUASH_EXP__M 0x3C0 - #define B_EQ_REG_RC_SEL_CAR__A 0x1C10032 -#define B_EQ_REG_RC_SEL_CAR__W 8 -#define B_EQ_REG_RC_SEL_CAR__M 0xFF #define B_EQ_REG_RC_SEL_CAR_INIT 0x2 -#define B_EQ_REG_RC_SEL_CAR_DIV__B 0 -#define B_EQ_REG_RC_SEL_CAR_DIV__W 1 -#define B_EQ_REG_RC_SEL_CAR_DIV__M 0x1 -#define B_EQ_REG_RC_SEL_CAR_DIV_OFF 0x0 #define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1 - -#define B_EQ_REG_RC_SEL_CAR_PASS__B 1 -#define B_EQ_REG_RC_SEL_CAR_PASS__W 2 -#define B_EQ_REG_RC_SEL_CAR_PASS__M 0x6 #define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0 #define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2 -#define B_EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4 -#define B_EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6 - -#define B_EQ_REG_RC_SEL_CAR_LOCAL__B 3 -#define B_EQ_REG_RC_SEL_CAR_LOCAL__W 2 -#define B_EQ_REG_RC_SEL_CAR_LOCAL__M 0x18 #define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0 #define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8 -#define B_EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10 -#define B_EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18 - -#define B_EQ_REG_RC_SEL_CAR_MEAS__B 5 -#define B_EQ_REG_RC_SEL_CAR_MEAS__W 2 -#define B_EQ_REG_RC_SEL_CAR_MEAS__M 0x60 #define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0 #define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20 -#define B_EQ_REG_RC_SEL_CAR_MEAS_C_DRI 0x40 -#define B_EQ_REG_RC_SEL_CAR_MEAS_D_CC 0x60 - -#define B_EQ_REG_RC_SEL_CAR_FFTMODE__B 7 -#define B_EQ_REG_RC_SEL_CAR_FFTMODE__W 1 #define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80 -#define B_EQ_REG_RC_SEL_CAR_FFTMODE_2K 0x0 -#define B_EQ_REG_RC_SEL_CAR_FFTMODE_8K 0x80 - -#define B_EQ_REG_RC_STS__A 0x1C10033 -#define B_EQ_REG_RC_STS__W 14 -#define B_EQ_REG_RC_STS__M 0x3FFF - -#define B_EQ_REG_RC_STS_DIFF__B 0 -#define B_EQ_REG_RC_STS_DIFF__W 9 -#define B_EQ_REG_RC_STS_DIFF__M 0x1FF - -#define B_EQ_REG_RC_STS_FIRST__B 9 -#define B_EQ_REG_RC_STS_FIRST__W 1 -#define B_EQ_REG_RC_STS_FIRST__M 0x200 -#define B_EQ_REG_RC_STS_FIRST_A_CE 0x0 -#define B_EQ_REG_RC_STS_FIRST_B_DRI 0x200 - -#define B_EQ_REG_RC_STS_SELEC__B 10 -#define B_EQ_REG_RC_STS_SELEC__W 1 -#define B_EQ_REG_RC_STS_SELEC__M 0x400 -#define B_EQ_REG_RC_STS_SELEC_A_CE 0x0 -#define B_EQ_REG_RC_STS_SELEC_B_DRI 0x400 - -#define B_EQ_REG_RC_STS_OVERFLOW__B 11 -#define B_EQ_REG_RC_STS_OVERFLOW__W 1 -#define B_EQ_REG_RC_STS_OVERFLOW__M 0x800 -#define B_EQ_REG_RC_STS_OVERFLOW_NO 0x0 -#define B_EQ_REG_RC_STS_OVERFLOW_YES 0x800 - -#define B_EQ_REG_RC_STS_LOC_PRS__B 12 -#define B_EQ_REG_RC_STS_LOC_PRS__W 1 -#define B_EQ_REG_RC_STS_LOC_PRS__M 0x1000 -#define B_EQ_REG_RC_STS_LOC_PRS_NO 0x0 -#define B_EQ_REG_RC_STS_LOC_PRS_YES 0x1000 - -#define B_EQ_REG_RC_STS_DRI_PRS__B 13 -#define B_EQ_REG_RC_STS_DRI_PRS__W 1 -#define B_EQ_REG_RC_STS_DRI_PRS__M 0x2000 -#define B_EQ_REG_RC_STS_DRI_PRS_NO 0x0 -#define B_EQ_REG_RC_STS_DRI_PRS_YES 0x2000 - #define B_EQ_REG_OT_CONST__A 0x1C10046 -#define B_EQ_REG_OT_CONST__W 2 -#define B_EQ_REG_OT_CONST__M 0x3 -#define B_EQ_REG_OT_CONST_INIT 0x2 - -#define B_EQ_REG_OT_ALPHA__A 0x1C10047 -#define B_EQ_REG_OT_ALPHA__W 2 -#define B_EQ_REG_OT_ALPHA__M 0x3 -#define B_EQ_REG_OT_ALPHA_INIT 0x0 - -#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 -#define B_EQ_REG_OT_QNT_THRES0__W 5 -#define B_EQ_REG_OT_QNT_THRES0__M 0x1F -#define B_EQ_REG_OT_QNT_THRES0_INIT 0x1E - -#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 -#define B_EQ_REG_OT_QNT_THRES1__W 5 -#define B_EQ_REG_OT_QNT_THRES1__M 0x1F -#define B_EQ_REG_OT_QNT_THRES1_INIT 0x1F - -#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A -#define B_EQ_REG_OT_CSI_STEP__W 4 -#define B_EQ_REG_OT_CSI_STEP__M 0xF -#define B_EQ_REG_OT_CSI_STEP_INIT 0x5 - -#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B -#define B_EQ_REG_OT_CSI_OFFSET__W 7 -#define B_EQ_REG_OT_CSI_OFFSET__M 0x7F -#define B_EQ_REG_OT_CSI_OFFSET_INIT 0x5 - -#define B_EQ_REG_OT_CSI_GAIN__A 0x1C1004C -#define B_EQ_REG_OT_CSI_GAIN__W 8 -#define B_EQ_REG_OT_CSI_GAIN__M 0xFF -#define B_EQ_REG_OT_CSI_GAIN_INIT 0x2B - -#define B_EQ_REG_OT_CSI_MEAN__A 0x1C1004D -#define B_EQ_REG_OT_CSI_MEAN__W 7 -#define B_EQ_REG_OT_CSI_MEAN__M 0x7F - -#define B_EQ_REG_OT_CSI_VARIANCE__A 0x1C1004E -#define B_EQ_REG_OT_CSI_VARIANCE__W 7 -#define B_EQ_REG_OT_CSI_VARIANCE__M 0x7F - -#define B_EQ_REG_TD_TPS_INIT__A 0x1C10050 -#define B_EQ_REG_TD_TPS_INIT__W 1 -#define B_EQ_REG_TD_TPS_INIT__M 0x1 -#define B_EQ_REG_TD_TPS_INIT_INIT 0x0 -#define B_EQ_REG_TD_TPS_INIT_POS 0x0 -#define B_EQ_REG_TD_TPS_INIT_NEG 0x1 - -#define B_EQ_REG_TD_TPS_SYNC__A 0x1C10051 -#define B_EQ_REG_TD_TPS_SYNC__W 16 -#define B_EQ_REG_TD_TPS_SYNC__M 0xFFFF -#define B_EQ_REG_TD_TPS_SYNC_INIT 0x0 -#define B_EQ_REG_TD_TPS_SYNC_ODD 0x35EE -#define B_EQ_REG_TD_TPS_SYNC_EVEN 0xCA11 - -#define B_EQ_REG_TD_TPS_LEN__A 0x1C10052 -#define B_EQ_REG_TD_TPS_LEN__W 6 -#define B_EQ_REG_TD_TPS_LEN__M 0x3F -#define B_EQ_REG_TD_TPS_LEN_INIT 0x0 -#define B_EQ_REG_TD_TPS_LEN_DEF 0x17 -#define B_EQ_REG_TD_TPS_LEN_ID_SUP 0x1F - -#define B_EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053 -#define B_EQ_REG_TD_TPS_FRM_NMB__W 2 -#define B_EQ_REG_TD_TPS_FRM_NMB__M 0x3 -#define B_EQ_REG_TD_TPS_FRM_NMB_INIT 0x0 -#define B_EQ_REG_TD_TPS_FRM_NMB_1 0x0 -#define B_EQ_REG_TD_TPS_FRM_NMB_2 0x1 -#define B_EQ_REG_TD_TPS_FRM_NMB_3 0x2 -#define B_EQ_REG_TD_TPS_FRM_NMB_4 0x3 - -#define B_EQ_REG_TD_TPS_CONST__A 0x1C10054 -#define B_EQ_REG_TD_TPS_CONST__W 2 -#define B_EQ_REG_TD_TPS_CONST__M 0x3 -#define B_EQ_REG_TD_TPS_CONST_INIT 0x0 -#define B_EQ_REG_TD_TPS_CONST_QPSK 0x0 -#define B_EQ_REG_TD_TPS_CONST_16QAM 0x1 -#define B_EQ_REG_TD_TPS_CONST_64QAM 0x2 - -#define B_EQ_REG_TD_TPS_HINFO__A 0x1C10055 -#define B_EQ_REG_TD_TPS_HINFO__W 3 -#define B_EQ_REG_TD_TPS_HINFO__M 0x7 -#define B_EQ_REG_TD_TPS_HINFO_INIT 0x0 -#define B_EQ_REG_TD_TPS_HINFO_NH 0x0 -#define B_EQ_REG_TD_TPS_HINFO_H1 0x1 -#define B_EQ_REG_TD_TPS_HINFO_H2 0x2 -#define B_EQ_REG_TD_TPS_HINFO_H4 0x3 - -#define B_EQ_REG_TD_TPS_CODE_HP__A 0x1C10056 -#define B_EQ_REG_TD_TPS_CODE_HP__W 3 -#define B_EQ_REG_TD_TPS_CODE_HP__M 0x7 -#define B_EQ_REG_TD_TPS_CODE_HP_INIT 0x0 -#define B_EQ_REG_TD_TPS_CODE_HP_1_2 0x0 -#define B_EQ_REG_TD_TPS_CODE_HP_2_3 0x1 -#define B_EQ_REG_TD_TPS_CODE_HP_3_4 0x2 -#define B_EQ_REG_TD_TPS_CODE_HP_5_6 0x3 -#define B_EQ_REG_TD_TPS_CODE_HP_7_8 0x4 - -#define B_EQ_REG_TD_TPS_CODE_LP__A 0x1C10057 -#define B_EQ_REG_TD_TPS_CODE_LP__W 3 -#define B_EQ_REG_TD_TPS_CODE_LP__M 0x7 -#define B_EQ_REG_TD_TPS_CODE_LP_INIT 0x0 -#define B_EQ_REG_TD_TPS_CODE_LP_1_2 0x0 -#define B_EQ_REG_TD_TPS_CODE_LP_2_3 0x1 -#define B_EQ_REG_TD_TPS_CODE_LP_3_4 0x2 -#define B_EQ_REG_TD_TPS_CODE_LP_5_6 0x3 -#define B_EQ_REG_TD_TPS_CODE_LP_7_8 0x4 - -#define B_EQ_REG_TD_TPS_GUARD__A 0x1C10058 -#define B_EQ_REG_TD_TPS_GUARD__W 2 -#define B_EQ_REG_TD_TPS_GUARD__M 0x3 -#define B_EQ_REG_TD_TPS_GUARD_INIT 0x0 -#define B_EQ_REG_TD_TPS_GUARD_32 0x0 -#define B_EQ_REG_TD_TPS_GUARD_16 0x1 -#define B_EQ_REG_TD_TPS_GUARD_08 0x2 -#define B_EQ_REG_TD_TPS_GUARD_04 0x3 - -#define B_EQ_REG_TD_TPS_TR_MODE__A 0x1C10059 -#define B_EQ_REG_TD_TPS_TR_MODE__W 2 -#define B_EQ_REG_TD_TPS_TR_MODE__M 0x3 -#define B_EQ_REG_TD_TPS_TR_MODE_INIT 0x0 -#define B_EQ_REG_TD_TPS_TR_MODE_2K 0x0 -#define B_EQ_REG_TD_TPS_TR_MODE_8K 0x1 - -#define B_EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A -#define B_EQ_REG_TD_TPS_CELL_ID_HI__W 8 -#define B_EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF -#define B_EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0 - -#define B_EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B -#define B_EQ_REG_TD_TPS_CELL_ID_LO__W 8 -#define B_EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF -#define B_EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0 - -#define B_EQ_REG_TD_TPS_RSV__A 0x1C1005C -#define B_EQ_REG_TD_TPS_RSV__W 6 -#define B_EQ_REG_TD_TPS_RSV__M 0x3F -#define B_EQ_REG_TD_TPS_RSV_INIT 0x0 - -#define B_EQ_REG_TD_TPS_BCH__A 0x1C1005D -#define B_EQ_REG_TD_TPS_BCH__W 14 -#define B_EQ_REG_TD_TPS_BCH__M 0x3FFF -#define B_EQ_REG_TD_TPS_BCH_INIT 0x0 - -#define B_EQ_REG_TD_SQR_ERR_I__A 0x1C1005E -#define B_EQ_REG_TD_SQR_ERR_I__W 16 -#define B_EQ_REG_TD_SQR_ERR_I__M 0xFFFF -#define B_EQ_REG_TD_SQR_ERR_I_INIT 0x0 - -#define B_EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F -#define B_EQ_REG_TD_SQR_ERR_Q__W 16 -#define B_EQ_REG_TD_SQR_ERR_Q__M 0xFFFF -#define B_EQ_REG_TD_SQR_ERR_Q_INIT 0x0 - -#define B_EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060 -#define B_EQ_REG_TD_SQR_ERR_EXP__W 4 -#define B_EQ_REG_TD_SQR_ERR_EXP__M 0xF -#define B_EQ_REG_TD_SQR_ERR_EXP_INIT 0x0 - +#define B_EQ_REG_OT_ALPHA__A 0x1C10047 +#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048 +#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049 +#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A +#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B #define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061 -#define B_EQ_REG_TD_REQ_SMB_CNT__W 16 -#define B_EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF -#define B_EQ_REG_TD_REQ_SMB_CNT_INIT 0x200 - #define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062 -#define B_EQ_REG_TD_TPS_PWR_OFS__W 16 -#define B_EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF -#define B_EQ_REG_TD_TPS_PWR_OFS_INIT 0x19F - -#define B_EC_COMM_EXEC__A 0x2000000 -#define B_EC_COMM_EXEC__W 3 -#define B_EC_COMM_EXEC__M 0x7 -#define B_EC_COMM_EXEC_CTL__B 0 -#define B_EC_COMM_EXEC_CTL__W 3 -#define B_EC_COMM_EXEC_CTL__M 0x7 -#define B_EC_COMM_EXEC_CTL_STOP 0x0 -#define B_EC_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EC_COMM_EXEC_CTL_HOLD 0x2 -#define B_EC_COMM_EXEC_CTL_STEP 0x3 -#define B_EC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_EC_COMM_STATE__A 0x2000001 -#define B_EC_COMM_STATE__W 16 -#define B_EC_COMM_STATE__M 0xFFFF -#define B_EC_COMM_MB__A 0x2000002 -#define B_EC_COMM_MB__W 16 -#define B_EC_COMM_MB__M 0xFFFF -#define B_EC_COMM_SERVICE0__A 0x2000003 -#define B_EC_COMM_SERVICE0__W 16 -#define B_EC_COMM_SERVICE0__M 0xFFFF -#define B_EC_COMM_SERVICE1__A 0x2000004 -#define B_EC_COMM_SERVICE1__W 16 -#define B_EC_COMM_SERVICE1__M 0xFFFF -#define B_EC_COMM_INT_STA__A 0x2000007 -#define B_EC_COMM_INT_STA__W 16 -#define B_EC_COMM_INT_STA__M 0xFFFF -#define B_EC_COMM_INT_MSK__A 0x2000008 -#define B_EC_COMM_INT_MSK__W 16 -#define B_EC_COMM_INT_MSK__M 0xFFFF - -#define B_EC_SB_SID 0x16 - #define B_EC_SB_REG_COMM_EXEC__A 0x2010000 -#define B_EC_SB_REG_COMM_EXEC__W 3 -#define B_EC_SB_REG_COMM_EXEC__M 0x7 -#define B_EC_SB_REG_COMM_EXEC_CTL__B 0 -#define B_EC_SB_REG_COMM_EXEC_CTL__W 3 -#define B_EC_SB_REG_COMM_EXEC_CTL__M 0x7 -#define B_EC_SB_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define B_EC_SB_REG_COMM_STATE__A 0x2010001 -#define B_EC_SB_REG_COMM_STATE__W 4 -#define B_EC_SB_REG_COMM_STATE__M 0xF -#define B_EC_SB_REG_COMM_MB__A 0x2010002 -#define B_EC_SB_REG_COMM_MB__W 2 -#define B_EC_SB_REG_COMM_MB__M 0x3 -#define B_EC_SB_REG_COMM_MB_CTR__B 0 -#define B_EC_SB_REG_COMM_MB_CTR__W 1 -#define B_EC_SB_REG_COMM_MB_CTR__M 0x1 -#define B_EC_SB_REG_COMM_MB_CTR_OFF 0x0 -#define B_EC_SB_REG_COMM_MB_CTR_ON 0x1 -#define B_EC_SB_REG_COMM_MB_OBS__B 1 -#define B_EC_SB_REG_COMM_MB_OBS__W 1 -#define B_EC_SB_REG_COMM_MB_OBS__M 0x2 -#define B_EC_SB_REG_COMM_MB_OBS_OFF 0x0 -#define B_EC_SB_REG_COMM_MB_OBS_ON 0x2 - #define B_EC_SB_REG_TR_MODE__A 0x2010010 -#define B_EC_SB_REG_TR_MODE__W 1 -#define B_EC_SB_REG_TR_MODE__M 0x1 -#define B_EC_SB_REG_TR_MODE_INIT 0x0 #define B_EC_SB_REG_TR_MODE_8K 0x0 #define B_EC_SB_REG_TR_MODE_2K 0x1 - #define B_EC_SB_REG_CONST__A 0x2010011 -#define B_EC_SB_REG_CONST__W 2 -#define B_EC_SB_REG_CONST__M 0x3 -#define B_EC_SB_REG_CONST_INIT 0x2 #define B_EC_SB_REG_CONST_QPSK 0x0 #define B_EC_SB_REG_CONST_16QAM 0x1 #define B_EC_SB_REG_CONST_64QAM 0x2 - #define B_EC_SB_REG_ALPHA__A 0x2010012 -#define B_EC_SB_REG_ALPHA__W 3 -#define B_EC_SB_REG_ALPHA__M 0x7 - -#define B_EC_SB_REG_ALPHA_INIT 0x0 - -#define B_EC_SB_REG_ALPHA_NH 0x0 - -#define B_EC_SB_REG_ALPHA_H1 0x1 - -#define B_EC_SB_REG_ALPHA_H2 0x2 - -#define B_EC_SB_REG_ALPHA_H4 0x3 - #define B_EC_SB_REG_PRIOR__A 0x2010013 -#define B_EC_SB_REG_PRIOR__W 1 -#define B_EC_SB_REG_PRIOR__M 0x1 -#define B_EC_SB_REG_PRIOR_INIT 0x0 #define B_EC_SB_REG_PRIOR_HI 0x0 #define B_EC_SB_REG_PRIOR_LO 0x1 - #define B_EC_SB_REG_CSI_HI__A 0x2010014 -#define B_EC_SB_REG_CSI_HI__W 5 -#define B_EC_SB_REG_CSI_HI__M 0x1F -#define B_EC_SB_REG_CSI_HI_INIT 0x1F -#define B_EC_SB_REG_CSI_HI_MAX 0x1F -#define B_EC_SB_REG_CSI_HI_MIN 0x0 -#define B_EC_SB_REG_CSI_HI_TAG 0x0 - #define B_EC_SB_REG_CSI_LO__A 0x2010015 -#define B_EC_SB_REG_CSI_LO__W 5 -#define B_EC_SB_REG_CSI_LO__M 0x1F -#define B_EC_SB_REG_CSI_LO_INIT 0x1E -#define B_EC_SB_REG_CSI_LO_MAX 0x1F -#define B_EC_SB_REG_CSI_LO_MIN 0x0 -#define B_EC_SB_REG_CSI_LO_TAG 0x0 - #define B_EC_SB_REG_SMB_TGL__A 0x2010016 -#define B_EC_SB_REG_SMB_TGL__W 1 -#define B_EC_SB_REG_SMB_TGL__M 0x1 -#define B_EC_SB_REG_SMB_TGL_OFF 0x0 -#define B_EC_SB_REG_SMB_TGL_ON 0x1 -#define B_EC_SB_REG_SMB_TGL_INIT 0x1 - #define B_EC_SB_REG_SNR_HI__A 0x2010017 -#define B_EC_SB_REG_SNR_HI__W 8 -#define B_EC_SB_REG_SNR_HI__M 0xFF -#define B_EC_SB_REG_SNR_HI_INIT 0x6E -#define B_EC_SB_REG_SNR_HI_MAX 0xFF -#define B_EC_SB_REG_SNR_HI_MIN 0x0 -#define B_EC_SB_REG_SNR_HI_TAG 0x0 - #define B_EC_SB_REG_SNR_MID__A 0x2010018 -#define B_EC_SB_REG_SNR_MID__W 8 -#define B_EC_SB_REG_SNR_MID__M 0xFF -#define B_EC_SB_REG_SNR_MID_INIT 0x6C -#define B_EC_SB_REG_SNR_MID_MAX 0xFF -#define B_EC_SB_REG_SNR_MID_MIN 0x0 -#define B_EC_SB_REG_SNR_MID_TAG 0x0 - #define B_EC_SB_REG_SNR_LO__A 0x2010019 -#define B_EC_SB_REG_SNR_LO__W 8 -#define B_EC_SB_REG_SNR_LO__M 0xFF -#define B_EC_SB_REG_SNR_LO_INIT 0x68 -#define B_EC_SB_REG_SNR_LO_MAX 0xFF -#define B_EC_SB_REG_SNR_LO_MIN 0x0 -#define B_EC_SB_REG_SNR_LO_TAG 0x0 - #define B_EC_SB_REG_SCALE_MSB__A 0x201001A -#define B_EC_SB_REG_SCALE_MSB__W 6 -#define B_EC_SB_REG_SCALE_MSB__M 0x3F -#define B_EC_SB_REG_SCALE_MSB_INIT 0x30 -#define B_EC_SB_REG_SCALE_MSB_MAX 0x3F - #define B_EC_SB_REG_SCALE_BIT2__A 0x201001B -#define B_EC_SB_REG_SCALE_BIT2__W 6 -#define B_EC_SB_REG_SCALE_BIT2__M 0x3F -#define B_EC_SB_REG_SCALE_BIT2_INIT 0xC -#define B_EC_SB_REG_SCALE_BIT2_MAX 0x3F - #define B_EC_SB_REG_SCALE_LSB__A 0x201001C -#define B_EC_SB_REG_SCALE_LSB__W 6 -#define B_EC_SB_REG_SCALE_LSB__M 0x3F -#define B_EC_SB_REG_SCALE_LSB_INIT 0x3 -#define B_EC_SB_REG_SCALE_LSB_MAX 0x3F - #define B_EC_SB_REG_CSI_OFS0__A 0x201001D -#define B_EC_SB_REG_CSI_OFS0__W 4 -#define B_EC_SB_REG_CSI_OFS0__M 0xF -#define B_EC_SB_REG_CSI_OFS0_INIT 0x4 - #define B_EC_SB_REG_CSI_OFS1__A 0x201001E -#define B_EC_SB_REG_CSI_OFS1__W 4 -#define B_EC_SB_REG_CSI_OFS1__M 0xF -#define B_EC_SB_REG_CSI_OFS1_INIT 0x1 - #define B_EC_SB_REG_CSI_OFS2__A 0x201001F -#define B_EC_SB_REG_CSI_OFS2__W 4 -#define B_EC_SB_REG_CSI_OFS2__M 0xF -#define B_EC_SB_REG_CSI_OFS2_INIT 0x2 - -#define B_EC_SB_REG_MAX0__A 0x2010020 -#define B_EC_SB_REG_MAX0__W 6 -#define B_EC_SB_REG_MAX0__M 0x3F -#define B_EC_SB_REG_MAX0_INIT 0x3F - -#define B_EC_SB_REG_MAX1__A 0x2010021 -#define B_EC_SB_REG_MAX1__W 6 -#define B_EC_SB_REG_MAX1__M 0x3F -#define B_EC_SB_REG_MAX1_INIT 0x3F - -#define B_EC_SB_REG_MAX2__A 0x2010022 -#define B_EC_SB_REG_MAX2__W 6 -#define B_EC_SB_REG_MAX2__M 0x3F -#define B_EC_SB_REG_MAX2_INIT 0x3F - -#define B_EC_SB_REG_CSI_DIS__A 0x2010023 -#define B_EC_SB_REG_CSI_DIS__W 1 -#define B_EC_SB_REG_CSI_DIS__M 0x1 -#define B_EC_SB_REG_CSI_DIS_INIT 0x0 - -#define B_EC_SB_SD_RAM__A 0x2020000 - -#define B_EC_SB_BD0_RAM__A 0x2030000 - -#define B_EC_SB_BD1_RAM__A 0x2040000 - -#define B_EC_VD_SID 0x17 - #define B_EC_VD_REG_COMM_EXEC__A 0x2090000 -#define B_EC_VD_REG_COMM_EXEC__W 3 -#define B_EC_VD_REG_COMM_EXEC__M 0x7 -#define B_EC_VD_REG_COMM_EXEC_CTL__B 0 -#define B_EC_VD_REG_COMM_EXEC_CTL__W 3 -#define B_EC_VD_REG_COMM_EXEC_CTL__M 0x7 -#define B_EC_VD_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define B_EC_VD_REG_COMM_STATE__A 0x2090001 -#define B_EC_VD_REG_COMM_STATE__W 4 -#define B_EC_VD_REG_COMM_STATE__M 0xF -#define B_EC_VD_REG_COMM_MB__A 0x2090002 -#define B_EC_VD_REG_COMM_MB__W 2 -#define B_EC_VD_REG_COMM_MB__M 0x3 -#define B_EC_VD_REG_COMM_MB_CTR__B 0 -#define B_EC_VD_REG_COMM_MB_CTR__W 1 -#define B_EC_VD_REG_COMM_MB_CTR__M 0x1 -#define B_EC_VD_REG_COMM_MB_CTR_OFF 0x0 -#define B_EC_VD_REG_COMM_MB_CTR_ON 0x1 -#define B_EC_VD_REG_COMM_MB_OBS__B 1 -#define B_EC_VD_REG_COMM_MB_OBS__W 1 -#define B_EC_VD_REG_COMM_MB_OBS__M 0x2 -#define B_EC_VD_REG_COMM_MB_OBS_OFF 0x0 -#define B_EC_VD_REG_COMM_MB_OBS_ON 0x2 - -#define B_EC_VD_REG_COMM_SERVICE0__A 0x2090003 -#define B_EC_VD_REG_COMM_SERVICE0__W 16 -#define B_EC_VD_REG_COMM_SERVICE0__M 0xFFFF -#define B_EC_VD_REG_COMM_SERVICE1__A 0x2090004 -#define B_EC_VD_REG_COMM_SERVICE1__W 16 -#define B_EC_VD_REG_COMM_SERVICE1__M 0xFFFF -#define B_EC_VD_REG_COMM_INT_STA__A 0x2090007 -#define B_EC_VD_REG_COMM_INT_STA__W 1 -#define B_EC_VD_REG_COMM_INT_STA__M 0x1 -#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__B 0 -#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__W 1 -#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1 - -#define B_EC_VD_REG_COMM_INT_MSK__A 0x2090008 -#define B_EC_VD_REG_COMM_INT_MSK__W 1 -#define B_EC_VD_REG_COMM_INT_MSK__M 0x1 -#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0 -#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1 -#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1 - #define B_EC_VD_REG_FORCE__A 0x2090010 -#define B_EC_VD_REG_FORCE__W 2 -#define B_EC_VD_REG_FORCE__M 0x3 -#define B_EC_VD_REG_FORCE_INIT 0x2 -#define B_EC_VD_REG_FORCE_FREE 0x0 -#define B_EC_VD_REG_FORCE_PROP 0x1 -#define B_EC_VD_REG_FORCE_FORCED 0x2 -#define B_EC_VD_REG_FORCE_FIXED 0x3 - #define B_EC_VD_REG_SET_CODERATE__A 0x2090011 -#define B_EC_VD_REG_SET_CODERATE__W 3 -#define B_EC_VD_REG_SET_CODERATE__M 0x7 -#define B_EC_VD_REG_SET_CODERATE_INIT 0x1 #define B_EC_VD_REG_SET_CODERATE_C1_2 0x0 #define B_EC_VD_REG_SET_CODERATE_C2_3 0x1 #define B_EC_VD_REG_SET_CODERATE_C3_4 0x2 #define B_EC_VD_REG_SET_CODERATE_C5_6 0x3 #define B_EC_VD_REG_SET_CODERATE_C7_8 0x4 - #define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012 -#define B_EC_VD_REG_REQ_SMB_CNT__W 16 -#define B_EC_VD_REG_REQ_SMB_CNT__M 0xFFFF -#define B_EC_VD_REG_REQ_SMB_CNT_INIT 0x1 - -#define B_EC_VD_REG_REQ_BIT_CNT__A 0x2090013 -#define B_EC_VD_REG_REQ_BIT_CNT__W 16 -#define B_EC_VD_REG_REQ_BIT_CNT__M 0xFFFF -#define B_EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF - #define B_EC_VD_REG_RLK_ENA__A 0x2090014 -#define B_EC_VD_REG_RLK_ENA__W 1 -#define B_EC_VD_REG_RLK_ENA__M 0x1 -#define B_EC_VD_REG_RLK_ENA_INIT 0x1 -#define B_EC_VD_REG_RLK_ENA_OFF 0x0 -#define B_EC_VD_REG_RLK_ENA_ON 0x1 - -#define B_EC_VD_REG_VAL__A 0x2090015 -#define B_EC_VD_REG_VAL__W 2 -#define B_EC_VD_REG_VAL__M 0x3 -#define B_EC_VD_REG_VAL_INIT 0x0 -#define B_EC_VD_REG_VAL_CODE 0x1 -#define B_EC_VD_REG_VAL_CNT 0x2 - -#define B_EC_VD_REG_GET_CODERATE__A 0x2090016 -#define B_EC_VD_REG_GET_CODERATE__W 3 -#define B_EC_VD_REG_GET_CODERATE__M 0x7 -#define B_EC_VD_REG_GET_CODERATE_INIT 0x0 -#define B_EC_VD_REG_GET_CODERATE_C1_2 0x0 -#define B_EC_VD_REG_GET_CODERATE_C2_3 0x1 -#define B_EC_VD_REG_GET_CODERATE_C3_4 0x2 -#define B_EC_VD_REG_GET_CODERATE_C5_6 0x3 -#define B_EC_VD_REG_GET_CODERATE_C7_8 0x4 - -#define B_EC_VD_REG_ERR_BIT_CNT__A 0x2090017 -#define B_EC_VD_REG_ERR_BIT_CNT__W 16 -#define B_EC_VD_REG_ERR_BIT_CNT__M 0xFFFF -#define B_EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF - -#define B_EC_VD_REG_IN_BIT_CNT__A 0x2090018 -#define B_EC_VD_REG_IN_BIT_CNT__W 16 -#define B_EC_VD_REG_IN_BIT_CNT__M 0xFFFF -#define B_EC_VD_REG_IN_BIT_CNT_INIT 0x0 - -#define B_EC_VD_REG_STS__A 0x2090019 -#define B_EC_VD_REG_STS__W 1 -#define B_EC_VD_REG_STS__M 0x1 -#define B_EC_VD_REG_STS_INIT 0x0 -#define B_EC_VD_REG_STS_NO_LOCK 0x0 -#define B_EC_VD_REG_STS_IN_LOCK 0x1 - -#define B_EC_VD_REG_RLK_CNT__A 0x209001A -#define B_EC_VD_REG_RLK_CNT__W 16 -#define B_EC_VD_REG_RLK_CNT__M 0xFFFF -#define B_EC_VD_REG_RLK_CNT_INIT 0x0 - -#define B_EC_VD_TB0_RAM__A 0x20A0000 - -#define B_EC_VD_TB1_RAM__A 0x20B0000 - -#define B_EC_VD_TB2_RAM__A 0x20C0000 - -#define B_EC_VD_TB3_RAM__A 0x20D0000 - -#define B_EC_VD_RE_RAM__A 0x2100000 - -#define B_EC_OD_SID 0x18 - #define B_EC_OD_REG_COMM_EXEC__A 0x2110000 -#define B_EC_OD_REG_COMM_EXEC__W 3 -#define B_EC_OD_REG_COMM_EXEC__M 0x7 -#define B_EC_OD_REG_COMM_EXEC_CTL__B 0 -#define B_EC_OD_REG_COMM_EXEC_CTL__W 3 -#define B_EC_OD_REG_COMM_EXEC_CTL__M 0x7 -#define B_EC_OD_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_EC_OD_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_EC_OD_REG_COMM_STATE__A 0x2110001 -#define B_EC_OD_REG_COMM_STATE__W 1 -#define B_EC_OD_REG_COMM_STATE__M 0x1 -#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__B 0 -#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__W 1 -#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__M 0x1 - -#define B_EC_OD_REG_COMM_MB__A 0x2110002 -#define B_EC_OD_REG_COMM_MB__W 3 -#define B_EC_OD_REG_COMM_MB__M 0x7 -#define B_EC_OD_REG_COMM_MB_CTR__B 0 -#define B_EC_OD_REG_COMM_MB_CTR__W 1 -#define B_EC_OD_REG_COMM_MB_CTR__M 0x1 -#define B_EC_OD_REG_COMM_MB_CTR_OFF 0x0 -#define B_EC_OD_REG_COMM_MB_CTR_ON 0x1 -#define B_EC_OD_REG_COMM_MB_OBS__B 1 -#define B_EC_OD_REG_COMM_MB_OBS__W 1 -#define B_EC_OD_REG_COMM_MB_OBS__M 0x2 -#define B_EC_OD_REG_COMM_MB_OBS_OFF 0x0 -#define B_EC_OD_REG_COMM_MB_OBS_ON 0x2 - -#define B_EC_OD_REG_COMM_SERVICE0__A 0x2110003 -#define B_EC_OD_REG_COMM_SERVICE0__W 10 -#define B_EC_OD_REG_COMM_SERVICE0__M 0x3FF -#define B_EC_OD_REG_COMM_SERVICE1__A 0x2110004 -#define B_EC_OD_REG_COMM_SERVICE1__W 11 -#define B_EC_OD_REG_COMM_SERVICE1__M 0x7FF - -#define B_EC_OD_REG_COMM_ACTIVATE__A 0x2110005 -#define B_EC_OD_REG_COMM_ACTIVATE__W 2 -#define B_EC_OD_REG_COMM_ACTIVATE__M 0x3 - -#define B_EC_OD_REG_COMM_COUNT__A 0x2110006 -#define B_EC_OD_REG_COMM_COUNT__W 16 -#define B_EC_OD_REG_COMM_COUNT__M 0xFFFF - -#define B_EC_OD_REG_COMM_INT_STA__A 0x2110007 -#define B_EC_OD_REG_COMM_INT_STA__W 2 -#define B_EC_OD_REG_COMM_INT_STA__M 0x3 -#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0 -#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1 -#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1 -#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1 -#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1 -#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2 - -#define B_EC_OD_REG_COMM_INT_MSK__A 0x2110008 -#define B_EC_OD_REG_COMM_INT_MSK__W 2 -#define B_EC_OD_REG_COMM_INT_MSK__M 0x3 -#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0 -#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1 -#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1 -#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1 -#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1 -#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2 - #define B_EC_OD_REG_SYNC__A 0x2110664 -#define B_EC_OD_REG_SYNC__W 12 -#define B_EC_OD_REG_SYNC__M 0xFFF -#define B_EC_OD_REG_SYNC_NR_SYNC__B 0 -#define B_EC_OD_REG_SYNC_NR_SYNC__W 5 -#define B_EC_OD_REG_SYNC_NR_SYNC__M 0x1F -#define B_EC_OD_REG_SYNC_IN_SYNC__B 5 -#define B_EC_OD_REG_SYNC_IN_SYNC__W 4 -#define B_EC_OD_REG_SYNC_IN_SYNC__M 0x1E0 -#define B_EC_OD_REG_SYNC_OUT_SYNC__B 9 -#define B_EC_OD_REG_SYNC_OUT_SYNC__W 3 -#define B_EC_OD_REG_SYNC_OUT_SYNC__M 0xE00 - -#define B_EC_OD_REG_NOSYNC__A 0x2110004 -#define B_EC_OD_REG_NOSYNC__W 8 -#define B_EC_OD_REG_NOSYNC__M 0xFF - #define B_EC_OD_DEINT_RAM__A 0x2120000 - -#define B_EC_RS_SID 0x19 - #define B_EC_RS_REG_COMM_EXEC__A 0x2130000 -#define B_EC_RS_REG_COMM_EXEC__W 3 -#define B_EC_RS_REG_COMM_EXEC__M 0x7 -#define B_EC_RS_REG_COMM_EXEC_CTL__B 0 -#define B_EC_RS_REG_COMM_EXEC_CTL__W 3 -#define B_EC_RS_REG_COMM_EXEC_CTL__M 0x7 -#define B_EC_RS_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2 - -#define B_EC_RS_REG_COMM_STATE__A 0x2130001 -#define B_EC_RS_REG_COMM_STATE__W 4 -#define B_EC_RS_REG_COMM_STATE__M 0xF -#define B_EC_RS_REG_COMM_MB__A 0x2130002 -#define B_EC_RS_REG_COMM_MB__W 2 -#define B_EC_RS_REG_COMM_MB__M 0x3 -#define B_EC_RS_REG_COMM_MB_CTR__B 0 -#define B_EC_RS_REG_COMM_MB_CTR__W 1 -#define B_EC_RS_REG_COMM_MB_CTR__M 0x1 -#define B_EC_RS_REG_COMM_MB_CTR_OFF 0x0 -#define B_EC_RS_REG_COMM_MB_CTR_ON 0x1 -#define B_EC_RS_REG_COMM_MB_OBS__B 1 -#define B_EC_RS_REG_COMM_MB_OBS__W 1 -#define B_EC_RS_REG_COMM_MB_OBS__M 0x2 -#define B_EC_RS_REG_COMM_MB_OBS_OFF 0x0 -#define B_EC_RS_REG_COMM_MB_OBS_ON 0x2 - -#define B_EC_RS_REG_COMM_SERVICE0__A 0x2130003 -#define B_EC_RS_REG_COMM_SERVICE0__W 16 -#define B_EC_RS_REG_COMM_SERVICE0__M 0xFFFF -#define B_EC_RS_REG_COMM_SERVICE1__A 0x2130004 -#define B_EC_RS_REG_COMM_SERVICE1__W 16 -#define B_EC_RS_REG_COMM_SERVICE1__M 0xFFFF -#define B_EC_RS_REG_COMM_INT_STA__A 0x2130007 -#define B_EC_RS_REG_COMM_INT_STA__W 1 -#define B_EC_RS_REG_COMM_INT_STA__M 0x1 -#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__B 0 -#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__W 1 -#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1 - -#define B_EC_RS_REG_COMM_INT_MSK__A 0x2130008 -#define B_EC_RS_REG_COMM_INT_MSK__W 1 -#define B_EC_RS_REG_COMM_INT_MSK__M 0x1 -#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0 -#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1 -#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1 - #define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010 -#define B_EC_RS_REG_REQ_PCK_CNT__W 16 -#define B_EC_RS_REG_REQ_PCK_CNT__M 0xFFFF -#define B_EC_RS_REG_REQ_PCK_CNT_INIT 0x200 - #define B_EC_RS_REG_VAL__A 0x2130011 -#define B_EC_RS_REG_VAL__W 1 -#define B_EC_RS_REG_VAL__M 0x1 -#define B_EC_RS_REG_VAL_INIT 0x0 #define B_EC_RS_REG_VAL_PCK 0x1 - -#define B_EC_RS_REG_ERR_PCK_CNT__A 0x2130012 -#define B_EC_RS_REG_ERR_PCK_CNT__W 16 -#define B_EC_RS_REG_ERR_PCK_CNT__M 0xFFFF -#define B_EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF - -#define B_EC_RS_REG_ERR_SMB_CNT__A 0x2130013 -#define B_EC_RS_REG_ERR_SMB_CNT__W 16 -#define B_EC_RS_REG_ERR_SMB_CNT__M 0xFFFF -#define B_EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF - -#define B_EC_RS_REG_ERR_BIT_CNT__A 0x2130014 -#define B_EC_RS_REG_ERR_BIT_CNT__W 16 -#define B_EC_RS_REG_ERR_BIT_CNT__M 0xFFFF -#define B_EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF - -#define B_EC_RS_REG_IN_PCK_CNT__A 0x2130015 -#define B_EC_RS_REG_IN_PCK_CNT__W 16 -#define B_EC_RS_REG_IN_PCK_CNT__M 0xFFFF -#define B_EC_RS_REG_IN_PCK_CNT_INIT 0x0 - #define B_EC_RS_EC_RAM__A 0x2140000 - -#define B_EC_OC_SID 0x1A - #define B_EC_OC_REG_COMM_EXEC__A 0x2150000 -#define B_EC_OC_REG_COMM_EXEC__W 3 -#define B_EC_OC_REG_COMM_EXEC__M 0x7 -#define B_EC_OC_REG_COMM_EXEC_CTL__B 0 -#define B_EC_OC_REG_COMM_EXEC_CTL__W 3 -#define B_EC_OC_REG_COMM_EXEC_CTL__M 0x7 -#define B_EC_OC_REG_COMM_EXEC_CTL_STOP 0x0 #define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1 #define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_EC_OC_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_EC_OC_REG_COMM_STATE__A 0x2150001 -#define B_EC_OC_REG_COMM_STATE__W 4 -#define B_EC_OC_REG_COMM_STATE__M 0xF - -#define B_EC_OC_REG_COMM_MB__A 0x2150002 -#define B_EC_OC_REG_COMM_MB__W 2 -#define B_EC_OC_REG_COMM_MB__M 0x3 -#define B_EC_OC_REG_COMM_MB_CTR__B 0 -#define B_EC_OC_REG_COMM_MB_CTR__W 1 -#define B_EC_OC_REG_COMM_MB_CTR__M 0x1 -#define B_EC_OC_REG_COMM_MB_CTR_OFF 0x0 -#define B_EC_OC_REG_COMM_MB_CTR_ON 0x1 -#define B_EC_OC_REG_COMM_MB_OBS__B 1 -#define B_EC_OC_REG_COMM_MB_OBS__W 1 -#define B_EC_OC_REG_COMM_MB_OBS__M 0x2 -#define B_EC_OC_REG_COMM_MB_OBS_OFF 0x0 -#define B_EC_OC_REG_COMM_MB_OBS_ON 0x2 - -#define B_EC_OC_REG_COMM_SERVICE0__A 0x2150003 -#define B_EC_OC_REG_COMM_SERVICE0__W 10 -#define B_EC_OC_REG_COMM_SERVICE0__M 0x3FF - -#define B_EC_OC_REG_COMM_SERVICE1__A 0x2150004 -#define B_EC_OC_REG_COMM_SERVICE1__W 11 -#define B_EC_OC_REG_COMM_SERVICE1__M 0x7FF - #define B_EC_OC_REG_COMM_INT_STA__A 0x2150007 -#define B_EC_OC_REG_COMM_INT_STA__W 6 -#define B_EC_OC_REG_COMM_INT_STA__M 0x3F -#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0 -#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1 -#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1 -#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1 -#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1 -#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2 -#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2 -#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4 -#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3 -#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8 -#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4 -#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10 -#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5 -#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1 -#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20 - -#define B_EC_OC_REG_COMM_INT_MSK__A 0x2150008 -#define B_EC_OC_REG_COMM_INT_MSK__W 6 -#define B_EC_OC_REG_COMM_INT_MSK__M 0x3F -#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0 -#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1 -#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1 -#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10 -#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5 -#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1 -#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20 - #define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010 -#define B_EC_OC_REG_OC_MODE_LOP__W 16 -#define B_EC_OC_REG_OC_MODE_LOP__M 0xFFFF -#define B_EC_OC_REG_OC_MODE_LOP_INIT 0x0 - -#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0 -#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1 #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1 #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0 #define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1 - -#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2 -#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1 #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4 #define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4 - -#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4 -#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10 -#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10 - -#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5 -#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20 -#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1 #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0 #define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000 - -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000 - -#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15 -#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1 -#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000 -#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000 - #define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011 -#define B_EC_OC_REG_OC_MODE_HIP__W 15 -#define B_EC_OC_REG_OC_MODE_HIP__M 0x7FFF -#define B_EC_OC_REG_OC_MODE_HIP_INIT 0x5 - -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2 - -#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2 -#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4 -#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4 - -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0 #define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10 - -#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5 -#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20 -#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20 - -#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6 -#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40 -#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1 #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200 #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0 #define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400 - -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800 - -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000 - -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000 - -#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__B 14 -#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__W 1 -#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__M 0x4000 -#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_ZER 0x0 -#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_CLC 0x4000 - #define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012 -#define B_EC_OC_REG_OC_MPG_SIO__W 12 #define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF -#define B_EC_OC_REG_OC_MPG_SIO_INIT 0xFFF - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400 - -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0 -#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800 - #define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014 -#define B_EC_OC_REG_DTO_INC_LOP__W 16 -#define B_EC_OC_REG_DTO_INC_LOP__M 0xFFFF -#define B_EC_OC_REG_DTO_INC_LOP_INIT 0x0 - #define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015 -#define B_EC_OC_REG_DTO_INC_HIP__W 8 -#define B_EC_OC_REG_DTO_INC_HIP__M 0xFF -#define B_EC_OC_REG_DTO_INC_HIP_INIT 0xC0 - #define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016 -#define B_EC_OC_REG_SNC_ISC_LVL__W 12 -#define B_EC_OC_REG_SNC_ISC_LVL__M 0xFFF -#define B_EC_OC_REG_SNC_ISC_LVL_INIT 0x422 - -#define B_EC_OC_REG_SNC_ISC_LVL_ISC__B 0 -#define B_EC_OC_REG_SNC_ISC_LVL_ISC__W 4 -#define B_EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF - -#define B_EC_OC_REG_SNC_ISC_LVL_OSC__B 4 -#define B_EC_OC_REG_SNC_ISC_LVL_OSC__W 4 #define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0 - -#define B_EC_OC_REG_SNC_ISC_LVL_NSC__B 8 -#define B_EC_OC_REG_SNC_ISC_LVL_NSC__W 4 -#define B_EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00 - -#define B_EC_OC_REG_SNC_NSC_LVL__A 0x2150017 -#define B_EC_OC_REG_SNC_NSC_LVL__W 8 -#define B_EC_OC_REG_SNC_NSC_LVL__M 0xFF -#define B_EC_OC_REG_SNC_NSC_LVL_INIT 0x0 - -#define B_EC_OC_REG_SNC_SNC_MODE__A 0x2150019 -#define B_EC_OC_REG_SNC_SNC_MODE__W 2 -#define B_EC_OC_REG_SNC_SNC_MODE__M 0x3 -#define B_EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0 -#define B_EC_OC_REG_SNC_SNC_MODE_TRACK 0x1 -#define B_EC_OC_REG_SNC_SNC_MODE_LOCK 0x2 - -#define B_EC_OC_REG_SNC_PCK_NMB__A 0x215001A -#define B_EC_OC_REG_SNC_PCK_NMB__W 16 -#define B_EC_OC_REG_SNC_PCK_NMB__M 0xFFFF - -#define B_EC_OC_REG_SNC_PCK_CNT__A 0x215001B -#define B_EC_OC_REG_SNC_PCK_CNT__W 16 -#define B_EC_OC_REG_SNC_PCK_CNT__M 0xFFFF - -#define B_EC_OC_REG_SNC_PCK_ERR__A 0x215001C -#define B_EC_OC_REG_SNC_PCK_ERR__W 16 -#define B_EC_OC_REG_SNC_PCK_ERR__M 0xFFFF - #define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D -#define B_EC_OC_REG_TMD_TOP_MODE__W 2 -#define B_EC_OC_REG_TMD_TOP_MODE__M 0x3 -#define B_EC_OC_REG_TMD_TOP_MODE_INIT 0x3 -#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0 -#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1 -#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2 -#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3 - #define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E -#define B_EC_OC_REG_TMD_TOP_CNT__W 10 -#define B_EC_OC_REG_TMD_TOP_CNT__M 0x3FF -#define B_EC_OC_REG_TMD_TOP_CNT_INIT 0x1F4 - #define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F -#define B_EC_OC_REG_TMD_HIL_MAR__W 10 -#define B_EC_OC_REG_TMD_HIL_MAR__M 0x3FF -#define B_EC_OC_REG_TMD_HIL_MAR_INIT 0x3C0 - #define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020 -#define B_EC_OC_REG_TMD_LOL_MAR__W 10 -#define B_EC_OC_REG_TMD_LOL_MAR__M 0x3FF -#define B_EC_OC_REG_TMD_LOL_MAR_INIT 0x40 - #define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021 -#define B_EC_OC_REG_TMD_CUR_CNT__W 4 -#define B_EC_OC_REG_TMD_CUR_CNT__M 0xF -#define B_EC_OC_REG_TMD_CUR_CNT_INIT 0x3 - -#define B_EC_OC_REG_TMD_IUR_CNT__A 0x2150022 -#define B_EC_OC_REG_TMD_IUR_CNT__W 4 -#define B_EC_OC_REG_TMD_IUR_CNT__M 0xF -#define B_EC_OC_REG_TMD_IUR_CNT_INIT 0x0 - #define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023 -#define B_EC_OC_REG_AVR_ASH_CNT__W 4 -#define B_EC_OC_REG_AVR_ASH_CNT__M 0xF -#define B_EC_OC_REG_AVR_ASH_CNT_INIT 0x6 - #define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024 -#define B_EC_OC_REG_AVR_BSH_CNT__W 4 -#define B_EC_OC_REG_AVR_BSH_CNT__M 0xF -#define B_EC_OC_REG_AVR_BSH_CNT_INIT 0x2 - -#define B_EC_OC_REG_AVR_AVE_LOP__A 0x2150025 -#define B_EC_OC_REG_AVR_AVE_LOP__W 16 -#define B_EC_OC_REG_AVR_AVE_LOP__M 0xFFFF - -#define B_EC_OC_REG_AVR_AVE_HIP__A 0x2150026 -#define B_EC_OC_REG_AVR_AVE_HIP__W 5 -#define B_EC_OC_REG_AVR_AVE_HIP__M 0x1F - #define B_EC_OC_REG_RCN_MODE__A 0x2150027 -#define B_EC_OC_REG_RCN_MODE__W 3 -#define B_EC_OC_REG_RCN_MODE__M 0x7 -#define B_EC_OC_REG_RCN_MODE_INIT 0x7 - -#define B_EC_OC_REG_RCN_MODE_MODE_0__B 0 -#define B_EC_OC_REG_RCN_MODE_MODE_0__W 1 -#define B_EC_OC_REG_RCN_MODE_MODE_0__M 0x1 -#define B_EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0 -#define B_EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1 - -#define B_EC_OC_REG_RCN_MODE_MODE_1__B 1 -#define B_EC_OC_REG_RCN_MODE_MODE_1__W 1 -#define B_EC_OC_REG_RCN_MODE_MODE_1__M 0x2 -#define B_EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0 -#define B_EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2 - -#define B_EC_OC_REG_RCN_MODE_MODE_2__B 2 -#define B_EC_OC_REG_RCN_MODE_MODE_2__W 1 -#define B_EC_OC_REG_RCN_MODE_MODE_2__M 0x4 -#define B_EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4 -#define B_EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0 - #define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028 -#define B_EC_OC_REG_RCN_CRA_LOP__W 16 -#define B_EC_OC_REG_RCN_CRA_LOP__M 0xFFFF -#define B_EC_OC_REG_RCN_CRA_LOP_INIT 0x0 - #define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029 -#define B_EC_OC_REG_RCN_CRA_HIP__W 8 -#define B_EC_OC_REG_RCN_CRA_HIP__M 0xFF -#define B_EC_OC_REG_RCN_CRA_HIP_INIT 0xC0 - #define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A -#define B_EC_OC_REG_RCN_CST_LOP__W 16 -#define B_EC_OC_REG_RCN_CST_LOP__M 0xFFFF -#define B_EC_OC_REG_RCN_CST_LOP_INIT 0x1000 - #define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B -#define B_EC_OC_REG_RCN_CST_HIP__W 8 -#define B_EC_OC_REG_RCN_CST_HIP__M 0xFF -#define B_EC_OC_REG_RCN_CST_HIP_INIT 0x0 - #define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C -#define B_EC_OC_REG_RCN_SET_LVL__W 9 -#define B_EC_OC_REG_RCN_SET_LVL__M 0x1FF -#define B_EC_OC_REG_RCN_SET_LVL_INIT 0x1FF - #define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D -#define B_EC_OC_REG_RCN_GAI_LVL__W 4 -#define B_EC_OC_REG_RCN_GAI_LVL__M 0xF -#define B_EC_OC_REG_RCN_GAI_LVL_INIT 0xA - -#define B_EC_OC_REG_RCN_DRA_LOP__A 0x215002E -#define B_EC_OC_REG_RCN_DRA_LOP__W 16 -#define B_EC_OC_REG_RCN_DRA_LOP__M 0xFFFF - -#define B_EC_OC_REG_RCN_DRA_HIP__A 0x215002F -#define B_EC_OC_REG_RCN_DRA_HIP__W 8 -#define B_EC_OC_REG_RCN_DRA_HIP__M 0xFF - -#define B_EC_OC_REG_RCN_DOF_LOP__A 0x2150030 -#define B_EC_OC_REG_RCN_DOF_LOP__W 16 -#define B_EC_OC_REG_RCN_DOF_LOP__M 0xFFFF - -#define B_EC_OC_REG_RCN_DOF_HIP__A 0x2150031 -#define B_EC_OC_REG_RCN_DOF_HIP__W 8 -#define B_EC_OC_REG_RCN_DOF_HIP__M 0xFF - #define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032 -#define B_EC_OC_REG_RCN_CLP_LOP__W 16 -#define B_EC_OC_REG_RCN_CLP_LOP__M 0xFFFF -#define B_EC_OC_REG_RCN_CLP_LOP_INIT 0x0 - #define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033 -#define B_EC_OC_REG_RCN_CLP_HIP__W 8 -#define B_EC_OC_REG_RCN_CLP_HIP__M 0xFF -#define B_EC_OC_REG_RCN_CLP_HIP_INIT 0xC0 - #define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034 -#define B_EC_OC_REG_RCN_MAP_LOP__W 16 -#define B_EC_OC_REG_RCN_MAP_LOP__M 0xFFFF - #define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035 -#define B_EC_OC_REG_RCN_MAP_HIP__W 8 -#define B_EC_OC_REG_RCN_MAP_HIP__M 0xFF - #define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036 -#define B_EC_OC_REG_OCR_MPG_UOS__W 12 #define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF #define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40 - -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80 - -#define B_EC_OC_REG_OCR_MPG_UOS_ERR__B 8 -#define B_EC_OC_REG_OCR_MPG_UOS_ERR__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100 -#define B_EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100 - -#define B_EC_OC_REG_OCR_MPG_UOS_STR__B 9 -#define B_EC_OC_REG_OCR_MPG_UOS_STR__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_STR__M 0x200 -#define B_EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200 - -#define B_EC_OC_REG_OCR_MPG_UOS_VAL__B 10 -#define B_EC_OC_REG_OCR_MPG_UOS_VAL__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400 -#define B_EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400 - -#define B_EC_OC_REG_OCR_MPG_UOS_CLK__B 11 -#define B_EC_OC_REG_OCR_MPG_UOS_CLK__W 1 -#define B_EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800 -#define B_EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800 - -#define B_EC_OC_REG_OCR_MPG_WRI__A 0x2150037 -#define B_EC_OC_REG_OCR_MPG_WRI__W 12 -#define B_EC_OC_REG_OCR_MPG_WRI__M 0xFFF -#define B_EC_OC_REG_OCR_MPG_WRI_INIT 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80 -#define B_EC_OC_REG_OCR_MPG_WRI_ERR__B 8 -#define B_EC_OC_REG_OCR_MPG_WRI_ERR__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100 -#define B_EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100 -#define B_EC_OC_REG_OCR_MPG_WRI_STR__B 9 -#define B_EC_OC_REG_OCR_MPG_WRI_STR__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_STR__M 0x200 -#define B_EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200 -#define B_EC_OC_REG_OCR_MPG_WRI_VAL__B 10 -#define B_EC_OC_REG_OCR_MPG_WRI_VAL__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400 -#define B_EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400 -#define B_EC_OC_REG_OCR_MPG_WRI_CLK__B 11 -#define B_EC_OC_REG_OCR_MPG_WRI_CLK__W 1 -#define B_EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800 -#define B_EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0 -#define B_EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800 - #define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038 -#define B_EC_OC_REG_OCR_MPG_USR_DAT__W 12 -#define B_EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF - -#define B_EC_OC_REG_OCR_MON_CNT__A 0x215003C -#define B_EC_OC_REG_OCR_MON_CNT__W 14 -#define B_EC_OC_REG_OCR_MON_CNT__M 0x3FFF -#define B_EC_OC_REG_OCR_MON_CNT_INIT 0x0 - -#define B_EC_OC_REG_OCR_MON_RDX__A 0x215003D -#define B_EC_OC_REG_OCR_MON_RDX__W 1 -#define B_EC_OC_REG_OCR_MON_RDX__M 0x1 -#define B_EC_OC_REG_OCR_MON_RDX_INIT 0x0 - -#define B_EC_OC_REG_OCR_MON_RD0__A 0x215003E -#define B_EC_OC_REG_OCR_MON_RD0__W 10 -#define B_EC_OC_REG_OCR_MON_RD0__M 0x3FF - -#define B_EC_OC_REG_OCR_MON_RD1__A 0x215003F -#define B_EC_OC_REG_OCR_MON_RD1__W 10 -#define B_EC_OC_REG_OCR_MON_RD1__M 0x3FF - -#define B_EC_OC_REG_OCR_MON_RD2__A 0x2150040 -#define B_EC_OC_REG_OCR_MON_RD2__W 10 -#define B_EC_OC_REG_OCR_MON_RD2__M 0x3FF - -#define B_EC_OC_REG_OCR_MON_RD3__A 0x2150041 -#define B_EC_OC_REG_OCR_MON_RD3__W 10 -#define B_EC_OC_REG_OCR_MON_RD3__M 0x3FF - -#define B_EC_OC_REG_OCR_MON_RD4__A 0x2150042 -#define B_EC_OC_REG_OCR_MON_RD4__W 10 -#define B_EC_OC_REG_OCR_MON_RD4__M 0x3FF - -#define B_EC_OC_REG_OCR_MON_RD5__A 0x2150043 -#define B_EC_OC_REG_OCR_MON_RD5__W 10 -#define B_EC_OC_REG_OCR_MON_RD5__M 0x3FF - -#define B_EC_OC_REG_OCR_INV_MON__A 0x2150044 -#define B_EC_OC_REG_OCR_INV_MON__W 12 -#define B_EC_OC_REG_OCR_INV_MON__M 0xFFF -#define B_EC_OC_REG_OCR_INV_MON_INIT 0x0 - #define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045 -#define B_EC_OC_REG_IPR_INV_MPG__W 12 -#define B_EC_OC_REG_IPR_INV_MPG__M 0xFFF -#define B_EC_OC_REG_IPR_INV_MPG_INIT 0x0 - -#define B_EC_OC_REG_IPR_MSR_SNC__A 0x2150046 -#define B_EC_OC_REG_IPR_MSR_SNC__W 6 -#define B_EC_OC_REG_IPR_MSR_SNC__M 0x3F -#define B_EC_OC_REG_IPR_MSR_SNC_INIT 0x0 - #define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047 -#define B_EC_OC_REG_DTO_CLKMODE__W 2 -#define B_EC_OC_REG_DTO_CLKMODE__M 0x3 -#define B_EC_OC_REG_DTO_CLKMODE_INIT 0x2 - -#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__B 0 -#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__W 1 -#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__M 0x1 -#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_EVEN_ODD 0x0 -#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_ODD_EVEN 0x1 - -#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__B 1 -#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__W 1 -#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__M 0x2 -#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_SERIAL_MODE 0x0 -#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_PARALLEL_MODE 0x2 - #define B_EC_OC_REG_DTO_PER__A 0x2150048 -#define B_EC_OC_REG_DTO_PER__W 8 -#define B_EC_OC_REG_DTO_PER__M 0xFF -#define B_EC_OC_REG_DTO_PER_INIT 0x6 - #define B_EC_OC_REG_DTO_BUR__A 0x2150049 -#define B_EC_OC_REG_DTO_BUR__W 2 -#define B_EC_OC_REG_DTO_BUR__M 0x3 -#define B_EC_OC_REG_DTO_BUR_INIT 0x1 -#define B_EC_OC_REG_DTO_BUR_SELECT_1 0x0 -#define B_EC_OC_REG_DTO_BUR_SELECT_188 0x1 -#define B_EC_OC_REG_DTO_BUR_SELECT_204 0x2 -#define B_EC_OC_REG_DTO_BUR_SELECT_47 0x3 - #define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A -#define B_EC_OC_REG_RCR_CLKMODE__W 3 -#define B_EC_OC_REG_RCR_CLKMODE__M 0x7 -#define B_EC_OC_REG_RCR_CLKMODE_INIT 0x0 - -#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__B 0 -#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__W 1 -#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__M 0x1 -#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_FRACIONAL 0x0 -#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_RATIONAL 0x1 - -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__B 1 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__W 1 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__M 0x2 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_FRACTIONAL 0x0 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_RATIONAL 0x2 - -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__B 2 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__W 1 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__M 0x4 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FIFO 0x0 -#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FEEDBACKLOOP 0x4 - -#define B_EC_OC_RAM__A 0x2160000 - -#define B_CC_SID 0x1B - -#define B_CC_COMM_EXEC__A 0x2400000 -#define B_CC_COMM_EXEC__W 3 -#define B_CC_COMM_EXEC__M 0x7 -#define B_CC_COMM_EXEC_CTL__B 0 -#define B_CC_COMM_EXEC_CTL__W 3 -#define B_CC_COMM_EXEC_CTL__M 0x7 -#define B_CC_COMM_EXEC_CTL_STOP 0x0 -#define B_CC_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CC_COMM_EXEC_CTL_HOLD 0x2 -#define B_CC_COMM_EXEC_CTL_STEP 0x3 -#define B_CC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_CC_COMM_STATE__A 0x2400001 -#define B_CC_COMM_STATE__W 16 -#define B_CC_COMM_STATE__M 0xFFFF -#define B_CC_COMM_MB__A 0x2400002 -#define B_CC_COMM_MB__W 16 -#define B_CC_COMM_MB__M 0xFFFF -#define B_CC_COMM_SERVICE0__A 0x2400003 -#define B_CC_COMM_SERVICE0__W 16 -#define B_CC_COMM_SERVICE0__M 0xFFFF -#define B_CC_COMM_SERVICE1__A 0x2400004 -#define B_CC_COMM_SERVICE1__W 16 -#define B_CC_COMM_SERVICE1__M 0xFFFF -#define B_CC_COMM_INT_STA__A 0x2400007 -#define B_CC_COMM_INT_STA__W 16 -#define B_CC_COMM_INT_STA__M 0xFFFF -#define B_CC_COMM_INT_MSK__A 0x2400008 -#define B_CC_COMM_INT_MSK__W 16 -#define B_CC_COMM_INT_MSK__M 0xFFFF - -#define B_CC_REG_COMM_EXEC__A 0x2410000 -#define B_CC_REG_COMM_EXEC__W 3 -#define B_CC_REG_COMM_EXEC__M 0x7 -#define B_CC_REG_COMM_EXEC_CTL__B 0 -#define B_CC_REG_COMM_EXEC_CTL__W 3 -#define B_CC_REG_COMM_EXEC_CTL__M 0x7 -#define B_CC_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_CC_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_CC_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_CC_REG_COMM_EXEC_CTL_STEP 0x3 -#define B_CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_CC_REG_COMM_STATE__A 0x2410001 -#define B_CC_REG_COMM_STATE__W 16 -#define B_CC_REG_COMM_STATE__M 0xFFFF -#define B_CC_REG_COMM_MB__A 0x2410002 -#define B_CC_REG_COMM_MB__W 16 -#define B_CC_REG_COMM_MB__M 0xFFFF -#define B_CC_REG_COMM_SERVICE0__A 0x2410003 -#define B_CC_REG_COMM_SERVICE0__W 16 -#define B_CC_REG_COMM_SERVICE0__M 0xFFFF -#define B_CC_REG_COMM_SERVICE1__A 0x2410004 -#define B_CC_REG_COMM_SERVICE1__W 16 -#define B_CC_REG_COMM_SERVICE1__M 0xFFFF -#define B_CC_REG_COMM_INT_STA__A 0x2410007 -#define B_CC_REG_COMM_INT_STA__W 16 -#define B_CC_REG_COMM_INT_STA__M 0xFFFF -#define B_CC_REG_COMM_INT_MSK__A 0x2410008 -#define B_CC_REG_COMM_INT_MSK__W 16 -#define B_CC_REG_COMM_INT_MSK__M 0xFFFF - #define B_CC_REG_OSC_MODE__A 0x2410010 -#define B_CC_REG_OSC_MODE__W 2 -#define B_CC_REG_OSC_MODE__M 0x3 -#define B_CC_REG_OSC_MODE_OHW 0x0 #define B_CC_REG_OSC_MODE_M20 0x1 -#define B_CC_REG_OSC_MODE_M48 0x2 - #define B_CC_REG_PLL_MODE__A 0x2410011 -#define B_CC_REG_PLL_MODE__W 6 -#define B_CC_REG_PLL_MODE__M 0x3F -#define B_CC_REG_PLL_MODE_INIT 0xC -#define B_CC_REG_PLL_MODE_BYPASS__B 0 -#define B_CC_REG_PLL_MODE_BYPASS__W 2 -#define B_CC_REG_PLL_MODE_BYPASS__M 0x3 -#define B_CC_REG_PLL_MODE_BYPASS_OHW 0x0 #define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1 -#define B_CC_REG_PLL_MODE_BYPASS_BYPASS 0x2 -#define B_CC_REG_PLL_MODE_PUMP__B 2 -#define B_CC_REG_PLL_MODE_PUMP__W 3 -#define B_CC_REG_PLL_MODE_PUMP__M 0x1C -#define B_CC_REG_PLL_MODE_PUMP_OFF 0x0 -#define B_CC_REG_PLL_MODE_PUMP_CUR_08 0x4 -#define B_CC_REG_PLL_MODE_PUMP_CUR_09 0x8 -#define B_CC_REG_PLL_MODE_PUMP_CUR_10 0xC -#define B_CC_REG_PLL_MODE_PUMP_CUR_11 0x10 #define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14 -#define B_CC_REG_PLL_MODE_OUT_EN__B 5 -#define B_CC_REG_PLL_MODE_OUT_EN__W 1 -#define B_CC_REG_PLL_MODE_OUT_EN__M 0x20 -#define B_CC_REG_PLL_MODE_OUT_EN_OFF 0x0 -#define B_CC_REG_PLL_MODE_OUT_EN_ON 0x20 - #define B_CC_REG_REF_DIVIDE__A 0x2410012 -#define B_CC_REG_REF_DIVIDE__W 4 -#define B_CC_REG_REF_DIVIDE__M 0xF -#define B_CC_REG_REF_DIVIDE_INIT 0xA -#define B_CC_REG_REF_DIVIDE_OHW 0x0 -#define B_CC_REG_REF_DIVIDE_D01 0x1 -#define B_CC_REG_REF_DIVIDE_D02 0x2 -#define B_CC_REG_REF_DIVIDE_D03 0x3 -#define B_CC_REG_REF_DIVIDE_D04 0x4 -#define B_CC_REG_REF_DIVIDE_D05 0x5 -#define B_CC_REG_REF_DIVIDE_D06 0x6 -#define B_CC_REG_REF_DIVIDE_D07 0x7 -#define B_CC_REG_REF_DIVIDE_D08 0x8 -#define B_CC_REG_REF_DIVIDE_D09 0x9 -#define B_CC_REG_REF_DIVIDE_D10 0xA - -#define B_CC_REG_REF_DELAY__A 0x2410013 -#define B_CC_REG_REF_DELAY__W 3 -#define B_CC_REG_REF_DELAY__M 0x7 -#define B_CC_REG_REF_DELAY_EDGE__B 0 -#define B_CC_REG_REF_DELAY_EDGE__W 1 -#define B_CC_REG_REF_DELAY_EDGE__M 0x1 -#define B_CC_REG_REF_DELAY_EDGE_POS 0x0 -#define B_CC_REG_REF_DELAY_EDGE_NEG 0x1 -#define B_CC_REG_REF_DELAY_DELAY__B 1 -#define B_CC_REG_REF_DELAY_DELAY__W 2 -#define B_CC_REG_REF_DELAY_DELAY__M 0x6 -#define B_CC_REG_REF_DELAY_DELAY_DEL_0 0x0 -#define B_CC_REG_REF_DELAY_DELAY_DEL_3 0x2 -#define B_CC_REG_REF_DELAY_DELAY_DEL_6 0x4 -#define B_CC_REG_REF_DELAY_DELAY_DEL_9 0x6 - -#define B_CC_REG_CLK_DELAY__A 0x2410014 -#define B_CC_REG_CLK_DELAY__W 5 -#define B_CC_REG_CLK_DELAY__M 0x1F -#define B_CC_REG_CLK_DELAY_DELAY__B 0 -#define B_CC_REG_CLK_DELAY_DELAY__W 4 -#define B_CC_REG_CLK_DELAY_DELAY__M 0xF -#define B_CC_REG_CLK_DELAY_DELAY_DEL_00 0x0 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_05 0x1 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_10 0x2 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_15 0x3 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_20 0x4 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_25 0x5 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_30 0x6 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_35 0x7 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_40 0x8 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_45 0x9 -#define B_CC_REG_CLK_DELAY_DELAY_DEL_50 0xA -#define B_CC_REG_CLK_DELAY_DELAY_DEL_55 0xB -#define B_CC_REG_CLK_DELAY_DELAY_DEL_60 0xC -#define B_CC_REG_CLK_DELAY_DELAY_DEL_65 0xD -#define B_CC_REG_CLK_DELAY_DELAY_DEL_70 0xE -#define B_CC_REG_CLK_DELAY_DELAY_DEL_75 0xF -#define B_CC_REG_CLK_DELAY_EDGE__B 4 -#define B_CC_REG_CLK_DELAY_EDGE__W 1 -#define B_CC_REG_CLK_DELAY_EDGE__M 0x10 -#define B_CC_REG_CLK_DELAY_EDGE_POS 0x0 -#define B_CC_REG_CLK_DELAY_EDGE_NEG 0x10 - #define B_CC_REG_PWD_MODE__A 0x2410015 -#define B_CC_REG_PWD_MODE__W 2 -#define B_CC_REG_PWD_MODE__M 0x3 -#define B_CC_REG_PWD_MODE_UP 0x0 -#define B_CC_REG_PWD_MODE_DOWN_CLK 0x1 #define B_CC_REG_PWD_MODE_DOWN_PLL 0x2 -#define B_CC_REG_PWD_MODE_DOWN_OSC 0x3 - -#define B_CC_REG_SOFT_RST__A 0x2410016 -#define B_CC_REG_SOFT_RST__W 2 -#define B_CC_REG_SOFT_RST__M 0x3 -#define B_CC_REG_SOFT_RST_SYS__B 0 -#define B_CC_REG_SOFT_RST_SYS__W 1 -#define B_CC_REG_SOFT_RST_SYS__M 0x1 -#define B_CC_REG_SOFT_RST_OSC__B 1 -#define B_CC_REG_SOFT_RST_OSC__W 1 -#define B_CC_REG_SOFT_RST_OSC__M 0x2 - #define B_CC_REG_UPDATE__A 0x2410017 -#define B_CC_REG_UPDATE__W 16 -#define B_CC_REG_UPDATE__M 0xFFFF #define B_CC_REG_UPDATE_KEY 0x3973 - -#define B_CC_REG_PLL_LOCK__A 0x2410018 -#define B_CC_REG_PLL_LOCK__W 1 -#define B_CC_REG_PLL_LOCK__M 0x1 -#define B_CC_REG_PLL_LOCK_LOCK 0x1 - #define B_CC_REG_JTAGID_L__A 0x2410019 -#define B_CC_REG_JTAGID_L__W 16 -#define B_CC_REG_JTAGID_L__M 0xFFFF -#define B_CC_REG_JTAGID_L_INIT 0x0 - -#define B_CC_REG_JTAGID_H__A 0x241001A -#define B_CC_REG_JTAGID_H__W 16 -#define B_CC_REG_JTAGID_H__M 0xFFFF -#define B_CC_REG_JTAGID_H_INIT 0x0 - #define B_CC_REG_DIVERSITY__A 0x241001B -#define B_CC_REG_DIVERSITY__W 1 -#define B_CC_REG_DIVERSITY__M 0x1 -#define B_CC_REG_DIVERSITY_INIT 0x0 - -#define B_CC_REG_BACKUP3V__A 0x241001C -#define B_CC_REG_BACKUP3V__W 1 -#define B_CC_REG_BACKUP3V__M 0x1 -#define B_CC_REG_BACKUP3V_INIT 0x0 - -#define B_CC_REG_DRV_IO__A 0x241001D -#define B_CC_REG_DRV_IO__W 3 -#define B_CC_REG_DRV_IO__M 0x7 -#define B_CC_REG_DRV_IO_INIT 0x2 - -#define B_CC_REG_DRV_MPG__A 0x241001E -#define B_CC_REG_DRV_MPG__W 3 -#define B_CC_REG_DRV_MPG__M 0x7 -#define B_CC_REG_DRV_MPG_INIT 0x2 - -#define B_CC_REG_DRV_I2C1__A 0x241001F -#define B_CC_REG_DRV_I2C1__W 3 -#define B_CC_REG_DRV_I2C1__M 0x7 -#define B_CC_REG_DRV_I2C1_INIT 0x2 - -#define B_CC_REG_DRV_I2C2__A 0x2410020 -#define B_CC_REG_DRV_I2C2__W 1 -#define B_CC_REG_DRV_I2C2__M 0x1 -#define B_CC_REG_DRV_I2C2_INIT 0x0 - -#define B_LC_SID 0x1C - #define B_LC_COMM_EXEC__A 0x2800000 -#define B_LC_COMM_EXEC__W 3 -#define B_LC_COMM_EXEC__M 0x7 -#define B_LC_COMM_EXEC_CTL__B 0 -#define B_LC_COMM_EXEC_CTL__W 3 -#define B_LC_COMM_EXEC_CTL__M 0x7 -#define B_LC_COMM_EXEC_CTL_STOP 0x0 -#define B_LC_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_LC_COMM_EXEC_CTL_HOLD 0x2 -#define B_LC_COMM_EXEC_CTL_STEP 0x3 -#define B_LC_COMM_EXEC_CTL_BYPASS_STOP 0x4 -#define B_LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6 - -#define B_LC_COMM_STATE__A 0x2800001 -#define B_LC_COMM_STATE__W 16 -#define B_LC_COMM_STATE__M 0xFFFF -#define B_LC_COMM_MB__A 0x2800002 -#define B_LC_COMM_MB__W 16 -#define B_LC_COMM_MB__M 0xFFFF -#define B_LC_COMM_SERVICE0__A 0x2800003 -#define B_LC_COMM_SERVICE0__W 16 -#define B_LC_COMM_SERVICE0__M 0xFFFF -#define B_LC_COMM_SERVICE1__A 0x2800004 -#define B_LC_COMM_SERVICE1__W 16 -#define B_LC_COMM_SERVICE1__M 0xFFFF -#define B_LC_COMM_INT_STA__A 0x2800007 -#define B_LC_COMM_INT_STA__W 16 -#define B_LC_COMM_INT_STA__M 0xFFFF -#define B_LC_COMM_INT_MSK__A 0x2800008 -#define B_LC_COMM_INT_MSK__W 16 -#define B_LC_COMM_INT_MSK__M 0xFFFF - -#define B_LC_CT_REG_COMM_EXEC__A 0x2810000 -#define B_LC_CT_REG_COMM_EXEC__W 3 -#define B_LC_CT_REG_COMM_EXEC__M 0x7 -#define B_LC_CT_REG_COMM_EXEC_CTL__B 0 -#define B_LC_CT_REG_COMM_EXEC_CTL__W 3 -#define B_LC_CT_REG_COMM_EXEC_CTL__M 0x7 -#define B_LC_CT_REG_COMM_EXEC_CTL_STOP 0x0 -#define B_LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1 -#define B_LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2 -#define B_LC_CT_REG_COMM_EXEC_CTL_STEP 0x3 - -#define B_LC_CT_REG_COMM_STATE__A 0x2810001 -#define B_LC_CT_REG_COMM_STATE__W 10 -#define B_LC_CT_REG_COMM_STATE__M 0x3FF -#define B_LC_CT_REG_COMM_SERVICE0__A 0x2810003 -#define B_LC_CT_REG_COMM_SERVICE0__W 16 -#define B_LC_CT_REG_COMM_SERVICE0__M 0xFFFF -#define B_LC_CT_REG_COMM_SERVICE1__A 0x2810004 -#define B_LC_CT_REG_COMM_SERVICE1__W 16 -#define B_LC_CT_REG_COMM_SERVICE1__M 0xFFFF -#define B_LC_CT_REG_COMM_SERVICE1_LC__B 12 -#define B_LC_CT_REG_COMM_SERVICE1_LC__W 1 -#define B_LC_CT_REG_COMM_SERVICE1_LC__M 0x1000 - -#define B_LC_CT_REG_COMM_INT_STA__A 0x2810007 -#define B_LC_CT_REG_COMM_INT_STA__W 1 -#define B_LC_CT_REG_COMM_INT_STA__M 0x1 -#define B_LC_CT_REG_COMM_INT_STA_REQUEST__B 0 -#define B_LC_CT_REG_COMM_INT_STA_REQUEST__W 1 -#define B_LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1 - -#define B_LC_CT_REG_COMM_INT_MSK__A 0x2810008 -#define B_LC_CT_REG_COMM_INT_MSK__W 1 -#define B_LC_CT_REG_COMM_INT_MSK__M 0x1 -#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__B 0 -#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__W 1 -#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1 - -#define B_LC_CT_REG_CTL_STK__AX 0x2810010 -#define B_LC_CT_REG_CTL_STK__XSZ 4 -#define B_LC_CT_REG_CTL_STK__W 10 -#define B_LC_CT_REG_CTL_STK__M 0x3FF - -#define B_LC_CT_REG_CTL_BPT_IDX__A 0x281001F -#define B_LC_CT_REG_CTL_BPT_IDX__W 1 -#define B_LC_CT_REG_CTL_BPT_IDX__M 0x1 - -#define B_LC_CT_REG_CTL_BPT__A 0x2810020 -#define B_LC_CT_REG_CTL_BPT__W 10 -#define B_LC_CT_REG_CTL_BPT__M 0x3FF - -#define B_LC_RA_RAM_PROC_DELAY_IF__A 0x2820006 -#define B_LC_RA_RAM_PROC_DELAY_IF__W 16 -#define B_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF -#define B_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6 -#define B_LC_RA_RAM_PROC_DELAY_FS__A 0x2820007 -#define B_LC_RA_RAM_PROC_DELAY_FS__W 16 -#define B_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF -#define B_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3 -#define B_LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008 -#define B_LC_RA_RAM_LOCK_TH_CRMM__W 16 -#define B_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF -#define B_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8 -#define B_LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009 -#define B_LC_RA_RAM_LOCK_TH_SRMM__W 16 -#define B_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF -#define B_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46 -#define B_LC_RA_RAM_LOCK_COUNT__A 0x282000A -#define B_LC_RA_RAM_LOCK_COUNT__W 16 -#define B_LC_RA_RAM_LOCK_COUNT__M 0xFFFF -#define B_LC_RA_RAM_CPRTOFS_NOM__A 0x282000B -#define B_LC_RA_RAM_CPRTOFS_NOM__W 16 -#define B_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF #define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C -#define B_LC_RA_RAM_IFINCR_NOM_L__W 16 -#define B_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF -#define B_LC_RA_RAM_IFINCR_NOM_H__A 0x282000D -#define B_LC_RA_RAM_IFINCR_NOM_H__W 16 -#define B_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF -#define B_LC_RA_RAM_FSINCR_NOM_L__A 0x282000E -#define B_LC_RA_RAM_FSINCR_NOM_L__W 16 -#define B_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF -#define B_LC_RA_RAM_FSINCR_NOM_H__A 0x282000F -#define B_LC_RA_RAM_FSINCR_NOM_H__W 16 -#define B_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF -#define B_LC_RA_RAM_MODE_2K__A 0x2820010 -#define B_LC_RA_RAM_MODE_2K__W 16 -#define B_LC_RA_RAM_MODE_2K__M 0xFFFF -#define B_LC_RA_RAM_MODE_GUARD__A 0x2820011 -#define B_LC_RA_RAM_MODE_GUARD__W 16 -#define B_LC_RA_RAM_MODE_GUARD__M 0xFFFF -#define B_LC_RA_RAM_MODE_GUARD_32 0x0 -#define B_LC_RA_RAM_MODE_GUARD_16 0x1 -#define B_LC_RA_RAM_MODE_GUARD_8 0x2 -#define B_LC_RA_RAM_MODE_GUARD_4 0x3 - -#define B_LC_RA_RAM_MODE_ADJUST__A 0x2820012 -#define B_LC_RA_RAM_MODE_ADJUST__W 16 -#define B_LC_RA_RAM_MODE_ADJUST__M 0xFFFF -#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0 -#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1 -#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1 -#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2 -#define B_LC_RA_RAM_MODE_ADJUST_SRMM__B 2 -#define B_LC_RA_RAM_MODE_ADJUST_SRMM__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4 -#define B_LC_RA_RAM_MODE_ADJUST_PHASE__B 3 -#define B_LC_RA_RAM_MODE_ADJUST_PHASE__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8 -#define B_LC_RA_RAM_MODE_ADJUST_DELAY__B 4 -#define B_LC_RA_RAM_MODE_ADJUST_DELAY__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10 -#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5 -#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20 -#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6 -#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40 -#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7 -#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80 -#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8 -#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100 -#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9 -#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1 -#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800 - -#define B_LC_RA_RAM_RC_STS__A 0x2820014 -#define B_LC_RA_RAM_RC_STS__W 16 -#define B_LC_RA_RAM_RC_STS__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x2820018 -#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16 -#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x2820019 -#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16 -#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF #define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A -#define B_LC_RA_RAM_FILTER_SYM_SET__W 16 -#define B_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF #define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8 -#define B_LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B -#define B_LC_RA_RAM_FILTER_SYM_CUR__W 16 -#define B_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF -#define B_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0 -#define B_LC_RA_RAM_DIVERSITY_DELAY__A 0x282001C -#define B_LC_RA_RAM_DIVERSITY_DELAY__W 16 -#define B_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF -#define B_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8 -#define B_LC_RA_RAM_MAX_ABS_EXP__A 0x282001D -#define B_LC_RA_RAM_MAX_ABS_EXP__W 16 -#define B_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF -#define B_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10 -#define B_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F -#define B_LC_RA_RAM_ACTUAL_CP_CRMM__W 16 -#define B_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020 -#define B_LC_RA_RAM_ACTUAL_CE_CRMM__W 16 -#define B_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021 -#define B_LC_RA_RAM_ACTUAL_CE_SRMM__W 16 -#define B_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_PHASE__A 0x2820022 -#define B_LC_RA_RAM_ACTUAL_PHASE__W 16 -#define B_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF -#define B_LC_RA_RAM_ACTUAL_DELAY__A 0x2820023 -#define B_LC_RA_RAM_ACTUAL_DELAY__W 16 -#define B_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF -#define B_LC_RA_RAM_ADJUST_CRMM__A 0x2820024 -#define B_LC_RA_RAM_ADJUST_CRMM__W 16 -#define B_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF -#define B_LC_RA_RAM_ADJUST_SRMM__A 0x2820025 -#define B_LC_RA_RAM_ADJUST_SRMM__W 16 -#define B_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF -#define B_LC_RA_RAM_ADJUST_PHASE__A 0x2820026 -#define B_LC_RA_RAM_ADJUST_PHASE__W 16 -#define B_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF -#define B_LC_RA_RAM_ADJUST_DELAY__A 0x2820027 -#define B_LC_RA_RAM_ADJUST_DELAY__W 16 -#define B_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF - -#define B_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028 -#define B_LC_RA_RAM_PIPE_CP_PHASE_0__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029 -#define B_LC_RA_RAM_PIPE_CP_PHASE_1__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A -#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B -#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C -#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D -#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16 -#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF - -#define B_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030 -#define B_LC_RA_RAM_PIPE_CP_CRMM_0__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031 -#define B_LC_RA_RAM_PIPE_CP_CRMM_1__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032 -#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033 -#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034 -#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035 -#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16 -#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF - -#define B_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038 -#define B_LC_RA_RAM_PIPE_CP_SRMM_0__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039 -#define B_LC_RA_RAM_PIPE_CP_SRMM_1__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A -#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B -#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C -#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF -#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D -#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16 -#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF - #define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060 -#define B_LC_RA_RAM_FILTER_CRMM_A__W 16 -#define B_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF #define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4 #define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061 -#define B_LC_RA_RAM_FILTER_CRMM_B__W 16 -#define B_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF #define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1 -#define B_LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062 -#define B_LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2 -#define B_LC_RA_RAM_FILTER_CRMM_Z1__W 16 -#define B_LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF -#define B_LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064 -#define B_LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2 -#define B_LC_RA_RAM_FILTER_CRMM_Z2__W 16 -#define B_LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF -#define B_LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066 -#define B_LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2 -#define B_LC_RA_RAM_FILTER_CRMM_TMP__W 16 -#define B_LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF - #define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068 -#define B_LC_RA_RAM_FILTER_SRMM_A__W 16 -#define B_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF #define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4 #define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069 -#define B_LC_RA_RAM_FILTER_SRMM_B__W 16 -#define B_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF #define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1 -#define B_LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A -#define B_LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2 -#define B_LC_RA_RAM_FILTER_SRMM_Z1__W 16 -#define B_LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF -#define B_LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C -#define B_LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2 -#define B_LC_RA_RAM_FILTER_SRMM_Z2__W 16 -#define B_LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF -#define B_LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E -#define B_LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2 -#define B_LC_RA_RAM_FILTER_SRMM_TMP__W 16 -#define B_LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF - -#define B_LC_RA_RAM_FILTER_PHASE_A__A 0x2820070 -#define B_LC_RA_RAM_FILTER_PHASE_A__W 16 -#define B_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF -#define B_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4 -#define B_LC_RA_RAM_FILTER_PHASE_B__A 0x2820071 -#define B_LC_RA_RAM_FILTER_PHASE_B__W 16 -#define B_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF -#define B_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1 -#define B_LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072 -#define B_LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2 -#define B_LC_RA_RAM_FILTER_PHASE_Z1__W 16 -#define B_LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF -#define B_LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074 -#define B_LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2 -#define B_LC_RA_RAM_FILTER_PHASE_Z2__W 16 -#define B_LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF -#define B_LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076 -#define B_LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2 -#define B_LC_RA_RAM_FILTER_PHASE_TMP__W 16 -#define B_LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF - -#define B_LC_RA_RAM_FILTER_DELAY_A__A 0x2820078 -#define B_LC_RA_RAM_FILTER_DELAY_A__W 16 -#define B_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF -#define B_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4 -#define B_LC_RA_RAM_FILTER_DELAY_B__A 0x2820079 -#define B_LC_RA_RAM_FILTER_DELAY_B__W 16 -#define B_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF -#define B_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1 -#define B_LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A -#define B_LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2 -#define B_LC_RA_RAM_FILTER_DELAY_Z1__W 16 -#define B_LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF -#define B_LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C -#define B_LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2 -#define B_LC_RA_RAM_FILTER_DELAY_Z2__W 16 -#define B_LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF -#define B_LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E -#define B_LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2 -#define B_LC_RA_RAM_FILTER_DELAY_TMP__W 16 -#define B_LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF - -#define B_LC_IF_RAM_TRP_BPT0__AX 0x2830000 -#define B_LC_IF_RAM_TRP_BPT0__XSZ 2 -#define B_LC_IF_RAM_TRP_BPT0__W 12 -#define B_LC_IF_RAM_TRP_BPT0__M 0xFFF - -#define B_LC_IF_RAM_TRP_STKU__AX 0x2830002 -#define B_LC_IF_RAM_TRP_STKU__XSZ 2 -#define B_LC_IF_RAM_TRP_STKU__W 12 -#define B_LC_IF_RAM_TRP_STKU__M 0xFFF - -#define B_LC_IF_RAM_TRP_WARM__AX 0x2830006 -#define B_LC_IF_RAM_TRP_WARM__XSZ 2 -#define B_LC_IF_RAM_TRP_WARM__W 12 -#define B_LC_IF_RAM_TRP_WARM__M 0xFFF #endif -- cgit v1.2.3 From bccd2d8a39a65b008e5af96404139c2260a42fc7 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab <mchehab@redhat.com> Date: Fri, 25 Mar 2011 10:46:32 -0300 Subject: [media] drxd: don't re-define u8/u16/u32 types Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd_firm.c | 70 ++++++++++++++--------------- drivers/media/dvb/frontends/drxd_firm.h | 79 ++++++++++++++++----------------- 2 files changed, 73 insertions(+), 76 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c index 9453929d0d1c..2949bde426b2 100644 --- a/drivers/media/dvb/frontends/drxd_firm.c +++ b/drivers/media/dvb/frontends/drxd_firm.c @@ -46,7 +46,7 @@ #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A #define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */ -u8_t DRXD_InitAtomicRead[] = { +u8 DRXD_InitAtomicRead[] = { WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE), 0x26, 0x00, /* 0 -> ring.rdy; */ 0x60, 0x04, /* r0rami.dt -> ring.xba; */ @@ -67,7 +67,7 @@ u8_t DRXD_InitAtomicRead[] = { #define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */ /* D0 Version */ -u8_t DRXD_HiI2cPatch_1[] = { +u8 DRXD_HiI2cPatch_1[] = { WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE), 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */ 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ @@ -114,13 +114,13 @@ u8_t DRXD_HiI2cPatch_1[] = { 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)), - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)), - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)), - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)), - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), /* Force quick and dirty reset */ WR16(B_HI_CT_REG_COMM_STATE__A, 0), @@ -128,7 +128,7 @@ u8_t DRXD_HiI2cPatch_1[] = { }; /* D0,D1 Version */ -u8_t DRXD_HiI2cPatch_3[] = { +u8 DRXD_HiI2cPatch_3[] = { WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE), 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */ 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */ @@ -175,20 +175,20 @@ u8_t DRXD_HiI2cPatch_3[] = { 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */ WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)), - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)), - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)), - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)), - (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)), + (u16) (HI_RST_FUNC_ADDR & 0x3FF)), /* Force quick and dirty reset */ WR16(B_HI_CT_REG_COMM_STATE__A, 0), END_OF_TABLE }; -u8_t DRXD_ResetCEFR[] = { +u8 DRXD_ResetCEFR[] = { WRBLOCK(CE_REG_FR_TREAL00__A, 57), 0x52, 0x00, /* CE_REG_FR_TREAL00__A */ 0x00, 0x00, /* CE_REG_FR_TIMAG00__A */ @@ -255,7 +255,7 @@ u8_t DRXD_ResetCEFR[] = { END_OF_TABLE }; -u8_t DRXD_InitFEA2_1[] = { +u8 DRXD_InitFEA2_1[] = { WRBLOCK(FE_AD_REG_PD__A, 3), 0x00, 0x00, /* FE_AD_REG_PD__A */ 0x01, 0x00, /* FE_AD_REG_INVEXT__A */ @@ -341,7 +341,7 @@ u8_t DRXD_InitFEA2_1[] = { /* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/ /* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ -u8_t DRXD_InitFEA2_2[] = { +u8 DRXD_InitFEA2_2[] = { WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010), WR16(FE_AG_REG_FGM_WRI__A, 48), /* Activate measurement, activate scale */ @@ -359,7 +359,7 @@ u8_t DRXD_InitFEA2_2[] = { END_OF_TABLE }; -u8_t DRXD_InitFEB1_1[] = { +u8 DRXD_InitFEB1_1[] = { WR16(B_FE_AD_REG_PD__A, 0x0000), WR16(B_FE_AD_REG_CLKNEG__A, 0x0000), WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000), @@ -382,7 +382,7 @@ u8_t DRXD_InitFEB1_1[] = { /* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */ /* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/ -u8_t DRXD_InitFEB1_2[] = { +u8 DRXD_InitFEB1_2[] = { WR16(B_FE_COMM_EXEC__A, 0x0001), /* RF-AGC setup */ @@ -404,7 +404,7 @@ u8_t DRXD_InitFEB1_2[] = { END_OF_TABLE }; -u8_t DRXD_InitCPA2[] = { +u8 DRXD_InitCPA2[] = { WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2), 0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */ 0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */ @@ -434,13 +434,13 @@ u8_t DRXD_InitCPA2[] = { END_OF_TABLE }; -u8_t DRXD_InitCPB1[] = { +u8 DRXD_InitCPB1[] = { WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008), WR16(B_CP_COMM_EXEC__A, 0x0001), END_OF_TABLE }; -u8_t DRXD_InitCEA2[] = { +u8 DRXD_InitCEA2[] = { WRBLOCK(CE_REG_AVG_POW__A, 4), 0x62, 0x00, /* CE_REG_AVG_POW__A */ 0x78, 0x00, /* CE_REG_MAX_POW__A */ @@ -483,14 +483,14 @@ u8_t DRXD_InitCEA2[] = { END_OF_TABLE }; -u8_t DRXD_InitCEB1[] = { +u8 DRXD_InitCEB1[] = { WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001), WR16(B_CE_REG_FR_PM_SET__A, 0x000D), END_OF_TABLE }; -u8_t DRXD_InitEQA2[] = { +u8 DRXD_InitEQA2[] = { WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4), 0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */ 0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */ @@ -499,18 +499,18 @@ u8_t DRXD_InitEQA2[] = { WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200), WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F), - WR16(EQ_REG_SN_OFFSET__A, (u16_t) (-7)), + WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)), WR16(EQ_REG_RC_SEL_CAR__A, 0x0002), WR16(EQ_REG_COMM_EXEC__A, 0x0001), END_OF_TABLE }; -u8_t DRXD_InitEQB1[] = { +u8 DRXD_InitEQB1[] = { WR16(B_EQ_REG_COMM_EXEC__A, 0x0001), END_OF_TABLE }; -u8_t DRXD_ResetECRAM[] = { +u8 DRXD_ResetECRAM[] = { /* Reset packet sync bytes in EC_VD ram */ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000), WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000), @@ -530,7 +530,7 @@ u8_t DRXD_ResetECRAM[] = { END_OF_TABLE }; -u8_t DRXD_InitECA2[] = { +u8 DRXD_InitECA2[] = { WRBLOCK(EC_SB_REG_CSI_HI__A, 6), 0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */ 0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */ @@ -616,7 +616,7 @@ u8_t DRXD_InitECA2[] = { END_OF_TABLE }; -u8_t DRXD_InitECB1[] = { +u8 DRXD_InitECB1[] = { WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001), WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001), WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001), @@ -671,7 +671,7 @@ u8_t DRXD_InitECB1[] = { END_OF_TABLE }; -u8_t DRXD_ResetECA2[] = { +u8 DRXD_ResetECA2[] = { WR16(EC_OC_REG_COMM_EXEC__A, 0x0000), WR16(EC_OD_REG_COMM_EXEC__A, 0x0000), @@ -742,7 +742,7 @@ u8_t DRXD_ResetECA2[] = { END_OF_TABLE }; -u8_t DRXD_InitSC[] = { +u8 DRXD_InitSC[] = { WR16(SC_COMM_EXEC__A, 0), WR16(SC_COMM_STATE__A, 0), @@ -756,7 +756,7 @@ u8_t DRXD_InitSC[] = { /* Diversity settings */ -u8_t DRXD_InitDiversityFront[] = { +u8 DRXD_InitDiversityFront[] = { /* Start demod ********* RF in , diversity out **************************** */ WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | B_SC_RA_RAM_CONFIG_FREQSCAN__M), @@ -793,7 +793,7 @@ u8_t DRXD_InitDiversityFront[] = { END_OF_TABLE }; -u8_t DRXD_InitDiversityEnd[] = { +u8 DRXD_InitDiversityEnd[] = { /* End demod *********** combining RF in and diversity in, MPEG TS out **** */ /* disable near/far; switch on timing slave mode */ WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M | @@ -835,7 +835,7 @@ u8_t DRXD_InitDiversityEnd[] = { END_OF_TABLE }; -u8_t DRXD_DisableDiversity[] = { +u8 DRXD_DisableDiversity[] = { WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE), WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE), WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, @@ -876,7 +876,7 @@ u8_t DRXD_DisableDiversity[] = { END_OF_TABLE }; -u8_t DRXD_StartDiversityFront[] = { +u8 DRXD_StartDiversityFront[] = { /* Start demod, RF in and diversity out, no combining */ WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), WR16(B_FE_AD_REG_FDB_IN__A, 0x0), @@ -890,7 +890,7 @@ u8_t DRXD_StartDiversityFront[] = { END_OF_TABLE }; -u8_t DRXD_StartDiversityEnd[] = { +u8 DRXD_StartDiversityEnd[] = { /* End demod, combining RF in and diversity in, MPEG TS out */ WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */ WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */ @@ -903,7 +903,7 @@ u8_t DRXD_StartDiversityEnd[] = { END_OF_TABLE }; -u8_t DRXD_DiversityDelay8MHZ[] = { +u8 DRXD_DiversityDelay8MHZ[] = { WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50), WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50), WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50), @@ -915,7 +915,7 @@ u8_t DRXD_DiversityDelay8MHZ[] = { END_OF_TABLE }; -u8_t DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */ +u8 DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */ { WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50), WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50), diff --git a/drivers/media/dvb/frontends/drxd_firm.h b/drivers/media/dvb/frontends/drxd_firm.h index 367930a11426..41597e89941c 100644 --- a/drivers/media/dvb/frontends/drxd_firm.h +++ b/drivers/media/dvb/frontends/drxd_firm.h @@ -24,12 +24,9 @@ #ifndef _DRXD_FIRM_H_ #define _DRXD_FIRM_H_ +#include <linux/types.h> #include "drxd_map_firm.h" -typedef unsigned char u8_t; -typedef unsigned short u16_t; -typedef unsigned long u32_t; - #define VERSION_MAJOR 1 #define VERSION_MINOR 4 #define VERSION_PATCH 23 @@ -77,42 +74,42 @@ typedef unsigned long u32_t; #define DIFF_TARGET (4) #define DIFF_MARGIN (1) -extern u8_t DRXD_InitAtomicRead[]; -extern u8_t DRXD_HiI2cPatch_1[]; -extern u8_t DRXD_HiI2cPatch_3[]; - -extern u8_t DRXD_InitSC[]; - -extern u8_t DRXD_ResetCEFR[]; -extern u8_t DRXD_InitFEA2_1[]; -extern u8_t DRXD_InitFEA2_2[]; -extern u8_t DRXD_InitCPA2[]; -extern u8_t DRXD_InitCEA2[]; -extern u8_t DRXD_InitEQA2[]; -extern u8_t DRXD_InitECA2[]; -extern u8_t DRXD_ResetECA2[]; -extern u8_t DRXD_ResetECRAM[]; - -extern u8_t DRXD_A2_microcode[]; -extern u32_t DRXD_A2_microcode_length; - -extern u8_t DRXD_InitFEB1_1[]; -extern u8_t DRXD_InitFEB1_2[]; -extern u8_t DRXD_InitCPB1[]; -extern u8_t DRXD_InitCEB1[]; -extern u8_t DRXD_InitEQB1[]; -extern u8_t DRXD_InitECB1[]; - -extern u8_t DRXD_InitDiversityFront[]; -extern u8_t DRXD_InitDiversityEnd[]; -extern u8_t DRXD_DisableDiversity[]; -extern u8_t DRXD_StartDiversityFront[]; -extern u8_t DRXD_StartDiversityEnd[]; - -extern u8_t DRXD_DiversityDelay8MHZ[]; -extern u8_t DRXD_DiversityDelay6MHZ[]; - -extern u8_t DRXD_B1_microcode[]; -extern u32_t DRXD_B1_microcode_length; +extern u8 DRXD_InitAtomicRead[]; +extern u8 DRXD_HiI2cPatch_1[]; +extern u8 DRXD_HiI2cPatch_3[]; + +extern u8 DRXD_InitSC[]; + +extern u8 DRXD_ResetCEFR[]; +extern u8 DRXD_InitFEA2_1[]; +extern u8 DRXD_InitFEA2_2[]; +extern u8 DRXD_InitCPA2[]; +extern u8 DRXD_InitCEA2[]; +extern u8 DRXD_InitEQA2[]; +extern u8 DRXD_InitECA2[]; +extern u8 DRXD_ResetECA2[]; +extern u8 DRXD_ResetECRAM[]; + +extern u8 DRXD_A2_microcode[]; +extern u32 DRXD_A2_microcode_length; + +extern u8 DRXD_InitFEB1_1[]; +extern u8 DRXD_InitFEB1_2[]; +extern u8 DRXD_InitCPB1[]; +extern u8 DRXD_InitCEB1[]; +extern u8 DRXD_InitEQB1[]; +extern u8 DRXD_InitECB1[]; + +extern u8 DRXD_InitDiversityFront[]; +extern u8 DRXD_InitDiversityEnd[]; +extern u8 DRXD_DisableDiversity[]; +extern u8 DRXD_StartDiversityFront[]; +extern u8 DRXD_StartDiversityEnd[]; + +extern u8 DRXD_DiversityDelay8MHZ[]; +extern u8 DRXD_DiversityDelay6MHZ[]; + +extern u8 DRXD_B1_microcode[]; +extern u32 DRXD_B1_microcode_length; #endif -- cgit v1.2.3 From 7fc7356f4eafa953197e1c4e2d236e199a51db28 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab <mchehab@redhat.com> Date: Fri, 25 Mar 2011 10:54:03 -0300 Subject: [media] drxd: Fix some CodingStyle issues Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd.h | 2 +- drivers/media/dvb/frontends/drxd_firm.c | 8 ++++---- drivers/media/dvb/frontends/drxd_hard.c | 4 ---- 3 files changed, 5 insertions(+), 9 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h index d3d6c9246535..7113535844f2 100644 --- a/drivers/media/dvb/frontends/drxd.h +++ b/drivers/media/dvb/frontends/drxd.h @@ -49,7 +49,7 @@ struct drxd_config { u32 IF; int (*pll_set) (void *priv, void *priv_params, - u8 pll_addr, u8 demoda_addr, s32 * off); + u8 pll_addr, u8 demoda_addr, s32 *off); s16(*osc_deviation) (void *priv, s16 dev, int flag); }; diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c index 2949bde426b2..5418b0b1dadc 100644 --- a/drivers/media/dvb/frontends/drxd_firm.c +++ b/drivers/media/dvb/frontends/drxd_firm.c @@ -36,10 +36,10 @@ /* Is written via block write, must be little endian */ #define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF) -#define WRBLOCK(a,l) ADDRESS(a),LENGTH(l) -#define WR16(a,d) ADDRESS(a),LENGTH(1),DATA16(d) +#define WRBLOCK(a, l) ADDRESS(a), LENGTH(l) +#define WR16(a, d) ADDRESS(a), LENGTH(1), DATA16(d) -#define END_OF_TABLE 0xFF,0xFF,0xFF,0xFF +#define END_OF_TABLE 0xFF, 0xFF, 0xFF, 0xFF /* HI firmware patches */ @@ -63,7 +63,7 @@ u8 DRXD_InitAtomicRead[] = { /* Pins D0 and D1 of the parallel MPEG output can be used to set the I2C address of a device. */ -#define HI_RST_FUNC_ADDR ( HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE) +#define HI_RST_FUNC_ADDR (HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE) #define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */ /* D0 Version */ diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c index ed6c529946dd..e4440af31cd2 100644 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -2782,12 +2782,8 @@ struct dvb_frontend *drxd_attach(const struct drxd_config *config, if (Read16(state, 0, 0, 0) < 0) goto error; -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) - state->frontend.ops = &state->ops; -#else memcpy(&state->frontend.ops, &drxd_ops, sizeof(struct dvb_frontend_ops)); -#endif state->frontend.demodulator_priv = state; ConfigureMPEGOutput(state, 0); return &state->frontend; -- cgit v1.2.3 From 58d5eaec9f877a9bcfa9b6dca0ea51850975c49f Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab <mchehab@redhat.com> Date: Fri, 25 Mar 2011 11:45:29 -0300 Subject: [media] drxd: Don't use a macro for CHK_ERROR with a break inside The macro is defined as: #define CHK_ERROR(s) if( (status = s)<0 ) break This sucks, as makes harder to debug if something got wrong and there are more than one level of loops. Also, violates CodingStyle. Fixed by this simple perl script: while (<>) { $f.=$_; }; $f=~ s,\n\#define CHK_ERROR[^\n]+\n,\n,; $f=~ s=(CHK_ERROR\(.*\,)\n\s+=\1 =g; $f=~ s=(CHK_ERROR\(.*\,)\n\s+=\1 =g; $f=~ s=(CHK_ERROR\(.*\,)\n\s+=\1 =g; $f=~ s=(CHK_ERROR\(.*)\s+(\,)\n\s+=\1\2 =g; $f=~ s=(CHK_ERROR\(.*)\s+(\,)\n\s+=\1\2 =g; $f=~ s=(CHK_ERROR\(.*)\s+(\,)\n\s+=\1\2 =g; $f=~ s,\n(\t+)CHK_ERROR\((.*)\)\;,\n\1status = \2;\n\1if (status < 0)\n\1\tbreak;,g; print $f; Plus a few manual adjustments Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd_hard.c | 1075 ++++++++++++++++++------------- 1 file changed, 637 insertions(+), 438 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c index e4440af31cd2..df70e18fc9b6 100644 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -38,7 +38,6 @@ #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw" #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw" -#define CHK_ERROR(s) if( (status = s)<0 ) break #define CHUNK_SIZE 48 #define DRX_I2C_RMW 0x10 @@ -376,24 +375,36 @@ static int InitCE(struct drxd_state *state) enum app_env AppEnv = state->app_env_default; do { - CHK_ERROR(WriteTable(state, state->m_InitCE)); + status = WriteTable(state, state->m_InitCE); + if (status < 0) + break; if (state->operation_mode == OM_DVBT_Diversity_Front || state->operation_mode == OM_DVBT_Diversity_End) { AppEnv = state->app_env_diversity; } if (AppEnv == APPENV_STATIC) { - CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0000, 0)); + status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0); + if (status < 0) + break; } else if (AppEnv == APPENV_PORTABLE) { - CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0001, 0)); + status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0); + if (status < 0) + break; } else if (AppEnv == APPENV_MOBILE && state->type_A) { - CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0002, 0)); + status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0); + if (status < 0) + break; } else if (AppEnv == APPENV_MOBILE && !state->type_A) { - CHK_ERROR(Write16(state, CE_REG_TAPSET__A, 0x0006, 0)); + status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0); + if (status < 0) + break; } /* start ce */ - CHK_ERROR(Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0)); + status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0); + if (status < 0) + break; } while (0); return status; } @@ -408,46 +419,58 @@ static int StopOC(struct drxd_state *state) do { /* Store output configuration */ - CHK_ERROR(Read16(state, EC_OC_REG_SNC_ISC_LVL__A, - &ocSyncLvl, 0));; - /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, - &ocModeLop)); */ + status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); + if (status < 0) + break;; + /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */ state->m_EcOcRegSncSncLvl = ocSyncLvl; /* m_EcOcRegOcModeLop = ocModeLop; */ /* Flush FIFO (byte-boundary) at fixed rate */ - CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_LOP__A, - &dtoIncLop, 0)); - CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_HIP__A, - &dtoIncHip, 0)); - CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_LOP__A, - dtoIncLop, 0)); - CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_HIP__A, - dtoIncHip, 0)); + status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0); + if (status < 0) + break; + status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0); + if (status < 0) + break; + status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0); + if (status < 0) + break; + status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0); + if (status < 0) + break; ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M); ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC; - CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, - ocModeLop, 0)); - CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, - EC_OC_REG_COMM_EXEC_CTL_HOLD, 0)); + status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); + if (status < 0) + break; + status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); + if (status < 0) + break; msleep(1); /* Output pins to '0' */ - CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A, - EC_OC_REG_OCR_MPG_UOS__M, 0)); + status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0); + if (status < 0) + break; /* Force the OC out of sync */ ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M); - CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A, - ocSyncLvl, 0)); + status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0); + if (status < 0) + break; ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M); ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE; ocModeLop |= 0x2; /* Magically-out-of-sync */ - CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, - ocModeLop, 0)); - CHK_ERROR(Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0)); - CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, - EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0)); + status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0); + if (status < 0) + break; + status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0); + if (status < 0) + break; + status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); + if (status < 0) + break; } while (0); return status; @@ -459,22 +482,27 @@ static int StartOC(struct drxd_state *state) do { /* Stop OC */ - CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, - EC_OC_REG_COMM_EXEC_CTL_HOLD, 0)); + status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0); + if (status < 0) + break; /* Restore output configuration */ - CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A, - state->m_EcOcRegSncSncLvl, 0)); - CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, - state->m_EcOcRegOcModeLop, 0)); + status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0); + if (status < 0) + break; + status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0); + if (status < 0) + break; /* Output pins active again */ - CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A, - EC_OC_REG_OCR_MPG_UOS_INIT, 0)); + status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0); + if (status < 0) + break; /* Start OC */ - CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A, - EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0)); + status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0); + if (status < 0) + break; } while (0); return status; } @@ -551,17 +579,20 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) u16 FeAgRegPm1AgcWri; u16 FeAgRegAgModeLop; - CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, - &FeAgRegAgModeLop, 0)); + status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); + if (status < 0) + break; FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC; - CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, - FeAgRegAgModeLop, 0)); + status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); + if (status < 0) + break; FeAgRegPm1AgcWri = (u16) (cfg->outputLevel & FE_AG_REG_PM1_AGC_WRI__M); - CHK_ERROR(Write16(state, FE_AG_REG_PM1_AGC_WRI__A, - FeAgRegPm1AgcWri, 0)); + status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); + if (status < 0) + break; } while (0); } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { @@ -578,20 +609,23 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) /* == Mode == */ - CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, - &FeAgRegAgModeLop, 0)); + status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0); + if (status < 0) + break; FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M); FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC; - CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, - FeAgRegAgModeLop, 0)); + status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0); + if (status < 0) + break; /* == Settle level == */ FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) & FE_AG_REG_EGC_SET_LVL__M); - CHK_ERROR(Write16(state, FE_AG_REG_EGC_SET_LVL__A, - FeAgRegEgcSetLvl, 0)); + status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0); + if (status < 0) + break; /* == Min/Max == */ @@ -600,10 +634,12 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) offset = (u16) ((cfg->maxOutputLevel + cfg->minOutputLevel) / 2 - 511); - CHK_ERROR(Write16(state, FE_AG_REG_GC1_AGC_RIC__A, - slope, 0)); - CHK_ERROR(Write16(state, FE_AG_REG_GC1_AGC_OFF__A, - offset, 0)); + status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0); + if (status < 0) + break; + status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0); + if (status < 0) + break; /* == Speed == */ { @@ -649,21 +685,21 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) (fineSteps / (3 + 1))]; - CHK_ERROR(Write16(state, - FE_AG_REG_EGC_RUR_CNT__A, - rurCount, 0)); - CHK_ERROR(Write16(state, - FE_AG_REG_EGC_FAS_INC__A, - fastIncrDec, 0)); - CHK_ERROR(Write16(state, - FE_AG_REG_EGC_FAS_DEC__A, - fastIncrDec, 0)); - CHK_ERROR(Write16(state, - FE_AG_REG_EGC_SLO_INC__A, - slowIncrDec, 0)); - CHK_ERROR(Write16(state, - FE_AG_REG_EGC_SLO_DEC__A, - slowIncrDec, 0)); + status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0); + if (status < 0) + break; + status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0); + if (status < 0) + break; + status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0); + if (status < 0) + break; + status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0); + if (status < 0) + break; + status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0); + if (status < 0) + break; } } } while (0); @@ -690,8 +726,9 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) if (level == DRXD_FE_CTRL_MAX) level++; - CHK_ERROR(Write16(state, FE_AG_REG_PM2_AGC_WRI__A, - level, 0x0000)); + status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000); + if (status < 0) + break; /*==== Mode ====*/ @@ -699,31 +736,34 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M); state->m_FeAgRegAgPwd |= FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; - CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A, - state->m_FeAgRegAgPwd, 0x0000)); + status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); + if (status < 0) + break; - CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, - &AgModeLop, 0x0000)); + status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); + if (status < 0) + break; AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | FE_AG_REG_AG_MODE_LOP_MODE_E__M)); AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); - CHK_ERROR(Write16(state, FE_AG_REG_AG_MODE_LOP__A, - AgModeLop, 0x0000)); + status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); + if (status < 0) + break; /* enable AGC2 pin */ { u16 FeAgRegAgAgcSio = 0; - CHK_ERROR(Read16(state, - FE_AG_REG_AG_AGC_SIO__A, - &FeAgRegAgAgcSio, 0x0000)); + status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); + if (status < 0) + break; FeAgRegAgAgcSio &= ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); FeAgRegAgAgcSio |= FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; - CHK_ERROR(Write16(state, - FE_AG_REG_AG_AGC_SIO__A, - FeAgRegAgAgcSio, 0x0000)); + status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); + if (status < 0) + break; } } while (0); @@ -738,24 +778,26 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) ~(FE_AG_REG_AG_PWD_PWD_PD2__M); (state->m_FeAgRegAgPwd) |= FE_AG_REG_AG_PWD_PWD_PD2_DISABLE; - CHK_ERROR(Write16(state, FE_AG_REG_AG_PWD__A, - (state->m_FeAgRegAgPwd), 0x0000)); + status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); + if (status < 0) + break; - CHK_ERROR(Read16(state, FE_AG_REG_AG_MODE_LOP__A, - &AgModeLop, 0x0000)); + status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); + if (status < 0) + break; AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | FE_AG_REG_AG_MODE_LOP_MODE_E__M)); AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC); - CHK_ERROR(Write16(state, - FE_AG_REG_AG_MODE_LOP__A, - AgModeLop, 0x0000)); + status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); + if (status < 0) + break; /* Settle level */ level = (((cfg->settleLevel) >> 4) & FE_AG_REG_TGC_SET_LVL__M); - CHK_ERROR(Write16(state, - FE_AG_REG_TGC_SET_LVL__A, - level, 0x0000)); + status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000); + if (status < 0) + break; /* Min/max: don't care */ @@ -764,16 +806,16 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) /* enable AGC2 pin */ { u16 FeAgRegAgAgcSio = 0; - CHK_ERROR(Read16(state, - FE_AG_REG_AG_AGC_SIO__A, - &FeAgRegAgAgcSio, 0x0000)); + status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); + if (status < 0) + break; FeAgRegAgAgcSio &= ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); FeAgRegAgAgcSio |= FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT; - CHK_ERROR(Write16(state, - FE_AG_REG_AG_AGC_SIO__A, - FeAgRegAgAgcSio, 0x0000)); + status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); + if (status < 0) + break; } } while (0); @@ -787,34 +829,34 @@ static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg) ~(FE_AG_REG_AG_PWD_PWD_PD2__M); (state->m_FeAgRegAgPwd) |= FE_AG_REG_AG_PWD_PWD_PD2_ENABLE; - CHK_ERROR(Write16(state, - FE_AG_REG_AG_PWD__A, - (state->m_FeAgRegAgPwd), 0x0000)); + status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000); + if (status < 0) + break; - CHK_ERROR(Read16(state, - FE_AG_REG_AG_MODE_LOP__A, - &AgModeLop, 0x0000)); + status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); + if (status < 0) + break; AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M | FE_AG_REG_AG_MODE_LOP_MODE_E__M)); AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC | FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC); - CHK_ERROR(Write16(state, - FE_AG_REG_AG_MODE_LOP__A, - AgModeLop, 0x0000)); + status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); + if (status < 0) + break; /* set FeAgRegAgAgcSio AGC2 (RF) as input */ { u16 FeAgRegAgAgcSio = 0; - CHK_ERROR(Read16(state, - FE_AG_REG_AG_AGC_SIO__A, - &FeAgRegAgAgcSio, 0x0000)); + status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000); + if (status < 0) + break; FeAgRegAgAgcSio &= ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M); FeAgRegAgAgcSio |= FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT; - CHK_ERROR(Write16(state, - FE_AG_REG_AG_AGC_SIO__A, - FeAgRegAgAgcSio, 0x0000)); + status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000); + if (status < 0) + break; } } while (0); } @@ -1025,18 +1067,25 @@ static int AtomicReadBlock(struct drxd_state *state, do { /* Instruct HI to read n bytes */ /* TODO use proper names forthese egisters */ - CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, - (HI_TR_FUNC_ADDR & 0xFFFF), 0)); - CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, - (u16) (Addr >> 16), 0)); - CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, - (u16) (Addr & 0xFFFF), 0)); - CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, - (u16) ((DataSize / 2) - 1), 0)); - CHK_ERROR(Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, - HI_TR_READ, 0)); - - CHK_ERROR(HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0)); + status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0); + if (status < 0) + break; + status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0); + if (status < 0) + break; + status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0); + if (status < 0) + break; + status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0); + if (status < 0) + break; + status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0); + if (status < 0) + break; + + status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0); + if (status < 0) + break; } while (0); @@ -1137,50 +1186,58 @@ static int SetCfgPga(struct drxd_state *state, int pgaSwitch) if (pgaSwitch) { /* PGA on */ /* fine gain */ - CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, - &AgModeLop, 0x0000)); + status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); + if (status < 0) + break; AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC; - CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, - AgModeLop, 0x0000)); + status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); + if (status < 0) + break; /* coarse gain */ - CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, - &AgModeHip, 0x0000)); + status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); + if (status < 0) + break; AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC; - CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, - AgModeHip, 0x0000)); + status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); + if (status < 0) + break; /* enable fine and coarse gain, enable AAF, no ext resistor */ - CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, - B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, - 0x0000)); + status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000); + if (status < 0) + break; } else { /* PGA off, bypass */ /* fine gain */ - CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, - &AgModeLop, 0x0000)); + status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000); + if (status < 0) + break; AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M)); AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC; - CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, - AgModeLop, 0x0000)); + status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000); + if (status < 0) + break; /* coarse gain */ - CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, - &AgModeHip, 0x0000)); + status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000); + if (status < 0) + break; AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M)); AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC; - CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, - AgModeHip, 0x0000)); + status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000); + if (status < 0) + break; /* disable fine and coarse gain, enable AAF, no ext resistor */ - CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, - B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, - 0x0000)); + status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000); + if (status < 0) + break; } } while (0); @@ -1192,7 +1249,9 @@ static int InitFE(struct drxd_state *state) int status; do { - CHK_ERROR(WriteTable(state, state->m_InitFE_1)); + status = WriteTable(state, state->m_InitFE_1); + if (status < 0) + break; if (state->type_A) { status = Write16(state, FE_AG_REG_AG_PGA_MODE__A, @@ -1210,13 +1269,16 @@ static int InitFE(struct drxd_state *state) if (status < 0) break; - CHK_ERROR(Write16(state, FE_AG_REG_AG_AGC_SIO__A, - state->m_FeAgRegAgAgcSio, 0x0000)); - CHK_ERROR(Write16 - (state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, - 0x0000)); + status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000); + if (status < 0) + break; + status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000); + if (status < 0) + break; - CHK_ERROR(WriteTable(state, state->m_InitFE_2)); + status = WriteTable(state, state->m_InitFE_2); + if (status < 0) + break; } while (0); @@ -1294,12 +1356,22 @@ static int SC_SetPrefParamCommand(struct drxd_state *state, down(&state->mutex); do { - CHK_ERROR(SC_WaitForReady(state)); - CHK_ERROR(Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0)); - CHK_ERROR(Write16(state, SC_RA_RAM_PARAM1__A, param1, 0)); - CHK_ERROR(Write16(state, SC_RA_RAM_PARAM0__A, param0, 0)); + status = SC_WaitForReady(state); + if (status < 0) + break; + status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0); + if (status < 0) + break; + status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0); + if (status < 0) + break; + status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0); + if (status < 0) + break; - CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM)); + status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM); + if (status < 0) + break; } while (0); up(&state->mutex); return status; @@ -1312,9 +1384,15 @@ static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result) down(&state->mutex); do { - CHK_ERROR(SC_WaitForReady(state)); - CHK_ERROR(SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM)); - CHK_ERROR(Read16(state, SC_RA_RAM_PARAM0__A, result, 0)); + status = SC_WaitForReady(state); + if (status < 0) + break; + status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM); + if (status < 0) + break; + status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0); + if (status < 0) + break; } while (0); up(&state->mutex); return status; @@ -1331,8 +1409,7 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) u16 EcOcRegOcModeHip = 0; u16 EcOcRegOcMpgSio = 0; - /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, - &EcOcRegOcModeLop, 0)); */ + /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */ if (state->operation_mode == OM_DVBT_Diversity_Front) { if (bEnableOutput) { @@ -1396,14 +1473,18 @@ static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput) EcOcRegIprInvMpg &= (~(0x0800)); /* EcOcRegOcModeLop =0x05; */ - CHK_ERROR(Write16(state, EC_OC_REG_IPR_INV_MPG__A, - EcOcRegIprInvMpg, 0)); - CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A, - EcOcRegOcModeLop, 0)); - CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_HIP__A, - EcOcRegOcModeHip, 0x0000)); - CHK_ERROR(Write16(state, EC_OC_REG_OC_MPG_SIO__A, - EcOcRegOcMpgSio, 0)); + status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0); + if (status < 0) + break; + status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0); + if (status < 0) + break; + status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0); + if (status < 0) + break; } while (0); return status; } @@ -1414,9 +1495,13 @@ static int SetDeviceTypeId(struct drxd_state *state) u16 deviceId = 0; do { - CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); + status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); + if (status < 0) + break; /* TODO: why twice? */ - CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0)); + status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); + if (status < 0) + break; printk("drxd: deviceId = %04x\n", deviceId); state->type_A = 0; @@ -1512,9 +1597,12 @@ static int CorrectSysClockDeviation(struct drxd_state *state) /* These accesses should be AtomicReadReg32, but that causes trouble (at least for diversity */ - CHK_ERROR(Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, - ((u32 *) & nomincr), 0)); - CHK_ERROR(Read32(state, FE_IF_REG_INCR0__A, (u32 *) & incr, 0)); + status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) & nomincr), 0); + if (status < 0) + break; + status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) & incr, 0); + if (status < 0) + break; if (state->type_A) { if ((nomincr - incr < -500) || (nomincr - incr > 500)) @@ -1571,13 +1659,14 @@ static int CorrectSysClockDeviation(struct drxd_state *state) } } /* switch OFF SRMM scan in SC */ - CHK_ERROR(Write16(state, - SC_RA_RAM_SAMPLE_RATE_COUNT__A, - DRXD_OSCDEV_DONT_SCAN, 0)); + status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0); + if (status < 0) + break; /* overrule FE_IF internal value for proper re-locking */ - CHK_ERROR(Write16(state, SC_RA_RAM_IF_SAVE__AX, - state->current_fe_if_incr, 0)); + status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0); + if (status < 0) + break; state->cscd_state = CSCD_SAVED; } } while (0); @@ -1595,46 +1684,56 @@ static int DRX_Stop(struct drxd_state *state) do { if (state->cscd_state != CSCD_SAVED) { u32 lock; - CHK_ERROR(DRX_GetLockStatus(state, &lock)); + status = DRX_GetLockStatus(state, &lock); + if (status < 0) + break; } - CHK_ERROR(StopOC(state)); + status = StopOC(state); + if (status < 0) + break; state->drxd_state = DRXD_STOPPED; - CHK_ERROR(ConfigureMPEGOutput(state, 0)); + status = ConfigureMPEGOutput(state, 0); + if (status < 0) + break; if (state->type_A) { /* Stop relevant processors off the device */ - CHK_ERROR(Write16(state, EC_OD_REG_COMM_EXEC__A, - 0x0000, 0x0000)); + status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000); + if (status < 0) + break; - CHK_ERROR(Write16(state, SC_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0)); - CHK_ERROR(Write16(state, LC_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0)); + status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); + if (status < 0) + break; + status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); + if (status < 0) + break; } else { /* Stop all processors except HI & CC & FE */ - CHK_ERROR(Write16(state, - B_SC_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0)); - CHK_ERROR(Write16(state, - B_LC_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0)); - CHK_ERROR(Write16(state, - B_FT_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0)); - CHK_ERROR(Write16(state, - B_CP_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0)); - CHK_ERROR(Write16(state, - B_CE_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0)); - CHK_ERROR(Write16(state, - B_EQ_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0)); - CHK_ERROR(Write16(state, - EC_OD_REG_COMM_EXEC__A, 0x0000, 0)); + status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); + if (status < 0) + break; + status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); + if (status < 0) + break; + status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); + if (status < 0) + break; + status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); + if (status < 0) + break; + status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); + if (status < 0) + break; + status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); + if (status < 0) + break; + status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0); + if (status < 0) + break; } } while (0); @@ -1689,33 +1788,35 @@ static int StartDiversity(struct drxd_state *state) do { if (state->operation_mode == OM_DVBT_Diversity_Front) { - CHK_ERROR(WriteTable(state, - state->m_StartDiversityFront)); + status = WriteTable(state, state->m_StartDiversityFront); + if (status < 0) + break; } else if (state->operation_mode == OM_DVBT_Diversity_End) { - CHK_ERROR(WriteTable(state, - state->m_StartDiversityEnd)); + status = WriteTable(state, state->m_StartDiversityEnd); + if (status < 0) + break; if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) { - CHK_ERROR(WriteTable(state, - state-> - m_DiversityDelay8MHZ)); + status = WriteTable(state, state->m_DiversityDelay8MHZ); + if (status < 0) + break; } else { - CHK_ERROR(WriteTable(state, - state-> - m_DiversityDelay6MHZ)); + status = WriteTable(state, state->m_DiversityDelay6MHZ); + if (status < 0) + break; } - CHK_ERROR(Read16(state, - B_EQ_REG_RC_SEL_CAR__A, - &rcControl, 0)); + status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0); + if (status < 0) + break; rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M); rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON | /* combining enabled */ B_EQ_REG_RC_SEL_CAR_MEAS_A_CC | B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC; - CHK_ERROR(Write16(state, - B_EQ_REG_RC_SEL_CAR__A, - rcControl, 0)); + status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0); + if (status < 0) + break; } } while (0); return status; @@ -1767,23 +1868,28 @@ static int SetCfgNoiseCalibration(struct drxd_state *state, int status = 0; do { - CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0)); + status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0); + if (status < 0) + break; if (noiseCal->cpOpt) { beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); } else { beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT); - CHK_ERROR(Write16(state, CP_REG_AC_NEXP_OFFS__A, - noiseCal->cpNexpOfs, 0)); + status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0); + if (status < 0) + break; } - CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0)); + status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0); + if (status < 0) + break; if (!state->type_A) { - CHK_ERROR(Write16(state, - B_SC_RA_RAM_CO_TD_CAL_2K__A, - noiseCal->tdCal2k, 0)); - CHK_ERROR(Write16(state, - B_SC_RA_RAM_CO_TD_CAL_8K__A, - noiseCal->tdCal8k, 0)); + status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0); + if (status < 0) + break; + status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0); + if (status < 0) + break; } } while (0); @@ -1823,21 +1929,39 @@ static int DRX_Start(struct drxd_state *state, s32 off) do { if (state->drxd_state != DRXD_STOPPED) return -1; - CHK_ERROR(ResetECOD(state)); + status = ResetECOD(state); + if (status < 0) + break; if (state->type_A) { - CHK_ERROR(InitSC(state)); + status = InitSC(state); + if (status < 0) + break; } else { - CHK_ERROR(InitFT(state)); - CHK_ERROR(InitCP(state)); - CHK_ERROR(InitCE(state)); - CHK_ERROR(InitEQ(state)); - CHK_ERROR(InitSC(state)); + status = InitFT(state); + if (status < 0) + break; + status = InitCP(state); + if (status < 0) + break; + status = InitCE(state); + if (status < 0) + break; + status = InitEQ(state); + if (status < 0) + break; + status = InitSC(state); + if (status < 0) + break; } /* Restore current IF & RF AGC settings */ - CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg)); - CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg)); + status = SetCfgIfAgc(state, &state->if_agc_cfg); + if (status < 0) + break; + status = SetCfgRfAgc(state, &state->rf_agc_cfg); + if (status < 0) + break; mirrorFreqSpect = (state->param.inversion == INVERSION_ON); @@ -1848,10 +1972,9 @@ static int DRX_Start(struct drxd_state *state, s32 off) case TRANSMISSION_MODE_8K: transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K; if (state->type_A) { - CHK_ERROR(Write16(state, - EC_SB_REG_TR_MODE__A, - EC_SB_REG_TR_MODE_8K, - 0x0000)); + status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000); + if (status < 0) + break; qpskSnCeGain = 99; qam16SnCeGain = 83; qam64SnCeGain = 67; @@ -1860,10 +1983,9 @@ static int DRX_Start(struct drxd_state *state, s32 off) case TRANSMISSION_MODE_2K: transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K; if (state->type_A) { - CHK_ERROR(Write16(state, - EC_SB_REG_TR_MODE__A, - EC_SB_REG_TR_MODE_2K, - 0x0000)); + status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000); + if (status < 0) + break; qpskSnCeGain = 97; qam16SnCeGain = 71; qam64SnCeGain = 65; @@ -1895,10 +2017,12 @@ static int DRX_Start(struct drxd_state *state, s32 off) case HIERARCHY_1: transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1; if (state->type_A) { - CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, - 0x0001, 0x0000)); - CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, - 0x0001, 0x0000)); + status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000); + if (status < 0) + break; qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1; @@ -1923,10 +2047,12 @@ static int DRX_Start(struct drxd_state *state, s32 off) case HIERARCHY_2: transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2; if (state->type_A) { - CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, - 0x0002, 0x0000)); - CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, - 0x0002, 0x0000)); + status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000); + if (status < 0) + break; qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2; @@ -1950,10 +2076,12 @@ static int DRX_Start(struct drxd_state *state, s32 off) case HIERARCHY_4: transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4; if (state->type_A) { - CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, - 0x0003, 0x0000)); - CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, - 0x0003, 0x0000)); + status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000); + if (status < 0) + break; qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN; qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4; @@ -1980,10 +2108,12 @@ static int DRX_Start(struct drxd_state *state, s32 off) operationMode |= SC_RA_RAM_OP_AUTO_HIER__M; transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO; if (state->type_A) { - CHK_ERROR(Write16(state, EQ_REG_OT_ALPHA__A, - 0x0000, 0x0000)); - CHK_ERROR(Write16(state, EC_SB_REG_ALPHA__A, - 0x0000, 0x0000)); + status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000); + if (status < 0) + break; qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK; qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN; @@ -2005,7 +2135,9 @@ static int DRX_Start(struct drxd_state *state, s32 off) } break; } - CHK_ERROR(status); + status = status; + if (status < 0) + break; switch (p->constellation) { default: @@ -2015,111 +2147,123 @@ static int DRX_Start(struct drxd_state *state, s32 off) case QAM_64: transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64; if (state->type_A) { - CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, - 0x0002, 0x0000)); - CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, - EC_SB_REG_CONST_64QAM, - 0x0000)); - CHK_ERROR(Write16(state, - EC_SB_REG_SCALE_MSB__A, - 0x0020, 0x0000)); - CHK_ERROR(Write16(state, - EC_SB_REG_SCALE_BIT2__A, - 0x0008, 0x0000)); - CHK_ERROR(Write16(state, - EC_SB_REG_SCALE_LSB__A, - 0x0002, 0x0000)); - - CHK_ERROR(Write16(state, - EQ_REG_TD_TPS_PWR_OFS__A, - qam64TdTpsPwr, 0x0000)); - CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A, - qam64SnCeGain, 0x0000)); - CHK_ERROR(Write16(state, EQ_REG_IS_GAIN_MAN__A, - qam64IsGainMan, 0x0000)); - CHK_ERROR(Write16(state, EQ_REG_IS_GAIN_EXP__A, - qam64IsGainExp, 0x0000)); + status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000); + if (status < 0) + break; + + status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000); + if (status < 0) + break; + status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000); + if (status < 0) + break; + status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000); + if (status < 0) + break; + status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000); + if (status < 0) + break; } break; case QPSK: transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK; if (state->type_A) { - CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, - 0x0000, 0x0000)); - CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, - EC_SB_REG_CONST_QPSK, - 0x0000)); - CHK_ERROR(Write16(state, - EC_SB_REG_SCALE_MSB__A, - 0x0010, 0x0000)); - CHK_ERROR(Write16(state, - EC_SB_REG_SCALE_BIT2__A, - 0x0000, 0x0000)); - CHK_ERROR(Write16(state, - EC_SB_REG_SCALE_LSB__A, - 0x0000, 0x0000)); - - CHK_ERROR(Write16(state, - EQ_REG_TD_TPS_PWR_OFS__A, - qpskTdTpsPwr, 0x0000)); - CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A, - qpskSnCeGain, 0x0000)); - CHK_ERROR(Write16(state, - EQ_REG_IS_GAIN_MAN__A, - qpskIsGainMan, 0x0000)); - CHK_ERROR(Write16(state, - EQ_REG_IS_GAIN_EXP__A, - qpskIsGainExp, 0x0000)); + status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); + if (status < 0) + break; + + status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000); + if (status < 0) + break; + status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000); + if (status < 0) + break; + status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000); + if (status < 0) + break; + status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000); + if (status < 0) + break; } break; case QAM_16: transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16; if (state->type_A) { - CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A, - 0x0001, 0x0000)); - CHK_ERROR(Write16(state, EC_SB_REG_CONST__A, - EC_SB_REG_CONST_16QAM, - 0x0000)); - CHK_ERROR(Write16(state, - EC_SB_REG_SCALE_MSB__A, - 0x0010, 0x0000)); - CHK_ERROR(Write16(state, - EC_SB_REG_SCALE_BIT2__A, - 0x0004, 0x0000)); - CHK_ERROR(Write16(state, - EC_SB_REG_SCALE_LSB__A, - 0x0000, 0x0000)); - - CHK_ERROR(Write16(state, - EQ_REG_TD_TPS_PWR_OFS__A, - qam16TdTpsPwr, 0x0000)); - CHK_ERROR(Write16(state, EQ_REG_SN_CEGAIN__A, - qam16SnCeGain, 0x0000)); - CHK_ERROR(Write16(state, - EQ_REG_IS_GAIN_MAN__A, - qam16IsGainMan, 0x0000)); - CHK_ERROR(Write16(state, - EQ_REG_IS_GAIN_EXP__A, - qam16IsGainExp, 0x0000)); + status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000); + if (status < 0) + break; + status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000); + if (status < 0) + break; + + status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000); + if (status < 0) + break; + status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000); + if (status < 0) + break; + status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000); + if (status < 0) + break; + status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000); + if (status < 0) + break; } break; } - CHK_ERROR(status); + status = status; + if (status < 0) + break; switch (DRX_CHANNEL_HIGH) { default: case DRX_CHANNEL_AUTO: case DRX_CHANNEL_LOW: transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO; - CHK_ERROR(Write16(state, EC_SB_REG_PRIOR__A, - EC_SB_REG_PRIOR_LO, 0x0000)); + status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000); + if (status < 0) + break; break; case DRX_CHANNEL_HIGH: transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI; - CHK_ERROR(Write16(state, EC_SB_REG_PRIOR__A, - EC_SB_REG_PRIOR_HI, 0x0000)); + status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000); + if (status < 0) + break; break; } @@ -2128,10 +2272,9 @@ static int DRX_Start(struct drxd_state *state, s32 off) case FEC_1_2: transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2; if (state->type_A) { - CHK_ERROR(Write16(state, - EC_VD_REG_SET_CODERATE__A, - EC_VD_REG_SET_CODERATE_C1_2, - 0x0000)); + status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000); + if (status < 0) + break; } break; default: @@ -2139,41 +2282,39 @@ static int DRX_Start(struct drxd_state *state, s32 off) case FEC_2_3: transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3; if (state->type_A) { - CHK_ERROR(Write16(state, - EC_VD_REG_SET_CODERATE__A, - EC_VD_REG_SET_CODERATE_C2_3, - 0x0000)); + status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000); + if (status < 0) + break; } break; case FEC_3_4: transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4; if (state->type_A) { - CHK_ERROR(Write16(state, - EC_VD_REG_SET_CODERATE__A, - EC_VD_REG_SET_CODERATE_C3_4, - 0x0000)); + status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000); + if (status < 0) + break; } break; case FEC_5_6: transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6; if (state->type_A) { - CHK_ERROR(Write16(state, - EC_VD_REG_SET_CODERATE__A, - EC_VD_REG_SET_CODERATE_C5_6, - 0x0000)); + status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000); + if (status < 0) + break; } break; case FEC_7_8: transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8; if (state->type_A) { - CHK_ERROR(Write16(state, - EC_VD_REG_SET_CODERATE__A, - EC_VD_REG_SET_CODERATE_C7_8, - 0x0000)); + status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000); + if (status < 0) + break; } break; } - CHK_ERROR(status); + status = status; + if (status < 0) + break; /* First determine real bandwidth (Hz) */ /* Also set delay for impulse noise cruncher (only A2) */ @@ -2207,15 +2348,19 @@ static int DRX_Start(struct drxd_state *state, s32 off) FE_AG_REG_IND_DEL__A, 71, 0x0000); break; } - CHK_ERROR(status); + status = status; + if (status < 0) + break; - CHK_ERROR(Write16(state, - SC_RA_RAM_BAND__A, bandwidthParam, 0x0000)); + status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000); + if (status < 0) + break; { u16 sc_config; - CHK_ERROR(Read16(state, - SC_RA_RAM_CONFIG__A, &sc_config, 0)); + status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0); + if (status < 0) + break; /* enable SLAVE mode in 2k 1/32 to prevent timing change glitches */ @@ -2227,19 +2372,21 @@ static int DRX_Start(struct drxd_state *state, s32 off) /* disable slave */ sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M; } - CHK_ERROR(Write16(state, - SC_RA_RAM_CONFIG__A, sc_config, 0)); + status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0); + if (status < 0) + break; } - CHK_ERROR(SetCfgNoiseCalibration(state, &state->noise_cal)); + status = SetCfgNoiseCalibration(state, &state->noise_cal); + if (status < 0) + break; if (state->cscd_state == CSCD_INIT) { /* switch on SRMM scan in SC */ - CHK_ERROR(Write16(state, - SC_RA_RAM_SAMPLE_RATE_COUNT__A, - DRXD_OSCDEV_DO_SCAN, 0x0000)); -/* CHK_ERROR( Write16( SC_RA_RAM_SAMPLE_RATE_STEP__A, - DRXD_OSCDEV_STEP , 0x0000 ));*/ + status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000); + if (status < 0) + break; +/* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/ state->cscd_state = CSCD_SET; } @@ -2248,14 +2395,12 @@ static int DRX_Start(struct drxd_state *state, s32 off) ((SysFreq / BandWidth) * (2^21) ) - (2^23) */ feIfIncr = MulDiv32(state->sys_clock_freq * 1000, (1ULL << 21), bandwidth) - (1 << 23); - CHK_ERROR(Write16(state, - FE_IF_REG_INCR0__A, - (u16) (feIfIncr & FE_IF_REG_INCR0__M), - 0x0000)); - CHK_ERROR(Write16(state, - FE_IF_REG_INCR1__A, - (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & - FE_IF_REG_INCR1__M), 0x0000)); + status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000); + if (status < 0) + break; + status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000); + if (status < 0) + break; /* Bandwidth setting done */ /* Mirror & frequency offset */ @@ -2264,8 +2409,12 @@ static int DRX_Start(struct drxd_state *state, s32 off) /* Start SC, write channel settings to SC */ /* Enable SC after setting all other parameters */ - CHK_ERROR(Write16(state, SC_COMM_STATE__A, 0, 0x0000)); - CHK_ERROR(Write16(state, SC_COMM_EXEC__A, 1, 0x0000)); + status = Write16(state, SC_COMM_STATE__A, 0, 0x0000); + if (status < 0) + break; + status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000); + if (status < 0) + break; /* Write SC parameter registers, operation mode */ #if 1 @@ -2275,19 +2424,23 @@ static int DRX_Start(struct drxd_state *state, s32 off) SC_RA_RAM_OP_AUTO_HIER__M | SC_RA_RAM_OP_AUTO_RATE__M); #endif - CHK_ERROR(SC_SetPrefParamCommand(state, 0x0000, - transmissionParams, - operationMode)); + status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode); + if (status < 0) + break; /* Start correct processes to get in lock */ - CHK_ERROR(SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, - SC_RA_RAM_SW_EVENT_RUN_NMASK__M, - SC_RA_RAM_LOCKTRACK_MIN)); + status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN); + if (status < 0) + break; - CHK_ERROR(StartOC(state)); + status = StartOC(state); + if (status < 0) + break; if (state->operation_mode != OM_Default) { - CHK_ERROR(StartDiversity(state)); + status = StartDiversity(state); + if (status < 0) + break; } state->drxd_state = DRXD_STARTED; @@ -2463,22 +2616,34 @@ int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size) do { state->operation_mode = OM_Default; - CHK_ERROR(SetDeviceTypeId(state)); + status = SetDeviceTypeId(state); + if (status < 0) + break; /* Apply I2c address patch to B1 */ if (!state->type_A && state->m_HiI2cPatch != NULL) - CHK_ERROR(WriteTable(state, state->m_HiI2cPatch)); + status = WriteTable(state, state->m_HiI2cPatch); + if (status < 0) + break; if (state->type_A) { /* HI firmware patch for UIO readout, avoid clearing of result register */ - CHK_ERROR(Write16(state, 0x43012D, 0x047f, 0)); + status = Write16(state, 0x43012D, 0x047f, 0); + if (status < 0) + break; } - CHK_ERROR(HI_ResetCommand(state)); + status = HI_ResetCommand(state); + if (status < 0) + break; - CHK_ERROR(StopAllProcessors(state)); - CHK_ERROR(InitCC(state)); + status = StopAllProcessors(state); + if (status < 0) + break; + status = InitCC(state); + if (status < 0) + break; state->osc_clock_deviation = 0; @@ -2506,18 +2671,29 @@ int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size) (u16) ((state->expected_sys_clock_freq) + deviation); } - CHK_ERROR(InitHI(state)); - CHK_ERROR(InitAtomicRead(state)); + status = InitHI(state); + if (status < 0) + break; + status = InitAtomicRead(state); + if (status < 0) + break; - CHK_ERROR(EnableAndResetMB(state)); + status = EnableAndResetMB(state); + if (status < 0) + break; if (state->type_A) - CHK_ERROR(ResetCEFR(state)); + status = ResetCEFR(state); + if (status < 0) + break; if (fw) { - CHK_ERROR(DownloadMicrocode(state, fw, fw_size)); + status = DownloadMicrocode(state, fw, fw_size); + if (status < 0) + break; } else { - CHK_ERROR(DownloadMicrocode(state, state->microcode, - state->microcode_length)); + status = DownloadMicrocode(state, state->microcode, state->microcode_length); + if (status < 0) + break; } if (state->PGA) { @@ -2529,22 +2705,42 @@ int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size) state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO; - CHK_ERROR(InitFE(state)); - CHK_ERROR(InitFT(state)); - CHK_ERROR(InitCP(state)); - CHK_ERROR(InitCE(state)); - CHK_ERROR(InitEQ(state)); - CHK_ERROR(InitEC(state)); - CHK_ERROR(InitSC(state)); + status = InitFE(state); + if (status < 0) + break; + status = InitFT(state); + if (status < 0) + break; + status = InitCP(state); + if (status < 0) + break; + status = InitCE(state); + if (status < 0) + break; + status = InitEQ(state); + if (status < 0) + break; + status = InitEC(state); + if (status < 0) + break; + status = InitSC(state); + if (status < 0) + break; - CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg)); - CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg)); + status = SetCfgIfAgc(state, &state->if_agc_cfg); + if (status < 0) + break; + status = SetCfgRfAgc(state, &state->rf_agc_cfg); + if (status < 0) + break; state->cscd_state = CSCD_INIT; - CHK_ERROR(Write16(state, SC_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0)); - CHK_ERROR(Write16(state, LC_COMM_EXEC__A, - SC_COMM_EXEC_CTL_STOP, 0)); + status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); + if (status < 0) + break; + status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0); + if (status < 0) + break; driverVersion = (((VERSION_MAJOR / 10) << 4) + (VERSION_MAJOR % 10)) << 24; @@ -2554,10 +2750,13 @@ int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size) ((VERSION_PATCH / 100) << 8) + ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10); - CHK_ERROR(Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, - driverVersion, 0)); + status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0); + if (status < 0) + break; - CHK_ERROR(StopOC(state)); + status = StopOC(state); + if (status < 0) + break; state->drxd_state = DRXD_STOPPED; state->init_done = 1; -- cgit v1.2.3 From 9999daf446b9fa43b5301af423b6798a600e36bc Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab <mchehab@redhat.com> Date: Fri, 25 Mar 2011 12:10:05 -0300 Subject: [media] drxd: CodingStyle cleanups There are still lots of 80-columns warnings and a few errors at some tables, but changing them would require more work and with probably not much gain. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd_hard.c | 87 ++++++++++++++++----------------- 1 file changed, 43 insertions(+), 44 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c index df70e18fc9b6..117df556ec3e 100644 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -209,7 +209,7 @@ struct drxd_state { static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len) { - struct i2c_msg msg = {.addr = adr,.flags = 0,.buf = data,.len = len }; + struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len }; if (i2c_transfer(adap, &msg, 1) != 1) return -1; @@ -217,12 +217,16 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len) } static int i2c_read(struct i2c_adapter *adap, - u8 adr, u8 * msg, int len, u8 * answ, int alen) + u8 adr, u8 *msg, int len, u8 *answ, int alen) { - struct i2c_msg msgs[2] = { {.addr = adr,.flags = 0, - .buf = msg,.len = len}, - {.addr = adr,.flags = I2C_M_RD, - .buf = answ,.len = alen} + struct i2c_msg msgs[2] = { + { + .addr = adr, .flags = 0, + .buf = msg, .len = len + }, { + .addr = adr, .flags = I2C_M_RD, + .buf = answ, .len = alen + } }; if (i2c_transfer(adap, msgs, 2) != 2) return -1; @@ -233,13 +237,13 @@ inline u32 MulDiv32(u32 a, u32 b, u32 c) { u64 tmp64; - tmp64 = (u64) a *(u64) b; + tmp64 = (u64)a * (u64)b; do_div(tmp64, c); return (u32) tmp64; } -static int Read16(struct drxd_state *state, u32 reg, u16 * data, u8 flags) +static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags) { u8 adr = state->config.demod_address; u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, @@ -253,7 +257,7 @@ static int Read16(struct drxd_state *state, u32 reg, u16 * data, u8 flags) return mm2[0] | (mm2[1] << 8); } -static int Read32(struct drxd_state *state, u32 reg, u32 * data, u8 flags) +static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags) { u8 adr = state->config.demod_address; u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff, @@ -297,7 +301,7 @@ static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags) } static int write_chunk(struct drxd_state *state, - u32 reg, u8 * data, u32 len, u8 flags) + u32 reg, u8 *data, u32 len, u8 flags) { u8 adr = state->config.demod_address; u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff, @@ -308,14 +312,14 @@ static int write_chunk(struct drxd_state *state, for (i = 0; i < len; i++) mm[4 + i] = data[i]; if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) { - printk("error in write_chunk\n"); + printk(KERN_ERR "error in write_chunk\n"); return -1; } return 0; } static int WriteBlock(struct drxd_state *state, - u32 Address, u16 BlockSize, u8 * pBlock, u8 Flags) + u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags) { while (BlockSize > 0) { u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize; @@ -421,7 +425,7 @@ static int StopOC(struct drxd_state *state) /* Store output configuration */ status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0); if (status < 0) - break;; + break; /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */ state->m_EcOcRegSncSncLvl = ocSyncLvl; /* m_EcOcRegOcModeLop = ocModeLop; */ @@ -545,7 +549,7 @@ static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus) status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000); if (status < 0) { - printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n", status); + printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status); return status; } @@ -593,15 +597,14 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0); if (status < 0) break; - } - while (0); + } while (0); } else if (cfg->ctrlMode == AGC_CTRL_AUTO) { if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) || ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) || ((cfg->speed) > DRXD_FE_CTRL_MAX) || ((cfg->settleLevel) > DRXD_FE_CTRL_MAX) ) - return (-1); + return -1; do { u16 FeAgRegAgModeLop; u16 FeAgRegEgcSetLvl; @@ -706,7 +709,7 @@ static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg) } else { /* No OFF mode for IF control */ - return (-1); + return -1; } return status; } @@ -919,7 +922,7 @@ static int load_firmware(struct drxd_state *state, const char *fw_name) } static int DownloadMicrocode(struct drxd_state *state, - const u8 * pMCImage, u32 Length) + const u8 *pMCImage, u32 Length) { u8 *pSrc; u16 Flags; @@ -973,7 +976,8 @@ static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult) u16 waitCmd; int status; - if ((status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0)) < 0) + status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0); + if (status < 0) return status; do { @@ -1053,7 +1057,7 @@ static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge) #if 0 static int AtomicReadBlock(struct drxd_state *state, - u32 Addr, u16 DataSize, u8 * pData, u8 Flags) + u32 Addr, u16 DataSize, u8 *pData, u8 Flags) { int status; int i = 0; @@ -1106,7 +1110,7 @@ static int AtomicReadBlock(struct drxd_state *state, } static int AtomicReadReg32(struct drxd_state *state, - u32 Addr, u32 * pData, u8 Flags) + u32 Addr, u32 *pData, u8 Flags) { u8 buf[sizeof(u32)]; int status; @@ -1145,7 +1149,7 @@ static int InitCC(struct drxd_state *state) if (state->osc_clock_freq == 0 || state->osc_clock_freq > 20000 || (state->osc_clock_freq % 4000) != 0) { - printk("invalid osc frequency %d\n", state->osc_clock_freq); + printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq); return -1; } @@ -1239,8 +1243,7 @@ static int SetCfgPga(struct drxd_state *state, int pgaSwitch) if (status < 0) break; } - } - while (0); + } while (0); return status; } @@ -1318,7 +1321,7 @@ static int SC_SendCommand(struct drxd_state *state, u16 cmd) Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0); if (errCode == 0xFFFF) { - printk("Command Error\n"); + printk(KERN_ERR "Command Error\n"); status = -1; } @@ -1502,17 +1505,17 @@ static int SetDeviceTypeId(struct drxd_state *state) status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0); if (status < 0) break; - printk("drxd: deviceId = %04x\n", deviceId); + printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId); state->type_A = 0; state->PGA = 0; state->diversity = 0; if (deviceId == 0) { /* on A2 only 3975 available */ state->type_A = 1; - printk("DRX3975D-A2\n"); + printk(KERN_INFO "DRX3975D-A2\n"); } else { deviceId >>= 12; - printk("DRX397%dD-B1\n", deviceId); + printk(KERN_INFO "DRX397%dD-B1\n", deviceId); switch (deviceId) { case 4: state->diversity = 1; @@ -1597,10 +1600,10 @@ static int CorrectSysClockDeviation(struct drxd_state *state) /* These accesses should be AtomicReadReg32, but that causes trouble (at least for diversity */ - status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) & nomincr), 0); + status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0); if (status < 0) break; - status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) & incr, 0); + status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0); if (status < 0) break; @@ -1633,9 +1636,8 @@ static int CorrectSysClockDeviation(struct drxd_state *state) sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21); sysClockFreq = (u32) (sysClockInHz / 1000); /* rounding */ - if ((sysClockInHz % 1000) > 500) { + if ((sysClockInHz % 1000) > 500) sysClockFreq++; - } /* Compute clock deviation in ppm */ oscClockDeviation = (u16) ((((s32) (sysClockFreq) - @@ -1646,7 +1648,7 @@ static int CorrectSysClockDeviation(struct drxd_state *state) (state->expected_sys_clock_freq)); Diff = oscClockDeviation - state->osc_clock_deviation; - /*printk("sysclockdiff=%d\n", Diff); */ + /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */ if (Diff >= -200 && Diff <= 200) { state->sys_clock_freq = (u16) sysClockFreq; if (oscClockDeviation != state->osc_clock_deviation) { @@ -1671,7 +1673,7 @@ static int CorrectSysClockDeviation(struct drxd_state *state) } } while (0); - return (status); + return status; } static int DRX_Stop(struct drxd_state *state) @@ -1843,9 +1845,8 @@ static int SetFrequencyShift(struct drxd_state *state, 1 << 28, state->sys_clock_freq); /* Remove integer part */ state->fe_fs_add_incr &= 0x0FFFFFFFL; - if (negativeShift) { + if (negativeShift) state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr); - } /* Save the frequency shift without tunerOffset compensation for CtrlGetChannel. */ @@ -2530,9 +2531,8 @@ static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency) state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed); } - if (ulRfAgcMode == 2) { + if (ulRfAgcMode == 2) state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF; - } if (ulEnvironment <= 2) state->app_env_default = (enum app_env) @@ -2842,6 +2842,7 @@ int drxd_config_i2c(struct dvb_frontend *fe, int onoff) return DRX_ConfigureI2CBridge(state, onoff); } +EXPORT_SYMBOL(drxd_config_i2c); static int drxd_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *sets) @@ -2909,7 +2910,7 @@ static int drxd_set_frontend(struct dvb_frontend *fe, state->config.pll_set(state->priv, param, state->config.pll_address, state->config.demoda_address, &off) < 0) { - printk("Error in pll_set\n"); + printk(KERN_ERR "Error in pll_set\n"); return -1; } @@ -2988,14 +2989,12 @@ struct dvb_frontend *drxd_attach(const struct drxd_config *config, return &state->frontend; error: - printk("drxd: not found\n"); + printk(KERN_ERR "drxd: not found\n"); kfree(state); return NULL; } +EXPORT_SYMBOL(drxd_attach); MODULE_DESCRIPTION("DRXD driver"); MODULE_AUTHOR("Micronas"); MODULE_LICENSE("GPL"); - -EXPORT_SYMBOL(drxd_attach); -EXPORT_SYMBOL(drxd_config_i2c); -- cgit v1.2.3 From b15ca3341442e573ef49207200ad42f6abd4f5b4 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab <mchehab@redhat.com> Date: Fri, 25 Mar 2011 12:38:56 -0300 Subject: [media] Remove the now obsolete drx397xD This was replaced by Micronas drxd driver Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/Kconfig | 13 - drivers/media/dvb/frontends/Makefile | 1 - drivers/media/dvb/frontends/drx397xD.c | 1511 ----------------------------- drivers/media/dvb/frontends/drx397xD.h | 130 --- drivers/media/dvb/frontends/drx397xD_fw.h | 40 - 5 files changed, 1695 deletions(-) delete mode 100644 drivers/media/dvb/frontends/drx397xD.c delete mode 100644 drivers/media/dvb/frontends/drx397xD.h delete mode 100644 drivers/media/dvb/frontends/drx397xD_fw.h (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig index 29ddeea2fffe..7ceb02d95ecf 100644 --- a/drivers/media/dvb/frontends/Kconfig +++ b/drivers/media/dvb/frontends/Kconfig @@ -263,19 +263,6 @@ config DVB_S5H1432 help A DVB-T tuner module. Say Y when you want to support this frontend. -config DVB_DRX397XD - tristate "Micronas DRX3975D/DRX3977D based" - depends on DVB_CORE && I2C - default m if DVB_FE_CUSTOMISE - help - A DVB-T tuner module. Say Y when you want to support this frontend. - - TODO: - This driver needs external firmware. Please use the command - "<kerneldir>/Documentation/dvb/get_dvb_firmware drx397xD" to - download/extract them, and then copy them to /usr/lib/hotplug/firmware - or /lib/firmware (depending on configuration of firmware hotplug). - config DVB_DRXD tristate "Micronas DRXD driver" depends on DVB_CORE && I2C diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile index fc08b6902a22..6d5192935889 100644 --- a/drivers/media/dvb/frontends/Makefile +++ b/drivers/media/dvb/frontends/Makefile @@ -37,7 +37,6 @@ obj-$(CONFIG_DVB_ZL10036) += zl10036.o obj-$(CONFIG_DVB_ZL10039) += zl10039.o obj-$(CONFIG_DVB_ZL10353) += zl10353.o obj-$(CONFIG_DVB_CX22702) += cx22702.o -obj-$(CONFIG_DVB_DRX397XD) += drx397xD.o obj-$(CONFIG_DVB_DRXD) += drxd.o obj-$(CONFIG_DVB_TDA10021) += tda10021.o obj-$(CONFIG_DVB_TDA10023) += tda10023.o diff --git a/drivers/media/dvb/frontends/drx397xD.c b/drivers/media/dvb/frontends/drx397xD.c deleted file mode 100644 index 536f02b17338..000000000000 --- a/drivers/media/dvb/frontends/drx397xD.c +++ /dev/null @@ -1,1511 +0,0 @@ -/* - * Driver for Micronas drx397xD demodulator - * - * Copyright (C) 2007 Henk Vergonet <Henk.Vergonet@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; If not, see <http://www.gnu.org/licenses/>. - */ - -#define DEBUG /* uncomment if you want debugging output */ -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/moduleparam.h> -#include <linux/init.h> -#include <linux/device.h> -#include <linux/delay.h> -#include <linux/string.h> -#include <linux/firmware.h> -#include <linux/slab.h> -#include <asm/div64.h> - -#include "dvb_frontend.h" -#include "drx397xD.h" - -static const char mod_name[] = "drx397xD"; - -#define MAX_CLOCK_DRIFT 200 /* maximal 200 PPM allowed */ - -#define F_SET_0D0h 1 -#define F_SET_0D4h 2 - -enum fw_ix { -#define _FW_ENTRY(a, b, c) b -#include "drx397xD_fw.h" -}; - -/* chip specifics */ -struct drx397xD_state { - struct i2c_adapter *i2c; - struct dvb_frontend frontend; - struct drx397xD_config config; - enum fw_ix chip_rev; - int flags; - u32 bandwidth_parm; /* internal bandwidth conversions */ - u32 f_osc; /* w90: actual osc frequency [Hz] */ -}; - -/* Firmware */ -static const char *blob_name[] = { -#define _BLOB_ENTRY(a, b) a -#include "drx397xD_fw.h" -}; - -enum blob_ix { -#define _BLOB_ENTRY(a, b) b -#include "drx397xD_fw.h" -}; - -static struct { - const char *name; - const struct firmware *file; - rwlock_t lock; - int refcnt; - const u8 *data[ARRAY_SIZE(blob_name)]; -} fw[] = { -#define _FW_ENTRY(a, b, c) { \ - .name = a, \ - .file = NULL, \ - .lock = __RW_LOCK_UNLOCKED(fw[c].lock), \ - .refcnt = 0, \ - .data = { } } -#include "drx397xD_fw.h" -}; - -/* use only with writer lock acquired */ -static void _drx_release_fw(struct drx397xD_state *s, enum fw_ix ix) -{ - memset(&fw[ix].data[0], 0, sizeof(fw[0].data)); - if (fw[ix].file) - release_firmware(fw[ix].file); -} - -static void drx_release_fw(struct drx397xD_state *s) -{ - enum fw_ix ix = s->chip_rev; - - pr_debug("%s\n", __func__); - - write_lock(&fw[ix].lock); - if (fw[ix].refcnt) { - fw[ix].refcnt--; - if (fw[ix].refcnt == 0) - _drx_release_fw(s, ix); - } - write_unlock(&fw[ix].lock); -} - -static int drx_load_fw(struct drx397xD_state *s, enum fw_ix ix) -{ - const u8 *data; - size_t size, len; - int i = 0, j, rc = -EINVAL; - - pr_debug("%s\n", __func__); - - if (ix < 0 || ix >= ARRAY_SIZE(fw)) - return -EINVAL; - s->chip_rev = ix; - - write_lock(&fw[ix].lock); - if (fw[ix].file) { - rc = 0; - goto exit_ok; - } - memset(&fw[ix].data[0], 0, sizeof(fw[0].data)); - - rc = request_firmware(&fw[ix].file, fw[ix].name, s->i2c->dev.parent); - if (rc != 0) { - printk(KERN_ERR "%s: Firmware \"%s\" not available\n", - mod_name, fw[ix].name); - goto exit_err; - } - - if (!fw[ix].file->data || fw[ix].file->size < 10) - goto exit_corrupt; - - data = fw[ix].file->data; - size = fw[ix].file->size; - - if (data[i++] != 2) /* check firmware version */ - goto exit_corrupt; - - do { - switch (data[i++]) { - case 0x00: /* bytecode */ - if (i >= size) - break; - i += data[i]; - case 0x01: /* reset */ - case 0x02: /* sleep */ - i++; - break; - case 0xfe: /* name */ - len = strnlen(&data[i], size - i); - if (i + len + 1 >= size) - goto exit_corrupt; - if (data[i + len + 1] != 0) - goto exit_corrupt; - for (j = 0; j < ARRAY_SIZE(blob_name); j++) { - if (strcmp(blob_name[j], &data[i]) == 0) { - fw[ix].data[j] = &data[i + len + 1]; - pr_debug("Loading %s\n", blob_name[j]); - } - } - i += len + 1; - break; - case 0xff: /* file terminator */ - if (i == size) { - rc = 0; - goto exit_ok; - } - default: - goto exit_corrupt; - } - } while (i < size); - -exit_corrupt: - printk(KERN_ERR "%s: Firmware is corrupt\n", mod_name); -exit_err: - _drx_release_fw(s, ix); - fw[ix].refcnt--; -exit_ok: - fw[ix].refcnt++; - write_unlock(&fw[ix].lock); - - return rc; -} - -/* i2c bus IO */ -static int write_fw(struct drx397xD_state *s, enum blob_ix ix) -{ - const u8 *data; - int len, rc = 0, i = 0; - struct i2c_msg msg = { - .addr = s->config.demod_address, - .flags = 0 - }; - - if (ix < 0 || ix >= ARRAY_SIZE(blob_name)) { - pr_debug("%s drx_fw_ix_t out of range\n", __func__); - return -EINVAL; - } - pr_debug("%s %s\n", __func__, blob_name[ix]); - - read_lock(&fw[s->chip_rev].lock); - data = fw[s->chip_rev].data[ix]; - if (!data) { - rc = -EINVAL; - goto exit_rc; - } - - for (;;) { - switch (data[i++]) { - case 0: /* bytecode */ - len = data[i++]; - msg.len = len; - msg.buf = (__u8 *) &data[i]; - if (i2c_transfer(s->i2c, &msg, 1) != 1) { - rc = -EIO; - goto exit_rc; - } - i += len; - break; - case 1: /* reset */ - case 2: /* sleep */ - i++; - break; - default: - goto exit_rc; - } - } -exit_rc: - read_unlock(&fw[s->chip_rev].lock); - - return rc; -} - -/* Function is not endian safe, use the RD16 wrapper below */ -static int _read16(struct drx397xD_state *s, __le32 i2c_adr) -{ - int rc; - u8 a[4]; - __le16 v; - struct i2c_msg msg[2] = { - { - .addr = s->config.demod_address, - .flags = 0, - .buf = a, - .len = sizeof(a) - }, { - .addr = s->config.demod_address, - .flags = I2C_M_RD, - .buf = (u8 *)&v, - .len = sizeof(v) - } - }; - - *(__le32 *) a = i2c_adr; - - rc = i2c_transfer(s->i2c, msg, 2); - if (rc != 2) - return -EIO; - - return le16_to_cpu(v); -} - -/* Function is not endian safe, use the WR16.. wrappers below */ -static int _write16(struct drx397xD_state *s, __le32 i2c_adr, __le16 val) -{ - u8 a[6]; - int rc; - struct i2c_msg msg = { - .addr = s->config.demod_address, - .flags = 0, - .buf = a, - .len = sizeof(a) - }; - - *(__le32 *)a = i2c_adr; - *(__le16 *)&a[4] = val; - - rc = i2c_transfer(s->i2c, &msg, 1); - if (rc != 1) - return -EIO; - - return 0; -} - -#define WR16(ss, adr, val) \ - _write16(ss, I2C_ADR_C0(adr), cpu_to_le16(val)) -#define WR16_E0(ss, adr, val) \ - _write16(ss, I2C_ADR_E0(adr), cpu_to_le16(val)) -#define RD16(ss, adr) \ - _read16(ss, I2C_ADR_C0(adr)) - -#define EXIT_RC(cmd) \ - if ((rc = (cmd)) < 0) \ - goto exit_rc - -/* Tuner callback */ -static int PLL_Set(struct drx397xD_state *s, - struct dvb_frontend_parameters *fep, int *df_tuner) -{ - struct dvb_frontend *fe = &s->frontend; - u32 f_tuner, f = fep->frequency; - int rc; - - pr_debug("%s\n", __func__); - - if ((f > s->frontend.ops.tuner_ops.info.frequency_max) || - (f < s->frontend.ops.tuner_ops.info.frequency_min)) - return -EINVAL; - - *df_tuner = 0; - if (!s->frontend.ops.tuner_ops.set_params || - !s->frontend.ops.tuner_ops.get_frequency) - return -ENOSYS; - - rc = s->frontend.ops.tuner_ops.set_params(fe, fep); - if (rc < 0) - return rc; - - rc = s->frontend.ops.tuner_ops.get_frequency(fe, &f_tuner); - if (rc < 0) - return rc; - - *df_tuner = f_tuner - f; - pr_debug("%s requested %d [Hz] tuner %d [Hz]\n", __func__, f, - f_tuner); - - return 0; -} - -/* Demodulator helper functions */ -static int SC_WaitForReady(struct drx397xD_state *s) -{ - int cnt = 1000; - int rc; - - pr_debug("%s\n", __func__); - - while (cnt--) { - rc = RD16(s, 0x820043); - if (rc == 0) - return 0; - } - - return -1; -} - -static int SC_SendCommand(struct drx397xD_state *s, int cmd) -{ - int rc; - - pr_debug("%s\n", __func__); - - WR16(s, 0x820043, cmd); - SC_WaitForReady(s); - rc = RD16(s, 0x820042); - if ((rc & 0xffff) == 0xffff) - return -1; - - return 0; -} - -static int HI_Command(struct drx397xD_state *s, u16 cmd) -{ - int rc, cnt = 1000; - - pr_debug("%s\n", __func__); - - rc = WR16(s, 0x420032, cmd); - if (rc < 0) - return rc; - - do { - rc = RD16(s, 0x420032); - if (rc == 0) { - rc = RD16(s, 0x420031); - return rc; - } - if (rc < 0) - return rc; - } while (--cnt); - - return rc; -} - -static int HI_CfgCommand(struct drx397xD_state *s) -{ - - pr_debug("%s\n", __func__); - - WR16(s, 0x420033, 0x3973); - WR16(s, 0x420034, s->config.w50); /* code 4, log 4 */ - WR16(s, 0x420035, s->config.w52); /* code 15, log 9 */ - WR16(s, 0x420036, s->config.demod_address << 1); - WR16(s, 0x420037, s->config.w56); /* code (set_i2c ?? initX 1 ), log 1 */ - /* WR16(s, 0x420033, 0x3973); */ - if ((s->config.w56 & 8) == 0) - return HI_Command(s, 3); - - return WR16(s, 0x420032, 0x3); -} - -static const u8 fastIncrDecLUT_15273[] = { - 0x0e, 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x12, 0x13, 0x14, - 0x15, 0x16, 0x17, 0x18, 0x1a, 0x1b, 0x1c, 0x1d, 0x1f -}; - -static const u8 slowIncrDecLUT_15272[] = { - 3, 4, 4, 5, 6 -}; - -static int SetCfgIfAgc(struct drx397xD_state *s, struct drx397xD_CfgIfAgc *agc) -{ - u16 w06 = agc->w06; - u16 w08 = agc->w08; - u16 w0A = agc->w0A; - u16 w0C = agc->w0C; - int quot, rem, i, rc = -EINVAL; - - pr_debug("%s\n", __func__); - - if (agc->w04 > 0x3ff) - goto exit_rc; - - if (agc->d00 == 1) { - EXIT_RC(RD16(s, 0x0c20010)); - rc &= ~0x10; - EXIT_RC(WR16(s, 0x0c20010, rc)); - return WR16(s, 0x0c20030, agc->w04 & 0x7ff); - } - - if (agc->d00 != 0) - goto exit_rc; - if (w0A < w08) - goto exit_rc; - if (w0A > 0x3ff) - goto exit_rc; - if (w0C > 0x3ff) - goto exit_rc; - if (w06 > 0x3ff) - goto exit_rc; - - EXIT_RC(RD16(s, 0x0c20010)); - rc |= 0x10; - EXIT_RC(WR16(s, 0x0c20010, rc)); - - EXIT_RC(WR16(s, 0x0c20025, (w06 >> 1) & 0x1ff)); - EXIT_RC(WR16(s, 0x0c20031, (w0A - w08) >> 1)); - EXIT_RC(WR16(s, 0x0c20032, ((w0A + w08) >> 1) - 0x1ff)); - - quot = w0C / 113; - rem = w0C % 113; - if (quot <= 8) { - quot = 8 - quot; - } else { - quot = 0; - rem += 113; - } - - EXIT_RC(WR16(s, 0x0c20024, quot)); - - i = fastIncrDecLUT_15273[rem / 8]; - EXIT_RC(WR16(s, 0x0c2002d, i)); - EXIT_RC(WR16(s, 0x0c2002e, i)); - - i = slowIncrDecLUT_15272[rem / 28]; - EXIT_RC(WR16(s, 0x0c2002b, i)); - rc = WR16(s, 0x0c2002c, i); -exit_rc: - return rc; -} - -static int SetCfgRfAgc(struct drx397xD_state *s, struct drx397xD_CfgRfAgc *agc) -{ - u16 w04 = agc->w04; - u16 w06 = agc->w06; - int rc = -1; - - pr_debug("%s %d 0x%x 0x%x\n", __func__, agc->d00, w04, w06); - - if (w04 > 0x3ff) - goto exit_rc; - - switch (agc->d00) { - case 1: - if (w04 == 0x3ff) - w04 = 0x400; - - EXIT_RC(WR16(s, 0x0c20036, w04)); - s->config.w9C &= ~2; - EXIT_RC(WR16(s, 0x0c20015, s->config.w9C)); - EXIT_RC(RD16(s, 0x0c20010)); - rc &= 0xbfdf; - EXIT_RC(WR16(s, 0x0c20010, rc)); - EXIT_RC(RD16(s, 0x0c20013)); - rc &= ~2; - break; - case 0: - /* loc_8000659 */ - s->config.w9C &= ~2; - EXIT_RC(WR16(s, 0x0c20015, s->config.w9C)); - EXIT_RC(RD16(s, 0x0c20010)); - rc &= 0xbfdf; - rc |= 0x4000; - EXIT_RC(WR16(s, 0x0c20010, rc)); - EXIT_RC(WR16(s, 0x0c20051, (w06 >> 4) & 0x3f)); - EXIT_RC(RD16(s, 0x0c20013)); - rc &= ~2; - break; - default: - s->config.w9C |= 2; - EXIT_RC(WR16(s, 0x0c20015, s->config.w9C)); - EXIT_RC(RD16(s, 0x0c20010)); - rc &= 0xbfdf; - EXIT_RC(WR16(s, 0x0c20010, rc)); - - EXIT_RC(WR16(s, 0x0c20036, 0)); - - EXIT_RC(RD16(s, 0x0c20013)); - rc |= 2; - } - rc = WR16(s, 0x0c20013, rc); - -exit_rc: - return rc; -} - -static int GetLockStatus(struct drx397xD_state *s, int *lockstat) -{ - int rc; - - *lockstat = 0; - - rc = RD16(s, 0x082004b); - if (rc < 0) - return rc; - - if (s->config.d60 != 2) - return 0; - - if ((rc & 7) == 7) - *lockstat |= 1; - if ((rc & 3) == 3) - *lockstat |= 2; - if (rc & 1) - *lockstat |= 4; - return 0; -} - -static int CorrectSysClockDeviation(struct drx397xD_state *s) -{ - int rc = -EINVAL; - int lockstat; - u32 clk, clk_limit; - - pr_debug("%s\n", __func__); - - if (s->config.d5C == 0) { - EXIT_RC(WR16(s, 0x08200e8, 0x010)); - EXIT_RC(WR16(s, 0x08200e9, 0x113)); - s->config.d5C = 1; - return rc; - } - if (s->config.d5C != 1) - goto exit_rc; - - rc = RD16(s, 0x0820048); - - rc = GetLockStatus(s, &lockstat); - if (rc < 0) - goto exit_rc; - if ((lockstat & 1) == 0) - goto exit_rc; - - EXIT_RC(WR16(s, 0x0420033, 0x200)); - EXIT_RC(WR16(s, 0x0420034, 0xc5)); - EXIT_RC(WR16(s, 0x0420035, 0x10)); - EXIT_RC(WR16(s, 0x0420036, 0x1)); - EXIT_RC(WR16(s, 0x0420037, 0xa)); - EXIT_RC(HI_Command(s, 6)); - EXIT_RC(RD16(s, 0x0420040)); - clk = rc; - EXIT_RC(RD16(s, 0x0420041)); - clk |= rc << 16; - - if (clk <= 0x26ffff) - goto exit_rc; - if (clk > 0x610000) - goto exit_rc; - - if (!s->bandwidth_parm) - return -EINVAL; - - /* round & convert to Hz */ - clk = ((u64) (clk + 0x800000) * s->bandwidth_parm + (1 << 20)) >> 21; - clk_limit = s->config.f_osc * MAX_CLOCK_DRIFT / 1000; - - if (clk - s->config.f_osc * 1000 + clk_limit <= 2 * clk_limit) { - s->f_osc = clk; - pr_debug("%s: osc %d %d [Hz]\n", __func__, - s->config.f_osc * 1000, clk - s->config.f_osc * 1000); - } - rc = WR16(s, 0x08200e8, 0); - -exit_rc: - return rc; -} - -static int ConfigureMPEGOutput(struct drx397xD_state *s, int type) -{ - int rc, si, bp; - - pr_debug("%s\n", __func__); - - si = s->config.wA0; - if (s->config.w98 == 0) { - si |= 1; - bp = 0; - } else { - si &= ~1; - bp = 0x200; - } - if (s->config.w9A == 0) - si |= 0x80; - else - si &= ~0x80; - - EXIT_RC(WR16(s, 0x2150045, 0)); - EXIT_RC(WR16(s, 0x2150010, si)); - EXIT_RC(WR16(s, 0x2150011, bp)); - rc = WR16(s, 0x2150012, (type == 0 ? 0xfff : 0)); - -exit_rc: - return rc; -} - -static int drx_tune(struct drx397xD_state *s, - struct dvb_frontend_parameters *fep) -{ - u16 v22 = 0; - u16 v1C = 0; - u16 v1A = 0; - u16 v18 = 0; - u32 edi = 0, ebx = 0, ebp = 0, edx = 0; - u16 v20 = 0, v1E = 0, v16 = 0, v14 = 0, v12 = 0, v10 = 0, v0E = 0; - - int rc, df_tuner = 0; - int a, b, c, d; - pr_debug("%s %d\n", __func__, s->config.d60); - - if (s->config.d60 != 2) - goto set_tuner; - rc = CorrectSysClockDeviation(s); - if (rc < 0) - goto set_tuner; - - s->config.d60 = 1; - rc = ConfigureMPEGOutput(s, 0); - if (rc < 0) - goto set_tuner; -set_tuner: - - rc = PLL_Set(s, fep, &df_tuner); - if (rc < 0) { - printk(KERN_ERR "Error in pll_set\n"); - goto exit_rc; - } - msleep(200); - - a = rc = RD16(s, 0x2150016); - if (rc < 0) - goto exit_rc; - b = rc = RD16(s, 0x2150010); - if (rc < 0) - goto exit_rc; - c = rc = RD16(s, 0x2150034); - if (rc < 0) - goto exit_rc; - d = rc = RD16(s, 0x2150035); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x2150014, c); - rc = WR16(s, 0x2150015, d); - rc = WR16(s, 0x2150010, 0); - rc = WR16(s, 0x2150000, 2); - rc = WR16(s, 0x2150036, 0x0fff); - rc = WR16(s, 0x2150016, a); - - rc = WR16(s, 0x2150010, 2); - rc = WR16(s, 0x2150007, 0); - rc = WR16(s, 0x2150000, 1); - rc = WR16(s, 0x2110000, 0); - rc = WR16(s, 0x0800000, 0); - rc = WR16(s, 0x2800000, 0); - rc = WR16(s, 0x2110010, 0x664); - - rc = write_fw(s, DRXD_ResetECRAM); - rc = WR16(s, 0x2110000, 1); - - rc = write_fw(s, DRXD_InitSC); - if (rc < 0) - goto exit_rc; - - rc = SetCfgIfAgc(s, &s->config.ifagc); - if (rc < 0) - goto exit_rc; - - rc = SetCfgRfAgc(s, &s->config.rfagc); - if (rc < 0) - goto exit_rc; - - if (fep->u.ofdm.transmission_mode != TRANSMISSION_MODE_2K) - v22 = 1; - switch (fep->u.ofdm.transmission_mode) { - case TRANSMISSION_MODE_8K: - edi = 1; - if (s->chip_rev == DRXD_FW_B1) - break; - - rc = WR16(s, 0x2010010, 0); - if (rc < 0) - break; - v1C = 0x63; - v1A = 0x53; - v18 = 0x43; - break; - default: - edi = 0; - if (s->chip_rev == DRXD_FW_B1) - break; - - rc = WR16(s, 0x2010010, 1); - if (rc < 0) - break; - - v1C = 0x61; - v1A = 0x47; - v18 = 0x41; - } - - switch (fep->u.ofdm.guard_interval) { - case GUARD_INTERVAL_1_4: - edi |= 0x0c; - break; - case GUARD_INTERVAL_1_8: - edi |= 0x08; - break; - case GUARD_INTERVAL_1_16: - edi |= 0x04; - break; - case GUARD_INTERVAL_1_32: - break; - default: - v22 |= 2; - } - - ebx = 0; - ebp = 0; - v20 = 0; - v1E = 0; - v16 = 0; - v14 = 0; - v12 = 0; - v10 = 0; - v0E = 0; - - switch (fep->u.ofdm.hierarchy_information) { - case HIERARCHY_1: - edi |= 0x40; - if (s->chip_rev == DRXD_FW_B1) - break; - rc = WR16(s, 0x1c10047, 1); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x2010012, 1); - if (rc < 0) - goto exit_rc; - ebx = 0x19f; - ebp = 0x1fb; - v20 = 0x0c0; - v1E = 0x195; - v16 = 0x1d6; - v14 = 0x1ef; - v12 = 4; - v10 = 5; - v0E = 5; - break; - case HIERARCHY_2: - edi |= 0x80; - if (s->chip_rev == DRXD_FW_B1) - break; - rc = WR16(s, 0x1c10047, 2); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x2010012, 2); - if (rc < 0) - goto exit_rc; - ebx = 0x08f; - ebp = 0x12f; - v20 = 0x0c0; - v1E = 0x11e; - v16 = 0x1d6; - v14 = 0x15e; - v12 = 4; - v10 = 5; - v0E = 5; - break; - case HIERARCHY_4: - edi |= 0xc0; - if (s->chip_rev == DRXD_FW_B1) - break; - rc = WR16(s, 0x1c10047, 3); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x2010012, 3); - if (rc < 0) - goto exit_rc; - ebx = 0x14d; - ebp = 0x197; - v20 = 0x0c0; - v1E = 0x1ce; - v16 = 0x1d6; - v14 = 0x11a; - v12 = 4; - v10 = 6; - v0E = 5; - break; - default: - v22 |= 8; - if (s->chip_rev == DRXD_FW_B1) - break; - rc = WR16(s, 0x1c10047, 0); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x2010012, 0); - if (rc < 0) - goto exit_rc; - /* QPSK QAM16 QAM64 */ - ebx = 0x19f; /* 62 */ - ebp = 0x1fb; /* 15 */ - v20 = 0x16a; /* 62 */ - v1E = 0x195; /* 62 */ - v16 = 0x1bb; /* 15 */ - v14 = 0x1ef; /* 15 */ - v12 = 5; /* 16 */ - v10 = 5; /* 16 */ - v0E = 5; /* 16 */ - } - - switch (fep->u.ofdm.constellation) { - default: - v22 |= 4; - case QPSK: - if (s->chip_rev == DRXD_FW_B1) - break; - - rc = WR16(s, 0x1c10046, 0); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x2010011, 0); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x201001a, 0x10); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x201001b, 0); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x201001c, 0); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c10062, v20); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c1002a, v1C); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c10015, v16); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c10016, v12); - if (rc < 0) - goto exit_rc; - break; - case QAM_16: - edi |= 0x10; - if (s->chip_rev == DRXD_FW_B1) - break; - - rc = WR16(s, 0x1c10046, 1); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x2010011, 1); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x201001a, 0x10); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x201001b, 4); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x201001c, 0); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c10062, v1E); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c1002a, v1A); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c10015, v14); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c10016, v10); - if (rc < 0) - goto exit_rc; - break; - case QAM_64: - edi |= 0x20; - rc = WR16(s, 0x1c10046, 2); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x2010011, 2); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x201001a, 0x20); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x201001b, 8); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x201001c, 2); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c10062, ebx); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c1002a, v18); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c10015, ebp); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x1c10016, v0E); - if (rc < 0) - goto exit_rc; - break; - } - - if (s->config.s20d24 == 1) { - rc = WR16(s, 0x2010013, 0); - } else { - rc = WR16(s, 0x2010013, 1); - edi |= 0x1000; - } - - switch (fep->u.ofdm.code_rate_HP) { - default: - v22 |= 0x10; - case FEC_1_2: - if (s->chip_rev == DRXD_FW_B1) - break; - rc = WR16(s, 0x2090011, 0); - break; - case FEC_2_3: - edi |= 0x200; - if (s->chip_rev == DRXD_FW_B1) - break; - rc = WR16(s, 0x2090011, 1); - break; - case FEC_3_4: - edi |= 0x400; - if (s->chip_rev == DRXD_FW_B1) - break; - rc = WR16(s, 0x2090011, 2); - break; - case FEC_5_6: /* 5 */ - edi |= 0x600; - if (s->chip_rev == DRXD_FW_B1) - break; - rc = WR16(s, 0x2090011, 3); - break; - case FEC_7_8: /* 7 */ - edi |= 0x800; - if (s->chip_rev == DRXD_FW_B1) - break; - rc = WR16(s, 0x2090011, 4); - break; - }; - if (rc < 0) - goto exit_rc; - - switch (fep->u.ofdm.bandwidth) { - default: - rc = -EINVAL; - goto exit_rc; - case BANDWIDTH_8_MHZ: /* 0 */ - case BANDWIDTH_AUTO: - rc = WR16(s, 0x0c2003f, 0x32); - s->bandwidth_parm = ebx = 0x8b8249; - edx = 0; - break; - case BANDWIDTH_7_MHZ: - rc = WR16(s, 0x0c2003f, 0x3b); - s->bandwidth_parm = ebx = 0x7a1200; - edx = 0x4807; - break; - case BANDWIDTH_6_MHZ: - rc = WR16(s, 0x0c2003f, 0x47); - s->bandwidth_parm = ebx = 0x68a1b6; - edx = 0x0f07; - break; - }; - - if (rc < 0) - goto exit_rc; - - rc = WR16(s, 0x08200ec, edx); - if (rc < 0) - goto exit_rc; - - rc = RD16(s, 0x0820050); - if (rc < 0) - goto exit_rc; - rc = WR16(s, 0x0820050, rc); - - { - /* Configure bandwidth specific factor */ - ebx = div64_u64(((u64) (s->f_osc) << 21) + (ebx >> 1), - (u64)ebx) - 0x800000; - EXIT_RC(WR16(s, 0x0c50010, ebx & 0xffff)); - EXIT_RC(WR16(s, 0x0c50011, ebx >> 16)); - - /* drx397xD oscillator calibration */ - ebx = div64_u64(((u64) (s->config.f_if + df_tuner) << 28) + - (s->f_osc >> 1), (u64)s->f_osc); - } - ebx &= 0xfffffff; - if (fep->inversion == INVERSION_ON) - ebx = 0x10000000 - ebx; - - EXIT_RC(WR16(s, 0x0c30010, ebx & 0xffff)); - EXIT_RC(WR16(s, 0x0c30011, ebx >> 16)); - - EXIT_RC(WR16(s, 0x0800000, 1)); - EXIT_RC(RD16(s, 0x0800000)); - - - EXIT_RC(SC_WaitForReady(s)); - EXIT_RC(WR16(s, 0x0820042, 0)); - EXIT_RC(WR16(s, 0x0820041, v22)); - EXIT_RC(WR16(s, 0x0820040, edi)); - EXIT_RC(SC_SendCommand(s, 3)); - - rc = RD16(s, 0x0800000); - - SC_WaitForReady(s); - WR16(s, 0x0820042, 0); - WR16(s, 0x0820041, 1); - WR16(s, 0x0820040, 1); - SC_SendCommand(s, 1); - - - rc = WR16(s, 0x2150000, 2); - rc = WR16(s, 0x2150016, a); - rc = WR16(s, 0x2150010, 4); - rc = WR16(s, 0x2150036, 0); - rc = WR16(s, 0x2150000, 1); - s->config.d60 = 2; - -exit_rc: - return rc; -} - -/******************************************************************************* - * DVB interface - ******************************************************************************/ - -static int drx397x_init(struct dvb_frontend *fe) -{ - struct drx397xD_state *s = fe->demodulator_priv; - int rc; - - pr_debug("%s\n", __func__); - - s->config.rfagc.d00 = 2; /* 0x7c */ - s->config.rfagc.w04 = 0; - s->config.rfagc.w06 = 0x3ff; - - s->config.ifagc.d00 = 0; /* 0x68 */ - s->config.ifagc.w04 = 0; - s->config.ifagc.w06 = 140; - s->config.ifagc.w08 = 0; - s->config.ifagc.w0A = 0x3ff; - s->config.ifagc.w0C = 0x388; - - /* for signal strength calculations */ - s->config.ss76 = 820; - s->config.ss78 = 2200; - s->config.ss7A = 150; - - /* HI_CfgCommand */ - s->config.w50 = 4; - s->config.w52 = 9; - - s->config.f_if = 42800000; /* d14: intermediate frequency [Hz] */ - s->config.f_osc = 48000; /* s66 : oscillator frequency [kHz] */ - s->config.w92 = 12000; - - s->config.w9C = 0x000e; - s->config.w9E = 0x0000; - - /* ConfigureMPEGOutput params */ - s->config.wA0 = 4; - s->config.w98 = 1; - s->config.w9A = 1; - - /* get chip revision */ - rc = RD16(s, 0x2410019); - if (rc < 0) - return -ENODEV; - - if (rc == 0) { - printk(KERN_INFO "%s: chip revision A2\n", mod_name); - rc = drx_load_fw(s, DRXD_FW_A2); - } else { - - rc = (rc >> 12) - 3; - switch (rc) { - case 1: - s->flags |= F_SET_0D4h; - case 0: - case 4: - s->flags |= F_SET_0D0h; - break; - case 2: - case 5: - break; - case 3: - s->flags |= F_SET_0D4h; - break; - default: - return -ENODEV; - }; - printk(KERN_INFO "%s: chip revision B1.%d\n", mod_name, rc); - rc = drx_load_fw(s, DRXD_FW_B1); - } - if (rc < 0) - goto error; - - rc = WR16(s, 0x0420033, 0x3973); - if (rc < 0) - goto error; - - rc = HI_Command(s, 2); - - msleep(1); - - if (s->chip_rev == DRXD_FW_A2) { - rc = WR16(s, 0x043012d, 0x47F); - if (rc < 0) - goto error; - } - rc = WR16_E0(s, 0x0400000, 0); - if (rc < 0) - goto error; - - if (s->config.w92 > 20000 || s->config.w92 % 4000) { - printk(KERN_ERR "%s: invalid osc frequency\n", mod_name); - rc = -1; - goto error; - } - - rc = WR16(s, 0x2410010, 1); - if (rc < 0) - goto error; - rc = WR16(s, 0x2410011, 0x15); - if (rc < 0) - goto error; - rc = WR16(s, 0x2410012, s->config.w92 / 4000); - if (rc < 0) - goto error; -#ifdef ORIG_FW - rc = WR16(s, 0x2410015, 2); - if (rc < 0) - goto error; -#endif - rc = WR16(s, 0x2410017, 0x3973); - if (rc < 0) - goto error; - - s->f_osc = s->config.f_osc * 1000; /* initial estimator */ - - s->config.w56 = 1; - - rc = HI_CfgCommand(s); - if (rc < 0) - goto error; - - rc = write_fw(s, DRXD_InitAtomicRead); - if (rc < 0) - goto error; - - if (s->chip_rev == DRXD_FW_A2) { - rc = WR16(s, 0x2150013, 0); - if (rc < 0) - goto error; - } - - rc = WR16_E0(s, 0x0400002, 0); - if (rc < 0) - goto error; - rc = WR16(s, 0x0400002, 0); - if (rc < 0) - goto error; - - if (s->chip_rev == DRXD_FW_A2) { - rc = write_fw(s, DRXD_ResetCEFR); - if (rc < 0) - goto error; - } - rc = write_fw(s, DRXD_microcode); - if (rc < 0) - goto error; - - s->config.w9C = 0x0e; - if (s->flags & F_SET_0D0h) { - s->config.w9C = 0; - rc = RD16(s, 0x0c20010); - if (rc < 0) - goto write_DRXD_InitFE_1; - - rc &= ~0x1000; - rc = WR16(s, 0x0c20010, rc); - if (rc < 0) - goto write_DRXD_InitFE_1; - - rc = RD16(s, 0x0c20011); - if (rc < 0) - goto write_DRXD_InitFE_1; - - rc &= ~0x8; - rc = WR16(s, 0x0c20011, rc); - if (rc < 0) - goto write_DRXD_InitFE_1; - - rc = WR16(s, 0x0c20012, 1); - } - -write_DRXD_InitFE_1: - - rc = write_fw(s, DRXD_InitFE_1); - if (rc < 0) - goto error; - - rc = 1; - if (s->chip_rev == DRXD_FW_B1) { - if (s->flags & F_SET_0D0h) - rc = 0; - } else { - if (s->flags & F_SET_0D0h) - rc = 4; - } - - rc = WR16(s, 0x0C20012, rc); - if (rc < 0) - goto error; - - rc = WR16(s, 0x0C20013, s->config.w9E); - if (rc < 0) - goto error; - rc = WR16(s, 0x0C20015, s->config.w9C); - if (rc < 0) - goto error; - - rc = write_fw(s, DRXD_InitFE_2); - if (rc < 0) - goto error; - rc = write_fw(s, DRXD_InitFT); - if (rc < 0) - goto error; - rc = write_fw(s, DRXD_InitCP); - if (rc < 0) - goto error; - rc = write_fw(s, DRXD_InitCE); - if (rc < 0) - goto error; - rc = write_fw(s, DRXD_InitEQ); - if (rc < 0) - goto error; - rc = write_fw(s, DRXD_InitEC); - if (rc < 0) - goto error; - rc = write_fw(s, DRXD_InitSC); - if (rc < 0) - goto error; - - rc = SetCfgIfAgc(s, &s->config.ifagc); - if (rc < 0) - goto error; - - rc = SetCfgRfAgc(s, &s->config.rfagc); - if (rc < 0) - goto error; - - rc = ConfigureMPEGOutput(s, 1); - rc = WR16(s, 0x08201fe, 0x0017); - rc = WR16(s, 0x08201ff, 0x0101); - - s->config.d5C = 0; - s->config.d60 = 1; - s->config.d48 = 1; - -error: - return rc; -} - -static int drx397x_get_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *params) -{ - return 0; -} - -static int drx397x_set_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *params) -{ - struct drx397xD_state *s = fe->demodulator_priv; - - s->config.s20d24 = 1; - - return drx_tune(s, params); -} - -static int drx397x_get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings - *fe_tune_settings) -{ - fe_tune_settings->min_delay_ms = 10000; - fe_tune_settings->step_size = 0; - fe_tune_settings->max_drift = 0; - - return 0; -} - -static int drx397x_read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct drx397xD_state *s = fe->demodulator_priv; - int lockstat; - - GetLockStatus(s, &lockstat); - - *status = 0; - if (lockstat & 2) { - CorrectSysClockDeviation(s); - ConfigureMPEGOutput(s, 1); - *status = FE_HAS_LOCK | FE_HAS_SYNC | FE_HAS_VITERBI; - } - if (lockstat & 4) - *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; - - return 0; -} - -static int drx397x_read_ber(struct dvb_frontend *fe, unsigned int *ber) -{ - *ber = 0; - - return 0; -} - -static int drx397x_read_snr(struct dvb_frontend *fe, u16 *snr) -{ - *snr = 0; - - return 0; -} - -static int drx397x_read_signal_strength(struct dvb_frontend *fe, u16 *strength) -{ - struct drx397xD_state *s = fe->demodulator_priv; - int rc; - - if (s->config.ifagc.d00 == 2) { - *strength = 0xffff; - return 0; - } - rc = RD16(s, 0x0c20035); - if (rc < 0) { - *strength = 0; - return 0; - } - rc &= 0x3ff; - /* Signal strength is calculated using the following formula: - * - * a = 2200 * 150 / (2200 + 150); - * a = a * 3300 / (a + 820); - * b = 2200 * 3300 / (2200 + 820); - * c = (((b-a) * rc) >> 10 + a) << 4; - * strength = ~c & 0xffff; - * - * The following does the same but with less rounding errors: - */ - *strength = ~(7720 + (rc * 30744 >> 10)); - - return 0; -} - -static int drx397x_read_ucblocks(struct dvb_frontend *fe, - unsigned int *ucblocks) -{ - *ucblocks = 0; - - return 0; -} - -static int drx397x_sleep(struct dvb_frontend *fe) -{ - return 0; -} - -static void drx397x_release(struct dvb_frontend *fe) -{ - struct drx397xD_state *s = fe->demodulator_priv; - printk(KERN_INFO "%s: release demodulator\n", mod_name); - if (s) { - drx_release_fw(s); - kfree(s); - } - -} - -static struct dvb_frontend_ops drx397x_ops = { - - .info = { - .name = "Micronas DRX397xD DVB-T Frontend", - .type = FE_OFDM, - .frequency_min = 47125000, - .frequency_max = 855250000, - .frequency_stepsize = 166667, - .frequency_tolerance = 0, - .caps = /* 0x0C01B2EAE */ - FE_CAN_FEC_1_2 | /* = 0x2, */ - FE_CAN_FEC_2_3 | /* = 0x4, */ - FE_CAN_FEC_3_4 | /* = 0x8, */ - FE_CAN_FEC_5_6 | /* = 0x20, */ - FE_CAN_FEC_7_8 | /* = 0x80, */ - FE_CAN_FEC_AUTO | /* = 0x200, */ - FE_CAN_QPSK | /* = 0x400, */ - FE_CAN_QAM_16 | /* = 0x800, */ - FE_CAN_QAM_64 | /* = 0x2000, */ - FE_CAN_QAM_AUTO | /* = 0x10000, */ - FE_CAN_TRANSMISSION_MODE_AUTO | /* = 0x20000, */ - FE_CAN_GUARD_INTERVAL_AUTO | /* = 0x80000, */ - FE_CAN_HIERARCHY_AUTO | /* = 0x100000, */ - FE_CAN_RECOVER | /* = 0x40000000, */ - FE_CAN_MUTE_TS /* = 0x80000000 */ - }, - - .release = drx397x_release, - .init = drx397x_init, - .sleep = drx397x_sleep, - - .set_frontend = drx397x_set_frontend, - .get_tune_settings = drx397x_get_tune_settings, - .get_frontend = drx397x_get_frontend, - - .read_status = drx397x_read_status, - .read_snr = drx397x_read_snr, - .read_signal_strength = drx397x_read_signal_strength, - .read_ber = drx397x_read_ber, - .read_ucblocks = drx397x_read_ucblocks, -}; - -struct dvb_frontend *drx397xD_attach(const struct drx397xD_config *config, - struct i2c_adapter *i2c) -{ - struct drx397xD_state *state; - - /* allocate memory for the internal state */ - state = kzalloc(sizeof(struct drx397xD_state), GFP_KERNEL); - if (!state) - goto error; - - /* setup the state */ - state->i2c = i2c; - memcpy(&state->config, config, sizeof(struct drx397xD_config)); - - /* check if the demod is there */ - if (RD16(state, 0x2410019) < 0) - goto error; - - /* create dvb_frontend */ - memcpy(&state->frontend.ops, &drx397x_ops, - sizeof(struct dvb_frontend_ops)); - state->frontend.demodulator_priv = state; - - return &state->frontend; -error: - kfree(state); - - return NULL; -} -EXPORT_SYMBOL(drx397xD_attach); - -MODULE_DESCRIPTION("Micronas DRX397xD DVB-T Frontend"); -MODULE_AUTHOR("Henk Vergonet"); -MODULE_LICENSE("GPL"); - diff --git a/drivers/media/dvb/frontends/drx397xD.h b/drivers/media/dvb/frontends/drx397xD.h deleted file mode 100644 index ba05d17290c6..000000000000 --- a/drivers/media/dvb/frontends/drx397xD.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Driver for Micronas DVB-T drx397xD demodulator - * - * Copyright (C) 2007 Henk vergonet <Henk.Vergonet@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.= - */ - -#ifndef _DRX397XD_H_INCLUDED -#define _DRX397XD_H_INCLUDED - -#include <linux/dvb/frontend.h> - -#define DRX_F_STEPSIZE 166667 -#define DRX_F_OFFSET 36000000 - -#define I2C_ADR_C0(x) \ -( cpu_to_le32( \ - (u32)( \ - (((u32)(x) & (u32)0x000000ffUL) ) | \ - (((u32)(x) & (u32)0x0000ff00UL) << 16) | \ - (((u32)(x) & (u32)0x0fff0000UL) >> 8) | \ - ( (u32)0x00c00000UL) \ - )) \ -) - -#define I2C_ADR_E0(x) \ -( cpu_to_le32( \ - (u32)( \ - (((u32)(x) & (u32)0x000000ffUL) ) | \ - (((u32)(x) & (u32)0x0000ff00UL) << 16) | \ - (((u32)(x) & (u32)0x0fff0000UL) >> 8) | \ - ( (u32)0x00e00000UL) \ - )) \ -) - -struct drx397xD_CfgRfAgc /* 0x7c */ -{ - int d00; /* 2 */ - u16 w04; - u16 w06; -}; - -struct drx397xD_CfgIfAgc /* 0x68 */ -{ - int d00; /* 0 */ - u16 w04; /* 0 */ - u16 w06; - u16 w08; - u16 w0A; - u16 w0C; -}; - -struct drx397xD_s20 { - int d04; - u32 d18; - u32 d1C; - u32 d20; - u32 d14; - u32 d24; - u32 d0C; - u32 d08; -}; - -struct drx397xD_config -{ - /* demodulator's I2C address */ - u8 demod_address; /* 0x0f */ - - struct drx397xD_CfgIfAgc ifagc; /* 0x68 */ - struct drx397xD_CfgRfAgc rfagc; /* 0x7c */ - u32 s20d24; - - /* HI_CfgCommand parameters */ - u16 w50, w52, /* w54, */ w56; - - int d5C; - int d60; - int d48; - int d28; - - u32 f_if; /* d14: intermediate frequency [Hz] */ - /* 36000000 on Cinergy 2400i DT */ - /* 42800000 on Pinnacle Hybrid PRO 330e */ - - u16 f_osc; /* s66: 48000 oscillator frequency [kHz] */ - - u16 w92; /* 20000 */ - - u16 wA0; - u16 w98; - u16 w9A; - - u16 w9C; /* 0xe0 */ - u16 w9E; /* 0x00 */ - - /* used for signal strength calculations in - drx397x_read_signal_strength - */ - u16 ss78; // 2200 - u16 ss7A; // 150 - u16 ss76; // 820 -}; - -#if defined(CONFIG_DVB_DRX397XD) || (defined(CONFIG_DVB_DRX397XD_MODULE) && defined(MODULE)) -extern struct dvb_frontend* drx397xD_attach(const struct drx397xD_config *config, - struct i2c_adapter *i2c); -#else -static inline struct dvb_frontend* drx397xD_attach(const struct drx397xD_config *config, - struct i2c_adapter *i2c) -{ - printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; -} -#endif /* CONFIG_DVB_DRX397XD */ - -#endif /* _DRX397XD_H_INCLUDED */ diff --git a/drivers/media/dvb/frontends/drx397xD_fw.h b/drivers/media/dvb/frontends/drx397xD_fw.h deleted file mode 100644 index c8b44c1e807f..000000000000 --- a/drivers/media/dvb/frontends/drx397xD_fw.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Firmware definitions for Micronas drx397xD - * - * Copyright (C) 2007 Henk Vergonet <Henk.Vergonet@gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; If not, see <http://www.gnu.org/licenses/>. - */ - -#ifdef _FW_ENTRY - _FW_ENTRY("drx397xD.A2.fw", DRXD_FW_A2 = 0, DRXD_FW_A2 ), - _FW_ENTRY("drx397xD.B1.fw", DRXD_FW_B1, DRXD_FW_B1 ), -#undef _FW_ENTRY -#endif /* _FW_ENTRY */ - -#ifdef _BLOB_ENTRY - _BLOB_ENTRY("InitAtomicRead", DRXD_InitAtomicRead = 0 ), - _BLOB_ENTRY("InitCE", DRXD_InitCE ), - _BLOB_ENTRY("InitCP", DRXD_InitCP ), - _BLOB_ENTRY("InitEC", DRXD_InitEC ), - _BLOB_ENTRY("InitEQ", DRXD_InitEQ ), - _BLOB_ENTRY("InitFE_1", DRXD_InitFE_1 ), - _BLOB_ENTRY("InitFE_2", DRXD_InitFE_2 ), - _BLOB_ENTRY("InitFT", DRXD_InitFT ), - _BLOB_ENTRY("InitSC", DRXD_InitSC ), - _BLOB_ENTRY("ResetCEFR", DRXD_ResetCEFR ), - _BLOB_ENTRY("ResetECRAM", DRXD_ResetECRAM ), - _BLOB_ENTRY("microcode", DRXD_microcode ), -#undef _BLOB_ENTRY -#endif /* _BLOB_ENTRY */ -- cgit v1.2.3 From 834751d4365822f769d8af2fd37dc674997a313c Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab <mchehab@redhat.com> Date: Fri, 25 Mar 2011 12:46:05 -0300 Subject: [media] drxd: use mutex instead of semaphore Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd_hard.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c index 117df556ec3e..30a78af424cb 100644 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -132,7 +132,7 @@ struct drxd_state { int i2c_access; int init_done; - struct semaphore mutex; + struct mutex mutex; u8 chip_adr; u16 hi_cfg_timing_div; @@ -998,7 +998,7 @@ static int HI_CfgCommand(struct drxd_state *state) { int status = 0; - down(&state->mutex); + mutex_lock(&state->mutex); Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0); Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); @@ -1013,7 +1013,7 @@ static int HI_CfgCommand(struct drxd_state *state) HI_RA_RAM_SRV_CMD_CONFIG, 0); else status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0); - up(&state->mutex); + mutex_unlock(&state->mutex); return status; } @@ -1029,12 +1029,12 @@ static int HI_ResetCommand(struct drxd_state *state) { int status; - down(&state->mutex); + mutex_lock(&state->mutex); status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0); if (status == 0) status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0); - up(&state->mutex); + mutex_unlock(&state->mutex); msleep(1); return status; } @@ -1066,7 +1066,7 @@ static int AtomicReadBlock(struct drxd_state *state, if ((!pData) || ((DataSize & 1) != 0)) return -1; - down(&state->mutex); + mutex_lock(&state->mutex); do { /* Instruct HI to read n bytes */ @@ -1105,7 +1105,7 @@ static int AtomicReadBlock(struct drxd_state *state, pData[(2 * i) + 1] = (u8) (word >> 8); } } - up(&state->mutex); + mutex_unlock(&state->mutex); return status; } @@ -1334,7 +1334,7 @@ static int SC_ProcStartCommand(struct drxd_state *state, int status = 0; u16 scExec; - down(&state->mutex); + mutex_lock(&state->mutex); do { Read16(state, SC_COMM_EXEC__A, &scExec, 0); if (scExec != 1) { @@ -1348,7 +1348,7 @@ static int SC_ProcStartCommand(struct drxd_state *state, SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START); } while (0); - up(&state->mutex); + mutex_unlock(&state->mutex); return status; } @@ -1357,7 +1357,7 @@ static int SC_SetPrefParamCommand(struct drxd_state *state, { int status; - down(&state->mutex); + mutex_lock(&state->mutex); do { status = SC_WaitForReady(state); if (status < 0) @@ -1376,7 +1376,7 @@ static int SC_SetPrefParamCommand(struct drxd_state *state, if (status < 0) break; } while (0); - up(&state->mutex); + mutex_unlock(&state->mutex); return status; } @@ -1385,7 +1385,7 @@ static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result) { int status = 0; - down(&state->mutex); + mutex_lock(&state->mutex); do { status = SC_WaitForReady(state); if (status < 0) @@ -1397,7 +1397,7 @@ static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result) if (status < 0) break; } while (0); - up(&state->mutex); + mutex_unlock(&state->mutex); return status; } #endif @@ -2977,7 +2977,7 @@ struct dvb_frontend *drxd_attach(const struct drxd_config *config, state->i2c = i2c; state->priv = priv; - sema_init(&state->mutex, 1); + mutex_init(&state->mutex); if (Read16(state, 0, 0, 0) < 0) goto error; -- cgit v1.2.3 From 7ea03d211c055cfdef7930a29a11a54d2682f953 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Sat, 9 Apr 2011 20:50:07 -0300 Subject: [media] anysee: I2C address fix Switch from 8 bit notation to real 7 bit. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/anysee.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index 6b402e943539..18184d30e481 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -162,7 +162,7 @@ static int anysee_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { u8 buf[6]; buf[0] = CMD_I2C_READ; - buf[1] = msg[i].addr + 1; + buf[1] = (msg[i].addr << 1) | 0x01; buf[2] = msg[i].buf[0]; buf[3] = 0x00; buf[4] = 0x00; @@ -173,7 +173,7 @@ static int anysee_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, } else { u8 buf[4+msg[i].len]; buf[0] = CMD_I2C_WRITE; - buf[1] = msg[i].addr; + buf[1] = (msg[i].addr << 1); buf[2] = msg[i].len; buf[3] = 0x01; memcpy(&buf[4], msg[i].buf, msg[i].len); @@ -224,7 +224,7 @@ static int anysee_mt352_demod_init(struct dvb_frontend *fe) /* Callbacks for DVB USB */ static struct tda10023_config anysee_tda10023_config = { - .demod_address = 0x1a, + .demod_address = (0x1a >> 1), .invert = 0, .xtal = 16000000, .pll_m = 11, @@ -235,12 +235,12 @@ static struct tda10023_config anysee_tda10023_config = { }; static struct mt352_config anysee_mt352_config = { - .demod_address = 0x1e, + .demod_address = (0x1e >> 1), .demod_init = anysee_mt352_demod_init, }; static struct zl10353_config anysee_zl10353_config = { - .demod_address = 0x1e, + .demod_address = (0x1e >> 1), .parallel_ts = 1, }; @@ -361,13 +361,13 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) /* Thomson dtt7579 (not sure) PLL inside of: Samsung DNOS404ZH102A NIM Samsung DNOS404ZH103A NIM */ - dvb_attach(dvb_pll_attach, adap->fe, 0x61, - NULL, DVB_PLL_THOMSON_DTT7579); + dvb_attach(dvb_pll_attach, adap->fe, (0xc2 >> 1), + NULL, DVB_PLL_THOMSON_DTT7579); break; case DVB_PLL_SAMSUNG_DTOS403IH102A: /* Unknown PLL inside of Samsung DTOS403IH102A tuner module */ - dvb_attach(dvb_pll_attach, adap->fe, 0xc0, - &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A); + dvb_attach(dvb_pll_attach, adap->fe, (0xc0 >> 1), + &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A); break; } -- cgit v1.2.3 From b3e6a5af2162d114df4fd67353bbadd3d8a22c3e Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Sat, 9 Apr 2011 21:00:51 -0300 Subject: [media] anysee: fix multibyte I2C read It can read more than one byte from I2C bus. Allow that. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/anysee.c | 2 +- drivers/media/dvb/dvb-usb/anysee.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index 18184d30e481..554186205eec 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -166,7 +166,7 @@ static int anysee_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, buf[2] = msg[i].buf[0]; buf[3] = 0x00; buf[4] = 0x00; - buf[5] = 0x01; + buf[5] = msg[i+1].len; ret = anysee_ctrl_msg(d, buf, sizeof(buf), msg[i+1].buf, msg[i+1].len); inc = 2; diff --git a/drivers/media/dvb/dvb-usb/anysee.h b/drivers/media/dvb/dvb-usb/anysee.h index 7ca01ff6e13c..686e06044fcb 100644 --- a/drivers/media/dvb/dvb-usb/anysee.h +++ b/drivers/media/dvb/dvb-usb/anysee.h @@ -136,7 +136,7 @@ General reply packet(s) are always used if not own reply defined. ---------------------------------------------------------------------------- | 04 | 0x00 ---------------------------------------------------------------------------- -| 05 | 0x01 +| 05 | data length ---------------------------------------------------------------------------- | 06-59 | don't care ---------------------------------------------------------------------------- -- cgit v1.2.3 From 592d9e21f5d875e84d09940eff7bc48812245855 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Sat, 9 Apr 2011 21:13:33 -0300 Subject: [media] anysee: change some messages Print firmware version as two digit long (change from 3 to 2). Windows app have changed that too. First byte was hard coded as 0. Change email list address to report non-working device to current one. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/anysee.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index 554186205eec..d50118ccc105 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -261,8 +261,8 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) return ret; /* Meaning of these info bytes are guessed. */ - info("firmware version:%d.%d.%d hardware id:%d", - 0, hw_info[1], hw_info[2], hw_info[0]); + info("firmware version:%d.%d hardware id:%d", + hw_info[1], hw_info[2], hw_info[0]); ret = anysee_read_reg(adap->dev, 0xb0, &io_d); /* IO port D */ if (ret) @@ -272,14 +272,14 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) /* Select demod using trial and error method. */ /* Try to attach demodulator in following order: - model demod hw firmware - 1. E30 MT352 02 0.2.1 - 2. E30 ZL10353 02 0.2.1 - 3. E30 Combo ZL10353 0f 0.1.2 DVB-T/C combo - 4. E30 Plus ZL10353 06 0.1.0 - 5. E30C Plus TDA10023 0a 0.1.0 rev 0.2 - E30C Plus TDA10023 0f 0.1.2 rev 0.4 - E30 Combo TDA10023 0f 0.1.2 DVB-T/C combo + model demod hw fw + 1. E30 MT352 02 2.1 + 2. E30 ZL10353 02 2.1 + 3. E30 Combo ZL10353 0f 1.2 DVB-T/C combo + 4. E30 Plus ZL10353 06 1.0 + 5. E30C Plus TDA10023 0a 1.0 rev 0.2 + E30C Plus TDA10023 0f 1.2 rev 0.4 + E30 Combo TDA10023 0f 1.2 DVB-T/C combo */ /* Zarlink MT352 DVB-T demod inside of Samsung DNOS404ZH102A NIM */ @@ -344,9 +344,9 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) if (ret) return ret; - err("Unknown Anysee version: %02x %02x %02x. "\ - "Please report the <linux-dvb@linuxtv.org>.", - hw_info[0], hw_info[1], hw_info[2]); + err("Unknown Anysee version: %02x %02x %02x. " \ + "Please report the <linux-media@vger.kernel.org>.", + hw_info[0], hw_info[1], hw_info[2]); return -ENODEV; } -- cgit v1.2.3 From 41f81f686a85af144ad9769a15ef8575b69eee38 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Sun, 10 Apr 2011 17:53:52 -0300 Subject: [media] anysee: reimplement demod and tuner attach Use board ID as base value when selecting correct hardware configuration. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/anysee.c | 302 ++++++++++++++++++++++++++----------- drivers/media/dvb/dvb-usb/anysee.h | 19 ++- 2 files changed, 233 insertions(+), 88 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index d50118ccc105..ff9226e1843d 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -105,6 +105,27 @@ static int anysee_write_reg(struct dvb_usb_device *d, u16 reg, u8 val) return anysee_ctrl_msg(d, buf, sizeof(buf), NULL, 0); } +/* write single register with mask */ +static int anysee_wr_reg_mask(struct dvb_usb_device *d, u16 reg, u8 val, + u8 mask) +{ + int ret; + u8 tmp; + + /* no need for read if whole reg is written */ + if (mask != 0xff) { + ret = anysee_read_reg(d, reg, &tmp); + if (ret) + return ret; + + val &= mask; + tmp &= ~mask; + val |= tmp; + } + + return anysee_write_reg(d, reg, val); +} + static int anysee_get_hw_info(struct dvb_usb_device *d, u8 *id) { u8 buf[] = {CMD_GET_HW_INFO}; @@ -244,134 +265,241 @@ static struct zl10353_config anysee_zl10353_config = { .parallel_ts = 1, }; +/* + * New USB device strings: Mfr=1, Product=2, SerialNumber=0 + * Manufacturer: AMT.CO.KR + * + * E30 VID=04b4 PID=861f HW=2 FW=2.1 Product=???????? + * PCB: ? + * parts: MT352, DTT7579(?), DNOS404ZH102A NIM + * + * E30 VID=04b4 PID=861f HW=2 FW=2.1 Product=???????? + * PCB: ? + * parts: ZL10353, DTT7579(?), DNOS404ZH103A NIM + * + * E30 Plus VID=04b4 PID=861f HW=6 FW=1.0 "anysee" + * PCB: 507CD (rev1.1) + * parts: ZL10353, DTT7579(?), CST56I01, DNOS404ZH103A NIM + * OEA=80 OEB=00 OEC=00 OED=ff OEF=fe + * IOD[0] ZL10353 1=enabled + * IOA[7] TS 0=enabled + * tuner is not behind ZL10353 I2C-gate (no care if gate disabled or not) + * + * E30 C Plus VID=04b4 PID=861f HW=10 FW=1.0 "anysee-DC(LP)" + * PCB: 507DC (rev0.2) + * parts: TDA10023, CST56I01, DTOS403IH102B TM + * OEA=80 OEB=00 OEC=00 OED=ff OEF=fe + * IOD[0] TDA10023 1=enabled + * + * E30 C Plus VID=1c73 PID=861f HW=15 FW=1.2 "anysee-FA(LP)" + * PCB: 507FA (rev0.4) + * parts: TDA10023, TDA8024, DTOS403IH102B TM + * OEA=80 OEB=00 OEC=ff OED=ff OEF=ff + * IOD[5] TDA10023 1=enabled + * IOE[0] tuner 1=enabled + * + * E30 Combo Plus VID=1c73 PID=861f HW=15 FW=1.2 "anysee-FA(LP)" + * PCB: 507FA (rev1.1) + * parts: ZL10353, TDA10023, TDA8024, DTOS403IH102B TM + * OEA=80 OEB=00 OEC=ff OED=ff OEF=ff + * DVB-C: + * IOD[5] TDA10023 1=enabled + * IOE[0] tuner 1=enabled + * DVB-T: + * IOD[0] ZL10353 1=enabled + * IOE[0] tuner 0=enabled + * tuner is behind ZL10353 I2C-gate + */ + static int anysee_frontend_attach(struct dvb_usb_adapter *adap) { int ret; struct anysee_state *state = adap->dev->priv; u8 hw_info[3]; - u8 io_d; /* IO port D */ - /* check which hardware we have - We must do this call two times to get reliable values (hw bug). */ + /* Check which hardware we have. + * We must do this call two times to get reliable values (hw bug). + */ ret = anysee_get_hw_info(adap->dev, hw_info); if (ret) - return ret; + goto error; + ret = anysee_get_hw_info(adap->dev, hw_info); if (ret) - return ret; + goto error; /* Meaning of these info bytes are guessed. */ info("firmware version:%d.%d hardware id:%d", hw_info[1], hw_info[2], hw_info[0]); - ret = anysee_read_reg(adap->dev, 0xb0, &io_d); /* IO port D */ - if (ret) - return ret; - deb_info("%s: IO port D:%02x\n", __func__, io_d); - - /* Select demod using trial and error method. */ - - /* Try to attach demodulator in following order: - model demod hw fw - 1. E30 MT352 02 2.1 - 2. E30 ZL10353 02 2.1 - 3. E30 Combo ZL10353 0f 1.2 DVB-T/C combo - 4. E30 Plus ZL10353 06 1.0 - 5. E30C Plus TDA10023 0a 1.0 rev 0.2 - E30C Plus TDA10023 0f 1.2 rev 0.4 - E30 Combo TDA10023 0f 1.2 DVB-T/C combo - */ - - /* Zarlink MT352 DVB-T demod inside of Samsung DNOS404ZH102A NIM */ - adap->fe = dvb_attach(mt352_attach, &anysee_mt352_config, - &adap->dev->i2c_adap); - if (adap->fe != NULL) { - state->tuner = DVB_PLL_THOMSON_DTT7579; - return 0; - } + state->hw = hw_info[0]; - /* Zarlink ZL10353 DVB-T demod inside of Samsung DNOS404ZH103A NIM */ - adap->fe = dvb_attach(zl10353_attach, &anysee_zl10353_config, - &adap->dev->i2c_adap); - if (adap->fe != NULL) { - state->tuner = DVB_PLL_THOMSON_DTT7579; - return 0; - } + switch (state->hw) { + case ANYSEE_HW_02: /* 2 */ + /* E30 */ - /* for E30 Combo Plus DVB-T demodulator */ - if (dvb_usb_anysee_delsys) { - ret = anysee_write_reg(adap->dev, 0xb0, 0x01); - if (ret) - return ret; + /* attach demod */ + adap->fe = dvb_attach(mt352_attach, &anysee_mt352_config, + &adap->dev->i2c_adap); + if (adap->fe) + break; - /* Zarlink ZL10353 DVB-T demod */ + /* attach demod */ adap->fe = dvb_attach(zl10353_attach, &anysee_zl10353_config, - &adap->dev->i2c_adap); - if (adap->fe != NULL) { - state->tuner = DVB_PLL_SAMSUNG_DTOS403IH102A; - return 0; - } - } + &adap->dev->i2c_adap); + if (adap->fe) + break; - /* connect demod on IO port D for TDA10023 & ZL10353 */ - ret = anysee_write_reg(adap->dev, 0xb0, 0x25); - if (ret) - return ret; + break; + case ANYSEE_HW_507CD: /* 6 */ + /* E30 Plus */ - /* Zarlink ZL10353 DVB-T demod inside of Samsung DNOS404ZH103A NIM */ - adap->fe = dvb_attach(zl10353_attach, &anysee_zl10353_config, - &adap->dev->i2c_adap); - if (adap->fe != NULL) { - state->tuner = DVB_PLL_THOMSON_DTT7579; - return 0; - } + /* enable DVB-T demod on IOD[0] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 0), 0x01); + if (ret) + goto error; - /* IO port E - E30C rev 0.4 board requires this */ - ret = anysee_write_reg(adap->dev, 0xb1, 0xa7); - if (ret) - return ret; + /* enable transport stream on IOA[7] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOA, (0 << 7), 0x80); + if (ret) + goto error; - /* Philips TDA10023 DVB-C demod */ - adap->fe = dvb_attach(tda10023_attach, &anysee_tda10023_config, - &adap->dev->i2c_adap, 0x48); - if (adap->fe != NULL) { - state->tuner = DVB_PLL_SAMSUNG_DTOS403IH102A; - return 0; - } + /* attach demod */ + adap->fe = dvb_attach(zl10353_attach, &anysee_zl10353_config, + &adap->dev->i2c_adap); + if (adap->fe) + break; - /* return IO port D to init value for safe */ - ret = anysee_write_reg(adap->dev, 0xb0, io_d); - if (ret) - return ret; + break; + case ANYSEE_HW_507DC: /* 10 */ + /* E30 C Plus */ + + /* enable DVB-C demod on IOD[0] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 0), 0x01); + if (ret) + goto error; + + /* attach demod */ + adap->fe = dvb_attach(tda10023_attach, &anysee_tda10023_config, + &adap->dev->i2c_adap, 0x48); + if (adap->fe) + break; - err("Unknown Anysee version: %02x %02x %02x. " \ - "Please report the <linux-media@vger.kernel.org>.", - hw_info[0], hw_info[1], hw_info[2]); + break; + case ANYSEE_HW_507FA: /* 15 */ + /* E30 Combo Plus */ + /* E30 C Plus */ + + if (dvb_usb_anysee_delsys) { + /* disable DVB-C demod on IOD[5] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (0 << 5), + 0x20); + if (ret) + goto error; + + /* enable DVB-T demod on IOD[0] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 0), + 0x01); + if (ret) + goto error; + + /* attach demod */ + adap->fe = dvb_attach(zl10353_attach, + &anysee_zl10353_config, &adap->dev->i2c_adap); + if (adap->fe) + break; + } else { + /* disable DVB-T demod on IOD[0] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (0 << 0), + 0x01); + if (ret) + goto error; + + /* enable DVB-C demod on IOD[5] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 5), + 0x20); + if (ret) + goto error; + + /* attach demod */ + adap->fe = dvb_attach(tda10023_attach, + &anysee_tda10023_config, &adap->dev->i2c_adap, + 0x48); + if (adap->fe) + break; + } + break; + } - return -ENODEV; + if (!adap->fe) { + /* we have no frontend :-( */ + ret = -ENODEV; + err("Unknown Anysee version: %02x %02x %02x. " \ + "Please report the <linux-media@vger.kernel.org>.", + hw_info[0], hw_info[1], hw_info[2]); + } +error: + return ret; } static int anysee_tuner_attach(struct dvb_usb_adapter *adap) { struct anysee_state *state = adap->dev->priv; + int ret = 0; deb_info("%s:\n", __func__); - switch (state->tuner) { - case DVB_PLL_THOMSON_DTT7579: - /* Thomson dtt7579 (not sure) PLL inside of: - Samsung DNOS404ZH102A NIM - Samsung DNOS404ZH103A NIM */ + switch (state->hw) { + case ANYSEE_HW_02: /* 2 */ + /* E30 */ + + /* attach tuner */ dvb_attach(dvb_pll_attach, adap->fe, (0xc2 >> 1), NULL, DVB_PLL_THOMSON_DTT7579); break; - case DVB_PLL_SAMSUNG_DTOS403IH102A: - /* Unknown PLL inside of Samsung DTOS403IH102A tuner module */ + case ANYSEE_HW_507CD: /* 6 */ + /* E30 Plus */ + + /* attach tuner */ + dvb_attach(dvb_pll_attach, adap->fe, (0xc2 >> 1), + &adap->dev->i2c_adap, DVB_PLL_THOMSON_DTT7579); + + break; + case ANYSEE_HW_507DC: /* 10 */ + /* E30 C Plus */ + + /* attach tuner */ + dvb_attach(dvb_pll_attach, adap->fe, (0xc0 >> 1), + &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A); + break; + case ANYSEE_HW_507FA: /* 15 */ + /* E30 Combo Plus */ + /* E30 C Plus */ + + if (dvb_usb_anysee_delsys) { + /* enable DVB-T tuner on IOE[0] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (0 << 0), + 0x01); + if (ret) + goto error; + } else { + /* enable DVB-C tuner on IOE[0] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 0), + 0x01); + if (ret) + goto error; + } + + /* attach tuner */ dvb_attach(dvb_pll_attach, adap->fe, (0xc0 >> 1), &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A); + break; + default: + ret = -ENODEV; } - return 0; +error: + return ret; } static int anysee_rc_query(struct dvb_usb_device *d) diff --git a/drivers/media/dvb/dvb-usb/anysee.h b/drivers/media/dvb/dvb-usb/anysee.h index 686e06044fcb..0f7b4d48a5c8 100644 --- a/drivers/media/dvb/dvb-usb/anysee.h +++ b/drivers/media/dvb/dvb-usb/anysee.h @@ -57,10 +57,27 @@ enum cmd { }; struct anysee_state { - u8 tuner; + u8 hw; /* PCB ID */ u8 seq; }; +#define ANYSEE_HW_02 2 /* E30 */ +#define ANYSEE_HW_507CD 6 /* E30 Plus */ +#define ANYSEE_HW_507DC 10 /* E30 C Plus */ +#define ANYSEE_HW_507SI 11 /* E30 S2 Plus */ +#define ANYSEE_HW_507FA 15 /* E30 Combo Plus / E30 C Plus */ + +#define REG_IOA 0x80 /* Port A (bit addressable) */ +#define REG_IOB 0x90 /* Port B (bit addressable) */ +#define REG_IOC 0xa0 /* Port C (bit addressable) */ +#define REG_IOD 0xb0 /* Port D (bit addressable) */ +#define REG_IOE 0xb1 /* Port E (NOT bit addressable) */ +#define REG_OEA 0xb2 /* Port A Output Enable */ +#define REG_OEB 0xb3 /* Port B Output Enable */ +#define REG_OEC 0xb4 /* Port C Output Enable */ +#define REG_OED 0xb5 /* Port D Output Enable */ +#define REG_OEE 0xb6 /* Port E Output Enable */ + #endif /*************************************************************************** -- cgit v1.2.3 From 72ffd2b822b4ff589432df0f56e3d2cd60c10447 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Sun, 10 Apr 2011 20:14:50 -0300 Subject: [media] anysee: add support for TDA18212 based E30 Combo Plus New models have new NXP TDA18212 silicon tuner. Not tested yet due to lack of HW... Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/Kconfig | 1 + drivers/media/dvb/dvb-usb/anysee.c | 106 +++++++++++++++++++++++++++++++++++-- 2 files changed, 102 insertions(+), 5 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig index c545039287ad..e624ff3ef070 100644 --- a/drivers/media/dvb/dvb-usb/Kconfig +++ b/drivers/media/dvb/dvb-usb/Kconfig @@ -292,6 +292,7 @@ config DVB_USB_ANYSEE select DVB_MT352 if !DVB_FE_CUSTOMISE select DVB_ZL10353 if !DVB_FE_CUSTOMISE select DVB_TDA10023 if !DVB_FE_CUSTOMISE + select MEDIA_TUNER_TDA18212 if !MEDIA_TUNER_CUSTOMISE help Say Y here to support the Anysee E30, Anysee E30 Plus or Anysee E30 C Plus DVB USB2.0 receiver. diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index ff9226e1843d..3c8a3abae831 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -36,6 +36,7 @@ #include "mt352.h" #include "mt352_priv.h" #include "zl10353.h" +#include "tda18212.h" /* debug */ static int dvb_usb_anysee_debug; @@ -265,6 +266,32 @@ static struct zl10353_config anysee_zl10353_config = { .parallel_ts = 1, }; +static struct zl10353_config anysee_zl10353_tda18212_config = { + .demod_address = (0x18 >> 1), + .parallel_ts = 1, + .disable_i2c_gate_ctrl = 1, + .no_tuner = 1, + .if2 = 41500, +}; + +static struct tda10023_config anysee_tda10023_tda18212_config = { + .demod_address = (0x1a >> 1), + .xtal = 16000000, + .pll_m = 12, + .pll_p = 3, + .pll_n = 1, + .output_mode = TDA10023_OUTPUT_MODE_PARALLEL_C, + .deltaf = 0xba02, +}; + +static struct tda18212_config anysee_tda18212_config = { + .i2c_address = (0xc0 >> 1), + .if_dvbt_6 = 4150, + .if_dvbt_7 = 4150, + .if_dvbt_8 = 4150, + .if_dvbc = 5000, +}; + /* * New USB device strings: Mfr=1, Product=2, SerialNumber=0 * Manufacturer: AMT.CO.KR @@ -316,6 +343,20 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) int ret; struct anysee_state *state = adap->dev->priv; u8 hw_info[3]; + u8 tmp; + struct i2c_msg msg[2] = { + { + .addr = anysee_tda18212_config.i2c_address, + .flags = 0, + .len = 1, + .buf = "\x00", + }, { + .addr = anysee_tda18212_config.i2c_address, + .flags = I2C_M_RD, + .len = 1, + .buf = &tmp, + } + }; /* Check which hardware we have. * We must do this call two times to get reliable values (hw bug). @@ -390,6 +431,24 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) /* E30 Combo Plus */ /* E30 C Plus */ + /* enable tuner on IOE[4] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 4), 0x10); + if (ret) + goto error; + + /* probe TDA18212 */ + tmp = 0; + ret = i2c_transfer(&adap->dev->i2c_adap, msg, 2); + if (ret == 2 && tmp == 0xc7) + deb_info("%s: TDA18212 found\n", __func__); + else + tmp = 0; + + /* disable tuner on IOE[4] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (0 << 4), 0x10); + if (ret) + goto error; + if (dvb_usb_anysee_delsys) { /* disable DVB-C demod on IOD[5] */ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (0 << 5), @@ -404,8 +463,17 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) goto error; /* attach demod */ - adap->fe = dvb_attach(zl10353_attach, - &anysee_zl10353_config, &adap->dev->i2c_adap); + if (tmp == 0xc7) { + /* TDA18212 config */ + adap->fe = dvb_attach(zl10353_attach, + &anysee_zl10353_tda18212_config, + &adap->dev->i2c_adap); + } else { + /* PLL config */ + adap->fe = dvb_attach(zl10353_attach, + &anysee_zl10353_config, + &adap->dev->i2c_adap); + } if (adap->fe) break; } else { @@ -422,9 +490,17 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) goto error; /* attach demod */ - adap->fe = dvb_attach(tda10023_attach, - &anysee_tda10023_config, &adap->dev->i2c_adap, - 0x48); + if (tmp == 0xc7) { + /* TDA18212 config */ + adap->fe = dvb_attach(tda10023_attach, + &anysee_tda10023_tda18212_config, + &adap->dev->i2c_adap, 0x48); + } else { + /* PLL config */ + adap->fe = dvb_attach(tda10023_attach, + &anysee_tda10023_config, + &adap->dev->i2c_adap, 0x48); + } if (adap->fe) break; } @@ -445,6 +521,7 @@ error: static int anysee_tuner_attach(struct dvb_usb_adapter *adap) { struct anysee_state *state = adap->dev->priv; + struct dvb_frontend *fe; int ret = 0; deb_info("%s:\n", __func__); @@ -475,6 +552,25 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) /* E30 Combo Plus */ /* E30 C Plus */ + /* Try first attach TDA18212 silicon tuner on IOE[4], if that + * fails attach old simple PLL. */ + + /* enable tuner on IOE[4] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 4), 0x10); + if (ret) + goto error; + + /* attach tuner */ + fe = dvb_attach(tda18212_attach, adap->fe, &adap->dev->i2c_adap, + &anysee_tda18212_config); + if (fe) + break; + + /* disable tuner on IOE[4] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (0 << 4), 0x10); + if (ret) + goto error; + if (dvb_usb_anysee_delsys) { /* enable DVB-T tuner on IOE[0] */ ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (0 << 0), -- cgit v1.2.3 From a43be980b3cf9c72f4bac4c7ce043e52004c6d90 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Sun, 10 Apr 2011 20:23:02 -0300 Subject: [media] anysee: add support for Anysee E7 TC It is ZL10353, TDA10023 and TDA18212. Tuner is inside of Samsung DNOD44CDH086A tuner module. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/anysee.c | 76 ++++++++++++++++++++++++++++++++++++++ drivers/media/dvb/dvb-usb/anysee.h | 1 + 2 files changed, 77 insertions(+) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index 3c8a3abae831..fa5acd040e93 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -505,6 +505,66 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) break; } break; + case ANYSEE_HW_508TC: /* 18 */ + /* E7 TC */ + + /* enable transport stream on IOA[7] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOA, (1 << 7), 0x80); + if (ret) + goto error; + + if (dvb_usb_anysee_delsys) { + /* disable DVB-C demod on IOD[5] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (0 << 5), + 0x20); + if (ret) + goto error; + + /* enable DVB-T demod on IOD[6] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 6), + 0x40); + if (ret) + goto error; + + /* enable IF route on IOE[0] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (0 << 0), + 0x01); + if (ret) + goto error; + + /* attach demod */ + adap->fe = dvb_attach(zl10353_attach, + &anysee_zl10353_tda18212_config, + &adap->dev->i2c_adap); + if (adap->fe) + break; + } else { + /* disable DVB-T demod on IOD[6] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (0 << 6), + 0x40); + if (ret) + goto error; + + /* enable DVB-C demod on IOD[5] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 5), + 0x20); + if (ret) + goto error; + + /* enable IF route on IOE[0] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 0), + 0x01); + if (ret) + goto error; + + /* attach demod */ + adap->fe = dvb_attach(tda10023_attach, + &anysee_tda10023_tda18212_config, + &adap->dev->i2c_adap, 0x48); + if (adap->fe) + break; + } + break; } if (!adap->fe) { @@ -590,6 +650,22 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A); break; + case ANYSEE_HW_508TC: /* 18 */ + /* E7 TC */ + + /* enable tuner on IOE[4] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 4), 0x10); + if (ret) + goto error; + + /* attach tuner */ + fe = dvb_attach(tda18212_attach, adap->fe, &adap->dev->i2c_adap, + &anysee_tda18212_config); + if (!fe) + ret = -ENODEV; + + break; + default: ret = -ENODEV; } diff --git a/drivers/media/dvb/dvb-usb/anysee.h b/drivers/media/dvb/dvb-usb/anysee.h index 0f7b4d48a5c8..c6181047b978 100644 --- a/drivers/media/dvb/dvb-usb/anysee.h +++ b/drivers/media/dvb/dvb-usb/anysee.h @@ -66,6 +66,7 @@ struct anysee_state { #define ANYSEE_HW_507DC 10 /* E30 C Plus */ #define ANYSEE_HW_507SI 11 /* E30 S2 Plus */ #define ANYSEE_HW_507FA 15 /* E30 Combo Plus / E30 C Plus */ +#define ANYSEE_HW_508TC 18 /* E7 TC */ #define REG_IOA 0x80 /* Port A (bit addressable) */ #define REG_IOB 0x90 /* Port B (bit addressable) */ -- cgit v1.2.3 From 59fb41409d21c491671f74c676373118f48e2136 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Tue, 12 Apr 2011 10:22:47 -0300 Subject: [media] anysee: fix E30 Combo Plus TDA18212 GPIO Looks like it is IF route switch on IOE[0]. Set it correctly to route signal from tuner to demod. Now it works for DVB-C too. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/anysee.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index fa5acd040e93..b0cac60d286f 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -612,6 +612,20 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) /* E30 Combo Plus */ /* E30 C Plus */ + if (dvb_usb_anysee_delsys) { + /* enable DVB-T tuner on IOE[0] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (0 << 0), + 0x01); + if (ret) + goto error; + } else { + /* enable DVB-C tuner on IOE[0] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 0), + 0x01); + if (ret) + goto error; + } + /* Try first attach TDA18212 silicon tuner on IOE[4], if that * fails attach old simple PLL. */ @@ -631,20 +645,6 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) if (ret) goto error; - if (dvb_usb_anysee_delsys) { - /* enable DVB-T tuner on IOE[0] */ - ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (0 << 0), - 0x01); - if (ret) - goto error; - } else { - /* enable DVB-C tuner on IOE[0] */ - ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 0), - 0x01); - if (ret) - goto error; - } - /* attach tuner */ dvb_attach(dvb_pll_attach, adap->fe, (0xc0 >> 1), &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A); -- cgit v1.2.3 From 1fd80701b5bd42fce36f4d32d5c5415354e68d98 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Tue, 12 Apr 2011 17:34:08 -0300 Subject: [media] anysee: fix E30 Combo Plus TDA18212 DVB-T Use correct I2C address for ZL10353 DVB-T demod. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/anysee.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index b0cac60d286f..e55a2c0ea81a 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -266,6 +266,14 @@ static struct zl10353_config anysee_zl10353_config = { .parallel_ts = 1, }; +static struct zl10353_config anysee_zl10353_tda18212_config2 = { + .demod_address = (0x1e >> 1), + .parallel_ts = 1, + .disable_i2c_gate_ctrl = 1, + .no_tuner = 1, + .if2 = 41500, +}; + static struct zl10353_config anysee_zl10353_tda18212_config = { .demod_address = (0x18 >> 1), .parallel_ts = 1, @@ -466,7 +474,7 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) if (tmp == 0xc7) { /* TDA18212 config */ adap->fe = dvb_attach(zl10353_attach, - &anysee_zl10353_tda18212_config, + &anysee_zl10353_tda18212_config2, &adap->dev->i2c_adap); } else { /* PLL config */ -- cgit v1.2.3 From e82eea79a3518e116f7e337fab2b5ca3072ed99c Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Tue, 12 Apr 2011 19:43:30 -0300 Subject: [media] anysee: enhance demod and tuner attach Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/anysee.c | 43 +++++++++++++++----------------------- 1 file changed, 17 insertions(+), 26 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index e55a2c0ea81a..27019471cdd9 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -396,8 +396,6 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) /* attach demod */ adap->fe = dvb_attach(zl10353_attach, &anysee_zl10353_config, &adap->dev->i2c_adap); - if (adap->fe) - break; break; case ANYSEE_HW_507CD: /* 6 */ @@ -416,8 +414,6 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) /* attach demod */ adap->fe = dvb_attach(zl10353_attach, &anysee_zl10353_config, &adap->dev->i2c_adap); - if (adap->fe) - break; break; case ANYSEE_HW_507DC: /* 10 */ @@ -431,8 +427,6 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) /* attach demod */ adap->fe = dvb_attach(tda10023_attach, &anysee_tda10023_config, &adap->dev->i2c_adap, 0x48); - if (adap->fe) - break; break; case ANYSEE_HW_507FA: /* 15 */ @@ -482,8 +476,6 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) &anysee_zl10353_config, &adap->dev->i2c_adap); } - if (adap->fe) - break; } else { /* disable DVB-T demod on IOD[0] */ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (0 << 0), @@ -509,9 +501,8 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) &anysee_tda10023_config, &adap->dev->i2c_adap, 0x48); } - if (adap->fe) - break; } + break; case ANYSEE_HW_508TC: /* 18 */ /* E7 TC */ @@ -544,8 +535,6 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) adap->fe = dvb_attach(zl10353_attach, &anysee_zl10353_tda18212_config, &adap->dev->i2c_adap); - if (adap->fe) - break; } else { /* disable DVB-T demod on IOD[6] */ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (0 << 6), @@ -569,18 +558,16 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) adap->fe = dvb_attach(tda10023_attach, &anysee_tda10023_tda18212_config, &adap->dev->i2c_adap, 0x48); - if (adap->fe) - break; } + break; } if (!adap->fe) { /* we have no frontend :-( */ ret = -ENODEV; - err("Unknown Anysee version: %02x %02x %02x. " \ - "Please report the <linux-media@vger.kernel.org>.", - hw_info[0], hw_info[1], hw_info[2]); + err("Unsupported Anysee version. " \ + "Please report the <linux-media@vger.kernel.org>."); } error: return ret; @@ -590,7 +577,7 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) { struct anysee_state *state = adap->dev->priv; struct dvb_frontend *fe; - int ret = 0; + int ret; deb_info("%s:\n", __func__); switch (state->hw) { @@ -598,14 +585,15 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) /* E30 */ /* attach tuner */ - dvb_attach(dvb_pll_attach, adap->fe, (0xc2 >> 1), + fe = dvb_attach(dvb_pll_attach, adap->fe, (0xc2 >> 1), NULL, DVB_PLL_THOMSON_DTT7579); + break; case ANYSEE_HW_507CD: /* 6 */ /* E30 Plus */ /* attach tuner */ - dvb_attach(dvb_pll_attach, adap->fe, (0xc2 >> 1), + fe = dvb_attach(dvb_pll_attach, adap->fe, (0xc2 >> 1), &adap->dev->i2c_adap, DVB_PLL_THOMSON_DTT7579); break; @@ -613,8 +601,9 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) /* E30 C Plus */ /* attach tuner */ - dvb_attach(dvb_pll_attach, adap->fe, (0xc0 >> 1), + fe = dvb_attach(dvb_pll_attach, adap->fe, (0xc0 >> 1), &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A); + break; case ANYSEE_HW_507FA: /* 15 */ /* E30 Combo Plus */ @@ -654,7 +643,7 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) goto error; /* attach tuner */ - dvb_attach(dvb_pll_attach, adap->fe, (0xc0 >> 1), + fe = dvb_attach(dvb_pll_attach, adap->fe, (0xc0 >> 1), &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A); break; @@ -669,15 +658,17 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) /* attach tuner */ fe = dvb_attach(tda18212_attach, adap->fe, &adap->dev->i2c_adap, &anysee_tda18212_config); - if (!fe) - ret = -ENODEV; break; - default: - ret = -ENODEV; + fe = NULL; } + if (fe) + ret = 0; + else + ret = -ENODEV; + error: return ret; } -- cgit v1.2.3 From 882b82caf2cb8210e6829231cb352dea33f83f4c Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Tue, 12 Apr 2011 19:49:25 -0300 Subject: [media] anysee: add support for two byte I2C address After that Anysee I2C adapter is capable of one and two byte long I2C addresses in case of read from I2C bus. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/anysee.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index 27019471cdd9..f365c2068e0f 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -186,8 +186,8 @@ static int anysee_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, buf[0] = CMD_I2C_READ; buf[1] = (msg[i].addr << 1) | 0x01; buf[2] = msg[i].buf[0]; - buf[3] = 0x00; - buf[4] = 0x00; + buf[3] = msg[i].buf[1]; + buf[4] = msg[i].len-1; buf[5] = msg[i+1].len; ret = anysee_ctrl_msg(d, buf, sizeof(buf), msg[i+1].buf, msg[i+1].len); -- cgit v1.2.3 From 70fc26fbcd0ac8e6bc1ca1cdc6fe623e7ac37ca1 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Tue, 12 Apr 2011 20:17:11 -0300 Subject: [media] anysee: add more info about known board configs Add some comments about known GPIO settings of supported board versions. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/anysee.c | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index f365c2068e0f..0e94541ffcff 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -306,37 +306,41 @@ static struct tda18212_config anysee_tda18212_config = { * * E30 VID=04b4 PID=861f HW=2 FW=2.1 Product=???????? * PCB: ? - * parts: MT352, DTT7579(?), DNOS404ZH102A NIM + * parts: DNOS404ZH102A(MT352, DTT7579(?)) * * E30 VID=04b4 PID=861f HW=2 FW=2.1 Product=???????? * PCB: ? - * parts: ZL10353, DTT7579(?), DNOS404ZH103A NIM + * parts: DNOS404ZH103A(ZL10353, DTT7579(?)) * * E30 Plus VID=04b4 PID=861f HW=6 FW=1.0 "anysee" * PCB: 507CD (rev1.1) - * parts: ZL10353, DTT7579(?), CST56I01, DNOS404ZH103A NIM + * parts: DNOS404ZH103A(ZL10353, DTT7579(?)), CST56I01 * OEA=80 OEB=00 OEC=00 OED=ff OEF=fe + * IOA=4f IOB=ff IOC=00 IOD=06 IOF=01 * IOD[0] ZL10353 1=enabled * IOA[7] TS 0=enabled * tuner is not behind ZL10353 I2C-gate (no care if gate disabled or not) * * E30 C Plus VID=04b4 PID=861f HW=10 FW=1.0 "anysee-DC(LP)" * PCB: 507DC (rev0.2) - * parts: TDA10023, CST56I01, DTOS403IH102B TM + * parts: TDA10023, DTOS403IH102B TM, CST56I01 * OEA=80 OEB=00 OEC=00 OED=ff OEF=fe + * IOA=4f IOB=ff IOC=00 IOD=26 IOF=01 * IOD[0] TDA10023 1=enabled * * E30 C Plus VID=1c73 PID=861f HW=15 FW=1.2 "anysee-FA(LP)" * PCB: 507FA (rev0.4) - * parts: TDA10023, TDA8024, DTOS403IH102B TM + * parts: TDA10023, DTOS403IH102B TM, TDA8024 * OEA=80 OEB=00 OEC=ff OED=ff OEF=ff + * IOA=4d IOB=ff IOC=00 IOD=00 IOF=c0 * IOD[5] TDA10023 1=enabled * IOE[0] tuner 1=enabled * * E30 Combo Plus VID=1c73 PID=861f HW=15 FW=1.2 "anysee-FA(LP)" * PCB: 507FA (rev1.1) - * parts: ZL10353, TDA10023, TDA8024, DTOS403IH102B TM + * parts: ZL10353, TDA10023, DTOS403IH102B TM, TDA8024 * OEA=80 OEB=00 OEC=ff OED=ff OEF=ff + * IOA=4d IOB=ff IOC=00 IOD=00 IOF=c0 * DVB-C: * IOD[5] TDA10023 1=enabled * IOE[0] tuner 1=enabled @@ -344,6 +348,22 @@ static struct tda18212_config anysee_tda18212_config = { * IOD[0] ZL10353 1=enabled * IOE[0] tuner 0=enabled * tuner is behind ZL10353 I2C-gate + * + * E7 TC VID=1c73 PID=861f HW=18 FW=0.7 AMTCI=0.5 "anysee-E7TC(LP)" + * PCB: 508TC (rev0.6) + * parts: ZL10353, TDA10023, DNOD44CDH086A(TDA18212) + * OEA=80 OEB=00 OEC=03 OED=f7 OEF=ff + * IOA=4d IOB=00 IOC=cc IOD=48 IOF=e4 + * IOA[7] TS 1=enabled + * IOE[4] TDA18212 1=enabled + * DVB-C: + * IOD[6] ZL10353 0=disabled + * IOD[5] TDA10023 1=enabled + * IOE[0] IF 1=enabled + * DVB-T: + * IOD[5] TDA10023 0=disabled + * IOD[6] ZL10353 1=enabled + * IOE[0] IF 0=enabled */ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) -- cgit v1.2.3 From 56c0893c4f66a5d249b8981101755bec5890500d Mon Sep 17 00:00:00 2001 From: Jarod Wilson <jarod@redhat.com> Date: Tue, 5 Apr 2011 18:42:30 -0300 Subject: [media] rc: further key name standardization Use the newly introduced KEY_IMAGES where appropriate, and standardize on KEY_MEDIA for media center/application launcher button (such as the Windows logo key on the Windows Media Center Ed. remotes). Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/dibusb-common.c | 2 +- drivers/media/dvb/dvb-usb/m920x.c | 16 ++++++++-------- drivers/media/dvb/dvb-usb/nova-t-usb2.c | 2 +- drivers/media/rc/keymaps/rc-avermedia-cardbus.c | 2 +- drivers/media/rc/keymaps/rc-imon-mce.c | 2 +- drivers/media/rc/keymaps/rc-imon-pad.c | 6 +++--- drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c | 2 +- drivers/media/rc/keymaps/rc-rc6-mce.c | 4 ++-- 8 files changed, 18 insertions(+), 18 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/dibusb-common.c b/drivers/media/dvb/dvb-usb/dibusb-common.c index 956f7ae2e510..4c2a689c820e 100644 --- a/drivers/media/dvb/dvb-usb/dibusb-common.c +++ b/drivers/media/dvb/dvb-usb/dibusb-common.c @@ -408,7 +408,7 @@ struct rc_map_table rc_map_dibusb_table[] = { { 0x8008, KEY_DVD }, { 0x8009, KEY_AUDIO }, - { 0x800a, KEY_MEDIA }, /* Pictures */ + { 0x800a, KEY_IMAGES }, /* Pictures */ { 0x800b, KEY_VIDEO }, { 0x800c, KEY_BACK }, diff --git a/drivers/media/dvb/dvb-usb/m920x.c b/drivers/media/dvb/dvb-usb/m920x.c index da9dc91ce910..51bfd42387c2 100644 --- a/drivers/media/dvb/dvb-usb/m920x.c +++ b/drivers/media/dvb/dvb-usb/m920x.c @@ -632,9 +632,9 @@ static struct rc_map_table rc_map_pinnacle310e_table[] = { { 0x16, KEY_POWER }, { 0x17, KEY_FAVORITES }, { 0x0f, KEY_TEXT }, - { 0x48, KEY_MEDIA }, /* preview */ + { 0x48, KEY_PROGRAM }, /* preview */ { 0x1c, KEY_EPG }, - { 0x04, KEY_LIST }, /* record list */ + { 0x04, KEY_LIST }, /* record list */ { 0x03, KEY_1 }, { 0x01, KEY_2 }, { 0x06, KEY_3 }, @@ -674,14 +674,14 @@ static struct rc_map_table rc_map_pinnacle310e_table[] = { { 0x0e, KEY_MUTE }, /* { 0x49, KEY_LR }, */ /* L/R */ { 0x07, KEY_SLEEP }, /* Hibernate */ - { 0x08, KEY_MEDIA }, /* A/V */ - { 0x0e, KEY_MENU }, /* Recall */ + { 0x08, KEY_VIDEO }, /* A/V */ + { 0x0e, KEY_MENU }, /* Recall */ { 0x45, KEY_ZOOMIN }, { 0x46, KEY_ZOOMOUT }, - { 0x18, KEY_TV }, /* Red */ - { 0x53, KEY_VCR }, /* Green */ - { 0x5e, KEY_SAT }, /* Yellow */ - { 0x5f, KEY_PLAYER }, /* Blue */ + { 0x18, KEY_RED }, /* Red */ + { 0x53, KEY_GREEN }, /* Green */ + { 0x5e, KEY_YELLOW }, /* Yellow */ + { 0x5f, KEY_BLUE }, /* Blue */ }; /* DVB USB Driver stuff */ diff --git a/drivers/media/dvb/dvb-usb/nova-t-usb2.c b/drivers/media/dvb/dvb-usb/nova-t-usb2.c index 9d3cd2de46fc..bc350e982b72 100644 --- a/drivers/media/dvb/dvb-usb/nova-t-usb2.c +++ b/drivers/media/dvb/dvb-usb/nova-t-usb2.c @@ -47,7 +47,7 @@ static struct rc_map_table rc_map_haupp_table[] = { { 0x1e17, KEY_RIGHT }, { 0x1e18, KEY_VIDEO }, { 0x1e19, KEY_AUDIO }, - { 0x1e1a, KEY_MEDIA }, + { 0x1e1a, KEY_IMAGES }, { 0x1e1b, KEY_EPG }, { 0x1e1c, KEY_TV }, { 0x1e1e, KEY_NEXT }, diff --git a/drivers/media/rc/keymaps/rc-avermedia-cardbus.c b/drivers/media/rc/keymaps/rc-avermedia-cardbus.c index bdf97b74cf90..22f54d413a35 100644 --- a/drivers/media/rc/keymaps/rc-avermedia-cardbus.c +++ b/drivers/media/rc/keymaps/rc-avermedia-cardbus.c @@ -52,7 +52,7 @@ static struct rc_map_table avermedia_cardbus[] = { { 0x28, KEY_SELECT }, /* Select */ { 0x29, KEY_BLUE }, /* Blue/Picture */ { 0x2a, KEY_BACKSPACE }, /* Back */ - { 0x2b, KEY_MEDIA }, /* PIP (Picture-in-picture) */ + { 0x2b, KEY_VIDEO }, /* PIP (Picture-in-picture) */ { 0x2c, KEY_DOWN }, { 0x2e, KEY_DOT }, { 0x2f, KEY_TV }, /* Live TV */ diff --git a/drivers/media/rc/keymaps/rc-imon-mce.c b/drivers/media/rc/keymaps/rc-imon-mce.c index 937a81989f00..0ea2aa190d81 100644 --- a/drivers/media/rc/keymaps/rc-imon-mce.c +++ b/drivers/media/rc/keymaps/rc-imon-mce.c @@ -111,7 +111,7 @@ static struct rc_map_table imon_mce[] = { { 0x800ff44d, KEY_TITLE }, { 0x800ff40c, KEY_POWER }, - { 0x800ff40d, KEY_LEFTMETA }, /* Windows MCE button */ + { 0x800ff40d, KEY_MEDIA }, /* Windows MCE button */ }; diff --git a/drivers/media/rc/keymaps/rc-imon-pad.c b/drivers/media/rc/keymaps/rc-imon-pad.c index 63d42bd24c9e..75d3843fdc30 100644 --- a/drivers/media/rc/keymaps/rc-imon-pad.c +++ b/drivers/media/rc/keymaps/rc-imon-pad.c @@ -87,7 +87,7 @@ static struct rc_map_table imon_pad[] = { { 0x2b8515b7, KEY_VIDEO }, { 0x299195b7, KEY_AUDIO }, - { 0x2ba115b7, KEY_CAMERA }, + { 0x2ba115b7, KEY_IMAGES }, { 0x28a515b7, KEY_TV }, { 0x29a395b7, KEY_DVD }, { 0x29a295b7, KEY_DVD }, @@ -97,7 +97,7 @@ static struct rc_map_table imon_pad[] = { { 0x2ba395b7, KEY_MENU }, { 0x288515b7, KEY_BOOKMARKS }, - { 0x2ab715b7, KEY_MEDIA }, /* Thumbnail */ + { 0x2ab715b7, KEY_CAMERA }, /* Thumbnail */ { 0x298595b7, KEY_SUBTITLE }, { 0x2b8595b7, KEY_LANGUAGE }, @@ -125,7 +125,7 @@ static struct rc_map_table imon_pad[] = { { 0x2b8195b7, KEY_CONTEXT_MENU }, /* Left Menu*/ { 0x02000065, KEY_COMPOSE }, /* RightMenu */ { 0x28b715b7, KEY_COMPOSE }, /* RightMenu */ - { 0x2ab195b7, KEY_LEFTMETA }, /* Go or MultiMon */ + { 0x2ab195b7, KEY_MEDIA }, /* Go or MultiMon */ { 0x29b715b7, KEY_DASHBOARD }, /* AppLauncher */ }; diff --git a/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c b/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c index 08d183120e41..7fa17a369f2d 100644 --- a/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c +++ b/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c @@ -17,7 +17,7 @@ */ static struct rc_map_table kworld_plus_tv_analog[] = { - { 0x0c, KEY_LEFTMETA }, /* Kworld key */ + { 0x0c, KEY_MEDIA }, /* Kworld key */ { 0x16, KEY_CLOSECD }, /* -> ) */ { 0x1d, KEY_POWER2 }, diff --git a/drivers/media/rc/keymaps/rc-rc6-mce.c b/drivers/media/rc/keymaps/rc-rc6-mce.c index 8dd519ecc58e..01b69bcc8666 100644 --- a/drivers/media/rc/keymaps/rc-rc6-mce.c +++ b/drivers/media/rc/keymaps/rc-rc6-mce.c @@ -30,7 +30,7 @@ static struct rc_map_table rc6_mce[] = { { 0x800f040a, KEY_DELETE }, { 0x800f040b, KEY_ENTER }, { 0x800f040c, KEY_POWER }, /* PC Power */ - { 0x800f040d, KEY_LEFTMETA }, /* Windows MCE button */ + { 0x800f040d, KEY_MEDIA }, /* Windows MCE button */ { 0x800f040e, KEY_MUTE }, { 0x800f040f, KEY_INFO }, @@ -87,7 +87,7 @@ static struct rc_map_table rc6_mce[] = { { 0x800f0465, KEY_POWER2 }, /* TV Power */ { 0x800f046e, KEY_PLAYPAUSE }, - { 0x800f046f, KEY_MEDIA }, /* Start media application (NEW) */ + { 0x800f046f, KEY_PLAYER }, /* Start media application (NEW) */ { 0x800f0480, KEY_BRIGHTNESSDOWN }, { 0x800f0481, KEY_PLAYPAUSE }, -- cgit v1.2.3 From 68a49a4a3dc9354b6daa24dd87e4e246b6da3c13 Mon Sep 17 00:00:00 2001 From: Jarod Wilson <jarod@redhat.com> Date: Thu, 24 Mar 2011 12:56:16 -0300 Subject: [media] ttusb-budget: driver has a debug param, use it Remove DEBUG define, key debug spew off of the module's debug param that already exists. Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c | 60 ++++++++++------------- 1 file changed, 27 insertions(+), 33 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c b/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c index cbe2f0de1442..420bb42d5233 100644 --- a/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c +++ b/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c @@ -52,7 +52,7 @@ my TTUSB, so let it undef'd unless you want to implement another frontend. never tested. - DEBUG: + debug: define it to > 3 for really hardcore debugging. you probably don't want this unless the device doesn't load at all. > 2 for bandwidth statistics. */ @@ -134,20 +134,19 @@ struct ttusb { /* ugly workaround ... don't know why it's necessary to read */ /* all result codes. */ -#define DEBUG 0 static int ttusb_cmd(struct ttusb *ttusb, const u8 * data, int len, int needresult) { int actual_len; int err; -#if DEBUG >= 3 int i; - printk(">"); - for (i = 0; i < len; ++i) - printk(" %02x", data[i]); - printk("\n"); -#endif + if (debug >= 3) { + printk(KERN_DEBUG ">"); + for (i = 0; i < len; ++i) + printk(KERN_CONT " %02x", data[i]); + printk(KERN_CONT "\n"); + } if (mutex_lock_interruptible(&ttusb->semusb) < 0) return -EAGAIN; @@ -176,13 +175,15 @@ static int ttusb_cmd(struct ttusb *ttusb, mutex_unlock(&ttusb->semusb); return err; } -#if DEBUG >= 3 - actual_len = ttusb->last_result[3] + 4; - printk("<"); - for (i = 0; i < actual_len; ++i) - printk(" %02x", ttusb->last_result[i]); - printk("\n"); -#endif + + if (debug >= 3) { + actual_len = ttusb->last_result[3] + 4; + printk(KERN_DEBUG "<"); + for (i = 0; i < actual_len; ++i) + printk(KERN_CONT " %02x", ttusb->last_result[i]); + printk(KERN_CONT "\n"); + } + if (!needresult) mutex_unlock(&ttusb->semusb); return 0; @@ -636,16 +637,13 @@ static void ttusb_process_frame(struct ttusb *ttusb, u8 * data, int len) ++ttusb->mux_state; else { ttusb->mux_state = 0; -#if DEBUG > 3 - if (ttusb->insync) - printk("%02x ", data[-1]); -#else if (ttusb->insync) { - printk("%s: lost sync.\n", + dprintk("%s: %02x\n", + __func__, data[-1]); + printk(KERN_INFO "%s: lost sync.\n", __func__); ttusb->insync = 0; } -#endif } break; case 3: @@ -744,6 +742,9 @@ static void ttusb_process_frame(struct ttusb *ttusb, u8 * data, int len) static void ttusb_iso_irq(struct urb *urb) { struct ttusb *ttusb = urb->context; + struct usb_iso_packet_descriptor *d; + u8 *data; + int len, i; if (!ttusb->iso_streaming) return; @@ -755,21 +756,14 @@ static void ttusb_iso_irq(struct urb *urb) #endif if (!urb->status) { - int i; for (i = 0; i < urb->number_of_packets; ++i) { - struct usb_iso_packet_descriptor *d; - u8 *data; - int len; numpkt++; if (time_after_eq(jiffies, lastj + HZ)) { -#if DEBUG > 2 - printk - ("frames/s: %d (ts: %d, stuff %d, sec: %d, invalid: %d, all: %d)\n", - numpkt * HZ / (jiffies - lastj), - numts, numstuff, numsec, numinvalid, - numts + numstuff + numsec + - numinvalid); -#endif + dprintk("frames/s: %lu (ts: %d, stuff %d, " + "sec: %d, invalid: %d, all: %d)\n", + numpkt * HZ / (jiffies - lastj), + numts, numstuff, numsec, numinvalid, + numts + numstuff + numsec + numinvalid); numts = numstuff = numsec = numinvalid = 0; lastj = jiffies; numpkt = 0; -- cgit v1.2.3 From b9f7b73c8c107d83a4c04c4f29a2ca96f7e73faf Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Sun, 20 Mar 2011 18:50:51 -0300 Subject: [media] lmedm04: correct indentation This should not change anything except whitespace. Signed-off-by: Florian Mickler <florian@mickler.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/lmedm04.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/lmedm04.c b/drivers/media/dvb/dvb-usb/lmedm04.c index 3c521db0a130..b47ec3055ff7 100644 --- a/drivers/media/dvb/dvb-usb/lmedm04.c +++ b/drivers/media/dvb/dvb-usb/lmedm04.c @@ -678,15 +678,15 @@ static int lme2510_download_firmware(struct usb_device *dev, data[0] = i | 0x80; dlen = (u8)(end - j)-1; } - data[1] = dlen; - memcpy(&data[2], fw_data, dlen+1); - wlen = (u8) dlen + 4; - data[wlen-1] = check_sum(fw_data, dlen+1); - deb_info(1, "Data S=%02x:E=%02x CS= %02x", data[3], + data[1] = dlen; + memcpy(&data[2], fw_data, dlen+1); + wlen = (u8) dlen + 4; + data[wlen-1] = check_sum(fw_data, dlen+1); + deb_info(1, "Data S=%02x:E=%02x CS= %02x", data[3], data[dlen+2], data[dlen+3]); - ret |= lme2510_bulk_write(dev, data, wlen, 1); - ret |= lme2510_bulk_read(dev, data, len_in , 1); - ret |= (data[0] == 0x88) ? 0 : -1; + ret |= lme2510_bulk_write(dev, data, wlen, 1); + ret |= lme2510_bulk_read(dev, data, len_in , 1); + ret |= (data[0] == 0x88) ? 0 : -1; } } -- cgit v1.2.3 From ffa5899ce8a6d82e42ae0ca23a10cf92d914045e Mon Sep 17 00:00:00 2001 From: Olivier Grenie <olivier.grenie@dibcom.fr> Date: Thu, 24 Mar 2011 09:32:26 -0300 Subject: [media] DiB0700: get rid of on-stack dma buffers This patch removes the on-stack buffers for USB DMA transfers. This is an alternative version of the patch discussed by Florian here: http://thread.gmane.org/gmane.linux.kernel/1115695/ Signed-off-by: Olivier Grenie <olivier.grenie@dibcom.fr> Signed-off-by: Patrick Boettcher <patrick.boettcher@dibcom.fr> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/dib0700.h | 5 +- drivers/media/dvb/dvb-usb/dib0700_core.c | 218 +++++++++++++++++++------------ 2 files changed, 136 insertions(+), 87 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/dib0700.h b/drivers/media/dvb/dvb-usb/dib0700.h index b2a87f2c2c3e..9bd6d51b3b93 100644 --- a/drivers/media/dvb/dvb-usb/dib0700.h +++ b/drivers/media/dvb/dvb-usb/dib0700.h @@ -46,8 +46,9 @@ struct dib0700_state { u8 is_dib7000pc; u8 fw_use_new_i2c_api; u8 disable_streaming_master_mode; - u32 fw_version; - u32 nb_packet_buffer_size; + u32 fw_version; + u32 nb_packet_buffer_size; + u8 buf[255]; }; extern int dib0700_get_version(struct dvb_usb_device *d, u32 *hwversion, diff --git a/drivers/media/dvb/dvb-usb/dib0700_core.c b/drivers/media/dvb/dvb-usb/dib0700_core.c index b79af68c54ae..0325825961b9 100644 --- a/drivers/media/dvb/dvb-usb/dib0700_core.c +++ b/drivers/media/dvb/dvb-usb/dib0700_core.c @@ -27,19 +27,25 @@ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); int dib0700_get_version(struct dvb_usb_device *d, u32 *hwversion, u32 *romversion, u32 *ramversion, u32 *fwtype) { - u8 b[16]; - int ret = usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev, 0), + struct dib0700_state *st = d->priv; + int ret; + + ret = usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev, 0), REQUEST_GET_VERSION, USB_TYPE_VENDOR | USB_DIR_IN, 0, 0, - b, sizeof(b), USB_CTRL_GET_TIMEOUT); + st->buf, 16, USB_CTRL_GET_TIMEOUT); if (hwversion != NULL) - *hwversion = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; + *hwversion = (st->buf[0] << 24) | (st->buf[1] << 16) | + (st->buf[2] << 8) | st->buf[3]; if (romversion != NULL) - *romversion = (b[4] << 24) | (b[5] << 16) | (b[6] << 8) | b[7]; + *romversion = (st->buf[4] << 24) | (st->buf[5] << 16) | + (st->buf[6] << 8) | st->buf[7]; if (ramversion != NULL) - *ramversion = (b[8] << 24) | (b[9] << 16) | (b[10] << 8) | b[11]; + *ramversion = (st->buf[8] << 24) | (st->buf[9] << 16) | + (st->buf[10] << 8) | st->buf[11]; if (fwtype != NULL) - *fwtype = (b[12] << 24) | (b[13] << 16) | (b[14] << 8) | b[15]; + *fwtype = (st->buf[12] << 24) | (st->buf[13] << 16) | + (st->buf[14] << 8) | st->buf[15]; return ret; } @@ -101,24 +107,31 @@ int dib0700_ctrl_rd(struct dvb_usb_device *d, u8 *tx, u8 txlen, u8 *rx, u8 rxlen int dib0700_set_gpio(struct dvb_usb_device *d, enum dib07x0_gpios gpio, u8 gpio_dir, u8 gpio_val) { - u8 buf[3] = { REQUEST_SET_GPIO, gpio, ((gpio_dir & 0x01) << 7) | ((gpio_val & 0x01) << 6) }; - return dib0700_ctrl_wr(d, buf, sizeof(buf)); + struct dib0700_state *st = d->priv; + s16 ret; + + st->buf[0] = REQUEST_SET_GPIO; + st->buf[1] = gpio; + st->buf[2] = ((gpio_dir & 0x01) << 7) | ((gpio_val & 0x01) << 6); + + ret = dib0700_ctrl_wr(d, st->buf, 3); + + return ret; } static int dib0700_set_usb_xfer_len(struct dvb_usb_device *d, u16 nb_ts_packets) { struct dib0700_state *st = d->priv; - u8 b[3]; int ret; if (st->fw_version >= 0x10201) { - b[0] = REQUEST_SET_USB_XFER_LEN; - b[1] = (nb_ts_packets >> 8) & 0xff; - b[2] = nb_ts_packets & 0xff; + st->buf[0] = REQUEST_SET_USB_XFER_LEN; + st->buf[1] = (nb_ts_packets >> 8) & 0xff; + st->buf[2] = nb_ts_packets & 0xff; deb_info("set the USB xfer len to %i Ts packet\n", nb_ts_packets); - ret = dib0700_ctrl_wr(d, b, sizeof(b)); + ret = dib0700_ctrl_wr(d, st->buf, 3); } else { deb_info("this firmware does not allow to change the USB xfer len\n"); ret = -EIO; @@ -137,11 +150,11 @@ static int dib0700_i2c_xfer_new(struct i2c_adapter *adap, struct i2c_msg *msg, properly support i2c read calls not preceded by a write */ struct dvb_usb_device *d = i2c_get_adapdata(adap); + struct dib0700_state *st = d->priv; uint8_t bus_mode = 1; /* 0=eeprom bus, 1=frontend bus */ uint8_t gen_mode = 0; /* 0=master i2c, 1=gpio i2c */ uint8_t en_start = 0; uint8_t en_stop = 0; - uint8_t buf[255]; /* TBV: malloc ? */ int result, i; /* Ensure nobody else hits the i2c bus while we're sending our @@ -195,24 +208,24 @@ static int dib0700_i2c_xfer_new(struct i2c_adapter *adap, struct i2c_msg *msg, } else { /* Write request */ - buf[0] = REQUEST_NEW_I2C_WRITE; - buf[1] = msg[i].addr << 1; - buf[2] = (en_start << 7) | (en_stop << 6) | + st->buf[0] = REQUEST_NEW_I2C_WRITE; + st->buf[1] = msg[i].addr << 1; + st->buf[2] = (en_start << 7) | (en_stop << 6) | (msg[i].len & 0x3F); /* I2C ctrl + FE bus; */ - buf[3] = ((gen_mode << 6) & 0xC0) | + st->buf[3] = ((gen_mode << 6) & 0xC0) | ((bus_mode << 4) & 0x30); /* The Actual i2c payload */ - memcpy(&buf[4], msg[i].buf, msg[i].len); + memcpy(&st->buf[4], msg[i].buf, msg[i].len); deb_data(">>> "); - debug_dump(buf, msg[i].len + 4, deb_data); + debug_dump(st->buf, msg[i].len + 4, deb_data); result = usb_control_msg(d->udev, usb_sndctrlpipe(d->udev, 0), REQUEST_NEW_I2C_WRITE, USB_TYPE_VENDOR | USB_DIR_OUT, - 0, 0, buf, msg[i].len + 4, + 0, 0, st->buf, msg[i].len + 4, USB_CTRL_GET_TIMEOUT); if (result < 0) { deb_info("i2c write error (status = %d)\n", result); @@ -231,27 +244,29 @@ static int dib0700_i2c_xfer_legacy(struct i2c_adapter *adap, struct i2c_msg *msg, int num) { struct dvb_usb_device *d = i2c_get_adapdata(adap); + struct dib0700_state *st = d->priv; int i,len; - u8 buf[255]; if (mutex_lock_interruptible(&d->i2c_mutex) < 0) return -EAGAIN; for (i = 0; i < num; i++) { /* fill in the address */ - buf[1] = msg[i].addr << 1; + st->buf[1] = msg[i].addr << 1; /* fill the buffer */ - memcpy(&buf[2], msg[i].buf, msg[i].len); + memcpy(&st->buf[2], msg[i].buf, msg[i].len); /* write/read request */ if (i+1 < num && (msg[i+1].flags & I2C_M_RD)) { - buf[0] = REQUEST_I2C_READ; - buf[1] |= 1; + st->buf[0] = REQUEST_I2C_READ; + st->buf[1] |= 1; /* special thing in the current firmware: when length is zero the read-failed */ - if ((len = dib0700_ctrl_rd(d, buf, msg[i].len + 2, msg[i+1].buf, msg[i+1].len)) <= 0) { + len = dib0700_ctrl_rd(d, st->buf, msg[i].len + 2, + msg[i+1].buf, msg[i+1].len); + if (len <= 0) { deb_info("I2C read failed on address 0x%02x\n", - msg[i].addr); + msg[i].addr); break; } @@ -259,13 +274,13 @@ static int dib0700_i2c_xfer_legacy(struct i2c_adapter *adap, i++; } else { - buf[0] = REQUEST_I2C_WRITE; - if (dib0700_ctrl_wr(d, buf, msg[i].len + 2) < 0) + st->buf[0] = REQUEST_I2C_WRITE; + if (dib0700_ctrl_wr(d, st->buf, msg[i].len + 2) < 0) break; } } - mutex_unlock(&d->i2c_mutex); + return i; } @@ -297,15 +312,23 @@ struct i2c_algorithm dib0700_i2c_algo = { int dib0700_identify_state(struct usb_device *udev, struct dvb_usb_device_properties *props, struct dvb_usb_device_description **desc, int *cold) { - u8 b[16]; - s16 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev,0), + s16 ret; + u8 *b; + + b = kmalloc(16, GFP_KERNEL); + if (!b) + return -ENOMEM; + + + ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), REQUEST_GET_VERSION, USB_TYPE_VENDOR | USB_DIR_IN, 0, 0, b, 16, USB_CTRL_GET_TIMEOUT); deb_info("FW GET_VERSION length: %d\n",ret); *cold = ret <= 0; - deb_info("cold: %d\n", *cold); + + kfree(b); return 0; } @@ -313,43 +336,50 @@ static int dib0700_set_clock(struct dvb_usb_device *d, u8 en_pll, u8 pll_src, u8 pll_range, u8 clock_gpio3, u16 pll_prediv, u16 pll_loopdiv, u16 free_div, u16 dsuScaler) { - u8 b[10]; - b[0] = REQUEST_SET_CLOCK; - b[1] = (en_pll << 7) | (pll_src << 6) | (pll_range << 5) | (clock_gpio3 << 4); - b[2] = (pll_prediv >> 8) & 0xff; // MSB - b[3] = pll_prediv & 0xff; // LSB - b[4] = (pll_loopdiv >> 8) & 0xff; // MSB - b[5] = pll_loopdiv & 0xff; // LSB - b[6] = (free_div >> 8) & 0xff; // MSB - b[7] = free_div & 0xff; // LSB - b[8] = (dsuScaler >> 8) & 0xff; // MSB - b[9] = dsuScaler & 0xff; // LSB - - return dib0700_ctrl_wr(d, b, 10); + struct dib0700_state *st = d->priv; + s16 ret; + + st->buf[0] = REQUEST_SET_CLOCK; + st->buf[1] = (en_pll << 7) | (pll_src << 6) | + (pll_range << 5) | (clock_gpio3 << 4); + st->buf[2] = (pll_prediv >> 8) & 0xff; /* MSB */ + st->buf[3] = pll_prediv & 0xff; /* LSB */ + st->buf[4] = (pll_loopdiv >> 8) & 0xff; /* MSB */ + st->buf[5] = pll_loopdiv & 0xff; /* LSB */ + st->buf[6] = (free_div >> 8) & 0xff; /* MSB */ + st->buf[7] = free_div & 0xff; /* LSB */ + st->buf[8] = (dsuScaler >> 8) & 0xff; /* MSB */ + st->buf[9] = dsuScaler & 0xff; /* LSB */ + + ret = dib0700_ctrl_wr(d, st->buf, 10); + + return ret; } int dib0700_set_i2c_speed(struct dvb_usb_device *d, u16 scl_kHz) { + struct dib0700_state *st = d->priv; u16 divider; - u8 b[8]; if (scl_kHz == 0) return -EINVAL; - b[0] = REQUEST_SET_I2C_PARAM; + st->buf[0] = REQUEST_SET_I2C_PARAM; divider = (u16) (30000 / scl_kHz); - b[2] = (u8) (divider >> 8); - b[3] = (u8) (divider & 0xff); + st->buf[1] = 0; + st->buf[2] = (u8) (divider >> 8); + st->buf[3] = (u8) (divider & 0xff); divider = (u16) (72000 / scl_kHz); - b[4] = (u8) (divider >> 8); - b[5] = (u8) (divider & 0xff); + st->buf[4] = (u8) (divider >> 8); + st->buf[5] = (u8) (divider & 0xff); divider = (u16) (72000 / scl_kHz); /* clock: 72MHz */ - b[6] = (u8) (divider >> 8); - b[7] = (u8) (divider & 0xff); + st->buf[6] = (u8) (divider >> 8); + st->buf[7] = (u8) (divider & 0xff); deb_info("setting I2C speed: %04x %04x %04x (%d kHz).", - (b[2] << 8) | (b[3]), (b[4] << 8) | b[5], (b[6] << 8) | b[7], scl_kHz); - return dib0700_ctrl_wr(d, b, 8); + (st->buf[2] << 8) | (st->buf[3]), (st->buf[4] << 8) | + st->buf[5], (st->buf[6] << 8) | st->buf[7], scl_kHz); + return dib0700_ctrl_wr(d, st->buf, 8); } @@ -364,32 +394,45 @@ int dib0700_ctrl_clock(struct dvb_usb_device *d, u32 clk_MHz, u8 clock_out_gp3) static int dib0700_jumpram(struct usb_device *udev, u32 address) { - int ret, actlen; - u8 buf[8] = { REQUEST_JUMPRAM, 0, 0, 0, - (address >> 24) & 0xff, - (address >> 16) & 0xff, - (address >> 8) & 0xff, - address & 0xff }; + int ret = 0, actlen; + u8 *buf; + + buf = kmalloc(8, GFP_KERNEL); + if (!buf) + return -ENOMEM; + buf[0] = REQUEST_JUMPRAM; + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + buf[4] = (address >> 24) & 0xff; + buf[5] = (address >> 16) & 0xff; + buf[6] = (address >> 8) & 0xff; + buf[7] = address & 0xff; if ((ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, 0x01),buf,8,&actlen,1000)) < 0) { deb_fw("jumpram to 0x%x failed\n",address); - return ret; + goto out; } if (actlen != 8) { deb_fw("jumpram to 0x%x failed\n",address); - return -EIO; + ret = -EIO; + goto out; } - return 0; +out: + kfree(buf); + return ret; } int dib0700_download_firmware(struct usb_device *udev, const struct firmware *fw) { struct hexline hx; int pos = 0, ret, act_len, i, adap_num; - u8 b[16]; + u8 *buf; u32 fw_version; - u8 buf[260]; + buf = kmalloc(260, GFP_KERNEL); + if (!buf) + return -ENOMEM; while ((ret = dvb_usb_get_hexline(fw, &hx, &pos)) > 0) { deb_fwdata("writing to address 0x%08x (buffer: 0x%02x %02x)\n", @@ -411,7 +454,7 @@ int dib0700_download_firmware(struct usb_device *udev, const struct firmware *fw if (ret < 0) { err("firmware download failed at %d with %d",pos,ret); - return ret; + goto out; } } @@ -432,8 +475,8 @@ int dib0700_download_firmware(struct usb_device *udev, const struct firmware *fw usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), REQUEST_GET_VERSION, USB_TYPE_VENDOR | USB_DIR_IN, 0, 0, - b, sizeof(b), USB_CTRL_GET_TIMEOUT); - fw_version = (b[8] << 24) | (b[9] << 16) | (b[10] << 8) | b[11]; + buf, 16, USB_CTRL_GET_TIMEOUT); + fw_version = (buf[8] << 24) | (buf[9] << 16) | (buf[10] << 8) | buf[11]; /* set the buffer size - DVB-USB is allocating URB buffers * only after the firwmare download was successful */ @@ -451,14 +494,14 @@ int dib0700_download_firmware(struct usb_device *udev, const struct firmware *fw } } } - +out: + kfree(buf); return ret; } int dib0700_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff) { struct dib0700_state *st = adap->dev->priv; - u8 b[4]; int ret; if ((onoff != 0) && (st->fw_version >= 0x10201)) { @@ -472,15 +515,17 @@ int dib0700_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff) } } - b[0] = REQUEST_ENABLE_VIDEO; - b[1] = (onoff << 4) | 0x00; /* this bit gives a kind of command, rather than enabling something or not */ + st->buf[0] = REQUEST_ENABLE_VIDEO; + /* this bit gives a kind of command, + * rather than enabling something or not */ + st->buf[1] = (onoff << 4) | 0x00; if (st->disable_streaming_master_mode == 1) - b[2] = 0x00; + st->buf[2] = 0x00; else - b[2] = 0x01 << 4; /* Master mode */ + st->buf[2] = 0x01 << 4; /* Master mode */ - b[3] = 0x00; + st->buf[3] = 0x00; deb_info("modifying (%d) streaming state for %d\n", onoff, adap->id); @@ -499,20 +544,23 @@ int dib0700_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff) st->channel_state |= 1 << (3-adap->stream.props.endpoint); } - b[2] |= st->channel_state; + st->buf[2] |= st->channel_state; - deb_info("data for streaming: %x %x\n", b[1], b[2]); + deb_info("data for streaming: %x %x\n", st->buf[1], st->buf[2]); - return dib0700_ctrl_wr(adap->dev, b, 4); + return dib0700_ctrl_wr(adap->dev, st->buf, 4); } int dib0700_change_protocol(struct rc_dev *rc, u64 rc_type) { struct dvb_usb_device *d = rc->priv; struct dib0700_state *st = d->priv; - u8 rc_setup[3] = { REQUEST_SET_RC, 0, 0 }; int new_proto, ret; + st->buf[0] = REQUEST_SET_RC; + st->buf[1] = 0; + st->buf[2] = 0; + /* Set the IR mode */ if (rc_type == RC_TYPE_RC5) new_proto = 1; @@ -526,9 +574,9 @@ int dib0700_change_protocol(struct rc_dev *rc, u64 rc_type) } else return -EINVAL; - rc_setup[1] = new_proto; + st->buf[1] = new_proto; - ret = dib0700_ctrl_wr(d, rc_setup, sizeof(rc_setup)); + ret = dib0700_ctrl_wr(d, st->buf, 3); if (ret < 0) { err("ir protocol setup failed"); return ret; -- cgit v1.2.3 From ca73877587abfb8213c8eb21fec4f7d2bca36069 Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Sun, 3 Apr 2011 14:23:43 -0300 Subject: [media] dib0700: remove unused variable This variable is never used. Signed-off-by: Florian Mickler <florian@mickler.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/dib0700_core.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/dib0700_core.c b/drivers/media/dvb/dvb-usb/dib0700_core.c index 0325825961b9..5eb91b4f8fd0 100644 --- a/drivers/media/dvb/dvb-usb/dib0700_core.c +++ b/drivers/media/dvb/dvb-usb/dib0700_core.c @@ -609,7 +609,6 @@ struct dib0700_rc_response { static void dib0700_rc_urb_completion(struct urb *purb) { struct dvb_usb_device *d = purb->context; - struct dib0700_state *st; struct dib0700_rc_response *poll_reply; u32 uninitialized_var(keycode); u8 toggle; @@ -624,7 +623,6 @@ static void dib0700_rc_urb_completion(struct urb *purb) return; } - st = d->priv; poll_reply = purb->transfer_buffer; if (purb->status < 0) { -- cgit v1.2.3 From 54f4e11ae3051ff7a921494be5106788db19dcf7 Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 15:33:41 -0300 Subject: [media] a800: get rid of on-stack dma buffers usb_control_msg initiates (and waits for completion of) a dma transfer using the supplied buffer. That buffer thus has to be seperately allocated on the heap. In lib/dma_debug.c the function check_for_stack even warns about it: WARNING: at lib/dma-debug.c:866 check_for_stack Note: This change is tested to compile only, as I don't have the hardware. Signed-off-by: Florian Mickler <florian@mickler.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/a800.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/a800.c b/drivers/media/dvb/dvb-usb/a800.c index f8e9bf116f21..b95a95e17840 100644 --- a/drivers/media/dvb/dvb-usb/a800.c +++ b/drivers/media/dvb/dvb-usb/a800.c @@ -78,17 +78,26 @@ static struct rc_map_table rc_map_a800_table[] = { static int a800_rc_query(struct dvb_usb_device *d, u32 *event, int *state) { - u8 key[5]; + int ret; + u8 *key = kmalloc(5, GFP_KERNEL); + if (!key) + return -ENOMEM; + if (usb_control_msg(d->udev,usb_rcvctrlpipe(d->udev,0), 0x04, USB_TYPE_VENDOR | USB_DIR_IN, 0, 0, key, 5, - 2000) != 5) - return -ENODEV; + 2000) != 5) { + ret = -ENODEV; + goto out; + } /* call the universal NEC remote processor, to find out the key's state and event */ dvb_usb_nec_rc_key_to_event(d,key,event,state); if (key[0] != 0) deb_rc("key: %x %x %x %x %x\n",key[0],key[1],key[2],key[3],key[4]); - return 0; + ret = 0; +out: + kfree(key); + return ret; } /* USB Driver stuff */ -- cgit v1.2.3 From ab22cbda6651db25d03052aa9ee9452b5eaa3edd Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 15:33:42 -0300 Subject: [media] vp7045: get rid of on-stack dma buffers Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/vp7045.c | 47 +++++++++++++++++++++++++++----------- 1 file changed, 34 insertions(+), 13 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/vp7045.c b/drivers/media/dvb/dvb-usb/vp7045.c index ab0ab3c35e80..3db89e3cb0bb 100644 --- a/drivers/media/dvb/dvb-usb/vp7045.c +++ b/drivers/media/dvb/dvb-usb/vp7045.c @@ -28,9 +28,9 @@ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); int vp7045_usb_op(struct dvb_usb_device *d, u8 cmd, u8 *out, int outlen, u8 *in, int inlen, int msec) { int ret = 0; - u8 inbuf[12] = { 0 }, outbuf[20] = { 0 }; + u8 *buf = d->priv; - outbuf[0] = cmd; + buf[0] = cmd; if (outlen > 19) outlen = 19; @@ -38,19 +38,21 @@ int vp7045_usb_op(struct dvb_usb_device *d, u8 cmd, u8 *out, int outlen, u8 *in, if (inlen > 11) inlen = 11; + ret = mutex_lock_interruptible(&d->usb_mutex); + if (ret) + return ret; + if (out != NULL && outlen > 0) - memcpy(&outbuf[1], out, outlen); + memcpy(&buf[1], out, outlen); deb_xfer("out buffer: "); - debug_dump(outbuf,outlen+1,deb_xfer); + debug_dump(buf, outlen+1, deb_xfer); - if ((ret = mutex_lock_interruptible(&d->usb_mutex))) - return ret; if (usb_control_msg(d->udev, usb_sndctrlpipe(d->udev,0), TH_COMMAND_OUT, USB_TYPE_VENDOR | USB_DIR_OUT, 0, 0, - outbuf, 20, 2000) != 20) { + buf, 20, 2000) != 20) { err("USB control message 'out' went wrong."); ret = -EIO; goto unlock; @@ -61,17 +63,17 @@ int vp7045_usb_op(struct dvb_usb_device *d, u8 cmd, u8 *out, int outlen, u8 *in, if (usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev,0), TH_COMMAND_IN, USB_TYPE_VENDOR | USB_DIR_IN, 0, 0, - inbuf, 12, 2000) != 12) { + buf, 12, 2000) != 12) { err("USB control message 'in' went wrong."); ret = -EIO; goto unlock; } deb_xfer("in buffer: "); - debug_dump(inbuf,12,deb_xfer); + debug_dump(buf, 12, deb_xfer); if (in != NULL && inlen > 0) - memcpy(in,&inbuf[1],inlen); + memcpy(in, &buf[1], inlen); unlock: mutex_unlock(&d->usb_mutex); @@ -222,8 +224,26 @@ static struct dvb_usb_device_properties vp7045_properties; static int vp7045_usb_probe(struct usb_interface *intf, const struct usb_device_id *id) { - return dvb_usb_device_init(intf, &vp7045_properties, - THIS_MODULE, NULL, adapter_nr); + struct dvb_usb_device *d; + int ret = dvb_usb_device_init(intf, &vp7045_properties, + THIS_MODULE, &d, adapter_nr); + if (ret) + return ret; + + d->priv = kmalloc(20, GFP_KERNEL); + if (!d->priv) { + dvb_usb_device_exit(intf); + return -ENOMEM; + } + + return ret; +} + +static void vp7045_usb_disconnect(struct usb_interface *intf) +{ + struct dvb_usb_device *d = usb_get_intfdata(intf); + kfree(d->priv); + dvb_usb_device_exit(intf); } static struct usb_device_id vp7045_usb_table [] = { @@ -238,6 +258,7 @@ MODULE_DEVICE_TABLE(usb, vp7045_usb_table); static struct dvb_usb_device_properties vp7045_properties = { .usb_ctrl = CYPRESS_FX2, .firmware = "dvb-usb-vp7045-01.fw", + .size_of_priv = sizeof(u8 *), .num_adapters = 1, .adapter = { @@ -284,7 +305,7 @@ static struct dvb_usb_device_properties vp7045_properties = { static struct usb_driver vp7045_usb_driver = { .name = "dvb_usb_vp7045", .probe = vp7045_usb_probe, - .disconnect = dvb_usb_device_exit, + .disconnect = vp7045_usb_disconnect, .id_table = vp7045_usb_table, }; -- cgit v1.2.3 From 0e4e7208e6b33816c457292ee771da3a5779027b Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 15:33:43 -0300 Subject: [media] friio: get rid of on-stack dma buffers usb_control_msg initiates (and waits for completion of) a dma transfer using the supplied buffer. That buffer thus has to be seperately allocated on the heap. In lib/dma_debug.c the function check_for_stack even warns about it: WARNING: at lib/dma-debug.c:866 check_for_stack Note: This change is tested to compile only, as I don't have the hardware. Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Akihiro Tsukada <tskd2@yahoo.co.jp> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/friio.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/friio.c b/drivers/media/dvb/dvb-usb/friio.c index 14a65b4aec07..76159aed9bb0 100644 --- a/drivers/media/dvb/dvb-usb/friio.c +++ b/drivers/media/dvb/dvb-usb/friio.c @@ -142,17 +142,20 @@ static u32 gl861_i2c_func(struct i2c_adapter *adapter) return I2C_FUNC_I2C; } - static int friio_ext_ctl(struct dvb_usb_adapter *adap, u32 sat_color, int lnb_on) { int i; int ret; struct i2c_msg msg; - u8 buf[2]; + u8 *buf; u32 mask; u8 lnb = (lnb_on) ? FRIIO_CTL_LNB : 0; + buf = kmalloc(2, GFP_KERNEL); + if (!buf) + return -ENOMEM; + msg.addr = 0x00; msg.flags = 0; msg.len = 2; @@ -189,6 +192,7 @@ static int friio_ext_ctl(struct dvb_usb_adapter *adap, buf[1] |= FRIIO_CTL_CLK; ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1); + kfree(buf); return (ret == 70); } @@ -219,11 +223,20 @@ static int friio_initialize(struct dvb_usb_device *d) int ret; int i; int retry = 0; - u8 rbuf[2]; - u8 wbuf[3]; + u8 *rbuf, *wbuf; deb_info("%s called.\n", __func__); + wbuf = kmalloc(3, GFP_KERNEL); + if (!wbuf) + return -ENOMEM; + + rbuf = kmalloc(2, GFP_KERNEL); + if (!rbuf) { + kfree(wbuf); + return -ENOMEM; + } + /* use gl861_i2c_msg instead of gl861_i2c_xfer(), */ /* because the i2c device is not set up yet. */ wbuf[0] = 0x11; @@ -358,6 +371,8 @@ restart: return 0; error: + kfree(wbuf); + kfree(rbuf); deb_info("%s:ret == %d\n", __func__, ret); return -EIO; } -- cgit v1.2.3 From b47b850116369a474f71c8ee1e7d06dfa9bf5468 Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 15:33:44 -0300 Subject: [media] dw2102: get rid of on-stack dma buffer usb_control_msg initiates (and waits for completion of) a dma transfer using the supplied buffer. That buffer thus has to be seperately allocated on the heap. In lib/dma_debug.c the function check_for_stack even warns about it: WARNING: at lib/dma-debug.c:866 check_for_stack Note: This change is tested to compile only, as I don't have the hardware. Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Igor M. Liplianin <liplianin@tut.by> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/dw2102.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/dw2102.c b/drivers/media/dvb/dvb-usb/dw2102.c index f5b9da18f611..5aabfbcb545b 100644 --- a/drivers/media/dvb/dvb-usb/dw2102.c +++ b/drivers/media/dvb/dvb-usb/dw2102.c @@ -121,12 +121,16 @@ static int dw210x_op_rw(struct usb_device *dev, u8 request, u16 value, u16 index, u8 * data, u16 len, int flags) { int ret; - u8 u8buf[len]; - + u8 *u8buf; unsigned int pipe = (flags == DW210X_READ_MSG) ? usb_rcvctrlpipe(dev, 0) : usb_sndctrlpipe(dev, 0); u8 request_type = (flags == DW210X_READ_MSG) ? USB_DIR_IN : USB_DIR_OUT; + u8buf = kmalloc(len, GFP_KERNEL); + if (!u8buf) + return -ENOMEM; + + if (flags == DW210X_WRITE_MSG) memcpy(u8buf, data, len); ret = usb_control_msg(dev, pipe, request, request_type | USB_TYPE_VENDOR, @@ -134,6 +138,8 @@ static int dw210x_op_rw(struct usb_device *dev, u8 request, u16 value, if (flags == DW210X_READ_MSG) memcpy(data, u8buf, len); + + kfree(u8buf); return ret; } -- cgit v1.2.3 From 513ea35ff9cd332abe650f5da3689bdb41824b43 Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 15:33:45 -0300 Subject: [media] m920x: get rid of on-stack dma buffers usb_control_msg initiates (and waits for completion of) a dma transfer using the supplied buffer. That buffer thus has to be seperately allocated on the heap. In lib/dma_debug.c the function check_for_stack even warns about it: WARNING: at lib/dma-debug.c:866 check_for_stack Note: This change is tested to compile only, as I don't have the hardware. Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Michael Krufky <mkrufky@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/m920x.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/m920x.c b/drivers/media/dvb/dvb-usb/m920x.c index 51bfd42387c2..9456792f219b 100644 --- a/drivers/media/dvb/dvb-usb/m920x.c +++ b/drivers/media/dvb/dvb-usb/m920x.c @@ -134,13 +134,17 @@ static int m920x_rc_query(struct dvb_usb_device *d, u32 *event, int *state) { struct m920x_state *m = d->priv; int i, ret = 0; - u8 rc_state[2]; + u8 *rc_state; + + rc_state = kmalloc(2, GFP_KERNEL); + if (!rc_state) + return -ENOMEM; if ((ret = m920x_read(d->udev, M9206_CORE, 0x0, M9206_RC_STATE, rc_state, 1)) != 0) - goto unlock; + goto out; if ((ret = m920x_read(d->udev, M9206_CORE, 0x0, M9206_RC_KEY, rc_state + 1, 1)) != 0) - goto unlock; + goto out; for (i = 0; i < d->props.rc.legacy.rc_map_size; i++) if (rc5_data(&d->props.rc.legacy.rc_map_table[i]) == rc_state[1]) { @@ -149,7 +153,7 @@ static int m920x_rc_query(struct dvb_usb_device *d, u32 *event, int *state) switch(rc_state[0]) { case 0x80: *state = REMOTE_NO_KEY_PRESSED; - goto unlock; + goto out; case 0x88: /* framing error or "invalid code" */ case 0x99: @@ -157,7 +161,7 @@ static int m920x_rc_query(struct dvb_usb_device *d, u32 *event, int *state) case 0xd8: *state = REMOTE_NO_KEY_PRESSED; m->rep_count = 0; - goto unlock; + goto out; case 0x93: case 0x92: @@ -165,7 +169,7 @@ static int m920x_rc_query(struct dvb_usb_device *d, u32 *event, int *state) case 0x82: m->rep_count = 0; *state = REMOTE_KEY_PRESSED; - goto unlock; + goto out; case 0x91: case 0x81: /* pinnacle PCTV310e */ @@ -174,12 +178,12 @@ static int m920x_rc_query(struct dvb_usb_device *d, u32 *event, int *state) *state = REMOTE_KEY_REPEAT; else *state = REMOTE_NO_KEY_PRESSED; - goto unlock; + goto out; default: deb("Unexpected rc state %02x\n", rc_state[0]); *state = REMOTE_NO_KEY_PRESSED; - goto unlock; + goto out; } } @@ -188,8 +192,8 @@ static int m920x_rc_query(struct dvb_usb_device *d, u32 *event, int *state) *state = REMOTE_NO_KEY_PRESSED; - unlock: - + out: + kfree(rc_state); return ret; } @@ -339,13 +343,19 @@ static int m920x_pid_filter(struct dvb_usb_adapter *adap, int index, u16 pid, in static int m920x_firmware_download(struct usb_device *udev, const struct firmware *fw) { u16 value, index, size; - u8 read[4], *buff; + u8 *read, *buff; int i, pass, ret = 0; buff = kmalloc(65536, GFP_KERNEL); if (buff == NULL) return -ENOMEM; + read = kmalloc(4, GFP_KERNEL); + if (!read) { + kfree(buff); + return -ENOMEM; + } + if ((ret = m920x_read(udev, M9206_FILTER, 0x0, 0x8000, read, 4)) != 0) goto done; deb("%x %x %x %x\n", read[0], read[1], read[2], read[3]); @@ -396,6 +406,7 @@ static int m920x_firmware_download(struct usb_device *udev, const struct firmwar deb("firmware uploaded!\n"); done: + kfree(read); kfree(buff); return ret; -- cgit v1.2.3 From 12fe2a6193df97b28f5ff9fd3f12d460e96c6a95 Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 15:33:46 -0300 Subject: [media] opera1: get rid of on-stack dma buffer usb_control_msg initiates (and waits for completion of) a dma transfer using the supplied buffer. That buffer thus has to be seperately allocated on the heap. In lib/dma_debug.c the function check_for_stack even warns about it: WARNING: at lib/dma-debug.c:866 check_for_stack Note: This change is tested to compile only, as I don't have the hardware. Signed-off-by: Florian Mickler <florian@mickler.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/opera1.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/opera1.c b/drivers/media/dvb/dvb-usb/opera1.c index 7e569f4dd80b..4258f127ea30 100644 --- a/drivers/media/dvb/dvb-usb/opera1.c +++ b/drivers/media/dvb/dvb-usb/opera1.c @@ -53,27 +53,36 @@ static int opera1_xilinx_rw(struct usb_device *dev, u8 request, u16 value, u8 * data, u16 len, int flags) { int ret; - u8 r; - u8 u8buf[len]; - + u8 tmp; + u8 *buf; unsigned int pipe = (flags == OPERA_READ_MSG) ? usb_rcvctrlpipe(dev,0) : usb_sndctrlpipe(dev, 0); u8 request_type = (flags == OPERA_READ_MSG) ? USB_DIR_IN : USB_DIR_OUT; + buf = kmalloc(len, GFP_KERNEL); + if (!buf) + return -ENOMEM; + if (flags == OPERA_WRITE_MSG) - memcpy(u8buf, data, len); - ret = - usb_control_msg(dev, pipe, request, request_type | USB_TYPE_VENDOR, - value, 0x0, u8buf, len, 2000); + memcpy(buf, data, len); + ret = usb_control_msg(dev, pipe, request, + request_type | USB_TYPE_VENDOR, value, 0x0, + buf, len, 2000); if (request == OPERA_TUNER_REQ) { + tmp = buf[0]; if (usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), - OPERA_TUNER_REQ, USB_DIR_IN | USB_TYPE_VENDOR, - 0x01, 0x0, &r, 1, 2000)<1 || r!=0x08) - return 0; + OPERA_TUNER_REQ, USB_DIR_IN | USB_TYPE_VENDOR, + 0x01, 0x0, buf, 1, 2000) < 1 || buf[0] != 0x08) { + ret = 0; + goto out; + } + buf[0] = tmp; } if (flags == OPERA_READ_MSG) - memcpy(data, u8buf, len); + memcpy(data, buf, len); +out: + kfree(buf); return ret; } -- cgit v1.2.3 From d30615d87e7bfbf610fae1cbee3fa509d1377edc Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 07:19:06 -0300 Subject: [media] vp702x: cleanup: whitespace and indentation Some whitespace, one linebreak and one unneded variable initialization... Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/vp702x.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/vp702x.c b/drivers/media/dvb/dvb-usb/vp702x.c index 7890e75600df..4c9939ffb720 100644 --- a/drivers/media/dvb/dvb-usb/vp702x.c +++ b/drivers/media/dvb/dvb-usb/vp702x.c @@ -36,14 +36,14 @@ struct vp702x_device_state { /* check for mutex FIXME */ int vp702x_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 *b, int blen) { - int ret = -1; + int ret; - ret = usb_control_msg(d->udev, - usb_rcvctrlpipe(d->udev,0), - req, - USB_TYPE_VENDOR | USB_DIR_IN, - value,index,b,blen, - 2000); + ret = usb_control_msg(d->udev, + usb_rcvctrlpipe(d->udev, 0), + req, + USB_TYPE_VENDOR | USB_DIR_IN, + value, index, b, blen, + 2000); if (ret < 0) { warn("usb in operation failed. (%d)", ret); @@ -221,7 +221,8 @@ static int vp702x_frontend_attach(struct dvb_usb_adapter *adap) vp702x_usb_out_op(adap->dev, SET_TUNER_POWER_REQ, 0, 7, NULL, 0); - if (vp702x_usb_inout_cmd(adap->dev, GET_SYSTEM_STRING, NULL, 0, buf, 10, 10)) + if (vp702x_usb_inout_cmd(adap->dev, GET_SYSTEM_STRING, NULL, 0, + buf, 10, 10)) return -EIO; buf[9] = '\0'; @@ -307,9 +308,9 @@ static struct dvb_usb_device_properties vp702x_properties = { /* usb specific object needed to register this driver with the usb subsystem */ static struct usb_driver vp702x_usb_driver = { .name = "dvb_usb_vp702x", - .probe = vp702x_usb_probe, - .disconnect = dvb_usb_device_exit, - .id_table = vp702x_usb_table, + .probe = vp702x_usb_probe, + .disconnect = dvb_usb_device_exit, + .id_table = vp702x_usb_table, }; /* module stuff */ -- cgit v1.2.3 From 36f773e8e3f207136a6b903b71754593e0e1819c Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 07:19:07 -0300 Subject: [media] vp702x: rename struct vp702x_state -> vp702x_adapter_state We need a state struct for the dvb_usb_device. In order to reduce confusion we rename the vp702x_state struct. Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/vp702x.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/vp702x.c b/drivers/media/dvb/dvb-usb/vp702x.c index 4c9939ffb720..25536f98c4d1 100644 --- a/drivers/media/dvb/dvb-usb/vp702x.c +++ b/drivers/media/dvb/dvb-usb/vp702x.c @@ -23,7 +23,7 @@ MODULE_PARM_DESC(debug, "set debugging level (1=info,xfer=2,rc=4 (or-able))." DV DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); -struct vp702x_state { +struct vp702x_adapter_state { int pid_filter_count; int pid_filter_can_bypass; u8 pid_filter_state; @@ -126,7 +126,7 @@ static int vp702x_set_pld_state(struct dvb_usb_adapter *adap, u8 state) static int vp702x_set_pid(struct dvb_usb_adapter *adap, u16 pid, u8 id, int onoff) { - struct vp702x_state *st = adap->priv; + struct vp702x_adapter_state *st = adap->priv; u8 buf[16] = { 0 }; if (onoff) @@ -147,7 +147,7 @@ static int vp702x_set_pid(struct dvb_usb_adapter *adap, u16 pid, u8 id, int onof static int vp702x_init_pid_filter(struct dvb_usb_adapter *adap) { - struct vp702x_state *st = adap->priv; + struct vp702x_adapter_state *st = adap->priv; int i; u8 b[10] = { 0 }; @@ -279,7 +279,7 @@ static struct dvb_usb_device_properties vp702x_properties = { } } }, - .size_of_priv = sizeof(struct vp702x_state), + .size_of_priv = sizeof(struct vp702x_adapter_state), } }, .read_mac_address = vp702x_read_mac_addr, -- cgit v1.2.3 From 1c6410f317c3e78409f0179283089034c77a6ad5 Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 07:19:08 -0300 Subject: [media] vp702x: preallocate memory on device probe This sets up a buffer and a mutex protecting that buffer in the struct vp702x_device_state. The definition of struct vp702x_device_state is moved into the header in order to use the buffer also in the frontend. Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/vp702x.c | 41 +++++++++++++++++++++++++++++++------- drivers/media/dvb/dvb-usb/vp702x.h | 8 ++++++++ 2 files changed, 42 insertions(+), 7 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/vp702x.c b/drivers/media/dvb/dvb-usb/vp702x.c index 25536f98c4d1..569c93fbb86c 100644 --- a/drivers/media/dvb/dvb-usb/vp702x.c +++ b/drivers/media/dvb/dvb-usb/vp702x.c @@ -15,6 +15,7 @@ * see Documentation/dvb/README.dvb-usb for more information */ #include "vp702x.h" +#include <linux/mutex.h> /* debug */ int dvb_usb_vp702x_debug; @@ -29,10 +30,6 @@ struct vp702x_adapter_state { u8 pid_filter_state; }; -struct vp702x_device_state { - u8 power_state; -}; - /* check for mutex FIXME */ int vp702x_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 *b, int blen) { @@ -241,8 +238,38 @@ static struct dvb_usb_device_properties vp702x_properties; static int vp702x_usb_probe(struct usb_interface *intf, const struct usb_device_id *id) { - return dvb_usb_device_init(intf, &vp702x_properties, - THIS_MODULE, NULL, adapter_nr); + struct dvb_usb_device *d; + struct vp702x_device_state *st; + int ret; + + ret = dvb_usb_device_init(intf, &vp702x_properties, + THIS_MODULE, &d, adapter_nr); + if (ret) + goto out; + + st = d->priv; + st->buf_len = 16; + st->buf = kmalloc(st->buf_len, GFP_KERNEL); + if (!st->buf) { + ret = -ENOMEM; + dvb_usb_device_exit(intf); + goto out; + } + mutex_init(&st->buf_mutex); + +out: + return ret; + +} + +static void vp702x_usb_disconnect(struct usb_interface *intf) +{ + struct dvb_usb_device *d = usb_get_intfdata(intf); + struct vp702x_device_state *st = d->priv; + mutex_lock(&st->buf_mutex); + kfree(st->buf); + mutex_unlock(&st->buf_mutex); + dvb_usb_device_exit(intf); } static struct usb_device_id vp702x_usb_table [] = { @@ -309,7 +336,7 @@ static struct dvb_usb_device_properties vp702x_properties = { static struct usb_driver vp702x_usb_driver = { .name = "dvb_usb_vp702x", .probe = vp702x_usb_probe, - .disconnect = dvb_usb_device_exit, + .disconnect = vp702x_usb_disconnect, .id_table = vp702x_usb_table, }; diff --git a/drivers/media/dvb/dvb-usb/vp702x.h b/drivers/media/dvb/dvb-usb/vp702x.h index c2f97f96c21f..86960c657522 100644 --- a/drivers/media/dvb/dvb-usb/vp702x.h +++ b/drivers/media/dvb/dvb-usb/vp702x.h @@ -98,6 +98,14 @@ extern int dvb_usb_vp702x_debug; #define RESET_TUNER 0xBE /* IN i: 0, v: 0, no extra buffer */ +struct vp702x_device_state { + u8 power_state; + struct mutex buf_mutex; + int buf_len; + u8 *buf; +}; + + extern struct dvb_frontend * vp702x_fe_attach(struct dvb_usb_device *d); extern int vp702x_usb_inout_op(struct dvb_usb_device *d, u8 *o, int olen, u8 *i, int ilen, int msec); -- cgit v1.2.3 From cf53b82d5d6eae920a1527b564f17c86e8118f0c Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 07:19:09 -0300 Subject: [media] vp702x: remove unused variable struct vp702x_device_state.power_state is nowhere referenced. Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/vp702x.h | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/vp702x.h b/drivers/media/dvb/dvb-usb/vp702x.h index 86960c657522..20b90055e7ac 100644 --- a/drivers/media/dvb/dvb-usb/vp702x.h +++ b/drivers/media/dvb/dvb-usb/vp702x.h @@ -99,7 +99,6 @@ extern int dvb_usb_vp702x_debug; /* IN i: 0, v: 0, no extra buffer */ struct vp702x_device_state { - u8 power_state; struct mutex buf_mutex; int buf_len; u8 *buf; -- cgit v1.2.3 From 57873c720caddf19eef2d5fe734575f7175abb48 Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 07:19:10 -0300 Subject: [media] vp702x: get rid of on-stack dma buffers usb_control_msg initiates (and waits for completion of) a dma transfer using the supplied buffer. That buffer thus has to be seperately allocated on the heap. In lib/dma_debug.c the function check_for_stack even warns about it: WARNING: at lib/dma-debug.c:866 check_for_stack Note: This change is tested to compile only, as I don't have the hardware. Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/vp702x-fe.c | 89 +++++++++++++++++++++++++---------- drivers/media/dvb/dvb-usb/vp702x.c | 78 +++++++++++++++++++++++------- 2 files changed, 124 insertions(+), 43 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/vp702x-fe.c b/drivers/media/dvb/dvb-usb/vp702x-fe.c index ccc7e4452664..7468a3839c5d 100644 --- a/drivers/media/dvb/dvb-usb/vp702x-fe.c +++ b/drivers/media/dvb/dvb-usb/vp702x-fe.c @@ -41,15 +41,26 @@ struct vp702x_fe_state { static int vp702x_fe_refresh_state(struct vp702x_fe_state *st) { - u8 buf[10]; - if (time_after(jiffies,st->next_status_check)) { - vp702x_usb_in_op(st->d,READ_STATUS,0,0,buf,10); - + u8 *buf; + + if (time_after(jiffies, st->next_status_check)) { + buf = kmalloc(10, GFP_KERNEL); + if (!buf) { + deb_fe("%s: buffer alloc failed\n", __func__); + return -ENOMEM; + } + vp702x_usb_in_op(st->d, READ_STATUS, 0, 0, buf, 10); st->lock = buf[4]; - vp702x_usb_in_op(st->d,READ_TUNER_REG_REQ,0x11,0,&st->snr,1); - vp702x_usb_in_op(st->d,READ_TUNER_REG_REQ,0x15,0,&st->sig,1); + + vp702x_usb_in_op(st->d, READ_TUNER_REG_REQ, 0x11, 0, buf, 1); + st->snr = buf[0]; + + vp702x_usb_in_op(st->d, READ_TUNER_REG_REQ, 0x15, 0, buf, 1); + st->sig = buf[0]; + st->next_status_check = jiffies + (st->status_check_interval*HZ)/1000; + kfree(buf); } return 0; } @@ -134,7 +145,11 @@ static int vp702x_fe_set_frontend(struct dvb_frontend* fe, /*CalFrequency*/ /* u16 frequencyRef[16] = { 2, 4, 8, 16, 32, 64, 128, 256, 24, 5, 10, 20, 40, 80, 160, 320 }; */ u64 sr; - u8 cmd[8] = { 0 },ibuf[10]; + u8 *cmd; + + cmd = kzalloc(10, GFP_KERNEL); + if (!cmd) + return -ENOMEM; cmd[0] = (freq >> 8) & 0x7f; cmd[1] = freq & 0xff; @@ -170,13 +185,14 @@ static int vp702x_fe_set_frontend(struct dvb_frontend* fe, st->status_check_interval = 250; st->next_status_check = jiffies; - vp702x_usb_inout_op(st->d,cmd,8,ibuf,10,100); + vp702x_usb_inout_op(st->d, cmd, 8, cmd, 10, 100); - if (ibuf[2] == 0 && ibuf[3] == 0) + if (cmd[2] == 0 && cmd[3] == 0) deb_fe("tuning failed.\n"); else deb_fe("tuning succeeded.\n"); + kfree(cmd); return 0; } @@ -204,28 +220,36 @@ static int vp702x_fe_get_frontend(struct dvb_frontend* fe, static int vp702x_fe_send_diseqc_msg (struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *m) { + int ret; + u8 *cmd; struct vp702x_fe_state *st = fe->demodulator_priv; - u8 cmd[8],ibuf[10]; - memset(cmd,0,8); + + cmd = kzalloc(10, GFP_KERNEL); + if (!cmd) + return -ENOMEM; deb_fe("%s\n",__func__); - if (m->msg_len > 4) - return -EINVAL; + if (m->msg_len > 4) { + ret = -EINVAL; + goto out; + } cmd[1] = SET_DISEQC_CMD; cmd[2] = m->msg_len; memcpy(&cmd[3], m->msg, m->msg_len); - cmd[7] = vp702x_chksum(cmd,0,7); + cmd[7] = vp702x_chksum(cmd, 0, 7); - vp702x_usb_inout_op(st->d,cmd,8,ibuf,10,100); + vp702x_usb_inout_op(st->d, cmd, 8, cmd, 10, 100); - if (ibuf[2] == 0 && ibuf[3] == 0) + if (cmd[2] == 0 && cmd[3] == 0) deb_fe("diseqc cmd failed.\n"); else deb_fe("diseqc cmd succeeded.\n"); - - return 0; + ret = 0; +out: + kfree(cmd); + return ret; } static int vp702x_fe_send_diseqc_burst (struct dvb_frontend* fe, fe_sec_mini_cmd_t burst) @@ -237,9 +261,14 @@ static int vp702x_fe_send_diseqc_burst (struct dvb_frontend* fe, fe_sec_mini_cmd static int vp702x_fe_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) { struct vp702x_fe_state *st = fe->demodulator_priv; - u8 ibuf[10]; + u8 *buf; + deb_fe("%s\n",__func__); + buf = kmalloc(10, GFP_KERNEL); + if (!buf) + return -ENOMEM; + st->tone_mode = tone; if (tone == SEC_TONE_ON) @@ -247,14 +276,16 @@ static int vp702x_fe_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) else st->lnb_buf[2] = 0x00; - st->lnb_buf[7] = vp702x_chksum(st->lnb_buf,0,7); + st->lnb_buf[7] = vp702x_chksum(st->lnb_buf, 0, 7); + memcpy(buf, st->lnb_buf, 8); - vp702x_usb_inout_op(st->d,st->lnb_buf,8,ibuf,10,100); - if (ibuf[2] == 0 && ibuf[3] == 0) + vp702x_usb_inout_op(st->d, buf, 8, buf, 10, 100); + if (buf[2] == 0 && buf[3] == 0) deb_fe("set_tone cmd failed.\n"); else deb_fe("set_tone cmd succeeded.\n"); + kfree(buf); return 0; } @@ -262,9 +293,13 @@ static int vp702x_fe_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage) { struct vp702x_fe_state *st = fe->demodulator_priv; - u8 ibuf[10]; + u8 *buf; deb_fe("%s\n",__func__); + buf = kmalloc(10, GFP_KERNEL); + if (!buf) + return -ENOMEM; + st->voltage = voltage; if (voltage != SEC_VOLTAGE_OFF) @@ -272,14 +307,16 @@ static int vp702x_fe_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t else st->lnb_buf[4] = 0x00; - st->lnb_buf[7] = vp702x_chksum(st->lnb_buf,0,7); + st->lnb_buf[7] = vp702x_chksum(st->lnb_buf, 0, 7); + memcpy(buf, st->lnb_buf, 8); - vp702x_usb_inout_op(st->d,st->lnb_buf,8,ibuf,10,100); - if (ibuf[2] == 0 && ibuf[3] == 0) + vp702x_usb_inout_op(st->d, buf, 8, buf, 10, 100); + if (buf[2] == 0 && buf[3] == 0) deb_fe("set_voltage cmd failed.\n"); else deb_fe("set_voltage cmd succeeded.\n"); + kfree(buf); return 0; } diff --git a/drivers/media/dvb/dvb-usb/vp702x.c b/drivers/media/dvb/dvb-usb/vp702x.c index 569c93fbb86c..35fe778993c1 100644 --- a/drivers/media/dvb/dvb-usb/vp702x.c +++ b/drivers/media/dvb/dvb-usb/vp702x.c @@ -93,38 +93,61 @@ int vp702x_usb_inout_op(struct dvb_usb_device *d, u8 *o, int olen, u8 *i, int il static int vp702x_usb_inout_cmd(struct dvb_usb_device *d, u8 cmd, u8 *o, int olen, u8 *i, int ilen, int msec) { - u8 bout[olen+2]; - u8 bin[ilen+1]; int ret = 0; + u8 *buf; + int buflen = max(olen + 2, ilen + 1); - bout[0] = 0x00; - bout[1] = cmd; - memcpy(&bout[2],o,olen); + buf = kmalloc(buflen, GFP_KERNEL); + if (!buf) + return -ENOMEM; - ret = vp702x_usb_inout_op(d, bout, olen+2, bin, ilen+1,msec); + buf[0] = 0x00; + buf[1] = cmd; + memcpy(&buf[2], o, olen); + + ret = vp702x_usb_inout_op(d, buf, olen+2, buf, ilen+1, msec); if (ret == 0) - memcpy(i,&bin[1],ilen); + memcpy(i, &buf[1], ilen); + kfree(buf); return ret; } static int vp702x_set_pld_mode(struct dvb_usb_adapter *adap, u8 bypass) { - u8 buf[16] = { 0 }; - return vp702x_usb_in_op(adap->dev, 0xe0, (bypass << 8) | 0x0e, 0, buf, 16); + int ret; + u8 *buf = kzalloc(16, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + ret = vp702x_usb_in_op(adap->dev, 0xe0, (bypass << 8) | 0x0e, + 0, buf, 16); + kfree(buf); + return ret; } static int vp702x_set_pld_state(struct dvb_usb_adapter *adap, u8 state) { - u8 buf[16] = { 0 }; - return vp702x_usb_in_op(adap->dev, 0xe0, (state << 8) | 0x0f, 0, buf, 16); + int ret; + u8 *buf = kzalloc(16, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + ret = vp702x_usb_in_op(adap->dev, 0xe0, (state << 8) | 0x0f, + 0, buf, 16); + kfree(buf); + return ret; } static int vp702x_set_pid(struct dvb_usb_adapter *adap, u16 pid, u8 id, int onoff) { struct vp702x_adapter_state *st = adap->priv; - u8 buf[16] = { 0 }; + u8 *buf; + + buf = kzalloc(16, GFP_KERNEL); + if (!buf) + return -ENOMEM; if (onoff) st->pid_filter_state |= (1 << id); @@ -138,6 +161,8 @@ static int vp702x_set_pid(struct dvb_usb_adapter *adap, u16 pid, u8 id, int onof vp702x_set_pld_state(adap, st->pid_filter_state); vp702x_usb_in_op(adap->dev, 0xe0, (((pid >> 8) & 0xff) << 8) | (id), 0, buf, 16); vp702x_usb_in_op(adap->dev, 0xe0, (((pid ) & 0xff) << 8) | (id+1), 0, buf, 16); + + kfree(buf); return 0; } @@ -146,13 +171,17 @@ static int vp702x_init_pid_filter(struct dvb_usb_adapter *adap) { struct vp702x_adapter_state *st = adap->priv; int i; - u8 b[10] = { 0 }; + u8 *b; + + b = kzalloc(10, GFP_KERNEL); + if (!b) + return -ENOMEM; st->pid_filter_count = 8; st->pid_filter_can_bypass = 1; st->pid_filter_state = 0x00; - vp702x_set_pld_mode(adap, 1); // bypass + vp702x_set_pld_mode(adap, 1); /* bypass */ for (i = 0; i < st->pid_filter_count; i++) vp702x_set_pid(adap, 0xffff, i, 1); @@ -162,6 +191,7 @@ static int vp702x_init_pid_filter(struct dvb_usb_adapter *adap) vp702x_usb_in_op(adap->dev, 0xb5, 1, 0, b, 10); //vp702x_set_pld_mode(d, 0); // filter + kfree(b); return 0; } @@ -179,18 +209,23 @@ static struct rc_map_table rc_map_vp702x_table[] = { /* remote control stuff (does not work with my box) */ static int vp702x_rc_query(struct dvb_usb_device *d, u32 *event, int *state) { - u8 key[10]; + u8 *key; int i; /* remove the following return to enabled remote querying */ return 0; + key = kmalloc(10, GFP_KERNEL); + if (!key) + return -ENOMEM; + vp702x_usb_in_op(d,READ_REMOTE_REQ,0,0,key,10); deb_rc("remote query key: %x %d\n",key[1],key[1]); if (key[1] == 0x44) { *state = REMOTE_NO_KEY_PRESSED; + kfree(key); return 0; } @@ -200,15 +235,24 @@ static int vp702x_rc_query(struct dvb_usb_device *d, u32 *event, int *state) *event = rc_map_vp702x_table[i].keycode; break; } + kfree(key); return 0; } static int vp702x_read_mac_addr(struct dvb_usb_device *d,u8 mac[6]) { - u8 i; + u8 i, *buf; + + buf = kmalloc(6, GFP_KERNEL); + if (!buf) + return -ENOMEM; + for (i = 6; i < 12; i++) - vp702x_usb_in_op(d, READ_EEPROM_REQ, i, 1, &mac[i - 6], 1); + vp702x_usb_in_op(d, READ_EEPROM_REQ, i, 1, &buf[i - 6], 1); + + memcpy(mac, buf, 6); + kfree(buf); return 0; } -- cgit v1.2.3 From 9a187c4183edb6e705245c0fb2439aa3e8dce1fe Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 07:19:11 -0300 Subject: [media] vp702x: fix locking of usb operations Otherwise it is not obvious that vp702x_usb_in_op or vp702x_usb_out_op will not interfere with any vp702x_usb_inout_op. Note: This change is tested to compile only, as I don't have the hardware. Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/vp702x.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/vp702x.c b/drivers/media/dvb/dvb-usb/vp702x.c index 35fe778993c1..c82cb6b3a27d 100644 --- a/drivers/media/dvb/dvb-usb/vp702x.c +++ b/drivers/media/dvb/dvb-usb/vp702x.c @@ -30,8 +30,8 @@ struct vp702x_adapter_state { u8 pid_filter_state; }; -/* check for mutex FIXME */ -int vp702x_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 *b, int blen) +static int vp702x_usb_in_op_unlocked(struct dvb_usb_device *d, u8 req, + u16 value, u16 index, u8 *b, int blen) { int ret; @@ -55,8 +55,20 @@ int vp702x_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 return ret; } -static int vp702x_usb_out_op(struct dvb_usb_device *d, u8 req, u16 value, - u16 index, u8 *b, int blen) +int vp702x_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, + u16 index, u8 *b, int blen) +{ + int ret; + + mutex_lock(&d->usb_mutex); + ret = vp702x_usb_in_op_unlocked(d, req, value, index, b, blen); + mutex_unlock(&d->usb_mutex); + + return ret; +} + +int vp702x_usb_out_op_unlocked(struct dvb_usb_device *d, u8 req, u16 value, + u16 index, u8 *b, int blen) { int ret; deb_xfer("out: req. %02x, val: %04x, ind: %04x, buffer: ",req,value,index); @@ -74,6 +86,18 @@ static int vp702x_usb_out_op(struct dvb_usb_device *d, u8 req, u16 value, return 0; } +int vp702x_usb_out_op(struct dvb_usb_device *d, u8 req, u16 value, + u16 index, u8 *b, int blen) +{ + int ret; + + mutex_lock(&d->usb_mutex); + ret = vp702x_usb_out_op_unlocked(d, req, value, index, b, blen); + mutex_unlock(&d->usb_mutex); + + return ret; +} + int vp702x_usb_inout_op(struct dvb_usb_device *d, u8 *o, int olen, u8 *i, int ilen, int msec) { int ret; @@ -81,12 +105,11 @@ int vp702x_usb_inout_op(struct dvb_usb_device *d, u8 *o, int olen, u8 *i, int il if ((ret = mutex_lock_interruptible(&d->usb_mutex))) return ret; - ret = vp702x_usb_out_op(d,REQUEST_OUT,0,0,o,olen); + ret = vp702x_usb_out_op_unlocked(d, REQUEST_OUT, 0, 0, o, olen); msleep(msec); - ret = vp702x_usb_in_op(d,REQUEST_IN,0,0,i,ilen); + ret = vp702x_usb_in_op_unlocked(d, REQUEST_IN, 0, 0, i, ilen); mutex_unlock(&d->usb_mutex); - return ret; } -- cgit v1.2.3 From 8ea793aa736137aa2453ce6877bb31a4b15dc28d Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 07:19:12 -0300 Subject: [media] vp702x: use preallocated buffer Note: This change is tested to compile only as I don't have the hardware. Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/vp702x.c | 59 ++++++++++++++++++++++---------------- 1 file changed, 35 insertions(+), 24 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/vp702x.c b/drivers/media/dvb/dvb-usb/vp702x.c index c82cb6b3a27d..6dd50bc8418e 100644 --- a/drivers/media/dvb/dvb-usb/vp702x.c +++ b/drivers/media/dvb/dvb-usb/vp702x.c @@ -140,38 +140,44 @@ static int vp702x_usb_inout_cmd(struct dvb_usb_device *d, u8 cmd, u8 *o, static int vp702x_set_pld_mode(struct dvb_usb_adapter *adap, u8 bypass) { int ret; - u8 *buf = kzalloc(16, GFP_KERNEL); - if (!buf) - return -ENOMEM; + struct vp702x_device_state *st = adap->dev->priv; + u8 *buf; + + mutex_lock(&st->buf_mutex); + + buf = st->buf; + memset(buf, 0, 16); ret = vp702x_usb_in_op(adap->dev, 0xe0, (bypass << 8) | 0x0e, 0, buf, 16); - kfree(buf); + mutex_unlock(&st->buf_mutex); return ret; } static int vp702x_set_pld_state(struct dvb_usb_adapter *adap, u8 state) { int ret; - u8 *buf = kzalloc(16, GFP_KERNEL); - if (!buf) - return -ENOMEM; + struct vp702x_device_state *st = adap->dev->priv; + u8 *buf; + + mutex_lock(&st->buf_mutex); + buf = st->buf; + memset(buf, 0, 16); ret = vp702x_usb_in_op(adap->dev, 0xe0, (state << 8) | 0x0f, 0, buf, 16); - kfree(buf); + + mutex_unlock(&st->buf_mutex); + return ret; } static int vp702x_set_pid(struct dvb_usb_adapter *adap, u16 pid, u8 id, int onoff) { struct vp702x_adapter_state *st = adap->priv; + struct vp702x_device_state *dst = adap->dev->priv; u8 *buf; - buf = kzalloc(16, GFP_KERNEL); - if (!buf) - return -ENOMEM; - if (onoff) st->pid_filter_state |= (1 << id); else { @@ -182,10 +188,16 @@ static int vp702x_set_pid(struct dvb_usb_adapter *adap, u16 pid, u8 id, int onof id = 0x10 + id*2; vp702x_set_pld_state(adap, st->pid_filter_state); + + mutex_lock(&dst->buf_mutex); + + buf = dst->buf; + memset(buf, 0, 16); vp702x_usb_in_op(adap->dev, 0xe0, (((pid >> 8) & 0xff) << 8) | (id), 0, buf, 16); vp702x_usb_in_op(adap->dev, 0xe0, (((pid ) & 0xff) << 8) | (id+1), 0, buf, 16); - kfree(buf); + mutex_unlock(&dst->buf_mutex); + return 0; } @@ -193,13 +205,10 @@ static int vp702x_set_pid(struct dvb_usb_adapter *adap, u16 pid, u8 id, int onof static int vp702x_init_pid_filter(struct dvb_usb_adapter *adap) { struct vp702x_adapter_state *st = adap->priv; + struct vp702x_device_state *dst = adap->dev->priv; int i; u8 *b; - b = kzalloc(10, GFP_KERNEL); - if (!b) - return -ENOMEM; - st->pid_filter_count = 8; st->pid_filter_can_bypass = 1; st->pid_filter_state = 0x00; @@ -209,12 +218,15 @@ static int vp702x_init_pid_filter(struct dvb_usb_adapter *adap) for (i = 0; i < st->pid_filter_count; i++) vp702x_set_pid(adap, 0xffff, i, 1); + mutex_lock(&dst->buf_mutex); + b = dst->buf; + memset(b, 0, 10); vp702x_usb_in_op(adap->dev, 0xb5, 3, 0, b, 10); vp702x_usb_in_op(adap->dev, 0xb5, 0, 0, b, 10); vp702x_usb_in_op(adap->dev, 0xb5, 1, 0, b, 10); + mutex_unlock(&dst->buf_mutex); + /*vp702x_set_pld_mode(d, 0); // filter */ - //vp702x_set_pld_mode(d, 0); // filter - kfree(b); return 0; } @@ -266,16 +278,15 @@ static int vp702x_rc_query(struct dvb_usb_device *d, u32 *event, int *state) static int vp702x_read_mac_addr(struct dvb_usb_device *d,u8 mac[6]) { u8 i, *buf; + struct vp702x_device_state *st = d->priv; - buf = kmalloc(6, GFP_KERNEL); - if (!buf) - return -ENOMEM; - + mutex_lock(&st->buf_mutex); + buf = st->buf; for (i = 6; i < 12; i++) vp702x_usb_in_op(d, READ_EEPROM_REQ, i, 1, &buf[i - 6], 1); memcpy(mac, buf, 6); - kfree(buf); + mutex_unlock(&st->buf_mutex); return 0; } -- cgit v1.2.3 From ee52f120b0adc469f5c67815cef79ecdd01cfd14 Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 07:19:13 -0300 Subject: [media] vp702x: use preallocated buffer in vp702x_usb_inout_cmd If we need a bigger buffer, we reallocte a new buffer and free the old one. Note: This change is tested to compile only as I don't have the hardware. Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/vp702x.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/vp702x.c b/drivers/media/dvb/dvb-usb/vp702x.c index 6dd50bc8418e..54355f84a98f 100644 --- a/drivers/media/dvb/dvb-usb/vp702x.c +++ b/drivers/media/dvb/dvb-usb/vp702x.c @@ -116,13 +116,28 @@ int vp702x_usb_inout_op(struct dvb_usb_device *d, u8 *o, int olen, u8 *i, int il static int vp702x_usb_inout_cmd(struct dvb_usb_device *d, u8 cmd, u8 *o, int olen, u8 *i, int ilen, int msec) { + struct vp702x_device_state *st = d->priv; int ret = 0; u8 *buf; int buflen = max(olen + 2, ilen + 1); - buf = kmalloc(buflen, GFP_KERNEL); - if (!buf) - return -ENOMEM; + ret = mutex_lock_interruptible(&st->buf_mutex); + if (ret < 0) + return ret; + + if (buflen > st->buf_len) { + buf = kmalloc(buflen, GFP_KERNEL); + if (!buf) { + mutex_unlock(&st->buf_mutex); + return -ENOMEM; + } + info("successfully reallocated a bigger buffer"); + kfree(st->buf); + st->buf = buf; + st->buf_len = buflen; + } else { + buf = st->buf; + } buf[0] = 0x00; buf[1] = cmd; @@ -132,8 +147,8 @@ static int vp702x_usb_inout_cmd(struct dvb_usb_device *d, u8 cmd, u8 *o, if (ret == 0) memcpy(i, &buf[1], ilen); + mutex_unlock(&st->buf_mutex); - kfree(buf); return ret; } -- cgit v1.2.3 From 60f81f12fa63213567b0b40546faa82b8f5d5b0c Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Mon, 21 Mar 2011 07:19:14 -0300 Subject: [media] vp702x: use preallocated buffer in the frontend Note: This change is tested to compile only as I don't have the hardware. Signed-off-by: Florian Mickler <florian@mickler.org> Cc: Patrick Boettcher <pb@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/vp702x-fe.c | 69 ++++++++++++++++++----------------- 1 file changed, 35 insertions(+), 34 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/vp702x-fe.c b/drivers/media/dvb/dvb-usb/vp702x-fe.c index 7468a3839c5d..2bb8d4cc8d88 100644 --- a/drivers/media/dvb/dvb-usb/vp702x-fe.c +++ b/drivers/media/dvb/dvb-usb/vp702x-fe.c @@ -41,14 +41,13 @@ struct vp702x_fe_state { static int vp702x_fe_refresh_state(struct vp702x_fe_state *st) { + struct vp702x_device_state *dst = st->d->priv; u8 *buf; if (time_after(jiffies, st->next_status_check)) { - buf = kmalloc(10, GFP_KERNEL); - if (!buf) { - deb_fe("%s: buffer alloc failed\n", __func__); - return -ENOMEM; - } + mutex_lock(&dst->buf_mutex); + buf = dst->buf; + vp702x_usb_in_op(st->d, READ_STATUS, 0, 0, buf, 10); st->lock = buf[4]; @@ -58,9 +57,8 @@ static int vp702x_fe_refresh_state(struct vp702x_fe_state *st) vp702x_usb_in_op(st->d, READ_TUNER_REG_REQ, 0x15, 0, buf, 1); st->sig = buf[0]; - + mutex_unlock(&dst->buf_mutex); st->next_status_check = jiffies + (st->status_check_interval*HZ)/1000; - kfree(buf); } return 0; } @@ -141,15 +139,17 @@ static int vp702x_fe_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep) { struct vp702x_fe_state *st = fe->demodulator_priv; + struct vp702x_device_state *dst = st->d->priv; u32 freq = fep->frequency/1000; /*CalFrequency*/ /* u16 frequencyRef[16] = { 2, 4, 8, 16, 32, 64, 128, 256, 24, 5, 10, 20, 40, 80, 160, 320 }; */ u64 sr; u8 *cmd; - cmd = kzalloc(10, GFP_KERNEL); - if (!cmd) - return -ENOMEM; + mutex_lock(&dst->buf_mutex); + + cmd = dst->buf; + memset(cmd, 0, 10); cmd[0] = (freq >> 8) & 0x7f; cmd[1] = freq & 0xff; @@ -192,7 +192,8 @@ static int vp702x_fe_set_frontend(struct dvb_frontend* fe, else deb_fe("tuning succeeded.\n"); - kfree(cmd); + mutex_unlock(&dst->buf_mutex); + return 0; } @@ -220,21 +221,18 @@ static int vp702x_fe_get_frontend(struct dvb_frontend* fe, static int vp702x_fe_send_diseqc_msg (struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *m) { - int ret; u8 *cmd; struct vp702x_fe_state *st = fe->demodulator_priv; - - cmd = kzalloc(10, GFP_KERNEL); - if (!cmd) - return -ENOMEM; + struct vp702x_device_state *dst = st->d->priv; deb_fe("%s\n",__func__); - if (m->msg_len > 4) { - ret = -EINVAL; - goto out; - } + if (m->msg_len > 4) + return -EINVAL; + + mutex_lock(&dst->buf_mutex); + cmd = dst->buf; cmd[1] = SET_DISEQC_CMD; cmd[2] = m->msg_len; memcpy(&cmd[3], m->msg, m->msg_len); @@ -246,10 +244,10 @@ static int vp702x_fe_send_diseqc_msg (struct dvb_frontend* fe, deb_fe("diseqc cmd failed.\n"); else deb_fe("diseqc cmd succeeded.\n"); - ret = 0; -out: - kfree(cmd); - return ret; + + mutex_unlock(&dst->buf_mutex); + + return 0; } static int vp702x_fe_send_diseqc_burst (struct dvb_frontend* fe, fe_sec_mini_cmd_t burst) @@ -261,14 +259,11 @@ static int vp702x_fe_send_diseqc_burst (struct dvb_frontend* fe, fe_sec_mini_cmd static int vp702x_fe_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) { struct vp702x_fe_state *st = fe->demodulator_priv; + struct vp702x_device_state *dst = st->d->priv; u8 *buf; deb_fe("%s\n",__func__); - buf = kmalloc(10, GFP_KERNEL); - if (!buf) - return -ENOMEM; - st->tone_mode = tone; if (tone == SEC_TONE_ON) @@ -277,6 +272,10 @@ static int vp702x_fe_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) st->lnb_buf[2] = 0x00; st->lnb_buf[7] = vp702x_chksum(st->lnb_buf, 0, 7); + + mutex_lock(&dst->buf_mutex); + + buf = dst->buf; memcpy(buf, st->lnb_buf, 8); vp702x_usb_inout_op(st->d, buf, 8, buf, 10, 100); @@ -285,7 +284,8 @@ static int vp702x_fe_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) else deb_fe("set_tone cmd succeeded.\n"); - kfree(buf); + mutex_unlock(&dst->buf_mutex); + return 0; } @@ -293,13 +293,10 @@ static int vp702x_fe_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage) { struct vp702x_fe_state *st = fe->demodulator_priv; + struct vp702x_device_state *dst = st->d->priv; u8 *buf; deb_fe("%s\n",__func__); - buf = kmalloc(10, GFP_KERNEL); - if (!buf) - return -ENOMEM; - st->voltage = voltage; if (voltage != SEC_VOLTAGE_OFF) @@ -308,6 +305,10 @@ static int vp702x_fe_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t st->lnb_buf[4] = 0x00; st->lnb_buf[7] = vp702x_chksum(st->lnb_buf, 0, 7); + + mutex_lock(&dst->buf_mutex); + + buf = dst->buf; memcpy(buf, st->lnb_buf, 8); vp702x_usb_inout_op(st->d, buf, 8, buf, 10, 100); @@ -316,7 +317,7 @@ static int vp702x_fe_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t else deb_fe("set_voltage cmd succeeded.\n"); - kfree(buf); + mutex_unlock(&dst->buf_mutex); return 0; } -- cgit v1.2.3 From 26b72c6e5a67ceef4c62c279d5952f723515d990 Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Sun, 20 Mar 2011 18:50:48 -0300 Subject: [media] ec168: get rid of on-stack dma buffers usb_control_msg initiates (and waits for completion of) a dma transfer using the supplied buffer. That buffer thus has to be seperately allocated on the heap. In lib/dma_debug.c the function check_for_stack even warns about it: WARNING: at lib/dma-debug.c:866 check_for_stack Signed-off-by: Florian Mickler <florian@mickler.org> Acked-by: Antti Palosaari <crope@iki.fi> Reviewed-by: Antti Palosaari <crope@iki.fi> Tested-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/ec168.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/ec168.c b/drivers/media/dvb/dvb-usb/ec168.c index 52f5d4f0f230..1ba3e5dbee10 100644 --- a/drivers/media/dvb/dvb-usb/ec168.c +++ b/drivers/media/dvb/dvb-usb/ec168.c @@ -36,7 +36,9 @@ static int ec168_rw_udev(struct usb_device *udev, struct ec168_req *req) int ret; unsigned int pipe; u8 request, requesttype; - u8 buf[req->size]; + u8 *buf; + + switch (req->cmd) { case DOWNLOAD_FIRMWARE: @@ -72,6 +74,12 @@ static int ec168_rw_udev(struct usb_device *udev, struct ec168_req *req) goto error; } + buf = kmalloc(req->size, GFP_KERNEL); + if (!buf) { + ret = -ENOMEM; + goto error; + } + if (requesttype == (USB_TYPE_VENDOR | USB_DIR_OUT)) { /* write */ memcpy(buf, req->data, req->size); @@ -84,13 +92,13 @@ static int ec168_rw_udev(struct usb_device *udev, struct ec168_req *req) msleep(1); /* avoid I2C errors */ ret = usb_control_msg(udev, pipe, request, requesttype, req->value, - req->index, buf, sizeof(buf), EC168_USB_TIMEOUT); + req->index, buf, req->size, EC168_USB_TIMEOUT); ec168_debug_dump(request, requesttype, req->value, req->index, buf, req->size, deb_xfer); if (ret < 0) - goto error; + goto err_dealloc; else ret = 0; @@ -98,7 +106,11 @@ static int ec168_rw_udev(struct usb_device *udev, struct ec168_req *req) if (!ret && requesttype == (USB_TYPE_VENDOR | USB_DIR_IN)) memcpy(req->data, buf, req->size); + kfree(buf); return ret; + +err_dealloc: + kfree(buf); error: deb_info("%s: failed:%d\n", __func__, ret); return ret; -- cgit v1.2.3 From 029461dbea04f4b6943bd24b6ae7906f28593a2f Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Sun, 20 Mar 2011 18:50:49 -0300 Subject: [media] ce6230: get rid of on-stack dma buffer usb_control_msg initiates (and waits for completion of) a dma transfer using the supplied buffer. That buffer thus has to be seperately allocated on the heap. In lib/dma_debug.c the function check_for_stack even warns about it: WARNING: at lib/dma-debug.c:866 check_for_stack Signed-off-by: Florian Mickler <florian@mickler.org> Acked-by: Antti Palosaari <crope@iki.fi> Reviewed-by: Antti Palosaari <crope@iki.fi> Tested-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/ce6230.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/ce6230.c b/drivers/media/dvb/dvb-usb/ce6230.c index 3df2045b7d2d..6d1a3041540d 100644 --- a/drivers/media/dvb/dvb-usb/ce6230.c +++ b/drivers/media/dvb/dvb-usb/ce6230.c @@ -39,7 +39,7 @@ static int ce6230_rw_udev(struct usb_device *udev, struct req_t *req) u8 requesttype; u16 value; u16 index; - u8 buf[req->data_len]; + u8 *buf; request = req->cmd; value = req->value; @@ -62,6 +62,12 @@ static int ce6230_rw_udev(struct usb_device *udev, struct req_t *req) goto error; } + buf = kmalloc(req->data_len, GFP_KERNEL); + if (!buf) { + ret = -ENOMEM; + goto error; + } + if (requesttype == (USB_TYPE_VENDOR | USB_DIR_OUT)) { /* write */ memcpy(buf, req->data, req->data_len); @@ -74,7 +80,7 @@ static int ce6230_rw_udev(struct usb_device *udev, struct req_t *req) msleep(1); /* avoid I2C errors */ ret = usb_control_msg(udev, pipe, request, requesttype, value, index, - buf, sizeof(buf), CE6230_USB_TIMEOUT); + buf, req->data_len, CE6230_USB_TIMEOUT); ce6230_debug_dump(request, requesttype, value, index, buf, req->data_len, deb_xfer); @@ -88,6 +94,7 @@ static int ce6230_rw_udev(struct usb_device *udev, struct req_t *req) if (!ret && requesttype == (USB_TYPE_VENDOR | USB_DIR_IN)) memcpy(req->data, buf, req->data_len); + kfree(buf); error: return ret; } -- cgit v1.2.3 From 2a596f84e2e368a3167947b32c8ea51125f87c58 Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Sun, 20 Mar 2011 18:50:50 -0300 Subject: [media] au6610: get rid of on-stack dma buffer usb_control_msg initiates (and waits for completion of) a dma transfer using the supplied buffer. That buffer thus has to be seperately allocated on the heap. In lib/dma_debug.c the function check_for_stack even warns about it: WARNING: at lib/dma-debug.c:866 check_for_stack Signed-off-by: Florian Mickler <florian@mickler.org> Acked-by: Antti Palosaari <crope@iki.fi> Reviewed-by: Antti Palosaari <crope@iki.fi> Tested-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/au6610.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/au6610.c b/drivers/media/dvb/dvb-usb/au6610.c index eb34cc3894e0..2351077ff2b3 100644 --- a/drivers/media/dvb/dvb-usb/au6610.c +++ b/drivers/media/dvb/dvb-usb/au6610.c @@ -33,8 +33,16 @@ static int au6610_usb_msg(struct dvb_usb_device *d, u8 operation, u8 addr, { int ret; u16 index; - u8 usb_buf[6]; /* enough for all known requests, - read returns 5 and write 6 bytes */ + u8 *usb_buf; + + /* + * allocate enough for all known requests, + * read returns 5 and write 6 bytes + */ + usb_buf = kmalloc(6, GFP_KERNEL); + if (!usb_buf) + return -ENOMEM; + switch (wlen) { case 1: index = wbuf[0] << 8; @@ -45,14 +53,15 @@ static int au6610_usb_msg(struct dvb_usb_device *d, u8 operation, u8 addr, break; default: warn("wlen = %x, aborting.", wlen); - return -EINVAL; + ret = -EINVAL; + goto error; } ret = usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev, 0), operation, USB_TYPE_VENDOR|USB_DIR_IN, addr << 1, index, - usb_buf, sizeof(usb_buf), AU6610_USB_TIMEOUT); + usb_buf, 6, AU6610_USB_TIMEOUT); if (ret < 0) - return ret; + goto error; switch (operation) { case AU6610_REQ_I2C_READ: @@ -60,7 +69,8 @@ static int au6610_usb_msg(struct dvb_usb_device *d, u8 operation, u8 addr, /* requested value is always 5th byte in buffer */ rbuf[0] = usb_buf[4]; } - +error: + kfree(usb_buf); return ret; } -- cgit v1.2.3 From 945b876600054081911d31bdb4f47b172c8a48ae Mon Sep 17 00:00:00 2001 From: Florian Mickler <florian@mickler.org> Date: Sun, 20 Mar 2011 18:50:52 -0300 Subject: [media] lmedm04: get rid of on-stack dma buffers usb_control_msg initiates (and waits for completion of) a dma transfer using the supplied buffer. That buffer thus has to be seperately allocated on the heap. In lib/dma_debug.c the function check_for_stack even warns about it: WARNING: at lib/dma-debug.c:866 check_for_stack Tested-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Florian Mickler <florian@mickler.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/lmedm04.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/lmedm04.c b/drivers/media/dvb/dvb-usb/lmedm04.c index b47ec3055ff7..a4457e4c1246 100644 --- a/drivers/media/dvb/dvb-usb/lmedm04.c +++ b/drivers/media/dvb/dvb-usb/lmedm04.c @@ -329,13 +329,19 @@ static int lme2510_int_read(struct dvb_usb_adapter *adap) static int lme2510_return_status(struct usb_device *dev) { int ret = 0; - u8 data[10] = {0}; + u8 *data; + + data = kzalloc(10, GFP_KERNEL); + if (!data) + return -ENOMEM; ret |= usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), 0x06, 0x80, 0x0302, 0x00, data, 0x0006, 200); info("Firmware Status: %x (%x)", ret , data[2]); - return (ret < 0) ? -ENODEV : data[2]; + ret = (ret < 0) ? -ENODEV : data[2]; + kfree(data); + return ret; } static int lme2510_msg(struct dvb_usb_device *d, @@ -655,7 +661,7 @@ static int lme2510_download_firmware(struct usb_device *dev, const struct firmware *fw) { int ret = 0; - u8 data[512] = {0}; + u8 *data; u16 j, wlen, len_in, start, end; u8 packet_size, dlen, i; u8 *fw_data; @@ -663,6 +669,11 @@ static int lme2510_download_firmware(struct usb_device *dev, packet_size = 0x31; len_in = 1; + data = kzalloc(512, GFP_KERNEL); + if (!data) { + info("FRM Could not start Firmware Download (Buffer allocation failed)"); + return -ENOMEM; + } info("FRM Starting Firmware Download"); @@ -706,7 +717,7 @@ static int lme2510_download_firmware(struct usb_device *dev, else info("FRM Firmware Download Completed - Resetting Device"); - + kfree(data); return (ret < 0) ? -ENODEV : 0; } -- cgit v1.2.3 From fd206508492caffaccc36cbfc40d3b1f8eeb1f0b Mon Sep 17 00:00:00 2001 From: Mariusz Kozlowski <mk@lab.zgora.pl> Date: Sat, 26 Mar 2011 15:23:56 -0300 Subject: [media] dib0700: fix possible NULL pointer dereference Seems like 'adap->fe' test for NULL was meant to be before we dereference that pointer. Signed-off-by: Mariusz Kozlowski <mk@lab.zgora.pl> Acked-by: Patrick Boettcher <patrick.boettcher@dibcom.fr> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/dib0700_devices.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c index 65214af5cd74..5c01d25875ed 100644 --- a/drivers/media/dvb/dvb-usb/dib0700_devices.c +++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c @@ -2439,7 +2439,6 @@ static int tfe7090pvr_frontend0_attach(struct dvb_usb_adapter *adap) dib0700_set_i2c_speed(adap->dev, 340); adap->fe = dvb_attach(dib7000p_attach, &adap->dev->i2c_adap, 0x90, &tfe7090pvr_dib7000p_config[0]); - if (adap->fe == NULL) return -ENODEV; -- cgit v1.2.3 From 53f1fe9465359e0cc080d4a7779cdfcd42b75e82 Mon Sep 17 00:00:00 2001 From: Hans Petter Selasky <hselasky@c2i.net> Date: Mon, 28 Mar 2011 14:37:36 -0300 Subject: [media] cx24116.c - fix for wrong parameter description Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/cx24116.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/cx24116.c b/drivers/media/dvb/frontends/cx24116.c index 2410d8b59b6b..cf1ec6c82042 100644 --- a/drivers/media/dvb/frontends/cx24116.c +++ b/drivers/media/dvb/frontends/cx24116.c @@ -137,7 +137,7 @@ MODULE_PARM_DESC(toneburst, "DiSEqC toneburst 0=OFF, 1=TONE CACHE, "\ /* SNR measurements */ static int esno_snr; module_param(esno_snr, int, 0644); -MODULE_PARM_DESC(debug, "SNR return units, 0=PERCENTAGE 0-100, "\ +MODULE_PARM_DESC(esno_snr, "SNR return units, 0=PERCENTAGE 0-100, "\ "1=ESNO(db * 10) (default:0)"); enum cmds { -- cgit v1.2.3 From 574312d8ceb689af5000fa78d40f7ee38e1ea895 Mon Sep 17 00:00:00 2001 From: Oliver Endriss <o.endriss@gmx.de> Date: Tue, 29 Mar 2011 17:37:00 -0300 Subject: [media] budget-ci: Add support for TT S-1500 with BSBE1-D01A tuner Add support for TT S-1500 with BSBE1-D01A tuner. Signed-off-by: Oliver Endriss <o.endriss@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/bsbe1-d01a.h | 146 +++++++++++++++++++++++++++++++ drivers/media/dvb/ttpci/Kconfig | 2 + drivers/media/dvb/ttpci/budget-ci.c | 21 +++++ 3 files changed, 169 insertions(+) create mode 100644 drivers/media/dvb/frontends/bsbe1-d01a.h (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/bsbe1-d01a.h b/drivers/media/dvb/frontends/bsbe1-d01a.h new file mode 100644 index 000000000000..7ed3c424178c --- /dev/null +++ b/drivers/media/dvb/frontends/bsbe1-d01a.h @@ -0,0 +1,146 @@ +/* + * bsbe1-d01a.h - ALPS BSBE1-D01A tuner support + * + * Copyright (C) 2011 Oliver Endriss <o.endriss@gmx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + * + * + * the project's page is at http://www.linuxtv.org + */ + +#ifndef BSBE1_D01A_H +#define BSBE1_D01A_H + +#include "stb6000.h" +#include "stv0288.h" + +static u8 stv0288_bsbe1_d01a_inittab[] = { + 0x01, 0x15, + 0x02, 0x20, + 0x09, 0x0, + 0x0a, 0x4, + 0x0b, 0x0, + 0x0c, 0x0, + 0x0d, 0x0, + 0x0e, 0xd4, + 0x0f, 0x30, + 0x11, 0x80, + 0x12, 0x03, + 0x13, 0x48, + 0x14, 0x84, + 0x15, 0x45, + 0x16, 0xb7, + 0x17, 0x9c, + 0x18, 0x0, + 0x19, 0xa6, + 0x1a, 0x88, + 0x1b, 0x8f, + 0x1c, 0xf0, + 0x20, 0x0b, + 0x21, 0x54, + 0x22, 0x0, + 0x23, 0x0, + 0x2b, 0xff, + 0x2c, 0xf7, + 0x30, 0x0, + 0x31, 0x1e, + 0x32, 0x14, + 0x33, 0x0f, + 0x34, 0x09, + 0x35, 0x0c, + 0x36, 0x05, + 0x37, 0x2f, + 0x38, 0x16, + 0x39, 0xbd, + 0x3a, 0x03, + 0x3b, 0x13, + 0x3c, 0x11, + 0x3d, 0x30, + 0x40, 0x63, + 0x41, 0x04, + 0x42, 0x60, + 0x43, 0x00, + 0x44, 0x00, + 0x45, 0x00, + 0x46, 0x00, + 0x47, 0x00, + 0x4a, 0x00, + 0x50, 0x10, + 0x51, 0x36, + 0x52, 0x09, + 0x53, 0x94, + 0x54, 0x62, + 0x55, 0x29, + 0x56, 0x64, + 0x57, 0x2b, + 0x58, 0x54, + 0x59, 0x86, + 0x5a, 0x0, + 0x5b, 0x9b, + 0x5c, 0x08, + 0x5d, 0x7f, + 0x5e, 0x0, + 0x5f, 0xff, + 0x70, 0x0, + 0x71, 0x0, + 0x72, 0x0, + 0x74, 0x0, + 0x75, 0x0, + 0x76, 0x0, + 0x81, 0x0, + 0x82, 0x3f, + 0x83, 0x3f, + 0x84, 0x0, + 0x85, 0x0, + 0x88, 0x0, + 0x89, 0x0, + 0x8a, 0x0, + 0x8b, 0x0, + 0x8c, 0x0, + 0x90, 0x0, + 0x91, 0x0, + 0x92, 0x0, + 0x93, 0x0, + 0x94, 0x1c, + 0x97, 0x0, + 0xa0, 0x48, + 0xa1, 0x0, + 0xb0, 0xb8, + 0xb1, 0x3a, + 0xb2, 0x10, + 0xb3, 0x82, + 0xb4, 0x80, + 0xb5, 0x82, + 0xb6, 0x82, + 0xb7, 0x82, + 0xb8, 0x20, + 0xb9, 0x0, + 0xf0, 0x0, + 0xf1, 0x0, + 0xf2, 0xc0, + 0xff, 0xff, +}; + +static struct stv0288_config stv0288_bsbe1_d01a_config = { + .demod_address = 0x68, + .min_delay_ms = 100, + .inittab = stv0288_bsbe1_d01a_inittab, +}; + +#endif diff --git a/drivers/media/dvb/ttpci/Kconfig b/drivers/media/dvb/ttpci/Kconfig index 44afab2fdc2d..9d83ced69dd6 100644 --- a/drivers/media/dvb/ttpci/Kconfig +++ b/drivers/media/dvb/ttpci/Kconfig @@ -95,6 +95,8 @@ config DVB_BUDGET_CI select DVB_STB0899 if !DVB_FE_CUSTOMISE select DVB_STB6100 if !DVB_FE_CUSTOMISE select DVB_LNBP21 if !DVB_FE_CUSTOMISE + select DVB_STV0288 if !DVB_FE_CUSTOMISE + select DVB_STB6000 if !DVB_FE_CUSTOMISE select DVB_TDA10023 if !DVB_FE_CUSTOMISE select MEDIA_TUNER_TDA827X if !MEDIA_TUNER_CUSTOMISE depends on RC_CORE diff --git a/drivers/media/dvb/ttpci/budget-ci.c b/drivers/media/dvb/ttpci/budget-ci.c index 1d79ada864d6..926f299b5225 100644 --- a/drivers/media/dvb/ttpci/budget-ci.c +++ b/drivers/media/dvb/ttpci/budget-ci.c @@ -52,6 +52,7 @@ #include "bsru6.h" #include "tda1002x.h" #include "tda827x.h" +#include "bsbe1-d01a.h" #define MODULE_NAME "budget_ci" @@ -224,6 +225,7 @@ static int msp430_ir_init(struct budget_ci *budget_ci) case 0x1017: case 0x1019: case 0x101a: + case 0x101b: /* for the Technotrend 1500 bundled remote */ dev->map_name = RC_MAP_TT_1500; break; @@ -1388,6 +1390,23 @@ static void frontend_init(struct budget_ci *budget_ci) } break; + case 0x101b: /* TT S-1500B (BSBE1-D01A - STV0288/STB6000/LNBP21) */ + budget_ci->budget.dvb_frontend = dvb_attach(stv0288_attach, &stv0288_bsbe1_d01a_config, &budget_ci->budget.i2c_adap); + if (budget_ci->budget.dvb_frontend) { + if (dvb_attach(stb6000_attach, budget_ci->budget.dvb_frontend, 0x63, &budget_ci->budget.i2c_adap)) { + if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) { + printk(KERN_ERR "%s: No LNBP21 found!\n", __func__); + dvb_frontend_detach(budget_ci->budget.dvb_frontend); + budget_ci->budget.dvb_frontend = NULL; + } + } else { + printk(KERN_ERR "%s: No STB6000 found!\n", __func__); + dvb_frontend_detach(budget_ci->budget.dvb_frontend); + budget_ci->budget.dvb_frontend = NULL; + } + } + break; + case 0x1019: // TT S2-3200 PCI /* * NOTE! on some STB0899 versions, the internal PLL takes a longer time @@ -1518,6 +1537,7 @@ MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT); MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT); MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT); MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT); +MAKE_BUDGET_INFO(ttbs1500b, "TT-Budget S-1500B PCI", BUDGET_TT); static struct pci_device_id pci_tbl[] = { MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c), @@ -1528,6 +1548,7 @@ static struct pci_device_id pci_tbl[] = { MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017), MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a), MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019), + MAKE_EXTENSION_PCI(ttbs1500b, 0x13c2, 0x101b), { .vendor = 0, } -- cgit v1.2.3 From 910c41cac0c5dfcf89ad2c0dc2f8a1aa1cbf3185 Mon Sep 17 00:00:00 2001 From: Malcolm Priestley <tvboxspy@gmail.com> Date: Sat, 2 Apr 2011 10:47:50 -0300 Subject: [media] DM04/QQBOX stv0288 register 42 - incorrect setting stv0288 Register 42 bits 6 & 7 should be set to 0. This is causing intermittent lock, the dvb-usb-lmedm04 driver uses register 50 (auto fine mode) to correct for this, this register is now returned to its default setting. Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/lmedm04.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/lmedm04.h b/drivers/media/dvb/dvb-usb/lmedm04.h index e6af16c1e3e5..3a30ab12edc2 100644 --- a/drivers/media/dvb/dvb-usb/lmedm04.h +++ b/drivers/media/dvb/dvb-usb/lmedm04.h @@ -108,14 +108,14 @@ static u8 s7395_inittab[] = { 0x3d, 0x30, 0x40, 0x63, 0x41, 0x04, - 0x42, 0x60, + 0x42, 0x20, 0x43, 0x00, 0x44, 0x00, 0x45, 0x00, 0x46, 0x00, 0x47, 0x00, 0x4a, 0x00, - 0x50, 0x12, + 0x50, 0x10, 0x51, 0x36, 0x52, 0x21, 0x53, 0x94, -- cgit v1.2.3 From bb19a4210540866443e51635733a83d0970939c8 Mon Sep 17 00:00:00 2001 From: Malcolm Priestley <tvboxspy@gmail.com> Date: Sat, 2 Apr 2011 10:51:53 -0300 Subject: [media] STV0288 Register 42 - Incorrect settings Register 42 bits 2,3,6 and 7 should be set to 0. This gives difficult locking on some channels and may be compensated for by other methods. This affects any driver using the stv0288 frontend on the default or earda inittab. Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/eds1547.h | 2 +- drivers/media/dvb/frontends/stv0288.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/eds1547.h b/drivers/media/dvb/frontends/eds1547.h index fa79b7c83dd2..c983f2f85802 100644 --- a/drivers/media/dvb/frontends/eds1547.h +++ b/drivers/media/dvb/frontends/eds1547.h @@ -61,7 +61,7 @@ static u8 stv0288_earda_inittab[] = { 0x3d, 0x30, 0x40, 0x63, 0x41, 0x04, - 0x42, 0x60, + 0x42, 0x20, 0x43, 0x00, 0x44, 0x00, 0x45, 0x00, diff --git a/drivers/media/dvb/frontends/stv0288.c b/drivers/media/dvb/frontends/stv0288.c index e3fe17fd96fb..8e0cfadba688 100644 --- a/drivers/media/dvb/frontends/stv0288.c +++ b/drivers/media/dvb/frontends/stv0288.c @@ -253,7 +253,7 @@ static u8 stv0288_inittab[] = { 0x3d, 0x30, 0x40, 0x63, 0x41, 0x04, - 0x42, 0x60, + 0x42, 0x20, 0x43, 0x00, 0x44, 0x00, 0x45, 0x00, -- cgit v1.2.3 From eb02d8571bebf53a9c18a82f9912d0a77ebb83e7 Mon Sep 17 00:00:00 2001 From: Malcolm Priestley <tvboxspy@gmail.com> Date: Sat, 2 Apr 2011 18:59:29 -0300 Subject: [media] DM04/QQBOX v1.84 added PID filter A greatly simplified version of the PID Filter now added back to the Driver. The driver allows for the PID filter to be turned off. applied after patch 683781. Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/lmedm04.c | 87 +++++++++++++++++++++++++++++++++++-- drivers/media/dvb/dvb-usb/lmedm04.h | 1 + 2 files changed, 85 insertions(+), 3 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/lmedm04.c b/drivers/media/dvb/dvb-usb/lmedm04.c index a4457e4c1246..5b0f43791f77 100644 --- a/drivers/media/dvb/dvb-usb/lmedm04.c +++ b/drivers/media/dvb/dvb-usb/lmedm04.c @@ -62,8 +62,6 @@ * LME2510: SHARP:BS2F7HZ0194(MV0194) cannot cold reset and share system * with other tuners. After a cold reset streaming will not start. * - * PID functions have been removed from this driver version due to - * problems with different firmware and application versions. */ #define DVB_USB_LOG_PREFIX "LME2510(C)" #include <linux/usb.h> @@ -104,6 +102,10 @@ static int dvb_usb_lme2510_firmware; module_param_named(firmware, dvb_usb_lme2510_firmware, int, 0644); MODULE_PARM_DESC(firmware, "set default firmware 0=Sharp7395 1=LG"); +static int pid_filter; +module_param_named(pid, pid_filter, int, 0644); +MODULE_PARM_DESC(pid, "set default 0=on 1=off"); + DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); @@ -216,6 +218,38 @@ static int lme2510_remote_keypress(struct dvb_usb_adapter *adap, u32 keypress) return 0; } +static int lme2510_enable_pid(struct dvb_usb_device *d, u8 index, u16 pid_out) +{ + struct lme2510_state *st = d->priv; + static u8 pid_buff[] = LME_ZERO_PID; + static u8 rbuf[1]; + u8 pid_no = index * 2; + int ret = 0; + deb_info(1, "PID Setting Pid %04x", pid_out); + + pid_buff[2] = pid_no; + pid_buff[3] = (u8)pid_out & 0xff; + pid_buff[4] = pid_no + 1; + pid_buff[5] = (u8)(pid_out >> 8); + + /* wait for i2c mutex */ + ret = mutex_lock_interruptible(&d->i2c_mutex); + if (ret < 0) { + ret = -EAGAIN; + return ret; + } + + ret |= lme2510_usb_talk(d, pid_buff , + sizeof(pid_buff) , rbuf, sizeof(rbuf)); + + if (st->stream_on & 1) + ret |= lme2510_stream_restart(d); + + mutex_unlock(&d->i2c_mutex); + + return ret; +} + static void lme2510_int_response(struct urb *lme_urb) { struct dvb_usb_adapter *adap = lme_urb->context; @@ -326,6 +360,41 @@ static int lme2510_int_read(struct dvb_usb_adapter *adap) return 0; } +static int lme2510_pid_filter_ctrl(struct dvb_usb_adapter *adap, int onoff) +{ + static u8 clear_pid_reg[] = LME_CLEAR_PID; + static u8 rbuf[1]; + int ret = 0; + + deb_info(1, "PID Clearing Filter"); + + ret = mutex_lock_interruptible(&adap->dev->i2c_mutex); + + if (!onoff) + ret |= lme2510_usb_talk(adap->dev, clear_pid_reg, + sizeof(clear_pid_reg), rbuf, sizeof(rbuf)); + + mutex_unlock(&adap->dev->i2c_mutex); + + return 0; +} + +static int lme2510_pid_filter(struct dvb_usb_adapter *adap, int index, u16 pid, + int onoff) +{ + int ret = 0; + + deb_info(3, "%s PID=%04x Index=%04x onoff=%02x", __func__, + pid, index, onoff); + + if (onoff) + if (!pid_filter) + ret = lme2510_enable_pid(adap->dev, index, pid); + + return ret; +} + + static int lme2510_return_status(struct usb_device *dev) { int ret = 0; @@ -1099,7 +1168,13 @@ static struct dvb_usb_device_properties lme2510_properties = { .num_adapters = 1, .adapter = { { + .caps = DVB_USB_ADAP_HAS_PID_FILTER| + DVB_USB_ADAP_NEED_PID_FILTERING| + DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF, .streaming_ctrl = lme2510_streaming_ctrl, + .pid_filter_count = 15, + .pid_filter = lme2510_pid_filter, + .pid_filter_ctrl = lme2510_pid_filter_ctrl, .frontend_attach = dm04_lme2510_frontend_attach, .tuner_attach = dm04_lme2510_tuner, /* parameter for the MPEG2-data transfer */ @@ -1135,7 +1210,13 @@ static struct dvb_usb_device_properties lme2510c_properties = { .num_adapters = 1, .adapter = { { + .caps = DVB_USB_ADAP_HAS_PID_FILTER| + DVB_USB_ADAP_NEED_PID_FILTERING| + DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF, .streaming_ctrl = lme2510_streaming_ctrl, + .pid_filter_count = 15, + .pid_filter = lme2510_pid_filter, + .pid_filter_ctrl = lme2510_pid_filter_ctrl, .frontend_attach = dm04_lme2510_frontend_attach, .tuner_attach = dm04_lme2510_tuner, /* parameter for the MPEG2-data transfer */ @@ -1233,5 +1314,5 @@ module_exit(lme2510_module_exit); MODULE_AUTHOR("Malcolm Priestley <tvboxspy@gmail.com>"); MODULE_DESCRIPTION("LME2510(C) DVB-S USB2.0"); -MODULE_VERSION("1.81"); +MODULE_VERSION("1.84"); MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb/dvb-usb/lmedm04.h b/drivers/media/dvb/dvb-usb/lmedm04.h index 3a30ab12edc2..ab21e2ef53fa 100644 --- a/drivers/media/dvb/dvb-usb/lmedm04.h +++ b/drivers/media/dvb/dvb-usb/lmedm04.h @@ -40,6 +40,7 @@ */ #define LME_ST_ON_W {0x06, 0x00} #define LME_CLEAR_PID {0x03, 0x02, 0x20, 0xa0} +#define LME_ZERO_PID {0x03, 0x06, 0x00, 0x00, 0x01, 0x00, 0x20, 0x9c} /* LNB Voltage * 07 XX XX -- cgit v1.2.3 From 451a51b218df9a3a93af9fd71a356cc6043df52a Mon Sep 17 00:00:00 2001 From: Jesper Juhl <jj@chaosbits.net> Date: Thu, 7 Apr 2011 16:34:30 -0300 Subject: [media] DVB, DiB9000: Fix leak in dib9000_attach() If the second memory allocation in dib9000_attach() fails, we'll leak the memory allocated by the first. Signed-off-by: Jesper Juhl <jj@chaosbits.net> Cc: Patrick Boettcher <patrick.boettcher@dibcom.fr> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/dib9000.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/dib9000.c b/drivers/media/dvb/frontends/dib9000.c index 91518761a2da..b25ef2bb5078 100644 --- a/drivers/media/dvb/frontends/dib9000.c +++ b/drivers/media/dvb/frontends/dib9000.c @@ -2255,8 +2255,10 @@ struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, c if (st == NULL) return NULL; fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL); - if (fe == NULL) + if (fe == NULL) { + kfree(st); return NULL; + } memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config)); st->i2c.i2c_adap = i2c_adap; -- cgit v1.2.3 From 38e009aac9e02d2c30fd9a5e979ab31433e7d578 Mon Sep 17 00:00:00 2001 From: Marko Ristola <marko.ristola@kolumbus.fi> Date: Fri, 8 Apr 2011 12:40:51 -0300 Subject: [media] Speed up DVB TS stream delivery from DMA buffer into dvb-core's buffer Avoid unnecessary DVB TS 188 sized packet copying from DMA buffer into stack. Backtrack one 188 sized packet just after some garbage bytes when possible. This obsoletes patch https://patchwork.kernel.org/patch/118147/ Signed-off-by: Marko Ristola <marko.ristola@kolumbus.fi> Acked-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-core/dvb_demux.c | 117 ++++++++++++++++----------------- 1 file changed, 57 insertions(+), 60 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-core/dvb_demux.c b/drivers/media/dvb/dvb-core/dvb_demux.c index 4a88a3e4db2b..faa3671b649e 100644 --- a/drivers/media/dvb/dvb-core/dvb_demux.c +++ b/drivers/media/dvb/dvb-core/dvb_demux.c @@ -478,97 +478,94 @@ void dvb_dmx_swfilter_packets(struct dvb_demux *demux, const u8 *buf, EXPORT_SYMBOL(dvb_dmx_swfilter_packets); -void dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, size_t count) +static inline int find_next_packet(const u8 *buf, int pos, size_t count, + const int pktsize) { - int p = 0, i, j; + int start = pos, lost; - spin_lock(&demux->lock); - - if (demux->tsbufp) { - i = demux->tsbufp; - j = 188 - i; - if (count < j) { - memcpy(&demux->tsbuf[i], buf, count); - demux->tsbufp += count; - goto bailout; - } - memcpy(&demux->tsbuf[i], buf, j); - if (demux->tsbuf[0] == 0x47) - dvb_dmx_swfilter_packet(demux, demux->tsbuf); - demux->tsbufp = 0; - p += j; + while (pos < count) { + if (buf[pos] == 0x47 || + (pktsize == 204 && buf[pos] == 0xB8)) + break; + pos++; } - while (p < count) { - if (buf[p] == 0x47) { - if (count - p >= 188) { - dvb_dmx_swfilter_packet(demux, &buf[p]); - p += 188; - } else { - i = count - p; - memcpy(demux->tsbuf, &buf[p], i); - demux->tsbufp = i; - goto bailout; - } - } else - p++; + lost = pos - start; + if (lost) { + /* This garbage is part of a valid packet? */ + int backtrack = pos - pktsize; + if (backtrack >= 0 && (buf[backtrack] == 0x47 || + (pktsize == 204 && buf[backtrack] == 0xB8))) + return backtrack; } -bailout: - spin_unlock(&demux->lock); + return pos; } -EXPORT_SYMBOL(dvb_dmx_swfilter); - -void dvb_dmx_swfilter_204(struct dvb_demux *demux, const u8 *buf, size_t count) +/* Filter all pktsize= 188 or 204 sized packets and skip garbage. */ +static inline void _dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, + size_t count, const int pktsize) { int p = 0, i, j; - u8 tmppack[188]; + const u8 *q; spin_lock(&demux->lock); - if (demux->tsbufp) { + if (demux->tsbufp) { /* tsbuf[0] is now 0x47. */ i = demux->tsbufp; - j = 204 - i; + j = pktsize - i; if (count < j) { memcpy(&demux->tsbuf[i], buf, count); demux->tsbufp += count; goto bailout; } memcpy(&demux->tsbuf[i], buf, j); - if ((demux->tsbuf[0] == 0x47) || (demux->tsbuf[0] == 0xB8)) { - memcpy(tmppack, demux->tsbuf, 188); - if (tmppack[0] == 0xB8) - tmppack[0] = 0x47; - dvb_dmx_swfilter_packet(demux, tmppack); - } + if (demux->tsbuf[0] == 0x47) /* double check */ + dvb_dmx_swfilter_packet(demux, demux->tsbuf); demux->tsbufp = 0; p += j; } - while (p < count) { - if ((buf[p] == 0x47) || (buf[p] == 0xB8)) { - if (count - p >= 204) { - memcpy(tmppack, &buf[p], 188); - if (tmppack[0] == 0xB8) - tmppack[0] = 0x47; - dvb_dmx_swfilter_packet(demux, tmppack); - p += 204; - } else { - i = count - p; - memcpy(demux->tsbuf, &buf[p], i); - demux->tsbufp = i; - goto bailout; - } - } else { - p++; + while (1) { + p = find_next_packet(buf, p, count, pktsize); + if (p >= count) + break; + if (count - p < pktsize) + break; + + q = &buf[p]; + + if (pktsize == 204 && (*q == 0xB8)) { + memcpy(demux->tsbuf, q, 188); + demux->tsbuf[0] = 0x47; + q = demux->tsbuf; } + dvb_dmx_swfilter_packet(demux, q); + p += pktsize; + } + + i = count - p; + if (i) { + memcpy(demux->tsbuf, &buf[p], i); + demux->tsbufp = i; + if (pktsize == 204 && demux->tsbuf[0] == 0xB8) + demux->tsbuf[0] = 0x47; } bailout: spin_unlock(&demux->lock); } +void dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, size_t count) +{ + _dvb_dmx_swfilter(demux, buf, count, 188); +} +EXPORT_SYMBOL(dvb_dmx_swfilter); + +void dvb_dmx_swfilter_204(struct dvb_demux *demux, const u8 *buf, size_t count) +{ + _dvb_dmx_swfilter(demux, buf, count, 204); +} EXPORT_SYMBOL(dvb_dmx_swfilter_204); static struct dvb_demux_filter *dvb_dmx_filter_alloc(struct dvb_demux *demux) -- cgit v1.2.3 From 6f030abf9a77f10213bc5a2da2eff478d4d4e0c3 Mon Sep 17 00:00:00 2001 From: Alexey Khoroshilov <khoroshilov@ispras.ru> Date: Fri, 15 Apr 2011 17:40:17 -0300 Subject: [media] lmedm04: Do not unlock mutex if mutex_lock_interruptible failed There are a couple of places where mutex_unlock() is called even if mutex_lock_interruptible() failed. The patch fixes the issue. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/lmedm04.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/lmedm04.c b/drivers/media/dvb/dvb-usb/lmedm04.c index 5b0f43791f77..773638475a79 100644 --- a/drivers/media/dvb/dvb-usb/lmedm04.c +++ b/drivers/media/dvb/dvb-usb/lmedm04.c @@ -666,9 +666,10 @@ static int lme2510_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff) else { deb_info(1, "STM Steam Off"); /* mutex is here only to avoid collision with I2C */ - ret = mutex_lock_interruptible(&adap->dev->i2c_mutex); + if (mutex_lock_interruptible(&adap->dev->i2c_mutex) < 0) + return -EAGAIN; - ret |= lme2510_usb_talk(adap->dev, clear_reg_3, + ret = lme2510_usb_talk(adap->dev, clear_reg_3, sizeof(clear_reg_3), rbuf, rlen); st->stream_on = 0; st->i2c_talk_onoff = 1; @@ -1099,12 +1100,13 @@ static int lme2510_powerup(struct dvb_usb_device *d, int onoff) static u8 rbuf[1]; int ret, len = 3, rlen = 1; - ret = mutex_lock_interruptible(&d->i2c_mutex); + if (mutex_lock_interruptible(&d->i2c_mutex) < 0) + return -EAGAIN; if (onoff) - ret |= lme2510_usb_talk(d, lnb_on, len, rbuf, rlen); + ret = lme2510_usb_talk(d, lnb_on, len, rbuf, rlen); else - ret |= lme2510_usb_talk(d, lnb_off, len, rbuf, rlen); + ret = lme2510_usb_talk(d, lnb_off, len, rbuf, rlen); st->i2c_talk_onoff = 1; -- cgit v1.2.3 From c8b7ced3460934cb31464463d7f909fef5db9391 Mon Sep 17 00:00:00 2001 From: Malcolm Priestley <tvboxspy@gmail.com> Date: Sat, 16 Apr 2011 13:30:32 -0300 Subject: [media] dvb-usb return device errors to demuxer Return device errors to demuxer from on/off streamming and pid filtering. Please test this patch with all dvb-usb devices. Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/dvb-usb-dvb.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c b/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c index df1ec3e69f4a..965698b2d974 100644 --- a/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c +++ b/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c @@ -12,7 +12,7 @@ static int dvb_usb_ctrl_feed(struct dvb_demux_feed *dvbdmxfeed, int onoff) { struct dvb_usb_adapter *adap = dvbdmxfeed->demux->priv; - int newfeedcount,ret; + int newfeedcount, ret; if (adap == NULL) return -ENODEV; @@ -24,9 +24,12 @@ static int dvb_usb_ctrl_feed(struct dvb_demux_feed *dvbdmxfeed, int onoff) deb_ts("stop feeding\n"); usb_urb_kill(&adap->stream); - if (adap->props.streaming_ctrl != NULL) - if ((ret = adap->props.streaming_ctrl(adap,0))) - err("error while stopping stream."); + if (adap->props.streaming_ctrl != NULL) { + ret = adap->props.streaming_ctrl(adap, 0); + err("error while stopping stream."); + if (ret < 0) + return ret; + } } adap->feedcount = newfeedcount; @@ -49,17 +52,24 @@ static int dvb_usb_ctrl_feed(struct dvb_demux_feed *dvbdmxfeed, int onoff) deb_ts("controlling pid parser\n"); if (adap->props.caps & DVB_USB_ADAP_HAS_PID_FILTER && - adap->props.caps & DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF && - adap->props.pid_filter_ctrl != NULL) - if (adap->props.pid_filter_ctrl(adap,adap->pid_filtering) < 0) + adap->props.caps & + DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF && + adap->props.pid_filter_ctrl != NULL) { + ret = adap->props.pid_filter_ctrl(adap, + adap->pid_filtering); + if (ret < 0) { err("could not handle pid_parser"); - + return ret; + } + } deb_ts("start feeding\n"); - if (adap->props.streaming_ctrl != NULL) - if (adap->props.streaming_ctrl(adap,1)) { + if (adap->props.streaming_ctrl != NULL) { + ret = adap->props.streaming_ctrl(adap, 1); + if (ret < 0) { err("error while enabling fifo."); - return -ENODEV; + return ret; } + } } return 0; -- cgit v1.2.3 From dca6b74bb332f6aa52bd2a6efc464233e542297b Mon Sep 17 00:00:00 2001 From: Malcolm Priestley <tvboxspy@gmail.com> Date: Sun, 17 Apr 2011 16:55:14 -0300 Subject: [media] dvb-usb: don't return error if stream stop Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/dvb-usb-dvb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c b/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c index 965698b2d974..b3cb626ed56e 100644 --- a/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c +++ b/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c @@ -26,9 +26,10 @@ static int dvb_usb_ctrl_feed(struct dvb_demux_feed *dvbdmxfeed, int onoff) if (adap->props.streaming_ctrl != NULL) { ret = adap->props.streaming_ctrl(adap, 0); - err("error while stopping stream."); - if (ret < 0) + if (ret < 0) { + err("error while stopping stream."); return ret; + } } } -- cgit v1.2.3 From 08921ac9e9d185d6f472238ea9c79a3a70eb7ea7 Mon Sep 17 00:00:00 2001 From: Jesper Juhl <jj@chaosbits.net> Date: Thu, 21 Apr 2011 18:11:25 -0300 Subject: [media] Media, DVB, Siano, smsusb: Avoid static analysis report about 'use after free' In drivers/media/dvb/siano/smsusb.c we have this code: ... kfree(dev); sms_info("device %p destroyed", dev); ... at least one static analysis tool (Coverity Prevent) complains about this as a use-after-free bug. While it's true that we do use the pointer variable after freeing it, the only use is to print the value of the pointer, so there's not actually any problem here. But still, silencing the complaint is trivial by just moving the kfree() call below the sms_info(), so why not just do it?. It doesn't change the workings of the code in any way, but it makes the tool shut up. The patch below also removes a rather pointless blank line. Signed-off-by: Jesper Juhl <jj@chaosbits.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/siano/smsusb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/siano/smsusb.c b/drivers/media/dvb/siano/smsusb.c index 0b8da57cf4c3..0c8164a2cc36 100644 --- a/drivers/media/dvb/siano/smsusb.c +++ b/drivers/media/dvb/siano/smsusb.c @@ -297,9 +297,8 @@ static void smsusb_term_device(struct usb_interface *intf) if (dev->coredev) smscore_unregister_device(dev->coredev); - kfree(dev); - sms_info("device %p destroyed", dev); + kfree(dev); } usb_set_intfdata(intf, NULL); -- cgit v1.2.3 From 853e3b2930001534b88fb36e936c9a734a79046c Mon Sep 17 00:00:00 2001 From: Malcolm Priestley <tvboxspy@gmail.com> Date: Fri, 22 Apr 2011 06:00:22 -0300 Subject: [media] IX2505V Keep I2C gate control alive Gate could close after first I2C message. On stv0288 it does. Keep 2nd and 3rd message I2C gate control alive. Remove unnecessary gate closing in this module. Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/ix2505v.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/ix2505v.c b/drivers/media/dvb/frontends/ix2505v.c index 6c2e929bd79f..9a517a4bf96d 100644 --- a/drivers/media/dvb/frontends/ix2505v.c +++ b/drivers/media/dvb/frontends/ix2505v.c @@ -218,11 +218,13 @@ static int ix2505v_set_params(struct dvb_frontend *fe, fe->ops.i2c_gate_ctrl(fe, 1); len = sizeof(data); - ret |= ix2505v_write(state, data, len); data[2] |= 0x4; /* set TM = 1 other bits same */ + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + len = 1; ret |= ix2505v_write(state, &data[2], len); /* write byte 4 only */ @@ -233,12 +235,12 @@ static int ix2505v_set_params(struct dvb_frontend *fe, deb_info("Data 2=[%x%x]\n", data[2], data[3]); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 1); + len = 2; ret |= ix2505v_write(state, &data[2], len); /* write byte 4 & 5 */ - if (fe->ops.i2c_gate_ctrl) - fe->ops.i2c_gate_ctrl(fe, 0); - if (state->config->min_delay_ms) msleep(state->config->min_delay_ms); -- cgit v1.2.3 From a760d63878b21fc16997b79e8ebee531b40c8b26 Mon Sep 17 00:00:00 2001 From: Malcolm Priestley <tvboxspy@gmail.com> Date: Fri, 22 Apr 2011 06:07:40 -0300 Subject: [media] lmedm04: don't write to buffer without a mutex usb_buffer not inside mutex lock, waiting caller can alter buffer. Static added to lme2510_exit and lme2510_exit_int. Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/lmedm04.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/lmedm04.c b/drivers/media/dvb/dvb-usb/lmedm04.c index 773638475a79..4b457e7e5d33 100644 --- a/drivers/media/dvb/dvb-usb/lmedm04.c +++ b/drivers/media/dvb/dvb-usb/lmedm04.c @@ -169,14 +169,14 @@ static int lme2510_usb_talk(struct dvb_usb_device *d, } buff = st->usb_buffer; - /* the read/write capped at 512 */ - memcpy(buff, wbuf, (wlen > 512) ? 512 : wlen); - ret = mutex_lock_interruptible(&d->usb_mutex); if (ret < 0) return -EAGAIN; + /* the read/write capped at 512 */ + memcpy(buff, wbuf, (wlen > 512) ? 512 : wlen); + ret |= usb_clear_halt(d->udev, usb_sndbulkpipe(d->udev, 0x01)); ret |= lme2510_bulk_write(d->udev, buff, wlen , 0x01); @@ -1247,7 +1247,7 @@ static struct dvb_usb_device_properties lme2510c_properties = { } }; -void *lme2510_exit_int(struct dvb_usb_device *d) +static void *lme2510_exit_int(struct dvb_usb_device *d) { struct lme2510_state *st = d->priv; struct dvb_usb_adapter *adap = &d->adapter[0]; @@ -1274,7 +1274,7 @@ void *lme2510_exit_int(struct dvb_usb_device *d) return buffer; } -void lme2510_exit(struct usb_interface *intf) +static void lme2510_exit(struct usb_interface *intf) { struct dvb_usb_device *d = usb_get_intfdata(intf); void *usb_buffer; @@ -1316,5 +1316,5 @@ module_exit(lme2510_module_exit); MODULE_AUTHOR("Malcolm Priestley <tvboxspy@gmail.com>"); MODULE_DESCRIPTION("LME2510(C) DVB-S USB2.0"); -MODULE_VERSION("1.84"); +MODULE_VERSION("1.85"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 449a0bada34e5e554ef52aca86aeaa81ed35533e Mon Sep 17 00:00:00 2001 From: Malcolm Priestley <tvboxspy@gmail.com> Date: Fri, 22 Apr 2011 06:20:57 -0300 Subject: [media] lmedm04: PID filtering changes Improve PID filtering and program register 20 correctly. Make sure stream_on message is sent if streaming is off, otherwise PIDs are not registered. Move mutex outside lme2510_enable_pid. Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/lmedm04.c | 37 ++++++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 13 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/lmedm04.c b/drivers/media/dvb/dvb-usb/lmedm04.c index 4b457e7e5d33..f36f471deae2 100644 --- a/drivers/media/dvb/dvb-usb/lmedm04.c +++ b/drivers/media/dvb/dvb-usb/lmedm04.c @@ -127,6 +127,7 @@ struct lme2510_state { u8 i2c_tuner_gate_r; u8 i2c_tuner_addr; u8 stream_on; + u8 pid_size; void *buffer; struct urb *lme_urb; void *usb_buffer; @@ -224,29 +225,28 @@ static int lme2510_enable_pid(struct dvb_usb_device *d, u8 index, u16 pid_out) static u8 pid_buff[] = LME_ZERO_PID; static u8 rbuf[1]; u8 pid_no = index * 2; + u8 pid_len = pid_no + 2; int ret = 0; deb_info(1, "PID Setting Pid %04x", pid_out); + if (st->pid_size == 0) + ret |= lme2510_stream_restart(d); + pid_buff[2] = pid_no; pid_buff[3] = (u8)pid_out & 0xff; pid_buff[4] = pid_no + 1; pid_buff[5] = (u8)(pid_out >> 8); - /* wait for i2c mutex */ - ret = mutex_lock_interruptible(&d->i2c_mutex); - if (ret < 0) { - ret = -EAGAIN; - return ret; - } + if (pid_len > st->pid_size) + st->pid_size = pid_len; + pid_buff[7] = 0x80 + st->pid_size; ret |= lme2510_usb_talk(d, pid_buff , sizeof(pid_buff) , rbuf, sizeof(rbuf)); - if (st->stream_on & 1) + if (st->stream_on) ret |= lme2510_stream_restart(d); - mutex_unlock(&d->i2c_mutex); - return ret; } @@ -362,18 +362,23 @@ static int lme2510_int_read(struct dvb_usb_adapter *adap) static int lme2510_pid_filter_ctrl(struct dvb_usb_adapter *adap, int onoff) { + struct lme2510_state *st = adap->dev->priv; static u8 clear_pid_reg[] = LME_CLEAR_PID; static u8 rbuf[1]; - int ret = 0; + int ret; deb_info(1, "PID Clearing Filter"); ret = mutex_lock_interruptible(&adap->dev->i2c_mutex); + if (ret < 0) + return -EAGAIN; if (!onoff) ret |= lme2510_usb_talk(adap->dev, clear_pid_reg, sizeof(clear_pid_reg), rbuf, sizeof(rbuf)); + st->pid_size = 0; + mutex_unlock(&adap->dev->i2c_mutex); return 0; @@ -388,8 +393,14 @@ static int lme2510_pid_filter(struct dvb_usb_adapter *adap, int index, u16 pid, pid, index, onoff); if (onoff) - if (!pid_filter) - ret = lme2510_enable_pid(adap->dev, index, pid); + if (!pid_filter) { + ret = mutex_lock_interruptible(&adap->dev->i2c_mutex); + if (ret < 0) + return -EAGAIN; + ret |= lme2510_enable_pid(adap->dev, index, pid); + mutex_unlock(&adap->dev->i2c_mutex); + } + return ret; } @@ -1316,5 +1327,5 @@ module_exit(lme2510_module_exit); MODULE_AUTHOR("Malcolm Priestley <tvboxspy@gmail.com>"); MODULE_DESCRIPTION("LME2510(C) DVB-S USB2.0"); -MODULE_VERSION("1.85"); +MODULE_VERSION("1.86"); MODULE_LICENSE("GPL"); -- cgit v1.2.3 From cae72c7c63fd4a8f20efc001108f12f34076c17b Mon Sep 17 00:00:00 2001 From: HIRANO Takahito <hiranotaka@zng.info> Date: Sun, 1 May 2011 02:29:40 -0300 Subject: [media] Fix panic on loading earth-pt1 Signed-off-by: HIRANO Takahito <hiranotaka@zng.info> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/pt1/pt1.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/pt1/pt1.c b/drivers/media/dvb/pt1/pt1.c index 0486919c1d0f..b81df5fafe26 100644 --- a/drivers/media/dvb/pt1/pt1.c +++ b/drivers/media/dvb/pt1/pt1.c @@ -1090,6 +1090,7 @@ pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent) i2c_adap->algo = &pt1_i2c_algo; i2c_adap->algo_data = NULL; i2c_adap->dev.parent = &pdev->dev; + strcpy(i2c_adap->name, DRIVER_NAME); i2c_set_adapdata(i2c_adap, pt1); ret = i2c_add_adapter(i2c_adap); if (ret < 0) @@ -1156,10 +1157,10 @@ err_pt1_disable_ram: pt1->power = 0; pt1->reset = 1; pt1_update_power(pt1); -err_pt1_cleanup_adapters: - pt1_cleanup_adapters(pt1); err_i2c_del_adapter: i2c_del_adapter(i2c_adap); +err_pt1_cleanup_adapters: + pt1_cleanup_adapters(pt1); err_kfree: pci_set_drvdata(pdev, NULL); kfree(pt1); -- cgit v1.2.3 From 24fb06049af849934a30a06da78b7c75fac280df Mon Sep 17 00:00:00 2001 From: Malcolm Priestley <tvboxspy@gmail.com> Date: Sat, 26 Mar 2011 21:57:33 -0300 Subject: [media] STV0299 incorrect standby setting issues register 02 (MCR) Issues with Register 02 causing spurious channel locking from standby. Should have always bits 4 & 5 written to 1. Lower nibble not used in any current driver. Usage if necessary can be applied through initab to mcr_reg. stv0299 not out of standby before writing inittab. Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Acked-by: Oliver Endriss <o.endriss@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/stv0299.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/stv0299.c b/drivers/media/dvb/frontends/stv0299.c index 4e3db3a42e06..42684bec8883 100644 --- a/drivers/media/dvb/frontends/stv0299.c +++ b/drivers/media/dvb/frontends/stv0299.c @@ -64,6 +64,7 @@ struct stv0299_state { fe_code_rate_t fec_inner; int errmode; u32 ucblocks; + u8 mcr_reg; }; #define STATUS_BER 0 @@ -457,6 +458,9 @@ static int stv0299_init (struct dvb_frontend* fe) dprintk("stv0299: init chip\n"); + stv0299_writeregI(state, 0x02, 0x30 | state->mcr_reg); + msleep(50); + for (i = 0; ; i += 2) { reg = state->config->inittab[i]; val = state->config->inittab[i+1]; @@ -464,6 +468,8 @@ static int stv0299_init (struct dvb_frontend* fe) break; if (reg == 0x0c && state->config->op0_off) val &= ~0x10; + if (reg == 0x2) + state->mcr_reg = val & 0xf; stv0299_writeregI(state, reg, val); } @@ -618,7 +624,7 @@ static int stv0299_sleep(struct dvb_frontend* fe) { struct stv0299_state* state = fe->demodulator_priv; - stv0299_writeregI(state, 0x02, 0x80); + stv0299_writeregI(state, 0x02, 0xb0 | state->mcr_reg); state->initialised = 0; return 0; @@ -680,7 +686,7 @@ struct dvb_frontend* stv0299_attach(const struct stv0299_config* config, state->errmode = STATUS_BER; /* check if the demod is there */ - stv0299_writeregI(state, 0x02, 0x34); /* standby off */ + stv0299_writeregI(state, 0x02, 0x30); /* standby off */ msleep(200); id = stv0299_readreg(state, 0x00); -- cgit v1.2.3 From 9d8e1b5490a4fd2fa71bf3b39e7f1ce513daebcd Mon Sep 17 00:00:00 2001 From: Malcolm Priestley <tvboxspy@gmail.com> Date: Sat, 26 Mar 2011 22:03:47 -0300 Subject: [media] STV0299 Register 02 on Opera1/Bsru6/z0194a/mantis_vp1033 Bits 4 and 5 on register 02 should always be set to 1. Opera1/Bsru6/z0194a/mantis_vp1033 Signed-off-by: Malcolm Priestley <tvboxspy@gmail.com> Acked-by: Oliver Endriss <o.endriss@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/opera1.c | 2 +- drivers/media/dvb/frontends/bsru6.h | 2 +- drivers/media/dvb/frontends/z0194a.h | 2 +- drivers/media/dvb/mantis/mantis_vp1033.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/opera1.c b/drivers/media/dvb/dvb-usb/opera1.c index 4258f127ea30..2e4fab7215f5 100644 --- a/drivers/media/dvb/dvb-usb/opera1.c +++ b/drivers/media/dvb/dvb-usb/opera1.c @@ -198,7 +198,7 @@ static int opera1_stv0299_set_symbol_rate(struct dvb_frontend *fe, u32 srate, static u8 opera1_inittab[] = { 0x00, 0xa1, 0x01, 0x15, - 0x02, 0x00, + 0x02, 0x30, 0x03, 0x00, 0x04, 0x7d, 0x05, 0x05, diff --git a/drivers/media/dvb/frontends/bsru6.h b/drivers/media/dvb/frontends/bsru6.h index 45a6dfd8ebb5..c480c839b302 100644 --- a/drivers/media/dvb/frontends/bsru6.h +++ b/drivers/media/dvb/frontends/bsru6.h @@ -27,7 +27,7 @@ static u8 alps_bsru6_inittab[] = { 0x01, 0x15, - 0x02, 0x00, + 0x02, 0x30, 0x03, 0x00, 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */ 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */ diff --git a/drivers/media/dvb/frontends/z0194a.h b/drivers/media/dvb/frontends/z0194a.h index 07f3fc0998f6..96d86d6eb473 100644 --- a/drivers/media/dvb/frontends/z0194a.h +++ b/drivers/media/dvb/frontends/z0194a.h @@ -42,7 +42,7 @@ static int sharp_z0194a_set_symbol_rate(struct dvb_frontend *fe, static u8 sharp_z0194a_inittab[] = { 0x01, 0x15, - 0x02, 0x00, + 0x02, 0x30, 0x03, 0x00, 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */ 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */ diff --git a/drivers/media/dvb/mantis/mantis_vp1033.c b/drivers/media/dvb/mantis/mantis_vp1033.c index deec927c7f7a..2ae0afa7756b 100644 --- a/drivers/media/dvb/mantis/mantis_vp1033.c +++ b/drivers/media/dvb/mantis/mantis_vp1033.c @@ -37,7 +37,7 @@ u8 lgtdqcs001f_inittab[] = { 0x01, 0x15, - 0x02, 0x00, + 0x02, 0x30, 0x03, 0x00, 0x04, 0x2a, 0x05, 0x85, -- cgit v1.2.3 From 107d7b181ddeaeea92d1aa25f2e1e5a3acb7da40 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Wed, 27 Apr 2011 21:03:07 -0300 Subject: [media] cx24116: add config option to split firmware download It is very rare I2C adapter hardware which can provide 32kB I2C write as one write. Add .i2c_wr_max option to set desired max packet size. Split transaction to smaller pieces according to that option. Signed-off-by: Antti Palosaari <crope@iki.fi> Cc: Steven Toth <stoth@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/cx24116.c | 17 ++++++++++++++--- drivers/media/dvb/frontends/cx24116.h | 3 +++ 2 files changed, 17 insertions(+), 3 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/cx24116.c b/drivers/media/dvb/frontends/cx24116.c index cf1ec6c82042..26e65a66719a 100644 --- a/drivers/media/dvb/frontends/cx24116.c +++ b/drivers/media/dvb/frontends/cx24116.c @@ -566,7 +566,7 @@ static int cx24116_load_firmware(struct dvb_frontend *fe, { struct cx24116_state *state = fe->demodulator_priv; struct cx24116_cmd cmd; - int i, ret; + int i, ret, len, remaining; unsigned char vers[4]; dprintk("%s\n", __func__); @@ -603,8 +603,19 @@ static int cx24116_load_firmware(struct dvb_frontend *fe, cx24116_writereg(state, 0xF5, 0x00); cx24116_writereg(state, 0xF6, 0x00); - /* write the entire firmware as one transaction */ - cx24116_writeregN(state, 0xF7, fw->data, fw->size); + /* Split firmware to the max I2C write len and write. + * This overflows 16 bit intentionally in order to get max write + * len when i2c_wr_max is set to 0. */ + for (remaining = fw->size; remaining > 0; + remaining -= (u16) (state->config->i2c_wr_max - 1)) { + + len = remaining; + if (len > (u16) (state->config->i2c_wr_max - 1)) + len = (u16) (state->config->i2c_wr_max - 1); + + cx24116_writeregN(state, 0xF7, &fw->data[fw->size - remaining], + len); + } cx24116_writereg(state, 0xF4, 0x10); cx24116_writereg(state, 0xF0, 0x00); diff --git a/drivers/media/dvb/frontends/cx24116.h b/drivers/media/dvb/frontends/cx24116.h index b1b76b47a14c..7d90ab949c03 100644 --- a/drivers/media/dvb/frontends/cx24116.h +++ b/drivers/media/dvb/frontends/cx24116.h @@ -35,6 +35,9 @@ struct cx24116_config { /* Need to set MPEG parameters */ u8 mpg_clk_pos_pol:0x02; + + /* max bytes I2C provider can write at once */ + u16 i2c_wr_max; }; #if defined(CONFIG_DVB_CX24116) || \ -- cgit v1.2.3 From f0a53105edabcf3d91fabeef4fbdb574d05ab551 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Wed, 27 Apr 2011 21:11:59 -0300 Subject: [media] anysee: add support for Anysee E30 S2 Plus It is USB DVB-S/S2 box. Conexant cx24116/cx24118 demod tuner combo Intersil ISL6423 LNB controller Signed-off-by: Antti Palosaari <crope@iki.fi> Cc: info@anysee.com Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/Kconfig | 2 ++ drivers/media/dvb/dvb-usb/anysee.c | 43 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig index e624ff3ef070..9931ec95d900 100644 --- a/drivers/media/dvb/dvb-usb/Kconfig +++ b/drivers/media/dvb/dvb-usb/Kconfig @@ -293,6 +293,8 @@ config DVB_USB_ANYSEE select DVB_ZL10353 if !DVB_FE_CUSTOMISE select DVB_TDA10023 if !DVB_FE_CUSTOMISE select MEDIA_TUNER_TDA18212 if !MEDIA_TUNER_CUSTOMISE + select DVB_CX24116 if !DVB_FE_CUSTOMISE + select DVB_ISL6423 if !DVB_FE_CUSTOMISE help Say Y here to support the Anysee E30, Anysee E30 Plus or Anysee E30 C Plus DVB USB2.0 receiver. diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index 0e94541ffcff..ebcc05b73c7f 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -37,6 +37,8 @@ #include "mt352_priv.h" #include "zl10353.h" #include "tda18212.h" +#include "cx24116.h" +#include "isl6423.h" /* debug */ static int dvb_usb_anysee_debug; @@ -300,6 +302,19 @@ static struct tda18212_config anysee_tda18212_config = { .if_dvbc = 5000, }; +static struct cx24116_config anysee_cx24116_config = { + .demod_address = (0xaa >> 1), + .mpg_clk_pos_pol = 0x00, + .i2c_wr_max = 48, +}; + +static struct isl6423_config anysee_isl6423_config = { + .current_max = SEC_CURRENT_800m, + .curlim = SEC_CURRENT_LIM_OFF, + .mod_extern = 1, + .addr = (0x10 >> 1), +}; + /* * New USB device strings: Mfr=1, Product=2, SerialNumber=0 * Manufacturer: AMT.CO.KR @@ -328,6 +343,13 @@ static struct tda18212_config anysee_tda18212_config = { * IOA=4f IOB=ff IOC=00 IOD=26 IOF=01 * IOD[0] TDA10023 1=enabled * + * E30 S2 Plus VID=04b4 PID=861f HW=11 FW=0.1 "anysee-S2(LP)" + * PCB: 507SI (rev2.1) + * parts: BS2N10WCC01(CX24116, CX24118), ISL6423, TDA8024 + * OEA=80 OEB=00 OEC=ff OED=ff OEF=fe + * IOA=4d IOB=ff IOC=00 IOD=26 IOF=01 + * IOD[0] CX24116 1=enabled + * * E30 C Plus VID=1c73 PID=861f HW=15 FW=1.2 "anysee-FA(LP)" * PCB: 507FA (rev0.4) * parts: TDA10023, DTOS403IH102B TM, TDA8024 @@ -448,6 +470,19 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) adap->fe = dvb_attach(tda10023_attach, &anysee_tda10023_config, &adap->dev->i2c_adap, 0x48); + break; + case ANYSEE_HW_507SI: /* 11 */ + /* E30 S2 Plus */ + + /* enable DVB-S/S2 demod on IOD[0] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 0), 0x01); + if (ret) + goto error; + + /* attach demod */ + adap->fe = dvb_attach(cx24116_attach, &anysee_cx24116_config, + &adap->dev->i2c_adap); + break; case ANYSEE_HW_507FA: /* 15 */ /* E30 Combo Plus */ @@ -624,6 +659,14 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) fe = dvb_attach(dvb_pll_attach, adap->fe, (0xc0 >> 1), &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A); + break; + case ANYSEE_HW_507SI: /* 11 */ + /* E30 S2 Plus */ + + /* attach LNB controller */ + fe = dvb_attach(isl6423_attach, adap->fe, &adap->dev->i2c_adap, + &anysee_isl6423_config); + break; case ANYSEE_HW_507FA: /* 15 */ /* E30 Combo Plus */ -- cgit v1.2.3 From bedbf3d1451dbecd7a46ffbc6ece28561673b748 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Fri, 29 Apr 2011 13:55:02 -0300 Subject: [media] anysee: add support for Anysee E7 S2 It is DVB-S/S2 USB box. * DNBU10512IST NIM * STV0903 demod * STV6110 tuner * Intersil ISL6423 LNB controller Signed-off-by: Antti Palosaari <crope@iki.fi> Cc: info@anysee.com Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/Kconfig | 2 ++ drivers/media/dvb/dvb-usb/anysee.c | 60 ++++++++++++++++++++++++++++++++++++++ drivers/media/dvb/dvb-usb/anysee.h | 1 + 3 files changed, 63 insertions(+) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig index 9931ec95d900..e85304c59a2b 100644 --- a/drivers/media/dvb/dvb-usb/Kconfig +++ b/drivers/media/dvb/dvb-usb/Kconfig @@ -294,6 +294,8 @@ config DVB_USB_ANYSEE select DVB_TDA10023 if !DVB_FE_CUSTOMISE select MEDIA_TUNER_TDA18212 if !MEDIA_TUNER_CUSTOMISE select DVB_CX24116 if !DVB_FE_CUSTOMISE + select DVB_STV0900 if !DVB_FE_CUSTOMISE + select DVB_STV6110 if !DVB_FE_CUSTOMISE select DVB_ISL6423 if !DVB_FE_CUSTOMISE help Say Y here to support the Anysee E30, Anysee E30 Plus or diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c index ebcc05b73c7f..4dc1ca333236 100644 --- a/drivers/media/dvb/dvb-usb/anysee.c +++ b/drivers/media/dvb/dvb-usb/anysee.c @@ -38,6 +38,8 @@ #include "zl10353.h" #include "tda18212.h" #include "cx24116.h" +#include "stv0900.h" +#include "stv6110.h" #include "isl6423.h" /* debug */ @@ -308,6 +310,23 @@ static struct cx24116_config anysee_cx24116_config = { .i2c_wr_max = 48, }; +static struct stv0900_config anysee_stv0900_config = { + .demod_address = (0xd0 >> 1), + .demod_mode = 0, + .xtal = 8000000, + .clkmode = 3, + .diseqc_mode = 2, + .tun1_maddress = 0, + .tun1_adc = 1, /* 1 Vpp */ + .path1_mode = 3, +}; + +static struct stv6110_config anysee_stv6110_config = { + .i2c_address = (0xc0 >> 1), + .mclk = 16000000, + .clk_div = 1, +}; + static struct isl6423_config anysee_isl6423_config = { .current_max = SEC_CURRENT_800m, .curlim = SEC_CURRENT_LIM_OFF, @@ -386,6 +405,15 @@ static struct isl6423_config anysee_isl6423_config = { * IOD[5] TDA10023 0=disabled * IOD[6] ZL10353 1=enabled * IOE[0] IF 0=enabled + * + * E7 S2 VID=1c73 PID=861f HW=19 FW=0.4 AMTCI=0.5 "anysee-E7S2(LP)" + * PCB: 508S2 (rev0.7) + * parts: DNBU10512IST(STV0903, STV6110), ISL6423 + * OEA=80 OEB=00 OEC=03 OED=f7 OEF=ff + * IOA=4d IOB=00 IOC=c4 IOD=08 IOF=e4 + * IOA[7] TS 1=enabled + * IOE[5] STV0903 1=enabled + * */ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) @@ -615,6 +643,24 @@ static int anysee_frontend_attach(struct dvb_usb_adapter *adap) &adap->dev->i2c_adap, 0x48); } + break; + case ANYSEE_HW_508S2: /* 19 */ + /* E7 S2 */ + + /* enable transport stream on IOA[7] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOA, (1 << 7), 0x80); + if (ret) + goto error; + + /* enable DVB-S/S2 demod on IOE[5] */ + ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 5), 0x20); + if (ret) + goto error; + + /* attach demod */ + adap->fe = dvb_attach(stv0900_attach, &anysee_stv0900_config, + &adap->dev->i2c_adap, 0); + break; } @@ -722,6 +768,20 @@ static int anysee_tuner_attach(struct dvb_usb_adapter *adap) fe = dvb_attach(tda18212_attach, adap->fe, &adap->dev->i2c_adap, &anysee_tda18212_config); + break; + case ANYSEE_HW_508S2: /* 19 */ + /* E7 S2 */ + + /* attach tuner */ + fe = dvb_attach(stv6110_attach, adap->fe, + &anysee_stv6110_config, &adap->dev->i2c_adap); + + if (fe) { + /* attach LNB controller */ + fe = dvb_attach(isl6423_attach, adap->fe, + &adap->dev->i2c_adap, &anysee_isl6423_config); + } + break; default: fe = NULL; diff --git a/drivers/media/dvb/dvb-usb/anysee.h b/drivers/media/dvb/dvb-usb/anysee.h index c6181047b978..a7673aa1e007 100644 --- a/drivers/media/dvb/dvb-usb/anysee.h +++ b/drivers/media/dvb/dvb-usb/anysee.h @@ -67,6 +67,7 @@ struct anysee_state { #define ANYSEE_HW_507SI 11 /* E30 S2 Plus */ #define ANYSEE_HW_507FA 15 /* E30 Combo Plus / E30 C Plus */ #define ANYSEE_HW_508TC 18 /* E7 TC */ +#define ANYSEE_HW_508S2 19 /* E7 S2 */ #define REG_IOA 0x80 /* Port A (bit addressable) */ #define REG_IOB 0x90 /* Port B (bit addressable) */ -- cgit v1.2.3 From e0bae9b33a406465bce6f38e9aaeef1ebfcfb461 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Wed, 4 May 2011 17:23:09 -0300 Subject: [media] cx24116: make FW DL split more readable Change firmware download split, which I introduced few patch earlier, a little bit to make it more readable as requested [1]. Anyhow, for some reason this seems to increase compiled binary size 52 bytes, on my AMD64 box, which is rather much for so small change. [1] http://www.spinics.net/lists/linux-media/msg31968.html Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/cx24116.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/cx24116.c b/drivers/media/dvb/frontends/cx24116.c index 26e65a66719a..95c6465b87a1 100644 --- a/drivers/media/dvb/frontends/cx24116.c +++ b/drivers/media/dvb/frontends/cx24116.c @@ -566,7 +566,7 @@ static int cx24116_load_firmware(struct dvb_frontend *fe, { struct cx24116_state *state = fe->demodulator_priv; struct cx24116_cmd cmd; - int i, ret, len, remaining; + int i, ret, len, max, remaining; unsigned char vers[4]; dprintk("%s\n", __func__); @@ -604,14 +604,16 @@ static int cx24116_load_firmware(struct dvb_frontend *fe, cx24116_writereg(state, 0xF6, 0x00); /* Split firmware to the max I2C write len and write. - * This overflows 16 bit intentionally in order to get max write - * len when i2c_wr_max is set to 0. */ - for (remaining = fw->size; remaining > 0; - remaining -= (u16) (state->config->i2c_wr_max - 1)) { + * Writes whole firmware as one write when i2c_wr_max is set to 0. */ + if (state->config->i2c_wr_max) + max = state->config->i2c_wr_max; + else + max = INT_MAX; /* enough for 32k firmware */ + for (remaining = fw->size; remaining > 0; remaining -= max - 1) { len = remaining; - if (len > (u16) (state->config->i2c_wr_max - 1)) - len = (u16) (state->config->i2c_wr_max - 1); + if (len > max - 1) + len = max - 1; cx24116_writeregN(state, 0xF7, &fw->data[fw->size - remaining], len); -- cgit v1.2.3 From 27cfc85e3dae187a470f7aa54123689a487970f2 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Thu, 7 Apr 2011 16:27:43 -0300 Subject: [media] Sony CXD2820R DVB-T/T2/C demodulator driver It is very first DVB-T2 Linux driver! Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/Kconfig | 7 + drivers/media/dvb/frontends/Makefile | 2 + drivers/media/dvb/frontends/cxd2820r.c | 886 ++++++++++++++++++++++++++++ drivers/media/dvb/frontends/cxd2820r.h | 118 ++++ drivers/media/dvb/frontends/cxd2820r_c.c | 336 +++++++++++ drivers/media/dvb/frontends/cxd2820r_priv.h | 77 +++ drivers/media/dvb/frontends/cxd2820r_t.c | 447 ++++++++++++++ drivers/media/dvb/frontends/cxd2820r_t2.c | 421 +++++++++++++ 8 files changed, 2294 insertions(+) create mode 100644 drivers/media/dvb/frontends/cxd2820r.c create mode 100644 drivers/media/dvb/frontends/cxd2820r.h create mode 100644 drivers/media/dvb/frontends/cxd2820r_c.c create mode 100644 drivers/media/dvb/frontends/cxd2820r_priv.h create mode 100644 drivers/media/dvb/frontends/cxd2820r_t.c create mode 100644 drivers/media/dvb/frontends/cxd2820r_t2.c (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig index 7ceb02d95ecf..44b816f2601e 100644 --- a/drivers/media/dvb/frontends/Kconfig +++ b/drivers/media/dvb/frontends/Kconfig @@ -383,6 +383,13 @@ config DVB_STV0367 help A DVB-T/C tuner module. Say Y when you want to support this frontend. +config DVB_CXD2820R + tristate "Sony CXD2820R" + depends on DVB_CORE && I2C + default m if DVB_FE_CUSTOMISE + help + Say Y when you want to support this frontend. + comment "DVB-C (cable) frontends" depends on DVB_CORE diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile index 6d5192935889..adec1a3f6291 100644 --- a/drivers/media/dvb/frontends/Makefile +++ b/drivers/media/dvb/frontends/Makefile @@ -86,3 +86,5 @@ obj-$(CONFIG_DVB_MB86A16) += mb86a16.o obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o obj-$(CONFIG_DVB_IX2505V) += ix2505v.o obj-$(CONFIG_DVB_STV0367) += stv0367.o +obj-$(CONFIG_DVB_CXD2820R) += cxd2820r.o + diff --git a/drivers/media/dvb/frontends/cxd2820r.c b/drivers/media/dvb/frontends/cxd2820r.c new file mode 100644 index 000000000000..b58f92c75116 --- /dev/null +++ b/drivers/media/dvb/frontends/cxd2820r.c @@ -0,0 +1,886 @@ +/* + * Sony CXD2820R demodulator driver + * + * Copyright (C) 2010 Antti Palosaari <crope@iki.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#include "cxd2820r_priv.h" + +int cxd2820r_debug; +module_param_named(debug, cxd2820r_debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); + +/* TODO: temporary hack, will be removed later when there is app support */ +unsigned int cxd2820r_dvbt2_freq[5]; +int cxd2820r_dvbt2_count; +module_param_array_named(dvbt2_freq, cxd2820r_dvbt2_freq, int, + &cxd2820r_dvbt2_count, 0644); +MODULE_PARM_DESC(dvbt2_freq, "RF frequencies forced to DVB-T2 (unit Hz)"); + +/* write multiple registers */ +static int cxd2820r_wr_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg, + u8 *val, int len) +{ + int ret; + u8 buf[len+1]; + struct i2c_msg msg[1] = { + { + .addr = i2c, + .flags = 0, + .len = sizeof(buf), + .buf = buf, + } + }; + + buf[0] = reg; + memcpy(&buf[1], val, len); + + ret = i2c_transfer(priv->i2c, msg, 1); + if (ret == 1) { + ret = 0; + } else { + warn("i2c wr failed ret:%d reg:%02x len:%d", ret, reg, len); + ret = -EREMOTEIO; + } + return ret; +} + +/* read multiple registers */ +static int cxd2820r_rd_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg, + u8 *val, int len) +{ + int ret; + u8 buf[len]; + struct i2c_msg msg[2] = { + { + .addr = i2c, + .flags = 0, + .len = 1, + .buf = ®, + }, { + .addr = i2c, + .flags = I2C_M_RD, + .len = sizeof(buf), + .buf = buf, + } + }; + + ret = i2c_transfer(priv->i2c, msg, 2); + if (ret == 2) { + memcpy(val, buf, len); + ret = 0; + } else { + warn("i2c rd failed ret:%d reg:%02x len:%d", ret, reg, len); + ret = -EREMOTEIO; + } + + return ret; +} + +/* write multiple registers */ +static int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, + int len) +{ + int ret; + u8 i2c_addr; + u8 reg = (reginfo >> 0) & 0xff; + u8 bank = (reginfo >> 8) & 0xff; + u8 i2c = (reginfo >> 16) & 0x01; + + /* select I2C */ + if (i2c) + i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */ + else + i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */ + + /* switch bank if needed */ + if (bank != priv->bank[i2c]) { + ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1); + if (ret) + return ret; + priv->bank[i2c] = bank; + } + return cxd2820r_wr_regs_i2c(priv, i2c_addr, reg, val, len); +} + +/* read multiple registers */ +static int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, + int len) +{ + int ret; + u8 i2c_addr; + u8 reg = (reginfo >> 0) & 0xff; + u8 bank = (reginfo >> 8) & 0xff; + u8 i2c = (reginfo >> 16) & 0x01; + + /* select I2C */ + if (i2c) + i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */ + else + i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */ + + /* switch bank if needed */ + if (bank != priv->bank[i2c]) { + ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1); + if (ret) + return ret; + priv->bank[i2c] = bank; + } + return cxd2820r_rd_regs_i2c(priv, i2c_addr, reg, val, len); +} + +/* write single register */ +static int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val) +{ + return cxd2820r_wr_regs(priv, reg, &val, 1); +} + +/* read single register */ +static int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val) +{ + return cxd2820r_rd_regs(priv, reg, val, 1); +} + +/* write single register with mask */ +static int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val, + u8 mask) +{ + int ret; + u8 tmp; + + /* no need for read if whole reg is written */ + if (mask != 0xff) { + ret = cxd2820r_rd_reg(priv, reg, &tmp); + if (ret) + return ret; + + val &= mask; + tmp &= ~mask; + val |= tmp; + } + + return cxd2820r_wr_reg(priv, reg, val); +} + +static int cxd2820r_gpio(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret, i; + u8 *gpio, tmp0, tmp1; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + gpio = priv->cfg.gpio_dvbt; + break; + case SYS_DVBT2: + gpio = priv->cfg.gpio_dvbt2; + break; + case SYS_DVBC_ANNEX_AC: + gpio = priv->cfg.gpio_dvbc; + break; + default: + ret = -EINVAL; + goto error; + } + + /* update GPIOs only when needed */ + if (!memcmp(gpio, priv->gpio, sizeof(priv->gpio))) + return 0; + + tmp0 = 0x00; + tmp1 = 0x00; + for (i = 0; i < sizeof(priv->gpio); i++) { + /* enable / disable */ + if (gpio[i] & CXD2820R_GPIO_E) + tmp0 |= (2 << 6) >> (2 * i); + else + tmp0 |= (1 << 6) >> (2 * i); + + /* input / output */ + if (gpio[i] & CXD2820R_GPIO_I) + tmp1 |= (1 << (3 + i)); + else + tmp1 |= (0 << (3 + i)); + + /* high / low */ + if (gpio[i] & CXD2820R_GPIO_H) + tmp1 |= (1 << (0 + i)); + else + tmp1 |= (0 << (0 + i)); + + dbg("%s: GPIO i=%d %02x %02x", __func__, i, tmp0, tmp1); + } + + dbg("%s: wr gpio=%02x %02x", __func__, tmp0, tmp1); + + /* write bits [7:2] */ + ret = cxd2820r_wr_reg_mask(priv, 0x00089, tmp0, 0xfc); + if (ret) + goto error; + + /* write bits [5:0] */ + ret = cxd2820r_wr_reg_mask(priv, 0x0008e, tmp1, 0x3f); + if (ret) + goto error; + + memcpy(priv->gpio, gpio, sizeof(priv->gpio)); + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +/* lock FE */ +static int cxd2820r_lock(struct cxd2820r_priv *priv, int active_fe) +{ + int ret = 0; + dbg("%s: active_fe=%d", __func__, active_fe); + + mutex_lock(&priv->fe_lock); + + /* -1=NONE, 0=DVB-T/T2, 1=DVB-C */ + if (priv->active_fe == active_fe) + ; + else if (priv->active_fe == -1) + priv->active_fe = active_fe; + else + ret = -EBUSY; + + mutex_unlock(&priv->fe_lock); + + return ret; +} + +/* unlock FE */ +static void cxd2820r_unlock(struct cxd2820r_priv *priv, int active_fe) +{ + dbg("%s: active_fe=%d", __func__, active_fe); + + mutex_lock(&priv->fe_lock); + + /* -1=NONE, 0=DVB-T/T2, 1=DVB-C */ + if (priv->active_fe == active_fe) + priv->active_fe = -1; + + mutex_unlock(&priv->fe_lock); + + return; +} + +/* 64 bit div with round closest, like DIV_ROUND_CLOSEST but 64 bit */ +static u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor) +{ + return div_u64(dividend + (divisor / 2), divisor); +} + +/* TODO: ... */ +#include "cxd2820r_t.c" +#include "cxd2820r_c.c" +#include "cxd2820r_t2.c" + +static int cxd2820r_set_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (priv->delivery_system) { + case SYS_UNDEFINED: + if (c->delivery_system == SYS_DVBT) { + /* SLEEP => DVB-T */ + ret = cxd2820r_set_frontend_t(fe, p); + } else { + /* SLEEP => DVB-T2 */ + ret = cxd2820r_set_frontend_t2(fe, p); + } + break; + case SYS_DVBT: + if (c->delivery_system == SYS_DVBT) { + /* DVB-T => DVB-T */ + ret = cxd2820r_set_frontend_t(fe, p); + } else if (c->delivery_system == SYS_DVBT2) { + /* DVB-T => DVB-T2 */ + ret = cxd2820r_sleep_t(fe); + ret = cxd2820r_set_frontend_t2(fe, p); + } + break; + case SYS_DVBT2: + if (c->delivery_system == SYS_DVBT2) { + /* DVB-T2 => DVB-T2 */ + ret = cxd2820r_set_frontend_t2(fe, p); + } else if (c->delivery_system == SYS_DVBT) { + /* DVB-T2 => DVB-T */ + ret = cxd2820r_sleep_t2(fe); + ret = cxd2820r_set_frontend_t(fe, p); + } + break; + default: + dbg("%s: error state=%d", __func__, + priv->delivery_system); + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_set_frontend_c(fe, p); + } + + return ret; +} + +static int cxd2820r_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_read_status_t(fe, status); + break; + case SYS_DVBT2: + ret = cxd2820r_read_status_t2(fe, status); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_read_status_c(fe, status); + } + + return ret; +} + +static int cxd2820r_get_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_get_frontend_t(fe, p); + break; + case SYS_DVBT2: + ret = cxd2820r_get_frontend_t2(fe, p); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_get_frontend_c(fe, p); + } + + return ret; +} + +static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_read_ber_t(fe, ber); + break; + case SYS_DVBT2: + ret = cxd2820r_read_ber_t2(fe, ber); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_read_ber_c(fe, ber); + } + + return ret; +} + +static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_read_signal_strength_t(fe, strength); + break; + case SYS_DVBT2: + ret = cxd2820r_read_signal_strength_t2(fe, strength); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_read_signal_strength_c(fe, strength); + } + + return ret; +} + +static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_read_snr_t(fe, snr); + break; + case SYS_DVBT2: + ret = cxd2820r_read_snr_t2(fe, snr); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_read_snr_c(fe, snr); + } + + return ret; +} + +static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_read_ucblocks_t(fe, ucblocks); + break; + case SYS_DVBT2: + ret = cxd2820r_read_ucblocks_t2(fe, ucblocks); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_read_ucblocks_c(fe, ucblocks); + } + + return ret; +} + +static int cxd2820r_init(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + priv->delivery_system = SYS_UNDEFINED; + /* delivery system is unknown at that (init) phase */ + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + ret = cxd2820r_init_t(fe); + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_init_c(fe); + } + + return ret; +} + +static int cxd2820r_sleep(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_sleep_t(fe); + break; + case SYS_DVBT2: + ret = cxd2820r_sleep_t2(fe); + break; + default: + ret = -EINVAL; + } + + cxd2820r_unlock(priv, 0); + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_sleep_c(fe); + + cxd2820r_unlock(priv, 1); + } + + return ret; +} + +static int cxd2820r_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *s) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret, i; + unsigned int rf1, rf2; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + /* TODO: hack! This will be removed later when there is better + * app support for DVB-T2... */ + + /* Hz => MHz */ + rf1 = DIV_ROUND_CLOSEST(fe->dtv_property_cache.frequency, + 1000000); + for (i = 0; i < cxd2820r_dvbt2_count; i++) { + if (cxd2820r_dvbt2_freq[i] > 100000000) { + /* Hz => MHz */ + rf2 = DIV_ROUND_CLOSEST(cxd2820r_dvbt2_freq[i], + 1000000); + } else if (cxd2820r_dvbt2_freq[i] > 100000) { + /* kHz => MHz */ + rf2 = DIV_ROUND_CLOSEST(cxd2820r_dvbt2_freq[i], + 1000); + } else { + rf2 = cxd2820r_dvbt2_freq[i]; + } + + dbg("%s: rf1=%d rf2=%d", __func__, rf1, rf2); + + if (rf1 == rf2) { + dbg("%s: forcing DVB-T2, frequency=%d", + __func__, fe->dtv_property_cache.frequency); + fe->dtv_property_cache.delivery_system = + SYS_DVBT2; + } + } + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_get_tune_settings_t(fe, s); + break; + case SYS_DVBT2: + ret = cxd2820r_get_tune_settings_t2(fe, s); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_get_tune_settings_c(fe, s); + } + + return ret; +} + +static void cxd2820r_release(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + dbg("%s", __func__); + + if (fe->ops.info.type == FE_OFDM) { + i2c_del_adapter(&priv->tuner_i2c_adapter); + kfree(priv); + } + + return; +} + +static u32 cxd2820r_tuner_i2c_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_I2C; +} + +static int cxd2820r_tuner_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg msg[], int num) +{ + struct cxd2820r_priv *priv = i2c_get_adapdata(i2c_adap); + u8 obuf[msg[0].len + 2]; + struct i2c_msg msg2[2] = { + { + .addr = priv->cfg.i2c_address, + .flags = 0, + .len = sizeof(obuf), + .buf = obuf, + }, { + .addr = priv->cfg.i2c_address, + .flags = I2C_M_RD, + .len = msg[1].len, + .buf = msg[1].buf, + } + }; + + obuf[0] = 0x09; + obuf[1] = (msg[0].addr << 1); + if (num == 2) { /* I2C read */ + obuf[1] = (msg[0].addr << 1) | I2C_M_RD; /* I2C RD flag */ + msg2[0].len = sizeof(obuf) - 1; /* maybe HW bug ? */ + } + memcpy(&obuf[2], msg[0].buf, msg[0].len); + + return i2c_transfer(priv->i2c, msg2, num); +} + +static struct i2c_algorithm cxd2820r_tuner_i2c_algo = { + .master_xfer = cxd2820r_tuner_i2c_xfer, + .functionality = cxd2820r_tuner_i2c_func, +}; + +struct i2c_adapter *cxd2820r_get_tuner_i2c_adapter(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + return &priv->tuner_i2c_adapter; +} +EXPORT_SYMBOL(cxd2820r_get_tuner_i2c_adapter); + +static struct dvb_frontend_ops cxd2820r_ops[2]; + +struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg, + struct i2c_adapter *i2c, struct dvb_frontend *fe) +{ + int ret; + struct cxd2820r_priv *priv = NULL; + u8 tmp; + + if (fe == NULL) { + /* FE0 */ + /* allocate memory for the internal priv */ + priv = kzalloc(sizeof(struct cxd2820r_priv), GFP_KERNEL); + if (priv == NULL) + goto error; + + /* setup the priv */ + priv->i2c = i2c; + memcpy(&priv->cfg, cfg, sizeof(struct cxd2820r_config)); + mutex_init(&priv->fe_lock); + + priv->active_fe = -1; /* NONE */ + + /* check if the demod is there */ + priv->bank[0] = priv->bank[1] = 0xff; + ret = cxd2820r_rd_reg(priv, 0x000fd, &tmp); + dbg("%s: chip id=%02x", __func__, tmp); + if (ret || tmp != 0xe1) + goto error; + + /* create frontends */ + memcpy(&priv->fe[0].ops, &cxd2820r_ops[0], + sizeof(struct dvb_frontend_ops)); + memcpy(&priv->fe[1].ops, &cxd2820r_ops[1], + sizeof(struct dvb_frontend_ops)); + + priv->fe[0].demodulator_priv = priv; + priv->fe[1].demodulator_priv = priv; + + /* create tuner i2c adapter */ + strlcpy(priv->tuner_i2c_adapter.name, + "CXD2820R tuner I2C adapter", + sizeof(priv->tuner_i2c_adapter.name)); + priv->tuner_i2c_adapter.algo = &cxd2820r_tuner_i2c_algo; + priv->tuner_i2c_adapter.algo_data = NULL; + i2c_set_adapdata(&priv->tuner_i2c_adapter, priv); + if (i2c_add_adapter(&priv->tuner_i2c_adapter) < 0) { + err("tuner I2C bus could not be initialized"); + goto error; + } + + return &priv->fe[0]; + + } else { + /* FE1: FE0 given as pointer, just return FE1 we have + * already created */ + priv = fe->demodulator_priv; + return &priv->fe[1]; + } + +error: + kfree(priv); + return NULL; +} +EXPORT_SYMBOL(cxd2820r_attach); + +static struct dvb_frontend_ops cxd2820r_ops[2] = { + { + /* DVB-T/T2 */ + .info = { + .name = "Sony CXD2820R (DVB-T/T2)", + .type = FE_OFDM, + .caps = + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | + FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_QPSK | FE_CAN_QAM_16 | + FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | + FE_CAN_HIERARCHY_AUTO | + FE_CAN_MUTE_TS | + FE_CAN_2G_MODULATION + }, + + .release = cxd2820r_release, + .init = cxd2820r_init, + .sleep = cxd2820r_sleep, + + .get_tune_settings = cxd2820r_get_tune_settings, + + .set_frontend = cxd2820r_set_frontend, + .get_frontend = cxd2820r_get_frontend, + + .read_status = cxd2820r_read_status, + .read_snr = cxd2820r_read_snr, + .read_ber = cxd2820r_read_ber, + .read_ucblocks = cxd2820r_read_ucblocks, + .read_signal_strength = cxd2820r_read_signal_strength, + }, + { + /* DVB-C */ + .info = { + .name = "Sony CXD2820R (DVB-C)", + .type = FE_QAM, + .caps = + FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | + FE_CAN_FEC_AUTO + }, + + .release = cxd2820r_release, + .init = cxd2820r_init, + .sleep = cxd2820r_sleep, + + .get_tune_settings = cxd2820r_get_tune_settings, + + .set_frontend = cxd2820r_set_frontend, + .get_frontend = cxd2820r_get_frontend, + + .read_status = cxd2820r_read_status, + .read_snr = cxd2820r_read_snr, + .read_ber = cxd2820r_read_ber, + .read_ucblocks = cxd2820r_read_ucblocks, + .read_signal_strength = cxd2820r_read_signal_strength, + }, +}; + + +MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); +MODULE_DESCRIPTION("Sony CXD2820R demodulator driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb/frontends/cxd2820r.h b/drivers/media/dvb/frontends/cxd2820r.h new file mode 100644 index 000000000000..ad17845123d9 --- /dev/null +++ b/drivers/media/dvb/frontends/cxd2820r.h @@ -0,0 +1,118 @@ +/* + * Sony CXD2820R demodulator driver + * + * Copyright (C) 2010 Antti Palosaari <crope@iki.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#ifndef CXD2820R_H +#define CXD2820R_H + +#include <linux/dvb/frontend.h> + +#define CXD2820R_GPIO_D (0 << 0) /* disable */ +#define CXD2820R_GPIO_E (1 << 0) /* enable */ +#define CXD2820R_GPIO_O (0 << 1) /* output */ +#define CXD2820R_GPIO_I (1 << 1) /* input */ +#define CXD2820R_GPIO_L (0 << 2) /* output low */ +#define CXD2820R_GPIO_H (1 << 2) /* output high */ + +#define CXD2820R_TS_SERIAL 0x08 +#define CXD2820R_TS_SERIAL_MSB 0x28 +#define CXD2820R_TS_PARALLEL 0x30 +#define CXD2820R_TS_PARALLEL_MSB 0x70 + +struct cxd2820r_config { + /* Demodulator I2C address. + * Driver determines DVB-C slave I2C address automatically from master + * address. + * Default: none, must set + * Values: 0x6c, 0x6d + */ + u8 i2c_address; + + /* TS output mode. + * Default: none, must set. + * Values: + */ + u8 ts_mode; + + /* IF AGC polarity. + * Default: 0 + * Values: 0, 1 + */ + int if_agc_polarity:1; + + /* Spectrum inversion. + * Default: 0 + * Values: 0, 1 + */ + int spec_inv:1; + + /* IFs for all used modes. + * Default: none, must set + * Values: <kHz> + */ + u16 if_dvbt_6; + u16 if_dvbt_7; + u16 if_dvbt_8; + u16 if_dvbt2_5; + u16 if_dvbt2_6; + u16 if_dvbt2_7; + u16 if_dvbt2_8; + u16 if_dvbc; + + /* GPIOs for all used modes. + * Default: none, disabled + * Values: <see above> + */ + u8 gpio_dvbt[3]; + u8 gpio_dvbt2[3]; + u8 gpio_dvbc[3]; +}; + + +#if defined(CONFIG_DVB_CXD2820R) || \ + (defined(CONFIG_DVB_CXD2820R_MODULE) && defined(MODULE)) +extern struct dvb_frontend *cxd2820r_attach( + const struct cxd2820r_config *config, + struct i2c_adapter *i2c, + struct dvb_frontend *fe +); +extern struct i2c_adapter *cxd2820r_get_tuner_i2c_adapter( + struct dvb_frontend *fe +); +#else +static inline struct dvb_frontend *cxd2820r_attach( + const struct cxd2820r_config *config, + struct i2c_adapter *i2c, + struct dvb_frontend *fe +) +{ + printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); + return NULL; +} +static inline struct i2c_adapter *cxd2820r_get_tuner_i2c_adapter( + struct dvb_frontend *fe +) +{ + return NULL; +} + +#endif + +#endif /* CXD2820R_H */ diff --git a/drivers/media/dvb/frontends/cxd2820r_c.c b/drivers/media/dvb/frontends/cxd2820r_c.c new file mode 100644 index 000000000000..a94bff944722 --- /dev/null +++ b/drivers/media/dvb/frontends/cxd2820r_c.c @@ -0,0 +1,336 @@ +/* + * Sony CXD2820R demodulator driver + * + * Copyright (C) 2010 Antti Palosaari <crope@iki.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +static int cxd2820r_set_frontend_c(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret, i; + u8 buf[2]; + u16 if_ctl; + u64 num; + struct reg_val_mask tab[] = { + { 0x00080, 0x01, 0xff }, + { 0x00081, 0x05, 0xff }, + { 0x00085, 0x07, 0xff }, + { 0x00088, 0x01, 0xff }, + + { 0x00082, 0x20, 0x60 }, + { 0x1016a, 0x48, 0xff }, + { 0x100a5, 0x00, 0x01 }, + { 0x10020, 0x06, 0x07 }, + { 0x10059, 0x50, 0xff }, + { 0x10087, 0x0c, 0x3c }, + { 0x1008b, 0x07, 0xff }, + { 0x1001f, priv->cfg.if_agc_polarity << 7, 0x80 }, + { 0x10070, priv->cfg.ts_mode, 0xff }, + }; + + dbg("%s: RF=%d SR=%d", __func__, c->frequency, c->symbol_rate); + + /* update GPIOs */ + ret = cxd2820r_gpio(fe); + if (ret) + goto error; + + /* program tuner */ + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe, params); + + if (priv->delivery_system != SYS_DVBC_ANNEX_AC) { + for (i = 0; i < ARRAY_SIZE(tab); i++) { + ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, + tab[i].val, tab[i].mask); + if (ret) + goto error; + } + } + + priv->delivery_system = SYS_DVBC_ANNEX_AC; + priv->ber_running = 0; /* tune stops BER counter */ + + num = priv->cfg.if_dvbc; + num *= 0x4000; + if_ctl = cxd2820r_div_u64_round_closest(num, 41000); + buf[0] = (if_ctl >> 8) & 0x3f; + buf[1] = (if_ctl >> 0) & 0xff; + + ret = cxd2820r_wr_regs(priv, 0x10042, buf, 2); + if (ret) + goto error; + + ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08); + if (ret) + goto error; + + ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01); + if (ret) + goto error; + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_get_frontend_c(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret; + u8 buf[2]; + + ret = cxd2820r_rd_regs(priv, 0x1001a, buf, 2); + if (ret) + goto error; + + c->symbol_rate = 2500 * ((buf[0] & 0x0f) << 8 | buf[1]); + + ret = cxd2820r_rd_reg(priv, 0x10019, &buf[0]); + if (ret) + goto error; + + switch ((buf[0] >> 0) & 0x03) { + case 0: + c->modulation = QAM_16; + break; + case 1: + c->modulation = QAM_32; + break; + case 2: + c->modulation = QAM_64; + break; + case 3: + c->modulation = QAM_128; + break; + case 4: + c->modulation = QAM_256; + break; + } + + switch ((buf[0] >> 7) & 0x01) { + case 0: + c->inversion = INVERSION_OFF; + break; + case 1: + c->inversion = INVERSION_ON; + break; + } + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_ber_c(struct dvb_frontend *fe, u32 *ber) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 buf[3], start_ber = 0; + *ber = 0; + + if (priv->ber_running) { + ret = cxd2820r_rd_regs(priv, 0x10076, buf, sizeof(buf)); + if (ret) + goto error; + + if ((buf[2] >> 7) & 0x01 || (buf[2] >> 4) & 0x01) { + *ber = (buf[2] & 0x0f) << 16 | buf[1] << 8 | buf[0]; + start_ber = 1; + } + } else { + priv->ber_running = 1; + start_ber = 1; + } + + if (start_ber) { + /* (re)start BER */ + ret = cxd2820r_wr_reg(priv, 0x10079, 0x01); + if (ret) + goto error; + } + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_signal_strength_c(struct dvb_frontend *fe, + u16 *strength) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 buf[2]; + u16 tmp; + + ret = cxd2820r_rd_regs(priv, 0x10049, buf, sizeof(buf)); + if (ret) + goto error; + + tmp = (buf[0] & 0x03) << 8 | buf[1]; + tmp = (~tmp & 0x03ff); + + if (tmp == 512) + /* ~no signal */ + tmp = 0; + else if (tmp > 350) + tmp = 350; + + /* scale value to 0x0000-0xffff */ + *strength = tmp * 0xffff / (350-0); + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_snr_c(struct dvb_frontend *fe, u16 *snr) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 tmp; + unsigned int A, B; + /* report SNR in dB * 10 */ + + ret = cxd2820r_rd_reg(priv, 0x10019, &tmp); + if (ret) + goto error; + + if (((tmp >> 0) & 0x03) % 2) { + A = 875; + B = 650; + } else { + A = 950; + B = 760; + } + + ret = cxd2820r_rd_reg(priv, 0x1004d, &tmp); + if (ret) + goto error; + + #define CXD2820R_LOG2_E_24 24204406 /* log2(e) << 24 */ + if (tmp) + *snr = A * (intlog2(B / tmp) >> 5) / (CXD2820R_LOG2_E_24 >> 5) + / 10; + else + *snr = 0; + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_ucblocks_c(struct dvb_frontend *fe, u32 *ucblocks) +{ + *ucblocks = 0; + /* no way to read ? */ + return 0; +} + +static int cxd2820r_read_status_c(struct dvb_frontend *fe, fe_status_t *status) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 buf[2]; + *status = 0; + + ret = cxd2820r_rd_regs(priv, 0x10088, buf, sizeof(buf)); + if (ret) + goto error; + + if (((buf[0] >> 0) & 0x01) == 1) { + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | + FE_HAS_VITERBI | FE_HAS_SYNC; + + if (((buf[1] >> 3) & 0x01) == 1) { + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | + FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; + } + } + + dbg("%s: lock=%02x %02x", __func__, buf[0], buf[1]); + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_init_c(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + + ret = cxd2820r_wr_reg(priv, 0x00085, 0x07); + if (ret) + goto error; + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_sleep_c(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret, i; + struct reg_val_mask tab[] = { + { 0x000ff, 0x1f, 0xff }, + { 0x00085, 0x00, 0xff }, + { 0x00088, 0x01, 0xff }, + { 0x00081, 0x00, 0xff }, + { 0x00080, 0x00, 0xff }, + }; + + dbg("%s", __func__); + + priv->delivery_system = SYS_UNDEFINED; + + for (i = 0; i < ARRAY_SIZE(tab); i++) { + ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val, + tab[i].mask); + if (ret) + goto error; + } + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_get_tune_settings_c(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *s) +{ + s->min_delay_ms = 500; + s->step_size = 0; /* no zigzag */ + s->max_drift = 0; + + return 0; +} + diff --git a/drivers/media/dvb/frontends/cxd2820r_priv.h b/drivers/media/dvb/frontends/cxd2820r_priv.h new file mode 100644 index 000000000000..4d2d79969d91 --- /dev/null +++ b/drivers/media/dvb/frontends/cxd2820r_priv.h @@ -0,0 +1,77 @@ +/* + * Sony CXD2820R demodulator driver + * + * Copyright (C) 2010 Antti Palosaari <crope@iki.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#ifndef CXD2820R_PRIV_H +#define CXD2820R_PRIV_H + +#include "dvb_frontend.h" +#include "dvb_math.h" +#include "cxd2820r.h" + +#define LOG_PREFIX "cxd2820r" + +#undef dbg +#define dbg(f, arg...) \ + if (cxd2820r_debug) \ + printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg) +#undef err +#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg) +#undef info +#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg) +#undef warn +#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg) + +/* + * FIXME: These are totally wrong and must be added properly to the API. + * Only temporary solution in order to get driver compile. + */ +#define SYS_DVBT2 SYS_DAB +#define TRANSMISSION_MODE_1K 0 +#define TRANSMISSION_MODE_16K 0 +#define TRANSMISSION_MODE_32K 0 +#define GUARD_INTERVAL_1_128 0 +#define GUARD_INTERVAL_19_128 0 +#define GUARD_INTERVAL_19_256 0 + +struct reg_val_mask { + u32 reg; + u8 val; + u8 mask; +}; + +struct cxd2820r_priv { + struct i2c_adapter *i2c; + struct dvb_frontend fe[2]; + struct cxd2820r_config cfg; + struct i2c_adapter tuner_i2c_adapter; + + struct mutex fe_lock; /* FE lock */ + int active_fe:2; /* FE lock, -1=NONE, 0=DVB-T/T2, 1=DVB-C */ + + int ber_running:1; + + u8 bank[2]; + u8 gpio[3]; + + fe_delivery_system_t delivery_system; +}; + +#endif /* CXD2820R_PRIV_H */ diff --git a/drivers/media/dvb/frontends/cxd2820r_t.c b/drivers/media/dvb/frontends/cxd2820r_t.c new file mode 100644 index 000000000000..6732a9843f13 --- /dev/null +++ b/drivers/media/dvb/frontends/cxd2820r_t.c @@ -0,0 +1,447 @@ +/* + * Sony CXD2820R demodulator driver + * + * Copyright (C) 2010 Antti Palosaari <crope@iki.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +static int cxd2820r_set_frontend_t(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret, i; + u32 if_khz, if_ctl; + u64 num; + u8 buf[3], bw_param; + u8 bw_params1[][5] = { + { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */ + { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */ + { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */ + }; + u8 bw_params2[][2] = { + { 0x1f, 0xdc }, /* 6 MHz */ + { 0x12, 0xf8 }, /* 7 MHz */ + { 0x01, 0xe0 }, /* 8 MHz */ + }; + struct reg_val_mask tab[] = { + { 0x00080, 0x00, 0xff }, + { 0x00081, 0x03, 0xff }, + { 0x00085, 0x07, 0xff }, + { 0x00088, 0x01, 0xff }, + + { 0x00070, priv->cfg.ts_mode, 0xff }, + { 0x000cb, priv->cfg.if_agc_polarity << 6, 0x40 }, + { 0x000a5, 0x00, 0x01 }, + { 0x00082, 0x20, 0x60 }, + { 0x000c2, 0xc3, 0xff }, + { 0x0016a, 0x50, 0xff }, + { 0x00427, 0x41, 0xff }, + }; + + dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz); + + /* update GPIOs */ + ret = cxd2820r_gpio(fe); + if (ret) + goto error; + + /* program tuner */ + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe, p); + + if (priv->delivery_system != SYS_DVBT) { + for (i = 0; i < ARRAY_SIZE(tab); i++) { + ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, + tab[i].val, tab[i].mask); + if (ret) + goto error; + } + } + + priv->delivery_system = SYS_DVBT; + priv->ber_running = 0; /* tune stops BER counter */ + + switch (c->bandwidth_hz) { + case 6000000: + if_khz = priv->cfg.if_dvbt_6; + i = 0; + bw_param = 2; + break; + case 7000000: + if_khz = priv->cfg.if_dvbt_7; + i = 1; + bw_param = 1; + break; + case 8000000: + if_khz = priv->cfg.if_dvbt_8; + i = 2; + bw_param = 0; + break; + default: + return -EINVAL; + } + + num = if_khz; + num *= 0x1000000; + if_ctl = cxd2820r_div_u64_round_closest(num, 41000); + buf[0] = ((if_ctl >> 16) & 0xff); + buf[1] = ((if_ctl >> 8) & 0xff); + buf[2] = ((if_ctl >> 0) & 0xff); + + ret = cxd2820r_wr_regs(priv, 0x000b6, buf, 3); + if (ret) + goto error; + + ret = cxd2820r_wr_regs(priv, 0x0009f, bw_params1[i], 5); + if (ret) + goto error; + + ret = cxd2820r_wr_reg_mask(priv, 0x000d7, bw_param << 6, 0xc0); + if (ret) + goto error; + + ret = cxd2820r_wr_regs(priv, 0x000d9, bw_params2[i], 2); + if (ret) + goto error; + + ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08); + if (ret) + goto error; + + ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01); + if (ret) + goto error; + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_get_frontend_t(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret; + u8 buf[2]; + + ret = cxd2820r_rd_regs(priv, 0x0002f, buf, sizeof(buf)); + if (ret) + goto error; + + switch ((buf[0] >> 6) & 0x03) { + case 0: + c->modulation = QPSK; + break; + case 1: + c->modulation = QAM_16; + break; + case 2: + c->modulation = QAM_64; + break; + } + + switch ((buf[1] >> 1) & 0x03) { + case 0: + c->transmission_mode = TRANSMISSION_MODE_2K; + break; + case 1: + c->transmission_mode = TRANSMISSION_MODE_8K; + break; + } + + switch ((buf[1] >> 3) & 0x03) { + case 0: + c->guard_interval = GUARD_INTERVAL_1_32; + break; + case 1: + c->guard_interval = GUARD_INTERVAL_1_16; + break; + case 2: + c->guard_interval = GUARD_INTERVAL_1_8; + break; + case 3: + c->guard_interval = GUARD_INTERVAL_1_4; + break; + } + + switch ((buf[0] >> 3) & 0x07) { + case 0: + c->hierarchy = HIERARCHY_NONE; + break; + case 1: + c->hierarchy = HIERARCHY_1; + break; + case 2: + c->hierarchy = HIERARCHY_2; + break; + case 3: + c->hierarchy = HIERARCHY_4; + break; + } + + switch ((buf[0] >> 0) & 0x07) { + case 0: + c->code_rate_HP = FEC_1_2; + break; + case 1: + c->code_rate_HP = FEC_2_3; + break; + case 2: + c->code_rate_HP = FEC_3_4; + break; + case 3: + c->code_rate_HP = FEC_5_6; + break; + case 4: + c->code_rate_HP = FEC_7_8; + break; + } + + switch ((buf[1] >> 5) & 0x07) { + case 0: + c->code_rate_LP = FEC_1_2; + break; + case 1: + c->code_rate_LP = FEC_2_3; + break; + case 2: + c->code_rate_LP = FEC_3_4; + break; + case 3: + c->code_rate_LP = FEC_5_6; + break; + case 4: + c->code_rate_LP = FEC_7_8; + break; + } + + ret = cxd2820r_rd_reg(priv, 0x007c6, &buf[0]); + if (ret) + goto error; + + switch ((buf[0] >> 0) & 0x01) { + case 0: + c->inversion = INVERSION_OFF; + break; + case 1: + c->inversion = INVERSION_ON; + break; + } + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 buf[3], start_ber = 0; + *ber = 0; + + if (priv->ber_running) { + ret = cxd2820r_rd_regs(priv, 0x00076, buf, sizeof(buf)); + if (ret) + goto error; + + if ((buf[2] >> 7) & 0x01 || (buf[2] >> 4) & 0x01) { + *ber = (buf[2] & 0x0f) << 16 | buf[1] << 8 | buf[0]; + start_ber = 1; + } + } else { + priv->ber_running = 1; + start_ber = 1; + } + + if (start_ber) { + /* (re)start BER */ + ret = cxd2820r_wr_reg(priv, 0x00079, 0x01); + if (ret) + goto error; + } + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe, + u16 *strength) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 buf[2]; + u16 tmp; + + ret = cxd2820r_rd_regs(priv, 0x00026, buf, sizeof(buf)); + if (ret) + goto error; + + tmp = (buf[0] & 0x0f) << 8 | buf[1]; + tmp = ~tmp & 0x0fff; + + /* scale value to 0x0000-0xffff from 0x0000-0x0fff */ + *strength = tmp * 0xffff / 0x0fff; + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 buf[2]; + u16 tmp; + /* report SNR in dB * 10 */ + + ret = cxd2820r_rd_regs(priv, 0x00028, buf, sizeof(buf)); + if (ret) + goto error; + + tmp = (buf[0] & 0x1f) << 8 | buf[1]; + #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */ + if (tmp) + *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24) + / 100); + else + *snr = 0; + + dbg("%s: dBx10=%d val=%04x", __func__, *snr, tmp); + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks) +{ + *ucblocks = 0; + /* no way to read ? */ + return 0; +} + +static int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 buf[4]; + *status = 0; + + ret = cxd2820r_rd_reg(priv, 0x00010, &buf[0]); + if (ret) + goto error; + + if ((buf[0] & 0x07) == 6) { + ret = cxd2820r_rd_reg(priv, 0x00073, &buf[1]); + if (ret) + goto error; + + if (((buf[1] >> 3) & 0x01) == 1) { + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | + FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; + } else { + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | + FE_HAS_VITERBI | FE_HAS_SYNC; + } + } else { + ret = cxd2820r_rd_reg(priv, 0x00014, &buf[2]); + if (ret) + goto error; + + if ((buf[2] & 0x0f) >= 4) { + ret = cxd2820r_rd_reg(priv, 0x00a14, &buf[3]); + if (ret) + goto error; + + if (((buf[3] >> 4) & 0x01) == 1) + *status |= FE_HAS_SIGNAL; + } + } + + dbg("%s: lock=%02x %02x %02x %02x", __func__, + buf[0], buf[1], buf[2], buf[3]); + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_init_t(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + + ret = cxd2820r_wr_reg(priv, 0x00085, 0x07); + if (ret) + goto error; + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_sleep_t(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret, i; + struct reg_val_mask tab[] = { + { 0x000ff, 0x1f, 0xff }, + { 0x00085, 0x00, 0xff }, + { 0x00088, 0x01, 0xff }, + { 0x00081, 0x00, 0xff }, + { 0x00080, 0x00, 0xff }, + }; + + dbg("%s", __func__); + + priv->delivery_system = SYS_UNDEFINED; + + for (i = 0; i < ARRAY_SIZE(tab); i++) { + ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val, + tab[i].mask); + if (ret) + goto error; + } + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *s) +{ + s->min_delay_ms = 500; + s->step_size = fe->ops.info.frequency_stepsize * 2; + s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1; + + return 0; +} + diff --git a/drivers/media/dvb/frontends/cxd2820r_t2.c b/drivers/media/dvb/frontends/cxd2820r_t2.c new file mode 100644 index 000000000000..6ec94ea77f15 --- /dev/null +++ b/drivers/media/dvb/frontends/cxd2820r_t2.c @@ -0,0 +1,421 @@ +/* + * Sony CXD2820R demodulator driver + * + * Copyright (C) 2010 Antti Palosaari <crope@iki.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +static int cxd2820r_set_frontend_t2(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret, i; + u32 if_khz, if_ctl; + u64 num; + u8 buf[3], bw_param; + u8 bw_params1[][5] = { + { 0x1c, 0xb3, 0x33, 0x33, 0x33 }, /* 5 MHz */ + { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */ + { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */ + { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */ + }; + struct reg_val_mask tab[] = { + { 0x00080, 0x02, 0xff }, + { 0x00081, 0x20, 0xff }, + { 0x00085, 0x07, 0xff }, + { 0x00088, 0x01, 0xff }, + { 0x02069, 0x01, 0xff }, + + { 0x0207f, 0x2a, 0xff }, + { 0x02082, 0x0a, 0xff }, + { 0x02083, 0x0a, 0xff }, + { 0x020cb, priv->cfg.if_agc_polarity << 6, 0x40 }, + { 0x02070, priv->cfg.ts_mode, 0xff }, + { 0x020b5, priv->cfg.spec_inv << 4, 0x10 }, + { 0x02567, 0x07, 0x0f }, + { 0x02569, 0x03, 0x03 }, + { 0x02595, 0x1a, 0xff }, + { 0x02596, 0x50, 0xff }, + { 0x02a8c, 0x00, 0xff }, + { 0x02a8d, 0x34, 0xff }, + { 0x02a45, 0x06, 0x07 }, + { 0x03f10, 0x0d, 0xff }, + { 0x03f11, 0x02, 0xff }, + { 0x03f12, 0x01, 0xff }, + { 0x03f23, 0x2c, 0xff }, + { 0x03f51, 0x13, 0xff }, + { 0x03f52, 0x01, 0xff }, + { 0x03f53, 0x00, 0xff }, + { 0x027e6, 0x14, 0xff }, + { 0x02786, 0x02, 0x07 }, + { 0x02787, 0x40, 0xe0 }, + { 0x027ef, 0x10, 0x18 }, + }; + + dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz); + + /* update GPIOs */ + ret = cxd2820r_gpio(fe); + if (ret) + goto error; + + /* program tuner */ + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe, params); + + if (priv->delivery_system != SYS_DVBT2) { + for (i = 0; i < ARRAY_SIZE(tab); i++) { + ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, + tab[i].val, tab[i].mask); + if (ret) + goto error; + } + } + + priv->delivery_system = SYS_DVBT2; + + switch (c->bandwidth_hz) { + case 5000000: + if_khz = priv->cfg.if_dvbt2_5; + i = 0; + bw_param = 3; + break; + case 6000000: + if_khz = priv->cfg.if_dvbt2_6; + i = 1; + bw_param = 2; + break; + case 7000000: + if_khz = priv->cfg.if_dvbt2_7; + i = 2; + bw_param = 1; + break; + case 8000000: + if_khz = priv->cfg.if_dvbt2_8; + i = 3; + bw_param = 0; + break; + default: + return -EINVAL; + } + + num = if_khz; + num *= 0x1000000; + if_ctl = cxd2820r_div_u64_round_closest(num, 41000); + buf[0] = ((if_ctl >> 16) & 0xff); + buf[1] = ((if_ctl >> 8) & 0xff); + buf[2] = ((if_ctl >> 0) & 0xff); + + ret = cxd2820r_wr_regs(priv, 0x020b6, buf, 3); + if (ret) + goto error; + + ret = cxd2820r_wr_regs(priv, 0x0209f, bw_params1[i], 5); + if (ret) + goto error; + + ret = cxd2820r_wr_reg_mask(priv, 0x020d7, bw_param << 6, 0xc0); + if (ret) + goto error; + + ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08); + if (ret) + goto error; + + ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01); + if (ret) + goto error; + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; + +} + +static int cxd2820r_get_frontend_t2(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret; + u8 buf[2]; + + ret = cxd2820r_rd_regs(priv, 0x0205c, buf, 2); + if (ret) + goto error; + + switch ((buf[0] >> 0) & 0x07) { + case 0: + c->transmission_mode = TRANSMISSION_MODE_2K; + break; + case 1: + c->transmission_mode = TRANSMISSION_MODE_8K; + break; + case 2: + c->transmission_mode = TRANSMISSION_MODE_4K; + break; + case 3: + c->transmission_mode = TRANSMISSION_MODE_1K; + break; + case 4: + c->transmission_mode = TRANSMISSION_MODE_16K; + break; + case 5: + c->transmission_mode = TRANSMISSION_MODE_32K; + break; + } + + switch ((buf[1] >> 4) & 0x07) { + case 0: + c->guard_interval = GUARD_INTERVAL_1_32; + break; + case 1: + c->guard_interval = GUARD_INTERVAL_1_16; + break; + case 2: + c->guard_interval = GUARD_INTERVAL_1_8; + break; + case 3: + c->guard_interval = GUARD_INTERVAL_1_4; + break; + case 4: + c->guard_interval = GUARD_INTERVAL_1_128; + break; + case 5: + c->guard_interval = GUARD_INTERVAL_19_128; + break; + case 6: + c->guard_interval = GUARD_INTERVAL_19_256; + break; + } + + ret = cxd2820r_rd_regs(priv, 0x0225b, buf, 2); + if (ret) + goto error; + + switch ((buf[0] >> 0) & 0x07) { + case 0: + c->fec_inner = FEC_1_2; + break; + case 1: + c->fec_inner = FEC_3_5; + break; + case 2: + c->fec_inner = FEC_2_3; + break; + case 3: + c->fec_inner = FEC_3_4; + break; + case 4: + c->fec_inner = FEC_4_5; + break; + case 5: + c->fec_inner = FEC_5_6; + break; + } + + switch ((buf[1] >> 0) & 0x07) { + case 0: + c->modulation = QPSK; + break; + case 1: + c->modulation = QAM_16; + break; + case 2: + c->modulation = QAM_64; + break; + case 3: + c->modulation = QAM_256; + break; + } + + ret = cxd2820r_rd_reg(priv, 0x020b5, &buf[0]); + if (ret) + goto error; + + switch ((buf[0] >> 4) & 0x01) { + case 0: + c->inversion = INVERSION_OFF; + break; + case 1: + c->inversion = INVERSION_ON; + break; + } + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 buf[1]; + *status = 0; + + ret = cxd2820r_rd_reg(priv, 0x02010 , &buf[0]); + if (ret) + goto error; + + if ((buf[0] & 0x07) == 6) { + if (((buf[0] >> 5) & 0x01) == 1) { + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | + FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; + } else { + *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER | + FE_HAS_VITERBI | FE_HAS_SYNC; + } + } + + dbg("%s: lock=%02x", __func__, buf[0]); + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 buf[4]; + unsigned int errbits; + *ber = 0; + /* FIXME: correct calculation */ + + ret = cxd2820r_rd_regs(priv, 0x02039, buf, sizeof(buf)); + if (ret) + goto error; + + if ((buf[0] >> 4) & 0x01) { + errbits = (buf[0] & 0x0f) << 24 | buf[1] << 16 | + buf[2] << 8 | buf[3]; + + if (errbits) + *ber = errbits * 64 / 16588800; + } + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe, + u16 *strength) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 buf[2]; + u16 tmp; + + ret = cxd2820r_rd_regs(priv, 0x02026, buf, sizeof(buf)); + if (ret) + goto error; + + tmp = (buf[0] & 0x0f) << 8 | buf[1]; + tmp = ~tmp & 0x0fff; + + /* scale value to 0x0000-0xffff from 0x0000-0x0fff */ + *strength = tmp * 0xffff / 0x0fff; + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + u8 buf[2]; + u16 tmp; + /* report SNR in dB * 10 */ + + ret = cxd2820r_rd_regs(priv, 0x02028, buf, sizeof(buf)); + if (ret) + goto error; + + tmp = (buf[0] & 0x0f) << 8 | buf[1]; + #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */ + if (tmp) + *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24) + / 100); + else + *snr = 0; + + dbg("%s: dBx10=%d val=%04x", __func__, *snr, tmp); + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks) +{ + *ucblocks = 0; + /* no way to read ? */ + return 0; +} + +static int cxd2820r_sleep_t2(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret, i; + struct reg_val_mask tab[] = { + { 0x000ff, 0x1f, 0xff }, + { 0x00085, 0x00, 0xff }, + { 0x00088, 0x01, 0xff }, + { 0x02069, 0x00, 0xff }, + { 0x00081, 0x00, 0xff }, + { 0x00080, 0x00, 0xff }, + }; + + dbg("%s", __func__); + + for (i = 0; i < ARRAY_SIZE(tab); i++) { + ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val, + tab[i].mask); + if (ret) + goto error; + } + + priv->delivery_system = SYS_UNDEFINED; + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +static int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *s) +{ + s->min_delay_ms = 1500; + s->step_size = fe->ops.info.frequency_stepsize * 2; + s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1; + + return 0; +} + -- cgit v1.2.3 From 9ac51c5e53d6b16c9a3fa541117cf96dedd6b3dd Mon Sep 17 00:00:00 2001 From: Steve Kerrison <steve@stevekerrison.com> Date: Mon, 2 May 2011 18:19:13 -0300 Subject: [media] cxd2820r: make C, T, T2 and core components as linked objects Signed-off-by: Steve Kerrison <steve@stevekerrison.com> Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/Makefile | 1 + drivers/media/dvb/frontends/cxd2820r.c | 886 ---------------------------- drivers/media/dvb/frontends/cxd2820r_c.c | 22 +- drivers/media/dvb/frontends/cxd2820r_core.c | 881 +++++++++++++++++++++++++++ drivers/media/dvb/frontends/cxd2820r_priv.h | 102 +++- drivers/media/dvb/frontends/cxd2820r_t.c | 22 +- drivers/media/dvb/frontends/cxd2820r_t2.c | 20 +- 7 files changed, 1018 insertions(+), 916 deletions(-) delete mode 100644 drivers/media/dvb/frontends/cxd2820r.c create mode 100644 drivers/media/dvb/frontends/cxd2820r_core.c (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile index adec1a3f6291..2f3a6f736d64 100644 --- a/drivers/media/dvb/frontends/Makefile +++ b/drivers/media/dvb/frontends/Makefile @@ -9,6 +9,7 @@ stb0899-objs = stb0899_drv.o stb0899_algo.o stv0900-objs = stv0900_core.o stv0900_sw.o au8522-objs = au8522_dig.o au8522_decoder.o drxd-objs = drxd_firm.o drxd_hard.o +cxd2820r-objs = cxd2820r_core.o cxd2820r_c.o cxd2820r_t.o cxd2820r_t2.o obj-$(CONFIG_DVB_PLL) += dvb-pll.o obj-$(CONFIG_DVB_STV0299) += stv0299.o diff --git a/drivers/media/dvb/frontends/cxd2820r.c b/drivers/media/dvb/frontends/cxd2820r.c deleted file mode 100644 index b58f92c75116..000000000000 --- a/drivers/media/dvb/frontends/cxd2820r.c +++ /dev/null @@ -1,886 +0,0 @@ -/* - * Sony CXD2820R demodulator driver - * - * Copyright (C) 2010 Antti Palosaari <crope@iki.fi> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - - -#include "cxd2820r_priv.h" - -int cxd2820r_debug; -module_param_named(debug, cxd2820r_debug, int, 0644); -MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); - -/* TODO: temporary hack, will be removed later when there is app support */ -unsigned int cxd2820r_dvbt2_freq[5]; -int cxd2820r_dvbt2_count; -module_param_array_named(dvbt2_freq, cxd2820r_dvbt2_freq, int, - &cxd2820r_dvbt2_count, 0644); -MODULE_PARM_DESC(dvbt2_freq, "RF frequencies forced to DVB-T2 (unit Hz)"); - -/* write multiple registers */ -static int cxd2820r_wr_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg, - u8 *val, int len) -{ - int ret; - u8 buf[len+1]; - struct i2c_msg msg[1] = { - { - .addr = i2c, - .flags = 0, - .len = sizeof(buf), - .buf = buf, - } - }; - - buf[0] = reg; - memcpy(&buf[1], val, len); - - ret = i2c_transfer(priv->i2c, msg, 1); - if (ret == 1) { - ret = 0; - } else { - warn("i2c wr failed ret:%d reg:%02x len:%d", ret, reg, len); - ret = -EREMOTEIO; - } - return ret; -} - -/* read multiple registers */ -static int cxd2820r_rd_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg, - u8 *val, int len) -{ - int ret; - u8 buf[len]; - struct i2c_msg msg[2] = { - { - .addr = i2c, - .flags = 0, - .len = 1, - .buf = ®, - }, { - .addr = i2c, - .flags = I2C_M_RD, - .len = sizeof(buf), - .buf = buf, - } - }; - - ret = i2c_transfer(priv->i2c, msg, 2); - if (ret == 2) { - memcpy(val, buf, len); - ret = 0; - } else { - warn("i2c rd failed ret:%d reg:%02x len:%d", ret, reg, len); - ret = -EREMOTEIO; - } - - return ret; -} - -/* write multiple registers */ -static int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, - int len) -{ - int ret; - u8 i2c_addr; - u8 reg = (reginfo >> 0) & 0xff; - u8 bank = (reginfo >> 8) & 0xff; - u8 i2c = (reginfo >> 16) & 0x01; - - /* select I2C */ - if (i2c) - i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */ - else - i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */ - - /* switch bank if needed */ - if (bank != priv->bank[i2c]) { - ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1); - if (ret) - return ret; - priv->bank[i2c] = bank; - } - return cxd2820r_wr_regs_i2c(priv, i2c_addr, reg, val, len); -} - -/* read multiple registers */ -static int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, - int len) -{ - int ret; - u8 i2c_addr; - u8 reg = (reginfo >> 0) & 0xff; - u8 bank = (reginfo >> 8) & 0xff; - u8 i2c = (reginfo >> 16) & 0x01; - - /* select I2C */ - if (i2c) - i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */ - else - i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */ - - /* switch bank if needed */ - if (bank != priv->bank[i2c]) { - ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1); - if (ret) - return ret; - priv->bank[i2c] = bank; - } - return cxd2820r_rd_regs_i2c(priv, i2c_addr, reg, val, len); -} - -/* write single register */ -static int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val) -{ - return cxd2820r_wr_regs(priv, reg, &val, 1); -} - -/* read single register */ -static int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val) -{ - return cxd2820r_rd_regs(priv, reg, val, 1); -} - -/* write single register with mask */ -static int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val, - u8 mask) -{ - int ret; - u8 tmp; - - /* no need for read if whole reg is written */ - if (mask != 0xff) { - ret = cxd2820r_rd_reg(priv, reg, &tmp); - if (ret) - return ret; - - val &= mask; - tmp &= ~mask; - val |= tmp; - } - - return cxd2820r_wr_reg(priv, reg, val); -} - -static int cxd2820r_gpio(struct dvb_frontend *fe) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - int ret, i; - u8 *gpio, tmp0, tmp1; - dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBT: - gpio = priv->cfg.gpio_dvbt; - break; - case SYS_DVBT2: - gpio = priv->cfg.gpio_dvbt2; - break; - case SYS_DVBC_ANNEX_AC: - gpio = priv->cfg.gpio_dvbc; - break; - default: - ret = -EINVAL; - goto error; - } - - /* update GPIOs only when needed */ - if (!memcmp(gpio, priv->gpio, sizeof(priv->gpio))) - return 0; - - tmp0 = 0x00; - tmp1 = 0x00; - for (i = 0; i < sizeof(priv->gpio); i++) { - /* enable / disable */ - if (gpio[i] & CXD2820R_GPIO_E) - tmp0 |= (2 << 6) >> (2 * i); - else - tmp0 |= (1 << 6) >> (2 * i); - - /* input / output */ - if (gpio[i] & CXD2820R_GPIO_I) - tmp1 |= (1 << (3 + i)); - else - tmp1 |= (0 << (3 + i)); - - /* high / low */ - if (gpio[i] & CXD2820R_GPIO_H) - tmp1 |= (1 << (0 + i)); - else - tmp1 |= (0 << (0 + i)); - - dbg("%s: GPIO i=%d %02x %02x", __func__, i, tmp0, tmp1); - } - - dbg("%s: wr gpio=%02x %02x", __func__, tmp0, tmp1); - - /* write bits [7:2] */ - ret = cxd2820r_wr_reg_mask(priv, 0x00089, tmp0, 0xfc); - if (ret) - goto error; - - /* write bits [5:0] */ - ret = cxd2820r_wr_reg_mask(priv, 0x0008e, tmp1, 0x3f); - if (ret) - goto error; - - memcpy(priv->gpio, gpio, sizeof(priv->gpio)); - - return ret; -error: - dbg("%s: failed:%d", __func__, ret); - return ret; -} - -/* lock FE */ -static int cxd2820r_lock(struct cxd2820r_priv *priv, int active_fe) -{ - int ret = 0; - dbg("%s: active_fe=%d", __func__, active_fe); - - mutex_lock(&priv->fe_lock); - - /* -1=NONE, 0=DVB-T/T2, 1=DVB-C */ - if (priv->active_fe == active_fe) - ; - else if (priv->active_fe == -1) - priv->active_fe = active_fe; - else - ret = -EBUSY; - - mutex_unlock(&priv->fe_lock); - - return ret; -} - -/* unlock FE */ -static void cxd2820r_unlock(struct cxd2820r_priv *priv, int active_fe) -{ - dbg("%s: active_fe=%d", __func__, active_fe); - - mutex_lock(&priv->fe_lock); - - /* -1=NONE, 0=DVB-T/T2, 1=DVB-C */ - if (priv->active_fe == active_fe) - priv->active_fe = -1; - - mutex_unlock(&priv->fe_lock); - - return; -} - -/* 64 bit div with round closest, like DIV_ROUND_CLOSEST but 64 bit */ -static u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor) -{ - return div_u64(dividend + (divisor / 2), divisor); -} - -/* TODO: ... */ -#include "cxd2820r_t.c" -#include "cxd2820r_c.c" -#include "cxd2820r_t2.c" - -static int cxd2820r_set_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *p) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - int ret; - dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); - - if (fe->ops.info.type == FE_OFDM) { - /* DVB-T/T2 */ - ret = cxd2820r_lock(priv, 0); - if (ret) - return ret; - - switch (priv->delivery_system) { - case SYS_UNDEFINED: - if (c->delivery_system == SYS_DVBT) { - /* SLEEP => DVB-T */ - ret = cxd2820r_set_frontend_t(fe, p); - } else { - /* SLEEP => DVB-T2 */ - ret = cxd2820r_set_frontend_t2(fe, p); - } - break; - case SYS_DVBT: - if (c->delivery_system == SYS_DVBT) { - /* DVB-T => DVB-T */ - ret = cxd2820r_set_frontend_t(fe, p); - } else if (c->delivery_system == SYS_DVBT2) { - /* DVB-T => DVB-T2 */ - ret = cxd2820r_sleep_t(fe); - ret = cxd2820r_set_frontend_t2(fe, p); - } - break; - case SYS_DVBT2: - if (c->delivery_system == SYS_DVBT2) { - /* DVB-T2 => DVB-T2 */ - ret = cxd2820r_set_frontend_t2(fe, p); - } else if (c->delivery_system == SYS_DVBT) { - /* DVB-T2 => DVB-T */ - ret = cxd2820r_sleep_t2(fe); - ret = cxd2820r_set_frontend_t(fe, p); - } - break; - default: - dbg("%s: error state=%d", __func__, - priv->delivery_system); - ret = -EINVAL; - } - } else { - /* DVB-C */ - ret = cxd2820r_lock(priv, 1); - if (ret) - return ret; - - ret = cxd2820r_set_frontend_c(fe, p); - } - - return ret; -} - -static int cxd2820r_read_status(struct dvb_frontend *fe, fe_status_t *status) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - int ret; - dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); - - if (fe->ops.info.type == FE_OFDM) { - /* DVB-T/T2 */ - ret = cxd2820r_lock(priv, 0); - if (ret) - return ret; - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBT: - ret = cxd2820r_read_status_t(fe, status); - break; - case SYS_DVBT2: - ret = cxd2820r_read_status_t2(fe, status); - break; - default: - ret = -EINVAL; - } - } else { - /* DVB-C */ - ret = cxd2820r_lock(priv, 1); - if (ret) - return ret; - - ret = cxd2820r_read_status_c(fe, status); - } - - return ret; -} - -static int cxd2820r_get_frontend(struct dvb_frontend *fe, - struct dvb_frontend_parameters *p) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - int ret; - dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); - - if (fe->ops.info.type == FE_OFDM) { - /* DVB-T/T2 */ - ret = cxd2820r_lock(priv, 0); - if (ret) - return ret; - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBT: - ret = cxd2820r_get_frontend_t(fe, p); - break; - case SYS_DVBT2: - ret = cxd2820r_get_frontend_t2(fe, p); - break; - default: - ret = -EINVAL; - } - } else { - /* DVB-C */ - ret = cxd2820r_lock(priv, 1); - if (ret) - return ret; - - ret = cxd2820r_get_frontend_c(fe, p); - } - - return ret; -} - -static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - int ret; - dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); - - if (fe->ops.info.type == FE_OFDM) { - /* DVB-T/T2 */ - ret = cxd2820r_lock(priv, 0); - if (ret) - return ret; - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBT: - ret = cxd2820r_read_ber_t(fe, ber); - break; - case SYS_DVBT2: - ret = cxd2820r_read_ber_t2(fe, ber); - break; - default: - ret = -EINVAL; - } - } else { - /* DVB-C */ - ret = cxd2820r_lock(priv, 1); - if (ret) - return ret; - - ret = cxd2820r_read_ber_c(fe, ber); - } - - return ret; -} - -static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - int ret; - dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); - - if (fe->ops.info.type == FE_OFDM) { - /* DVB-T/T2 */ - ret = cxd2820r_lock(priv, 0); - if (ret) - return ret; - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBT: - ret = cxd2820r_read_signal_strength_t(fe, strength); - break; - case SYS_DVBT2: - ret = cxd2820r_read_signal_strength_t2(fe, strength); - break; - default: - ret = -EINVAL; - } - } else { - /* DVB-C */ - ret = cxd2820r_lock(priv, 1); - if (ret) - return ret; - - ret = cxd2820r_read_signal_strength_c(fe, strength); - } - - return ret; -} - -static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - int ret; - dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); - - if (fe->ops.info.type == FE_OFDM) { - /* DVB-T/T2 */ - ret = cxd2820r_lock(priv, 0); - if (ret) - return ret; - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBT: - ret = cxd2820r_read_snr_t(fe, snr); - break; - case SYS_DVBT2: - ret = cxd2820r_read_snr_t2(fe, snr); - break; - default: - ret = -EINVAL; - } - } else { - /* DVB-C */ - ret = cxd2820r_lock(priv, 1); - if (ret) - return ret; - - ret = cxd2820r_read_snr_c(fe, snr); - } - - return ret; -} - -static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - int ret; - dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); - - if (fe->ops.info.type == FE_OFDM) { - /* DVB-T/T2 */ - ret = cxd2820r_lock(priv, 0); - if (ret) - return ret; - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBT: - ret = cxd2820r_read_ucblocks_t(fe, ucblocks); - break; - case SYS_DVBT2: - ret = cxd2820r_read_ucblocks_t2(fe, ucblocks); - break; - default: - ret = -EINVAL; - } - } else { - /* DVB-C */ - ret = cxd2820r_lock(priv, 1); - if (ret) - return ret; - - ret = cxd2820r_read_ucblocks_c(fe, ucblocks); - } - - return ret; -} - -static int cxd2820r_init(struct dvb_frontend *fe) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - int ret; - dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); - - priv->delivery_system = SYS_UNDEFINED; - /* delivery system is unknown at that (init) phase */ - - if (fe->ops.info.type == FE_OFDM) { - /* DVB-T/T2 */ - ret = cxd2820r_lock(priv, 0); - if (ret) - return ret; - - ret = cxd2820r_init_t(fe); - } else { - /* DVB-C */ - ret = cxd2820r_lock(priv, 1); - if (ret) - return ret; - - ret = cxd2820r_init_c(fe); - } - - return ret; -} - -static int cxd2820r_sleep(struct dvb_frontend *fe) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - int ret; - dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); - - if (fe->ops.info.type == FE_OFDM) { - /* DVB-T/T2 */ - ret = cxd2820r_lock(priv, 0); - if (ret) - return ret; - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBT: - ret = cxd2820r_sleep_t(fe); - break; - case SYS_DVBT2: - ret = cxd2820r_sleep_t2(fe); - break; - default: - ret = -EINVAL; - } - - cxd2820r_unlock(priv, 0); - } else { - /* DVB-C */ - ret = cxd2820r_lock(priv, 1); - if (ret) - return ret; - - ret = cxd2820r_sleep_c(fe); - - cxd2820r_unlock(priv, 1); - } - - return ret; -} - -static int cxd2820r_get_tune_settings(struct dvb_frontend *fe, - struct dvb_frontend_tune_settings *s) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - int ret, i; - unsigned int rf1, rf2; - dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); - - if (fe->ops.info.type == FE_OFDM) { - /* DVB-T/T2 */ - ret = cxd2820r_lock(priv, 0); - if (ret) - return ret; - - /* TODO: hack! This will be removed later when there is better - * app support for DVB-T2... */ - - /* Hz => MHz */ - rf1 = DIV_ROUND_CLOSEST(fe->dtv_property_cache.frequency, - 1000000); - for (i = 0; i < cxd2820r_dvbt2_count; i++) { - if (cxd2820r_dvbt2_freq[i] > 100000000) { - /* Hz => MHz */ - rf2 = DIV_ROUND_CLOSEST(cxd2820r_dvbt2_freq[i], - 1000000); - } else if (cxd2820r_dvbt2_freq[i] > 100000) { - /* kHz => MHz */ - rf2 = DIV_ROUND_CLOSEST(cxd2820r_dvbt2_freq[i], - 1000); - } else { - rf2 = cxd2820r_dvbt2_freq[i]; - } - - dbg("%s: rf1=%d rf2=%d", __func__, rf1, rf2); - - if (rf1 == rf2) { - dbg("%s: forcing DVB-T2, frequency=%d", - __func__, fe->dtv_property_cache.frequency); - fe->dtv_property_cache.delivery_system = - SYS_DVBT2; - } - } - - switch (fe->dtv_property_cache.delivery_system) { - case SYS_DVBT: - ret = cxd2820r_get_tune_settings_t(fe, s); - break; - case SYS_DVBT2: - ret = cxd2820r_get_tune_settings_t2(fe, s); - break; - default: - ret = -EINVAL; - } - } else { - /* DVB-C */ - ret = cxd2820r_lock(priv, 1); - if (ret) - return ret; - - ret = cxd2820r_get_tune_settings_c(fe, s); - } - - return ret; -} - -static void cxd2820r_release(struct dvb_frontend *fe) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - dbg("%s", __func__); - - if (fe->ops.info.type == FE_OFDM) { - i2c_del_adapter(&priv->tuner_i2c_adapter); - kfree(priv); - } - - return; -} - -static u32 cxd2820r_tuner_i2c_func(struct i2c_adapter *adapter) -{ - return I2C_FUNC_I2C; -} - -static int cxd2820r_tuner_i2c_xfer(struct i2c_adapter *i2c_adap, - struct i2c_msg msg[], int num) -{ - struct cxd2820r_priv *priv = i2c_get_adapdata(i2c_adap); - u8 obuf[msg[0].len + 2]; - struct i2c_msg msg2[2] = { - { - .addr = priv->cfg.i2c_address, - .flags = 0, - .len = sizeof(obuf), - .buf = obuf, - }, { - .addr = priv->cfg.i2c_address, - .flags = I2C_M_RD, - .len = msg[1].len, - .buf = msg[1].buf, - } - }; - - obuf[0] = 0x09; - obuf[1] = (msg[0].addr << 1); - if (num == 2) { /* I2C read */ - obuf[1] = (msg[0].addr << 1) | I2C_M_RD; /* I2C RD flag */ - msg2[0].len = sizeof(obuf) - 1; /* maybe HW bug ? */ - } - memcpy(&obuf[2], msg[0].buf, msg[0].len); - - return i2c_transfer(priv->i2c, msg2, num); -} - -static struct i2c_algorithm cxd2820r_tuner_i2c_algo = { - .master_xfer = cxd2820r_tuner_i2c_xfer, - .functionality = cxd2820r_tuner_i2c_func, -}; - -struct i2c_adapter *cxd2820r_get_tuner_i2c_adapter(struct dvb_frontend *fe) -{ - struct cxd2820r_priv *priv = fe->demodulator_priv; - return &priv->tuner_i2c_adapter; -} -EXPORT_SYMBOL(cxd2820r_get_tuner_i2c_adapter); - -static struct dvb_frontend_ops cxd2820r_ops[2]; - -struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg, - struct i2c_adapter *i2c, struct dvb_frontend *fe) -{ - int ret; - struct cxd2820r_priv *priv = NULL; - u8 tmp; - - if (fe == NULL) { - /* FE0 */ - /* allocate memory for the internal priv */ - priv = kzalloc(sizeof(struct cxd2820r_priv), GFP_KERNEL); - if (priv == NULL) - goto error; - - /* setup the priv */ - priv->i2c = i2c; - memcpy(&priv->cfg, cfg, sizeof(struct cxd2820r_config)); - mutex_init(&priv->fe_lock); - - priv->active_fe = -1; /* NONE */ - - /* check if the demod is there */ - priv->bank[0] = priv->bank[1] = 0xff; - ret = cxd2820r_rd_reg(priv, 0x000fd, &tmp); - dbg("%s: chip id=%02x", __func__, tmp); - if (ret || tmp != 0xe1) - goto error; - - /* create frontends */ - memcpy(&priv->fe[0].ops, &cxd2820r_ops[0], - sizeof(struct dvb_frontend_ops)); - memcpy(&priv->fe[1].ops, &cxd2820r_ops[1], - sizeof(struct dvb_frontend_ops)); - - priv->fe[0].demodulator_priv = priv; - priv->fe[1].demodulator_priv = priv; - - /* create tuner i2c adapter */ - strlcpy(priv->tuner_i2c_adapter.name, - "CXD2820R tuner I2C adapter", - sizeof(priv->tuner_i2c_adapter.name)); - priv->tuner_i2c_adapter.algo = &cxd2820r_tuner_i2c_algo; - priv->tuner_i2c_adapter.algo_data = NULL; - i2c_set_adapdata(&priv->tuner_i2c_adapter, priv); - if (i2c_add_adapter(&priv->tuner_i2c_adapter) < 0) { - err("tuner I2C bus could not be initialized"); - goto error; - } - - return &priv->fe[0]; - - } else { - /* FE1: FE0 given as pointer, just return FE1 we have - * already created */ - priv = fe->demodulator_priv; - return &priv->fe[1]; - } - -error: - kfree(priv); - return NULL; -} -EXPORT_SYMBOL(cxd2820r_attach); - -static struct dvb_frontend_ops cxd2820r_ops[2] = { - { - /* DVB-T/T2 */ - .info = { - .name = "Sony CXD2820R (DVB-T/T2)", - .type = FE_OFDM, - .caps = - FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | - FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | - FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | - FE_CAN_QPSK | FE_CAN_QAM_16 | - FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | - FE_CAN_TRANSMISSION_MODE_AUTO | - FE_CAN_GUARD_INTERVAL_AUTO | - FE_CAN_HIERARCHY_AUTO | - FE_CAN_MUTE_TS | - FE_CAN_2G_MODULATION - }, - - .release = cxd2820r_release, - .init = cxd2820r_init, - .sleep = cxd2820r_sleep, - - .get_tune_settings = cxd2820r_get_tune_settings, - - .set_frontend = cxd2820r_set_frontend, - .get_frontend = cxd2820r_get_frontend, - - .read_status = cxd2820r_read_status, - .read_snr = cxd2820r_read_snr, - .read_ber = cxd2820r_read_ber, - .read_ucblocks = cxd2820r_read_ucblocks, - .read_signal_strength = cxd2820r_read_signal_strength, - }, - { - /* DVB-C */ - .info = { - .name = "Sony CXD2820R (DVB-C)", - .type = FE_QAM, - .caps = - FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | - FE_CAN_QAM_128 | FE_CAN_QAM_256 | - FE_CAN_FEC_AUTO - }, - - .release = cxd2820r_release, - .init = cxd2820r_init, - .sleep = cxd2820r_sleep, - - .get_tune_settings = cxd2820r_get_tune_settings, - - .set_frontend = cxd2820r_set_frontend, - .get_frontend = cxd2820r_get_frontend, - - .read_status = cxd2820r_read_status, - .read_snr = cxd2820r_read_snr, - .read_ber = cxd2820r_read_ber, - .read_ucblocks = cxd2820r_read_ucblocks, - .read_signal_strength = cxd2820r_read_signal_strength, - }, -}; - - -MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); -MODULE_DESCRIPTION("Sony CXD2820R demodulator driver"); -MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb/frontends/cxd2820r_c.c b/drivers/media/dvb/frontends/cxd2820r_c.c index a94bff944722..3c07d400731d 100644 --- a/drivers/media/dvb/frontends/cxd2820r_c.c +++ b/drivers/media/dvb/frontends/cxd2820r_c.c @@ -19,7 +19,9 @@ */ -static int cxd2820r_set_frontend_c(struct dvb_frontend *fe, +#include "cxd2820r_priv.h" + +int cxd2820r_set_frontend_c(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) { struct cxd2820r_priv *priv = fe->demodulator_priv; @@ -92,7 +94,7 @@ error: return ret; } -static int cxd2820r_get_frontend_c(struct dvb_frontend *fe, +int cxd2820r_get_frontend_c(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) { struct cxd2820r_priv *priv = fe->demodulator_priv; @@ -143,7 +145,7 @@ error: return ret; } -static int cxd2820r_read_ber_c(struct dvb_frontend *fe, u32 *ber) +int cxd2820r_read_ber_c(struct dvb_frontend *fe, u32 *ber) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret; @@ -177,7 +179,7 @@ error: return ret; } -static int cxd2820r_read_signal_strength_c(struct dvb_frontend *fe, +int cxd2820r_read_signal_strength_c(struct dvb_frontend *fe, u16 *strength) { struct cxd2820r_priv *priv = fe->demodulator_priv; @@ -207,7 +209,7 @@ error: return ret; } -static int cxd2820r_read_snr_c(struct dvb_frontend *fe, u16 *snr) +int cxd2820r_read_snr_c(struct dvb_frontend *fe, u16 *snr) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret; @@ -244,14 +246,14 @@ error: return ret; } -static int cxd2820r_read_ucblocks_c(struct dvb_frontend *fe, u32 *ucblocks) +int cxd2820r_read_ucblocks_c(struct dvb_frontend *fe, u32 *ucblocks) { *ucblocks = 0; /* no way to read ? */ return 0; } -static int cxd2820r_read_status_c(struct dvb_frontend *fe, fe_status_t *status) +int cxd2820r_read_status_c(struct dvb_frontend *fe, fe_status_t *status) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret; @@ -280,7 +282,7 @@ error: return ret; } -static int cxd2820r_init_c(struct dvb_frontend *fe) +int cxd2820r_init_c(struct dvb_frontend *fe) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret; @@ -295,7 +297,7 @@ error: return ret; } -static int cxd2820r_sleep_c(struct dvb_frontend *fe) +int cxd2820r_sleep_c(struct dvb_frontend *fe) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret, i; @@ -324,7 +326,7 @@ error: return ret; } -static int cxd2820r_get_tune_settings_c(struct dvb_frontend *fe, +int cxd2820r_get_tune_settings_c(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *s) { s->min_delay_ms = 500; diff --git a/drivers/media/dvb/frontends/cxd2820r_core.c b/drivers/media/dvb/frontends/cxd2820r_core.c new file mode 100644 index 000000000000..59d302f7a8f1 --- /dev/null +++ b/drivers/media/dvb/frontends/cxd2820r_core.c @@ -0,0 +1,881 @@ +/* + * Sony CXD2820R demodulator driver + * + * Copyright (C) 2010 Antti Palosaari <crope@iki.fi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#include "cxd2820r_priv.h" + +int cxd2820r_debug; +module_param_named(debug, cxd2820r_debug, int, 0644); +MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); + +/* TODO: temporary hack, will be removed later when there is app support */ +unsigned int cxd2820r_dvbt2_freq[5]; +int cxd2820r_dvbt2_count; +module_param_array_named(dvbt2_freq, cxd2820r_dvbt2_freq, int, + &cxd2820r_dvbt2_count, 0644); +MODULE_PARM_DESC(dvbt2_freq, "RF frequencies forced to DVB-T2 (unit Hz)"); + +/* write multiple registers */ +static int cxd2820r_wr_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg, + u8 *val, int len) +{ + int ret; + u8 buf[len+1]; + struct i2c_msg msg[1] = { + { + .addr = i2c, + .flags = 0, + .len = sizeof(buf), + .buf = buf, + } + }; + + buf[0] = reg; + memcpy(&buf[1], val, len); + + ret = i2c_transfer(priv->i2c, msg, 1); + if (ret == 1) { + ret = 0; + } else { + warn("i2c wr failed ret:%d reg:%02x len:%d", ret, reg, len); + ret = -EREMOTEIO; + } + return ret; +} + +/* read multiple registers */ +static int cxd2820r_rd_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg, + u8 *val, int len) +{ + int ret; + u8 buf[len]; + struct i2c_msg msg[2] = { + { + .addr = i2c, + .flags = 0, + .len = 1, + .buf = ®, + }, { + .addr = i2c, + .flags = I2C_M_RD, + .len = sizeof(buf), + .buf = buf, + } + }; + + ret = i2c_transfer(priv->i2c, msg, 2); + if (ret == 2) { + memcpy(val, buf, len); + ret = 0; + } else { + warn("i2c rd failed ret:%d reg:%02x len:%d", ret, reg, len); + ret = -EREMOTEIO; + } + + return ret; +} + +/* write multiple registers */ +int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, + int len) +{ + int ret; + u8 i2c_addr; + u8 reg = (reginfo >> 0) & 0xff; + u8 bank = (reginfo >> 8) & 0xff; + u8 i2c = (reginfo >> 16) & 0x01; + + /* select I2C */ + if (i2c) + i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */ + else + i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */ + + /* switch bank if needed */ + if (bank != priv->bank[i2c]) { + ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1); + if (ret) + return ret; + priv->bank[i2c] = bank; + } + return cxd2820r_wr_regs_i2c(priv, i2c_addr, reg, val, len); +} + +/* read multiple registers */ +int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, + int len) +{ + int ret; + u8 i2c_addr; + u8 reg = (reginfo >> 0) & 0xff; + u8 bank = (reginfo >> 8) & 0xff; + u8 i2c = (reginfo >> 16) & 0x01; + + /* select I2C */ + if (i2c) + i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */ + else + i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */ + + /* switch bank if needed */ + if (bank != priv->bank[i2c]) { + ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1); + if (ret) + return ret; + priv->bank[i2c] = bank; + } + return cxd2820r_rd_regs_i2c(priv, i2c_addr, reg, val, len); +} + +/* write single register */ +int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val) +{ + return cxd2820r_wr_regs(priv, reg, &val, 1); +} + +/* read single register */ +int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val) +{ + return cxd2820r_rd_regs(priv, reg, val, 1); +} + +/* write single register with mask */ +int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val, + u8 mask) +{ + int ret; + u8 tmp; + + /* no need for read if whole reg is written */ + if (mask != 0xff) { + ret = cxd2820r_rd_reg(priv, reg, &tmp); + if (ret) + return ret; + + val &= mask; + tmp &= ~mask; + val |= tmp; + } + + return cxd2820r_wr_reg(priv, reg, val); +} + +int cxd2820r_gpio(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret, i; + u8 *gpio, tmp0, tmp1; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + gpio = priv->cfg.gpio_dvbt; + break; + case SYS_DVBT2: + gpio = priv->cfg.gpio_dvbt2; + break; + case SYS_DVBC_ANNEX_AC: + gpio = priv->cfg.gpio_dvbc; + break; + default: + ret = -EINVAL; + goto error; + } + + /* update GPIOs only when needed */ + if (!memcmp(gpio, priv->gpio, sizeof(priv->gpio))) + return 0; + + tmp0 = 0x00; + tmp1 = 0x00; + for (i = 0; i < sizeof(priv->gpio); i++) { + /* enable / disable */ + if (gpio[i] & CXD2820R_GPIO_E) + tmp0 |= (2 << 6) >> (2 * i); + else + tmp0 |= (1 << 6) >> (2 * i); + + /* input / output */ + if (gpio[i] & CXD2820R_GPIO_I) + tmp1 |= (1 << (3 + i)); + else + tmp1 |= (0 << (3 + i)); + + /* high / low */ + if (gpio[i] & CXD2820R_GPIO_H) + tmp1 |= (1 << (0 + i)); + else + tmp1 |= (0 << (0 + i)); + + dbg("%s: GPIO i=%d %02x %02x", __func__, i, tmp0, tmp1); + } + + dbg("%s: wr gpio=%02x %02x", __func__, tmp0, tmp1); + + /* write bits [7:2] */ + ret = cxd2820r_wr_reg_mask(priv, 0x00089, tmp0, 0xfc); + if (ret) + goto error; + + /* write bits [5:0] */ + ret = cxd2820r_wr_reg_mask(priv, 0x0008e, tmp1, 0x3f); + if (ret) + goto error; + + memcpy(priv->gpio, gpio, sizeof(priv->gpio)); + + return ret; +error: + dbg("%s: failed:%d", __func__, ret); + return ret; +} + +/* lock FE */ +static int cxd2820r_lock(struct cxd2820r_priv *priv, int active_fe) +{ + int ret = 0; + dbg("%s: active_fe=%d", __func__, active_fe); + + mutex_lock(&priv->fe_lock); + + /* -1=NONE, 0=DVB-T/T2, 1=DVB-C */ + if (priv->active_fe == active_fe) + ; + else if (priv->active_fe == -1) + priv->active_fe = active_fe; + else + ret = -EBUSY; + + mutex_unlock(&priv->fe_lock); + + return ret; +} + +/* unlock FE */ +static void cxd2820r_unlock(struct cxd2820r_priv *priv, int active_fe) +{ + dbg("%s: active_fe=%d", __func__, active_fe); + + mutex_lock(&priv->fe_lock); + + /* -1=NONE, 0=DVB-T/T2, 1=DVB-C */ + if (priv->active_fe == active_fe) + priv->active_fe = -1; + + mutex_unlock(&priv->fe_lock); + + return; +} + +/* 64 bit div with round closest, like DIV_ROUND_CLOSEST but 64 bit */ +u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor) +{ + return div_u64(dividend + (divisor / 2), divisor); +} + +static int cxd2820r_set_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (priv->delivery_system) { + case SYS_UNDEFINED: + if (c->delivery_system == SYS_DVBT) { + /* SLEEP => DVB-T */ + ret = cxd2820r_set_frontend_t(fe, p); + } else { + /* SLEEP => DVB-T2 */ + ret = cxd2820r_set_frontend_t2(fe, p); + } + break; + case SYS_DVBT: + if (c->delivery_system == SYS_DVBT) { + /* DVB-T => DVB-T */ + ret = cxd2820r_set_frontend_t(fe, p); + } else if (c->delivery_system == SYS_DVBT2) { + /* DVB-T => DVB-T2 */ + ret = cxd2820r_sleep_t(fe); + ret = cxd2820r_set_frontend_t2(fe, p); + } + break; + case SYS_DVBT2: + if (c->delivery_system == SYS_DVBT2) { + /* DVB-T2 => DVB-T2 */ + ret = cxd2820r_set_frontend_t2(fe, p); + } else if (c->delivery_system == SYS_DVBT) { + /* DVB-T2 => DVB-T */ + ret = cxd2820r_sleep_t2(fe); + ret = cxd2820r_set_frontend_t(fe, p); + } + break; + default: + dbg("%s: error state=%d", __func__, + priv->delivery_system); + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_set_frontend_c(fe, p); + } + + return ret; +} + +static int cxd2820r_read_status(struct dvb_frontend *fe, fe_status_t *status) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_read_status_t(fe, status); + break; + case SYS_DVBT2: + ret = cxd2820r_read_status_t2(fe, status); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_read_status_c(fe, status); + } + + return ret; +} + +static int cxd2820r_get_frontend(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_get_frontend_t(fe, p); + break; + case SYS_DVBT2: + ret = cxd2820r_get_frontend_t2(fe, p); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_get_frontend_c(fe, p); + } + + return ret; +} + +static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_read_ber_t(fe, ber); + break; + case SYS_DVBT2: + ret = cxd2820r_read_ber_t2(fe, ber); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_read_ber_c(fe, ber); + } + + return ret; +} + +static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_read_signal_strength_t(fe, strength); + break; + case SYS_DVBT2: + ret = cxd2820r_read_signal_strength_t2(fe, strength); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_read_signal_strength_c(fe, strength); + } + + return ret; +} + +static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_read_snr_t(fe, snr); + break; + case SYS_DVBT2: + ret = cxd2820r_read_snr_t2(fe, snr); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_read_snr_c(fe, snr); + } + + return ret; +} + +static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_read_ucblocks_t(fe, ucblocks); + break; + case SYS_DVBT2: + ret = cxd2820r_read_ucblocks_t2(fe, ucblocks); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_read_ucblocks_c(fe, ucblocks); + } + + return ret; +} + +static int cxd2820r_init(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + priv->delivery_system = SYS_UNDEFINED; + /* delivery system is unknown at that (init) phase */ + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + ret = cxd2820r_init_t(fe); + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_init_c(fe); + } + + return ret; +} + +static int cxd2820r_sleep(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_sleep_t(fe); + break; + case SYS_DVBT2: + ret = cxd2820r_sleep_t2(fe); + break; + default: + ret = -EINVAL; + } + + cxd2820r_unlock(priv, 0); + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_sleep_c(fe); + + cxd2820r_unlock(priv, 1); + } + + return ret; +} + +static int cxd2820r_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *s) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + int ret, i; + unsigned int rf1, rf2; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + if (fe->ops.info.type == FE_OFDM) { + /* DVB-T/T2 */ + ret = cxd2820r_lock(priv, 0); + if (ret) + return ret; + + /* TODO: hack! This will be removed later when there is better + * app support for DVB-T2... */ + + /* Hz => MHz */ + rf1 = DIV_ROUND_CLOSEST(fe->dtv_property_cache.frequency, + 1000000); + for (i = 0; i < cxd2820r_dvbt2_count; i++) { + if (cxd2820r_dvbt2_freq[i] > 100000000) { + /* Hz => MHz */ + rf2 = DIV_ROUND_CLOSEST(cxd2820r_dvbt2_freq[i], + 1000000); + } else if (cxd2820r_dvbt2_freq[i] > 100000) { + /* kHz => MHz */ + rf2 = DIV_ROUND_CLOSEST(cxd2820r_dvbt2_freq[i], + 1000); + } else { + rf2 = cxd2820r_dvbt2_freq[i]; + } + + dbg("%s: rf1=%d rf2=%d", __func__, rf1, rf2); + + if (rf1 == rf2) { + dbg("%s: forcing DVB-T2, frequency=%d", + __func__, fe->dtv_property_cache.frequency); + fe->dtv_property_cache.delivery_system = + SYS_DVBT2; + } + } + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBT: + ret = cxd2820r_get_tune_settings_t(fe, s); + break; + case SYS_DVBT2: + ret = cxd2820r_get_tune_settings_t2(fe, s); + break; + default: + ret = -EINVAL; + } + } else { + /* DVB-C */ + ret = cxd2820r_lock(priv, 1); + if (ret) + return ret; + + ret = cxd2820r_get_tune_settings_c(fe, s); + } + + return ret; +} + +static void cxd2820r_release(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + dbg("%s", __func__); + + if (fe->ops.info.type == FE_OFDM) { + i2c_del_adapter(&priv->tuner_i2c_adapter); + kfree(priv); + } + + return; +} + +static u32 cxd2820r_tuner_i2c_func(struct i2c_adapter *adapter) +{ + return I2C_FUNC_I2C; +} + +static int cxd2820r_tuner_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg msg[], int num) +{ + struct cxd2820r_priv *priv = i2c_get_adapdata(i2c_adap); + u8 obuf[msg[0].len + 2]; + struct i2c_msg msg2[2] = { + { + .addr = priv->cfg.i2c_address, + .flags = 0, + .len = sizeof(obuf), + .buf = obuf, + }, { + .addr = priv->cfg.i2c_address, + .flags = I2C_M_RD, + .len = msg[1].len, + .buf = msg[1].buf, + } + }; + + obuf[0] = 0x09; + obuf[1] = (msg[0].addr << 1); + if (num == 2) { /* I2C read */ + obuf[1] = (msg[0].addr << 1) | I2C_M_RD; /* I2C RD flag */ + msg2[0].len = sizeof(obuf) - 1; /* maybe HW bug ? */ + } + memcpy(&obuf[2], msg[0].buf, msg[0].len); + + return i2c_transfer(priv->i2c, msg2, num); +} + +static struct i2c_algorithm cxd2820r_tuner_i2c_algo = { + .master_xfer = cxd2820r_tuner_i2c_xfer, + .functionality = cxd2820r_tuner_i2c_func, +}; + +struct i2c_adapter *cxd2820r_get_tuner_i2c_adapter(struct dvb_frontend *fe) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + return &priv->tuner_i2c_adapter; +} +EXPORT_SYMBOL(cxd2820r_get_tuner_i2c_adapter); + +static struct dvb_frontend_ops cxd2820r_ops[2]; + +struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg, + struct i2c_adapter *i2c, struct dvb_frontend *fe) +{ + int ret; + struct cxd2820r_priv *priv = NULL; + u8 tmp; + + if (fe == NULL) { + /* FE0 */ + /* allocate memory for the internal priv */ + priv = kzalloc(sizeof(struct cxd2820r_priv), GFP_KERNEL); + if (priv == NULL) + goto error; + + /* setup the priv */ + priv->i2c = i2c; + memcpy(&priv->cfg, cfg, sizeof(struct cxd2820r_config)); + mutex_init(&priv->fe_lock); + + priv->active_fe = -1; /* NONE */ + + /* check if the demod is there */ + priv->bank[0] = priv->bank[1] = 0xff; + ret = cxd2820r_rd_reg(priv, 0x000fd, &tmp); + dbg("%s: chip id=%02x", __func__, tmp); + if (ret || tmp != 0xe1) + goto error; + + /* create frontends */ + memcpy(&priv->fe[0].ops, &cxd2820r_ops[0], + sizeof(struct dvb_frontend_ops)); + memcpy(&priv->fe[1].ops, &cxd2820r_ops[1], + sizeof(struct dvb_frontend_ops)); + + priv->fe[0].demodulator_priv = priv; + priv->fe[1].demodulator_priv = priv; + + /* create tuner i2c adapter */ + strlcpy(priv->tuner_i2c_adapter.name, + "CXD2820R tuner I2C adapter", + sizeof(priv->tuner_i2c_adapter.name)); + priv->tuner_i2c_adapter.algo = &cxd2820r_tuner_i2c_algo; + priv->tuner_i2c_adapter.algo_data = NULL; + i2c_set_adapdata(&priv->tuner_i2c_adapter, priv); + if (i2c_add_adapter(&priv->tuner_i2c_adapter) < 0) { + err("tuner I2C bus could not be initialized"); + goto error; + } + + return &priv->fe[0]; + + } else { + /* FE1: FE0 given as pointer, just return FE1 we have + * already created */ + priv = fe->demodulator_priv; + return &priv->fe[1]; + } + +error: + kfree(priv); + return NULL; +} +EXPORT_SYMBOL(cxd2820r_attach); + +static struct dvb_frontend_ops cxd2820r_ops[2] = { + { + /* DVB-T/T2 */ + .info = { + .name = "Sony CXD2820R (DVB-T/T2)", + .type = FE_OFDM, + .caps = + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | + FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | + FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_QPSK | FE_CAN_QAM_16 | + FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | + FE_CAN_HIERARCHY_AUTO | + FE_CAN_MUTE_TS | + FE_CAN_2G_MODULATION + }, + + .release = cxd2820r_release, + .init = cxd2820r_init, + .sleep = cxd2820r_sleep, + + .get_tune_settings = cxd2820r_get_tune_settings, + + .set_frontend = cxd2820r_set_frontend, + .get_frontend = cxd2820r_get_frontend, + + .read_status = cxd2820r_read_status, + .read_snr = cxd2820r_read_snr, + .read_ber = cxd2820r_read_ber, + .read_ucblocks = cxd2820r_read_ucblocks, + .read_signal_strength = cxd2820r_read_signal_strength, + }, + { + /* DVB-C */ + .info = { + .name = "Sony CXD2820R (DVB-C)", + .type = FE_QAM, + .caps = + FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | + FE_CAN_QAM_128 | FE_CAN_QAM_256 | + FE_CAN_FEC_AUTO + }, + + .release = cxd2820r_release, + .init = cxd2820r_init, + .sleep = cxd2820r_sleep, + + .get_tune_settings = cxd2820r_get_tune_settings, + + .set_frontend = cxd2820r_set_frontend, + .get_frontend = cxd2820r_get_frontend, + + .read_status = cxd2820r_read_status, + .read_snr = cxd2820r_read_snr, + .read_ber = cxd2820r_read_ber, + .read_ucblocks = cxd2820r_read_ucblocks, + .read_signal_strength = cxd2820r_read_signal_strength, + }, +}; + + +MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>"); +MODULE_DESCRIPTION("Sony CXD2820R demodulator driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb/frontends/cxd2820r_priv.h b/drivers/media/dvb/frontends/cxd2820r_priv.h index 4d2d79969d91..2437d51bdae3 100644 --- a/drivers/media/dvb/frontends/cxd2820r_priv.h +++ b/drivers/media/dvb/frontends/cxd2820r_priv.h @@ -22,6 +22,7 @@ #ifndef CXD2820R_PRIV_H #define CXD2820R_PRIV_H +#include <linux/dvb/version.h> #include "dvb_frontend.h" #include "dvb_math.h" #include "cxd2820r.h" @@ -70,8 +71,107 @@ struct cxd2820r_priv { u8 bank[2]; u8 gpio[3]; - + fe_delivery_system_t delivery_system; }; +/* cxd2820r_core.c */ + +extern int cxd2820r_debug; + +int cxd2820r_gpio(struct dvb_frontend *fe); + +int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val, + u8 mask); + +int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, + int len); + +u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor); + +int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, + int len); + +int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, + int len); + +int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val); + +int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val); + +/* cxd2820r_c.c */ + +int cxd2820r_get_frontend_c(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p); + +int cxd2820r_set_frontend_c(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params); + +int cxd2820r_read_status_c(struct dvb_frontend *fe, fe_status_t *status); + +int cxd2820r_read_ber_c(struct dvb_frontend *fe, u32 *ber); + +int cxd2820r_read_signal_strength_c(struct dvb_frontend *fe, u16 *strength); + +int cxd2820r_read_snr_c(struct dvb_frontend *fe, u16 *snr); + +int cxd2820r_read_ucblocks_c(struct dvb_frontend *fe, u32 *ucblocks); + +int cxd2820r_init_c(struct dvb_frontend *fe); + +int cxd2820r_sleep_c(struct dvb_frontend *fe); + +int cxd2820r_get_tune_settings_c(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *s); + +/* cxd2820r_t.c */ + +int cxd2820r_get_frontend_t(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p); + +int cxd2820r_set_frontend_t(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params); + +int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status); + +int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber); + +int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe, u16 *strength); + +int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr); + +int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks); + +int cxd2820r_init_t(struct dvb_frontend *fe); + +int cxd2820r_sleep_t(struct dvb_frontend *fe); + +int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *s); + +/* cxd2820r_t2.c */ + +int cxd2820r_get_frontend_t2(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p); + +int cxd2820r_set_frontend_t2(struct dvb_frontend *fe, + struct dvb_frontend_parameters *params); + +int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status); + +int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber); + +int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe, u16 *strength); + +int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr); + +int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks); + +int cxd2820r_init_t2(struct dvb_frontend *fe); + +int cxd2820r_sleep_t2(struct dvb_frontend *fe); + +int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *s); + #endif /* CXD2820R_PRIV_H */ diff --git a/drivers/media/dvb/frontends/cxd2820r_t.c b/drivers/media/dvb/frontends/cxd2820r_t.c index 6732a9843f13..6582564c930c 100644 --- a/drivers/media/dvb/frontends/cxd2820r_t.c +++ b/drivers/media/dvb/frontends/cxd2820r_t.c @@ -19,7 +19,9 @@ */ -static int cxd2820r_set_frontend_t(struct dvb_frontend *fe, +#include "cxd2820r_priv.h" + +int cxd2820r_set_frontend_t(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) { struct cxd2820r_priv *priv = fe->demodulator_priv; @@ -133,7 +135,7 @@ error: return ret; } -static int cxd2820r_get_frontend_t(struct dvb_frontend *fe, +int cxd2820r_get_frontend_t(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) { struct cxd2820r_priv *priv = fe->demodulator_priv; @@ -251,7 +253,7 @@ error: return ret; } -static int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber) +int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret; @@ -285,7 +287,7 @@ error: return ret; } -static int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe, +int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe, u16 *strength) { struct cxd2820r_priv *priv = fe->demodulator_priv; @@ -309,7 +311,7 @@ error: return ret; } -static int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr) +int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret; @@ -337,14 +339,14 @@ error: return ret; } -static int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks) +int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks) { *ucblocks = 0; /* no way to read ? */ return 0; } -static int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status) +int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret; @@ -391,7 +393,7 @@ error: return ret; } -static int cxd2820r_init_t(struct dvb_frontend *fe) +int cxd2820r_init_t(struct dvb_frontend *fe) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret; @@ -406,7 +408,7 @@ error: return ret; } -static int cxd2820r_sleep_t(struct dvb_frontend *fe) +int cxd2820r_sleep_t(struct dvb_frontend *fe) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret, i; @@ -435,7 +437,7 @@ error: return ret; } -static int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe, +int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *s) { s->min_delay_ms = 500; diff --git a/drivers/media/dvb/frontends/cxd2820r_t2.c b/drivers/media/dvb/frontends/cxd2820r_t2.c index 6ec94ea77f15..c47b35c8acf1 100644 --- a/drivers/media/dvb/frontends/cxd2820r_t2.c +++ b/drivers/media/dvb/frontends/cxd2820r_t2.c @@ -19,7 +19,9 @@ */ -static int cxd2820r_set_frontend_t2(struct dvb_frontend *fe, +#include "cxd2820r_priv.h" + +int cxd2820r_set_frontend_t2(struct dvb_frontend *fe, struct dvb_frontend_parameters *params) { struct cxd2820r_priv *priv = fe->demodulator_priv; @@ -148,7 +150,7 @@ error: } -static int cxd2820r_get_frontend_t2(struct dvb_frontend *fe, +int cxd2820r_get_frontend_t2(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) { struct cxd2820r_priv *priv = fe->demodulator_priv; @@ -264,7 +266,7 @@ error: return ret; } -static int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status) +int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret; @@ -293,7 +295,7 @@ error: return ret; } -static int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber) +int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret; @@ -320,7 +322,7 @@ error: return ret; } -static int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe, +int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe, u16 *strength) { struct cxd2820r_priv *priv = fe->demodulator_priv; @@ -344,7 +346,7 @@ error: return ret; } -static int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr) +int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret; @@ -372,14 +374,14 @@ error: return ret; } -static int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks) +int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks) { *ucblocks = 0; /* no way to read ? */ return 0; } -static int cxd2820r_sleep_t2(struct dvb_frontend *fe) +int cxd2820r_sleep_t2(struct dvb_frontend *fe) { struct cxd2820r_priv *priv = fe->demodulator_priv; int ret, i; @@ -409,7 +411,7 @@ error: return ret; } -static int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe, +int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *s) { s->min_delay_ms = 1500; -- cgit v1.2.3 From 2e1ea06e9cc7aacdd6e77939e51743405299c9c2 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Tue, 3 May 2011 20:21:59 -0300 Subject: [media] cxd2820r: whitespace fix Make checkpatch.pl happy by fixing whitespaces introduced by commit 79e8b8e3b8cbf67130247a3f6d25732373fe2f34 Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/cxd2820r_priv.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/cxd2820r_priv.h b/drivers/media/dvb/frontends/cxd2820r_priv.h index 2437d51bdae3..835e37b98049 100644 --- a/drivers/media/dvb/frontends/cxd2820r_priv.h +++ b/drivers/media/dvb/frontends/cxd2820r_priv.h @@ -71,7 +71,7 @@ struct cxd2820r_priv { u8 bank[2]; u8 gpio[3]; - + fe_delivery_system_t delivery_system; }; @@ -83,10 +83,10 @@ int cxd2820r_gpio(struct dvb_frontend *fe); int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val, u8 mask); - + int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, int len); - + u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor); int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val, @@ -106,7 +106,7 @@ int cxd2820r_get_frontend_c(struct dvb_frontend *fe, int cxd2820r_set_frontend_c(struct dvb_frontend *fe, struct dvb_frontend_parameters *params); - + int cxd2820r_read_status_c(struct dvb_frontend *fe, fe_status_t *status); int cxd2820r_read_ber_c(struct dvb_frontend *fe, u32 *ber); @@ -131,7 +131,7 @@ int cxd2820r_get_frontend_t(struct dvb_frontend *fe, int cxd2820r_set_frontend_t(struct dvb_frontend *fe, struct dvb_frontend_parameters *params); - + int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status); int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber); @@ -156,7 +156,7 @@ int cxd2820r_get_frontend_t2(struct dvb_frontend *fe, int cxd2820r_set_frontend_t2(struct dvb_frontend *fe, struct dvb_frontend_parameters *params); - + int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status); int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber); @@ -173,5 +173,5 @@ int cxd2820r_sleep_t2(struct dvb_frontend *fe); int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *s); - + #endif /* CXD2820R_PRIV_H */ -- cgit v1.2.3 From e47b78f036bf1c30a5263ccdf1f638d1612b0586 Mon Sep 17 00:00:00 2001 From: Antti Palosaari <crope@iki.fi> Date: Tue, 3 May 2011 20:31:36 -0300 Subject: [media] cxd2820r: switch automatically between DVB-T and DVB-T2 Remove old DVB-T2 freq module param and detect DVB-T/T2 automatically. Implementation is trial and error, if DVB-T does not lock try DVB-T2 and vice versa. That's done by replacing normal DVBFE_ALGO_SW with DVBFE_ALGO_CUSTOM which gives better control for tuning process. DVB-C still uses normal software ZigZag, DVBFE_ALGO_SW. Signed-off-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/cxd2820r_core.c | 111 ++++++++++++++++++---------- drivers/media/dvb/frontends/cxd2820r_priv.h | 1 + 2 files changed, 73 insertions(+), 39 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/cxd2820r_core.c b/drivers/media/dvb/frontends/cxd2820r_core.c index 59d302f7a8f1..e900c4cad7fd 100644 --- a/drivers/media/dvb/frontends/cxd2820r_core.c +++ b/drivers/media/dvb/frontends/cxd2820r_core.c @@ -25,13 +25,6 @@ int cxd2820r_debug; module_param_named(debug, cxd2820r_debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); -/* TODO: temporary hack, will be removed later when there is app support */ -unsigned int cxd2820r_dvbt2_freq[5]; -int cxd2820r_dvbt2_count; -module_param_array_named(dvbt2_freq, cxd2820r_dvbt2_freq, int, - &cxd2820r_dvbt2_count, 0644); -MODULE_PARM_DESC(dvbt2_freq, "RF frequencies forced to DVB-T2 (unit Hz)"); - /* write multiple registers */ static int cxd2820r_wr_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg, u8 *val, int len) @@ -626,8 +619,7 @@ static int cxd2820r_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *s) { struct cxd2820r_priv *priv = fe->demodulator_priv; - int ret, i; - unsigned int rf1, rf2; + int ret; dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); if (fe->ops.info.type == FE_OFDM) { @@ -636,35 +628,6 @@ static int cxd2820r_get_tune_settings(struct dvb_frontend *fe, if (ret) return ret; - /* TODO: hack! This will be removed later when there is better - * app support for DVB-T2... */ - - /* Hz => MHz */ - rf1 = DIV_ROUND_CLOSEST(fe->dtv_property_cache.frequency, - 1000000); - for (i = 0; i < cxd2820r_dvbt2_count; i++) { - if (cxd2820r_dvbt2_freq[i] > 100000000) { - /* Hz => MHz */ - rf2 = DIV_ROUND_CLOSEST(cxd2820r_dvbt2_freq[i], - 1000000); - } else if (cxd2820r_dvbt2_freq[i] > 100000) { - /* kHz => MHz */ - rf2 = DIV_ROUND_CLOSEST(cxd2820r_dvbt2_freq[i], - 1000); - } else { - rf2 = cxd2820r_dvbt2_freq[i]; - } - - dbg("%s: rf1=%d rf2=%d", __func__, rf1, rf2); - - if (rf1 == rf2) { - dbg("%s: forcing DVB-T2, frequency=%d", - __func__, fe->dtv_property_cache.frequency); - fe->dtv_property_cache.delivery_system = - SYS_DVBT2; - } - } - switch (fe->dtv_property_cache.delivery_system) { case SYS_DVBT: ret = cxd2820r_get_tune_settings_t(fe, s); @@ -687,6 +650,74 @@ static int cxd2820r_get_tune_settings(struct dvb_frontend *fe, return ret; } +static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe, + struct dvb_frontend_parameters *p) +{ + struct cxd2820r_priv *priv = fe->demodulator_priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; + int ret, i; + fe_status_t status = 0; + dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system); + + /* switch between DVB-T and DVB-T2 when tune fails */ + if (priv->last_tune_failed) { + if (priv->delivery_system == SYS_DVBT) + c->delivery_system = SYS_DVBT2; + else + c->delivery_system = SYS_DVBT; + } + + /* set frontend */ + ret = cxd2820r_set_frontend(fe, p); + if (ret) + goto error; + + + /* frontend lock wait loop count */ + switch (priv->delivery_system) { + case SYS_DVBT: + i = 20; + break; + case SYS_DVBT2: + i = 40; + break; + case SYS_UNDEFINED: + default: + i = 0; + break; + } + + /* wait frontend lock */ + for (; i > 0; i--) { + dbg("%s: LOOP=%d", __func__, i); + msleep(50); + ret = cxd2820r_read_status(fe, &status); + if (ret) + goto error; + + if (status & FE_HAS_SIGNAL) + break; + } + + /* check if we have a valid signal */ + if (status) { + priv->last_tune_failed = 0; + return DVBFE_ALGO_SEARCH_SUCCESS; + } else { + priv->last_tune_failed = 1; + return DVBFE_ALGO_SEARCH_AGAIN; + } + +error: + dbg("%s: failed:%d", __func__, ret); + return DVBFE_ALGO_SEARCH_ERROR; +} + +static int cxd2820r_get_frontend_algo(struct dvb_frontend *fe) +{ + return DVBFE_ALGO_CUSTOM; +} + static void cxd2820r_release(struct dvb_frontend *fe) { struct cxd2820r_priv *priv = fe->demodulator_priv; @@ -838,9 +869,11 @@ static struct dvb_frontend_ops cxd2820r_ops[2] = { .get_tune_settings = cxd2820r_get_tune_settings, - .set_frontend = cxd2820r_set_frontend, .get_frontend = cxd2820r_get_frontend, + .get_frontend_algo = cxd2820r_get_frontend_algo, + .search = cxd2820r_search, + .read_status = cxd2820r_read_status, .read_snr = cxd2820r_read_snr, .read_ber = cxd2820r_read_ber, diff --git a/drivers/media/dvb/frontends/cxd2820r_priv.h b/drivers/media/dvb/frontends/cxd2820r_priv.h index 835e37b98049..d4e2e0b76c10 100644 --- a/drivers/media/dvb/frontends/cxd2820r_priv.h +++ b/drivers/media/dvb/frontends/cxd2820r_priv.h @@ -73,6 +73,7 @@ struct cxd2820r_priv { u8 gpio[3]; fe_delivery_system_t delivery_system; + int last_tune_failed:1; /* for switch between T and T2 tune */ }; /* cxd2820r_core.c */ -- cgit v1.2.3 From 5a0deeed5741117ee8625d6305d0034e219f102c Mon Sep 17 00:00:00 2001 From: Olivier Grenie <olivier.grenie@dibcom.fr> Date: Tue, 3 May 2011 12:27:33 -0300 Subject: [media] DiBxxxx: get rid of DMA buffer on stack This patch removes the remaining on-stack buffer for USB DMA transfer. This patch also reduces the stack memory usage. Cc: stable@kernel.org Cc: Florian Mickler <florian@mickler.org> Signed-off-by: Olivier Grenie <olivier.grenie@dibcom.fr> Signed-off-by: Patrick Boettcher <patrick.boettcher@dibcom.fr> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/dib0070.c | 40 +++++-- drivers/media/dvb/frontends/dib0090.c | 71 ++++++++--- drivers/media/dvb/frontends/dib7000m.c | 49 +++++--- drivers/media/dvb/frontends/dib7000p.c | 72 +++++++---- drivers/media/dvb/frontends/dib8000.c | 126 +++++++++++++++----- drivers/media/dvb/frontends/dib9000.c | 172 +++++++++++++++++---------- drivers/media/dvb/frontends/dibx000_common.c | 109 ++++++++++------- drivers/media/dvb/frontends/dibx000_common.h | 5 + 8 files changed, 443 insertions(+), 201 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/dib0070.c b/drivers/media/dvb/frontends/dib0070.c index d4e466a90e43..1d47d4da7d4c 100644 --- a/drivers/media/dvb/frontends/dib0070.c +++ b/drivers/media/dvb/frontends/dib0070.c @@ -73,27 +73,47 @@ struct dib0070_state { u8 wbd_gain_current; u16 wbd_offset_3_3[2]; + + /* for the I2C transfer */ + struct i2c_msg msg[2]; + u8 i2c_write_buffer[3]; + u8 i2c_read_buffer[2]; }; static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg) { - u8 b[2]; - struct i2c_msg msg[2] = { - { .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 }, - { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2 }, - }; - if (i2c_transfer(state->i2c, msg, 2) != 2) { + state->i2c_write_buffer[0] = reg; + + memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); + state->msg[0].addr = state->cfg->i2c_address; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = 1; + state->msg[1].addr = state->cfg->i2c_address; + state->msg[1].flags = I2C_M_RD; + state->msg[1].buf = state->i2c_read_buffer; + state->msg[1].len = 2; + + if (i2c_transfer(state->i2c, state->msg, 2) != 2) { printk(KERN_WARNING "DiB0070 I2C read failed\n"); return 0; } - return (b[0] << 8) | b[1]; + return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; } static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val) { - u8 b[3] = { reg, val >> 8, val & 0xff }; - struct i2c_msg msg = { .addr = state->cfg->i2c_address, .flags = 0, .buf = b, .len = 3 }; - if (i2c_transfer(state->i2c, &msg, 1) != 1) { + state->i2c_write_buffer[0] = reg; + state->i2c_write_buffer[1] = val >> 8; + state->i2c_write_buffer[2] = val & 0xff; + + memset(state->msg, 0, sizeof(struct i2c_msg)); + state->msg[0].addr = state->cfg->i2c_address; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = 3; + + if (i2c_transfer(state->i2c, state->msg, 1) != 1) { printk(KERN_WARNING "DiB0070 I2C write failed\n"); return -EREMOTEIO; } diff --git a/drivers/media/dvb/frontends/dib0090.c b/drivers/media/dvb/frontends/dib0090.c index 52ff1a252a90..c9c935ae41e4 100644 --- a/drivers/media/dvb/frontends/dib0090.c +++ b/drivers/media/dvb/frontends/dib0090.c @@ -191,6 +191,11 @@ struct dib0090_state { u8 wbd_calibration_gain; const struct dib0090_wbd_slope *current_wbd_table; u16 wbdmux; + + /* for the I2C transfer */ + struct i2c_msg msg[2]; + u8 i2c_write_buffer[3]; + u8 i2c_read_buffer[2]; }; struct dib0090_fw_state { @@ -198,27 +203,48 @@ struct dib0090_fw_state { struct dvb_frontend *fe; struct dib0090_identity identity; const struct dib0090_config *config; + + /* for the I2C transfer */ + struct i2c_msg msg; + u8 i2c_write_buffer[2]; + u8 i2c_read_buffer[2]; }; static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg) { - u8 b[2]; - struct i2c_msg msg[2] = { - {.addr = state->config->i2c_address, .flags = 0, .buf = ®, .len = 1}, - {.addr = state->config->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2}, - }; - if (i2c_transfer(state->i2c, msg, 2) != 2) { + state->i2c_write_buffer[0] = reg; + + memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); + state->msg[0].addr = state->config->i2c_address; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = 1; + state->msg[1].addr = state->config->i2c_address; + state->msg[1].flags = I2C_M_RD; + state->msg[1].buf = state->i2c_read_buffer; + state->msg[1].len = 2; + + if (i2c_transfer(state->i2c, state->msg, 2) != 2) { printk(KERN_WARNING "DiB0090 I2C read failed\n"); return 0; } - return (b[0] << 8) | b[1]; + + return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; } static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) { - u8 b[3] = { reg & 0xff, val >> 8, val & 0xff }; - struct i2c_msg msg = {.addr = state->config->i2c_address, .flags = 0, .buf = b, .len = 3 }; - if (i2c_transfer(state->i2c, &msg, 1) != 1) { + state->i2c_write_buffer[0] = reg & 0xff; + state->i2c_write_buffer[1] = val >> 8; + state->i2c_write_buffer[2] = val & 0xff; + + memset(state->msg, 0, sizeof(struct i2c_msg)); + state->msg[0].addr = state->config->i2c_address; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = 3; + + if (i2c_transfer(state->i2c, state->msg, 1) != 1) { printk(KERN_WARNING "DiB0090 I2C write failed\n"); return -EREMOTEIO; } @@ -227,20 +253,31 @@ static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg) { - u8 b[2]; - struct i2c_msg msg = {.addr = reg, .flags = I2C_M_RD, .buf = b, .len = 2 }; - if (i2c_transfer(state->i2c, &msg, 1) != 1) { + state->i2c_write_buffer[0] = reg; + + memset(&state->msg, 0, sizeof(struct i2c_msg)); + state->msg.addr = reg; + state->msg.flags = I2C_M_RD; + state->msg.buf = state->i2c_read_buffer; + state->msg.len = 2; + if (i2c_transfer(state->i2c, &state->msg, 1) != 1) { printk(KERN_WARNING "DiB0090 I2C read failed\n"); return 0; } - return (b[0] << 8) | b[1]; + return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; } static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val) { - u8 b[2] = { val >> 8, val & 0xff }; - struct i2c_msg msg = {.addr = reg, .flags = 0, .buf = b, .len = 2 }; - if (i2c_transfer(state->i2c, &msg, 1) != 1) { + state->i2c_write_buffer[0] = val >> 8; + state->i2c_write_buffer[1] = val & 0xff; + + memset(&state->msg, 0, sizeof(struct i2c_msg)); + state->msg.addr = reg; + state->msg.flags = 0; + state->msg.buf = state->i2c_write_buffer; + state->msg.len = 2; + if (i2c_transfer(state->i2c, &state->msg, 1) != 1) { printk(KERN_WARNING "DiB0090 I2C write failed\n"); return -EREMOTEIO; } diff --git a/drivers/media/dvb/frontends/dib7000m.c b/drivers/media/dvb/frontends/dib7000m.c index 289a79837f24..79cb1c20df24 100644 --- a/drivers/media/dvb/frontends/dib7000m.c +++ b/drivers/media/dvb/frontends/dib7000m.c @@ -50,6 +50,11 @@ struct dib7000m_state { u16 revision; u8 agc_state; + + /* for the I2C transfer */ + struct i2c_msg msg[2]; + u8 i2c_write_buffer[4]; + u8 i2c_read_buffer[2]; }; enum dib7000m_power_mode { @@ -64,29 +69,39 @@ enum dib7000m_power_mode { static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg) { - u8 wb[2] = { (reg >> 8) | 0x80, reg & 0xff }; - u8 rb[2]; - struct i2c_msg msg[2] = { - { .addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2 }, - { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 }, - }; - - if (i2c_transfer(state->i2c_adap, msg, 2) != 2) + state->i2c_write_buffer[0] = (reg >> 8) | 0x80; + state->i2c_write_buffer[1] = reg & 0xff; + + memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); + state->msg[0].addr = state->i2c_addr >> 1; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = 2; + state->msg[1].addr = state->i2c_addr >> 1; + state->msg[1].flags = I2C_M_RD; + state->msg[1].buf = state->i2c_read_buffer; + state->msg[1].len = 2; + + if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2) dprintk("i2c read error on %d",reg); - return (rb[0] << 8) | rb[1]; + return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; } static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val) { - u8 b[4] = { - (reg >> 8) & 0xff, reg & 0xff, - (val >> 8) & 0xff, val & 0xff, - }; - struct i2c_msg msg = { - .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4 - }; - return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; + state->i2c_write_buffer[0] = (reg >> 8) & 0xff; + state->i2c_write_buffer[1] = reg & 0xff; + state->i2c_write_buffer[2] = (val >> 8) & 0xff; + state->i2c_write_buffer[3] = val & 0xff; + + memset(&state->msg[0], 0, sizeof(struct i2c_msg)); + state->msg[0].addr = state->i2c_addr >> 1; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = 4; + + return i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0; } static void dib7000m_write_tab(struct dib7000m_state *state, u16 *buf) { diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c index 900af60b9d36..0c9f40c2a251 100644 --- a/drivers/media/dvb/frontends/dib7000p.c +++ b/drivers/media/dvb/frontends/dib7000p.c @@ -63,6 +63,11 @@ struct dib7000p_state { u16 tuner_enable; struct i2c_adapter dib7090_tuner_adap; + + /* for the I2C transfer */ + struct i2c_msg msg[2]; + u8 i2c_write_buffer[4]; + u8 i2c_read_buffer[2]; }; enum dib7000p_power_mode { @@ -76,29 +81,39 @@ static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff); static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg) { - u8 wb[2] = { reg >> 8, reg & 0xff }; - u8 rb[2]; - struct i2c_msg msg[2] = { - {.addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2}, - {.addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2}, - }; + state->i2c_write_buffer[0] = reg >> 8; + state->i2c_write_buffer[1] = reg & 0xff; + + memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); + state->msg[0].addr = state->i2c_addr >> 1; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = 2; + state->msg[1].addr = state->i2c_addr >> 1; + state->msg[1].flags = I2C_M_RD; + state->msg[1].buf = state->i2c_read_buffer; + state->msg[1].len = 2; - if (i2c_transfer(state->i2c_adap, msg, 2) != 2) + if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2) dprintk("i2c read error on %d", reg); - return (rb[0] << 8) | rb[1]; + return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; } static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val) { - u8 b[4] = { - (reg >> 8) & 0xff, reg & 0xff, - (val >> 8) & 0xff, val & 0xff, - }; - struct i2c_msg msg = { - .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4 - }; - return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; + state->i2c_write_buffer[0] = (reg >> 8) & 0xff; + state->i2c_write_buffer[1] = reg & 0xff; + state->i2c_write_buffer[2] = (val >> 8) & 0xff; + state->i2c_write_buffer[3] = val & 0xff; + + memset(&state->msg[0], 0, sizeof(struct i2c_msg)); + state->msg[0].addr = state->i2c_addr >> 1; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = 4; + + return i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0; } static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf) @@ -1550,11 +1565,24 @@ static void dib7000p_release(struct dvb_frontend *demod) int dib7000pc_detection(struct i2c_adapter *i2c_adap) { - u8 tx[2], rx[2]; + u8 *tx, *rx; struct i2c_msg msg[2] = { - {.addr = 18 >> 1, .flags = 0, .buf = tx, .len = 2}, - {.addr = 18 >> 1, .flags = I2C_M_RD, .buf = rx, .len = 2}, + {.addr = 18 >> 1, .flags = 0, .len = 2}, + {.addr = 18 >> 1, .flags = I2C_M_RD, .len = 2}, }; + int ret = 0; + + tx = kzalloc(2*sizeof(u8), GFP_KERNEL); + if (!tx) + return -ENOMEM; + rx = kzalloc(2*sizeof(u8), GFP_KERNEL); + if (!rx) { + goto rx_memory_error; + ret = -ENOMEM; + } + + msg[0].buf = tx; + msg[1].buf = rx; tx[0] = 0x03; tx[1] = 0x00; @@ -1574,7 +1602,11 @@ int dib7000pc_detection(struct i2c_adapter *i2c_adap) } dprintk("-D- DiB7000PC not detected"); - return 0; + + kfree(rx); +rx_memory_error: + kfree(tx); + return ret; } EXPORT_SYMBOL(dib7000pc_detection); diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c index c1c3e26906e2..7d2ea112ae2b 100644 --- a/drivers/media/dvb/frontends/dib8000.c +++ b/drivers/media/dvb/frontends/dib8000.c @@ -35,6 +35,8 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); struct i2c_device { struct i2c_adapter *adap; u8 addr; + u8 *i2c_write_buffer; + u8 *i2c_read_buffer; }; struct dib8000_state { @@ -70,6 +72,11 @@ struct dib8000_state { u32 status; struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS]; + + /* for the I2C transfer */ + struct i2c_msg msg[2]; + u8 i2c_write_buffer[4]; + u8 i2c_read_buffer[2]; }; enum dib8000_power_mode { @@ -79,22 +86,41 @@ enum dib8000_power_mode { static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg) { - u8 wb[2] = { reg >> 8, reg & 0xff }; - u8 rb[2]; struct i2c_msg msg[2] = { - {.addr = i2c->addr >> 1,.flags = 0,.buf = wb,.len = 2}, - {.addr = i2c->addr >> 1,.flags = I2C_M_RD,.buf = rb,.len = 2}, + {.addr = i2c->addr >> 1, .flags = 0, + .buf = i2c->i2c_write_buffer, .len = 2}, + {.addr = i2c->addr >> 1, .flags = I2C_M_RD, + .buf = i2c->i2c_read_buffer, .len = 2}, }; + msg[0].buf[0] = reg >> 8; + msg[0].buf[1] = reg & 0xff; + if (i2c_transfer(i2c->adap, msg, 2) != 2) dprintk("i2c read error on %d", reg); - return (rb[0] << 8) | rb[1]; + return (msg[1].buf[0] << 8) | msg[1].buf[1]; } static u16 dib8000_read_word(struct dib8000_state *state, u16 reg) { - return dib8000_i2c_read16(&state->i2c, reg); + state->i2c_write_buffer[0] = reg >> 8; + state->i2c_write_buffer[1] = reg & 0xff; + + memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); + state->msg[0].addr = state->i2c.addr >> 1; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = 2; + state->msg[1].addr = state->i2c.addr >> 1; + state->msg[1].flags = I2C_M_RD; + state->msg[1].buf = state->i2c_read_buffer; + state->msg[1].len = 2; + + if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2) + dprintk("i2c read error on %d", reg); + + return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; } static u32 dib8000_read32(struct dib8000_state *state, u16 reg) @@ -109,19 +135,34 @@ static u32 dib8000_read32(struct dib8000_state *state, u16 reg) static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val) { - u8 b[4] = { - (reg >> 8) & 0xff, reg & 0xff, - (val >> 8) & 0xff, val & 0xff, - }; - struct i2c_msg msg = { - .addr = i2c->addr >> 1,.flags = 0,.buf = b,.len = 4 - }; - return i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0; + struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, + .buf = i2c->i2c_write_buffer, .len = 4}; + int ret = 0; + + msg.buf[0] = (reg >> 8) & 0xff; + msg.buf[1] = reg & 0xff; + msg.buf[2] = (val >> 8) & 0xff; + msg.buf[3] = val & 0xff; + + ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0; + + return ret; } static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val) { - return dib8000_i2c_write16(&state->i2c, reg, val); + state->i2c_write_buffer[0] = (reg >> 8) & 0xff; + state->i2c_write_buffer[1] = reg & 0xff; + state->i2c_write_buffer[2] = (val >> 8) & 0xff; + state->i2c_write_buffer[3] = val & 0xff; + + memset(&state->msg[0], 0, sizeof(struct i2c_msg)); + state->msg[0].addr = state->i2c.addr >> 1; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = 4; + + return i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ? -EREMOTEIO : 0; } static const s16 coeff_2k_sb_1seg_dqpsk[8] = { @@ -980,30 +1021,31 @@ static void dib8000_update_timf(struct dib8000_state *state) dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default); } +static const u16 adc_target_16dB[11] = { + (1 << 13) - 825 - 117, + (1 << 13) - 837 - 117, + (1 << 13) - 811 - 117, + (1 << 13) - 766 - 117, + (1 << 13) - 737 - 117, + (1 << 13) - 693 - 117, + (1 << 13) - 648 - 117, + (1 << 13) - 619 - 117, + (1 << 13) - 575 - 117, + (1 << 13) - 531 - 117, + (1 << 13) - 501 - 117 +}; +static const u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 }; + static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosearching) { u16 mode, max_constellation, seg_diff_mask = 0, nbseg_diff = 0; u8 guard, crate, constellation, timeI; - u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 }; u16 i, coeff[4], P_cfr_left_edge = 0, P_cfr_right_edge = 0, seg_mask13 = 0x1fff; // All 13 segments enabled const s16 *ncoeff = NULL, *ana_fe; u16 tmcc_pow = 0; u16 coff_pow = 0x2800; u16 init_prbs = 0xfff; u16 ana_gain = 0; - u16 adc_target_16dB[11] = { - (1 << 13) - 825 - 117, - (1 << 13) - 837 - 117, - (1 << 13) - 811 - 117, - (1 << 13) - 766 - 117, - (1 << 13) - 737 - 117, - (1 << 13) - 693 - 117, - (1 << 13) - 648 - 117, - (1 << 13) - 619 - 117, - (1 << 13) - 575 - 117, - (1 << 13) - 531 - 117, - (1 << 13) - 501 - 117 - }; if (state->ber_monitored_layer != LAYER_ALL) dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & 0x60) | state->ber_monitored_layer); @@ -2379,10 +2421,22 @@ EXPORT_SYMBOL(dib8000_get_slave_frontend); int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr) { - int k = 0; + int k = 0, ret = 0; u8 new_addr = 0; struct i2c_device client = {.adap = host }; + client.i2c_write_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL); + if (!client.i2c_write_buffer) { + dprintk("%s: not enough memory", __func__); + return -ENOMEM; + } + client.i2c_read_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL); + if (!client.i2c_read_buffer) { + dprintk("%s: not enough memory", __func__); + ret = -ENOMEM; + goto error_memory; + } + for (k = no_of_demods - 1; k >= 0; k--) { /* designated i2c address */ new_addr = first_addr + (k << 1); @@ -2394,7 +2448,8 @@ int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 defau client.addr = default_addr; if (dib8000_identify(&client) == 0) { dprintk("#%d: not identified", k); - return -EINVAL; + ret = -EINVAL; + goto error; } } @@ -2420,7 +2475,12 @@ int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 defau dib8000_i2c_write16(&client, 1286, 0); } - return 0; +error: + kfree(client.i2c_read_buffer); +error_memory: + kfree(client.i2c_write_buffer); + + return ret; } EXPORT_SYMBOL(dib8000_i2c_enumeration); @@ -2519,6 +2579,8 @@ struct dvb_frontend *dib8000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, s memcpy(&state->cfg, cfg, sizeof(struct dib8000_config)); state->i2c.adap = i2c_adap; state->i2c.addr = i2c_addr; + state->i2c.i2c_write_buffer = state->i2c_write_buffer; + state->i2c.i2c_read_buffer = state->i2c_read_buffer; state->gpio_val = cfg->gpio_val; state->gpio_dir = cfg->gpio_dir; diff --git a/drivers/media/dvb/frontends/dib9000.c b/drivers/media/dvb/frontends/dib9000.c index b25ef2bb5078..a0855883b5ce 100644 --- a/drivers/media/dvb/frontends/dib9000.c +++ b/drivers/media/dvb/frontends/dib9000.c @@ -27,6 +27,8 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); struct i2c_device { struct i2c_adapter *i2c_adap; u8 i2c_addr; + u8 *i2c_read_buffer; + u8 *i2c_write_buffer; }; /* lock */ @@ -92,11 +94,16 @@ struct dib9000_state { struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS]; u16 component_bus_speed; + + /* for the I2C transfer */ + struct i2c_msg msg[2]; + u8 i2c_write_buffer[255]; + u8 i2c_read_buffer[255]; }; -u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +static const u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 + 0, 0, 0, 0, 0, 0, 0, 0 }; enum dib9000_power_mode { @@ -217,25 +224,33 @@ static u16 dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 * b, u32 u32 chunk_size = 126; u32 l; int ret; - u8 wb[2] = { reg >> 8, reg & 0xff }; - struct i2c_msg msg[2] = { - {.addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2}, - {.addr = state->i2c.i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = len}, - }; if (state->platform.risc.fw_is_running && (reg < 1024)) return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len); + memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); + state->msg[0].addr = state->i2c.i2c_addr >> 1; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = 2; + state->msg[1].addr = state->i2c.i2c_addr >> 1; + state->msg[1].flags = I2C_M_RD; + state->msg[1].buf = b; + state->msg[1].len = len; + + state->i2c_write_buffer[0] = reg >> 8; + state->i2c_write_buffer[1] = reg & 0xff; + if (attribute & DATA_BUS_ACCESS_MODE_8BIT) - wb[0] |= (1 << 5); + state->i2c_write_buffer[0] |= (1 << 5); if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT) - wb[0] |= (1 << 4); + state->i2c_write_buffer[0] |= (1 << 4); do { l = len < chunk_size ? len : chunk_size; - msg[1].len = l; - msg[1].buf = b; - ret = i2c_transfer(state->i2c.i2c_adap, msg, 2) != 2 ? -EREMOTEIO : 0; + state->msg[1].len = l; + state->msg[1].buf = b; + ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 2) != 2 ? -EREMOTEIO : 0; if (ret != 0) { dprintk("i2c read error on %d", reg); return -EREMOTEIO; @@ -253,50 +268,47 @@ static u16 dib9000_read16_attr(struct dib9000_state *state, u16 reg, u8 * b, u32 static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg) { - u8 b[2]; - u8 wb[2] = { reg >> 8, reg & 0xff }; struct i2c_msg msg[2] = { - {.addr = i2c->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2}, - {.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = 2}, + {.addr = i2c->i2c_addr >> 1, .flags = 0, + .buf = i2c->i2c_write_buffer, .len = 2}, + {.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD, + .buf = i2c->i2c_read_buffer, .len = 2}, }; + i2c->i2c_write_buffer[0] = reg >> 8; + i2c->i2c_write_buffer[1] = reg & 0xff; + if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) { dprintk("read register %x error", reg); return 0; } - return (b[0] << 8) | b[1]; + return (i2c->i2c_read_buffer[0] << 8) | i2c->i2c_read_buffer[1]; } static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg) { - u8 b[2]; - if (dib9000_read16_attr(state, reg, b, 2, 0) != 0) + if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2, 0) != 0) return 0; - return (b[0] << 8 | b[1]); + return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; } static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute) { - u8 b[2]; - if (dib9000_read16_attr(state, reg, b, 2, attribute) != 0) + if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2, + attribute) != 0) return 0; - return (b[0] << 8 | b[1]); + return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; } #define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT) static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * buf, u32 len, u16 attribute) { - u8 b[255]; u32 chunk_size = 126; u32 l; int ret; - struct i2c_msg msg = { - .addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = b, .len = len + 2 - }; - if (state->platform.risc.fw_is_running && (reg < 1024)) { if (dib9000_risc_apb_access_write (state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0) @@ -304,20 +316,26 @@ static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * return 0; } - b[0] = (reg >> 8) & 0xff; - b[1] = (reg) & 0xff; + memset(&state->msg[0], 0, sizeof(struct i2c_msg)); + state->msg[0].addr = state->i2c.i2c_addr >> 1; + state->msg[0].flags = 0; + state->msg[0].buf = state->i2c_write_buffer; + state->msg[0].len = len + 2; + + state->i2c_write_buffer[0] = (reg >> 8) & 0xff; + state->i2c_write_buffer[1] = (reg) & 0xff; if (attribute & DATA_BUS_ACCESS_MODE_8BIT) - b[0] |= (1 << 5); + state->i2c_write_buffer[0] |= (1 << 5); if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT) - b[0] |= (1 << 4); + state->i2c_write_buffer[0] |= (1 << 4); do { l = len < chunk_size ? len : chunk_size; - msg.len = l + 2; - memcpy(&b[2], buf, l); + state->msg[0].len = l + 2; + memcpy(&state->i2c_write_buffer[2], buf, l); - ret = i2c_transfer(state->i2c.i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; + ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0; buf += l; len -= l; @@ -331,11 +349,16 @@ static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val) { - u8 b[4] = { (reg >> 8) & 0xff, reg & 0xff, (val >> 8) & 0xff, val & 0xff }; struct i2c_msg msg = { - .addr = i2c->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4 + .addr = i2c->i2c_addr >> 1, .flags = 0, + .buf = i2c->i2c_write_buffer, .len = 4 }; + i2c->i2c_write_buffer[0] = (reg >> 8) & 0xff; + i2c->i2c_write_buffer[1] = reg & 0xff; + i2c->i2c_write_buffer[2] = (val >> 8) & 0xff; + i2c->i2c_write_buffer[3] = val & 0xff; + return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; } @@ -1015,8 +1038,8 @@ static int dib9000_fw_memmbx_sync(struct dib9000_state *state, u8 i) return 0; dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i); do { - dib9000_risc_mem_read(state, FE_MM_RW_SYNC, &i, 1); - } while (i && index_loop--); + dib9000_risc_mem_read(state, FE_MM_RW_SYNC, state->i2c_read_buffer, 1); + } while (state->i2c_read_buffer[0] && index_loop--); if (index_loop > 0) return 0; @@ -1139,7 +1162,7 @@ static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_p s8 intlv_native; }; - struct dibDVBTChannel ch; + struct dibDVBTChannel *ch; int ret = 0; DibAcquireLock(&state->platform.risc.mem_mbx_lock); @@ -1148,9 +1171,12 @@ static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_p ret = -EIO; } - dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION, (u8 *) &ch, sizeof(struct dibDVBTChannel)); + dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION, + state->i2c_read_buffer, sizeof(struct dibDVBTChannel)); + ch = (struct dibDVBTChannel *)state->i2c_read_buffer; + - switch (ch.spectrum_inversion & 0x7) { + switch (ch->spectrum_inversion & 0x7) { case 1: state->fe[0]->dtv_property_cache.inversion = INVERSION_ON; break; @@ -1162,7 +1188,7 @@ static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_p state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO; break; } - switch (ch.nfft) { + switch (ch->nfft) { case 0: state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K; break; @@ -1177,7 +1203,7 @@ static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_p state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO; break; } - switch (ch.guard) { + switch (ch->guard) { case 0: state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32; break; @@ -1195,7 +1221,7 @@ static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_p state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO; break; } - switch (ch.constellation) { + switch (ch->constellation) { case 2: state->fe[0]->dtv_property_cache.modulation = QAM_64; break; @@ -1210,7 +1236,7 @@ static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_p state->fe[0]->dtv_property_cache.modulation = QAM_AUTO; break; } - switch (ch.hrch) { + switch (ch->hrch) { case 0: state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE; break; @@ -1222,7 +1248,7 @@ static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_p state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO; break; } - switch (ch.code_rate_hp) { + switch (ch->code_rate_hp) { case 1: state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2; break; @@ -1243,7 +1269,7 @@ static int dib9000_fw_get_channel(struct dvb_frontend *fe, struct dvb_frontend_p state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO; break; } - switch (ch.code_rate_lp) { + switch (ch->code_rate_lp) { case 1: state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2; break; @@ -1439,9 +1465,10 @@ static int dib9000_fw_tune(struct dvb_frontend *fe, struct dvb_frontend_paramete break; case CT_DEMOD_STEP_1: if (search) - dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, (u8 *) &i, 1); + dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, state->i2c_read_buffer, 1); else - dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, (u8 *) &i, 1); + dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, state->i2c_read_buffer, 1); + i = (s8)state->i2c_read_buffer[0]; switch (i) { /* something happened */ case 0: break; @@ -2038,14 +2065,17 @@ static int dib9000_read_status(struct dvb_frontend *fe, fe_status_t * stat) static int dib9000_read_ber(struct dvb_frontend *fe, u32 * ber) { struct dib9000_state *state = fe->demodulator_priv; - u16 c[16]; + u16 *c; DibAcquireLock(&state->platform.risc.mem_mbx_lock); if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) return -EIO; - dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c)); + dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, + state->i2c_read_buffer, 16 * 2); DibReleaseLock(&state->platform.risc.mem_mbx_lock); + c = (u16 *)state->i2c_read_buffer; + *ber = c[10] << 16 | c[11]; return 0; } @@ -2054,7 +2084,7 @@ static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength) { struct dib9000_state *state = fe->demodulator_priv; u8 index_frontend; - u16 c[16]; + u16 *c = (u16 *)state->i2c_read_buffer; u16 val; *strength = 0; @@ -2069,7 +2099,7 @@ static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength) DibAcquireLock(&state->platform.risc.mem_mbx_lock); if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) return -EIO; - dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c)); + dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2); DibReleaseLock(&state->platform.risc.mem_mbx_lock); val = 65535 - c[4]; @@ -2083,14 +2113,14 @@ static int dib9000_read_signal_strength(struct dvb_frontend *fe, u16 * strength) static u32 dib9000_get_snr(struct dvb_frontend *fe) { struct dib9000_state *state = fe->demodulator_priv; - u16 c[16]; + u16 *c = (u16 *)state->i2c_read_buffer; u32 n, s, exp; u16 val; DibAcquireLock(&state->platform.risc.mem_mbx_lock); if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) return -EIO; - dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c)); + dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2); DibReleaseLock(&state->platform.risc.mem_mbx_lock); val = c[7]; @@ -2137,12 +2167,12 @@ static int dib9000_read_snr(struct dvb_frontend *fe, u16 * snr) static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc) { struct dib9000_state *state = fe->demodulator_priv; - u16 c[16]; + u16 *c = (u16 *)state->i2c_read_buffer; DibAcquireLock(&state->platform.risc.mem_mbx_lock); if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0) return -EIO; - dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c)); + dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2); DibReleaseLock(&state->platform.risc.mem_mbx_lock); *unc = c[12]; @@ -2151,10 +2181,22 @@ static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc) int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, u8 first_addr) { - int k = 0; + int k = 0, ret = 0; u8 new_addr = 0; struct i2c_device client = {.i2c_adap = i2c }; + client.i2c_write_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL); + if (!client.i2c_write_buffer) { + dprintk("%s: not enough memory", __func__); + return -ENOMEM; + } + client.i2c_read_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL); + if (!client.i2c_read_buffer) { + dprintk("%s: not enough memory", __func__); + ret = -ENOMEM; + goto error_memory; + } + client.i2c_addr = default_addr + 16; dib9000_i2c_write16(&client, 1796, 0x0); @@ -2178,7 +2220,8 @@ int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defaul client.i2c_addr = default_addr; if (dib9000_identify(&client) == 0) { dprintk("DiB9000 #%d: not identified", k); - return -EIO; + ret = -EIO; + goto error; } } @@ -2196,7 +2239,12 @@ int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defaul dib9000_i2c_write16(&client, 1795, 0); } - return 0; +error: + kfree(client.i2c_read_buffer); +error_memory: + kfree(client.i2c_write_buffer); + + return ret; } EXPORT_SYMBOL(dib9000_i2c_enumeration); @@ -2263,6 +2311,8 @@ struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, c memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config)); st->i2c.i2c_adap = i2c_adap; st->i2c.i2c_addr = i2c_addr; + st->i2c.i2c_write_buffer = st->i2c_write_buffer; + st->i2c.i2c_read_buffer = st->i2c_read_buffer; st->gpio_dir = DIB9000_GPIO_DEFAULT_DIRECTIONS; st->gpio_val = DIB9000_GPIO_DEFAULT_VALUES; diff --git a/drivers/media/dvb/frontends/dibx000_common.c b/drivers/media/dvb/frontends/dibx000_common.c index f6938f97feb4..dc5d17a67579 100644 --- a/drivers/media/dvb/frontends/dibx000_common.c +++ b/drivers/media/dvb/frontends/dibx000_common.c @@ -10,30 +10,39 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)"); static int dibx000_write_word(struct dibx000_i2c_master *mst, u16 reg, u16 val) { - u8 b[4] = { - (reg >> 8) & 0xff, reg & 0xff, - (val >> 8) & 0xff, val & 0xff, - }; - struct i2c_msg msg = { - .addr = mst->i2c_addr,.flags = 0,.buf = b,.len = 4 - }; - - return i2c_transfer(mst->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; + mst->i2c_write_buffer[0] = (reg >> 8) & 0xff; + mst->i2c_write_buffer[1] = reg & 0xff; + mst->i2c_write_buffer[2] = (val >> 8) & 0xff; + mst->i2c_write_buffer[3] = val & 0xff; + + memset(mst->msg, 0, sizeof(struct i2c_msg)); + mst->msg[0].addr = mst->i2c_addr; + mst->msg[0].flags = 0; + mst->msg[0].buf = mst->i2c_write_buffer; + mst->msg[0].len = 4; + + return i2c_transfer(mst->i2c_adap, mst->msg, 1) != 1 ? -EREMOTEIO : 0; } static u16 dibx000_read_word(struct dibx000_i2c_master *mst, u16 reg) { - u8 wb[2] = { reg >> 8, reg & 0xff }; - u8 rb[2]; - struct i2c_msg msg[2] = { - {.addr = mst->i2c_addr, .flags = 0, .buf = wb, .len = 2}, - {.addr = mst->i2c_addr, .flags = I2C_M_RD, .buf = rb, .len = 2}, - }; - - if (i2c_transfer(mst->i2c_adap, msg, 2) != 2) + mst->i2c_write_buffer[0] = reg >> 8; + mst->i2c_write_buffer[1] = reg & 0xff; + + memset(mst->msg, 0, 2 * sizeof(struct i2c_msg)); + mst->msg[0].addr = mst->i2c_addr; + mst->msg[0].flags = 0; + mst->msg[0].buf = mst->i2c_write_buffer; + mst->msg[0].len = 2; + mst->msg[1].addr = mst->i2c_addr; + mst->msg[1].flags = I2C_M_RD; + mst->msg[1].buf = mst->i2c_read_buffer; + mst->msg[1].len = 2; + + if (i2c_transfer(mst->i2c_adap, mst->msg, 2) != 2) dprintk("i2c read error on %d", reg); - return (rb[0] << 8) | rb[1]; + return (mst->i2c_read_buffer[0] << 8) | mst->i2c_read_buffer[1]; } static int dibx000_is_i2c_done(struct dibx000_i2c_master *mst) @@ -248,26 +257,32 @@ static int dibx000_i2c_gated_gpio67_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num) { struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap); - struct i2c_msg m[2 + num]; - u8 tx_open[4], tx_close[4]; - memset(m, 0, sizeof(struct i2c_msg) * (2 + num)); + if (num > 32) { + dprintk("%s: too much I2C message to be transmitted (%i).\ + Maximum is 32", __func__, num); + return -ENOMEM; + } + + memset(mst->msg, 0, sizeof(struct i2c_msg) * (2 + num)); dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_6_7); - dibx000_i2c_gate_ctrl(mst, tx_open, msg[0].addr, 1); - m[0].addr = mst->i2c_addr; - m[0].buf = tx_open; - m[0].len = 4; + /* open the gate */ + dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[0], msg[0].addr, 1); + mst->msg[0].addr = mst->i2c_addr; + mst->msg[0].buf = &mst->i2c_write_buffer[0]; + mst->msg[0].len = 4; - memcpy(&m[1], msg, sizeof(struct i2c_msg) * num); + memcpy(&mst->msg[1], msg, sizeof(struct i2c_msg) * num); - dibx000_i2c_gate_ctrl(mst, tx_close, 0, 0); - m[num + 1].addr = mst->i2c_addr; - m[num + 1].buf = tx_close; - m[num + 1].len = 4; + /* close the gate */ + dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[4], 0, 0); + mst->msg[num + 1].addr = mst->i2c_addr; + mst->msg[num + 1].buf = &mst->i2c_write_buffer[4]; + mst->msg[num + 1].len = 4; - return i2c_transfer(mst->i2c_adap, m, 2 + num) == 2 + num ? num : -EIO; + return i2c_transfer(mst->i2c_adap, mst->msg, 2 + num) == 2 + num ? num : -EIO; } static struct i2c_algorithm dibx000_i2c_gated_gpio67_algo = { @@ -279,26 +294,32 @@ static int dibx000_i2c_gated_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num) { struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap); - struct i2c_msg m[2 + num]; - u8 tx_open[4], tx_close[4]; - memset(m, 0, sizeof(struct i2c_msg) * (2 + num)); + if (num > 32) { + dprintk("%s: too much I2C message to be transmitted (%i).\ + Maximum is 32", __func__, num); + return -ENOMEM; + } + + memset(mst->msg, 0, sizeof(struct i2c_msg) * (2 + num)); dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_TUNER); - dibx000_i2c_gate_ctrl(mst, tx_open, msg[0].addr, 1); - m[0].addr = mst->i2c_addr; - m[0].buf = tx_open; - m[0].len = 4; + /* open the gate */ + dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[0], msg[0].addr, 1); + mst->msg[0].addr = mst->i2c_addr; + mst->msg[0].buf = &mst->i2c_write_buffer[0]; + mst->msg[0].len = 4; - memcpy(&m[1], msg, sizeof(struct i2c_msg) * num); + memcpy(&mst->msg[1], msg, sizeof(struct i2c_msg) * num); - dibx000_i2c_gate_ctrl(mst, tx_close, 0, 0); - m[num + 1].addr = mst->i2c_addr; - m[num + 1].buf = tx_close; - m[num + 1].len = 4; + /* close the gate */ + dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[4], 0, 0); + mst->msg[num + 1].addr = mst->i2c_addr; + mst->msg[num + 1].buf = &mst->i2c_write_buffer[4]; + mst->msg[num + 1].len = 4; - return i2c_transfer(mst->i2c_adap, m, 2 + num) == 2 + num ? num : -EIO; + return i2c_transfer(mst->i2c_adap, mst->msg, 2 + num) == 2 + num ? num : -EIO; } static struct i2c_algorithm dibx000_i2c_gated_tuner_algo = { diff --git a/drivers/media/dvb/frontends/dibx000_common.h b/drivers/media/dvb/frontends/dibx000_common.h index 977d343369aa..f031165c0459 100644 --- a/drivers/media/dvb/frontends/dibx000_common.h +++ b/drivers/media/dvb/frontends/dibx000_common.h @@ -28,6 +28,11 @@ struct dibx000_i2c_master { u8 i2c_addr; u16 base_reg; + + /* for the I2C transfer */ + struct i2c_msg msg[34]; + u8 i2c_write_buffer[8]; + u8 i2c_read_buffer[2]; }; extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, -- cgit v1.2.3 From aff8ab5cc11c2c14b7ae3bb38cbe012c43b7dcef Mon Sep 17 00:00:00 2001 From: Andreas Oberritter <obi@linuxtv.org> Date: Mon, 9 May 2011 00:03:34 +0100 Subject: [media] DVB: return meaningful error codes in dvb_frontend - Return values should not be ORed. Abort early instead. - Return -EINVAL instead of -1. Signed-off-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-core/dvb_frontend.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index 31e2c0d45db3..95c3fec6ae40 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -1325,12 +1325,12 @@ static int dtv_property_process_get(struct dvb_frontend *fe, tvp->u.data = fe->dtv_property_cache.isdbs_ts_id; break; default: - r = -1; + return -EINVAL; } dtv_property_dump(tvp); - return r; + return 0; } static int dtv_property_process_set(struct dvb_frontend *fe, @@ -1342,11 +1342,11 @@ static int dtv_property_process_set(struct dvb_frontend *fe, dtv_property_dump(tvp); /* Allow the frontend to validate incoming properties */ - if (fe->ops.set_property) + if (fe->ops.set_property) { r = fe->ops.set_property(fe, tvp); - - if (r < 0) - return r; + if (r < 0) + return r; + } switch(tvp->cmd) { case DTV_CLEAR: @@ -1365,7 +1365,7 @@ static int dtv_property_process_set(struct dvb_frontend *fe, dprintk("%s() Finalised property cache\n", __func__); dtv_property_cache_submit(fe); - r |= dvb_frontend_ioctl_legacy(file, FE_SET_FRONTEND, + r = dvb_frontend_ioctl_legacy(file, FE_SET_FRONTEND, &fepriv->parameters); break; case DTV_FREQUENCY: @@ -1480,7 +1480,7 @@ static int dtv_property_process_set(struct dvb_frontend *fe, fe->dtv_property_cache.isdbs_ts_id = tvp->u.data; break; default: - r = -1; + return -EINVAL; } return r; @@ -1554,8 +1554,10 @@ static int dvb_frontend_ioctl_properties(struct file *file, } for (i = 0; i < tvps->num; i++) { - (tvp + i)->result = dtv_property_process_set(fe, tvp + i, file); - err |= (tvp + i)->result; + err = dtv_property_process_set(fe, tvp + i, file); + if (err < 0) + goto out; + (tvp + i)->result = err; } if(fe->dtv_property_cache.state == DTV_TUNE) @@ -1586,8 +1588,10 @@ static int dvb_frontend_ioctl_properties(struct file *file, } for (i = 0; i < tvps->num; i++) { - (tvp + i)->result = dtv_property_process_get(fe, tvp + i, file); - err |= (tvp + i)->result; + err = dtv_property_process_get(fe, tvp + i, file); + if (err < 0) + goto out; + (tvp + i)->result = err; } if (copy_to_user(tvps->props, tvp, tvps->num * sizeof(struct dtv_property))) { -- cgit v1.2.3 From 94d56ffa0a9bf11dfb602dae9223089e09a8e050 Mon Sep 17 00:00:00 2001 From: Andreas Oberritter <obi@linuxtv.org> Date: Thu, 12 May 2011 18:11:06 -0300 Subject: [media] DVB: Add basic API support for DVB-T2 and bump minor version [steve@stevekerrison.com: Remove private definitions from cxd2820r that existed before API was defined] Signed-off-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Steve Kerrison <steve@stevekerrison.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-core/dvb_frontend.c | 13 +++++++++---- drivers/media/dvb/dvb-core/dvb_frontend.h | 3 +++ drivers/media/dvb/frontends/cxd2820r_priv.h | 12 ------------ include/linux/dvb/frontend.h | 20 ++++++++++++++++---- include/linux/dvb/version.h | 2 +- 5 files changed, 29 insertions(+), 21 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index 95c3fec6ae40..3639edce65e0 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -1148,10 +1148,9 @@ static void dtv_property_adv_params_sync(struct dvb_frontend *fe) break; } - if(c->delivery_system == SYS_ISDBT) { - /* Fake out a generic DVB-T request so we pass validation in the ioctl */ - p->frequency = c->frequency; - p->inversion = c->inversion; + /* Fake out a generic DVB-T request so we pass validation in the ioctl */ + if ((c->delivery_system == SYS_ISDBT) || + (c->delivery_system == SYS_DVBT2)) { p->u.ofdm.constellation = QAM_AUTO; p->u.ofdm.code_rate_HP = FEC_AUTO; p->u.ofdm.code_rate_LP = FEC_AUTO; @@ -1324,6 +1323,9 @@ static int dtv_property_process_get(struct dvb_frontend *fe, case DTV_ISDBS_TS_ID: tvp->u.data = fe->dtv_property_cache.isdbs_ts_id; break; + case DTV_DVBT2_PLP_ID: + tvp->u.data = fe->dtv_property_cache.dvbt2_plp_id; + break; default: return -EINVAL; } @@ -1479,6 +1481,9 @@ static int dtv_property_process_set(struct dvb_frontend *fe, case DTV_ISDBS_TS_ID: fe->dtv_property_cache.isdbs_ts_id = tvp->u.data; break; + case DTV_DVBT2_PLP_ID: + fe->dtv_property_cache.dvbt2_plp_id = tvp->u.data; + break; default: return -EINVAL; } diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.h b/drivers/media/dvb/dvb-core/dvb_frontend.h index 3b860504bf04..5590eb6eb408 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.h +++ b/drivers/media/dvb/dvb-core/dvb_frontend.h @@ -358,6 +358,9 @@ struct dtv_frontend_properties { /* ISDB-T specifics */ u32 isdbs_ts_id; + + /* DVB-T2 specifics */ + u32 dvbt2_plp_id; }; struct dvb_frontend { diff --git a/drivers/media/dvb/frontends/cxd2820r_priv.h b/drivers/media/dvb/frontends/cxd2820r_priv.h index d4e2e0b76c10..25adbeefa6d3 100644 --- a/drivers/media/dvb/frontends/cxd2820r_priv.h +++ b/drivers/media/dvb/frontends/cxd2820r_priv.h @@ -40,18 +40,6 @@ #undef warn #define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg) -/* - * FIXME: These are totally wrong and must be added properly to the API. - * Only temporary solution in order to get driver compile. - */ -#define SYS_DVBT2 SYS_DAB -#define TRANSMISSION_MODE_1K 0 -#define TRANSMISSION_MODE_16K 0 -#define TRANSMISSION_MODE_32K 0 -#define GUARD_INTERVAL_1_128 0 -#define GUARD_INTERVAL_19_128 0 -#define GUARD_INTERVAL_19_256 0 - struct reg_val_mask { u32 reg; u8 val; diff --git a/include/linux/dvb/frontend.h b/include/linux/dvb/frontend.h index 493a2bf85f62..36a3ed63f571 100644 --- a/include/linux/dvb/frontend.h +++ b/include/linux/dvb/frontend.h @@ -175,14 +175,20 @@ typedef enum fe_transmit_mode { TRANSMISSION_MODE_2K, TRANSMISSION_MODE_8K, TRANSMISSION_MODE_AUTO, - TRANSMISSION_MODE_4K + TRANSMISSION_MODE_4K, + TRANSMISSION_MODE_1K, + TRANSMISSION_MODE_16K, + TRANSMISSION_MODE_32K, } fe_transmit_mode_t; typedef enum fe_bandwidth { BANDWIDTH_8_MHZ, BANDWIDTH_7_MHZ, BANDWIDTH_6_MHZ, - BANDWIDTH_AUTO + BANDWIDTH_AUTO, + BANDWIDTH_5_MHZ, + BANDWIDTH_10_MHZ, + BANDWIDTH_1_712_MHZ, } fe_bandwidth_t; @@ -191,7 +197,10 @@ typedef enum fe_guard_interval { GUARD_INTERVAL_1_16, GUARD_INTERVAL_1_8, GUARD_INTERVAL_1_4, - GUARD_INTERVAL_AUTO + GUARD_INTERVAL_AUTO, + GUARD_INTERVAL_1_128, + GUARD_INTERVAL_19_128, + GUARD_INTERVAL_19_256, } fe_guard_interval_t; @@ -305,7 +314,9 @@ struct dvb_frontend_event { #define DTV_ISDBS_TS_ID 42 -#define DTV_MAX_COMMAND DTV_ISDBS_TS_ID +#define DTV_DVBT2_PLP_ID 43 + +#define DTV_MAX_COMMAND DTV_DVBT2_PLP_ID typedef enum fe_pilot { PILOT_ON, @@ -337,6 +348,7 @@ typedef enum fe_delivery_system { SYS_DMBTH, SYS_CMMB, SYS_DAB, + SYS_DVBT2, } fe_delivery_system_t; struct dtv_cmds_h { diff --git a/include/linux/dvb/version.h b/include/linux/dvb/version.h index 5a7546c12688..1421cc84afaa 100644 --- a/include/linux/dvb/version.h +++ b/include/linux/dvb/version.h @@ -24,6 +24,6 @@ #define _DVBVERSION_H_ #define DVB_API_VERSION 5 -#define DVB_API_VERSION_MINOR 2 +#define DVB_API_VERSION_MINOR 3 #endif /*_DVBVERSION_H_*/ -- cgit v1.2.3 From 63952e8c4ae7f3272cd37321a71428f3637f650f Mon Sep 17 00:00:00 2001 From: Andreas Oberritter <obi@linuxtv.org> Date: Fri, 20 May 2011 18:56:23 -0300 Subject: [media] DVB: drxd_hard: handle new bandwidths by returning -EINVAL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/media/dvb/frontends/drxd_hard.c: In function ‘DRX_Start’: drivers/media/dvb/frontends/drxd_hard.c:2327: warning: enumeration value ‘BANDWIDTH_5_MHZ’ not handled in switch drivers/media/dvb/frontends/drxd_hard.c:2327: warning: enumeration value ‘BANDWIDTH_10_MHZ’ not handled in switch drivers/media/dvb/frontends/drxd_hard.c:2327: warning: enumeration value ‘BANDWIDTH_1_712_MHZ’ not handled in switch [mchehab@redhat.com: removed the status = status assignment after the switch] Signed-off-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/drxd_hard.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c index 30a78af424cb..ea4c1c361d2b 100644 --- a/drivers/media/dvb/frontends/drxd_hard.c +++ b/drivers/media/dvb/frontends/drxd_hard.c @@ -2348,8 +2348,9 @@ static int DRX_Start(struct drxd_state *state, s32 off) status = Write16(state, FE_AG_REG_IND_DEL__A, 71, 0x0000); break; + default: + status = -EINVAL; } - status = status; if (status < 0) break; -- cgit v1.2.3 From 7285d4cc2cd4199a5b831a451511ccd6595806fd Mon Sep 17 00:00:00 2001 From: Steve Kerrison <steve@stevekerrison.com> Date: Sun, 8 May 2011 16:17:19 -0300 Subject: [media] cxd2820r: Update frontend capabilities to advertise QAM-256 This is supported in DVB-T2 mode, so added to the T/T2 frontend. Signed-off-by: Steve Kerrison <steve@stevekerrison.com> Acked-by: Antti Palosaari <crope@iki.fi> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/frontends/cxd2820r_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/frontends/cxd2820r_core.c b/drivers/media/dvb/frontends/cxd2820r_core.c index e900c4cad7fd..0779f69db793 100644 --- a/drivers/media/dvb/frontends/cxd2820r_core.c +++ b/drivers/media/dvb/frontends/cxd2820r_core.c @@ -855,7 +855,8 @@ static struct dvb_frontend_ops cxd2820r_ops[2] = { FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_QAM_16 | - FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | + FE_CAN_QAM_64 | FE_CAN_QAM_256 | + FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | -- cgit v1.2.3 From 15cc2bb385ced95be35d13895a67bfe52066778c Mon Sep 17 00:00:00 2001 From: Andreas Oberritter <obi@linuxtv.org> Date: Sun, 8 May 2011 20:03:35 -0300 Subject: [media] DVB: dtv_property_cache_submit shouldn't modifiy the cache - Use const pointers and remove assignments. - delivery_system already gets assigned by DTV_DELIVERY_SYSTEM and dtv_property_cache_sync. Signed-off-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-core/dvb_frontend.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index 3639edce65e0..67558bd26d89 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -1074,7 +1074,7 @@ static void dtv_property_cache_sync(struct dvb_frontend *fe, */ static void dtv_property_legacy_params_sync(struct dvb_frontend *fe) { - struct dtv_frontend_properties *c = &fe->dtv_property_cache; + const struct dtv_frontend_properties *c = &fe->dtv_property_cache; struct dvb_frontend_private *fepriv = fe->frontend_priv; struct dvb_frontend_parameters *p = &fepriv->parameters; @@ -1086,14 +1086,12 @@ static void dtv_property_legacy_params_sync(struct dvb_frontend *fe) dprintk("%s() Preparing QPSK req\n", __func__); p->u.qpsk.symbol_rate = c->symbol_rate; p->u.qpsk.fec_inner = c->fec_inner; - c->delivery_system = SYS_DVBS; break; case FE_QAM: dprintk("%s() Preparing QAM req\n", __func__); p->u.qam.symbol_rate = c->symbol_rate; p->u.qam.fec_inner = c->fec_inner; p->u.qam.modulation = c->modulation; - c->delivery_system = SYS_DVBC_ANNEX_AC; break; case FE_OFDM: dprintk("%s() Preparing OFDM req\n", __func__); @@ -1111,15 +1109,10 @@ static void dtv_property_legacy_params_sync(struct dvb_frontend *fe) p->u.ofdm.transmission_mode = c->transmission_mode; p->u.ofdm.guard_interval = c->guard_interval; p->u.ofdm.hierarchy_information = c->hierarchy; - c->delivery_system = SYS_DVBT; break; case FE_ATSC: dprintk("%s() Preparing VSB req\n", __func__); p->u.vsb.modulation = c->modulation; - if ((c->modulation == VSB_8) || (c->modulation == VSB_16)) - c->delivery_system = SYS_ATSC; - else - c->delivery_system = SYS_DVBC_ANNEX_B; break; } } @@ -1129,7 +1122,7 @@ static void dtv_property_legacy_params_sync(struct dvb_frontend *fe) */ static void dtv_property_adv_params_sync(struct dvb_frontend *fe) { - struct dtv_frontend_properties *c = &fe->dtv_property_cache; + const struct dtv_frontend_properties *c = &fe->dtv_property_cache; struct dvb_frontend_private *fepriv = fe->frontend_priv; struct dvb_frontend_parameters *p = &fepriv->parameters; @@ -1170,7 +1163,7 @@ static void dtv_property_adv_params_sync(struct dvb_frontend *fe) static void dtv_property_cache_submit(struct dvb_frontend *fe) { - struct dtv_frontend_properties *c = &fe->dtv_property_cache; + const struct dtv_frontend_properties *c = &fe->dtv_property_cache; /* For legacy delivery systems we don't need the delivery_system to * be specified, but we populate the older structures from the cache -- cgit v1.2.3 From e23d9ae343f9d196382ab213612d76126f9c99af Mon Sep 17 00:00:00 2001 From: Andreas Oberritter <obi@linuxtv.org> Date: Sun, 8 May 2011 20:03:36 -0300 Subject: [media] DVB: call get_property at the end of dtv_property_process_get - Drivers should be able to override properties returned to the user. - The default values get prefilled from the cache. Signed-off-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-core/dvb_frontend.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index 67558bd26d89..fe6cd73620e6 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -1196,14 +1196,7 @@ static int dtv_property_process_get(struct dvb_frontend *fe, struct dtv_property *tvp, struct file *file) { - int r = 0; - - /* Allow the frontend to validate incoming properties */ - if (fe->ops.get_property) - r = fe->ops.get_property(fe, tvp); - - if (r < 0) - return r; + int r; switch(tvp->cmd) { case DTV_FREQUENCY: @@ -1323,6 +1316,13 @@ static int dtv_property_process_get(struct dvb_frontend *fe, return -EINVAL; } + /* Allow the frontend to override outgoing properties */ + if (fe->ops.get_property) { + r = fe->ops.get_property(fe, tvp); + if (r < 0) + return r; + } + dtv_property_dump(tvp); return 0; -- cgit v1.2.3 From 61cb27af660168e3ad9a8922508c44a7d7453927 Mon Sep 17 00:00:00 2001 From: Andreas Oberritter <obi@linuxtv.org> Date: Sun, 8 May 2011 20:03:37 -0300 Subject: [media] DVB: dvb_frontend: rename parameters to parameters_in - Preparation to distinguish input parameters from output parameters. Signed-off-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-core/dvb_frontend.c | 60 +++++++++++++++---------------- 1 file changed, 30 insertions(+), 30 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index fe6cd73620e6..19ffb7178e8f 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -105,7 +105,7 @@ struct dvb_frontend_private { /* thread/frontend values */ struct dvb_device *dvbdev; - struct dvb_frontend_parameters parameters; + struct dvb_frontend_parameters parameters_in; struct dvb_fe_events events; struct semaphore sem; struct list_head list_head; @@ -160,7 +160,7 @@ static void dvb_frontend_add_event(struct dvb_frontend *fe, fe_status_t status) e = &events->events[events->eventw]; - memcpy (&e->parameters, &fepriv->parameters, + memcpy (&e->parameters, &fepriv->parameters_in, sizeof (struct dvb_frontend_parameters)); if (status & FE_HAS_LOCK) @@ -277,12 +277,12 @@ static int dvb_frontend_swzigzag_autotune(struct dvb_frontend *fe, int check_wra int ready = 0; int fe_set_err = 0; struct dvb_frontend_private *fepriv = fe->frontend_priv; - int original_inversion = fepriv->parameters.inversion; - u32 original_frequency = fepriv->parameters.frequency; + int original_inversion = fepriv->parameters_in.inversion; + u32 original_frequency = fepriv->parameters_in.frequency; /* are we using autoinversion? */ autoinversion = ((!(fe->ops.info.caps & FE_CAN_INVERSION_AUTO)) && - (fepriv->parameters.inversion == INVERSION_AUTO)); + (fepriv->parameters_in.inversion == INVERSION_AUTO)); /* setup parameters correctly */ while(!ready) { @@ -348,18 +348,18 @@ static int dvb_frontend_swzigzag_autotune(struct dvb_frontend *fe, int check_wra fepriv->auto_step, fepriv->auto_sub_step, fepriv->started_auto_step); /* set the frontend itself */ - fepriv->parameters.frequency += fepriv->lnb_drift; + fepriv->parameters_in.frequency += fepriv->lnb_drift; if (autoinversion) - fepriv->parameters.inversion = fepriv->inversion; + fepriv->parameters_in.inversion = fepriv->inversion; if (fe->ops.set_frontend) - fe_set_err = fe->ops.set_frontend(fe, &fepriv->parameters); + fe_set_err = fe->ops.set_frontend(fe, &fepriv->parameters_in); if (fe_set_err < 0) { fepriv->state = FESTATE_ERROR; return fe_set_err; } - fepriv->parameters.frequency = original_frequency; - fepriv->parameters.inversion = original_inversion; + fepriv->parameters_in.frequency = original_frequency; + fepriv->parameters_in.inversion = original_inversion; fepriv->auto_sub_step++; return 0; @@ -383,7 +383,7 @@ static void dvb_frontend_swzigzag(struct dvb_frontend *fe) if (fepriv->state & FESTATE_RETUNE) { if (fe->ops.set_frontend) retval = fe->ops.set_frontend(fe, - &fepriv->parameters); + &fepriv->parameters_in); if (retval < 0) fepriv->state = FESTATE_ERROR; else @@ -413,8 +413,8 @@ static void dvb_frontend_swzigzag(struct dvb_frontend *fe) /* if we're tuned, then we have determined the correct inversion */ if ((!(fe->ops.info.caps & FE_CAN_INVERSION_AUTO)) && - (fepriv->parameters.inversion == INVERSION_AUTO)) { - fepriv->parameters.inversion = fepriv->inversion; + (fepriv->parameters_in.inversion == INVERSION_AUTO)) { + fepriv->parameters_in.inversion = fepriv->inversion; } return; } @@ -594,7 +594,7 @@ restart: if (fepriv->state & FESTATE_RETUNE) { dprintk("%s: Retune requested, FESTATE_RETUNE\n", __func__); - params = &fepriv->parameters; + params = &fepriv->parameters_in; fepriv->state = FESTATE_TUNED; } @@ -616,7 +616,7 @@ restart: dprintk("%s: Frontend ALGO = DVBFE_ALGO_CUSTOM, state=%d\n", __func__, fepriv->state); if (fepriv->state & FESTATE_RETUNE) { dprintk("%s: Retune requested, FESTAT_RETUNE\n", __func__); - params = &fepriv->parameters; + params = &fepriv->parameters_in; fepriv->state = FESTATE_TUNED; } /* Case where we are going to search for a carrier @@ -625,7 +625,7 @@ restart: */ if (fepriv->algo_status & DVBFE_ALGO_SEARCH_AGAIN) { if (fe->ops.search) { - fepriv->algo_status = fe->ops.search(fe, &fepriv->parameters); + fepriv->algo_status = fe->ops.search(fe, &fepriv->parameters_in); /* We did do a search as was requested, the flags are * now unset as well and has the flags wrt to search. */ @@ -636,7 +636,7 @@ restart: /* Track the carrier if the search was successful */ if (fepriv->algo_status == DVBFE_ALGO_SEARCH_SUCCESS) { if (fe->ops.track) - fe->ops.track(fe, &fepriv->parameters); + fe->ops.track(fe, &fepriv->parameters_in); } else { fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN; fepriv->delay = HZ / 2; @@ -1076,7 +1076,7 @@ static void dtv_property_legacy_params_sync(struct dvb_frontend *fe) { const struct dtv_frontend_properties *c = &fe->dtv_property_cache; struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct dvb_frontend_parameters *p = &fepriv->parameters; + struct dvb_frontend_parameters *p = &fepriv->parameters_in; p->frequency = c->frequency; p->inversion = c->inversion; @@ -1124,7 +1124,7 @@ static void dtv_property_adv_params_sync(struct dvb_frontend *fe) { const struct dtv_frontend_properties *c = &fe->dtv_property_cache; struct dvb_frontend_private *fepriv = fe->frontend_priv; - struct dvb_frontend_parameters *p = &fepriv->parameters; + struct dvb_frontend_parameters *p = &fepriv->parameters_in; p->frequency = c->frequency; p->inversion = c->inversion; @@ -1361,7 +1361,7 @@ static int dtv_property_process_set(struct dvb_frontend *fe, dtv_property_cache_submit(fe); r = dvb_frontend_ioctl_legacy(file, FE_SET_FRONTEND, - &fepriv->parameters); + &fepriv->parameters_in); break; case DTV_FREQUENCY: fe->dtv_property_cache.frequency = tvp->u.data; @@ -1792,7 +1792,7 @@ static int dvb_frontend_ioctl_legacy(struct file *file, struct dvb_frontend_tune_settings fetunesettings; if(fe->dtv_property_cache.state == DTV_TUNE) { - if (dvb_frontend_check_parameters(fe, &fepriv->parameters) < 0) { + if (dvb_frontend_check_parameters(fe, &fepriv->parameters_in) < 0) { err = -EINVAL; break; } @@ -1802,9 +1802,9 @@ static int dvb_frontend_ioctl_legacy(struct file *file, break; } - memcpy (&fepriv->parameters, parg, + memcpy (&fepriv->parameters_in, parg, sizeof (struct dvb_frontend_parameters)); - dtv_property_cache_sync(fe, &fepriv->parameters); + dtv_property_cache_sync(fe, &fepriv->parameters_in); } memset(&fetunesettings, 0, sizeof(struct dvb_frontend_tune_settings)); @@ -1813,15 +1813,15 @@ static int dvb_frontend_ioctl_legacy(struct file *file, /* force auto frequency inversion if requested */ if (dvb_force_auto_inversion) { - fepriv->parameters.inversion = INVERSION_AUTO; + fepriv->parameters_in.inversion = INVERSION_AUTO; fetunesettings.parameters.inversion = INVERSION_AUTO; } if (fe->ops.info.type == FE_OFDM) { /* without hierarchical coding code_rate_LP is irrelevant, * so we tolerate the otherwise invalid FEC_NONE setting */ - if (fepriv->parameters.u.ofdm.hierarchy_information == HIERARCHY_NONE && - fepriv->parameters.u.ofdm.code_rate_LP == FEC_NONE) - fepriv->parameters.u.ofdm.code_rate_LP = FEC_AUTO; + if (fepriv->parameters_in.u.ofdm.hierarchy_information == HIERARCHY_NONE && + fepriv->parameters_in.u.ofdm.code_rate_LP == FEC_NONE) + fepriv->parameters_in.u.ofdm.code_rate_LP = FEC_AUTO; } /* get frontend-specific tuning settings */ @@ -1834,8 +1834,8 @@ static int dvb_frontend_ioctl_legacy(struct file *file, switch(fe->ops.info.type) { case FE_QPSK: fepriv->min_delay = HZ/20; - fepriv->step_size = fepriv->parameters.u.qpsk.symbol_rate / 16000; - fepriv->max_drift = fepriv->parameters.u.qpsk.symbol_rate / 2000; + fepriv->step_size = fepriv->parameters_in.u.qpsk.symbol_rate / 16000; + fepriv->max_drift = fepriv->parameters_in.u.qpsk.symbol_rate / 2000; break; case FE_QAM: @@ -1877,7 +1877,7 @@ static int dvb_frontend_ioctl_legacy(struct file *file, case FE_GET_FRONTEND: if (fe->ops.get_frontend) { - memcpy (parg, &fepriv->parameters, sizeof (struct dvb_frontend_parameters)); + memcpy (parg, &fepriv->parameters_in, sizeof (struct dvb_frontend_parameters)); err = fe->ops.get_frontend(fe, (struct dvb_frontend_parameters*) parg); } break; -- cgit v1.2.3 From 68bdee041317116bccaf830a9ff8f46f9aa857bd Mon Sep 17 00:00:00 2001 From: Andreas Oberritter <obi@linuxtv.org> Date: Sun, 8 May 2011 20:03:38 -0300 Subject: [media] DVB: dvb_frontend: remove unused assignments Signed-off-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-core/dvb_frontend.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index 19ffb7178e8f..e24ebf51f076 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -612,11 +612,9 @@ restart: dvb_frontend_swzigzag(fe); break; case DVBFE_ALGO_CUSTOM: - params = NULL; /* have we been asked to RETUNE ? */ dprintk("%s: Frontend ALGO = DVBFE_ALGO_CUSTOM, state=%d\n", __func__, fepriv->state); if (fepriv->state & FESTATE_RETUNE) { dprintk("%s: Retune requested, FESTAT_RETUNE\n", __func__); - params = &fepriv->parameters_in; fepriv->state = FESTATE_TUNED; } /* Case where we are going to search for a carrier -- cgit v1.2.3 From 507277193253cd4ea44d0a55ade37bdef20f3a44 Mon Sep 17 00:00:00 2001 From: Andreas Oberritter <obi@linuxtv.org> Date: Sun, 8 May 2011 20:03:39 -0300 Subject: [media] DVB: dvb_frontend: use shortcut to access fe->dtv_property_cache Signed-off-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-core/dvb_frontend.c | 211 +++++++++++++++--------------- 1 file changed, 108 insertions(+), 103 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index e24ebf51f076..4a05a2c61aba 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -858,34 +858,34 @@ static int dvb_frontend_check_parameters(struct dvb_frontend *fe, static int dvb_frontend_clear_cache(struct dvb_frontend *fe) { + struct dtv_frontend_properties *c = &fe->dtv_property_cache; int i; - memset(&(fe->dtv_property_cache), 0, - sizeof(struct dtv_frontend_properties)); - - fe->dtv_property_cache.state = DTV_CLEAR; - fe->dtv_property_cache.delivery_system = SYS_UNDEFINED; - fe->dtv_property_cache.inversion = INVERSION_AUTO; - fe->dtv_property_cache.fec_inner = FEC_AUTO; - fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO; - fe->dtv_property_cache.bandwidth_hz = BANDWIDTH_AUTO; - fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO; - fe->dtv_property_cache.hierarchy = HIERARCHY_AUTO; - fe->dtv_property_cache.symbol_rate = QAM_AUTO; - fe->dtv_property_cache.code_rate_HP = FEC_AUTO; - fe->dtv_property_cache.code_rate_LP = FEC_AUTO; - - fe->dtv_property_cache.isdbt_partial_reception = -1; - fe->dtv_property_cache.isdbt_sb_mode = -1; - fe->dtv_property_cache.isdbt_sb_subchannel = -1; - fe->dtv_property_cache.isdbt_sb_segment_idx = -1; - fe->dtv_property_cache.isdbt_sb_segment_count = -1; - fe->dtv_property_cache.isdbt_layer_enabled = 0x7; + memset(c, 0, sizeof(struct dtv_frontend_properties)); + + c->state = DTV_CLEAR; + c->delivery_system = SYS_UNDEFINED; + c->inversion = INVERSION_AUTO; + c->fec_inner = FEC_AUTO; + c->transmission_mode = TRANSMISSION_MODE_AUTO; + c->bandwidth_hz = BANDWIDTH_AUTO; + c->guard_interval = GUARD_INTERVAL_AUTO; + c->hierarchy = HIERARCHY_AUTO; + c->symbol_rate = QAM_AUTO; + c->code_rate_HP = FEC_AUTO; + c->code_rate_LP = FEC_AUTO; + + c->isdbt_partial_reception = -1; + c->isdbt_sb_mode = -1; + c->isdbt_sb_subchannel = -1; + c->isdbt_sb_segment_idx = -1; + c->isdbt_sb_segment_count = -1; + c->isdbt_layer_enabled = 0x7; for (i = 0; i < 3; i++) { - fe->dtv_property_cache.layer[i].fec = FEC_AUTO; - fe->dtv_property_cache.layer[i].modulation = QAM_AUTO; - fe->dtv_property_cache.layer[i].interleaving = -1; - fe->dtv_property_cache.layer[i].segment_count = -1; + c->layer[i].fec = FEC_AUTO; + c->layer[i].modulation = QAM_AUTO; + c->layer[i].interleaving = -1; + c->layer[i].segment_count = -1; } return 0; @@ -1194,121 +1194,122 @@ static int dtv_property_process_get(struct dvb_frontend *fe, struct dtv_property *tvp, struct file *file) { + const struct dtv_frontend_properties *c = &fe->dtv_property_cache; int r; switch(tvp->cmd) { case DTV_FREQUENCY: - tvp->u.data = fe->dtv_property_cache.frequency; + tvp->u.data = c->frequency; break; case DTV_MODULATION: - tvp->u.data = fe->dtv_property_cache.modulation; + tvp->u.data = c->modulation; break; case DTV_BANDWIDTH_HZ: - tvp->u.data = fe->dtv_property_cache.bandwidth_hz; + tvp->u.data = c->bandwidth_hz; break; case DTV_INVERSION: - tvp->u.data = fe->dtv_property_cache.inversion; + tvp->u.data = c->inversion; break; case DTV_SYMBOL_RATE: - tvp->u.data = fe->dtv_property_cache.symbol_rate; + tvp->u.data = c->symbol_rate; break; case DTV_INNER_FEC: - tvp->u.data = fe->dtv_property_cache.fec_inner; + tvp->u.data = c->fec_inner; break; case DTV_PILOT: - tvp->u.data = fe->dtv_property_cache.pilot; + tvp->u.data = c->pilot; break; case DTV_ROLLOFF: - tvp->u.data = fe->dtv_property_cache.rolloff; + tvp->u.data = c->rolloff; break; case DTV_DELIVERY_SYSTEM: - tvp->u.data = fe->dtv_property_cache.delivery_system; + tvp->u.data = c->delivery_system; break; case DTV_VOLTAGE: - tvp->u.data = fe->dtv_property_cache.voltage; + tvp->u.data = c->voltage; break; case DTV_TONE: - tvp->u.data = fe->dtv_property_cache.sectone; + tvp->u.data = c->sectone; break; case DTV_API_VERSION: tvp->u.data = (DVB_API_VERSION << 8) | DVB_API_VERSION_MINOR; break; case DTV_CODE_RATE_HP: - tvp->u.data = fe->dtv_property_cache.code_rate_HP; + tvp->u.data = c->code_rate_HP; break; case DTV_CODE_RATE_LP: - tvp->u.data = fe->dtv_property_cache.code_rate_LP; + tvp->u.data = c->code_rate_LP; break; case DTV_GUARD_INTERVAL: - tvp->u.data = fe->dtv_property_cache.guard_interval; + tvp->u.data = c->guard_interval; break; case DTV_TRANSMISSION_MODE: - tvp->u.data = fe->dtv_property_cache.transmission_mode; + tvp->u.data = c->transmission_mode; break; case DTV_HIERARCHY: - tvp->u.data = fe->dtv_property_cache.hierarchy; + tvp->u.data = c->hierarchy; break; /* ISDB-T Support here */ case DTV_ISDBT_PARTIAL_RECEPTION: - tvp->u.data = fe->dtv_property_cache.isdbt_partial_reception; + tvp->u.data = c->isdbt_partial_reception; break; case DTV_ISDBT_SOUND_BROADCASTING: - tvp->u.data = fe->dtv_property_cache.isdbt_sb_mode; + tvp->u.data = c->isdbt_sb_mode; break; case DTV_ISDBT_SB_SUBCHANNEL_ID: - tvp->u.data = fe->dtv_property_cache.isdbt_sb_subchannel; + tvp->u.data = c->isdbt_sb_subchannel; break; case DTV_ISDBT_SB_SEGMENT_IDX: - tvp->u.data = fe->dtv_property_cache.isdbt_sb_segment_idx; + tvp->u.data = c->isdbt_sb_segment_idx; break; case DTV_ISDBT_SB_SEGMENT_COUNT: - tvp->u.data = fe->dtv_property_cache.isdbt_sb_segment_count; + tvp->u.data = c->isdbt_sb_segment_count; break; case DTV_ISDBT_LAYER_ENABLED: - tvp->u.data = fe->dtv_property_cache.isdbt_layer_enabled; + tvp->u.data = c->isdbt_layer_enabled; break; case DTV_ISDBT_LAYERA_FEC: - tvp->u.data = fe->dtv_property_cache.layer[0].fec; + tvp->u.data = c->layer[0].fec; break; case DTV_ISDBT_LAYERA_MODULATION: - tvp->u.data = fe->dtv_property_cache.layer[0].modulation; + tvp->u.data = c->layer[0].modulation; break; case DTV_ISDBT_LAYERA_SEGMENT_COUNT: - tvp->u.data = fe->dtv_property_cache.layer[0].segment_count; + tvp->u.data = c->layer[0].segment_count; break; case DTV_ISDBT_LAYERA_TIME_INTERLEAVING: - tvp->u.data = fe->dtv_property_cache.layer[0].interleaving; + tvp->u.data = c->layer[0].interleaving; break; case DTV_ISDBT_LAYERB_FEC: - tvp->u.data = fe->dtv_property_cache.layer[1].fec; + tvp->u.data = c->layer[1].fec; break; case DTV_ISDBT_LAYERB_MODULATION: - tvp->u.data = fe->dtv_property_cache.layer[1].modulation; + tvp->u.data = c->layer[1].modulation; break; case DTV_ISDBT_LAYERB_SEGMENT_COUNT: - tvp->u.data = fe->dtv_property_cache.layer[1].segment_count; + tvp->u.data = c->layer[1].segment_count; break; case DTV_ISDBT_LAYERB_TIME_INTERLEAVING: - tvp->u.data = fe->dtv_property_cache.layer[1].interleaving; + tvp->u.data = c->layer[1].interleaving; break; case DTV_ISDBT_LAYERC_FEC: - tvp->u.data = fe->dtv_property_cache.layer[2].fec; + tvp->u.data = c->layer[2].fec; break; case DTV_ISDBT_LAYERC_MODULATION: - tvp->u.data = fe->dtv_property_cache.layer[2].modulation; + tvp->u.data = c->layer[2].modulation; break; case DTV_ISDBT_LAYERC_SEGMENT_COUNT: - tvp->u.data = fe->dtv_property_cache.layer[2].segment_count; + tvp->u.data = c->layer[2].segment_count; break; case DTV_ISDBT_LAYERC_TIME_INTERLEAVING: - tvp->u.data = fe->dtv_property_cache.layer[2].interleaving; + tvp->u.data = c->layer[2].interleaving; break; case DTV_ISDBS_TS_ID: - tvp->u.data = fe->dtv_property_cache.isdbs_ts_id; + tvp->u.data = c->isdbs_ts_id; break; case DTV_DVBT2_PLP_ID: - tvp->u.data = fe->dtv_property_cache.dvbt2_plp_id; + tvp->u.data = c->dvbt2_plp_id; break; default: return -EINVAL; @@ -1331,6 +1332,7 @@ static int dtv_property_process_set(struct dvb_frontend *fe, struct file *file) { int r = 0; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; struct dvb_frontend_private *fepriv = fe->frontend_priv; dtv_property_dump(tvp); @@ -1354,7 +1356,7 @@ static int dtv_property_process_set(struct dvb_frontend *fe, * tunerequest so we can pass validation in the FE_SET_FRONTEND * ioctl. */ - fe->dtv_property_cache.state = tvp->cmd; + c->state = tvp->cmd; dprintk("%s() Finalised property cache\n", __func__); dtv_property_cache_submit(fe); @@ -1362,118 +1364,118 @@ static int dtv_property_process_set(struct dvb_frontend *fe, &fepriv->parameters_in); break; case DTV_FREQUENCY: - fe->dtv_property_cache.frequency = tvp->u.data; + c->frequency = tvp->u.data; break; case DTV_MODULATION: - fe->dtv_property_cache.modulation = tvp->u.data; + c->modulation = tvp->u.data; break; case DTV_BANDWIDTH_HZ: - fe->dtv_property_cache.bandwidth_hz = tvp->u.data; + c->bandwidth_hz = tvp->u.data; break; case DTV_INVERSION: - fe->dtv_property_cache.inversion = tvp->u.data; + c->inversion = tvp->u.data; break; case DTV_SYMBOL_RATE: - fe->dtv_property_cache.symbol_rate = tvp->u.data; + c->symbol_rate = tvp->u.data; break; case DTV_INNER_FEC: - fe->dtv_property_cache.fec_inner = tvp->u.data; + c->fec_inner = tvp->u.data; break; case DTV_PILOT: - fe->dtv_property_cache.pilot = tvp->u.data; + c->pilot = tvp->u.data; break; case DTV_ROLLOFF: - fe->dtv_property_cache.rolloff = tvp->u.data; + c->rolloff = tvp->u.data; break; case DTV_DELIVERY_SYSTEM: - fe->dtv_property_cache.delivery_system = tvp->u.data; + c->delivery_system = tvp->u.data; break; case DTV_VOLTAGE: - fe->dtv_property_cache.voltage = tvp->u.data; + c->voltage = tvp->u.data; r = dvb_frontend_ioctl_legacy(file, FE_SET_VOLTAGE, - (void *)fe->dtv_property_cache.voltage); + (void *)c->voltage); break; case DTV_TONE: - fe->dtv_property_cache.sectone = tvp->u.data; + c->sectone = tvp->u.data; r = dvb_frontend_ioctl_legacy(file, FE_SET_TONE, - (void *)fe->dtv_property_cache.sectone); + (void *)c->sectone); break; case DTV_CODE_RATE_HP: - fe->dtv_property_cache.code_rate_HP = tvp->u.data; + c->code_rate_HP = tvp->u.data; break; case DTV_CODE_RATE_LP: - fe->dtv_property_cache.code_rate_LP = tvp->u.data; + c->code_rate_LP = tvp->u.data; break; case DTV_GUARD_INTERVAL: - fe->dtv_property_cache.guard_interval = tvp->u.data; + c->guard_interval = tvp->u.data; break; case DTV_TRANSMISSION_MODE: - fe->dtv_property_cache.transmission_mode = tvp->u.data; + c->transmission_mode = tvp->u.data; break; case DTV_HIERARCHY: - fe->dtv_property_cache.hierarchy = tvp->u.data; + c->hierarchy = tvp->u.data; break; /* ISDB-T Support here */ case DTV_ISDBT_PARTIAL_RECEPTION: - fe->dtv_property_cache.isdbt_partial_reception = tvp->u.data; + c->isdbt_partial_reception = tvp->u.data; break; case DTV_ISDBT_SOUND_BROADCASTING: - fe->dtv_property_cache.isdbt_sb_mode = tvp->u.data; + c->isdbt_sb_mode = tvp->u.data; break; case DTV_ISDBT_SB_SUBCHANNEL_ID: - fe->dtv_property_cache.isdbt_sb_subchannel = tvp->u.data; + c->isdbt_sb_subchannel = tvp->u.data; break; case DTV_ISDBT_SB_SEGMENT_IDX: - fe->dtv_property_cache.isdbt_sb_segment_idx = tvp->u.data; + c->isdbt_sb_segment_idx = tvp->u.data; break; case DTV_ISDBT_SB_SEGMENT_COUNT: - fe->dtv_property_cache.isdbt_sb_segment_count = tvp->u.data; + c->isdbt_sb_segment_count = tvp->u.data; break; case DTV_ISDBT_LAYER_ENABLED: - fe->dtv_property_cache.isdbt_layer_enabled = tvp->u.data; + c->isdbt_layer_enabled = tvp->u.data; break; case DTV_ISDBT_LAYERA_FEC: - fe->dtv_property_cache.layer[0].fec = tvp->u.data; + c->layer[0].fec = tvp->u.data; break; case DTV_ISDBT_LAYERA_MODULATION: - fe->dtv_property_cache.layer[0].modulation = tvp->u.data; + c->layer[0].modulation = tvp->u.data; break; case DTV_ISDBT_LAYERA_SEGMENT_COUNT: - fe->dtv_property_cache.layer[0].segment_count = tvp->u.data; + c->layer[0].segment_count = tvp->u.data; break; case DTV_ISDBT_LAYERA_TIME_INTERLEAVING: - fe->dtv_property_cache.layer[0].interleaving = tvp->u.data; + c->layer[0].interleaving = tvp->u.data; break; case DTV_ISDBT_LAYERB_FEC: - fe->dtv_property_cache.layer[1].fec = tvp->u.data; + c->layer[1].fec = tvp->u.data; break; case DTV_ISDBT_LAYERB_MODULATION: - fe->dtv_property_cache.layer[1].modulation = tvp->u.data; + c->layer[1].modulation = tvp->u.data; break; case DTV_ISDBT_LAYERB_SEGMENT_COUNT: - fe->dtv_property_cache.layer[1].segment_count = tvp->u.data; + c->layer[1].segment_count = tvp->u.data; break; case DTV_ISDBT_LAYERB_TIME_INTERLEAVING: - fe->dtv_property_cache.layer[1].interleaving = tvp->u.data; + c->layer[1].interleaving = tvp->u.data; break; case DTV_ISDBT_LAYERC_FEC: - fe->dtv_property_cache.layer[2].fec = tvp->u.data; + c->layer[2].fec = tvp->u.data; break; case DTV_ISDBT_LAYERC_MODULATION: - fe->dtv_property_cache.layer[2].modulation = tvp->u.data; + c->layer[2].modulation = tvp->u.data; break; case DTV_ISDBT_LAYERC_SEGMENT_COUNT: - fe->dtv_property_cache.layer[2].segment_count = tvp->u.data; + c->layer[2].segment_count = tvp->u.data; break; case DTV_ISDBT_LAYERC_TIME_INTERLEAVING: - fe->dtv_property_cache.layer[2].interleaving = tvp->u.data; + c->layer[2].interleaving = tvp->u.data; break; case DTV_ISDBS_TS_ID: - fe->dtv_property_cache.isdbs_ts_id = tvp->u.data; + c->isdbs_ts_id = tvp->u.data; break; case DTV_DVBT2_PLP_ID: - fe->dtv_property_cache.dvbt2_plp_id = tvp->u.data; + c->dvbt2_plp_id = tvp->u.data; break; default: return -EINVAL; @@ -1487,6 +1489,7 @@ static int dvb_frontend_ioctl(struct file *file, { struct dvb_device *dvbdev = file->private_data; struct dvb_frontend *fe = dvbdev->priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; struct dvb_frontend_private *fepriv = fe->frontend_priv; int err = -EOPNOTSUPP; @@ -1506,7 +1509,7 @@ static int dvb_frontend_ioctl(struct file *file, if ((cmd == FE_SET_PROPERTY) || (cmd == FE_GET_PROPERTY)) err = dvb_frontend_ioctl_properties(file, cmd, parg); else { - fe->dtv_property_cache.state = DTV_UNDEFINED; + c->state = DTV_UNDEFINED; err = dvb_frontend_ioctl_legacy(file, cmd, parg); } @@ -1519,6 +1522,7 @@ static int dvb_frontend_ioctl_properties(struct file *file, { struct dvb_device *dvbdev = file->private_data; struct dvb_frontend *fe = dvbdev->priv; + struct dtv_frontend_properties *c = &fe->dtv_property_cache; int err = 0; struct dtv_properties *tvps = NULL; @@ -1556,7 +1560,7 @@ static int dvb_frontend_ioctl_properties(struct file *file, (tvp + i)->result = err; } - if(fe->dtv_property_cache.state == DTV_TUNE) + if (c->state == DTV_TUNE) dprintk("%s() Property cache is full, tuning\n", __func__); } else @@ -1787,9 +1791,10 @@ static int dvb_frontend_ioctl_legacy(struct file *file, break; case FE_SET_FRONTEND: { + struct dtv_frontend_properties *c = &fe->dtv_property_cache; struct dvb_frontend_tune_settings fetunesettings; - if(fe->dtv_property_cache.state == DTV_TUNE) { + if (c->state == DTV_TUNE) { if (dvb_frontend_check_parameters(fe, &fepriv->parameters_in) < 0) { err = -EINVAL; break; -- cgit v1.2.3 From a5959dbea37973a2440eeba39fba32c79d862ec2 Mon Sep 17 00:00:00 2001 From: Andreas Oberritter <obi@linuxtv.org> Date: Sun, 8 May 2011 20:03:40 -0300 Subject: [media] DVB: dvb_frontend: add parameters_out - Holds the parameters detected by the demod. - Updated on every call to get_frontend, either through ioctl or when a frontend event occurs. - Reset to input parameters after every call to set_frontend, tune or search/track. Signed-off-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-core/dvb_frontend.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index 4a05a2c61aba..3666529e2dd4 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -106,6 +106,7 @@ struct dvb_frontend_private { /* thread/frontend values */ struct dvb_device *dvbdev; struct dvb_frontend_parameters parameters_in; + struct dvb_frontend_parameters parameters_out; struct dvb_fe_events events; struct semaphore sem; struct list_head list_head; @@ -160,12 +161,11 @@ static void dvb_frontend_add_event(struct dvb_frontend *fe, fe_status_t status) e = &events->events[events->eventw]; - memcpy (&e->parameters, &fepriv->parameters_in, - sizeof (struct dvb_frontend_parameters)); - if (status & FE_HAS_LOCK) if (fe->ops.get_frontend) - fe->ops.get_frontend(fe, &e->parameters); + fe->ops.get_frontend(fe, &fepriv->parameters_out); + + e->parameters = fepriv->parameters_out; events->eventw = wp; @@ -353,6 +353,7 @@ static int dvb_frontend_swzigzag_autotune(struct dvb_frontend *fe, int check_wra fepriv->parameters_in.inversion = fepriv->inversion; if (fe->ops.set_frontend) fe_set_err = fe->ops.set_frontend(fe, &fepriv->parameters_in); + fepriv->parameters_out = fepriv->parameters_in; if (fe_set_err < 0) { fepriv->state = FESTATE_ERROR; return fe_set_err; @@ -384,6 +385,7 @@ static void dvb_frontend_swzigzag(struct dvb_frontend *fe) if (fe->ops.set_frontend) retval = fe->ops.set_frontend(fe, &fepriv->parameters_in); + fepriv->parameters_out = fepriv->parameters_in; if (retval < 0) fepriv->state = FESTATE_ERROR; else @@ -600,6 +602,8 @@ restart: if (fe->ops.tune) fe->ops.tune(fe, params, fepriv->tune_mode_flags, &fepriv->delay, &s); + if (params) + fepriv->parameters_out = *params; if (s != fepriv->status && !(fepriv->tune_mode_flags & FE_TUNE_MODE_ONESHOT)) { dprintk("%s: state changed, adding current state\n", __func__); @@ -639,6 +643,7 @@ restart: fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN; fepriv->delay = HZ / 2; } + fepriv->parameters_out = fepriv->parameters_in; fe->ops.read_status(fe, &s); if (s != fepriv->status) { dvb_frontend_add_event(fe, s); /* update event list */ @@ -1880,8 +1885,8 @@ static int dvb_frontend_ioctl_legacy(struct file *file, case FE_GET_FRONTEND: if (fe->ops.get_frontend) { - memcpy (parg, &fepriv->parameters_in, sizeof (struct dvb_frontend_parameters)); - err = fe->ops.get_frontend(fe, (struct dvb_frontend_parameters*) parg); + err = fe->ops.get_frontend(fe, &fepriv->parameters_out); + memcpy(parg, &fepriv->parameters_out, sizeof(struct dvb_frontend_parameters)); } break; -- cgit v1.2.3 From bbe880b4a7c66ba14b67ee7acfbaaaa1c7be2d03 Mon Sep 17 00:00:00 2001 From: Andreas Oberritter <obi@linuxtv.org> Date: Sun, 8 May 2011 20:03:41 -0300 Subject: [media] DVB: allow to read back of detected parameters through S2API Signed-off-by: Andreas Oberritter <obi@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-core/dvb_frontend.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index 3666529e2dd4..98278041d75f 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c @@ -1023,10 +1023,9 @@ static int is_legacy_delivery_system(fe_delivery_system_t s) * it's being used for the legacy or new API, reducing code and complexity. */ static void dtv_property_cache_sync(struct dvb_frontend *fe, - struct dvb_frontend_parameters *p) + struct dtv_frontend_properties *c, + const struct dvb_frontend_parameters *p) { - struct dtv_frontend_properties *c = &fe->dtv_property_cache; - c->frequency = p->frequency; c->inversion = p->inversion; @@ -1200,8 +1199,20 @@ static int dtv_property_process_get(struct dvb_frontend *fe, struct file *file) { const struct dtv_frontend_properties *c = &fe->dtv_property_cache; + struct dvb_frontend_private *fepriv = fe->frontend_priv; + struct dtv_frontend_properties cdetected; int r; + /* + * If the driver implements a get_frontend function, then convert + * detected parameters to S2API properties. + */ + if (fe->ops.get_frontend) { + cdetected = *c; + dtv_property_cache_sync(fe, &cdetected, &fepriv->parameters_out); + c = &cdetected; + } + switch(tvp->cmd) { case DTV_FREQUENCY: tvp->u.data = c->frequency; @@ -1812,7 +1823,7 @@ static int dvb_frontend_ioctl_legacy(struct file *file, memcpy (&fepriv->parameters_in, parg, sizeof (struct dvb_frontend_parameters)); - dtv_property_cache_sync(fe, &fepriv->parameters_in); + dtv_property_cache_sync(fe, c, &fepriv->parameters_in); } memset(&fetunesettings, 0, sizeof(struct dvb_frontend_tune_settings)); -- cgit v1.2.3 From d1402307c23cfeafce2313d936a4a990eb8783f7 Mon Sep 17 00:00:00 2001 From: Stéphane Elmaleh <stephane.elmaleh@laposte.net> Date: Sat, 21 May 2011 07:33:38 -0300 Subject: [media] support for medion dvb stick 1660:1921 [mchehab@redhat.com: The same patch were sent by Alf and by Randoslaw. I've applied the oldest version, just fixing the entry index] Cc: Patrick Boettcher <pboettcher@kernellabs.com> Tested-by: James Huk <huk256@gmail.com> Tested-by: Alf Fahland <alf-f@gmx.de> Signed-off-by: Radoslaw Warowny <radoslaww@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> --- drivers/media/dvb/dvb-usb/dib0700_devices.c | 7 ++++++- drivers/media/dvb/dvb-usb/dvb-usb-ids.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers/media/dvb') diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c index 5c01d25875ed..c519ad5eb731 100644 --- a/drivers/media/dvb/dvb-usb/dib0700_devices.c +++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c @@ -2801,6 +2801,7 @@ struct usb_device_id dib0700_usb_id_table[] = { { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_NIM7090) }, { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_TFE7090PVR) }, { USB_DEVICE(USB_VID_TECHNISAT, USB_PID_TECHNISAT_AIRSTAR_TELESTICK_2) }, +/* 75 */{ USB_DEVICE(USB_VID_MEDION, USB_PID_CREATIX_CTX1921) }, { 0 } /* Terminating entry */ }; MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table); @@ -3410,7 +3411,7 @@ struct dvb_usb_device_properties dib0700_devices[] = { }, }, - .num_device_descs = 3, + .num_device_descs = 4, .devices = { { "DiBcom STK7770P reference design", { &dib0700_usb_id_table[59], NULL }, @@ -3426,6 +3427,10 @@ struct dvb_usb_device_properties dib0700_devices[] = { { &dib0700_usb_id_table[74], NULL }, { NULL }, }, + { "Medion CTX1921 DVB-T USB", + { &dib0700_usb_id_table[75], NULL }, + { NULL }, + }, }, .rc.core = { diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h index 3a8b7446b7b0..21b15495d2d7 100644 --- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h +++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h @@ -91,6 +91,7 @@ #define USB_PID_COMPRO_VIDEOMATE_U500_PC 0x1e80 #define USB_PID_CONCEPTRONIC_CTVDIGRCU 0xe397 #define USB_PID_CONEXANT_D680_DMB 0x86d6 +#define USB_PID_CREATIX_CTX1921 0x1921 #define USB_PID_DIBCOM_HOOK_DEFAULT 0x0064 #define USB_PID_DIBCOM_HOOK_DEFAULT_REENUM 0x0065 #define USB_PID_DIBCOM_MOD3000_COLD 0x0bb8 -- cgit v1.2.3