From 23d51b818151273125e35b1a1ce1b294f7d8c073 Mon Sep 17 00:00:00 2001 From: Matt Hsiao Date: Mon, 31 May 2021 16:55:51 +0800 Subject: misc: hpilo: map iLO shared memory by PCI revision id Starting from iLO ASIC 'Neches' with subsystem device id 0x00E4, bar 5 is used for shared memory region mapping instead of bar 2 because bar 2 is made inaccessible after system POST for security reason. As this holds true for future iLO ASIC generations, it does not make sense to map shared memory region according to the subsystem device id of each following generations. Map iLO shared memory region with PCI revision id that maps to the iLO ASIC generation, starting from Neches (Rev 7). Signed-off-by: Matt Hsiao Link: https://lore.kernel.org/r/20210531085551.26421-1-matt.hsiao@hpe.com Signed-off-by: Greg Kroah-Hartman --- drivers/misc/hpilo.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/misc/hpilo.h') diff --git a/drivers/misc/hpilo.h b/drivers/misc/hpilo.h index f69ff645cac9..d57c34680b09 100644 --- a/drivers/misc/hpilo.h +++ b/drivers/misc/hpilo.h @@ -10,6 +10,9 @@ #define ILO_NAME "hpilo" +/* iLO ASIC PCI revision id */ +#define PCI_REV_ID_NECHES 7 + /* max number of open channel control blocks per device, hw limited to 32 */ #define MAX_CCB 24 /* min number of open channel control blocks per device, hw limited to 32 */ -- cgit v1.2.3