From 394cf0a1ca02e7998c8d01975b60a3cdc121e7d8 Mon Sep 17 00:00:00 2001 From: Sujith Date: Mon, 9 Feb 2009 13:26:54 +0530 Subject: ath9k: Header file cleanup Split the core header files into manageable pieces. Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/eeprom.h | 484 ++++++++++++++++++++++++++++++++++++ 1 file changed, 484 insertions(+) create mode 100644 drivers/net/wireless/ath9k/eeprom.h (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h new file mode 100644 index 000000000000..9eb777465144 --- /dev/null +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -0,0 +1,484 @@ +/* + * Copyright (c) 2008 Atheros Communications Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef EEPROM_H +#define EEPROM_H + +#define AH_USE_EEPROM 0x1 + +#ifdef __BIG_ENDIAN +#define AR5416_EEPROM_MAGIC 0x5aa5 +#else +#define AR5416_EEPROM_MAGIC 0xa55a +#endif + +#define CTRY_DEBUG 0x1ff +#define CTRY_DEFAULT 0 + +#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 +#define AR_EEPROM_EEPCAP_AES_DIS 0x0002 +#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 +#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 +#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 +#define AR_EEPROM_EEPCAP_MAXQCU_S 4 +#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 +#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 +#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 + +#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 +#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 +#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 +#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 +#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 +#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 + +#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 +#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 + +#define AR5416_EEPROM_MAGIC_OFFSET 0x0 +#define AR5416_EEPROM_S 2 +#define AR5416_EEPROM_OFFSET 0x2000 +#define AR5416_EEPROM_MAX 0xae0 + +#define AR5416_EEPROM_START_ADDR \ + (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 + +#define SD_NO_CTL 0xE0 +#define NO_CTL 0xff +#define CTL_MODE_M 7 +#define CTL_11A 0 +#define CTL_11B 1 +#define CTL_11G 2 +#define CTL_2GHT20 5 +#define CTL_5GHT20 6 +#define CTL_2GHT40 7 +#define CTL_5GHT40 8 + +#define EXT_ADDITIVE (0x8000) +#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) +#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) +#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) + +#define SUB_NUM_CTL_MODES_AT_5G_40 2 +#define SUB_NUM_CTL_MODES_AT_2G_40 3 + +#define AR_EEPROM_MAC(i) (0x1d+(i)) +#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) +#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) +#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) + +#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c +#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 +#define AR_EEPROM_RFSILENT_POLARITY 0x0002 +#define AR_EEPROM_RFSILENT_POLARITY_S 1 + +#define EEP_RFSILENT_ENABLED 0x0001 +#define EEP_RFSILENT_ENABLED_S 0 +#define EEP_RFSILENT_POLARITY 0x0002 +#define EEP_RFSILENT_POLARITY_S 1 +#define EEP_RFSILENT_GPIO_SEL 0x001c +#define EEP_RFSILENT_GPIO_SEL_S 2 + +#define AR5416_OPFLAGS_11A 0x01 +#define AR5416_OPFLAGS_11G 0x02 +#define AR5416_OPFLAGS_N_5G_HT40 0x04 +#define AR5416_OPFLAGS_N_2G_HT40 0x08 +#define AR5416_OPFLAGS_N_5G_HT20 0x10 +#define AR5416_OPFLAGS_N_2G_HT20 0x20 + +#define AR5416_EEP_NO_BACK_VER 0x1 +#define AR5416_EEP_VER 0xE +#define AR5416_EEP_VER_MINOR_MASK 0x0FFF +#define AR5416_EEP_MINOR_VER_2 0x2 +#define AR5416_EEP_MINOR_VER_3 0x3 +#define AR5416_EEP_MINOR_VER_7 0x7 +#define AR5416_EEP_MINOR_VER_9 0x9 +#define AR5416_EEP_MINOR_VER_16 0x10 +#define AR5416_EEP_MINOR_VER_17 0x11 +#define AR5416_EEP_MINOR_VER_19 0x13 +#define AR5416_EEP_MINOR_VER_20 0x14 + +#define AR5416_NUM_5G_CAL_PIERS 8 +#define AR5416_NUM_2G_CAL_PIERS 4 +#define AR5416_NUM_5G_20_TARGET_POWERS 8 +#define AR5416_NUM_5G_40_TARGET_POWERS 8 +#define AR5416_NUM_2G_CCK_TARGET_POWERS 3 +#define AR5416_NUM_2G_20_TARGET_POWERS 4 +#define AR5416_NUM_2G_40_TARGET_POWERS 4 +#define AR5416_NUM_CTLS 24 +#define AR5416_NUM_BAND_EDGES 8 +#define AR5416_NUM_PD_GAINS 4 +#define AR5416_PD_GAINS_IN_MASK 4 +#define AR5416_PD_GAIN_ICEPTS 5 +#define AR5416_EEPROM_MODAL_SPURS 5 +#define AR5416_MAX_RATE_POWER 63 +#define AR5416_NUM_PDADC_VALUES 128 +#define AR5416_BCHAN_UNUSED 0xFF +#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 +#define AR5416_MAX_CHAINS 3 +#define AR5416_PWR_TABLE_OFFSET -5 + +/* Rx gain type values */ +#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 +#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 +#define AR5416_EEP_RXGAIN_ORIG 2 + +/* Tx gain type values */ +#define AR5416_EEP_TXGAIN_ORIGINAL 0 +#define AR5416_EEP_TXGAIN_HIGH_POWER 1 + +#define AR5416_EEP4K_START_LOC 64 +#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 +#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 +#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 +#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 +#define AR5416_EEP4K_NUM_CTLS 12 +#define AR5416_EEP4K_NUM_BAND_EDGES 4 +#define AR5416_EEP4K_NUM_PD_GAINS 2 +#define AR5416_EEP4K_PD_GAINS_IN_MASK 4 +#define AR5416_EEP4K_PD_GAIN_ICEPTS 5 +#define AR5416_EEP4K_MAX_CHAINS 1 + +enum eeprom_param { + EEP_NFTHRESH_5, + EEP_NFTHRESH_2, + EEP_MAC_MSW, + EEP_MAC_MID, + EEP_MAC_LSW, + EEP_REG_0, + EEP_REG_1, + EEP_OP_CAP, + EEP_OP_MODE, + EEP_RF_SILENT, + EEP_OB_5, + EEP_DB_5, + EEP_OB_2, + EEP_DB_2, + EEP_MINOR_REV, + EEP_TX_MASK, + EEP_RX_MASK, + EEP_RXGAIN_TYPE, + EEP_TXGAIN_TYPE, + EEP_DAC_HPWR_5G, +}; + +enum ar5416_rates { + rate6mb, rate9mb, rate12mb, rate18mb, + rate24mb, rate36mb, rate48mb, rate54mb, + rate1l, rate2l, rate2s, rate5_5l, + rate5_5s, rate11l, rate11s, rateXr, + rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, + rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, + rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, + rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, + rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, + Ar5416RateSize +}; + +enum ath9k_hal_freq_band { + ATH9K_HAL_FREQ_BAND_5GHZ = 0, + ATH9K_HAL_FREQ_BAND_2GHZ = 1 +}; + +struct base_eep_header { + u16 length; + u16 checksum; + u16 version; + u8 opCapFlags; + u8 eepMisc; + u16 regDmn[2]; + u8 macAddr[6]; + u8 rxMask; + u8 txMask; + u16 rfSilent; + u16 blueToothOptions; + u16 deviceCap; + u32 binBuildNumber; + u8 deviceType; + u8 pwdclkind; + u8 futureBase_1[2]; + u8 rxGainType; + u8 dacHiPwrMode_5G; + u8 futureBase_2; + u8 dacLpMode; + u8 txGainType; + u8 rcChainMask; + u8 desiredScaleCCK; + u8 futureBase_3[23]; +} __packed; + +struct base_eep_header_4k { + u16 length; + u16 checksum; + u16 version; + u8 opCapFlags; + u8 eepMisc; + u16 regDmn[2]; + u8 macAddr[6]; + u8 rxMask; + u8 txMask; + u16 rfSilent; + u16 blueToothOptions; + u16 deviceCap; + u32 binBuildNumber; + u8 deviceType; + u8 futureBase[1]; +} __packed; + + +struct spur_chan { + u16 spurChan; + u8 spurRangeLow; + u8 spurRangeHigh; +} __packed; + +struct modal_eep_header { + u32 antCtrlChain[AR5416_MAX_CHAINS]; + u32 antCtrlCommon; + u8 antennaGainCh[AR5416_MAX_CHAINS]; + u8 switchSettling; + u8 txRxAttenCh[AR5416_MAX_CHAINS]; + u8 rxTxMarginCh[AR5416_MAX_CHAINS]; + u8 adcDesiredSize; + u8 pgaDesiredSize; + u8 xlnaGainCh[AR5416_MAX_CHAINS]; + u8 txEndToXpaOff; + u8 txEndToRxOn; + u8 txFrameToXpaOn; + u8 thresh62; + u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; + u8 xpdGain; + u8 xpd; + u8 iqCalICh[AR5416_MAX_CHAINS]; + u8 iqCalQCh[AR5416_MAX_CHAINS]; + u8 pdGainOverlap; + u8 ob; + u8 db; + u8 xpaBiasLvl; + u8 pwrDecreaseFor2Chain; + u8 pwrDecreaseFor3Chain; + u8 txFrameToDataStart; + u8 txFrameToPaOn; + u8 ht40PowerIncForPdadc; + u8 bswAtten[AR5416_MAX_CHAINS]; + u8 bswMargin[AR5416_MAX_CHAINS]; + u8 swSettleHt40; + u8 xatten2Db[AR5416_MAX_CHAINS]; + u8 xatten2Margin[AR5416_MAX_CHAINS]; + u8 ob_ch1; + u8 db_ch1; + u8 useAnt1:1, + force_xpaon:1, + local_bias:1, + femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1; + u8 miscBits; + u16 xpaBiasLvlFreq[3]; + u8 futureModal[6]; + + struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; +} __packed; + +struct modal_eep_4k_header { + u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; + u32 antCtrlCommon; + u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; + u8 switchSettling; + u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; + u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; + u8 adcDesiredSize; + u8 pgaDesiredSize; + u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; + u8 txEndToXpaOff; + u8 txEndToRxOn; + u8 txFrameToXpaOn; + u8 thresh62; + u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; + u8 xpdGain; + u8 xpd; + u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; + u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; + u8 pdGainOverlap; + u8 ob_01; + u8 db1_01; + u8 xpaBiasLvl; + u8 txFrameToDataStart; + u8 txFrameToPaOn; + u8 ht40PowerIncForPdadc; + u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; + u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; + u8 swSettleHt40; + u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; + u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; + u8 db2_01; + u8 version; + u16 ob_234; + u16 db1_234; + u16 db2_234; + u8 futureModal[4]; + + struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; +} __packed; + + +struct cal_data_per_freq { + u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; + u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; +} __packed; + +struct cal_data_per_freq_4k { + u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; + u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; +} __packed; + +struct cal_target_power_leg { + u8 bChannel; + u8 tPow2x[4]; +} __packed; + +struct cal_target_power_ht { + u8 bChannel; + u8 tPow2x[8]; +} __packed; + + +#ifdef __BIG_ENDIAN_BITFIELD +struct cal_ctl_edges { + u8 bChannel; + u8 flag:2, tPower:6; +} __packed; +#else +struct cal_ctl_edges { + u8 bChannel; + u8 tPower:6, flag:2; +} __packed; +#endif + +struct cal_ctl_data { + struct cal_ctl_edges + ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; +} __packed; + +struct cal_ctl_data_4k { + struct cal_ctl_edges + ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; +} __packed; + +struct ar5416_eeprom_def { + struct base_eep_header baseEepHeader; + u8 custData[64]; + struct modal_eep_header modalHeader[2]; + u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; + u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; + struct cal_data_per_freq + calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; + struct cal_data_per_freq + calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; + struct cal_target_power_leg + calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; + struct cal_target_power_leg + calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; + struct cal_target_power_leg + calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; + u8 ctlIndex[AR5416_NUM_CTLS]; + struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; + u8 padding; +} __packed; + +struct ar5416_eeprom_4k { + struct base_eep_header_4k baseEepHeader; + u8 custData[20]; + struct modal_eep_4k_header modalHeader; + u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; + struct cal_data_per_freq_4k + calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; + struct cal_target_power_leg + calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; + struct cal_target_power_leg + calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; + struct cal_target_power_ht + calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; + u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; + struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; + u8 padding; +} __packed; + +enum reg_ext_bitmap { + REG_EXT_JAPAN_MIDBAND = 1, + REG_EXT_FCC_DFS_HT40 = 2, + REG_EXT_JAPAN_NONDFS_HT40 = 3, + REG_EXT_JAPAN_DFS_HT40 = 4 +}; + +struct ath9k_country_entry { + u16 countryCode; + u16 regDmnEnum; + u16 regDmn5G; + u16 regDmn2G; + u8 isMultidomain; + u8 iso[3]; +}; + +enum hal_eep_map { + EEP_MAP_DEFAULT = 0x0, + EEP_MAP_4KBITS, + EEP_MAP_MAX +}; + +#define ar5416_get_eep_ver(_ahp) \ + (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) +#define ar5416_get_eep_rev(_ahp) \ + (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF) +#define ar5416_get_ntxchains(_txchainmask) \ + (((_txchainmask >> 2) & 1) + \ + ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) + +#define ar5416_get_eep4k_ver(_ahp) \ + (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) +#define ar5416_get_eep4k_rev(_ahp) \ + (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) + +int ath9k_hw_set_txpower(struct ath_hal *ah, struct ath9k_channel *chan, + u16 cfgCtl, u8 twiceAntennaReduction, + u8 twiceMaxRegulatoryPower, u8 powerLimit); +void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan); +bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, + struct ath9k_channel *chan, int16_t *ratesArray, + u16 cfgCtl, u8 AntennaReduction, + u8 twiceMaxRegulatoryPower, u8 powerLimit); +bool ath9k_hw_set_power_cal_table(struct ath_hal *ah, + struct ath9k_channel *chan, + int16_t *pTxPowerIndexOffset); +bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, + struct ath9k_channel *chan); +u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, + struct ath9k_channel *chan); +u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, + enum ieee80211_band freq_band); +u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz); +u32 ath9k_hw_get_eeprom(struct ath_hal *ah, enum eeprom_param param); +int ath9k_hw_eeprom_attach(struct ath_hal *ah); + +#endif /* EEPROM_H */ -- cgit v1.2.3 From cbe61d8a41210600bc76b212edcd4dc0f55c014f Mon Sep 17 00:00:00 2001 From: Sujith Date: Mon, 9 Feb 2009 13:27:12 +0530 Subject: ath9k: Merge ath_hal and ath_hal_5416 structures Finally, merge these structures and have a single HW specific data structure. Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/ahb.c | 4 +- drivers/net/wireless/ath9k/ani.c | 232 ++++++------- drivers/net/wireless/ath9k/ani.h | 22 +- drivers/net/wireless/ath9k/ath9k.h | 6 +- drivers/net/wireless/ath9k/beacon.c | 12 +- drivers/net/wireless/ath9k/calib.c | 175 +++++----- drivers/net/wireless/ath9k/calib.h | 20 +- drivers/net/wireless/ath9k/debug.c | 2 +- drivers/net/wireless/ath9k/eeprom.c | 251 ++++++-------- drivers/net/wireless/ath9k/eeprom.h | 36 +- drivers/net/wireless/ath9k/hw.c | 675 +++++++++++++++++------------------- drivers/net/wireless/ath9k/hw.h | 134 ++++--- drivers/net/wireless/ath9k/mac.c | 144 ++++---- drivers/net/wireless/ath9k/mac.h | 64 ++-- drivers/net/wireless/ath9k/main.c | 22 +- drivers/net/wireless/ath9k/pci.c | 4 +- drivers/net/wireless/ath9k/phy.c | 194 +++++------ drivers/net/wireless/ath9k/phy.h | 14 +- drivers/net/wireless/ath9k/recv.c | 10 +- drivers/net/wireless/ath9k/regd.c | 18 +- drivers/net/wireless/ath9k/regd.h | 14 +- drivers/net/wireless/ath9k/xmit.c | 12 +- 22 files changed, 956 insertions(+), 1109 deletions(-) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/ahb.c b/drivers/net/wireless/ath9k/ahb.c index d254b357804d..391c9fd3b646 100644 --- a/drivers/net/wireless/ath9k/ahb.c +++ b/drivers/net/wireless/ath9k/ahb.c @@ -32,7 +32,7 @@ static void ath_ahb_cleanup(struct ath_softc *sc) iounmap(sc->mem); } -static bool ath_ahb_eeprom_read(struct ath_hal *ah, u32 off, u16 *data) +static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data) { struct ath_softc *sc = ah->ah_sc; struct platform_device *pdev = to_platform_device(sc->dev); @@ -65,7 +65,7 @@ static int ath_ahb_probe(struct platform_device *pdev) struct resource *res; int irq; int ret = 0; - struct ath_hal *ah; + struct ath_hw *ah; if (!pdev->dev.platform_data) { dev_err(&pdev->dev, "no platform data specified\n"); diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c index 9cebf0e78a76..6bd2d5766019 100644 --- a/drivers/net/wireless/ath9k/ani.c +++ b/drivers/net/wireless/ath9k/ani.c @@ -16,18 +16,17 @@ #include "ath9k.h" -static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, +static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; - for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { - if (ahp->ah_ani[i].c && - ahp->ah_ani[i].c->channel == chan->channel) + for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { + if (ah->ah_ani[i].c && + ah->ah_ani[i].c->channel == chan->channel) return i; - if (ahp->ah_ani[i].c == NULL) { - ahp->ah_ani[i].c = chan; + if (ah->ah_ani[i].c == NULL) { + ah->ah_ani[i].c = chan; return i; } } @@ -38,41 +37,40 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, return 0; } -static bool ath9k_hw_ani_control(struct ath_hal *ah, +static bool ath9k_hw_ani_control(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416AniState *aniState = ahp->ah_curani; + struct ar5416AniState *aniState = ah->ah_curani; - switch (cmd & ahp->ah_ani_function) { + switch (cmd & ah->ah_ani_function) { case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ u32 level = param; - if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) { + if (level >= ARRAY_SIZE(ah->ah_totalSizeDesired)) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "level out of range (%u > %u)\n", level, - (unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired)); + (unsigned)ARRAY_SIZE(ah->ah_totalSizeDesired)); return false; } REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_TOT_DES, - ahp->ah_totalSizeDesired[level]); + ah->ah_totalSizeDesired[level]); REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_LOW, - ahp->ah_coarseLow[level]); + ah->ah_coarseLow[level]); REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_HIGH, - ahp->ah_coarseHigh[level]); + ah->ah_coarseHigh[level]); REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR, - ahp->ah_firpwr[level]); + ah->ah_firpwr[level]); if (level > aniState->noiseImmunityLevel) - ahp->ah_stats.ast_ani_niup++; + ah->ah_stats.ast_ani_niup++; else if (level < aniState->noiseImmunityLevel) - ahp->ah_stats.ast_ani_nidown++; + ah->ah_stats.ast_ani_nidown++; aniState->noiseImmunityLevel = level; break; } @@ -126,9 +124,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, if (!on != aniState->ofdmWeakSigDetectOff) { if (on) - ahp->ah_stats.ast_ani_ofdmon++; + ah->ah_stats.ast_ani_ofdmon++; else - ahp->ah_stats.ast_ani_ofdmoff++; + ah->ah_stats.ast_ani_ofdmoff++; aniState->ofdmWeakSigDetectOff = !on; } break; @@ -142,9 +140,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, weakSigThrCck[high]); if (high != aniState->cckWeakSigThreshold) { if (high) - ahp->ah_stats.ast_ani_cckhigh++; + ah->ah_stats.ast_ani_cckhigh++; else - ahp->ah_stats.ast_ani_ccklow++; + ah->ah_stats.ast_ani_ccklow++; aniState->cckWeakSigThreshold = high; } break; @@ -164,9 +162,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, AR_PHY_FIND_SIG_FIRSTEP, firstep[level]); if (level > aniState->firstepLevel) - ahp->ah_stats.ast_ani_stepup++; + ah->ah_stats.ast_ani_stepup++; else if (level < aniState->firstepLevel) - ahp->ah_stats.ast_ani_stepdown++; + ah->ah_stats.ast_ani_stepdown++; aniState->firstepLevel = level; break; } @@ -187,9 +185,9 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, AR_PHY_TIMING5_CYCPWR_THR1, cycpwrThr1[level]); if (level > aniState->spurImmunityLevel) - ahp->ah_stats.ast_ani_spurup++; + ah->ah_stats.ast_ani_spurup++; else if (level < aniState->spurImmunityLevel) - ahp->ah_stats.ast_ani_spurdown++; + ah->ah_stats.ast_ani_spurdown++; aniState->spurImmunityLevel = level; break; } @@ -220,7 +218,7 @@ static bool ath9k_hw_ani_control(struct ath_hal *ah, return true; } -static void ath9k_hw_update_mibstats(struct ath_hal *ah, +static void ath9k_hw_update_mibstats(struct ath_hw *ah, struct ath9k_mib_stats *stats) { stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL); @@ -230,18 +228,17 @@ static void ath9k_hw_update_mibstats(struct ath_hal *ah, stats->beacons += REG_READ(ah, AR_BEACON_CNT); } -static void ath9k_ani_restart(struct ath_hal *ah) +static void ath9k_ani_restart(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; if (!DO_ANI(ah)) return; - aniState = ahp->ah_curani; + aniState = ah->ah_curani; aniState->listenTime = 0; - if (ahp->ah_hasHwPhyCounters) { + if (ah->ah_hasHwPhyCounters) { if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { aniState->ofdmPhyErrBase = 0; DPRINTF(ah->ah_sc, ATH_DBG_ANI, @@ -267,15 +264,14 @@ static void ath9k_ani_restart(struct ath_hal *ah) REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); - ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); + ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); } aniState->ofdmPhyErrCount = 0; aniState->cckPhyErrCount = 0; } -static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) +static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; struct ar5416AniState *aniState; int32_t rssi; @@ -283,7 +279,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) if (!DO_ANI(ah)) return; - aniState = ahp->ah_curani; + aniState = ah->ah_curani; if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, @@ -306,7 +302,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) } return; } - rssi = BEACON_RSSI(ahp); + rssi = BEACON_RSSI(ah); if (rssi > aniState->rssiThrHigh) { if (!aniState->ofdmWeakSigDetectOff) { if (ath9k_hw_ani_control(ah, @@ -345,9 +341,8 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah) } } -static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) +static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; struct ar5416AniState *aniState; int32_t rssi; @@ -355,7 +350,7 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) if (!DO_ANI(ah)) return; - aniState = ahp->ah_curani; + aniState = ah->ah_curani; if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, aniState->noiseImmunityLevel + 1)) { @@ -369,7 +364,7 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) } return; } - rssi = BEACON_RSSI(ahp); + rssi = BEACON_RSSI(ah); if (rssi > aniState->rssiThrLow) { if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, @@ -383,13 +378,12 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah) } } -static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) +static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; int32_t rssi; - aniState = ahp->ah_curani; + aniState = ah->ah_curani; if (ah->ah_opmode == NL80211_IFTYPE_AP) { if (aniState->firstepLevel > 0) { @@ -398,7 +392,7 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) return; } } else { - rssi = BEACON_RSSI(ahp); + rssi = BEACON_RSSI(ah); if (rssi > aniState->rssiThrHigh) { /* XXX: Handle me */ } else if (rssi > aniState->rssiThrLow) { @@ -437,9 +431,8 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah) } } -static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) +static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; u32 txFrameCount, rxFrameCount, cycleCount; int32_t listenTime; @@ -448,11 +441,11 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) rxFrameCount = REG_READ(ah, AR_RFCNT); cycleCount = REG_READ(ah, AR_CCCNT); - aniState = ahp->ah_curani; + aniState = ah->ah_curani; if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { listenTime = 0; - ahp->ah_stats.ast_ani_lzero++; + ah->ah_stats.ast_ani_lzero++; } else { int32_t ccdelta = cycleCount - aniState->cycleCount; int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; @@ -466,9 +459,8 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah) return listenTime; } -void ath9k_ani_reset(struct ath_hal *ah) +void ath9k_ani_reset(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; struct ath9k_channel *chan = ah->ah_curchan; int index; @@ -477,14 +469,14 @@ void ath9k_ani_reset(struct ath_hal *ah) return; index = ath9k_hw_get_ani_channel_idx(ah, chan); - aniState = &ahp->ah_ani[index]; - ahp->ah_curani = aniState; + aniState = &ah->ah_ani[index]; + ah->ah_curani = aniState; if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION && ah->ah_opmode != NL80211_IFTYPE_ADHOC) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Reset ANI state opmode %u\n", ah->ah_opmode); - ahp->ah_stats.ast_ani_reset++; + ah->ah_stats.ast_ani_reset++; ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); @@ -498,13 +490,13 @@ void ath9k_ani_reset(struct ath_hal *ah) ATH9K_RX_FILTER_PHYERR); if (ah->ah_opmode == NL80211_IFTYPE_AP) { - ahp->ah_curani->ofdmTrigHigh = + ah->ah_curani->ofdmTrigHigh = ah->ah_config.ofdm_trig_high; - ahp->ah_curani->ofdmTrigLow = + ah->ah_curani->ofdmTrigLow = ah->ah_config.ofdm_trig_low; - ahp->ah_curani->cckTrigHigh = + ah->ah_curani->cckTrigHigh = ah->ah_config.cck_trig_high; - ahp->ah_curani->cckTrigLow = + ah->ah_curani->cckTrigLow = ah->ah_config.cck_trig_low; } ath9k_ani_restart(ah); @@ -526,7 +518,7 @@ void ath9k_ani_reset(struct ath_hal *ah) if (aniState->firstepLevel != 0) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel); - if (ahp->ah_hasHwPhyCounters) { + if (ah->ah_hasHwPhyCounters) { ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & ~ATH9K_RX_FILTER_PHYERR); ath9k_ani_restart(ah); @@ -540,34 +532,33 @@ void ath9k_ani_reset(struct ath_hal *ah) } } -void ath9k_hw_ani_monitor(struct ath_hal *ah, +void ath9k_hw_ani_monitor(struct ath_hw *ah, const struct ath9k_node_stats *stats, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416AniState *aniState; int32_t listenTime; if (!DO_ANI(ah)) return; - aniState = ahp->ah_curani; - ahp->ah_stats.ast_nodestats = *stats; + aniState = ah->ah_curani; + ah->ah_stats.ast_nodestats = *stats; listenTime = ath9k_hw_ani_get_listen_time(ah); if (listenTime < 0) { - ahp->ah_stats.ast_ani_lneg++; + ah->ah_stats.ast_ani_lneg++; ath9k_ani_restart(ah); return; } aniState->listenTime += listenTime; - if (ahp->ah_hasHwPhyCounters) { + if (ah->ah_hasHwPhyCounters) { u32 phyCnt1, phyCnt2; u32 ofdmPhyErrCnt, cckPhyErrCnt; - ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); + ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); @@ -600,24 +591,24 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah, } ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; - ahp->ah_stats.ast_ani_ofdmerrs += + ah->ah_stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount; aniState->ofdmPhyErrCount = ofdmPhyErrCnt; cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; - ahp->ah_stats.ast_ani_cckerrs += + ah->ah_stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount; aniState->cckPhyErrCount = cckPhyErrCnt; } - if (aniState->listenTime > 5 * ahp->ah_aniPeriod) { + if (aniState->listenTime > 5 * ah->ah_aniPeriod) { if (aniState->ofdmPhyErrCount <= aniState->listenTime * aniState->ofdmTrigLow / 1000 && aniState->cckPhyErrCount <= aniState->listenTime * aniState->cckTrigLow / 1000) ath9k_hw_ani_lower_immunity(ah); ath9k_ani_restart(ah); - } else if (aniState->listenTime > ahp->ah_aniPeriod) { + } else if (aniState->listenTime > ah->ah_aniPeriod) { if (aniState->ofdmPhyErrCount > aniState->listenTime * aniState->ofdmTrigHigh / 1000) { ath9k_hw_ani_ofdm_err_trigger(ah); @@ -631,20 +622,16 @@ void ath9k_hw_ani_monitor(struct ath_hal *ah, } } -bool ath9k_hw_phycounters(struct ath_hal *ah) +bool ath9k_hw_phycounters(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ahp->ah_hasHwPhyCounters ? true : false; + return ah->ah_hasHwPhyCounters ? true : false; } -void ath9k_enable_mib_counters(struct ath_hal *ah) +void ath9k_enable_mib_counters(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n"); - ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); + ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); REG_WRITE(ah, AR_FILT_OFDM, 0); REG_WRITE(ah, AR_FILT_CCK, 0); @@ -655,21 +642,19 @@ void ath9k_enable_mib_counters(struct ath_hal *ah) REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); } -void ath9k_hw_disable_mib_counters(struct ath_hal *ah) +void ath9k_hw_disable_mib_counters(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n"); REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC); - ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); + ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); REG_WRITE(ah, AR_FILT_OFDM, 0); REG_WRITE(ah, AR_FILT_CCK, 0); } -u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, +u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt, u32 *rxf_pcnt, u32 *txf_pcnt) @@ -714,10 +699,9 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, * any of the MIB counters overflow/trigger so don't assume we're * here because a PHY error counter triggered. */ -void ath9k_hw_procmibevent(struct ath_hal *ah, +void ath9k_hw_procmibevent(struct ath_hw *ah, const struct ath9k_node_stats *stats) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 phyCnt1, phyCnt2; /* Reset these counters regardless */ @@ -727,8 +711,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah, REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR); /* Clear the mib counters and save them in the stats */ - ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats); - ahp->ah_stats.ast_nodestats = *stats; + ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); + ah->ah_stats.ast_nodestats = *stats; if (!DO_ANI(ah)) return; @@ -738,17 +722,17 @@ void ath9k_hw_procmibevent(struct ath_hal *ah, phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { - struct ar5416AniState *aniState = ahp->ah_curani; + struct ar5416AniState *aniState = ah->ah_curani; u32 ofdmPhyErrCnt, cckPhyErrCnt; /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; - ahp->ah_stats.ast_ani_ofdmerrs += + ah->ah_stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount; aniState->ofdmPhyErrCount = ofdmPhyErrCnt; cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; - ahp->ah_stats.ast_ani_cckerrs += + ah->ah_stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount; aniState->cckPhyErrCount = cckPhyErrCnt; @@ -767,9 +751,8 @@ void ath9k_hw_procmibevent(struct ath_hal *ah, } } -void ath9k_hw_ani_setup(struct ath_hal *ah) +void ath9k_hw_ani_setup(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; const int totalSizeDesired[] = { -55, -55, -55, -55, -62 }; @@ -778,66 +761,63 @@ void ath9k_hw_ani_setup(struct ath_hal *ah) const int firpwr[] = { -78, -78, -78, -78, -80 }; for (i = 0; i < 5; i++) { - ahp->ah_totalSizeDesired[i] = totalSizeDesired[i]; - ahp->ah_coarseHigh[i] = coarseHigh[i]; - ahp->ah_coarseLow[i] = coarseLow[i]; - ahp->ah_firpwr[i] = firpwr[i]; + ah->ah_totalSizeDesired[i] = totalSizeDesired[i]; + ah->ah_coarseHigh[i] = coarseHigh[i]; + ah->ah_coarseLow[i] = coarseLow[i]; + ah->ah_firpwr[i] = firpwr[i]; } } -void ath9k_hw_ani_attach(struct ath_hal *ah) +void ath9k_hw_ani_attach(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n"); - ahp->ah_hasHwPhyCounters = 1; - - memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani)); - for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) { - ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; - ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; - ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; - ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; - ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; - ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; - ahp->ah_ani[i].ofdmWeakSigDetectOff = + ah->ah_hasHwPhyCounters = 1; + + memset(ah->ah_ani, 0, sizeof(ah->ah_ani)); + for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { + ah->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; + ah->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; + ah->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; + ah->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; + ah->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; + ah->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; + ah->ah_ani[i].ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; - ahp->ah_ani[i].cckWeakSigThreshold = + ah->ah_ani[i].cckWeakSigThreshold = ATH9K_ANI_CCK_WEAK_SIG_THR; - ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; - ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; - if (ahp->ah_hasHwPhyCounters) { - ahp->ah_ani[i].ofdmPhyErrBase = + ah->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; + ah->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; + if (ah->ah_hasHwPhyCounters) { + ah->ah_ani[i].ofdmPhyErrBase = AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; - ahp->ah_ani[i].cckPhyErrBase = + ah->ah_ani[i].cckPhyErrBase = AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; } } - if (ahp->ah_hasHwPhyCounters) { + if (ah->ah_hasHwPhyCounters) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting OfdmErrBase = 0x%08x\n", - ahp->ah_ani[0].ofdmPhyErrBase); + ah->ah_ani[0].ofdmPhyErrBase); DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", - ahp->ah_ani[0].cckPhyErrBase); + ah->ah_ani[0].cckPhyErrBase); - REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase); - REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase); + REG_WRITE(ah, AR_PHY_ERR_1, ah->ah_ani[0].ofdmPhyErrBase); + REG_WRITE(ah, AR_PHY_ERR_2, ah->ah_ani[0].cckPhyErrBase); ath9k_enable_mib_counters(ah); } - ahp->ah_aniPeriod = ATH9K_ANI_PERIOD; + ah->ah_aniPeriod = ATH9K_ANI_PERIOD; if (ah->ah_config.enable_ani) - ahp->ah_procPhyErr |= HAL_PROCESS_ANI; + ah->ah_procPhyErr |= HAL_PROCESS_ANI; } -void ath9k_hw_ani_detach(struct ath_hal *ah) +void ath9k_hw_ani_detach(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n"); - if (ahp->ah_hasHwPhyCounters) { + if (ah->ah_hasHwPhyCounters) { ath9k_hw_disable_mib_counters(ah); REG_WRITE(ah, AR_PHY_ERR_1, 0); REG_WRITE(ah, AR_PHY_ERR_2, 0); diff --git a/drivers/net/wireless/ath9k/ani.h b/drivers/net/wireless/ath9k/ani.h index 78880e591052..7e9ca9519799 100644 --- a/drivers/net/wireless/ath9k/ani.h +++ b/drivers/net/wireless/ath9k/ani.h @@ -20,7 +20,7 @@ #define HAL_PROCESS_ANI 0x00000001 #define ATH9K_RSSI_EP_MULTIPLIER (1<<7) -#define DO_ANI(ah) ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI)) +#define DO_ANI(ah) (((ah)->ah_procPhyErr & HAL_PROCESS_ANI)) #define HAL_EP_RND(x, mul) \ ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) @@ -120,19 +120,19 @@ struct ar5416Stats { }; #define ah_mibStats ah_stats.ast_mibstats -void ath9k_ani_reset(struct ath_hal *ah); -void ath9k_hw_ani_monitor(struct ath_hal *ah, +void ath9k_ani_reset(struct ath_hw *ah); +void ath9k_hw_ani_monitor(struct ath_hw *ah, const struct ath9k_node_stats *stats, struct ath9k_channel *chan); -bool ath9k_hw_phycounters(struct ath_hal *ah); -void ath9k_enable_mib_counters(struct ath_hal *ah); -void ath9k_hw_disable_mib_counters(struct ath_hal *ah); -u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, u32 *rxc_pcnt, +bool ath9k_hw_phycounters(struct ath_hw *ah); +void ath9k_enable_mib_counters(struct ath_hw *ah); +void ath9k_hw_disable_mib_counters(struct ath_hw *ah); +u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt, u32 *rxf_pcnt, u32 *txf_pcnt); -void ath9k_hw_procmibevent(struct ath_hal *ah, +void ath9k_hw_procmibevent(struct ath_hw *ah, const struct ath9k_node_stats *stats); -void ath9k_hw_ani_setup(struct ath_hal *ah); -void ath9k_hw_ani_attach(struct ath_hal *ah); -void ath9k_hw_ani_detach(struct ath_hal *ah); +void ath9k_hw_ani_setup(struct ath_hw *ah); +void ath9k_hw_ani_attach(struct ath_hw *ah); +void ath9k_hw_ani_detach(struct ath_hw *ah); #endif /* ANI_H */ diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index 03e4d0bf1590..91140b7214b1 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h @@ -455,7 +455,7 @@ struct ath_beacon { void ath9k_beacon_tasklet(unsigned long data); void ath_beacon_config(struct ath_softc *sc, int if_id); -int ath_beaconq_setup(struct ath_hal *ah); +int ath_beaconq_setup(struct ath_hw *ah); int ath_beacon_alloc(struct ath_softc *sc, int if_id); void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); void ath_beacon_sync(struct ath_softc *sc, int if_id); @@ -565,7 +565,7 @@ struct ath_rfkill { struct ath_bus_ops { void (*read_cachesize)(struct ath_softc *sc, int *csz); void (*cleanup)(struct ath_softc *sc); - bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data); + bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data); }; struct ath_softc { @@ -573,7 +573,7 @@ struct ath_softc { struct device *dev; struct tasklet_struct intr_tq; struct tasklet_struct bcon_tasklet; - struct ath_hal *sc_ah; + struct ath_hw *sc_ah; void __iomem *mem; int irq; spinlock_t sc_resetlock; diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c index 139bba738c5f..19ec4e8791b4 100644 --- a/drivers/net/wireless/ath9k/beacon.c +++ b/drivers/net/wireless/ath9k/beacon.c @@ -23,7 +23,7 @@ */ static int ath_beaconq_config(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath9k_tx_queue_info qi; ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); @@ -66,7 +66,7 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp, struct ath_buf *bf) { struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_desc *ds; struct ath9k_11n_rate_series series[4]; struct ath_rate_table *rt; @@ -248,7 +248,7 @@ static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) { struct ieee80211_vif *vif; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_buf *bf; struct ath_vif *avp; struct sk_buff *skb; @@ -276,7 +276,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc); } -int ath_beaconq_setup(struct ath_hal *ah) +int ath_beaconq_setup(struct ath_hw *ah) { struct ath9k_tx_queue_info qi; @@ -444,7 +444,7 @@ void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp) void ath9k_beacon_tasklet(unsigned long data) { struct ath_softc *sc = (struct ath_softc *)data; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_buf *bf = NULL; int slot, if_id; u32 bfaddr; @@ -619,7 +619,7 @@ void ath9k_beacon_tasklet(unsigned long data) void ath_beacon_config(struct ath_softc *sc, int if_id) { struct ieee80211_vif *vif; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_beacon_config conf; struct ath_vif *avp; enum nl80211_iftype opmode; diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c index 016302c53cc5..8c44d5a439e7 100644 --- a/drivers/net/wireless/ath9k/calib.c +++ b/drivers/net/wireless/ath9k/calib.c @@ -23,7 +23,7 @@ * is incorrect and we should use the static NF value. Later we can try to * find out why they are reporting these values */ -static bool ath9k_hw_nf_in_range(struct ath_hal *ah, s16 nf) +static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf) { if (nf > ATH9K_NF_TOO_LOW) { DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, @@ -86,7 +86,7 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h, return; } -static void ath9k_hw_do_getnf(struct ath_hal *ah, +static void ath9k_hw_do_getnf(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]) { int16_t nf; @@ -166,7 +166,7 @@ static void ath9k_hw_do_getnf(struct ath_hal *ah, } } -static bool getNoiseFloorThresh(struct ath_hal *ah, +static bool getNoiseFloorThresh(struct ath_hw *ah, enum ieee80211_band band, int16_t *nft) { @@ -185,7 +185,7 @@ static bool getNoiseFloorThresh(struct ath_hal *ah, return true; } -static void ath9k_hw_setup_calibration(struct ath_hal *ah, +static void ath9k_hw_setup_calibration(struct ath_hw *ah, struct hal_cal_list *currCal) { REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), @@ -219,10 +219,9 @@ static void ath9k_hw_setup_calibration(struct ath_hal *ah, AR_PHY_TIMING_CTRL4_DO_CAL); } -static void ath9k_hw_reset_calibration(struct ath_hal *ah, +static void ath9k_hw_reset_calibration(struct ath_hw *ah, struct hal_cal_list *currCal) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; ath9k_hw_setup_calibration(ah, currCal); @@ -230,23 +229,21 @@ static void ath9k_hw_reset_calibration(struct ath_hal *ah, currCal->calState = CAL_RUNNING; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ahp->ah_Meas0.sign[i] = 0; - ahp->ah_Meas1.sign[i] = 0; - ahp->ah_Meas2.sign[i] = 0; - ahp->ah_Meas3.sign[i] = 0; + ah->ah_Meas0.sign[i] = 0; + ah->ah_Meas1.sign[i] = 0; + ah->ah_Meas2.sign[i] = 0; + ah->ah_Meas3.sign[i] = 0; } - ahp->ah_CalSamples = 0; + ah->ah_CalSamples = 0; } -static void ath9k_hw_per_calibration(struct ath_hal *ah, +static void ath9k_hw_per_calibration(struct ath_hw *ah, struct ath9k_channel *ichan, u8 rxchainmask, struct hal_cal_list *currCal, bool *isCalDone) { - struct ath_hal_5416 *ahp = AH5416(ah); - *isCalDone = false; if (currCal->calState == CAL_RUNNING) { @@ -254,9 +251,9 @@ static void ath9k_hw_per_calibration(struct ath_hal *ah, AR_PHY_TIMING_CTRL4_DO_CAL)) { currCal->calData->calCollect(ah); - ahp->ah_CalSamples++; + ah->ah_CalSamples++; - if (ahp->ah_CalSamples >= currCal->calData->calNumSamples) { + if (ah->ah_CalSamples >= currCal->calData->calNumSamples) { int i, numChains = 0; for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (rxchainmask & (1 << i)) @@ -277,13 +274,12 @@ static void ath9k_hw_per_calibration(struct ath_hal *ah, } /* Assumes you are talking about the currently configured channel */ -static bool ath9k_hw_iscal_supported(struct ath_hal *ah, +static bool ath9k_hw_iscal_supported(struct ath_hw *ah, enum hal_cal_types calType) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - switch (calType & ahp->ah_suppCals) { + switch (calType & ah->ah_suppCals) { case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ return true; case ADC_GAIN_CAL: @@ -296,90 +292,86 @@ static bool ath9k_hw_iscal_supported(struct ath_hal *ah, return false; } -static void ath9k_hw_iqcal_collect(struct ath_hal *ah) +static void ath9k_hw_iqcal_collect(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ahp->ah_totalPowerMeasI[i] += + ah->ah_totalPowerMeasI[i] += REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ahp->ah_totalPowerMeasQ[i] += + ah->ah_totalPowerMeasQ[i] += REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ahp->ah_totalIqCorrMeas[i] += + ah->ah_totalIqCorrMeas[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", - ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i], - ahp->ah_totalPowerMeasQ[i], - ahp->ah_totalIqCorrMeas[i]); + ah->ah_CalSamples, i, ah->ah_totalPowerMeasI[i], + ah->ah_totalPowerMeasQ[i], + ah->ah_totalIqCorrMeas[i]); } } -static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah) +static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ahp->ah_totalAdcIOddPhase[i] += + ah->ah_totalAdcIOddPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ahp->ah_totalAdcIEvenPhase[i] += + ah->ah_totalAdcIEvenPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ahp->ah_totalAdcQOddPhase[i] += + ah->ah_totalAdcQOddPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); - ahp->ah_totalAdcQEvenPhase[i] += + ah->ah_totalAdcQEvenPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "oddq=0x%08x; evenq=0x%08x;\n", - ahp->ah_CalSamples, i, - ahp->ah_totalAdcIOddPhase[i], - ahp->ah_totalAdcIEvenPhase[i], - ahp->ah_totalAdcQOddPhase[i], - ahp->ah_totalAdcQEvenPhase[i]); + ah->ah_CalSamples, i, + ah->ah_totalAdcIOddPhase[i], + ah->ah_totalAdcIEvenPhase[i], + ah->ah_totalAdcQOddPhase[i], + ah->ah_totalAdcQEvenPhase[i]); } } -static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah) +static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ahp->ah_totalAdcDcOffsetIOddPhase[i] += + ah->ah_totalAdcDcOffsetIOddPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ahp->ah_totalAdcDcOffsetIEvenPhase[i] += + ah->ah_totalAdcDcOffsetIEvenPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ahp->ah_totalAdcDcOffsetQOddPhase[i] += + ah->ah_totalAdcDcOffsetQOddPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); - ahp->ah_totalAdcDcOffsetQEvenPhase[i] += + ah->ah_totalAdcDcOffsetQEvenPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "oddq=0x%08x; evenq=0x%08x;\n", - ahp->ah_CalSamples, i, - ahp->ah_totalAdcDcOffsetIOddPhase[i], - ahp->ah_totalAdcDcOffsetIEvenPhase[i], - ahp->ah_totalAdcDcOffsetQOddPhase[i], - ahp->ah_totalAdcDcOffsetQEvenPhase[i]); + ah->ah_CalSamples, i, + ah->ah_totalAdcDcOffsetIOddPhase[i], + ah->ah_totalAdcDcOffsetIEvenPhase[i], + ah->ah_totalAdcDcOffsetQOddPhase[i], + ah->ah_totalAdcDcOffsetQEvenPhase[i]); } } -static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) +static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 powerMeasQ, powerMeasI, iqCorrMeas; u32 qCoffDenom, iCoffDenom; int32_t qCoff, iCoff; int iqCorrNeg, i; for (i = 0; i < numChains; i++) { - powerMeasI = ahp->ah_totalPowerMeasI[i]; - powerMeasQ = ahp->ah_totalPowerMeasQ[i]; - iqCorrMeas = ahp->ah_totalIqCorrMeas[i]; + powerMeasI = ah->ah_totalPowerMeasI[i]; + powerMeasQ = ah->ah_totalPowerMeasQ[i]; + iqCorrMeas = ah->ah_totalIqCorrMeas[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting IQ Cal and Correction for Chain %d\n", @@ -387,7 +379,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Orignal: Chn %diq_corr_meas = 0x%08x\n", - i, ahp->ah_totalIqCorrMeas[i]); + i, ah->ah_totalIqCorrMeas[i]); iqCorrNeg = 0; @@ -445,17 +437,16 @@ static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u8 numChains) AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); } -static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains) +static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset; u32 qGainMismatch, iGainMismatch, val, i; for (i = 0; i < numChains; i++) { - iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i]; - iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i]; - qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i]; - qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i]; + iOddMeasOffset = ah->ah_totalAdcIOddPhase[i]; + iEvenMeasOffset = ah->ah_totalAdcIEvenPhase[i]; + qOddMeasOffset = ah->ah_totalAdcQOddPhase[i]; + qEvenMeasOffset = ah->ah_totalAdcQEvenPhase[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting ADC Gain Cal for Chain %d\n", i); @@ -503,21 +494,20 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u8 numChains) AR_PHY_NEW_ADC_GAIN_CORR_ENABLE); } -static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains) +static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 iOddMeasOffset, iEvenMeasOffset, val, i; int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; const struct hal_percal_data *calData = - ahp->ah_cal_list_curr->calData; + ah->ah_cal_list_curr->calData; u32 numSamples = (1 << (calData->calCountMax + 5)) * calData->calNumSamples; for (i = 0; i < numChains; i++) { - iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i]; - iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i]; - qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i]; - qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i]; + iOddMeasOffset = ah->ah_totalAdcDcOffsetIOddPhase[i]; + iEvenMeasOffset = ah->ah_totalAdcDcOffsetIEvenPhase[i]; + qOddMeasOffset = ah->ah_totalAdcDcOffsetQOddPhase[i]; + qEvenMeasOffset = ah->ah_totalAdcDcOffsetQEvenPhase[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting ADC DC Offset Cal for Chain %d\n", i); @@ -562,11 +552,10 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u8 numChains) } /* This is done for the currently configured channel */ -bool ath9k_hw_reset_calvalid(struct ath_hal *ah) +bool ath9k_hw_reset_calvalid(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - struct hal_cal_list *currCal = ahp->ah_cal_list_curr; + struct hal_cal_list *currCal = ah->ah_cal_list_curr; if (!ah->ah_curchan) return true; @@ -597,7 +586,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hal *ah) return false; } -void ath9k_hw_start_nfcal(struct ath_hal *ah) +void ath9k_hw_start_nfcal(struct ath_hw *ah) { REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); @@ -606,7 +595,7 @@ void ath9k_hw_start_nfcal(struct ath_hal *ah) REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); } -void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan) +void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) { struct ath9k_nfcal_hist *h; int i, j; @@ -662,7 +651,7 @@ void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan) } } -int16_t ath9k_hw_getnf(struct ath_hal *ah, +int16_t ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan) { int16_t nf, nfThresh; @@ -698,7 +687,7 @@ int16_t ath9k_hw_getnf(struct ath_hal *ah, return chan->rawNoiseFloor; } -void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah) +void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah) { int i, j; @@ -712,10 +701,9 @@ void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah) AR_PHY_CCA_MAX_GOOD_VALUE; } } - return; } -s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan) +s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan) { s16 nf; @@ -730,12 +718,11 @@ s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan) return nf; } -bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, +bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, bool longcal, bool *isCalDone) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct hal_cal_list *currCal = ahp->ah_cal_list_curr; + struct hal_cal_list *currCal = ah->ah_cal_list_curr; *isCalDone = true; @@ -745,7 +732,7 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, isCalDone); if (*isCalDone) { - ahp->ah_cal_list_curr = currCal = currCal->calNext; + ah->ah_cal_list_curr = currCal = currCal->calNext; if (currCal->calState == CAL_WAITING) { *isCalDone = false; @@ -766,7 +753,7 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, return true; } -static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah) +static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah) { u32 regVal; @@ -861,11 +848,9 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah) } -bool ath9k_hw_init_cal(struct ath_hal *ah, +bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - REG_WRITE(ah, AR_PHY_AGC_CONTROL, REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); @@ -884,32 +869,32 @@ bool ath9k_hw_init_cal(struct ath_hal *ah, REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF); - ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL; + ah->ah_cal_list = ah->ah_cal_list_last = ah->ah_cal_list_curr = NULL; if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { - INIT_CAL(&ahp->ah_adcGainCalData); - INSERT_CAL(ahp, &ahp->ah_adcGainCalData); + INIT_CAL(&ah->ah_adcGainCalData); + INSERT_CAL(ah, &ah->ah_adcGainCalData); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling ADC Gain Calibration.\n"); } if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { - INIT_CAL(&ahp->ah_adcDcCalData); - INSERT_CAL(ahp, &ahp->ah_adcDcCalData); + INIT_CAL(&ah->ah_adcDcCalData); + INSERT_CAL(ah, &ah->ah_adcDcCalData); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling ADC DC Calibration.\n"); } if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { - INIT_CAL(&ahp->ah_iqCalData); - INSERT_CAL(ahp, &ahp->ah_iqCalData); + INIT_CAL(&ah->ah_iqCalData); + INSERT_CAL(ah, &ah->ah_iqCalData); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling IQ Calibration.\n"); } - ahp->ah_cal_list_curr = ahp->ah_cal_list; + ah->ah_cal_list_curr = ah->ah_cal_list; - if (ahp->ah_cal_list_curr) - ath9k_hw_reset_calibration(ah, ahp->ah_cal_list_curr); + if (ah->ah_cal_list_curr) + ath9k_hw_reset_calibration(ah, ah->ah_cal_list_curr); } chan->CalValid = 0; diff --git a/drivers/net/wireless/ath9k/calib.h b/drivers/net/wireless/ath9k/calib.h index ac7d88fa8268..e2c614098545 100644 --- a/drivers/net/wireless/ath9k/calib.h +++ b/drivers/net/wireless/ath9k/calib.h @@ -91,8 +91,8 @@ struct hal_percal_data { enum hal_cal_types calType; u32 calNumSamples; u32 calCountMax; - void (*calCollect) (struct ath_hal *); - void (*calPostProc) (struct ath_hal *, u8); + void (*calCollect) (struct ath_hw *); + void (*calPostProc) (struct ath_hw *, u8); }; struct hal_cal_list { @@ -108,17 +108,17 @@ struct ath9k_nfcal_hist { u8 invalidNFcount; }; -bool ath9k_hw_reset_calvalid(struct ath_hal *ah); -void ath9k_hw_start_nfcal(struct ath_hal *ah); -void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan); -int16_t ath9k_hw_getnf(struct ath_hal *ah, +bool ath9k_hw_reset_calvalid(struct ath_hw *ah); +void ath9k_hw_start_nfcal(struct ath_hw *ah); +void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan); +int16_t ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan); -void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah); -s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan); -bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, +void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah); +s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan); +bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, bool longcal, bool *isCalDone); -bool ath9k_hw_init_cal(struct ath_hal *ah, +bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan); #endif /* CALIB_H */ diff --git a/drivers/net/wireless/ath9k/debug.c b/drivers/net/wireless/ath9k/debug.c index daca5ce91452..800ad5926b6f 100644 --- a/drivers/net/wireless/ath9k/debug.c +++ b/drivers/net/wireless/ath9k/debug.c @@ -44,7 +44,7 @@ static ssize_t read_file_dma(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) { struct ath_softc *sc = file->private_data; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; char buf[1024]; unsigned int len = 0; u32 val[ATH9K_NUM_DMA_DEBUG_REGS]; diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index d58d8a330b64..94e79938b93a 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -16,7 +16,7 @@ #include "ath9k.h" -static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah, +static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, u32 shift, u32 val) { @@ -88,18 +88,17 @@ static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, return false; } -static inline bool ath9k_hw_nvram_read(struct ath_hal *ah, u32 off, u16 *data) +static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data) { struct ath_softc *sc = ah->ah_sc; return sc->bus_ops->eeprom_read(ah, off, data); } -static bool ath9k_hw_fill_4k_eeprom(struct ath_hal *ah) +static bool ath9k_hw_fill_4k_eeprom(struct ath_hw *ah) { #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; u16 *eep_data; int addr, eep_start_loc = 0; @@ -124,11 +123,10 @@ static bool ath9k_hw_fill_4k_eeprom(struct ath_hal *ah) #undef SIZE_EEPROM_4K } -static bool ath9k_hw_fill_def_eeprom(struct ath_hal *ah) +static bool ath9k_hw_fill_def_eeprom(struct ath_hw *ah) { #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; u16 *eep_data; int addr, ar5416_eep_start_loc = 0x100; @@ -147,23 +145,20 @@ static bool ath9k_hw_fill_def_eeprom(struct ath_hal *ah) #undef SIZE_EEPROM_DEF } -static bool (*ath9k_fill_eeprom[]) (struct ath_hal *) = { +static bool (*ath9k_fill_eeprom[]) (struct ath_hw *) = { ath9k_hw_fill_def_eeprom, ath9k_hw_fill_4k_eeprom }; -static inline bool ath9k_hw_fill_eeprom(struct ath_hal *ah) +static inline bool ath9k_hw_fill_eeprom(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_fill_eeprom[ahp->ah_eep_map](ah); + return ath9k_fill_eeprom[ah->ah_eep_map](ah); } -static int ath9k_hw_check_def_eeprom(struct ath_hal *ah) +static int ath9k_hw_check_def_eeprom(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416_eeprom_def *eep = - (struct ar5416_eeprom_def *) &ahp->ah_eeprom.def; + (struct ar5416_eeprom_def *) &ah->ah_eeprom.def; u16 *eepdata, temp, magic, magic2; u32 sum = 0, el; bool need_swap = false; @@ -187,7 +182,7 @@ static int ath9k_hw_check_def_eeprom(struct ath_hal *ah) if (magic2 == AR5416_EEPROM_MAGIC) { size = sizeof(struct ar5416_eeprom_def); need_swap = true; - eepdata = (u16 *) (&ahp->ah_eeprom); + eepdata = (u16 *) (&ah->ah_eeprom); for (addr = 0; addr < size / sizeof(u16); addr++) { temp = swab16(*eepdata); @@ -214,16 +209,16 @@ static int ath9k_hw_check_def_eeprom(struct ath_hal *ah) need_swap ? "True" : "False"); if (need_swap) - el = swab16(ahp->ah_eeprom.def.baseEepHeader.length); + el = swab16(ah->ah_eeprom.def.baseEepHeader.length); else - el = ahp->ah_eeprom.def.baseEepHeader.length; + el = ah->ah_eeprom.def.baseEepHeader.length; if (el > sizeof(struct ar5416_eeprom_def)) el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); else el = el / sizeof(u16); - eepdata = (u16 *)(&ahp->ah_eeprom); + eepdata = (u16 *)(&ah->ah_eeprom); for (i = 0; i < el; i++) sum ^= *eepdata++; @@ -277,23 +272,22 @@ static int ath9k_hw_check_def_eeprom(struct ath_hal *ah) } } - if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER || - ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) { + if (sum != 0xffff || ar5416_get_eep_ver(ah) != AR5416_EEP_VER || + ar5416_get_eep_rev(ah) < AR5416_EEP_NO_BACK_VER) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", - sum, ar5416_get_eep_ver(ahp)); + sum, ar5416_get_eep_ver(ah)); return -EINVAL; } return 0; } -static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) +static int ath9k_hw_check_4k_eeprom(struct ath_hw *ah) { #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) - struct ath_hal_5416 *ahp = AH5416(ah); struct ar5416_eeprom_4k *eep = - (struct ar5416_eeprom_4k *) &ahp->ah_eeprom.map4k; + (struct ar5416_eeprom_4k *) &ah->ah_eeprom.map4k; u16 *eepdata, temp, magic, magic2; u32 sum = 0, el; bool need_swap = false; @@ -317,7 +311,7 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) if (magic2 == AR5416_EEPROM_MAGIC) { need_swap = true; - eepdata = (u16 *) (&ahp->ah_eeprom); + eepdata = (u16 *) (&ah->ah_eeprom); for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { temp = swab16(*eepdata); @@ -344,16 +338,16 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) need_swap ? "True" : "False"); if (need_swap) - el = swab16(ahp->ah_eeprom.map4k.baseEepHeader.length); + el = swab16(ah->ah_eeprom.map4k.baseEepHeader.length); else - el = ahp->ah_eeprom.map4k.baseEepHeader.length; + el = ah->ah_eeprom.map4k.baseEepHeader.length; if (el > sizeof(struct ar5416_eeprom_def)) el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); else el = el / sizeof(u16); - eepdata = (u16 *)(&ahp->ah_eeprom); + eepdata = (u16 *)(&ah->ah_eeprom); for (i = 0; i < el; i++) sum ^= *eepdata++; @@ -403,11 +397,11 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) } } - if (sum != 0xffff || ar5416_get_eep4k_ver(ahp) != AR5416_EEP_VER || - ar5416_get_eep4k_rev(ahp) < AR5416_EEP_NO_BACK_VER) { + if (sum != 0xffff || ar5416_get_eep4k_ver(ah) != AR5416_EEP_VER || + ar5416_get_eep4k_rev(ah) < AR5416_EEP_NO_BACK_VER) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", - sum, ar5416_get_eep4k_ver(ahp)); + sum, ar5416_get_eep4k_ver(ah)); return -EINVAL; } @@ -415,16 +409,14 @@ static int ath9k_hw_check_4k_eeprom(struct ath_hal *ah) #undef EEPROM_4K_SIZE } -static int (*ath9k_check_eeprom[]) (struct ath_hal *) = { +static int (*ath9k_check_eeprom[]) (struct ath_hw *) = { ath9k_hw_check_def_eeprom, ath9k_hw_check_4k_eeprom }; -static inline int ath9k_hw_check_eeprom(struct ath_hal *ah) +static inline int ath9k_hw_check_eeprom(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_check_eeprom[ahp->ah_eep_map](ah); + return ath9k_check_eeprom[ah->ah_eep_map](ah); } static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, @@ -456,7 +448,7 @@ static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, return true; } -static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hal *ah, +static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_data_per_freq_4k *pRawDataSet, u8 *bChans, u16 availPiers, @@ -624,7 +616,7 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hal *ah, #undef TMP_VAL_VPD_TABLE } -static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hal *ah, +static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_data_per_freq *pRawDataSet, u8 *bChans, u16 availPiers, @@ -789,7 +781,7 @@ static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hal *ah, return; } -static void ath9k_hw_get_legacy_target_powers(struct ath_hal *ah, +static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_leg *powInfo, u16 numChannels, @@ -844,7 +836,7 @@ static void ath9k_hw_get_legacy_target_powers(struct ath_hal *ah, } } -static void ath9k_hw_get_target_powers(struct ath_hal *ah, +static void ath9k_hw_get_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_ht *powInfo, u16 numChannels, @@ -927,12 +919,11 @@ static u16 ath9k_hw_get_max_edge_power(u16 freq, return twiceMaxEdgePower; } -static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah, +static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; struct cal_data_per_freq *pRawDataset; u8 *pCalBChans = NULL; u16 pdGainOverlap_t2; @@ -988,7 +979,7 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah, for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (AR_SREV_5416_V20_OR_LATER(ah) && - (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) && + (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && (i != 0)) { regChainOffset = (i == 1) ? 0x2000 : 0x1000; } else @@ -1054,12 +1045,11 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hal *ah, return true; } -static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah, +static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; struct cal_data_per_freq_4k *pRawDataset; u8 *pCalBChans = NULL; u16 pdGainOverlap_t2; @@ -1108,7 +1098,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah, for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (AR_SREV_5416_V20_OR_LATER(ah) && - (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) && + (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && (i != 0)) { regChainOffset = (i == 1) ? 0x2000 : 0x1000; } else @@ -1171,7 +1161,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hal *ah, return true; } -static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, +static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, @@ -1182,8 +1172,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; static const u16 tpScaleReductionTable[5] = { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; @@ -1213,7 +1202,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, int tx_chainmask; u16 twiceMinEdgePower; - tx_chainmask = ahp->ah_txchainmask; + tx_chainmask = ah->ah_txchainmask; ath9k_hw_get_channel_centers(ah, chan, ¢ers); @@ -1322,7 +1311,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, else freq = centers.ctl_center; - if (ar5416_get_eep_ver(ahp) == 14 && ar5416_get_eep_rev(ahp) <= 2) + if (ar5416_get_eep_ver(ah) == 14 && ar5416_get_eep_rev(ah) <= 2) twiceMaxEdgePower = AR5416_MAX_RATE_POWER; DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, @@ -1462,7 +1451,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hal *ah, return true; } -static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, +static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, @@ -1470,8 +1459,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, u16 twiceMaxRegulatoryPower, u16 powerLimit) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; static const u16 tpScaleReductionTable[5] = { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; @@ -1499,7 +1487,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, int tx_chainmask; u16 twiceMinEdgePower; - tx_chainmask = ahp->ah_txchainmask; + tx_chainmask = ah->ah_txchainmask; ath9k_hw_get_channel_centers(ah, chan, ¢ers); @@ -1560,8 +1548,8 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, else freq = centers.ctl_center; - if (ar5416_get_eep_ver(ahp) == 14 && - ar5416_get_eep_rev(ahp) <= 2) + if (ar5416_get_eep_ver(ah) == 14 && + ar5416_get_eep_rev(ah) <= 2) twiceMaxEdgePower = AR5416_MAX_RATE_POWER; DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, @@ -1698,15 +1686,14 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hal *ah, return true; } -static int ath9k_hw_def_set_txpower(struct ath_hal *ah, +static int ath9k_hw_def_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *pEepData = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; struct modal_eep_header *pModal = &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); int16_t ratesArray[Ar5416RateSize]; @@ -1831,15 +1818,14 @@ static int ath9k_hw_def_set_txpower(struct ath_hal *ah, return 0; } -static int ath9k_hw_4k_set_txpower(struct ath_hal *ah, +static int ath9k_hw_4k_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *pEepData = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; struct modal_eep_4k_header *pModal = &pEepData->modalHeader; int16_t ratesArray[Ar5416RateSize]; int16_t txPowerIndexOffset = 0; @@ -1959,40 +1945,37 @@ static int ath9k_hw_4k_set_txpower(struct ath_hal *ah, return 0; } -static int (*ath9k_set_txpower[]) (struct ath_hal *, +static int (*ath9k_set_txpower[]) (struct ath_hw *, struct ath9k_channel *, u16, u8, u8, u8) = { ath9k_hw_def_set_txpower, ath9k_hw_4k_set_txpower }; -int ath9k_hw_set_txpower(struct ath_hal *ah, +int ath9k_hw_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_set_txpower[ahp->ah_eep_map](ah, chan, cfgCtl, - twiceAntennaReduction, twiceMaxRegulatoryPower, - powerLimit); + return ath9k_set_txpower[ah->ah_eep_map](ah, chan, cfgCtl, + twiceAntennaReduction, twiceMaxRegulatoryPower, + powerLimit); } -static void ath9k_hw_set_def_addac(struct ath_hal *ah, +static void ath9k_hw_set_def_addac(struct ath_hw *ah, struct ath9k_channel *chan) { #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) struct modal_eep_header *pModal; - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; u8 biaslevel; if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) return; - if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) + if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7) return; pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); @@ -2026,60 +2009,54 @@ static void ath9k_hw_set_def_addac(struct ath_hal *ah, } if (IS_CHAN_2GHZ(chan)) { - INI_RA(&ahp->ah_iniAddac, 7, 1) = (INI_RA(&ahp->ah_iniAddac, + INI_RA(&ah->ah_iniAddac, 7, 1) = (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; } else { - INI_RA(&ahp->ah_iniAddac, 6, 1) = (INI_RA(&ahp->ah_iniAddac, + INI_RA(&ah->ah_iniAddac, 6, 1) = (INI_RA(&ah->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel << 6; } #undef XPA_LVL_FREQ } -static void ath9k_hw_set_4k_addac(struct ath_hal *ah, +static void ath9k_hw_set_4k_addac(struct ath_hw *ah, struct ath9k_channel *chan) { struct modal_eep_4k_header *pModal; - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; u8 biaslevel; if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) return; - if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) + if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7) return; pModal = &eep->modalHeader; if (pModal->xpaBiasLvl != 0xff) { biaslevel = pModal->xpaBiasLvl; - INI_RA(&ahp->ah_iniAddac, 7, 1) = - (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; + INI_RA(&ah->ah_iniAddac, 7, 1) = + (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; } } -static void (*ath9k_set_addac[]) (struct ath_hal *, struct ath9k_channel *) = { +static void (*ath9k_set_addac[]) (struct ath_hw *, struct ath9k_channel *) = { ath9k_hw_set_def_addac, ath9k_hw_set_4k_addac }; -void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan) +void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - - ath9k_set_addac[ahp->ah_eep_map](ah, chan); + ath9k_set_addac[ah->ah_eep_map](ah, chan); } - - /* XXX: Clean me up, make me more legible */ -static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah, +static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) struct modal_eep_header *pModal; - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; int i, regChainOffset; u8 txRxAttenLocal; @@ -2097,7 +2074,7 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah, } if (AR_SREV_5416_V20_OR_LATER(ah) && - (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) + (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && (i != 0)) regChainOffset = (i == 1) ? 0x2000 : 0x1000; else @@ -2318,12 +2295,11 @@ static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hal *ah, #undef AR5416_VER_MASK } -static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hal *ah, +static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { struct modal_eep_4k_header *pModal; - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; int regChainOffset; u8 txRxAttenLocal; u8 ob[5], db1[5], db2[5]; @@ -2505,66 +2481,59 @@ static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hal *ah, return true; } -static bool (*ath9k_eeprom_set_board_values[])(struct ath_hal *, +static bool (*ath9k_eeprom_set_board_values[])(struct ath_hw *, struct ath9k_channel *) = { ath9k_hw_eeprom_set_def_board_values, ath9k_hw_eeprom_set_4k_board_values }; -bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, +bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_eeprom_set_board_values[ahp->ah_eep_map](ah, chan); + return ath9k_eeprom_set_board_values[ah->ah_eep_map](ah, chan); } -static u16 ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hal *ah, +static u16 ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; struct modal_eep_header *pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); return pModal->antCtrlCommon & 0xFFFF; } -static u16 ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hal *ah, +static u16 ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; struct modal_eep_4k_header *pModal = &eep->modalHeader; return pModal->antCtrlCommon & 0xFFFF; } -static u16 (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hal *, +static u16 (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hw *, struct ath9k_channel *) = { ath9k_hw_get_def_eeprom_antenna_cfg, ath9k_hw_get_4k_eeprom_antenna_cfg }; -u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, +u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_get_eeprom_antenna_cfg[ahp->ah_eep_map](ah, chan); + return ath9k_get_eeprom_antenna_cfg[ah->ah_eep_map](ah, chan); } -static u8 ath9k_hw_get_4k_num_ant_config(struct ath_hal *ah, +static u8 ath9k_hw_get_4k_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band) { return 1; } -static u8 ath9k_hw_get_def_num_ant_config(struct ath_hal *ah, +static u8 ath9k_hw_get_def_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; struct modal_eep_header *pModal = &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]); struct base_eep_header *pBase = &eep->baseEepHeader; @@ -2579,27 +2548,24 @@ static u8 ath9k_hw_get_def_num_ant_config(struct ath_hal *ah, return num_ant_config; } -static u8 (*ath9k_get_num_ant_config[])(struct ath_hal *, +static u8 (*ath9k_get_num_ant_config[])(struct ath_hw *, enum ieee80211_band) = { ath9k_hw_get_def_num_ant_config, ath9k_hw_get_4k_num_ant_config }; -u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, +u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_get_num_ant_config[ahp->ah_eep_map](ah, freq_band); + return ath9k_get_num_ant_config[ah->ah_eep_map](ah, freq_band); } -u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz) +u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz) { #define EEP_MAP4K_SPURCHAN \ - (ahp->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) + (ah->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) #define EEP_DEF_SPURCHAN \ - (ahp->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) - struct ath_hal_5416 *ahp = AH5416(ah); + (ah->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) u16 spur_val = AR_NO_SPUR; DPRINTF(ah->ah_sc, ATH_DBG_ANI, @@ -2615,7 +2581,7 @@ u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz) "Getting spur val from new loc. %d\n", spur_val); break; case SPUR_ENABLE_EEPROM: - if (ahp->ah_eep_map == EEP_MAP_4KBITS) + if (ah->ah_eep_map == EEP_MAP_4KBITS) spur_val = EEP_MAP4K_SPURCHAN; else spur_val = EEP_DEF_SPURCHAN; @@ -2628,11 +2594,10 @@ u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz) #undef EEP_MAP4K_SPURCHAN } -static u32 ath9k_hw_get_eeprom_4k(struct ath_hal *ah, +static u32 ath9k_hw_get_eeprom_4k(struct ath_hw *ah, enum eeprom_param param) { - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_4k *eep = &ahp->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; struct modal_eep_4k_header *pModal = &eep->modalHeader; struct base_eep_header_4k *pBase = &eep->baseEepHeader; @@ -2670,12 +2635,11 @@ static u32 ath9k_hw_get_eeprom_4k(struct ath_hal *ah, } } -static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah, +static u32 ath9k_hw_get_eeprom_def(struct ath_hw *ah, enum eeprom_param param) { #define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) - struct ath_hal_5416 *ahp = AH5416(ah); - struct ar5416_eeprom_def *eep = &ahp->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; struct modal_eep_header *pModal = eep->modalHeader; struct base_eep_header *pBase = &eep->baseEepHeader; @@ -2729,28 +2693,25 @@ static u32 ath9k_hw_get_eeprom_def(struct ath_hal *ah, #undef AR5416_VER_MASK } -static u32 (*ath9k_get_eeprom[])(struct ath_hal *, enum eeprom_param) = { +static u32 (*ath9k_get_eeprom[])(struct ath_hw *, enum eeprom_param) = { ath9k_hw_get_eeprom_def, ath9k_hw_get_eeprom_4k }; -u32 ath9k_hw_get_eeprom(struct ath_hal *ah, +u32 ath9k_hw_get_eeprom(struct ath_hw *ah, enum eeprom_param param) { - struct ath_hal_5416 *ahp = AH5416(ah); - - return ath9k_get_eeprom[ahp->ah_eep_map](ah, param); + return ath9k_get_eeprom[ah->ah_eep_map](ah, param); } -int ath9k_hw_eeprom_attach(struct ath_hal *ah) +int ath9k_hw_eeprom_attach(struct ath_hw *ah) { int status; - struct ath_hal_5416 *ahp = AH5416(ah); if (AR_SREV_9285(ah)) - ahp->ah_eep_map = EEP_MAP_4KBITS; + ah->ah_eep_map = EEP_MAP_4KBITS; else - ahp->ah_eep_map = EEP_MAP_DEFAULT; + ah->ah_eep_map = EEP_MAP_DEFAULT; if (!ath9k_hw_fill_eeprom(ah)) return -EIO; diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 9eb777465144..81a7a708bc85 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -447,38 +447,38 @@ enum hal_eep_map { EEP_MAP_MAX }; -#define ar5416_get_eep_ver(_ahp) \ - (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) -#define ar5416_get_eep_rev(_ahp) \ - (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF) +#define ar5416_get_eep_ver(_ah) \ + (((_ah)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) +#define ar5416_get_eep_rev(_ah) \ + (((_ah)->ah_eeprom.def.baseEepHeader.version) & 0xFFF) #define ar5416_get_ntxchains(_txchainmask) \ (((_txchainmask >> 2) & 1) + \ ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) -#define ar5416_get_eep4k_ver(_ahp) \ - (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) -#define ar5416_get_eep4k_rev(_ahp) \ - (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) +#define ar5416_get_eep4k_ver(_ah) \ + (((_ah)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) +#define ar5416_get_eep4k_rev(_ah) \ + (((_ah)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) -int ath9k_hw_set_txpower(struct ath_hal *ah, struct ath9k_channel *chan, +int ath9k_hw_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit); -void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan); -bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, +void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan); +bool ath9k_hw_set_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, u8 AntennaReduction, u8 twiceMaxRegulatoryPower, u8 powerLimit); -bool ath9k_hw_set_power_cal_table(struct ath_hal *ah, +bool ath9k_hw_set_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset); -bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, +bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan); -u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, +u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan); -u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, +u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band); -u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz); -u32 ath9k_hw_get_eeprom(struct ath_hal *ah, enum eeprom_param param); -int ath9k_hw_eeprom_attach(struct ath_hal *ah); +u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz); +u32 ath9k_hw_get_eeprom(struct ath_hw *ah, enum eeprom_param param); +int ath9k_hw_eeprom_attach(struct ath_hw *ah); #endif /* EEPROM_H */ diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 5d7287549c0b..ba908e9f1a8e 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -28,41 +28,45 @@ MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support"); #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 -static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type); -static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, +static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); +static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, enum ath9k_ht_macmode macmode); -static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, +static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, struct ar5416_eeprom_def *pEepData, u32 reg, u32 value); -static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); -static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan); +static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); +static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan); /********************/ /* Helper Functions */ /********************/ -static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks) +static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; + if (!ah->ah_curchan) /* should really check for CCK instead */ return clks / ATH9K_CLOCK_RATE_CCK; if (conf->channel->band == IEEE80211_BAND_2GHZ) return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM; + return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM; } -static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks) +static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; + if (conf_is_ht40(conf)) return ath9k_hw_mac_usec(ah, clks) / 2; else return ath9k_hw_mac_usec(ah, clks); } -static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs) +static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; + if (!ah->ah_curchan) /* should really check for CCK instead */ return usecs *ATH9K_CLOCK_RATE_CCK; if (conf->channel->band == IEEE80211_BAND_2GHZ) @@ -70,16 +74,17 @@ static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs) return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; } -static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs) +static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; + if (conf_is_ht40(conf)) return ath9k_hw_mac_clks(ah, usecs) * 2; else return ath9k_hw_mac_clks(ah, usecs); } -bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val) +bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val) { int i; @@ -109,7 +114,7 @@ u32 ath9k_hw_reverse_bits(u32 val, u32 n) return retval; } -bool ath9k_get_channel_edges(struct ath_hal *ah, +bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high) { @@ -128,7 +133,7 @@ bool ath9k_get_channel_edges(struct ath_hal *ah, return false; } -u16 ath9k_hw_computetxtime(struct ath_hal *ah, +u16 ath9k_hw_computetxtime(struct ath_hw *ah, struct ath_rate_table *rates, u32 frameLen, u16 rateix, bool shortPreamble) @@ -184,12 +189,11 @@ u16 ath9k_hw_computetxtime(struct ath_hal *ah, return txTime; } -void ath9k_hw_get_channel_centers(struct ath_hal *ah, +void ath9k_hw_get_channel_centers(struct ath_hw *ah, struct ath9k_channel *chan, struct chan_centers *centers) { int8_t extoff; - struct ath_hal_5416 *ahp = AH5416(ah); if (!IS_CHAN_HT40(chan)) { centers->ctl_center = centers->ext_center = @@ -212,16 +216,15 @@ void ath9k_hw_get_channel_centers(struct ath_hal *ah, centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); centers->ext_center = centers->synth_center + (extoff * - ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? + ((ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? HT40_CHANNEL_CENTER_SHIFT : 15)); - } /******************/ /* Chip Revisions */ /******************/ -static void ath9k_hw_read_revisions(struct ath_hal *ah) +static void ath9k_hw_read_revisions(struct ath_hw *ah) { u32 val; @@ -244,7 +247,7 @@ static void ath9k_hw_read_revisions(struct ath_hal *ah) } } -static int ath9k_hw_get_radiorev(struct ath_hal *ah) +static int ath9k_hw_get_radiorev(struct ath_hw *ah) { u32 val; int i; @@ -263,7 +266,7 @@ static int ath9k_hw_get_radiorev(struct ath_hal *ah) /* HW Attach, Detach, Init Routines */ /************************************/ -static void ath9k_hw_disablepcie(struct ath_hal *ah) +static void ath9k_hw_disablepcie(struct ath_hw *ah) { if (AR_SREV_9100(ah)) return; @@ -281,7 +284,7 @@ static void ath9k_hw_disablepcie(struct ath_hal *ah) REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); } -static bool ath9k_hw_chip_test(struct ath_hal *ah) +static bool ath9k_hw_chip_test(struct ath_hw *ah) { u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) }; u32 regHold[2]; @@ -323,6 +326,7 @@ static bool ath9k_hw_chip_test(struct ath_hal *ah) REG_WRITE(ah, regAddr[i], regHold[i]); } udelay(100); + return true; } @@ -347,7 +351,7 @@ static const char *ath9k_hw_devname(u16 devid) return NULL; } -static void ath9k_hw_set_defaults(struct ath_hal *ah) +static void ath9k_hw_set_defaults(struct ath_hw *ah) { int i; @@ -387,25 +391,20 @@ static void ath9k_hw_set_defaults(struct ath_hal *ah) ah->ah_config.intr_mitigation = 1; } -static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, - struct ath_softc *sc, - void __iomem *mem, - int *status) +static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc, + int *status) { - struct ath_hal_5416 *ahp; - struct ath_hal *ah; + struct ath_hw *ah; - ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL); - if (ahp == NULL) { + ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); + if (ah == NULL) { DPRINTF(sc, ATH_DBG_FATAL, "Cannot allocate memory for state block\n"); *status = -ENOMEM; return NULL; } - ah = &ahp->ah; ah->ah_sc = sc; - ah->ah_sh = mem; ah->hw_version.magic = AR5416_MAGIC; ah->regulatory.country_code = CTRY_DEFAULT; ah->hw_version.devid = devid; @@ -419,24 +418,24 @@ static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, ah->regulatory.power_limit = MAX_RATE_POWER; ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX; - ahp->ah_atimWindow = 0; - ahp->ah_diversityControl = ah->ah_config.diversity_control; - ahp->ah_antennaSwitchSwap = + ah->ah_atimWindow = 0; + ah->ah_diversityControl = ah->ah_config.diversity_control; + ah->ah_antennaSwitchSwap = ah->ah_config.antenna_switch_swap; - ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; - ahp->ah_beaconInterval = 100; - ahp->ah_enable32kHzClock = DONT_USE_32KHZ; - ahp->ah_slottime = (u32) -1; - ahp->ah_acktimeout = (u32) -1; - ahp->ah_ctstimeout = (u32) -1; - ahp->ah_globaltxtimeout = (u32) -1; + ah->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; + ah->ah_beaconInterval = 100; + ah->ah_enable32kHzClock = DONT_USE_32KHZ; + ah->ah_slottime = (u32) -1; + ah->ah_acktimeout = (u32) -1; + ah->ah_ctstimeout = (u32) -1; + ah->ah_globaltxtimeout = (u32) -1; - ahp->ah_gBeaconRate = 0; + ah->ah_gBeaconRate = 0; - return ahp; + return ah; } -static int ath9k_hw_rfattach(struct ath_hal *ah) +static int ath9k_hw_rfattach(struct ath_hw *ah) { bool rfStatus = false; int ecode = 0; @@ -451,7 +450,7 @@ static int ath9k_hw_rfattach(struct ath_hal *ah) return 0; } -static int ath9k_hw_rf_claim(struct ath_hal *ah) +static int ath9k_hw_rf_claim(struct ath_hw *ah) { u32 val; @@ -480,7 +479,7 @@ static int ath9k_hw_rf_claim(struct ath_hal *ah) return 0; } -static int ath9k_hw_init_macaddr(struct ath_hal *ah) +static int ath9k_hw_init_macaddr(struct ath_hw *ah) { u32 sum; int i; @@ -503,55 +502,55 @@ static int ath9k_hw_init_macaddr(struct ath_hal *ah) return 0; } -static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah) +static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) { u32 rxgain_type; - struct ath_hal_5416 *ahp = AH5416(ah); if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE); if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) - INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->ah_iniModesRxGain, ar9280Modes_backoff_13db_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) - INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->ah_iniModesRxGain, ar9280Modes_backoff_23db_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); else - INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->ah_iniModesRxGain, ar9280Modes_original_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); - } else - INIT_INI_ARRAY(&ahp->ah_iniModesRxGain, + } else { + INIT_INI_ARRAY(&ah->ah_iniModesRxGain, ar9280Modes_original_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); + } } -static void ath9k_hw_init_txgain_ini(struct ath_hal *ah) +static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) { u32 txgain_type; - struct ath_hal_5416 *ahp = AH5416(ah); if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE); if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) - INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, + INIT_INI_ARRAY(&ah->ah_iniModesTxGain, ar9280Modes_high_power_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); else - INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, + INIT_INI_ARRAY(&ah->ah_iniModesTxGain, ar9280Modes_original_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); - } else - INIT_INI_ARRAY(&ahp->ah_iniModesTxGain, + } else { + INIT_INI_ARRAY(&ah->ah_iniModesTxGain, ar9280Modes_original_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); + } } -static int ath9k_hw_post_attach(struct ath_hal *ah) +static int ath9k_hw_post_attach(struct ath_hw *ah) { int ecode; @@ -580,33 +579,30 @@ static int ath9k_hw_post_attach(struct ath_hal *ah) return 0; } -static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, - void __iomem *mem, int *status) +static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, + int *status) { - struct ath_hal_5416 *ahp; - struct ath_hal *ah; + struct ath_hw *ah; int ecode; u32 i, j; - ahp = ath9k_hw_newstate(devid, sc, mem, status); - if (ahp == NULL) + ah = ath9k_hw_newstate(devid, sc, status); + if (ah == NULL) return NULL; - ah = &ahp->ah; - ath9k_hw_set_defaults(ah); if (ah->ah_config.intr_mitigation != 0) - ahp->ah_intrMitigation = true; + ah->ah_intrMitigation = true; if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n"); + DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n"); ecode = -EIO; goto bad; } if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n"); + DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n"); ecode = -EIO; goto bad; } @@ -621,15 +617,14 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, } } - DPRINTF(ah->ah_sc, ATH_DBG_RESET, - "serialize_regmode is %d\n", + DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n", ah->ah_config.serialize_regmode); if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) && (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && (ah->hw_version.macVersion != AR_SREV_VERSION_9160) && (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, + DPRINTF(sc, ATH_DBG_RESET, "Mac Chip Rev 0x%02x.%x is not supported by " "this driver\n", ah->hw_version.macVersion, ah->hw_version.macRev); @@ -638,176 +633,176 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, } if (AR_SREV_9100(ah)) { - ahp->ah_iqCalData.calData = &iq_cal_multi_sample; - ahp->ah_suppCals = IQ_MISMATCH_CAL; + ah->ah_iqCalData.calData = &iq_cal_multi_sample; + ah->ah_suppCals = IQ_MISMATCH_CAL; ah->ah_isPciExpress = false; } ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); if (AR_SREV_9160_10_OR_LATER(ah)) { if (AR_SREV_9280_10_OR_LATER(ah)) { - ahp->ah_iqCalData.calData = &iq_cal_single_sample; - ahp->ah_adcGainCalData.calData = + ah->ah_iqCalData.calData = &iq_cal_single_sample; + ah->ah_adcGainCalData.calData = &adc_gain_cal_single_sample; - ahp->ah_adcDcCalData.calData = + ah->ah_adcDcCalData.calData = &adc_dc_cal_single_sample; - ahp->ah_adcDcCalInitData.calData = + ah->ah_adcDcCalInitData.calData = &adc_init_dc_cal; } else { - ahp->ah_iqCalData.calData = &iq_cal_multi_sample; - ahp->ah_adcGainCalData.calData = + ah->ah_iqCalData.calData = &iq_cal_multi_sample; + ah->ah_adcGainCalData.calData = &adc_gain_cal_multi_sample; - ahp->ah_adcDcCalData.calData = + ah->ah_adcDcCalData.calData = &adc_dc_cal_multi_sample; - ahp->ah_adcDcCalInitData.calData = + ah->ah_adcDcCalInitData.calData = &adc_init_dc_cal; } - ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; + ah->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; } if (AR_SREV_9160(ah)) { ah->ah_config.enable_ani = 1; - ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | + ah->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | ATH9K_ANI_FIRSTEP_LEVEL); } else { - ahp->ah_ani_function = ATH9K_ANI_ALL; + ah->ah_ani_function = ATH9K_ANI_ALL; if (AR_SREV_9280_10_OR_LATER(ah)) { - ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; + ah->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; } } - DPRINTF(ah->ah_sc, ATH_DBG_RESET, + DPRINTF(sc, ATH_DBG_RESET, "This Mac Chip Rev 0x%02x.%x is \n", ah->hw_version.macVersion, ah->hw_version.macRev); if (AR_SREV_9285_12_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2, + INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285_1_2, ARRAY_SIZE(ar9285Modes_9285_1_2), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285_1_2, ARRAY_SIZE(ar9285Common_9285_1_2), 2); if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9285PciePhy_clkreq_off_L1_9285_1_2, ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); } else { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9285PciePhy_clkreq_always_on_L1_9285_1_2, ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 2); } } else if (AR_SREV_9285_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285, + INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285, ARRAY_SIZE(ar9285Modes_9285), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285, ARRAY_SIZE(ar9285Common_9285), 2); if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9285PciePhy_clkreq_off_L1_9285, ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); } else { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9285PciePhy_clkreq_always_on_L1_9285, ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); } } else if (AR_SREV_9280_20_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2, + INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280_2, ARRAY_SIZE(ar9280Modes_9280_2), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280_2, ARRAY_SIZE(ar9280Common_9280_2), 2); if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9280PciePhy_clkreq_off_L1_9280, ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); } else { - INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, ar9280PciePhy_clkreq_always_on_L1_9280, ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); } - INIT_INI_ARRAY(&ahp->ah_iniModesAdditional, + INIT_INI_ARRAY(&ah->ah_iniModesAdditional, ar9280Modes_fast_clock_9280_2, ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); } else if (AR_SREV_9280_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280, + INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280, ARRAY_SIZE(ar9280Modes_9280), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280, ARRAY_SIZE(ar9280Common_9280), 2); } else if (AR_SREV_9160_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160, + INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9160, ARRAY_SIZE(ar5416Modes_9160), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9160, ARRAY_SIZE(ar5416Common_9160), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160, + INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9160, ARRAY_SIZE(ar5416Bank0_9160), 2); - INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160, + INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9160, ARRAY_SIZE(ar5416BB_RfGain_9160), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160, + INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9160, ARRAY_SIZE(ar5416Bank1_9160), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160, + INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9160, ARRAY_SIZE(ar5416Bank2_9160), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160, + INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9160, ARRAY_SIZE(ar5416Bank3_9160), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160, + INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9160, ARRAY_SIZE(ar5416Bank6_9160), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160, + INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9160, ARRAY_SIZE(ar5416Bank6TPC_9160), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160, + INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9160, ARRAY_SIZE(ar5416Bank7_9160), 2); if (AR_SREV_9160_11(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniAddac, + INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_91601_1, ARRAY_SIZE(ar5416Addac_91601_1), 2); } else { - INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160, + INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9160, ARRAY_SIZE(ar5416Addac_9160), 2); } } else if (AR_SREV_9100_OR_LATER(ah)) { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100, + INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9100, ARRAY_SIZE(ar5416Modes_9100), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9100, ARRAY_SIZE(ar5416Common_9100), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100, + INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9100, ARRAY_SIZE(ar5416Bank0_9100), 2); - INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100, + INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9100, ARRAY_SIZE(ar5416BB_RfGain_9100), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100, + INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9100, ARRAY_SIZE(ar5416Bank1_9100), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100, + INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9100, ARRAY_SIZE(ar5416Bank2_9100), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100, + INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9100, ARRAY_SIZE(ar5416Bank3_9100), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100, + INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9100, ARRAY_SIZE(ar5416Bank6_9100), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100, + INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9100, ARRAY_SIZE(ar5416Bank6TPC_9100), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100, + INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9100, ARRAY_SIZE(ar5416Bank7_9100), 2); - INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100, + INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9100, ARRAY_SIZE(ar5416Addac_9100), 2); } else { - INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes, + INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes, ARRAY_SIZE(ar5416Modes), 6); - INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common, + INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common, ARRAY_SIZE(ar5416Common), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0, + INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0, ARRAY_SIZE(ar5416Bank0), 2); - INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain, + INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain, ARRAY_SIZE(ar5416BB_RfGain), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1, + INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1, ARRAY_SIZE(ar5416Bank1), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2, + INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2, ARRAY_SIZE(ar5416Bank2), 2); - INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3, + INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3, ARRAY_SIZE(ar5416Bank3), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6, + INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6, ARRAY_SIZE(ar5416Bank6), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC, + INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC, ARRAY_SIZE(ar5416Bank6TPC), 3); - INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7, + INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7, ARRAY_SIZE(ar5416Bank7), 2); - INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac, + INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac, ARRAY_SIZE(ar5416Addac), 2); } @@ -829,22 +824,22 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ath9k_hw_init_txgain_ini(ah); if (ah->hw_version.devid == AR9280_DEVID_PCI) { - for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { - u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); + for (i = 0; i < ah->ah_iniModes.ia_rows; i++) { + u32 reg = INI_RA(&ah->ah_iniModes, i, 0); - for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) { - u32 val = INI_RA(&ahp->ah_iniModes, i, j); + for (j = 1; j < ah->ah_iniModes.ia_columns; j++) { + u32 val = INI_RA(&ah->ah_iniModes, i, j); - INI_RA(&ahp->ah_iniModes, i, j) = + INI_RA(&ah->ah_iniModes, i, j) = ath9k_hw_ini_fixup(ah, - &ahp->ah_eeprom.def, + &ah->ah_eeprom.def, reg, val); } } } if (!ath9k_hw_fill_cap_info(ah)) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, + DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n"); ecode = -EINVAL; goto bad; @@ -852,7 +847,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ecode = ath9k_hw_init_macaddr(ah); if (ecode != 0) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, + DPRINTF(sc, ATH_DBG_RESET, "failed initializing mac address\n"); goto bad; } @@ -866,15 +861,15 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, return ah; bad: - if (ahp) - ath9k_hw_detach((struct ath_hal *) ahp); + if (ah) + ath9k_hw_detach(ah); if (status) *status = ecode; return NULL; } -static void ath9k_hw_init_bb(struct ath_hal *ah, +static void ath9k_hw_init_bb(struct ath_hw *ah, struct ath9k_channel *chan) { u32 synthDelay; @@ -890,7 +885,7 @@ static void ath9k_hw_init_bb(struct ath_hal *ah, udelay(synthDelay + BASE_ACTIVATE_DELAY); } -static void ath9k_hw_init_qos(struct ath_hal *ah) +static void ath9k_hw_init_qos(struct ath_hw *ah) { REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); @@ -907,7 +902,7 @@ static void ath9k_hw_init_qos(struct ath_hal *ah) REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); } -static void ath9k_hw_init_pll(struct ath_hal *ah, +static void ath9k_hw_init_pll(struct ath_hw *ah, struct ath9k_channel *chan) { u32 pll; @@ -975,13 +970,12 @@ static void ath9k_hw_init_pll(struct ath_hal *ah, REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); } -static void ath9k_hw_init_chain_masks(struct ath_hal *ah) +static void ath9k_hw_init_chain_masks(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); int rx_chainmask, tx_chainmask; - rx_chainmask = ahp->ah_rxchainmask; - tx_chainmask = ahp->ah_txchainmask; + rx_chainmask = ah->ah_rxchainmask; + tx_chainmask = ah->ah_txchainmask; switch (rx_chainmask) { case 0x5: @@ -1013,28 +1007,26 @@ static void ath9k_hw_init_chain_masks(struct ath_hal *ah) REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); } -static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, +static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, enum nl80211_iftype opmode) { - struct ath_hal_5416 *ahp = AH5416(ah); - - ahp->ah_maskReg = AR_IMR_TXERR | + ah->ah_maskReg = AR_IMR_TXERR | AR_IMR_TXURN | AR_IMR_RXERR | AR_IMR_RXORN | AR_IMR_BCNMISC; - if (ahp->ah_intrMitigation) - ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; + if (ah->ah_intrMitigation) + ah->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; else - ahp->ah_maskReg |= AR_IMR_RXOK; + ah->ah_maskReg |= AR_IMR_RXOK; - ahp->ah_maskReg |= AR_IMR_TXOK; + ah->ah_maskReg |= AR_IMR_TXOK; if (opmode == NL80211_IFTYPE_AP) - ahp->ah_maskReg |= AR_IMR_MIB; + ah->ah_maskReg |= AR_IMR_MIB; - REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); + REG_WRITE(ah, AR_IMR, ah->ah_maskReg); REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); if (!AR_SREV_9100(ah)) { @@ -1044,72 +1036,64 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, } } -static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us) +static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); - ahp->ah_acktimeout = (u32) -1; + ah->ah_acktimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); - ahp->ah_acktimeout = us; + ah->ah_acktimeout = us; return true; } } -static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us) +static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); - ahp->ah_ctstimeout = (u32) -1; + ah->ah_ctstimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); - ahp->ah_ctstimeout = us; + ah->ah_ctstimeout = us; return true; } } -static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu) +static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (tu > 0xFFFF) { DPRINTF(ah->ah_sc, ATH_DBG_XMIT, "bad global tx timeout %u\n", tu); - ahp->ah_globaltxtimeout = (u32) -1; + ah->ah_globaltxtimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); - ahp->ah_globaltxtimeout = tu; + ah->ah_globaltxtimeout = tu; return true; } } -static void ath9k_hw_init_user_settings(struct ath_hal *ah) +static void ath9k_hw_init_user_settings(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); + DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->ah_miscMode 0x%x\n", + ah->ah_miscMode); - DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n", - ahp->ah_miscMode); - - if (ahp->ah_miscMode != 0) + if (ah->ah_miscMode != 0) REG_WRITE(ah, AR_PCU_MISC, - REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode); - if (ahp->ah_slottime != (u32) -1) - ath9k_hw_setslottime(ah, ahp->ah_slottime); - if (ahp->ah_acktimeout != (u32) -1) - ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout); - if (ahp->ah_ctstimeout != (u32) -1) - ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout); - if (ahp->ah_globaltxtimeout != (u32) -1) - ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout); + REG_READ(ah, AR_PCU_MISC) | ah->ah_miscMode); + if (ah->ah_slottime != (u32) -1) + ath9k_hw_setslottime(ah, ah->ah_slottime); + if (ah->ah_acktimeout != (u32) -1) + ath9k_hw_set_ack_timeout(ah, ah->ah_acktimeout); + if (ah->ah_ctstimeout != (u32) -1) + ath9k_hw_set_cts_timeout(ah, ah->ah_ctstimeout); + if (ah->ah_globaltxtimeout != (u32) -1) + ath9k_hw_set_global_txtimeout(ah, ah->ah_globaltxtimeout); } const char *ath9k_hw_probe(u16 vendorid, u16 devid) @@ -1118,7 +1102,7 @@ const char *ath9k_hw_probe(u16 vendorid, u16 devid) ath9k_hw_devname(devid) : NULL; } -void ath9k_hw_detach(struct ath_hal *ah) +void ath9k_hw_detach(struct ath_hw *ah) { if (!AR_SREV_9100(ah)) ath9k_hw_ani_detach(ah); @@ -1128,10 +1112,9 @@ void ath9k_hw_detach(struct ath_hal *ah) kfree(ah); } -struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, - void __iomem *mem, int *error) +struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error) { - struct ath_hal *ah = NULL; + struct ath_hw *ah = NULL; switch (devid) { case AR5416_DEVID_PCI: @@ -1141,7 +1124,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, case AR9280_DEVID_PCI: case AR9280_DEVID_PCIE: case AR9285_DEVID_PCIE: - ah = ath9k_hw_do_attach(devid, sc, mem, error); + ah = ath9k_hw_do_attach(devid, sc, error); break; default: *error = -ENXIO; @@ -1155,7 +1138,7 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, /* INI */ /*******/ -static void ath9k_hw_override_ini(struct ath_hal *ah, +static void ath9k_hw_override_ini(struct ath_hw *ah, struct ath9k_channel *chan) { /* @@ -1173,7 +1156,7 @@ static void ath9k_hw_override_ini(struct ath_hal *ah, REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); } -static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah, +static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah, struct ar5416_eeprom_def *pEepData, u32 reg, u32 value) { @@ -1207,24 +1190,21 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah, return value; } -static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, +static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, struct ar5416_eeprom_def *pEepData, u32 reg, u32 value) { - struct ath_hal_5416 *ahp = AH5416(ah); - - if (ahp->ah_eep_map == EEP_MAP_4KBITS) + if (ah->ah_eep_map == EEP_MAP_4KBITS) return value; else return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); } -static int ath9k_hw_process_ini(struct ath_hal *ah, +static int ath9k_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan, enum ath9k_ht_macmode macmode) { int i, regWrites = 0; - struct ath_hal_5416 *ahp = AH5416(ah); struct ieee80211_channel *channel = chan->chan; u32 modesIndex, freqIndex; int status; @@ -1257,35 +1237,33 @@ static int ath9k_hw_process_ini(struct ath_hal *ah, } REG_WRITE(ah, AR_PHY(0), 0x00000007); - REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); - ath9k_hw_set_addac(ah, chan); if (AR_SREV_5416_V22_OR_LATER(ah)) { - REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites); + REG_WRITE_ARRAY(&ah->ah_iniAddac, 1, regWrites); } else { struct ar5416IniArray temp; u32 addacSize = - sizeof(u32) * ahp->ah_iniAddac.ia_rows * - ahp->ah_iniAddac.ia_columns; + sizeof(u32) * ah->ah_iniAddac.ia_rows * + ah->ah_iniAddac.ia_columns; - memcpy(ahp->ah_addac5416_21, - ahp->ah_iniAddac.ia_array, addacSize); + memcpy(ah->ah_addac5416_21, + ah->ah_iniAddac.ia_array, addacSize); - (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0; + (ah->ah_addac5416_21)[31 * ah->ah_iniAddac.ia_columns + 1] = 0; - temp.ia_array = ahp->ah_addac5416_21; - temp.ia_columns = ahp->ah_iniAddac.ia_columns; - temp.ia_rows = ahp->ah_iniAddac.ia_rows; + temp.ia_array = ah->ah_addac5416_21; + temp.ia_columns = ah->ah_iniAddac.ia_columns; + temp.ia_rows = ah->ah_iniAddac.ia_rows; REG_WRITE_ARRAY(&temp, 1, regWrites); } REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); - for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) { - u32 reg = INI_RA(&ahp->ah_iniModes, i, 0); - u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex); + for (i = 0; i < ah->ah_iniModes.ia_rows; i++) { + u32 reg = INI_RA(&ah->ah_iniModes, i, 0); + u32 val = INI_RA(&ah->ah_iniModes, i, modesIndex); REG_WRITE(ah, reg, val); @@ -1298,14 +1276,14 @@ static int ath9k_hw_process_ini(struct ath_hal *ah, } if (AR_SREV_9280(ah)) - REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites); + REG_WRITE_ARRAY(&ah->ah_iniModesRxGain, modesIndex, regWrites); if (AR_SREV_9280(ah)) - REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites); + REG_WRITE_ARRAY(&ah->ah_iniModesTxGain, modesIndex, regWrites); - for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) { - u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0); - u32 val = INI_RA(&ahp->ah_iniCommon, i, 1); + for (i = 0; i < ah->ah_iniCommon.ia_rows; i++) { + u32 reg = INI_RA(&ah->ah_iniCommon, i, 0); + u32 val = INI_RA(&ah->ah_iniCommon, i, 1); REG_WRITE(ah, reg, val); @@ -1320,7 +1298,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah, ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { - REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex, + REG_WRITE_ARRAY(&ah->ah_iniModesAdditional, modesIndex, regWrites); } @@ -1353,7 +1331,7 @@ static int ath9k_hw_process_ini(struct ath_hal *ah, /* Reset and Channel Switching Routines */ /****************************************/ -static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan) +static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan) { u32 rfMode = 0; @@ -1373,12 +1351,12 @@ static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan) REG_WRITE(ah, AR_PHY_MODE, rfMode); } -static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah) +static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah) { REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); } -static inline void ath9k_hw_set_dma(struct ath_hal *ah) +static inline void ath9k_hw_set_dma(struct ath_hw *ah) { u32 regval; @@ -1404,7 +1382,7 @@ static inline void ath9k_hw_set_dma(struct ath_hal *ah) } } -static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) +static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) { u32 val; @@ -1428,7 +1406,7 @@ static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode) } } -static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, +static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, u32 *coef_mantissa, u32 *coef_exponent) @@ -1447,7 +1425,7 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah, *coef_exponent = coef_exp - 16; } -static void ath9k_hw_set_delta_slope(struct ath_hal *ah, +static void ath9k_hw_set_delta_slope(struct ath_hw *ah, struct ath9k_channel *chan) { u32 coef_scaled, ds_coef_exp, ds_coef_man; @@ -1481,7 +1459,7 @@ static void ath9k_hw_set_delta_slope(struct ath_hal *ah, AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); } -static bool ath9k_hw_set_reset(struct ath_hal *ah, int type) +static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) { u32 rst_flags; u32 tmpReg; @@ -1529,7 +1507,7 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type) return true; } -static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah) +static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) { REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); @@ -1550,7 +1528,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah) return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); } -static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type) +static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) { REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); @@ -1568,12 +1546,11 @@ static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type) } } -static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, +static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, enum ath9k_ht_macmode macmode) { u32 phymode; u32 enableDacFifo = 0; - struct ath_hal_5416 *ahp = AH5416(ah); if (AR_SREV_9285_10_OR_LATER(ah)) enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & @@ -1589,7 +1566,7 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, (chan->chanmode == CHANNEL_G_HT40PLUS)) phymode |= AR_PHY_FC_DYN2040_PRI_CH; - if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) + if (ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) phymode |= AR_PHY_FC_DYN2040_EXT_CH; } REG_WRITE(ah, AR_PHY_TURBO, phymode); @@ -1600,27 +1577,23 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); } -static bool ath9k_hw_chip_reset(struct ath_hal *ah, +static bool ath9k_hw_chip_reset(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) return false; if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) return false; - ahp->ah_chipFullSleep = false; - + ah->ah_chipFullSleep = false; ath9k_hw_init_pll(ah, chan); - ath9k_hw_set_rfmode(ah, chan); return true; } -static bool ath9k_hw_channel_change(struct ath_hal *ah, +static bool ath9k_hw_channel_change(struct ath_hw *ah, struct ath9k_channel *chan, enum ath9k_ht_macmode macmode) { @@ -1694,7 +1667,7 @@ static bool ath9k_hw_channel_change(struct ath_hal *ah, return true; } -static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) +static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) { int bb_spur = AR_NO_SPUR; int freq; @@ -1944,7 +1917,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); } -static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan) +static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) { int bb_spur = AR_NO_SPUR; int bin, cur_bin; @@ -2145,27 +2118,26 @@ static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *cha REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); } -int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, +int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, bool bChannelChange) { u32 saveLedState; struct ath_softc *sc = ah->ah_sc; - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_channel *curchan = ah->ah_curchan; u32 saveDefAntenna; u32 macStaId1; int i, rx_chainmask, r; - ahp->ah_extprotspacing = sc->ht_extprotspacing; - ahp->ah_txchainmask = sc->tx_chainmask; - ahp->ah_rxchainmask = sc->rx_chainmask; + ah->ah_extprotspacing = sc->ht_extprotspacing; + ah->ah_txchainmask = sc->tx_chainmask; + ah->ah_rxchainmask = sc->rx_chainmask; if (AR_SREV_9285(ah)) { - ahp->ah_txchainmask &= 0x1; - ahp->ah_rxchainmask &= 0x1; + ah->ah_txchainmask &= 0x1; + ah->ah_rxchainmask &= 0x1; } else if (AR_SREV_9280(ah)) { - ahp->ah_txchainmask &= 0x3; - ahp->ah_rxchainmask &= 0x3; + ah->ah_txchainmask &= 0x3; + ah->ah_rxchainmask &= 0x3; } if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) @@ -2175,7 +2147,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, ath9k_hw_getnf(ah, curchan); if (bChannelChange && - (ahp->ah_chipFullSleep != true) && + (ah->ah_chipFullSleep != true) && (ah->ah_curchan != NULL) && (chan->channel != ah->ah_curchan->channel) && ((chan->channelFlags & CHANNEL_ALL) == @@ -2253,7 +2225,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, | AR_STA_ID1_RTS_USE_DEF | (ah->ah_config. ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) - | ahp->ah_staId1Defaults); + | ah->ah_staId1Defaults); ath9k_hw_set_operating_mode(ah, ah->ah_opmode); REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); @@ -2280,7 +2252,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, for (i = 0; i < AR_NUM_DCU; i++) REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); - ahp->ah_intrTxqs = 0; + ah->ah_intrTxqs = 0; for (i = 0; i < ah->ah_caps.total_queues; i++) ath9k_hw_resettxqueue(ah, i); @@ -2300,7 +2272,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, REG_WRITE(ah, AR_OBS, 8); - if (ahp->ah_intrMitigation) { + if (ah->ah_intrMitigation) { REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); @@ -2311,7 +2283,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, if (!ath9k_hw_init_cal(ah, chan)) return -EIO;; - rx_chainmask = ahp->ah_rxchainmask; + rx_chainmask = ah->ah_rxchainmask; if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); @@ -2345,7 +2317,7 @@ int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, /* Key Cache Management */ /************************/ -bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) +bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) { u32 keyType; @@ -2382,7 +2354,7 @@ bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry) return true; } -bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac) +bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) { u32 macHi, macLo; @@ -2410,7 +2382,7 @@ bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac) return true; } -bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, +bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, const struct ath9k_keyval *k, const u8 *mac, int xorKey) { @@ -2420,7 +2392,6 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, u32 xorMask = xorKey ? (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8 | ATH9K_KEY_XOR) : 0; - struct ath_hal_5416 *ahp = AH5416(ah); if (entry >= pCap->keycache_size) { DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, @@ -2491,7 +2462,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); (void) ath9k_hw_keysetmac(ah, entry, mac); - if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { + if (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { u32 mic0, mic1, mic2, mic3, mic4; mic0 = get_unaligned_le32(k->kv_mic + 0); @@ -2541,7 +2512,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, return true; } -bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) +bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) { if (entry < ah->ah_caps.keycache_size) { u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); @@ -2555,7 +2526,7 @@ bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry) /* Power Management (Chipset) */ /******************************/ -static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip) +static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) { REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); if (setChip) { @@ -2569,7 +2540,7 @@ static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip) } } -static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip) +static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) { REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); if (setChip) { @@ -2585,8 +2556,7 @@ static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip) } } -static bool ath9k_hw_set_power_awake(struct ath_hal *ah, - int setChip) +static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) { u32 val; int i; @@ -2627,17 +2597,15 @@ static bool ath9k_hw_set_power_awake(struct ath_hal *ah, return true; } -bool ath9k_hw_setpower(struct ath_hal *ah, - enum ath9k_power_mode mode) +bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) { - struct ath_hal_5416 *ahp = AH5416(ah); + int status = true, setChip = true; static const char *modes[] = { "AWAKE", "FULL-SLEEP", "NETWORK SLEEP", "UNDEFINED" }; - int status = true, setChip = true; DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n", modes[ah->ah_power_mode], modes[mode], @@ -2649,7 +2617,7 @@ bool ath9k_hw_setpower(struct ath_hal *ah, break; case ATH9K_PM_FULL_SLEEP: ath9k_set_power_sleep(ah, setChip); - ahp->ah_chipFullSleep = true; + ah->ah_chipFullSleep = true; break; case ATH9K_PM_NETWORK_SLEEP: ath9k_set_power_network_sleep(ah, setChip); @@ -2664,9 +2632,8 @@ bool ath9k_hw_setpower(struct ath_hal *ah, return status; } -void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) +void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) { - struct ath_hal_5416 *ahp = AH5416(ah); u8 i; if (ah->ah_isPciExpress != true) @@ -2679,9 +2646,9 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) return; if (AR_SREV_9280_20_OR_LATER(ah)) { - for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) { - REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0), - INI_RA(&ahp->ah_iniPcieSerdes, i, 1)); + for (i = 0; i < ah->ah_iniPcieSerdes.ia_rows; i++) { + REG_WRITE(ah, INI_RA(&ah->ah_iniPcieSerdes, i, 0), + INI_RA(&ah->ah_iniPcieSerdes, i, 1)); } udelay(1000); } else if (AR_SREV_9280(ah) && @@ -2730,14 +2697,13 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) else REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); } - } /**********************/ /* Interrupt Handling */ /**********************/ -bool ath9k_hw_intrpend(struct ath_hal *ah) +bool ath9k_hw_intrpend(struct ath_hw *ah) { u32 host_isr; @@ -2756,14 +2722,13 @@ bool ath9k_hw_intrpend(struct ath_hal *ah) return false; } -bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) +bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) { u32 isr = 0; u32 mask2 = 0; struct ath9k_hw_capabilities *pCap = &ah->ah_caps; u32 sync_cause = 0; bool fatal_int = false; - struct ath_hal_5416 *ahp = AH5416(ah); if (!AR_SREV_9100(ah)) { if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { @@ -2811,7 +2776,7 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) *masked = isr & ATH9K_INT_COMMON; - if (ahp->ah_intrMitigation) { + if (ah->ah_intrMitigation) { if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) *masked |= ATH9K_INT_RX; } @@ -2826,12 +2791,12 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) *masked |= ATH9K_INT_TX; s0_s = REG_READ(ah, AR_ISR_S0_S); - ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); - ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); + ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); + ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); s1_s = REG_READ(ah, AR_ISR_S1_S); - ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); - ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); + ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); + ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); } if (isr & AR_ISR_RXORN) { @@ -2888,15 +2853,14 @@ bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked) return true; } -enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah) +enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah) { - return AH5416(ah)->ah_maskReg; + return ah->ah_maskReg; } -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) { - struct ath_hal_5416 *ahp = AH5416(ah); - u32 omask = ahp->ah_maskReg; + u32 omask = ah->ah_maskReg; u32 mask, mask2; struct ath9k_hw_capabilities *pCap = &ah->ah_caps; @@ -2919,18 +2883,18 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) mask2 = 0; if (ints & ATH9K_INT_TX) { - if (ahp->ah_txOkInterruptMask) + if (ah->ah_txOkInterruptMask) mask |= AR_IMR_TXOK; - if (ahp->ah_txDescInterruptMask) + if (ah->ah_txDescInterruptMask) mask |= AR_IMR_TXDESC; - if (ahp->ah_txErrInterruptMask) + if (ah->ah_txErrInterruptMask) mask |= AR_IMR_TXERR; - if (ahp->ah_txEolInterruptMask) + if (ah->ah_txEolInterruptMask) mask |= AR_IMR_TXEOL; } if (ints & ATH9K_INT_RX) { mask |= AR_IMR_RXERR; - if (ahp->ah_intrMitigation) + if (ah->ah_intrMitigation) mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; else mask |= AR_IMR_RXOK | AR_IMR_RXDESC; @@ -2968,7 +2932,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); REG_WRITE(ah, AR_IMR_S2, mask | mask2); - ahp->ah_maskReg = ints; + ah->ah_maskReg = ints; if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { if (ints & ATH9K_INT_TIM_TIMER) @@ -3002,12 +2966,11 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints) /* Beacon Handling */ /*******************/ -void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period) +void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) { - struct ath_hal_5416 *ahp = AH5416(ah); int flags = 0; - ahp->ah_beaconInterval = beacon_period; + ah->ah_beaconInterval = beacon_period; switch (ah->ah_opmode) { case NL80211_IFTYPE_STATION: @@ -3022,7 +2985,7 @@ void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period) AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); REG_WRITE(ah, AR_NEXT_NDP_TIMER, TU_TO_USEC(next_beacon + - (ahp->ah_atimWindow ? ahp-> + (ah->ah_atimWindow ? ah-> ah_atimWindow : 1))); flags |= AR_NDP_TIMER_EN; case NL80211_IFTYPE_AP: @@ -3060,7 +3023,7 @@ void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period) REG_SET_BIT(ah, AR_TIMER_MODE, flags); } -void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, +void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, const struct ath9k_beacon_state *bs) { u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; @@ -3124,9 +3087,8 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, /* HW Capabilities */ /*******************/ -bool ath9k_hw_fill_cap_info(struct ath_hal *ah) +bool ath9k_hw_fill_cap_info(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; u16 capField = 0, eeval; @@ -3195,7 +3157,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) } if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) - ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; + ah->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; pCap->low_2ghz_chan = 2312; pCap->high_2ghz_chan = 2732; @@ -3317,10 +3279,9 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) return true; } -bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, +bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 *result) { - struct ath_hal_5416 *ahp = AH5416(ah); const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; switch (type) { @@ -3341,17 +3302,17 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, case 0: return true; case 1: - return (ahp->ah_staId1Defaults & + return (ah->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) ? true : false; } case ATH9K_CAP_TKIP_SPLIT: - return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? + return (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? false : true; case ATH9K_CAP_WME_TKIPMIC: return 0; case ATH9K_CAP_PHYCOUNTERS: - return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO; + return ah->ah_hasHwPhyCounters ? 0 : -ENXIO; case ATH9K_CAP_DIVERSITY: return (REG_READ(ah, AR_PHY_CCK_DETECT) & AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? @@ -3366,14 +3327,14 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { return false; } else { - return (ahp->ah_staId1Defaults & + return (ah->ah_staId1Defaults & AR_STA_ID1_MCAST_KSRCH) ? true : false; } } return false; case ATH9K_CAP_TSF_ADJUST: - return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ? + return (ah->ah_miscMode & AR_PCU_TX_ADD_TSF) ? true : false; case ATH9K_CAP_RFSILENT: if (capability == 3) @@ -3404,19 +3365,18 @@ bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, } } -bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, +bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 setting, int *status) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 v; switch (type) { case ATH9K_CAP_TKIP_MIC: if (setting) - ahp->ah_staId1Defaults |= + ah->ah_staId1Defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; else - ahp->ah_staId1Defaults &= + ah->ah_staId1Defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; return true; case ATH9K_CAP_DIVERSITY: @@ -3429,15 +3389,15 @@ bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, return true; case ATH9K_CAP_MCAST_KEYSRCH: if (setting) - ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; + ah->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; else - ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; + ah->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; return true; case ATH9K_CAP_TSF_ADJUST: if (setting) - ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; + ah->ah_miscMode |= AR_PCU_TX_ADD_TSF; else - ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; + ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; return true; default: return false; @@ -3448,7 +3408,7 @@ bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, /* GPIO / RFKILL / Antennae */ /****************************/ -static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, +static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type) { int addr; @@ -3476,7 +3436,7 @@ static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah, } } -void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio) +void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) { u32 gpio_shift; @@ -3490,7 +3450,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio) (AR_GPIO_OE_OUT_DRV << gpio_shift)); } -u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) +u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) { #define MS_REG_READ(x, y) \ (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) @@ -3506,7 +3466,7 @@ u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio) return MS_REG_READ(AR, gpio) != 0; } -void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, +void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, u32 ah_signal_type) { u32 gpio_shift; @@ -3521,14 +3481,14 @@ void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, (AR_GPIO_OE_OUT_DRV << gpio_shift)); } -void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val) +void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) { REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), AR_GPIO_BIT(gpio)); } #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) -void ath9k_enable_rfkill(struct ath_hal *ah) +void ath9k_enable_rfkill(struct ath_hw *ah) { REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); @@ -3541,24 +3501,23 @@ void ath9k_enable_rfkill(struct ath_hal *ah) } #endif -u32 ath9k_hw_getdefantenna(struct ath_hal *ah) +u32 ath9k_hw_getdefantenna(struct ath_hw *ah) { return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; } -void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna) +void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) { REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); } -bool ath9k_hw_setantennaswitch(struct ath_hal *ah, +bool ath9k_hw_setantennaswitch(struct ath_hw *ah, enum ath9k_ant_setting settings, struct ath9k_channel *chan, u8 *tx_chainmask, u8 *rx_chainmask, u8 *antenna_cfgd) { - struct ath_hal_5416 *ahp = AH5416(ah); static u8 tx_chainmask_cfg, rx_chainmask_cfg; if (AR_SREV_9280(ah)) { @@ -3591,7 +3550,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hal *ah, break; } } else { - ahp->ah_diversityControl = settings; + ah->ah_diversityControl = settings; } return true; @@ -3601,7 +3560,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hal *ah, /* General Operation */ /*********************/ -u32 ath9k_hw_getrxfilter(struct ath_hal *ah) +u32 ath9k_hw_getrxfilter(struct ath_hw *ah) { u32 bits = REG_READ(ah, AR_RX_FILTER); u32 phybits = REG_READ(ah, AR_PHY_ERR); @@ -3614,7 +3573,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hal *ah) return bits; } -void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits) +void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) { u32 phybits; @@ -3634,12 +3593,12 @@ void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits) REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); } -bool ath9k_hw_phy_disable(struct ath_hal *ah) +bool ath9k_hw_phy_disable(struct ath_hw *ah) { return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM); } -bool ath9k_hw_disable(struct ath_hal *ah) +bool ath9k_hw_disable(struct ath_hw *ah) { if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) return false; @@ -3647,7 +3606,7 @@ bool ath9k_hw_disable(struct ath_hal *ah) return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD); } -bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) +bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) { struct ath9k_channel *chan = ah->ah_curchan; struct ieee80211_channel *channel = chan->chan; @@ -3665,17 +3624,17 @@ bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit) return true; } -void ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac) +void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) { memcpy(ah->macaddr, mac, ETH_ALEN); } -void ath9k_hw_setopmode(struct ath_hal *ah) +void ath9k_hw_setopmode(struct ath_hw *ah) { ath9k_hw_set_operating_mode(ah, ah->ah_opmode); } -void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1) +void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) { REG_WRITE(ah, AR_MCAST_FIL0, filter0); REG_WRITE(ah, AR_MCAST_FIL1, filter1); @@ -3694,7 +3653,7 @@ void ath9k_hw_write_associd(struct ath_softc *sc) ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); } -u64 ath9k_hw_gettsf64(struct ath_hal *ah) +u64 ath9k_hw_gettsf64(struct ath_hw *ah) { u64 tsf; @@ -3704,14 +3663,14 @@ u64 ath9k_hw_gettsf64(struct ath_hal *ah) return tsf; } -void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64) +void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) { REG_WRITE(ah, AR_TSF_L32, 0x00000000); REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); } -void ath9k_hw_reset_tsf(struct ath_hal *ah) +void ath9k_hw_reset_tsf(struct ath_hw *ah) { int count; @@ -3728,34 +3687,30 @@ void ath9k_hw_reset_tsf(struct ath_hal *ah) REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); } -bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting) +bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (setting) - ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF; + ah->ah_miscMode |= AR_PCU_TX_ADD_TSF; else - ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; + ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; return true; } -bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us) +bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); - ahp->ah_slottime = (u32) -1; + ah->ah_slottime = (u32) -1; return false; } else { REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); - ahp->ah_slottime = us; + ah->ah_slottime = us; return true; } } -void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) +void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode) { u32 macmode; @@ -3772,7 +3727,7 @@ void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode) /* Bluetooth Coexistence */ /***************************/ -void ath9k_hw_btcoex_enable(struct ath_hal *ah) +void ath9k_hw_btcoex_enable(struct ath_hw *ah) { /* connect bt_active to baseband */ REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index f4bf70215744..84914e205892 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -42,8 +42,8 @@ #define AR5416_MAGIC 0x19641014 /* Register read/write primitives */ -#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg) -#define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg) +#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sc->mem + _reg) +#define REG_READ(_ah, _reg) ioread32(_ah->ah_sc->mem + _reg) #define SM(_v, _f) (((_v) << _f##_S) & _f) #define MS(_v, _f) (((_v) & _f) >> _f##_S) @@ -417,46 +417,38 @@ struct ath9k_hw_version { u16 analog2GhzRev; }; -struct ath_hal { - struct ath9k_hw_version hw_version; - void __iomem *ah_sh; +struct ath_hw { struct ath_softc *ah_sc; - - enum nl80211_iftype ah_opmode; + struct ath9k_hw_version hw_version; struct ath9k_ops_config ah_config; struct ath9k_hw_capabilities ah_caps; struct ath9k_regulatory regulatory; - u32 ah_flags; - u8 macaddr[ETH_ALEN]; - - enum ath9k_power_mode ah_power_mode; - enum ath9k_power_mode ah_restore_mode; - struct ath9k_channel ah_channels[38]; struct ath9k_channel *ah_curchan; + union { + struct ar5416_eeprom_def def; + struct ar5416_eeprom_4k map4k; + } ah_eeprom; + + bool sw_mgmt_crypto; bool ah_isPciExpress; + u8 macaddr[ETH_ALEN]; u16 ah_txTrigLevel; u16 ah_rfsilent; u32 ah_rfkill_gpio; u32 ah_rfkill_polarity; u32 ah_btactive_gpio; u32 ah_wlanactive_gpio; + u32 ah_flags; + enum nl80211_iftype ah_opmode; - struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; - - bool sw_mgmt_crypto; -}; + enum ath9k_power_mode ah_power_mode; + enum ath9k_power_mode ah_restore_mode; -struct ath_hal_5416 { - struct ath_hal ah; - union { - struct ar5416_eeprom_def def; - struct ar5416_eeprom_4k map4k; - } ah_eeprom; + struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; struct ar5416Stats ah_stats; struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES]; - void __iomem *ah_cal_mem; int16_t ah_curchanRadIndex; u32 ah_maskReg; @@ -574,85 +566,83 @@ struct ath_hal_5416 { /* To indicate EEPROM mapping used */ enum hal_eep_map ah_eep_map; }; -#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) /* Attach, Detach, Reset */ const char *ath9k_hw_probe(u16 vendorid, u16 devid); -void ath9k_hw_detach(struct ath_hal *ah); -struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, - void __iomem *mem, int *error); -void ath9k_hw_rfdetach(struct ath_hal *ah); -int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, +void ath9k_hw_detach(struct ath_hw *ah); +struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error); +void ath9k_hw_rfdetach(struct ath_hw *ah); +int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, bool bChannelChange); -bool ath9k_hw_fill_cap_info(struct ath_hal *ah); -bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, +bool ath9k_hw_fill_cap_info(struct ath_hw *ah); +bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 *result); -bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, +bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 setting, int *status); /* Key Cache Management */ -bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry); -bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac); -bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, +bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); +bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac); +bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, const struct ath9k_keyval *k, const u8 *mac, int xorKey); -bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry); +bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry); /* GPIO / RFKILL / Antennae */ -void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio); -u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio); -void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, +void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); +u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); +void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, u32 ah_signal_type); -void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val); +void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) -void ath9k_enable_rfkill(struct ath_hal *ah); +void ath9k_enable_rfkill(struct ath_hw *ah); #endif -u32 ath9k_hw_getdefantenna(struct ath_hal *ah); -void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna); -bool ath9k_hw_setantennaswitch(struct ath_hal *ah, +u32 ath9k_hw_getdefantenna(struct ath_hw *ah); +void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); +bool ath9k_hw_setantennaswitch(struct ath_hw *ah, enum ath9k_ant_setting settings, struct ath9k_channel *chan, u8 *tx_chainmask, u8 *rx_chainmask, u8 *antenna_cfgd); /* General Operation */ -bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val); +bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val); u32 ath9k_hw_reverse_bits(u32 val, u32 n); -bool ath9k_get_channel_edges(struct ath_hal *ah, u16 flags, u16 *low, u16 *high); -u16 ath9k_hw_computetxtime(struct ath_hal *ah, struct ath_rate_table *rates, +bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high); +u16 ath9k_hw_computetxtime(struct ath_hw *ah, struct ath_rate_table *rates, u32 frameLen, u16 rateix, bool shortPreamble); -void ath9k_hw_get_channel_centers(struct ath_hal *ah, +void ath9k_hw_get_channel_centers(struct ath_hw *ah, struct ath9k_channel *chan, struct chan_centers *centers); -u32 ath9k_hw_getrxfilter(struct ath_hal *ah); -void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits); -bool ath9k_hw_phy_disable(struct ath_hal *ah); -bool ath9k_hw_disable(struct ath_hal *ah); -bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit); -void ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac); -void ath9k_hw_setopmode(struct ath_hal *ah); -void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1); +u32 ath9k_hw_getrxfilter(struct ath_hw *ah); +void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); +bool ath9k_hw_phy_disable(struct ath_hw *ah); +bool ath9k_hw_disable(struct ath_hw *ah); +bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit); +void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac); +void ath9k_hw_setopmode(struct ath_hw *ah); +void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); void ath9k_hw_setbssidmask(struct ath_softc *sc); void ath9k_hw_write_associd(struct ath_softc *sc); -u64 ath9k_hw_gettsf64(struct ath_hal *ah); -void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64); -void ath9k_hw_reset_tsf(struct ath_hal *ah); -bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting); -bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us); -void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode); -void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period); -void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, +u64 ath9k_hw_gettsf64(struct ath_hw *ah); +void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); +void ath9k_hw_reset_tsf(struct ath_hw *ah); +bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); +bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us); +void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode); +void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); +void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, const struct ath9k_beacon_state *bs); -bool ath9k_hw_setpower(struct ath_hal *ah, +bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); -void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore); +void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore); /* Interrupt Handling */ -bool ath9k_hw_intrpend(struct ath_hal *ah); -bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked); -enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah); -enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints); +bool ath9k_hw_intrpend(struct ath_hw *ah); +bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked); +enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah); +enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints); -void ath9k_hw_btcoex_enable(struct ath_hal *ah); +void ath9k_hw_btcoex_enable(struct ath_hw *ah); #endif diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c index b375a2964d2a..ac2071444017 100644 --- a/drivers/net/wireless/ath9k/mac.c +++ b/drivers/net/wireless/ath9k/mac.c @@ -16,40 +16,38 @@ #include "ath9k.h" -static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah, +static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, struct ath9k_tx_queue_info *qi) { - struct ath_hal_5416 *ahp = AH5416(ah); - DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", - ahp->ah_txOkInterruptMask, ahp->ah_txErrInterruptMask, - ahp->ah_txDescInterruptMask, ahp->ah_txEolInterruptMask, - ahp->ah_txUrnInterruptMask); + ah->ah_txOkInterruptMask, ah->ah_txErrInterruptMask, + ah->ah_txDescInterruptMask, ah->ah_txEolInterruptMask, + ah->ah_txUrnInterruptMask); REG_WRITE(ah, AR_IMR_S0, - SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) - | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)); + SM(ah->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) + | SM(ah->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)); REG_WRITE(ah, AR_IMR_S1, - SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) - | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)); + SM(ah->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) + | SM(ah->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)); REG_RMW_FIELD(ah, AR_IMR_S2, - AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask); + AR_IMR_S2_QCU_TXURN, ah->ah_txUrnInterruptMask); } -u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q) +u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) { return REG_READ(ah, AR_QTXDP(q)); } -bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp) +bool ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp) { REG_WRITE(ah, AR_QTXDP(q), txdp); return true; } -bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) +bool ath9k_hw_txstart(struct ath_hw *ah, u32 q) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); @@ -58,7 +56,7 @@ bool ath9k_hw_txstart(struct ath_hal *ah, u32 q) return true; } -u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q) +u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q) { u32 npend; @@ -72,16 +70,15 @@ u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q) return npend; } -bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel) +bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) { - struct ath_hal_5416 *ahp = AH5416(ah); u32 txcfg, curLevel, newLevel; enum ath9k_int omask; if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD) return false; - omask = ath9k_hw_set_interrupts(ah, ahp->ah_maskReg & ~ATH9K_INT_GLOBAL); + omask = ath9k_hw_set_interrupts(ah, ah->ah_maskReg & ~ATH9K_INT_GLOBAL); txcfg = REG_READ(ah, AR_TXCFG); curLevel = MS(txcfg, AR_FTRIG); @@ -102,12 +99,11 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel) return newLevel != curLevel; } -bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) +bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) { #define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */ #define ATH9K_TIME_QUANTUM 100 /* usec */ - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_tx_queue_info *qi; u32 tsfLow, j, wait; @@ -118,7 +114,7 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) return false; } - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -180,7 +176,7 @@ bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q) #undef ATH9K_TIME_QUANTUM } -bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, +bool ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds, u32 segLen, bool firstSeg, bool lastSeg, const struct ath_desc *ds0) { @@ -208,7 +204,7 @@ bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, return true; } -void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds) +void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -219,7 +215,7 @@ void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds) ads->ds_txstatus8 = ads->ds_txstatus9 = 0; } -int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds) +int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -294,14 +290,13 @@ int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds) return 0; } -void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds, u32 pktLen, enum ath9k_pkt_type type, u32 txPower, u32 keyIx, enum ath9k_key_type keyType, u32 flags) { struct ar5416_desc *ads = AR5416DESC(ds); - struct ath_hal_5416 *ahp = AH5416(ah); - txPower += ahp->ah_txPowerIndexOffset; + txPower += ah->ah_txPowerIndexOffset; if (txPower > 63) txPower = 63; @@ -330,7 +325,7 @@ void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, } } -void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds, struct ath_desc *lastds, u32 durUpdateEn, u32 rtsctsRate, u32 rtsctsDuration, @@ -385,7 +380,7 @@ void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, last_ads->ds_ctl3 = ads->ds_ctl3; } -void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds, u32 aggrLen) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -395,7 +390,7 @@ void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen); } -void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds, u32 numDelims) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -409,7 +404,7 @@ void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, ads->ds_ctl6 = ctl6; } -void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds) +void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -418,14 +413,14 @@ void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds) ads->ds_ctl6 &= ~AR_PadDelim; } -void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds) +void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds) { struct ar5416_desc *ads = AR5416DESC(ds); ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); } -void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds, u32 burstDuration) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -434,7 +429,7 @@ void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); } -void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds, u32 vmf) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -445,19 +440,16 @@ void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, ads->ds_ctl0 &= ~AR_VirtMoreFrag; } -void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs) +void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs) { - struct ath_hal_5416 *ahp = AH5416(ah); - - *txqs &= ahp->ah_intrTxqs; - ahp->ah_intrTxqs &= ~(*txqs); + *txqs &= ah->ah_intrTxqs; + ah->ah_intrTxqs &= ~(*txqs); } -bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, +bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, const struct ath9k_tx_queue_info *qinfo) { u32 cw; - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_tx_queue_info *qi; @@ -466,7 +458,7 @@ bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, return false; } - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -522,10 +514,9 @@ bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, return true; } -bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, +bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, struct ath9k_tx_queue_info *qinfo) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_tx_queue_info *qi; @@ -534,7 +525,7 @@ bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, return false; } - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -558,10 +549,9 @@ bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, return true; } -int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, +int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, const struct ath9k_tx_queue_info *qinfo) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_tx_queue_info *qi; struct ath9k_hw_capabilities *pCap = &ah->ah_caps; int q; @@ -581,7 +571,7 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, break; case ATH9K_TX_QUEUE_DATA: for (q = 0; q < pCap->total_queues; q++) - if (ahp->ah_txq[q].tqi_type == + if (ah->ah_txq[q].tqi_type == ATH9K_TX_QUEUE_INACTIVE) break; if (q == pCap->total_queues) { @@ -597,7 +587,7 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "tx queue %u already active\n", q); @@ -624,9 +614,8 @@ int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, return q; } -bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) +bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_tx_queue_info *qi; @@ -634,7 +623,7 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); return false; } - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); return false; @@ -643,19 +632,18 @@ bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q) DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q); qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; - ahp->ah_txOkInterruptMask &= ~(1 << q); - ahp->ah_txErrInterruptMask &= ~(1 << q); - ahp->ah_txDescInterruptMask &= ~(1 << q); - ahp->ah_txEolInterruptMask &= ~(1 << q); - ahp->ah_txUrnInterruptMask &= ~(1 << q); + ah->ah_txOkInterruptMask &= ~(1 << q); + ah->ah_txErrInterruptMask &= ~(1 << q); + ah->ah_txDescInterruptMask &= ~(1 << q); + ah->ah_txEolInterruptMask &= ~(1 << q); + ah->ah_txUrnInterruptMask &= ~(1 << q); ath9k_hw_set_txq_interrupts(ah, qi); return true; } -bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) +bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) { - struct ath_hal_5416 *ahp = AH5416(ah); struct ath9k_hw_capabilities *pCap = &ah->ah_caps; struct ath9k_channel *chan = ah->ah_curchan; struct ath9k_tx_queue_info *qi; @@ -666,7 +654,7 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) return false; } - qi = &ahp->ah_txq[q]; + qi = &ah->ah_txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); return true; @@ -784,31 +772,31 @@ bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q) } if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) - ahp->ah_txOkInterruptMask |= 1 << q; + ah->ah_txOkInterruptMask |= 1 << q; else - ahp->ah_txOkInterruptMask &= ~(1 << q); + ah->ah_txOkInterruptMask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) - ahp->ah_txErrInterruptMask |= 1 << q; + ah->ah_txErrInterruptMask |= 1 << q; else - ahp->ah_txErrInterruptMask &= ~(1 << q); + ah->ah_txErrInterruptMask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) - ahp->ah_txDescInterruptMask |= 1 << q; + ah->ah_txDescInterruptMask |= 1 << q; else - ahp->ah_txDescInterruptMask &= ~(1 << q); + ah->ah_txDescInterruptMask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) - ahp->ah_txEolInterruptMask |= 1 << q; + ah->ah_txEolInterruptMask |= 1 << q; else - ahp->ah_txEolInterruptMask &= ~(1 << q); + ah->ah_txEolInterruptMask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) - ahp->ah_txUrnInterruptMask |= 1 << q; + ah->ah_txUrnInterruptMask |= 1 << q; else - ahp->ah_txUrnInterruptMask &= ~(1 << q); + ah->ah_txUrnInterruptMask &= ~(1 << q); ath9k_hw_set_txq_interrupts(ah, qi); return true; } -int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, +int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, u32 pa, struct ath_desc *nds, u64 tsf) { struct ar5416_desc ads; @@ -873,7 +861,7 @@ int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, return 0; } -bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, +bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, u32 size, u32 flags) { struct ar5416_desc *ads = AR5416DESC(ds); @@ -890,7 +878,7 @@ bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, return true; } -bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set) +bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set) { u32 reg; @@ -917,17 +905,17 @@ bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set) return true; } -void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp) +void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp) { REG_WRITE(ah, AR_RXDP, rxdp); } -void ath9k_hw_rxena(struct ath_hal *ah) +void ath9k_hw_rxena(struct ath_hw *ah) { REG_WRITE(ah, AR_CR, AR_CR_RXE); } -void ath9k_hw_startpcureceive(struct ath_hal *ah) +void ath9k_hw_startpcureceive(struct ath_hw *ah) { ath9k_enable_mib_counters(ah); @@ -936,14 +924,14 @@ void ath9k_hw_startpcureceive(struct ath_hal *ah) REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); } -void ath9k_hw_stoppcurecv(struct ath_hal *ah) +void ath9k_hw_stoppcurecv(struct ath_hw *ah) { REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); ath9k_hw_disable_mib_counters(ah); } -bool ath9k_hw_stopdmarecv(struct ath_hal *ah) +bool ath9k_hw_stopdmarecv(struct ath_hw *ah) { REG_WRITE(ah, AR_CR, AR_CR_RXD); diff --git a/drivers/net/wireless/ath9k/mac.h b/drivers/net/wireless/ath9k/mac.h index 9012af247797..74b660ae8add 100644 --- a/drivers/net/wireless/ath9k/mac.h +++ b/drivers/net/wireless/ath9k/mac.h @@ -619,58 +619,58 @@ enum ath9k_ht_extprotspacing { ATH9K_HT_EXTPROTSPACING_25 = 1, }; -struct ath_hal; +struct ath_hw; struct ath9k_channel; struct ath_rate_table; -u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q); -bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp); -bool ath9k_hw_txstart(struct ath_hal *ah, u32 q); -u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q); -bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel); -bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q); -bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, +u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); +bool ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); +bool ath9k_hw_txstart(struct ath_hw *ah, u32 q); +u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); +bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); +bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q); +bool ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds, u32 segLen, bool firstSeg, bool lastSeg, const struct ath_desc *ds0); -void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds); -int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds); -void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds); +int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds); +void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds, u32 pktLen, enum ath9k_pkt_type type, u32 txPower, u32 keyIx, enum ath9k_key_type keyType, u32 flags); -void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds, struct ath_desc *lastds, u32 durUpdateEn, u32 rtsctsRate, u32 rtsctsDuration, struct ath9k_11n_rate_series series[], u32 nseries, u32 flags); -void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds, u32 aggrLen); -void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds, u32 numDelims); -void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); -void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds); -void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds); +void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds); +void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds, u32 burstDuration); -void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, +void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds, u32 vmf); -void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs); -bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, +void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs); +bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, const struct ath9k_tx_queue_info *qinfo); -bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, +bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, struct ath9k_tx_queue_info *qinfo); -int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, +int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, const struct ath9k_tx_queue_info *qinfo); -bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q); -bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q); -int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, +bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q); +bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q); +int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, u32 pa, struct ath_desc *nds, u64 tsf); -bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, +bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, u32 size, u32 flags); -bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set); -void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp); -void ath9k_hw_rxena(struct ath_hal *ah); -void ath9k_hw_startpcureceive(struct ath_hal *ah); -void ath9k_hw_stoppcurecv(struct ath_hal *ah); -bool ath9k_hw_stopdmarecv(struct ath_hal *ah); +bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); +void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); +void ath9k_hw_rxena(struct ath_hw *ah); +void ath9k_hw_startpcureceive(struct ath_hw *ah); +void ath9k_hw_stoppcurecv(struct ath_hw *ah); +bool ath9k_hw_stopdmarecv(struct ath_hw *ah); #endif /* MAC_H */ diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index bafefbed8382..a50f989abd6c 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c @@ -137,7 +137,7 @@ static void ath_cache_conf_rate(struct ath_softc *sc, static void ath_update_txpow(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; u32 txpow; if (sc->curtxpow != sc->config.txpowlimit) { @@ -234,7 +234,7 @@ static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band) */ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; bool fastcc = true, stopped; struct ieee80211_hw *hw = sc->hw; struct ieee80211_channel *channel = hw->conf.channel; @@ -309,7 +309,7 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan) static void ath_ani_calibrate(unsigned long data) { struct ath_softc *sc; - struct ath_hal *ah; + struct ath_hw *ah; bool longcal = false; bool shortcal = false; bool aniflag = false; @@ -479,7 +479,7 @@ static void ath9k_tasklet(unsigned long data) irqreturn_t ath_isr(int irq, void *dev) { struct ath_softc *sc = dev; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; enum ath9k_int status; bool sched = false; @@ -1091,7 +1091,7 @@ fail: static void ath_radio_enable(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ieee80211_channel *channel = sc->hw->conf.channel; int r; @@ -1132,7 +1132,7 @@ static void ath_radio_enable(struct ath_softc *sc) static void ath_radio_disable(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ieee80211_channel *channel = sc->hw->conf.channel; int r; @@ -1167,7 +1167,7 @@ static void ath_radio_disable(struct ath_softc *sc) static bool ath_is_rfkill_set(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) == ah->ah_rfkill_polarity; @@ -1345,7 +1345,7 @@ void ath_detach(struct ath_softc *sc) static int ath_init(u16 devid, struct ath_softc *sc) { - struct ath_hal *ah = NULL; + struct ath_hw *ah = NULL; int status; int error = 0, i; int csz = 0; @@ -1370,7 +1370,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) /* XXX assert csz is non-zero */ sc->cachelsz = csz << 2; /* convert to bytes */ - ah = ath9k_hw_attach(devid, sc, sc->mem, &status); + ah = ath9k_hw_attach(devid, sc, &status); if (ah == NULL) { DPRINTF(sc, ATH_DBG_FATAL, "Unable to attach hardware; HAL status %d\n", status); @@ -1671,7 +1671,7 @@ detach: int ath_reset(struct ath_softc *sc, bool retry_tx) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ieee80211_hw *hw = sc->hw; int r; @@ -2272,7 +2272,7 @@ static int ath9k_config_interface(struct ieee80211_hw *hw, struct ieee80211_if_conf *conf) { struct ath_softc *sc = hw->priv; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_vif *avp = (void *)vif->drv_priv; u32 rfilt = 0; int error, i; diff --git a/drivers/net/wireless/ath9k/pci.c b/drivers/net/wireless/ath9k/pci.c index 192c8c4e59fc..eac8db742602 100644 --- a/drivers/net/wireless/ath9k/pci.c +++ b/drivers/net/wireless/ath9k/pci.c @@ -56,7 +56,7 @@ static void ath_pci_cleanup(struct ath_softc *sc) pci_disable_device(pdev); } -static bool ath_pci_eeprom_read(struct ath_hal *ah, u32 off, u16 *data) +static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data) { (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); @@ -87,7 +87,7 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) u8 csz; u32 val; int ret = 0; - struct ath_hal *ah; + struct ath_hw *ah; if (pci_enable_device(pdev)) return -EIO; diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c index ea29941412d4..da4165b8d6be 100644 --- a/drivers/net/wireless/ath9k/phy.c +++ b/drivers/net/wireless/ath9k/phy.c @@ -17,16 +17,14 @@ #include "ath9k.h" void -ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex, +ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, int regWrites) { - struct ath_hal_5416 *ahp = AH5416(ah); - - REG_WRITE_ARRAY(&ahp->ah_iniBB_RfGain, freqIndex, regWrites); + REG_WRITE_ARRAY(&ah->ah_iniBB_RfGain, freqIndex, regWrites); } bool -ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan) +ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) { u32 channelSel = 0; u32 bModeSynth = 0; @@ -93,14 +91,13 @@ ath9k_hw_set_channel(struct ath_hal *ah, struct ath9k_channel *chan) REG_WRITE(ah, AR_PHY(0x37), reg32); ah->ah_curchan = chan; - - AH5416(ah)->ah_curchanRadIndex = -1; + ah->ah_curchanRadIndex = -1; return true; } bool -ath9k_hw_ar9280_set_channel(struct ath_hal *ah, +ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) { u16 bMode, fracMode, aModeRefSel = 0; @@ -164,8 +161,7 @@ ath9k_hw_ar9280_set_channel(struct ath_hal *ah, REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); ah->ah_curchan = chan; - - AH5416(ah)->ah_curchanRadIndex = -1; + ah->ah_curchanRadIndex = -1; return true; } @@ -198,11 +194,9 @@ ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, } bool -ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan, +ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex) { - struct ath_hal_5416 *ahp = AH5416(ah); - u32 eepMinorRev; u32 ob5GHz = 0, db5GHz = 0; u32 ob2GHz = 0, db2GHz = 0; @@ -213,19 +207,19 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan, eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV); - RF_BANK_SETUP(ahp->ah_analogBank0Data, &ahp->ah_iniBank0, 1); + RF_BANK_SETUP(ah->ah_analogBank0Data, &ah->ah_iniBank0, 1); - RF_BANK_SETUP(ahp->ah_analogBank1Data, &ahp->ah_iniBank1, 1); + RF_BANK_SETUP(ah->ah_analogBank1Data, &ah->ah_iniBank1, 1); - RF_BANK_SETUP(ahp->ah_analogBank2Data, &ahp->ah_iniBank2, 1); + RF_BANK_SETUP(ah->ah_analogBank2Data, &ah->ah_iniBank2, 1); - RF_BANK_SETUP(ahp->ah_analogBank3Data, &ahp->ah_iniBank3, + RF_BANK_SETUP(ah->ah_analogBank3Data, &ah->ah_iniBank3, modesIndex); { int i; - for (i = 0; i < ahp->ah_iniBank6TPC.ia_rows; i++) { - ahp->ah_analogBank6Data[i] = - INI_RA(&ahp->ah_iniBank6TPC, i, modesIndex); + for (i = 0; i < ah->ah_iniBank6TPC.ia_rows; i++) { + ah->ah_analogBank6Data[i] = + INI_RA(&ah->ah_iniBank6TPC, i, modesIndex); } } @@ -233,137 +227,132 @@ ath9k_hw_set_rf_regs(struct ath_hal *ah, struct ath9k_channel *chan, if (IS_CHAN_2GHZ(chan)) { ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2); db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2); - ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ob2GHz, 3, 197, 0); - ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, db2GHz, 3, 194, 0); } else { ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5); db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5); - ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ob5GHz, 3, 203, 0); - ath9k_phy_modify_rx_buffer(ahp->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, db5GHz, 3, 200, 0); } } - RF_BANK_SETUP(ahp->ah_analogBank7Data, &ahp->ah_iniBank7, 1); + RF_BANK_SETUP(ah->ah_analogBank7Data, &ah->ah_iniBank7, 1); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank0, ahp->ah_analogBank0Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank0, ah->ah_analogBank0Data, regWrites); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank1, ahp->ah_analogBank1Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank1, ah->ah_analogBank1Data, regWrites); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank2, ahp->ah_analogBank2Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank2, ah->ah_analogBank2Data, regWrites); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank3, ahp->ah_analogBank3Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank3, ah->ah_analogBank3Data, regWrites); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6TPC, ahp->ah_analogBank6Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank6TPC, ah->ah_analogBank6Data, regWrites); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank7, ahp->ah_analogBank7Data, + REG_WRITE_RF_ARRAY(&ah->ah_iniBank7, ah->ah_analogBank7Data, regWrites); return true; } void -ath9k_hw_rfdetach(struct ath_hal *ah) +ath9k_hw_rfdetach(struct ath_hw *ah) { - struct ath_hal_5416 *ahp = AH5416(ah); - - if (ahp->ah_analogBank0Data != NULL) { - kfree(ahp->ah_analogBank0Data); - ahp->ah_analogBank0Data = NULL; + if (ah->ah_analogBank0Data != NULL) { + kfree(ah->ah_analogBank0Data); + ah->ah_analogBank0Data = NULL; } - if (ahp->ah_analogBank1Data != NULL) { - kfree(ahp->ah_analogBank1Data); - ahp->ah_analogBank1Data = NULL; + if (ah->ah_analogBank1Data != NULL) { + kfree(ah->ah_analogBank1Data); + ah->ah_analogBank1Data = NULL; } - if (ahp->ah_analogBank2Data != NULL) { - kfree(ahp->ah_analogBank2Data); - ahp->ah_analogBank2Data = NULL; + if (ah->ah_analogBank2Data != NULL) { + kfree(ah->ah_analogBank2Data); + ah->ah_analogBank2Data = NULL; } - if (ahp->ah_analogBank3Data != NULL) { - kfree(ahp->ah_analogBank3Data); - ahp->ah_analogBank3Data = NULL; + if (ah->ah_analogBank3Data != NULL) { + kfree(ah->ah_analogBank3Data); + ah->ah_analogBank3Data = NULL; } - if (ahp->ah_analogBank6Data != NULL) { - kfree(ahp->ah_analogBank6Data); - ahp->ah_analogBank6Data = NULL; + if (ah->ah_analogBank6Data != NULL) { + kfree(ah->ah_analogBank6Data); + ah->ah_analogBank6Data = NULL; } - if (ahp->ah_analogBank6TPCData != NULL) { - kfree(ahp->ah_analogBank6TPCData); - ahp->ah_analogBank6TPCData = NULL; + if (ah->ah_analogBank6TPCData != NULL) { + kfree(ah->ah_analogBank6TPCData); + ah->ah_analogBank6TPCData = NULL; } - if (ahp->ah_analogBank7Data != NULL) { - kfree(ahp->ah_analogBank7Data); - ahp->ah_analogBank7Data = NULL; + if (ah->ah_analogBank7Data != NULL) { + kfree(ah->ah_analogBank7Data); + ah->ah_analogBank7Data = NULL; } - if (ahp->ah_addac5416_21 != NULL) { - kfree(ahp->ah_addac5416_21); - ahp->ah_addac5416_21 = NULL; + if (ah->ah_addac5416_21 != NULL) { + kfree(ah->ah_addac5416_21); + ah->ah_addac5416_21 = NULL; } - if (ahp->ah_bank6Temp != NULL) { - kfree(ahp->ah_bank6Temp); - ahp->ah_bank6Temp = NULL; + if (ah->ah_bank6Temp != NULL) { + kfree(ah->ah_bank6Temp); + ah->ah_bank6Temp = NULL; } } -bool ath9k_hw_init_rf(struct ath_hal *ah, int *status) +bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) { - struct ath_hal_5416 *ahp = AH5416(ah); - if (!AR_SREV_9280_10_OR_LATER(ah)) { - - ahp->ah_analogBank0Data = + ah->ah_analogBank0Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank0.ia_rows), GFP_KERNEL); - ahp->ah_analogBank1Data = + ah->ah_iniBank0.ia_rows), GFP_KERNEL); + ah->ah_analogBank1Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank1.ia_rows), GFP_KERNEL); - ahp->ah_analogBank2Data = + ah->ah_iniBank1.ia_rows), GFP_KERNEL); + ah->ah_analogBank2Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank2.ia_rows), GFP_KERNEL); - ahp->ah_analogBank3Data = + ah->ah_iniBank2.ia_rows), GFP_KERNEL); + ah->ah_analogBank3Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank3.ia_rows), GFP_KERNEL); - ahp->ah_analogBank6Data = + ah->ah_iniBank3.ia_rows), GFP_KERNEL); + ah->ah_analogBank6Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank6.ia_rows), GFP_KERNEL); - ahp->ah_analogBank6TPCData = + ah->ah_iniBank6.ia_rows), GFP_KERNEL); + ah->ah_analogBank6TPCData = kzalloc((sizeof(u32) * - ahp->ah_iniBank6TPC.ia_rows), GFP_KERNEL); - ahp->ah_analogBank7Data = + ah->ah_iniBank6TPC.ia_rows), GFP_KERNEL); + ah->ah_analogBank7Data = kzalloc((sizeof(u32) * - ahp->ah_iniBank7.ia_rows), GFP_KERNEL); - - if (ahp->ah_analogBank0Data == NULL - || ahp->ah_analogBank1Data == NULL - || ahp->ah_analogBank2Data == NULL - || ahp->ah_analogBank3Data == NULL - || ahp->ah_analogBank6Data == NULL - || ahp->ah_analogBank6TPCData == NULL - || ahp->ah_analogBank7Data == NULL) { + ah->ah_iniBank7.ia_rows), GFP_KERNEL); + + if (ah->ah_analogBank0Data == NULL + || ah->ah_analogBank1Data == NULL + || ah->ah_analogBank2Data == NULL + || ah->ah_analogBank3Data == NULL + || ah->ah_analogBank6Data == NULL + || ah->ah_analogBank6TPCData == NULL + || ah->ah_analogBank7Data == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Cannot allocate RF banks\n"); *status = -ENOMEM; return false; } - ahp->ah_addac5416_21 = + ah->ah_addac5416_21 = kzalloc((sizeof(u32) * - ahp->ah_iniAddac.ia_rows * - ahp->ah_iniAddac.ia_columns), GFP_KERNEL); - if (ahp->ah_addac5416_21 == NULL) { + ah->ah_iniAddac.ia_rows * + ah->ah_iniAddac.ia_columns), GFP_KERNEL); + if (ah->ah_addac5416_21 == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Cannot allocate ah_addac5416_21\n"); *status = -ENOMEM; return false; } - ahp->ah_bank6Temp = + ah->ah_bank6Temp = kzalloc((sizeof(u32) * - ahp->ah_iniBank6.ia_rows), GFP_KERNEL); - if (ahp->ah_bank6Temp == NULL) { + ah->ah_iniBank6.ia_rows), GFP_KERNEL); + if (ah->ah_bank6Temp == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Cannot allocate ah_bank6Temp\n"); *status = -ENOMEM; @@ -375,23 +364,22 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, int *status) } void -ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan) +ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) { int i, regWrites = 0; - struct ath_hal_5416 *ahp = AH5416(ah); u32 bank6SelMask; - u32 *bank6Temp = ahp->ah_bank6Temp; + u32 *bank6Temp = ah->ah_bank6Temp; - switch (ahp->ah_diversityControl) { + switch (ah->ah_diversityControl) { case ATH9K_ANT_FIXED_A: bank6SelMask = - (ahp-> + (ah-> ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : REDUCE_CHAIN_1; break; case ATH9K_ANT_FIXED_B: bank6SelMask = - (ahp-> + (ah-> ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : REDUCE_CHAIN_0; break; @@ -403,8 +391,8 @@ ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan) break; } - for (i = 0; i < ahp->ah_iniBank6.ia_rows; i++) - bank6Temp[i] = ahp->ah_analogBank6Data[i]; + for (i = 0; i < ah->ah_iniBank6.ia_rows; i++) + bank6Temp[i] = ah->ah_analogBank6Data[i]; REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); @@ -418,7 +406,7 @@ ath9k_hw_decrease_chain_power(struct ath_hal *ah, struct ath9k_channel *chan) ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0); ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0); - REG_WRITE_RF_ARRAY(&ahp->ah_iniBank6, bank6Temp, regWrites); + REG_WRITE_RF_ARRAY(&ah->ah_iniBank6, bank6Temp, regWrites); REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); #ifdef ALTER_SWITCH diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h index 3a406a5c0593..71a7f5af7004 100644 --- a/drivers/net/wireless/ath9k/phy.h +++ b/drivers/net/wireless/ath9k/phy.h @@ -17,19 +17,19 @@ #ifndef PHY_H #define PHY_H -bool ath9k_hw_ar9280_set_channel(struct ath_hal *ah, +bool ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan); -bool ath9k_hw_set_channel(struct ath_hal *ah, +bool ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan); -void ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, +void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, int regWrites); -bool ath9k_hw_set_rf_regs(struct ath_hal *ah, +bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, u16 modesIndex); -void ath9k_hw_decrease_chain_power(struct ath_hal *ah, +void ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan); -bool ath9k_hw_init_rf(struct ath_hal *ah, +bool ath9k_hw_init_rf(struct ath_hw *ah, int *status); #define AR_PHY_BASE 0x9800 @@ -533,7 +533,7 @@ bool ath9k_hw_init_rf(struct ath_hal *ah, #define ATH9K_KEY_XOR 0xaa #define ATH9K_IS_MIC_ENABLED(ah) \ - (AH5416(ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) + ((ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) #define ANTSWAP_AB 0x0001 #define REDUCE_CHAIN_0 0x00000050 diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c index c51c085f55d6..7c011b1ba333 100644 --- a/drivers/net/wireless/ath9k/recv.c +++ b/drivers/net/wireless/ath9k/recv.c @@ -26,7 +26,7 @@ */ static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_desc *ds; struct sk_buff *skb; @@ -233,7 +233,7 @@ rx_next: static void ath_opmode_init(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; u32 rfilt, mfilt[2]; /* configure rx filter */ @@ -391,7 +391,7 @@ u32 ath_calcrxfilter(struct ath_softc *sc) int ath_startrecv(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_buf *bf, *tbf; spin_lock_bh(&sc->rx.rxbuflock); @@ -421,7 +421,7 @@ start_recv: bool ath_stoprecv(struct ath_softc *sc) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; bool stopped; ath9k_hw_stoppcurecv(ah); @@ -452,7 +452,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush) struct ath_desc *ds; struct sk_buff *skb = NULL, *requeue_skb; struct ieee80211_rx_status rx_status; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ieee80211_hdr *hdr; int hdrlen, padsize, retval; bool decrypt_error = false; diff --git a/drivers/net/wireless/ath9k/regd.c b/drivers/net/wireless/ath9k/regd.c index 32dd0cb34490..8c2b56ac55ff 100644 --- a/drivers/net/wireless/ath9k/regd.c +++ b/drivers/net/wireless/ath9k/regd.c @@ -106,17 +106,17 @@ static const struct ieee80211_regdomain ath9k_world_regdom_67_68_6A = { } }; -static u16 ath9k_regd_get_eepromRD(struct ath_hal *ah) +static u16 ath9k_regd_get_eepromRD(struct ath_hw *ah) { return ah->regulatory.current_rd & ~WORLDWIDE_ROAMING_FLAG; } -u16 ath9k_regd_get_rd(struct ath_hal *ah) +u16 ath9k_regd_get_rd(struct ath_hw *ah) { return ath9k_regd_get_eepromRD(ah); } -bool ath9k_is_world_regd(struct ath_hal *ah) +bool ath9k_is_world_regd(struct ath_hw *ah) { return isWwrSKU(ah); } @@ -127,7 +127,7 @@ const struct ieee80211_regdomain *ath9k_default_world_regdomain(void) return &ath9k_world_regdom_64; } -const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah) +const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hw *ah) { switch (ah->regulatory.regpair->regDmnEnum) { case 0x60: @@ -282,7 +282,7 @@ void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby) { struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); struct ath_softc *sc = hw->priv; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; switch (ah->regulatory.regpair->regDmnEnum) { case 0x60: @@ -322,7 +322,7 @@ int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) return 0; } -bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah) +bool ath9k_regd_is_eeprom_valid(struct ath_hw *ah) { u16 rd = ath9k_regd_get_eepromRD(ah); int i; @@ -371,7 +371,7 @@ ath9k_regd_find_country_by_rd(int regdmn) } /* Returns the map of the EEPROM set RD to a country code */ -static u16 ath9k_regd_get_default_country(struct ath_hal *ah) +static u16 ath9k_regd_get_default_country(struct ath_hw *ah) { u16 rd; @@ -402,7 +402,7 @@ ath9k_get_regpair(int regdmn) return NULL; } -int ath9k_regd_init(struct ath_hal *ah) +int ath9k_regd_init(struct ath_hw *ah) { struct country_code_to_enum_rd *country = NULL; int regdmn; @@ -462,7 +462,7 @@ int ath9k_regd_init(struct ath_hal *ah) return 0; } -u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan) +u32 ath9k_regd_get_ctl(struct ath_hw *ah, struct ath9k_channel *chan) { u32 ctl = NO_CTL; diff --git a/drivers/net/wireless/ath9k/regd.h b/drivers/net/wireless/ath9k/regd.h index 65abdf46115d..39420de818f8 100644 --- a/drivers/net/wireless/ath9k/regd.h +++ b/drivers/net/wireless/ath9k/regd.h @@ -239,17 +239,17 @@ enum CountryCode { CTRY_BELGIUM2 = 5002 }; -u16 ath9k_regd_get_rd(struct ath_hal *ah); -bool ath9k_is_world_regd(struct ath_hal *ah); -const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah); +u16 ath9k_regd_get_rd(struct ath_hw *ah); +bool ath9k_is_world_regd(struct ath_hw *ah); +const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hw *ah); const struct ieee80211_regdomain *ath9k_default_world_regdomain(void); void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby); void ath9k_reg_apply_radar_flags(struct wiphy *wiphy); -int ath9k_regd_init(struct ath_hal *ah); -bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah); -u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan); +int ath9k_regd_init(struct ath_hw *ah); +bool ath9k_regd_is_eeprom_valid(struct ath_hw *ah); +u32 ath9k_regd_get_ctl(struct ath_hw *ah, struct ath9k_channel *chan); int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request); -void ath9k_regd_get_current_country(struct ath_hal *ah, +void ath9k_regd_get_current_country(struct ath_hw *ah, struct ath9k_country_entry *ctry); #endif diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c index 777376094a4a..3fff3344b2ee 100644 --- a/drivers/net/wireless/ath9k/xmit.c +++ b/drivers/net/wireless/ath9k/xmit.c @@ -809,7 +809,7 @@ static void ath_txq_drain_pending_buffers(struct ath_softc *sc, struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath9k_tx_queue_info qi; int qnum; @@ -926,7 +926,7 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) int ath_txq_update(struct ath_softc *sc, int qnum, struct ath9k_tx_queue_info *qinfo) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; int error = 0; struct ath9k_tx_queue_info qi; @@ -1047,7 +1047,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_txq *txq; int i, npend = 0; @@ -1165,7 +1165,7 @@ int ath_tx_setup(struct ath_softc *sc, int haltype) static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, struct list_head *head) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_buf *bf; /* @@ -1580,7 +1580,7 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, struct list_head bf_head; struct ath_desc *ds; struct ath_atx_tid *tid; - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; int frm_type; frm_type = get_hw_packet_type(skb); @@ -1879,7 +1879,7 @@ static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) { - struct ath_hal *ah = sc->sc_ah; + struct ath_hw *ah = sc->sc_ah; struct ath_buf *bf, *lastbf, *bf_held = NULL; struct list_head bf_head; struct ath_desc *ds; -- cgit v1.2.3 From e153789dc3846b35494435b4a8ae82a034c99dae Mon Sep 17 00:00:00 2001 From: Sujith Date: Mon, 9 Feb 2009 13:27:15 +0530 Subject: ath9k: Add callbacks hooks for EEPROM operations This is preparatory work for removing the individual function pointer assignments in eeprom.c Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/eeprom.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 81a7a708bc85..47c8eea85e83 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -447,6 +447,23 @@ enum hal_eep_map { EEP_MAP_MAX }; +struct eeprom_ops { + int (*check_eeprom)(struct ath_hw *hw); + u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); + bool (*fill_eeprom)(struct ath_hw *hw); + int (*get_eeprom_ver)(struct ath_hw *hw); + int (*get_eeprom_rev)(struct ath_hw *hw); + u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band); + u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw, + struct ath9k_channel *chan); + bool (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); + void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); + int (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, + u16 cfgCtl, u8 twiceAntennaReduction, + u8 twiceMaxRegulatoryPower, u8 powerLimit); + u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); +}; + #define ar5416_get_eep_ver(_ah) \ (((_ah)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) #define ar5416_get_eep_rev(_ah) \ -- cgit v1.2.3 From f74df6fbe31561091bf42be0ed30232be2b9d3ac Mon Sep 17 00:00:00 2001 From: Sujith Date: Mon, 9 Feb 2009 13:27:24 +0530 Subject: ath9k: Cleanup EEPROM operations This patch removes the various function pointer assignments and unifies them in a single ops structure. Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/calib.c | 4 +- drivers/net/wireless/ath9k/eeprom.c | 3912 +++++++++++++++++------------------ drivers/net/wireless/ath9k/eeprom.h | 30 +- drivers/net/wireless/ath9k/hw.c | 72 +- drivers/net/wireless/ath9k/hw.h | 1 + drivers/net/wireless/ath9k/phy.c | 10 +- 6 files changed, 1995 insertions(+), 2034 deletions(-) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c index 8c44d5a439e7..7e70a81e21de 100644 --- a/drivers/net/wireless/ath9k/calib.c +++ b/drivers/net/wireless/ath9k/calib.c @@ -172,10 +172,10 @@ static bool getNoiseFloorThresh(struct ath_hw *ah, { switch (band) { case IEEE80211_BAND_5GHZ: - *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_5); + *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5); break; case IEEE80211_BAND_2GHZ: - *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_2); + *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2); break; default: BUG_ON(1); diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index 94e79938b93a..2e604e1fb3e1 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -95,7 +95,188 @@ static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data) return sc->bus_ops->eeprom_read(ah, off, data); } -static bool ath9k_hw_fill_4k_eeprom(struct ath_hw *ah) +static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, + u8 *pVpdList, u16 numIntercepts, + u8 *pRetVpdList) +{ + u16 i, k; + u8 currPwr = pwrMin; + u16 idxL = 0, idxR = 0; + + for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { + ath9k_hw_get_lower_upper_index(currPwr, pPwrList, + numIntercepts, &(idxL), + &(idxR)); + if (idxR < 1) + idxR = 1; + if (idxL == numIntercepts - 1) + idxL = (u16) (numIntercepts - 2); + if (pPwrList[idxL] == pPwrList[idxR]) + k = pVpdList[idxL]; + else + k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] + + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / + (pPwrList[idxR] - pPwrList[idxL])); + pRetVpdList[i] = (u8) k; + currPwr += 2; + } + + return true; +} + +static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, + struct ath9k_channel *chan, + struct cal_target_power_leg *powInfo, + u16 numChannels, + struct cal_target_power_leg *pNewPower, + u16 numRates, bool isExtTarget) +{ + struct chan_centers centers; + u16 clo, chi; + int i; + int matchIndex = -1, lowIndex = -1; + u16 freq; + + ath9k_hw_get_channel_centers(ah, chan, ¢ers); + freq = (isExtTarget) ? centers.ext_center : centers.ctl_center; + + if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, + IS_CHAN_2GHZ(chan))) { + matchIndex = 0; + } else { + for (i = 0; (i < numChannels) && + (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { + if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, + IS_CHAN_2GHZ(chan))) { + matchIndex = i; + break; + } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, + IS_CHAN_2GHZ(chan))) && + (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, + IS_CHAN_2GHZ(chan)))) { + lowIndex = i - 1; + break; + } + } + if ((matchIndex == -1) && (lowIndex == -1)) + matchIndex = i - 1; + } + + if (matchIndex != -1) { + *pNewPower = powInfo[matchIndex]; + } else { + clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, + IS_CHAN_2GHZ(chan)); + chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, + IS_CHAN_2GHZ(chan)); + + for (i = 0; i < numRates; i++) { + pNewPower->tPow2x[i] = + (u8)ath9k_hw_interpolate(freq, clo, chi, + powInfo[lowIndex].tPow2x[i], + powInfo[lowIndex + 1].tPow2x[i]); + } + } +} + +static void ath9k_hw_get_target_powers(struct ath_hw *ah, + struct ath9k_channel *chan, + struct cal_target_power_ht *powInfo, + u16 numChannels, + struct cal_target_power_ht *pNewPower, + u16 numRates, bool isHt40Target) +{ + struct chan_centers centers; + u16 clo, chi; + int i; + int matchIndex = -1, lowIndex = -1; + u16 freq; + + ath9k_hw_get_channel_centers(ah, chan, ¢ers); + freq = isHt40Target ? centers.synth_center : centers.ctl_center; + + if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { + matchIndex = 0; + } else { + for (i = 0; (i < numChannels) && + (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { + if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, + IS_CHAN_2GHZ(chan))) { + matchIndex = i; + break; + } else + if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, + IS_CHAN_2GHZ(chan))) && + (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, + IS_CHAN_2GHZ(chan)))) { + lowIndex = i - 1; + break; + } + } + if ((matchIndex == -1) && (lowIndex == -1)) + matchIndex = i - 1; + } + + if (matchIndex != -1) { + *pNewPower = powInfo[matchIndex]; + } else { + clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, + IS_CHAN_2GHZ(chan)); + chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, + IS_CHAN_2GHZ(chan)); + + for (i = 0; i < numRates; i++) { + pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq, + clo, chi, + powInfo[lowIndex].tPow2x[i], + powInfo[lowIndex + 1].tPow2x[i]); + } + } +} + +static u16 ath9k_hw_get_max_edge_power(u16 freq, + struct cal_ctl_edges *pRdEdgesPower, + bool is2GHz, int num_band_edges) +{ + u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; + int i; + + for (i = 0; (i < num_band_edges) && + (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { + if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { + twiceMaxEdgePower = pRdEdgesPower[i].tPower; + break; + } else if ((i > 0) && + (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, + is2GHz))) { + if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel, + is2GHz) < freq && + pRdEdgesPower[i - 1].flag) { + twiceMaxEdgePower = + pRdEdgesPower[i - 1].tPower; + } + break; + } + } + + return twiceMaxEdgePower; +} + +/****************************************/ +/* EEPROM Operations for 4K sized cards */ +/****************************************/ + +static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) +{ + return ((ah->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF); +} + +static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah) +{ + return ((ah->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF); +} + +static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) { #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; @@ -123,56 +304,26 @@ static bool ath9k_hw_fill_4k_eeprom(struct ath_hw *ah) #undef SIZE_EEPROM_4K } -static bool ath9k_hw_fill_def_eeprom(struct ath_hw *ah) -{ -#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; - u16 *eep_data; - int addr, ar5416_eep_start_loc = 0x100; - - eep_data = (u16 *)eep; - - for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { - if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, - eep_data)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Unable to read eeprom region\n"); - return false; - } - eep_data++; - } - return true; -#undef SIZE_EEPROM_DEF -} - -static bool (*ath9k_fill_eeprom[]) (struct ath_hw *) = { - ath9k_hw_fill_def_eeprom, - ath9k_hw_fill_4k_eeprom -}; - -static inline bool ath9k_hw_fill_eeprom(struct ath_hw *ah) -{ - return ath9k_fill_eeprom[ah->ah_eep_map](ah); -} - -static int ath9k_hw_check_def_eeprom(struct ath_hw *ah) +static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) { - struct ar5416_eeprom_def *eep = - (struct ar5416_eeprom_def *) &ah->ah_eeprom.def; +#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) + struct ar5416_eeprom_4k *eep = + (struct ar5416_eeprom_4k *) &ah->ah_eeprom.map4k; u16 *eepdata, temp, magic, magic2; u32 sum = 0, el; bool need_swap = false; - int i, addr, size; + int i, addr; - if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, - &magic)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Reading Magic # failed\n"); - return false; - } if (!ath9k_hw_use_flash(ah)) { + if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, + &magic)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Reading Magic # failed\n"); + return false; + } + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "Read Magic = 0x%04X\n", magic); @@ -180,11 +331,10 @@ static int ath9k_hw_check_def_eeprom(struct ath_hw *ah) magic2 = swab16(magic); if (magic2 == AR5416_EEPROM_MAGIC) { - size = sizeof(struct ar5416_eeprom_def); need_swap = true; eepdata = (u16 *) (&ah->ah_eeprom); - for (addr = 0; addr < size / sizeof(u16); addr++) { + for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { temp = swab16(*eepdata); *eepdata = temp; eepdata++; @@ -209,12 +359,12 @@ static int ath9k_hw_check_def_eeprom(struct ath_hw *ah) need_swap ? "True" : "False"); if (need_swap) - el = swab16(ah->ah_eeprom.def.baseEepHeader.length); + el = swab16(ah->ah_eeprom.map4k.baseEepHeader.length); else - el = ah->ah_eeprom.def.baseEepHeader.length; + el = ah->ah_eeprom.map4k.baseEepHeader.length; if (el > sizeof(struct ar5416_eeprom_def)) - el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); + el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); else el = el / sizeof(u16); @@ -224,7 +374,7 @@ static int ath9k_hw_check_def_eeprom(struct ath_hw *ah) sum ^= *eepdata++; if (need_swap) { - u32 integer, j; + u32 integer; u16 word; DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, @@ -254,198 +404,71 @@ static int ath9k_hw_check_def_eeprom(struct ath_hw *ah) word = swab16(eep->baseEepHeader.deviceCap); eep->baseEepHeader.deviceCap = word; - for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { - struct modal_eep_header *pModal = - &eep->modalHeader[j]; - integer = swab32(pModal->antCtrlCommon); - pModal->antCtrlCommon = integer; + integer = swab32(eep->modalHeader.antCtrlCommon); + eep->modalHeader.antCtrlCommon = integer; - for (i = 0; i < AR5416_MAX_CHAINS; i++) { - integer = swab32(pModal->antCtrlChain[i]); - pModal->antCtrlChain[i] = integer; - } + for (i = 0; i < AR5416_MAX_CHAINS; i++) { + integer = swab32(eep->modalHeader.antCtrlChain[i]); + eep->modalHeader.antCtrlChain[i] = integer; + } - for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { - word = swab16(pModal->spurChans[i].spurChan); - pModal->spurChans[i].spurChan = word; - } + for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { + word = swab16(eep->modalHeader.spurChans[i].spurChan); + eep->modalHeader.spurChans[i].spurChan = word; } } - if (sum != 0xffff || ar5416_get_eep_ver(ah) != AR5416_EEP_VER || - ar5416_get_eep_rev(ah) < AR5416_EEP_NO_BACK_VER) { + if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || + ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", - sum, ar5416_get_eep_ver(ah)); + sum, ah->eep_ops->get_eeprom_ver(ah)); return -EINVAL; } return 0; +#undef EEPROM_4K_SIZE } -static int ath9k_hw_check_4k_eeprom(struct ath_hw *ah) +static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, + enum eeprom_param param) { -#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) - struct ar5416_eeprom_4k *eep = - (struct ar5416_eeprom_4k *) &ah->ah_eeprom.map4k; - u16 *eepdata, temp, magic, magic2; - u32 sum = 0, el; - bool need_swap = false; - int i, addr; - - - if (!ath9k_hw_use_flash(ah)) { - - if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, - &magic)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Reading Magic # failed\n"); - return false; - } - - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Read Magic = 0x%04X\n", magic); - - if (magic != AR5416_EEPROM_MAGIC) { - magic2 = swab16(magic); - - if (magic2 == AR5416_EEPROM_MAGIC) { - need_swap = true; - eepdata = (u16 *) (&ah->ah_eeprom); - - for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { - temp = swab16(*eepdata); - *eepdata = temp; - eepdata++; - - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "0x%04X ", *eepdata); - - if (((addr + 1) % 6) == 0) - DPRINTF(ah->ah_sc, - ATH_DBG_EEPROM, "\n"); - } - } else { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Invalid EEPROM Magic. " - "endianness mismatch.\n"); - return -EINVAL; - } - } - } - - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", - need_swap ? "True" : "False"); - - if (need_swap) - el = swab16(ah->ah_eeprom.map4k.baseEepHeader.length); - else - el = ah->ah_eeprom.map4k.baseEepHeader.length; - - if (el > sizeof(struct ar5416_eeprom_def)) - el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); - else - el = el / sizeof(u16); - - eepdata = (u16 *)(&ah->ah_eeprom); - - for (i = 0; i < el; i++) - sum ^= *eepdata++; - - if (need_swap) { - u32 integer; - u16 word; - - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "EEPROM Endianness is not native.. Changing \n"); - - word = swab16(eep->baseEepHeader.length); - eep->baseEepHeader.length = word; - - word = swab16(eep->baseEepHeader.checksum); - eep->baseEepHeader.checksum = word; - - word = swab16(eep->baseEepHeader.version); - eep->baseEepHeader.version = word; - - word = swab16(eep->baseEepHeader.regDmn[0]); - eep->baseEepHeader.regDmn[0] = word; - - word = swab16(eep->baseEepHeader.regDmn[1]); - eep->baseEepHeader.regDmn[1] = word; - - word = swab16(eep->baseEepHeader.rfSilent); - eep->baseEepHeader.rfSilent = word; - - word = swab16(eep->baseEepHeader.blueToothOptions); - eep->baseEepHeader.blueToothOptions = word; - - word = swab16(eep->baseEepHeader.deviceCap); - eep->baseEepHeader.deviceCap = word; - - integer = swab32(eep->modalHeader.antCtrlCommon); - eep->modalHeader.antCtrlCommon = integer; - - for (i = 0; i < AR5416_MAX_CHAINS; i++) { - integer = swab32(eep->modalHeader.antCtrlChain[i]); - eep->modalHeader.antCtrlChain[i] = integer; - } - - for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { - word = swab16(eep->modalHeader.spurChans[i].spurChan); - eep->modalHeader.spurChans[i].spurChan = word; - } - } - - if (sum != 0xffff || ar5416_get_eep4k_ver(ah) != AR5416_EEP_VER || - ar5416_get_eep4k_rev(ah) < AR5416_EEP_NO_BACK_VER) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "Bad EEPROM checksum 0x%x or revision 0x%04x\n", - sum, ar5416_get_eep4k_ver(ah)); - return -EINVAL; - } - - return 0; -#undef EEPROM_4K_SIZE -} - -static int (*ath9k_check_eeprom[]) (struct ath_hw *) = { - ath9k_hw_check_def_eeprom, - ath9k_hw_check_4k_eeprom -}; - -static inline int ath9k_hw_check_eeprom(struct ath_hw *ah) -{ - return ath9k_check_eeprom[ah->ah_eep_map](ah); -} - -static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, - u8 *pVpdList, u16 numIntercepts, - u8 *pRetVpdList) -{ - u16 i, k; - u8 currPwr = pwrMin; - u16 idxL = 0, idxR = 0; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct modal_eep_4k_header *pModal = &eep->modalHeader; + struct base_eep_header_4k *pBase = &eep->baseEepHeader; - for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { - ath9k_hw_get_lower_upper_index(currPwr, pPwrList, - numIntercepts, &(idxL), - &(idxR)); - if (idxR < 1) - idxR = 1; - if (idxL == numIntercepts - 1) - idxL = (u16) (numIntercepts - 2); - if (pPwrList[idxL] == pPwrList[idxR]) - k = pVpdList[idxL]; - else - k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] + - (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / - (pPwrList[idxR] - pPwrList[idxL])); - pRetVpdList[i] = (u8) k; - currPwr += 2; + switch (param) { + case EEP_NFTHRESH_2: + return pModal[1].noiseFloorThreshCh[0]; + case AR_EEPROM_MAC(0): + return pBase->macAddr[0] << 8 | pBase->macAddr[1]; + case AR_EEPROM_MAC(1): + return pBase->macAddr[2] << 8 | pBase->macAddr[3]; + case AR_EEPROM_MAC(2): + return pBase->macAddr[4] << 8 | pBase->macAddr[5]; + case EEP_REG_0: + return pBase->regDmn[0]; + case EEP_REG_1: + return pBase->regDmn[1]; + case EEP_OP_CAP: + return pBase->deviceCap; + case EEP_OP_MODE: + return pBase->opCapFlags; + case EEP_RF_SILENT: + return pBase->rfSilent; + case EEP_OB_2: + return pModal->ob_01; + case EEP_DB_2: + return pModal->db1_01; + case EEP_MINOR_REV: + return pBase->version & AR5416_EEP_VER_MINOR_MASK; + case EEP_TX_MASK: + return pBase->txMask; + case EEP_RX_MASK: + return pBase->rxMask; + default: + return 0; } - - return true; } static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, @@ -616,1355 +639,1218 @@ static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah, #undef TMP_VAL_VPD_TABLE } -static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah, - struct ath9k_channel *chan, - struct cal_data_per_freq *pRawDataSet, - u8 *bChans, u16 availPiers, - u16 tPdGainOverlap, int16_t *pMinCalPower, - u16 *pPdGainBoundaries, u8 *pPDADCValues, - u16 numXpdGains) +static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, + struct ath9k_channel *chan, + int16_t *pTxPowerIndexOffset) { - int i, j, k; - int16_t ss; - u16 idxL = 0, idxR = 0, numPiers; - static u8 vpdTableL[AR5416_NUM_PD_GAINS] - [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; - static u8 vpdTableR[AR5416_NUM_PD_GAINS] - [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; - static u8 vpdTableI[AR5416_NUM_PD_GAINS] - [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; - - u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; - u8 minPwrT4[AR5416_NUM_PD_GAINS]; - u8 maxPwrT4[AR5416_NUM_PD_GAINS]; - int16_t vpdStep; - int16_t tmpVal; - u16 sizeCurrVpdTable, maxIndex, tgtIndex; - bool match; - int16_t minDelta = 0; - struct chan_centers centers; + struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; + struct cal_data_per_freq_4k *pRawDataset; + u8 *pCalBChans = NULL; + u16 pdGainOverlap_t2; + static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; + u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; + u16 numPiers, i, j; + int16_t tMinCalPower; + u16 numXpdGain, xpdMask; + u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; + u32 reg32, regOffset, regChainOffset; - ath9k_hw_get_channel_centers(ah, chan, ¢ers); + xpdMask = pEepData->modalHeader.xpdGain; - for (numPiers = 0; numPiers < availPiers; numPiers++) { - if (bChans[numPiers] == AR5416_BCHAN_UNUSED) - break; + if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= + AR5416_EEP_MINOR_VER_2) { + pdGainOverlap_t2 = + pEepData->modalHeader.pdGainOverlap; + } else { + pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), + AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); } - match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center, - IS_CHAN_2GHZ(chan)), - bChans, numPiers, &idxL, &idxR); + pCalBChans = pEepData->calFreqPier2G; + numPiers = AR5416_NUM_2G_CAL_PIERS; - if (match) { - for (i = 0; i < numXpdGains; i++) { - minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; - maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], - pRawDataSet[idxL].pwrPdg[i], - pRawDataSet[idxL].vpdPdg[i], - AR5416_PD_GAIN_ICEPTS, - vpdTableI[i]); - } - } else { - for (i = 0; i < numXpdGains; i++) { - pVpdL = pRawDataSet[idxL].vpdPdg[i]; - pPwrL = pRawDataSet[idxL].pwrPdg[i]; - pVpdR = pRawDataSet[idxR].vpdPdg[i]; - pPwrR = pRawDataSet[idxR].pwrPdg[i]; - - minPwrT4[i] = max(pPwrL[0], pPwrR[0]); - - maxPwrT4[i] = - min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], - pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); - - - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], - pPwrL, pVpdL, - AR5416_PD_GAIN_ICEPTS, - vpdTableL[i]); - ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], - pPwrR, pVpdR, - AR5416_PD_GAIN_ICEPTS, - vpdTableR[i]); + numXpdGain = 0; - for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { - vpdTableI[i][j] = - (u8)(ath9k_hw_interpolate((u16) - FREQ2FBIN(centers. - synth_center, - IS_CHAN_2GHZ - (chan)), - bChans[idxL], bChans[idxR], - vpdTableL[i][j], vpdTableR[i][j])); - } + for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { + if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { + if (numXpdGain >= AR5416_NUM_PD_GAINS) + break; + xpdGainValues[numXpdGain] = + (u16)(AR5416_PD_GAINS_IN_MASK - i); + numXpdGain++; } } - *pMinCalPower = (int16_t)(minPwrT4[0] / 2); - - k = 0; - - for (i = 0; i < numXpdGains; i++) { - if (i == (numXpdGains - 1)) - pPdGainBoundaries[i] = - (u16)(maxPwrT4[i] / 2); - else - pPdGainBoundaries[i] = - (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); - - pPdGainBoundaries[i] = - min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, + (numXpdGain - 1) & 0x3); + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, + xpdGainValues[0]); + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, + xpdGainValues[1]); + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, + xpdGainValues[2]); - if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { - minDelta = pPdGainBoundaries[0] - 23; - pPdGainBoundaries[0] = 23; - } else { - minDelta = 0; - } + for (i = 0; i < AR5416_MAX_CHAINS; i++) { + if (AR_SREV_5416_V20_OR_LATER(ah) && + (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && + (i != 0)) { + regChainOffset = (i == 1) ? 0x2000 : 0x1000; + } else + regChainOffset = i * 0x1000; - if (i == 0) { - if (AR_SREV_9280_10_OR_LATER(ah)) - ss = (int16_t)(0 - (minPwrT4[i] / 2)); - else - ss = 0; - } else { - ss = (int16_t)((pPdGainBoundaries[i - 1] - - (minPwrT4[i] / 2)) - - tPdGainOverlap + 1 + minDelta); - } - vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); - vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); + if (pEepData->baseEepHeader.txMask & (1 << i)) { + pRawDataset = pEepData->calPierData2G[i]; - while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { - tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); - pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); - ss++; - } + ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan, + pRawDataset, pCalBChans, + numPiers, pdGainOverlap_t2, + &tMinCalPower, gainBoundaries, + pdadcValues, numXpdGain); - sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); - tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap - - (minPwrT4[i] / 2)); - maxIndex = (tgtIndex < sizeCurrVpdTable) ? - tgtIndex : sizeCurrVpdTable; + if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { + REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, + SM(pdGainOverlap_t2, + AR_PHY_TPCRG5_PD_GAIN_OVERLAP) + | SM(gainBoundaries[0], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) + | SM(gainBoundaries[1], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) + | SM(gainBoundaries[2], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) + | SM(gainBoundaries[3], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); + } - while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { - pPDADCValues[k++] = vpdTableI[i][ss++]; - } + regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; + for (j = 0; j < 32; j++) { + reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | + ((pdadcValues[4 * j + 1] & 0xFF) << 8) | + ((pdadcValues[4 * j + 2] & 0xFF) << 16)| + ((pdadcValues[4 * j + 3] & 0xFF) << 24); + REG_WRITE(ah, regOffset, reg32); - vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - - vpdTableI[i][sizeCurrVpdTable - 2]); - vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); + DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, + "PDADC (%d,%4x): %4.4x %8.8x\n", + i, regChainOffset, regOffset, + reg32); + DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, + "PDADC: Chain %d | " + "PDADC %3d Value %3d | " + "PDADC %3d Value %3d | " + "PDADC %3d Value %3d | " + "PDADC %3d Value %3d |\n", + i, 4 * j, pdadcValues[4 * j], + 4 * j + 1, pdadcValues[4 * j + 1], + 4 * j + 2, pdadcValues[4 * j + 2], + 4 * j + 3, + pdadcValues[4 * j + 3]); - if (tgtIndex > maxIndex) { - while ((ss <= tgtIndex) && - (k < (AR5416_NUM_PDADC_VALUES - 1))) { - tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + - (ss - maxIndex + 1) * vpdStep)); - pPDADCValues[k++] = (u8)((tmpVal > 255) ? - 255 : tmpVal); - ss++; + regOffset += 4; } } } - while (i < AR5416_PD_GAINS_IN_MASK) { - pPdGainBoundaries[i] = pPdGainBoundaries[i - 1]; - i++; - } - - while (k < AR5416_NUM_PDADC_VALUES) { - pPDADCValues[k] = pPDADCValues[k - 1]; - k++; - } + *pTxPowerIndexOffset = 0; - return; + return true; } -static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, - struct ath9k_channel *chan, - struct cal_target_power_leg *powInfo, - u16 numChannels, - struct cal_target_power_leg *pNewPower, - u16 numRates, bool isExtTarget) +static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, + struct ath9k_channel *chan, + int16_t *ratesArray, + u16 cfgCtl, + u16 AntennaReduction, + u16 twiceMaxRegulatoryPower, + u16 powerLimit) { - struct chan_centers centers; - u16 clo, chi; + struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; + u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; + static const u16 tpScaleReductionTable[5] = + { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; + int i; - int matchIndex = -1, lowIndex = -1; - u16 freq; + int16_t twiceLargestAntenna; + struct cal_ctl_data_4k *rep; + struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { + 0, { 0, 0, 0, 0} + }; + struct cal_target_power_leg targetPowerOfdmExt = { + 0, { 0, 0, 0, 0} }, targetPowerCckExt = { + 0, { 0, 0, 0, 0 } + }; + struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { + 0, {0, 0, 0, 0} + }; + u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; + u16 ctlModesFor11g[] = + { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, + CTL_2GHT40 + }; + u16 numCtlModes, *pCtlMode, ctlMode, freq; + struct chan_centers centers; + int tx_chainmask; + u16 twiceMinEdgePower; + + tx_chainmask = ah->ah_txchainmask; ath9k_hw_get_channel_centers(ah, chan, ¢ers); - freq = (isExtTarget) ? centers.ext_center : centers.ctl_center; - if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, - IS_CHAN_2GHZ(chan))) { - matchIndex = 0; - } else { - for (i = 0; (i < numChannels) && - (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { - if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, - IS_CHAN_2GHZ(chan))) { - matchIndex = i; - break; - } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, - IS_CHAN_2GHZ(chan))) && - (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, - IS_CHAN_2GHZ(chan)))) { - lowIndex = i - 1; - break; - } - } - if ((matchIndex == -1) && (lowIndex == -1)) - matchIndex = i - 1; - } + twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; - if (matchIndex != -1) { - *pNewPower = powInfo[matchIndex]; - } else { - clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, - IS_CHAN_2GHZ(chan)); - chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, - IS_CHAN_2GHZ(chan)); + twiceLargestAntenna = (int16_t)min(AntennaReduction - + twiceLargestAntenna, 0); - for (i = 0; i < numRates; i++) { - pNewPower->tPow2x[i] = - (u8)ath9k_hw_interpolate(freq, clo, chi, - powInfo[lowIndex].tPow2x[i], - powInfo[lowIndex + 1].tPow2x[i]); - } + maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; + + if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) { + maxRegAllowedPower -= + (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2); } -} -static void ath9k_hw_get_target_powers(struct ath_hw *ah, - struct ath9k_channel *chan, - struct cal_target_power_ht *powInfo, - u16 numChannels, - struct cal_target_power_ht *pNewPower, - u16 numRates, bool isHt40Target) -{ - struct chan_centers centers; - u16 clo, chi; - int i; - int matchIndex = -1, lowIndex = -1; - u16 freq; + scaledPower = min(powerLimit, maxRegAllowedPower); + scaledPower = max((u16)0, scaledPower); - ath9k_hw_get_channel_centers(ah, chan, ¢ers); - freq = isHt40Target ? centers.synth_center : centers.ctl_center; + numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; + pCtlMode = ctlModesFor11g; - if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { - matchIndex = 0; - } else { - for (i = 0; (i < numChannels) && - (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { - if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, - IS_CHAN_2GHZ(chan))) { - matchIndex = i; - break; - } else - if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, - IS_CHAN_2GHZ(chan))) && - (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, - IS_CHAN_2GHZ(chan)))) { - lowIndex = i - 1; - break; - } - } - if ((matchIndex == -1) && (lowIndex == -1)) - matchIndex = i - 1; + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPowerCck, + AR5416_NUM_2G_CCK_TARGET_POWERS, + &targetPowerCck, 4, false); + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPower2G, + AR5416_NUM_2G_20_TARGET_POWERS, + &targetPowerOfdm, 4, false); + ath9k_hw_get_target_powers(ah, chan, + pEepData->calTargetPower2GHT20, + AR5416_NUM_2G_20_TARGET_POWERS, + &targetPowerHt20, 8, false); + + if (IS_CHAN_HT40(chan)) { + numCtlModes = ARRAY_SIZE(ctlModesFor11g); + ath9k_hw_get_target_powers(ah, chan, + pEepData->calTargetPower2GHT40, + AR5416_NUM_2G_40_TARGET_POWERS, + &targetPowerHt40, 8, true); + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPowerCck, + AR5416_NUM_2G_CCK_TARGET_POWERS, + &targetPowerCckExt, 4, true); + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPower2G, + AR5416_NUM_2G_20_TARGET_POWERS, + &targetPowerOfdmExt, 4, true); } - if (matchIndex != -1) { - *pNewPower = powInfo[matchIndex]; - } else { - clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, - IS_CHAN_2GHZ(chan)); - chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, - IS_CHAN_2GHZ(chan)); + for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { + bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || + (pCtlMode[ctlMode] == CTL_2GHT40); + if (isHt40CtlMode) + freq = centers.synth_center; + else if (pCtlMode[ctlMode] & EXT_ADDITIVE) + freq = centers.ext_center; + else + freq = centers.ctl_center; - for (i = 0; i < numRates; i++) { - pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq, - clo, chi, - powInfo[lowIndex].tPow2x[i], - powInfo[lowIndex + 1].tPow2x[i]); + if (ah->eep_ops->get_eeprom_ver(ah) == 14 && + ah->eep_ops->get_eeprom_rev(ah) <= 2) + twiceMaxEdgePower = AR5416_MAX_RATE_POWER; + + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " + "EXT_ADDITIVE %d\n", + ctlMode, numCtlModes, isHt40CtlMode, + (pCtlMode[ctlMode] & EXT_ADDITIVE)); + + for (i = 0; (i < AR5416_NUM_CTLS) && + pEepData->ctlIndex[i]; i++) { + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " + "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " + "chan %d\n", + i, cfgCtl, pCtlMode[ctlMode], + pEepData->ctlIndex[i], chan->channel); + + if ((((cfgCtl & ~CTL_MODE_M) | + (pCtlMode[ctlMode] & CTL_MODE_M)) == + pEepData->ctlIndex[i]) || + (((cfgCtl & ~CTL_MODE_M) | + (pCtlMode[ctlMode] & CTL_MODE_M)) == + ((pEepData->ctlIndex[i] & CTL_MODE_M) | + SD_NO_CTL))) { + rep = &(pEepData->ctlData[i]); + + twiceMinEdgePower = + ath9k_hw_get_max_edge_power(freq, + rep->ctlEdges[ar5416_get_ntxchains + (tx_chainmask) - 1], + IS_CHAN_2GHZ(chan), + AR5416_EEP4K_NUM_BAND_EDGES); + + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + " MATCH-EE_IDX %d: ch %d is2 %d " + "2xMinEdge %d chainmask %d chains %d\n", + i, freq, IS_CHAN_2GHZ(chan), + twiceMinEdgePower, tx_chainmask, + ar5416_get_ntxchains + (tx_chainmask)); + if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { + twiceMaxEdgePower = + min(twiceMaxEdgePower, + twiceMinEdgePower); + } else { + twiceMaxEdgePower = twiceMinEdgePower; + break; + } + } } - } -} -static u16 ath9k_hw_get_max_edge_power(u16 freq, - struct cal_ctl_edges *pRdEdgesPower, - bool is2GHz, int num_band_edges) -{ - u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; - int i; + minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); - for (i = 0; (i < num_band_edges) && - (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { - if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { - twiceMaxEdgePower = pRdEdgesPower[i].tPower; + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + " SEL-Min ctlMode %d pCtlMode %d " + "2xMaxEdge %d sP %d minCtlPwr %d\n", + ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, + scaledPower, minCtlPower); + + switch (pCtlMode[ctlMode]) { + case CTL_11B: + for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); + i++) { + targetPowerCck.tPow2x[i] = + min((u16)targetPowerCck.tPow2x[i], + minCtlPower); + } break; - } else if ((i > 0) && - (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, - is2GHz))) { - if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel, - is2GHz) < freq && - pRdEdgesPower[i - 1].flag) { - twiceMaxEdgePower = - pRdEdgesPower[i - 1].tPower; + case CTL_11G: + for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); + i++) { + targetPowerOfdm.tPow2x[i] = + min((u16)targetPowerOfdm.tPow2x[i], + minCtlPower); + } + break; + case CTL_2GHT20: + for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); + i++) { + targetPowerHt20.tPow2x[i] = + min((u16)targetPowerHt20.tPow2x[i], + minCtlPower); + } + break; + case CTL_11B_EXT: + targetPowerCckExt.tPow2x[0] = min((u16) + targetPowerCckExt.tPow2x[0], + minCtlPower); + break; + case CTL_11G_EXT: + targetPowerOfdmExt.tPow2x[0] = min((u16) + targetPowerOfdmExt.tPow2x[0], + minCtlPower); + break; + case CTL_2GHT40: + for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); + i++) { + targetPowerHt40.tPow2x[i] = + min((u16)targetPowerHt40.tPow2x[i], + minCtlPower); } break; + default: + break; } } - return twiceMaxEdgePower; + ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = + ratesArray[rate18mb] = ratesArray[rate24mb] = + targetPowerOfdm.tPow2x[0]; + ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; + ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; + ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; + ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; + + for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) + ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; + + ratesArray[rate1l] = targetPowerCck.tPow2x[0]; + ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; + ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; + ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; + + if (IS_CHAN_HT40(chan)) { + for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { + ratesArray[rateHt40_0 + i] = + targetPowerHt40.tPow2x[i]; + } + ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; + ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; + ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; + ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; + } + return true; } -static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, - struct ath9k_channel *chan, - int16_t *pTxPowerIndexOffset) +static int ath9k_hw_4k_set_txpower(struct ath_hw *ah, + struct ath9k_channel *chan, + u16 cfgCtl, + u8 twiceAntennaReduction, + u8 twiceMaxRegulatoryPower, + u8 powerLimit) { - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; - struct cal_data_per_freq *pRawDataset; - u8 *pCalBChans = NULL; - u16 pdGainOverlap_t2; - static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; - u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; - u16 numPiers, i, j; - int16_t tMinCalPower; - u16 numXpdGain, xpdMask; - u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; - u32 reg32, regOffset, regChainOffset; - int16_t modalIdx; + struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; + struct modal_eep_4k_header *pModal = &pEepData->modalHeader; + int16_t ratesArray[Ar5416RateSize]; + int16_t txPowerIndexOffset = 0; + u8 ht40PowerIncForPdadc = 2; + int i; - modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; - xpdMask = pEepData->modalHeader[modalIdx].xpdGain; + memset(ratesArray, 0, sizeof(ratesArray)); if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= AR5416_EEP_MINOR_VER_2) { - pdGainOverlap_t2 = - pEepData->modalHeader[modalIdx].pdGainOverlap; - } else { - pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), - AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); + ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; } - if (IS_CHAN_2GHZ(chan)) { - pCalBChans = pEepData->calFreqPier2G; - numPiers = AR5416_NUM_2G_CAL_PIERS; - } else { - pCalBChans = pEepData->calFreqPier5G; - numPiers = AR5416_NUM_5G_CAL_PIERS; + if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan, + &ratesArray[0], cfgCtl, + twiceAntennaReduction, + twiceMaxRegulatoryPower, + powerLimit)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "ath9k_hw_set_txpower: unable to set " + "tx power per rate table\n"); + return -EIO; } - numXpdGain = 0; + if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "ath9k_hw_set_txpower: unable to set power table\n"); + return -EIO; + } - for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { - if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { - if (numXpdGain >= AR5416_NUM_PD_GAINS) - break; - xpdGainValues[numXpdGain] = - (u16)(AR5416_PD_GAINS_IN_MASK - i); - numXpdGain++; - } + for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { + ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); + if (ratesArray[i] > AR5416_MAX_RATE_POWER) + ratesArray[i] = AR5416_MAX_RATE_POWER; } - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, - (numXpdGain - 1) & 0x3); - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, - xpdGainValues[0]); - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, - xpdGainValues[1]); - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, - xpdGainValues[2]); + if (AR_SREV_9280_10_OR_LATER(ah)) { + for (i = 0; i < Ar5416RateSize; i++) + ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; + } - for (i = 0; i < AR5416_MAX_CHAINS; i++) { - if (AR_SREV_5416_V20_OR_LATER(ah) && - (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && - (i != 0)) { - regChainOffset = (i == 1) ? 0x2000 : 0x1000; - } else - regChainOffset = i * 0x1000; + REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, + ATH9K_POW_SM(ratesArray[rate18mb], 24) + | ATH9K_POW_SM(ratesArray[rate12mb], 16) + | ATH9K_POW_SM(ratesArray[rate9mb], 8) + | ATH9K_POW_SM(ratesArray[rate6mb], 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, + ATH9K_POW_SM(ratesArray[rate54mb], 24) + | ATH9K_POW_SM(ratesArray[rate48mb], 16) + | ATH9K_POW_SM(ratesArray[rate36mb], 8) + | ATH9K_POW_SM(ratesArray[rate24mb], 0)); - if (pEepData->baseEepHeader.txMask & (1 << i)) { - if (IS_CHAN_2GHZ(chan)) - pRawDataset = pEepData->calPierData2G[i]; - else - pRawDataset = pEepData->calPierData5G[i]; + if (IS_CHAN_2GHZ(chan)) { + REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, + ATH9K_POW_SM(ratesArray[rate2s], 24) + | ATH9K_POW_SM(ratesArray[rate2l], 16) + | ATH9K_POW_SM(ratesArray[rateXr], 8) + | ATH9K_POW_SM(ratesArray[rate1l], 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, + ATH9K_POW_SM(ratesArray[rate11s], 24) + | ATH9K_POW_SM(ratesArray[rate11l], 16) + | ATH9K_POW_SM(ratesArray[rate5_5s], 8) + | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); + } - ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan, - pRawDataset, pCalBChans, - numPiers, pdGainOverlap_t2, - &tMinCalPower, gainBoundaries, - pdadcValues, numXpdGain); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, + ATH9K_POW_SM(ratesArray[rateHt20_3], 24) + | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) + | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) + | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, + ATH9K_POW_SM(ratesArray[rateHt20_7], 24) + | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) + | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) + | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); - if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { - REG_WRITE(ah, - AR_PHY_TPCRG5 + regChainOffset, - SM(pdGainOverlap_t2, - AR_PHY_TPCRG5_PD_GAIN_OVERLAP) - | SM(gainBoundaries[0], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) - | SM(gainBoundaries[1], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) - | SM(gainBoundaries[2], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) - | SM(gainBoundaries[3], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); - } + if (IS_CHAN_HT40(chan)) { + REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, + ATH9K_POW_SM(ratesArray[rateHt40_3] + + ht40PowerIncForPdadc, 24) + | ATH9K_POW_SM(ratesArray[rateHt40_2] + + ht40PowerIncForPdadc, 16) + | ATH9K_POW_SM(ratesArray[rateHt40_1] + + ht40PowerIncForPdadc, 8) + | ATH9K_POW_SM(ratesArray[rateHt40_0] + + ht40PowerIncForPdadc, 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, + ATH9K_POW_SM(ratesArray[rateHt40_7] + + ht40PowerIncForPdadc, 24) + | ATH9K_POW_SM(ratesArray[rateHt40_6] + + ht40PowerIncForPdadc, 16) + | ATH9K_POW_SM(ratesArray[rateHt40_5] + + ht40PowerIncForPdadc, 8) + | ATH9K_POW_SM(ratesArray[rateHt40_4] + + ht40PowerIncForPdadc, 0)); - regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; - for (j = 0; j < 32; j++) { - reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | - ((pdadcValues[4 * j + 1] & 0xFF) << 8) | - ((pdadcValues[4 * j + 2] & 0xFF) << 16)| - ((pdadcValues[4 * j + 3] & 0xFF) << 24); - REG_WRITE(ah, regOffset, reg32); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, + ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) + | ATH9K_POW_SM(ratesArray[rateExtCck], 16) + | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) + | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); + } - DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, - "PDADC (%d,%4x): %4.4x %8.8x\n", - i, regChainOffset, regOffset, - reg32); - DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, - "PDADC: Chain %d | PDADC %3d " - "Value %3d | PDADC %3d Value %3d | " - "PDADC %3d Value %3d | PDADC %3d " - "Value %3d |\n", - i, 4 * j, pdadcValues[4 * j], - 4 * j + 1, pdadcValues[4 * j + 1], - 4 * j + 2, pdadcValues[4 * j + 2], - 4 * j + 3, - pdadcValues[4 * j + 3]); + i = rate6mb; - regOffset += 4; - } - } - } + if (IS_CHAN_HT40(chan)) + i = rateHt40_0; + else if (IS_CHAN_HT20(chan)) + i = rateHt20_0; - *pTxPowerIndexOffset = 0; + if (AR_SREV_9280_10_OR_LATER(ah)) + ah->regulatory.max_power_level = + ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; + else + ah->regulatory.max_power_level = ratesArray[i]; - return true; + return 0; } -static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, - struct ath9k_channel *chan, - int16_t *pTxPowerIndexOffset) +static void ath9k_hw_4k_set_addac(struct ath_hw *ah, + struct ath9k_channel *chan) { - struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; - struct cal_data_per_freq_4k *pRawDataset; - u8 *pCalBChans = NULL; - u16 pdGainOverlap_t2; - static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; - u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; - u16 numPiers, i, j; - int16_t tMinCalPower; - u16 numXpdGain, xpdMask; - u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; - u32 reg32, regOffset, regChainOffset; - - xpdMask = pEepData->modalHeader.xpdGain; + struct modal_eep_4k_header *pModal; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + u8 biaslevel; - if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= - AR5416_EEP_MINOR_VER_2) { - pdGainOverlap_t2 = - pEepData->modalHeader.pdGainOverlap; - } else { - pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), - AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); - } + if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) + return; - pCalBChans = pEepData->calFreqPier2G; - numPiers = AR5416_NUM_2G_CAL_PIERS; + if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7) + return; - numXpdGain = 0; + pModal = &eep->modalHeader; - for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { - if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { - if (numXpdGain >= AR5416_NUM_PD_GAINS) - break; - xpdGainValues[numXpdGain] = - (u16)(AR5416_PD_GAINS_IN_MASK - i); - numXpdGain++; - } + if (pModal->xpaBiasLvl != 0xff) { + biaslevel = pModal->xpaBiasLvl; + INI_RA(&ah->ah_iniAddac, 7, 1) = + (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; } +} - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, - (numXpdGain - 1) & 0x3); - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, - xpdGainValues[0]); - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, - xpdGainValues[1]); - REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, - xpdGainValues[2]); +static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah, + struct ath9k_channel *chan) +{ + struct modal_eep_4k_header *pModal; + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + int regChainOffset; + u8 txRxAttenLocal; + u8 ob[5], db1[5], db2[5]; + u8 ant_div_control1, ant_div_control2; + u32 regVal; - for (i = 0; i < AR5416_MAX_CHAINS; i++) { - if (AR_SREV_5416_V20_OR_LATER(ah) && - (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && - (i != 0)) { - regChainOffset = (i == 1) ? 0x2000 : 0x1000; - } else - regChainOffset = i * 0x1000; - if (pEepData->baseEepHeader.txMask & (1 << i)) { - pRawDataset = pEepData->calPierData2G[i]; + pModal = &eep->modalHeader; - ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan, - pRawDataset, pCalBChans, - numPiers, pdGainOverlap_t2, - &tMinCalPower, gainBoundaries, - pdadcValues, numXpdGain); + txRxAttenLocal = 23; - if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { - REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, - SM(pdGainOverlap_t2, - AR_PHY_TPCRG5_PD_GAIN_OVERLAP) - | SM(gainBoundaries[0], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) - | SM(gainBoundaries[1], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) - | SM(gainBoundaries[2], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) - | SM(gainBoundaries[3], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); - } + REG_WRITE(ah, AR_PHY_SWITCH_COM, + ah->eep_ops->get_eeprom_antenna_cfg(ah, chan)); - regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; - for (j = 0; j < 32; j++) { - reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | - ((pdadcValues[4 * j + 1] & 0xFF) << 8) | - ((pdadcValues[4 * j + 2] & 0xFF) << 16)| - ((pdadcValues[4 * j + 3] & 0xFF) << 24); - REG_WRITE(ah, regOffset, reg32); + regChainOffset = 0; + REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, + pModal->antCtrlChain[0]); - DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, - "PDADC (%d,%4x): %4.4x %8.8x\n", - i, regChainOffset, regOffset, - reg32); - DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, - "PDADC: Chain %d | " - "PDADC %3d Value %3d | " - "PDADC %3d Value %3d | " - "PDADC %3d Value %3d | " - "PDADC %3d Value %3d |\n", - i, 4 * j, pdadcValues[4 * j], - 4 * j + 1, pdadcValues[4 * j + 1], - 4 * j + 2, pdadcValues[4 * j + 2], - 4 * j + 3, - pdadcValues[4 * j + 3]); + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, + (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & + ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | + AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | + SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | + SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); - regOffset += 4; - } - } + if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= + AR5416_EEP_MINOR_VER_3) { + txRxAttenLocal = pModal->txRxAttenCh[0]; + REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); + REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); + REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, + pModal->xatten2Margin[0]); + REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); } - *pTxPowerIndexOffset = 0; + REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, + AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); + REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, + AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); - return true; -} + if (AR_SREV_9285_11(ah)) + REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); -static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, - struct ath9k_channel *chan, - int16_t *ratesArray, - u16 cfgCtl, - u16 AntennaReduction, - u16 twiceMaxRegulatoryPower, - u16 powerLimit) -{ -#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ -#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ + /* Initialize Ant Diversity settings from EEPROM */ + if (pModal->version == 3) { + ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf); + ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf); + regVal = REG_READ(ah, 0x99ac); + regVal &= (~(0x7f000000)); + regVal |= ((ant_div_control1 & 0x1) << 24); + regVal |= (((ant_div_control1 >> 1) & 0x1) << 29); + regVal |= (((ant_div_control1 >> 2) & 0x1) << 30); + regVal |= ((ant_div_control2 & 0x3) << 25); + regVal |= (((ant_div_control2 >> 2) & 0x3) << 27); + REG_WRITE(ah, 0x99ac, regVal); + regVal = REG_READ(ah, 0x99ac); + regVal = REG_READ(ah, 0xa208); + regVal &= (~(0x1 << 13)); + regVal |= (((ant_div_control1 >> 3) & 0x1) << 13); + REG_WRITE(ah, 0xa208, regVal); + regVal = REG_READ(ah, 0xa208); + } - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; - u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; - static const u16 tpScaleReductionTable[5] = - { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; + if (pModal->version >= 2) { + ob[0] = (pModal->ob_01 & 0xf); + ob[1] = (pModal->ob_01 >> 4) & 0xf; + ob[2] = (pModal->ob_234 & 0xf); + ob[3] = ((pModal->ob_234 >> 4) & 0xf); + ob[4] = ((pModal->ob_234 >> 8) & 0xf); - int i; - int16_t twiceLargestAntenna; - struct cal_ctl_data *rep; - struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { - 0, { 0, 0, 0, 0} - }; - struct cal_target_power_leg targetPowerOfdmExt = { - 0, { 0, 0, 0, 0} }, targetPowerCckExt = { - 0, { 0, 0, 0, 0 } - }; - struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { - 0, {0, 0, 0, 0} - }; - u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; - u16 ctlModesFor11a[] = - { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 }; - u16 ctlModesFor11g[] = - { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, - CTL_2GHT40 - }; - u16 numCtlModes, *pCtlMode, ctlMode, freq; - struct chan_centers centers; - int tx_chainmask; - u16 twiceMinEdgePower; + db1[0] = (pModal->db1_01 & 0xf); + db1[1] = ((pModal->db1_01 >> 4) & 0xf); + db1[2] = (pModal->db1_234 & 0xf); + db1[3] = ((pModal->db1_234 >> 4) & 0xf); + db1[4] = ((pModal->db1_234 >> 8) & 0xf); - tx_chainmask = ah->ah_txchainmask; + db2[0] = (pModal->db2_01 & 0xf); + db2[1] = ((pModal->db2_01 >> 4) & 0xf); + db2[2] = (pModal->db2_234 & 0xf); + db2[3] = ((pModal->db2_234 >> 4) & 0xf); + db2[4] = ((pModal->db2_234 >> 8) & 0xf); - ath9k_hw_get_channel_centers(ah, chan, ¢ers); + } else if (pModal->version == 1) { - twiceLargestAntenna = max( - pEepData->modalHeader - [IS_CHAN_2GHZ(chan)].antennaGainCh[0], - pEepData->modalHeader - [IS_CHAN_2GHZ(chan)].antennaGainCh[1]); + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "EEPROM Model version is set to 1 \n"); + ob[0] = (pModal->ob_01 & 0xf); + ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf; + db1[0] = (pModal->db1_01 & 0xf); + db1[1] = db1[2] = db1[3] = + db1[4] = ((pModal->db1_01 >> 4) & 0xf); + db2[0] = (pModal->db2_01 & 0xf); + db2[1] = db2[2] = db2[3] = + db2[4] = ((pModal->db2_01 >> 4) & 0xf); + } else { + int i; + for (i = 0; i < 5; i++) { + ob[i] = pModal->ob_01; + db1[i] = pModal->db1_01; + db2[i] = pModal->db1_01; + } + } - twiceLargestAntenna = max((u8)twiceLargestAntenna, - pEepData->modalHeader - [IS_CHAN_2GHZ(chan)].antennaGainCh[2]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]); - twiceLargestAntenna = (int16_t)min(AntennaReduction - - twiceLargestAntenna, 0); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, + AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]); - maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]); + ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, + AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]); - if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) { - maxRegAllowedPower -= - (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2); - } - scaledPower = min(powerLimit, maxRegAllowedPower); + if (AR_SREV_9285_11(ah)) + REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT); - switch (ar5416_get_ntxchains(tx_chainmask)) { - case 1: - break; - case 2: - scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; - break; - case 3: - scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; - break; - } + REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, + pModal->switchSettling); + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, + pModal->adcDesiredSize); - scaledPower = max((u16)0, scaledPower); + REG_WRITE(ah, AR_PHY_RF_CTL4, + SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | + SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | + SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | + SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); - if (IS_CHAN_2GHZ(chan)) { - numCtlModes = ARRAY_SIZE(ctlModesFor11g) - - SUB_NUM_CTL_MODES_AT_2G_40; - pCtlMode = ctlModesFor11g; + REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, + pModal->txEndToRxOn); + REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, + pModal->thresh62); + REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, + pModal->thresh62); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPowerCck, - AR5416_NUM_2G_CCK_TARGET_POWERS, - &targetPowerCck, 4, false); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPower2G, - AR5416_NUM_2G_20_TARGET_POWERS, - &targetPowerOfdm, 4, false); - ath9k_hw_get_target_powers(ah, chan, - pEepData->calTargetPower2GHT20, - AR5416_NUM_2G_20_TARGET_POWERS, - &targetPowerHt20, 8, false); + if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= + AR5416_EEP_MINOR_VER_2) { + REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START, + pModal->txFrameToDataStart); + REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, + pModal->txFrameToPaOn); + } - if (IS_CHAN_HT40(chan)) { - numCtlModes = ARRAY_SIZE(ctlModesFor11g); - ath9k_hw_get_target_powers(ah, chan, - pEepData->calTargetPower2GHT40, - AR5416_NUM_2G_40_TARGET_POWERS, - &targetPowerHt40, 8, true); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPowerCck, - AR5416_NUM_2G_CCK_TARGET_POWERS, - &targetPowerCckExt, 4, true); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPower2G, - AR5416_NUM_2G_20_TARGET_POWERS, - &targetPowerOfdmExt, 4, true); - } - } else { - numCtlModes = ARRAY_SIZE(ctlModesFor11a) - - SUB_NUM_CTL_MODES_AT_5G_40; - pCtlMode = ctlModesFor11a; + if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= + AR5416_EEP_MINOR_VER_3) { + if (IS_CHAN_HT40(chan)) + REG_RMW_FIELD(ah, AR_PHY_SETTLING, + AR_PHY_SETTLING_SWITCH, + pModal->swSettleHt40); + } - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPower5G, - AR5416_NUM_5G_20_TARGET_POWERS, - &targetPowerOfdm, 4, false); - ath9k_hw_get_target_powers(ah, chan, - pEepData->calTargetPower5GHT20, - AR5416_NUM_5G_20_TARGET_POWERS, - &targetPowerHt20, 8, false); + return true; +} - if (IS_CHAN_HT40(chan)) { - numCtlModes = ARRAY_SIZE(ctlModesFor11a); - ath9k_hw_get_target_powers(ah, chan, - pEepData->calTargetPower5GHT40, - AR5416_NUM_5G_40_TARGET_POWERS, - &targetPowerHt40, 8, true); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPower5G, - AR5416_NUM_5G_20_TARGET_POWERS, - &targetPowerOfdmExt, 4, true); - } - } +static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah, + struct ath9k_channel *chan) +{ + struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct modal_eep_4k_header *pModal = &eep->modalHeader; - for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { - bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || - (pCtlMode[ctlMode] == CTL_2GHT40); - if (isHt40CtlMode) - freq = centers.synth_center; - else if (pCtlMode[ctlMode] & EXT_ADDITIVE) - freq = centers.ext_center; - else - freq = centers.ctl_center; + return pModal->antCtrlCommon & 0xFFFF; +} - if (ar5416_get_eep_ver(ah) == 14 && ar5416_get_eep_rev(ah) <= 2) - twiceMaxEdgePower = AR5416_MAX_RATE_POWER; +static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah, + enum ieee80211_band freq_band) +{ + return 1; +} - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " - "EXT_ADDITIVE %d\n", - ctlMode, numCtlModes, isHt40CtlMode, - (pCtlMode[ctlMode] & EXT_ADDITIVE)); +u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) +{ +#define EEP_MAP4K_SPURCHAN \ + (ah->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) - for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " - "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " - "chan %d\n", - i, cfgCtl, pCtlMode[ctlMode], - pEepData->ctlIndex[i], chan->channel); + u16 spur_val = AR_NO_SPUR; - if ((((cfgCtl & ~CTL_MODE_M) | - (pCtlMode[ctlMode] & CTL_MODE_M)) == - pEepData->ctlIndex[i]) || - (((cfgCtl & ~CTL_MODE_M) | - (pCtlMode[ctlMode] & CTL_MODE_M)) == - ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { - rep = &(pEepData->ctlData[i]); + DPRINTF(ah->ah_sc, ATH_DBG_ANI, + "Getting spur idx %d is2Ghz. %d val %x\n", + i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); - twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq, - rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], - IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); + switch (ah->ah_config.spurmode) { + case SPUR_DISABLE: + break; + case SPUR_ENABLE_IOCTL: + spur_val = ah->ah_config.spurchans[i][is2GHz]; + DPRINTF(ah->ah_sc, ATH_DBG_ANI, + "Getting spur val from new loc. %d\n", spur_val); + break; + case SPUR_ENABLE_EEPROM: + spur_val = EEP_MAP4K_SPURCHAN; + break; + } - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - " MATCH-EE_IDX %d: ch %d is2 %d " - "2xMinEdge %d chainmask %d chains %d\n", - i, freq, IS_CHAN_2GHZ(chan), - twiceMinEdgePower, tx_chainmask, - ar5416_get_ntxchains - (tx_chainmask)); - if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { - twiceMaxEdgePower = min(twiceMaxEdgePower, - twiceMinEdgePower); - } else { - twiceMaxEdgePower = twiceMinEdgePower; - break; - } - } - } + return spur_val; - minCtlPower = min(twiceMaxEdgePower, scaledPower); +#undef EEP_MAP4K_SPURCHAN +} - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - " SEL-Min ctlMode %d pCtlMode %d " - "2xMaxEdge %d sP %d minCtlPwr %d\n", - ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, - scaledPower, minCtlPower); +struct eeprom_ops eep_4k_ops = { + .check_eeprom = ath9k_hw_4k_check_eeprom, + .get_eeprom = ath9k_hw_4k_get_eeprom, + .fill_eeprom = ath9k_hw_4k_fill_eeprom, + .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver, + .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev, + .get_num_ant_config = ath9k_hw_4k_get_num_ant_config, + .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg, + .set_board_values = ath9k_hw_4k_set_board_values, + .set_addac = ath9k_hw_4k_set_addac, + .set_txpower = ath9k_hw_4k_set_txpower, + .get_spur_channel = ath9k_hw_4k_get_spur_channel +}; - switch (pCtlMode[ctlMode]) { - case CTL_11B: - for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { - targetPowerCck.tPow2x[i] = - min((u16)targetPowerCck.tPow2x[i], - minCtlPower); - } - break; - case CTL_11A: - case CTL_11G: - for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { - targetPowerOfdm.tPow2x[i] = - min((u16)targetPowerOfdm.tPow2x[i], - minCtlPower); - } - break; - case CTL_5GHT20: - case CTL_2GHT20: - for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { - targetPowerHt20.tPow2x[i] = - min((u16)targetPowerHt20.tPow2x[i], - minCtlPower); - } - break; - case CTL_11B_EXT: - targetPowerCckExt.tPow2x[0] = min((u16) - targetPowerCckExt.tPow2x[0], - minCtlPower); - break; - case CTL_11A_EXT: - case CTL_11G_EXT: - targetPowerOfdmExt.tPow2x[0] = min((u16) - targetPowerOfdmExt.tPow2x[0], - minCtlPower); - break; - case CTL_5GHT40: - case CTL_2GHT40: - for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { - targetPowerHt40.tPow2x[i] = - min((u16)targetPowerHt40.tPow2x[i], - minCtlPower); - } - break; - default: - break; - } - } +/************************************************/ +/* EEPROM Operations for non-4K (Default) cards */ +/************************************************/ - ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = - ratesArray[rate18mb] = ratesArray[rate24mb] = - targetPowerOfdm.tPow2x[0]; - ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; - ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; - ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; - ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; +static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah) +{ + return ((ah->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF); +} - for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) - ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; +static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah) +{ + return ((ah->ah_eeprom.def.baseEepHeader.version) & 0xFFF); +} - if (IS_CHAN_2GHZ(chan)) { - ratesArray[rate1l] = targetPowerCck.tPow2x[0]; - ratesArray[rate2s] = ratesArray[rate2l] = - targetPowerCck.tPow2x[1]; - ratesArray[rate5_5s] = ratesArray[rate5_5l] = - targetPowerCck.tPow2x[2]; - ; - ratesArray[rate11s] = ratesArray[rate11l] = - targetPowerCck.tPow2x[3]; - ; - } - if (IS_CHAN_HT40(chan)) { - for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { - ratesArray[rateHt40_0 + i] = - targetPowerHt40.tPow2x[i]; - } - ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; - ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; - ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; - if (IS_CHAN_2GHZ(chan)) { - ratesArray[rateExtCck] = - targetPowerCckExt.tPow2x[0]; +static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) +{ +#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + u16 *eep_data; + int addr, ar5416_eep_start_loc = 0x100; + + eep_data = (u16 *)eep; + + for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { + if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, + eep_data)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Unable to read eeprom region\n"); + return false; } + eep_data++; } return true; +#undef SIZE_EEPROM_DEF } -static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, - struct ath9k_channel *chan, - int16_t *ratesArray, - u16 cfgCtl, - u16 AntennaReduction, - u16 twiceMaxRegulatoryPower, - u16 powerLimit) +static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) { - struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; - u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; - static const u16 tpScaleReductionTable[5] = - { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; + struct ar5416_eeprom_def *eep = + (struct ar5416_eeprom_def *) &ah->ah_eeprom.def; + u16 *eepdata, temp, magic, magic2; + u32 sum = 0, el; + bool need_swap = false; + int i, addr, size; - int i; - int16_t twiceLargestAntenna; - struct cal_ctl_data_4k *rep; - struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { - 0, { 0, 0, 0, 0} - }; - struct cal_target_power_leg targetPowerOfdmExt = { - 0, { 0, 0, 0, 0} }, targetPowerCckExt = { - 0, { 0, 0, 0, 0 } - }; - struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { - 0, {0, 0, 0, 0} - }; - u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; - u16 ctlModesFor11g[] = - { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, - CTL_2GHT40 - }; - u16 numCtlModes, *pCtlMode, ctlMode, freq; - struct chan_centers centers; - int tx_chainmask; - u16 twiceMinEdgePower; + if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, + &magic)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Reading Magic # failed\n"); + return false; + } - tx_chainmask = ah->ah_txchainmask; + if (!ath9k_hw_use_flash(ah)) { - ath9k_hw_get_channel_centers(ah, chan, ¢ers); + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Read Magic = 0x%04X\n", magic); - twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; + if (magic != AR5416_EEPROM_MAGIC) { + magic2 = swab16(magic); - twiceLargestAntenna = (int16_t)min(AntennaReduction - - twiceLargestAntenna, 0); + if (magic2 == AR5416_EEPROM_MAGIC) { + size = sizeof(struct ar5416_eeprom_def); + need_swap = true; + eepdata = (u16 *) (&ah->ah_eeprom); - maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; + for (addr = 0; addr < size / sizeof(u16); addr++) { + temp = swab16(*eepdata); + *eepdata = temp; + eepdata++; - if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) { - maxRegAllowedPower -= - (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2); + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "0x%04X ", *eepdata); + + if (((addr + 1) % 6) == 0) + DPRINTF(ah->ah_sc, + ATH_DBG_EEPROM, "\n"); + } + } else { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Invalid EEPROM Magic. " + "endianness mismatch.\n"); + return -EINVAL; + } + } } - scaledPower = min(powerLimit, maxRegAllowedPower); - scaledPower = max((u16)0, scaledPower); + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", + need_swap ? "True" : "False"); - numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; - pCtlMode = ctlModesFor11g; + if (need_swap) + el = swab16(ah->ah_eeprom.def.baseEepHeader.length); + else + el = ah->ah_eeprom.def.baseEepHeader.length; - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPowerCck, - AR5416_NUM_2G_CCK_TARGET_POWERS, - &targetPowerCck, 4, false); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPower2G, - AR5416_NUM_2G_20_TARGET_POWERS, - &targetPowerOfdm, 4, false); - ath9k_hw_get_target_powers(ah, chan, - pEepData->calTargetPower2GHT20, - AR5416_NUM_2G_20_TARGET_POWERS, - &targetPowerHt20, 8, false); + if (el > sizeof(struct ar5416_eeprom_def)) + el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); + else + el = el / sizeof(u16); - if (IS_CHAN_HT40(chan)) { - numCtlModes = ARRAY_SIZE(ctlModesFor11g); - ath9k_hw_get_target_powers(ah, chan, - pEepData->calTargetPower2GHT40, - AR5416_NUM_2G_40_TARGET_POWERS, - &targetPowerHt40, 8, true); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPowerCck, - AR5416_NUM_2G_CCK_TARGET_POWERS, - &targetPowerCckExt, 4, true); - ath9k_hw_get_legacy_target_powers(ah, chan, - pEepData->calTargetPower2G, - AR5416_NUM_2G_20_TARGET_POWERS, - &targetPowerOfdmExt, 4, true); - } + eepdata = (u16 *)(&ah->ah_eeprom); - for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { - bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || - (pCtlMode[ctlMode] == CTL_2GHT40); - if (isHt40CtlMode) - freq = centers.synth_center; - else if (pCtlMode[ctlMode] & EXT_ADDITIVE) - freq = centers.ext_center; - else - freq = centers.ctl_center; + for (i = 0; i < el; i++) + sum ^= *eepdata++; - if (ar5416_get_eep_ver(ah) == 14 && - ar5416_get_eep_rev(ah) <= 2) - twiceMaxEdgePower = AR5416_MAX_RATE_POWER; + if (need_swap) { + u32 integer, j; + u16 word; - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " - "EXT_ADDITIVE %d\n", - ctlMode, numCtlModes, isHt40CtlMode, - (pCtlMode[ctlMode] & EXT_ADDITIVE)); + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "EEPROM Endianness is not native.. Changing \n"); - for (i = 0; (i < AR5416_NUM_CTLS) && - pEepData->ctlIndex[i]; i++) { - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " - "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " - "chan %d\n", - i, cfgCtl, pCtlMode[ctlMode], - pEepData->ctlIndex[i], chan->channel); + word = swab16(eep->baseEepHeader.length); + eep->baseEepHeader.length = word; - if ((((cfgCtl & ~CTL_MODE_M) | - (pCtlMode[ctlMode] & CTL_MODE_M)) == - pEepData->ctlIndex[i]) || - (((cfgCtl & ~CTL_MODE_M) | - (pCtlMode[ctlMode] & CTL_MODE_M)) == - ((pEepData->ctlIndex[i] & CTL_MODE_M) | - SD_NO_CTL))) { - rep = &(pEepData->ctlData[i]); + word = swab16(eep->baseEepHeader.checksum); + eep->baseEepHeader.checksum = word; - twiceMinEdgePower = - ath9k_hw_get_max_edge_power(freq, - rep->ctlEdges[ar5416_get_ntxchains - (tx_chainmask) - 1], - IS_CHAN_2GHZ(chan), - AR5416_EEP4K_NUM_BAND_EDGES); + word = swab16(eep->baseEepHeader.version); + eep->baseEepHeader.version = word; - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - " MATCH-EE_IDX %d: ch %d is2 %d " - "2xMinEdge %d chainmask %d chains %d\n", - i, freq, IS_CHAN_2GHZ(chan), - twiceMinEdgePower, tx_chainmask, - ar5416_get_ntxchains - (tx_chainmask)); - if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { - twiceMaxEdgePower = - min(twiceMaxEdgePower, - twiceMinEdgePower); - } else { - twiceMaxEdgePower = twiceMinEdgePower; - break; - } - } - } + word = swab16(eep->baseEepHeader.regDmn[0]); + eep->baseEepHeader.regDmn[0] = word; - minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); + word = swab16(eep->baseEepHeader.regDmn[1]); + eep->baseEepHeader.regDmn[1] = word; - DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, - " SEL-Min ctlMode %d pCtlMode %d " - "2xMaxEdge %d sP %d minCtlPwr %d\n", - ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, - scaledPower, minCtlPower); + word = swab16(eep->baseEepHeader.rfSilent); + eep->baseEepHeader.rfSilent = word; - switch (pCtlMode[ctlMode]) { - case CTL_11B: - for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); - i++) { - targetPowerCck.tPow2x[i] = - min((u16)targetPowerCck.tPow2x[i], - minCtlPower); - } - break; - case CTL_11G: - for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); - i++) { - targetPowerOfdm.tPow2x[i] = - min((u16)targetPowerOfdm.tPow2x[i], - minCtlPower); - } - break; - case CTL_2GHT20: - for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); - i++) { - targetPowerHt20.tPow2x[i] = - min((u16)targetPowerHt20.tPow2x[i], - minCtlPower); + word = swab16(eep->baseEepHeader.blueToothOptions); + eep->baseEepHeader.blueToothOptions = word; + + word = swab16(eep->baseEepHeader.deviceCap); + eep->baseEepHeader.deviceCap = word; + + for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { + struct modal_eep_header *pModal = + &eep->modalHeader[j]; + integer = swab32(pModal->antCtrlCommon); + pModal->antCtrlCommon = integer; + + for (i = 0; i < AR5416_MAX_CHAINS; i++) { + integer = swab32(pModal->antCtrlChain[i]); + pModal->antCtrlChain[i] = integer; } - break; - case CTL_11B_EXT: - targetPowerCckExt.tPow2x[0] = min((u16) - targetPowerCckExt.tPow2x[0], - minCtlPower); - break; - case CTL_11G_EXT: - targetPowerOfdmExt.tPow2x[0] = min((u16) - targetPowerOfdmExt.tPow2x[0], - minCtlPower); - break; - case CTL_2GHT40: - for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); - i++) { - targetPowerHt40.tPow2x[i] = - min((u16)targetPowerHt40.tPow2x[i], - minCtlPower); + + for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { + word = swab16(pModal->spurChans[i].spurChan); + pModal->spurChans[i].spurChan = word; } - break; - default: - break; } } - ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = - ratesArray[rate18mb] = ratesArray[rate24mb] = - targetPowerOfdm.tPow2x[0]; - ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; - ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; - ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; - ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; + if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || + ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Bad EEPROM checksum 0x%x or revision 0x%04x\n", + sum, ah->eep_ops->get_eeprom_ver(ah)); + return -EINVAL; + } - for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) - ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; + return 0; +} - ratesArray[rate1l] = targetPowerCck.tPow2x[0]; - ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; - ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; - ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; +static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, + enum eeprom_param param) +{ +#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct modal_eep_header *pModal = eep->modalHeader; + struct base_eep_header *pBase = &eep->baseEepHeader; - if (IS_CHAN_HT40(chan)) { - for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { - ratesArray[rateHt40_0 + i] = - targetPowerHt40.tPow2x[i]; - } - ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; - ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; - ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; - ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; + switch (param) { + case EEP_NFTHRESH_5: + return pModal[0].noiseFloorThreshCh[0]; + case EEP_NFTHRESH_2: + return pModal[1].noiseFloorThreshCh[0]; + case AR_EEPROM_MAC(0): + return pBase->macAddr[0] << 8 | pBase->macAddr[1]; + case AR_EEPROM_MAC(1): + return pBase->macAddr[2] << 8 | pBase->macAddr[3]; + case AR_EEPROM_MAC(2): + return pBase->macAddr[4] << 8 | pBase->macAddr[5]; + case EEP_REG_0: + return pBase->regDmn[0]; + case EEP_REG_1: + return pBase->regDmn[1]; + case EEP_OP_CAP: + return pBase->deviceCap; + case EEP_OP_MODE: + return pBase->opCapFlags; + case EEP_RF_SILENT: + return pBase->rfSilent; + case EEP_OB_5: + return pModal[0].ob; + case EEP_DB_5: + return pModal[0].db; + case EEP_OB_2: + return pModal[1].ob; + case EEP_DB_2: + return pModal[1].db; + case EEP_MINOR_REV: + return AR5416_VER_MASK; + case EEP_TX_MASK: + return pBase->txMask; + case EEP_RX_MASK: + return pBase->rxMask; + case EEP_RXGAIN_TYPE: + return pBase->rxGainType; + case EEP_TXGAIN_TYPE: + return pBase->txGainType; + case EEP_DAC_HPWR_5G: + if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) + return pBase->dacHiPwrMode_5G; + else + return 0; + default: + return 0; } - return true; +#undef AR5416_VER_MASK } -static int ath9k_hw_def_set_txpower(struct ath_hw *ah, - struct ath9k_channel *chan, - u16 cfgCtl, - u8 twiceAntennaReduction, - u8 twiceMaxRegulatoryPower, - u8 powerLimit) +/* XXX: Clean me up, make me more legible */ +static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, + struct ath9k_channel *chan) { - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; - struct modal_eep_header *pModal = - &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); - int16_t ratesArray[Ar5416RateSize]; - int16_t txPowerIndexOffset = 0; - u8 ht40PowerIncForPdadc = 2; - int i; - - memset(ratesArray, 0, sizeof(ratesArray)); - - if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= - AR5416_EEP_MINOR_VER_2) { - ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; - } - - if (!ath9k_hw_set_def_power_per_rate_table(ah, chan, - &ratesArray[0], cfgCtl, - twiceAntennaReduction, - twiceMaxRegulatoryPower, - powerLimit)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "ath9k_hw_set_txpower: unable to set " - "tx power per rate table\n"); - return -EIO; - } - - if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "ath9k_hw_set_txpower: unable to set power table\n"); - return -EIO; - } - - for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { - ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); - if (ratesArray[i] > AR5416_MAX_RATE_POWER) - ratesArray[i] = AR5416_MAX_RATE_POWER; - } - - if (AR_SREV_9280_10_OR_LATER(ah)) { - for (i = 0; i < Ar5416RateSize; i++) - ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; - } - - REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, - ATH9K_POW_SM(ratesArray[rate18mb], 24) - | ATH9K_POW_SM(ratesArray[rate12mb], 16) - | ATH9K_POW_SM(ratesArray[rate9mb], 8) - | ATH9K_POW_SM(ratesArray[rate6mb], 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, - ATH9K_POW_SM(ratesArray[rate54mb], 24) - | ATH9K_POW_SM(ratesArray[rate48mb], 16) - | ATH9K_POW_SM(ratesArray[rate36mb], 8) - | ATH9K_POW_SM(ratesArray[rate24mb], 0)); - - if (IS_CHAN_2GHZ(chan)) { - REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, - ATH9K_POW_SM(ratesArray[rate2s], 24) - | ATH9K_POW_SM(ratesArray[rate2l], 16) - | ATH9K_POW_SM(ratesArray[rateXr], 8) - | ATH9K_POW_SM(ratesArray[rate1l], 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, - ATH9K_POW_SM(ratesArray[rate11s], 24) - | ATH9K_POW_SM(ratesArray[rate11l], 16) - | ATH9K_POW_SM(ratesArray[rate5_5s], 8) - | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); - } - - REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, - ATH9K_POW_SM(ratesArray[rateHt20_3], 24) - | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) - | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) - | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, - ATH9K_POW_SM(ratesArray[rateHt20_7], 24) - | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) - | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) - | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); - - if (IS_CHAN_HT40(chan)) { - REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, - ATH9K_POW_SM(ratesArray[rateHt40_3] + - ht40PowerIncForPdadc, 24) - | ATH9K_POW_SM(ratesArray[rateHt40_2] + - ht40PowerIncForPdadc, 16) - | ATH9K_POW_SM(ratesArray[rateHt40_1] + - ht40PowerIncForPdadc, 8) - | ATH9K_POW_SM(ratesArray[rateHt40_0] + - ht40PowerIncForPdadc, 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, - ATH9K_POW_SM(ratesArray[rateHt40_7] + - ht40PowerIncForPdadc, 24) - | ATH9K_POW_SM(ratesArray[rateHt40_6] + - ht40PowerIncForPdadc, 16) - | ATH9K_POW_SM(ratesArray[rateHt40_5] + - ht40PowerIncForPdadc, 8) - | ATH9K_POW_SM(ratesArray[rateHt40_4] + - ht40PowerIncForPdadc, 0)); - - REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, - ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) - | ATH9K_POW_SM(ratesArray[rateExtCck], 16) - | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) - | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); - } - - REG_WRITE(ah, AR_PHY_POWER_TX_SUB, - ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) - | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); - - i = rate6mb; - - if (IS_CHAN_HT40(chan)) - i = rateHt40_0; - else if (IS_CHAN_HT20(chan)) - i = rateHt20_0; +#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) + struct modal_eep_header *pModal; + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + int i, regChainOffset; + u8 txRxAttenLocal; - if (AR_SREV_9280_10_OR_LATER(ah)) - ah->regulatory.max_power_level = - ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; - else - ah->regulatory.max_power_level = ratesArray[i]; + pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); - return 0; -} + txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; -static int ath9k_hw_4k_set_txpower(struct ath_hw *ah, - struct ath9k_channel *chan, - u16 cfgCtl, - u8 twiceAntennaReduction, - u8 twiceMaxRegulatoryPower, - u8 powerLimit) -{ - struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; - struct modal_eep_4k_header *pModal = &pEepData->modalHeader; - int16_t ratesArray[Ar5416RateSize]; - int16_t txPowerIndexOffset = 0; - u8 ht40PowerIncForPdadc = 2; - int i; + REG_WRITE(ah, AR_PHY_SWITCH_COM, + ah->eep_ops->get_eeprom_antenna_cfg(ah, chan)); - memset(ratesArray, 0, sizeof(ratesArray)); + for (i = 0; i < AR5416_MAX_CHAINS; i++) { + if (AR_SREV_9280(ah)) { + if (i >= 2) + break; + } - if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= - AR5416_EEP_MINOR_VER_2) { - ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; - } + if (AR_SREV_5416_V20_OR_LATER(ah) && + (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) + && (i != 0)) + regChainOffset = (i == 1) ? 0x2000 : 0x1000; + else + regChainOffset = i * 0x1000; - if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan, - &ratesArray[0], cfgCtl, - twiceAntennaReduction, - twiceMaxRegulatoryPower, - powerLimit)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "ath9k_hw_set_txpower: unable to set " - "tx power per rate table\n"); - return -EIO; - } + REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, + pModal->antCtrlChain[i]); - if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "ath9k_hw_set_txpower: unable to set power table\n"); - return -EIO; - } + REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, + (REG_READ(ah, + AR_PHY_TIMING_CTRL4(0) + + regChainOffset) & + ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | + AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | + SM(pModal->iqCalICh[i], + AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | + SM(pModal->iqCalQCh[i], + AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); - for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { - ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); - if (ratesArray[i] > AR5416_MAX_RATE_POWER) - ratesArray[i] = AR5416_MAX_RATE_POWER; + if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { + if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { + txRxAttenLocal = pModal->txRxAttenCh[i]; + if (AR_SREV_9280_10_OR_LATER(ah)) { + REG_RMW_FIELD(ah, + AR_PHY_GAIN_2GHZ + + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, + pModal-> + bswMargin[i]); + REG_RMW_FIELD(ah, + AR_PHY_GAIN_2GHZ + + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN1_DB, + pModal-> + bswAtten[i]); + REG_RMW_FIELD(ah, + AR_PHY_GAIN_2GHZ + + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, + pModal-> + xatten2Margin[i]); + REG_RMW_FIELD(ah, + AR_PHY_GAIN_2GHZ + + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN2_DB, + pModal-> + xatten2Db[i]); + } else { + REG_WRITE(ah, + AR_PHY_GAIN_2GHZ + + regChainOffset, + (REG_READ(ah, + AR_PHY_GAIN_2GHZ + + regChainOffset) & + ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) + | SM(pModal-> + bswMargin[i], + AR_PHY_GAIN_2GHZ_BSW_MARGIN)); + REG_WRITE(ah, + AR_PHY_GAIN_2GHZ + + regChainOffset, + (REG_READ(ah, + AR_PHY_GAIN_2GHZ + + regChainOffset) & + ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) + | SM(pModal->bswAtten[i], + AR_PHY_GAIN_2GHZ_BSW_ATTEN)); + } + } + if (AR_SREV_9280_10_OR_LATER(ah)) { + REG_RMW_FIELD(ah, + AR_PHY_RXGAIN + + regChainOffset, + AR9280_PHY_RXGAIN_TXRX_ATTEN, + txRxAttenLocal); + REG_RMW_FIELD(ah, + AR_PHY_RXGAIN + + regChainOffset, + AR9280_PHY_RXGAIN_TXRX_MARGIN, + pModal->rxTxMarginCh[i]); + } else { + REG_WRITE(ah, + AR_PHY_RXGAIN + regChainOffset, + (REG_READ(ah, + AR_PHY_RXGAIN + + regChainOffset) & + ~AR_PHY_RXGAIN_TXRX_ATTEN) | + SM(txRxAttenLocal, + AR_PHY_RXGAIN_TXRX_ATTEN)); + REG_WRITE(ah, + AR_PHY_GAIN_2GHZ + + regChainOffset, + (REG_READ(ah, + AR_PHY_GAIN_2GHZ + + regChainOffset) & + ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | + SM(pModal->rxTxMarginCh[i], + AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); + } + } } if (AR_SREV_9280_10_OR_LATER(ah)) { - for (i = 0; i < Ar5416RateSize; i++) - ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; - } - - REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, - ATH9K_POW_SM(ratesArray[rate18mb], 24) - | ATH9K_POW_SM(ratesArray[rate12mb], 16) - | ATH9K_POW_SM(ratesArray[rate9mb], 8) - | ATH9K_POW_SM(ratesArray[rate6mb], 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, - ATH9K_POW_SM(ratesArray[rate54mb], 24) - | ATH9K_POW_SM(ratesArray[rate48mb], 16) - | ATH9K_POW_SM(ratesArray[rate36mb], 8) - | ATH9K_POW_SM(ratesArray[rate24mb], 0)); - - if (IS_CHAN_2GHZ(chan)) { - REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, - ATH9K_POW_SM(ratesArray[rate2s], 24) - | ATH9K_POW_SM(ratesArray[rate2l], 16) - | ATH9K_POW_SM(ratesArray[rateXr], 8) - | ATH9K_POW_SM(ratesArray[rate1l], 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, - ATH9K_POW_SM(ratesArray[rate11s], 24) - | ATH9K_POW_SM(ratesArray[rate11l], 16) - | ATH9K_POW_SM(ratesArray[rate5_5s], 8) - | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); + if (IS_CHAN_2GHZ(chan)) { + ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, + AR_AN_RF2G1_CH0_OB, + AR_AN_RF2G1_CH0_OB_S, + pModal->ob); + ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, + AR_AN_RF2G1_CH0_DB, + AR_AN_RF2G1_CH0_DB_S, + pModal->db); + ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, + AR_AN_RF2G1_CH1_OB, + AR_AN_RF2G1_CH1_OB_S, + pModal->ob_ch1); + ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, + AR_AN_RF2G1_CH1_DB, + AR_AN_RF2G1_CH1_DB_S, + pModal->db_ch1); + } else { + ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, + AR_AN_RF5G1_CH0_OB5, + AR_AN_RF5G1_CH0_OB5_S, + pModal->ob); + ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, + AR_AN_RF5G1_CH0_DB5, + AR_AN_RF5G1_CH0_DB5_S, + pModal->db); + ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, + AR_AN_RF5G1_CH1_OB5, + AR_AN_RF5G1_CH1_OB5_S, + pModal->ob_ch1); + ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, + AR_AN_RF5G1_CH1_DB5, + AR_AN_RF5G1_CH1_DB5_S, + pModal->db_ch1); + } + ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, + AR_AN_TOP2_XPABIAS_LVL, + AR_AN_TOP2_XPABIAS_LVL_S, + pModal->xpaBiasLvl); + ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, + AR_AN_TOP2_LOCALBIAS, + AR_AN_TOP2_LOCALBIAS_S, + pModal->local_bias); + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "ForceXPAon: %d\n", + pModal->force_xpaon); + REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, + pModal->force_xpaon); } - REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, - ATH9K_POW_SM(ratesArray[rateHt20_3], 24) - | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) - | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) - | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, - ATH9K_POW_SM(ratesArray[rateHt20_7], 24) - | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) - | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) - | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); + REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, + pModal->switchSettling); + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, + pModal->adcDesiredSize); - if (IS_CHAN_HT40(chan)) { - REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, - ATH9K_POW_SM(ratesArray[rateHt40_3] + - ht40PowerIncForPdadc, 24) - | ATH9K_POW_SM(ratesArray[rateHt40_2] + - ht40PowerIncForPdadc, 16) - | ATH9K_POW_SM(ratesArray[rateHt40_1] + - ht40PowerIncForPdadc, 8) - | ATH9K_POW_SM(ratesArray[rateHt40_0] + - ht40PowerIncForPdadc, 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, - ATH9K_POW_SM(ratesArray[rateHt40_7] + - ht40PowerIncForPdadc, 24) - | ATH9K_POW_SM(ratesArray[rateHt40_6] + - ht40PowerIncForPdadc, 16) - | ATH9K_POW_SM(ratesArray[rateHt40_5] + - ht40PowerIncForPdadc, 8) - | ATH9K_POW_SM(ratesArray[rateHt40_4] + - ht40PowerIncForPdadc, 0)); + if (!AR_SREV_9280_10_OR_LATER(ah)) + REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, + AR_PHY_DESIRED_SZ_PGA, + pModal->pgaDesiredSize); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, - ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) - | ATH9K_POW_SM(ratesArray[rateExtCck], 16) - | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) - | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); - } + REG_WRITE(ah, AR_PHY_RF_CTL4, + SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) + | SM(pModal->txEndToXpaOff, + AR_PHY_RF_CTL4_TX_END_XPAB_OFF) + | SM(pModal->txFrameToXpaOn, + AR_PHY_RF_CTL4_FRAME_XPAA_ON) + | SM(pModal->txFrameToXpaOn, + AR_PHY_RF_CTL4_FRAME_XPAB_ON)); - i = rate6mb; + REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, + pModal->txEndToRxOn); + if (AR_SREV_9280_10_OR_LATER(ah)) { + REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, + pModal->thresh62); + REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, + AR_PHY_EXT_CCA0_THRESH62, + pModal->thresh62); + } else { + REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, + pModal->thresh62); + REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, + AR_PHY_EXT_CCA_THRESH62, + pModal->thresh62); + } - if (IS_CHAN_HT40(chan)) - i = rateHt40_0; - else if (IS_CHAN_HT20(chan)) - i = rateHt20_0; + if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) { + REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, + AR_PHY_TX_END_DATA_START, + pModal->txFrameToDataStart); + REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, + pModal->txFrameToPaOn); + } - if (AR_SREV_9280_10_OR_LATER(ah)) - ah->regulatory.max_power_level = - ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; - else - ah->regulatory.max_power_level = ratesArray[i]; + if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { + if (IS_CHAN_HT40(chan)) + REG_RMW_FIELD(ah, AR_PHY_SETTLING, + AR_PHY_SETTLING_SWITCH, + pModal->swSettleHt40); + } - return 0; -} + if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) { + if (IS_CHAN_HT20(chan)) + REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, + eep->baseEepHeader.dacLpMode); + else if (eep->baseEepHeader.dacHiPwrMode_5G) + REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); + else + REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, + eep->baseEepHeader.dacLpMode); -static int (*ath9k_set_txpower[]) (struct ath_hw *, - struct ath9k_channel *, - u16, u8, u8, u8) = { - ath9k_hw_def_set_txpower, - ath9k_hw_4k_set_txpower -}; + REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, + pModal->miscBits >> 2); + } -int ath9k_hw_set_txpower(struct ath_hw *ah, - struct ath9k_channel *chan, - u16 cfgCtl, - u8 twiceAntennaReduction, - u8 twiceMaxRegulatoryPower, - u8 powerLimit) -{ - return ath9k_set_txpower[ah->ah_eep_map](ah, chan, cfgCtl, - twiceAntennaReduction, twiceMaxRegulatoryPower, - powerLimit); + return true; +#undef AR5416_VER_MASK } -static void ath9k_hw_set_def_addac(struct ath_hw *ah, +static void ath9k_hw_def_set_addac(struct ath_hw *ah, struct ath9k_channel *chan) { #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) @@ -1975,7 +1861,7 @@ static void ath9k_hw_set_def_addac(struct ath_hw *ah, if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) return; - if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7) + if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7) return; pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); @@ -2018,519 +1904,721 @@ static void ath9k_hw_set_def_addac(struct ath_hw *ah, #undef XPA_LVL_FREQ } -static void ath9k_hw_set_4k_addac(struct ath_hw *ah, - struct ath9k_channel *chan) +static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah, + struct ath9k_channel *chan, + struct cal_data_per_freq *pRawDataSet, + u8 *bChans, u16 availPiers, + u16 tPdGainOverlap, int16_t *pMinCalPower, + u16 *pPdGainBoundaries, u8 *pPDADCValues, + u16 numXpdGains) { - struct modal_eep_4k_header *pModal; - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; - u8 biaslevel; + int i, j, k; + int16_t ss; + u16 idxL = 0, idxR = 0, numPiers; + static u8 vpdTableL[AR5416_NUM_PD_GAINS] + [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; + static u8 vpdTableR[AR5416_NUM_PD_GAINS] + [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; + static u8 vpdTableI[AR5416_NUM_PD_GAINS] + [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; - if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) - return; + u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; + u8 minPwrT4[AR5416_NUM_PD_GAINS]; + u8 maxPwrT4[AR5416_NUM_PD_GAINS]; + int16_t vpdStep; + int16_t tmpVal; + u16 sizeCurrVpdTable, maxIndex, tgtIndex; + bool match; + int16_t minDelta = 0; + struct chan_centers centers; + + ath9k_hw_get_channel_centers(ah, chan, ¢ers); + + for (numPiers = 0; numPiers < availPiers; numPiers++) { + if (bChans[numPiers] == AR5416_BCHAN_UNUSED) + break; + } + + match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center, + IS_CHAN_2GHZ(chan)), + bChans, numPiers, &idxL, &idxR); + + if (match) { + for (i = 0; i < numXpdGains; i++) { + minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; + maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; + ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], + pRawDataSet[idxL].pwrPdg[i], + pRawDataSet[idxL].vpdPdg[i], + AR5416_PD_GAIN_ICEPTS, + vpdTableI[i]); + } + } else { + for (i = 0; i < numXpdGains; i++) { + pVpdL = pRawDataSet[idxL].vpdPdg[i]; + pPwrL = pRawDataSet[idxL].pwrPdg[i]; + pVpdR = pRawDataSet[idxR].vpdPdg[i]; + pPwrR = pRawDataSet[idxR].pwrPdg[i]; + + minPwrT4[i] = max(pPwrL[0], pPwrR[0]); + + maxPwrT4[i] = + min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], + pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); + + + ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], + pPwrL, pVpdL, + AR5416_PD_GAIN_ICEPTS, + vpdTableL[i]); + ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], + pPwrR, pVpdR, + AR5416_PD_GAIN_ICEPTS, + vpdTableR[i]); + + for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { + vpdTableI[i][j] = + (u8)(ath9k_hw_interpolate((u16) + FREQ2FBIN(centers. + synth_center, + IS_CHAN_2GHZ + (chan)), + bChans[idxL], bChans[idxR], + vpdTableL[i][j], vpdTableR[i][j])); + } + } + } + + *pMinCalPower = (int16_t)(minPwrT4[0] / 2); + + k = 0; + + for (i = 0; i < numXpdGains; i++) { + if (i == (numXpdGains - 1)) + pPdGainBoundaries[i] = + (u16)(maxPwrT4[i] / 2); + else + pPdGainBoundaries[i] = + (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); + + pPdGainBoundaries[i] = + min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); + + if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { + minDelta = pPdGainBoundaries[0] - 23; + pPdGainBoundaries[0] = 23; + } else { + minDelta = 0; + } + + if (i == 0) { + if (AR_SREV_9280_10_OR_LATER(ah)) + ss = (int16_t)(0 - (minPwrT4[i] / 2)); + else + ss = 0; + } else { + ss = (int16_t)((pPdGainBoundaries[i - 1] - + (minPwrT4[i] / 2)) - + tPdGainOverlap + 1 + minDelta); + } + vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); + vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); + + while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { + tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); + pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); + ss++; + } + + sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); + tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap - + (minPwrT4[i] / 2)); + maxIndex = (tgtIndex < sizeCurrVpdTable) ? + tgtIndex : sizeCurrVpdTable; + + while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { + pPDADCValues[k++] = vpdTableI[i][ss++]; + } - if (ar5416_get_eep_rev(ah) < AR5416_EEP_MINOR_VER_7) - return; + vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - + vpdTableI[i][sizeCurrVpdTable - 2]); + vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); - pModal = &eep->modalHeader; + if (tgtIndex > maxIndex) { + while ((ss <= tgtIndex) && + (k < (AR5416_NUM_PDADC_VALUES - 1))) { + tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + + (ss - maxIndex + 1) * vpdStep)); + pPDADCValues[k++] = (u8)((tmpVal > 255) ? + 255 : tmpVal); + ss++; + } + } + } - if (pModal->xpaBiasLvl != 0xff) { - biaslevel = pModal->xpaBiasLvl; - INI_RA(&ah->ah_iniAddac, 7, 1) = - (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; + while (i < AR5416_PD_GAINS_IN_MASK) { + pPdGainBoundaries[i] = pPdGainBoundaries[i - 1]; + i++; } -} -static void (*ath9k_set_addac[]) (struct ath_hw *, struct ath9k_channel *) = { - ath9k_hw_set_def_addac, - ath9k_hw_set_4k_addac -}; + while (k < AR5416_NUM_PDADC_VALUES) { + pPDADCValues[k] = pPDADCValues[k - 1]; + k++; + } -void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan) -{ - ath9k_set_addac[ah->ah_eep_map](ah, chan); + return; } -/* XXX: Clean me up, make me more legible */ -static bool ath9k_hw_eeprom_set_def_board_values(struct ath_hw *ah, - struct ath9k_channel *chan) +static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, + struct ath9k_channel *chan, + int16_t *pTxPowerIndexOffset) { -#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) - struct modal_eep_header *pModal; - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; - int i, regChainOffset; - u8 txRxAttenLocal; - - pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); - - txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; - - REG_WRITE(ah, AR_PHY_SWITCH_COM, - ath9k_hw_get_eeprom_antenna_cfg(ah, chan)); - - for (i = 0; i < AR5416_MAX_CHAINS; i++) { - if (AR_SREV_9280(ah)) { - if (i >= 2) - break; - } - - if (AR_SREV_5416_V20_OR_LATER(ah) && - (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) - && (i != 0)) - regChainOffset = (i == 1) ? 0x2000 : 0x1000; - else - regChainOffset = i * 0x1000; + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + struct cal_data_per_freq *pRawDataset; + u8 *pCalBChans = NULL; + u16 pdGainOverlap_t2; + static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; + u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; + u16 numPiers, i, j; + int16_t tMinCalPower; + u16 numXpdGain, xpdMask; + u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; + u32 reg32, regOffset, regChainOffset; + int16_t modalIdx; - REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, - pModal->antCtrlChain[i]); + modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; + xpdMask = pEepData->modalHeader[modalIdx].xpdGain; - REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, - (REG_READ(ah, - AR_PHY_TIMING_CTRL4(0) + - regChainOffset) & - ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | - AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | - SM(pModal->iqCalICh[i], - AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | - SM(pModal->iqCalQCh[i], - AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); + if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= + AR5416_EEP_MINOR_VER_2) { + pdGainOverlap_t2 = + pEepData->modalHeader[modalIdx].pdGainOverlap; + } else { + pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), + AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); + } - if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { - if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { - txRxAttenLocal = pModal->txRxAttenCh[i]; - if (AR_SREV_9280_10_OR_LATER(ah)) { - REG_RMW_FIELD(ah, - AR_PHY_GAIN_2GHZ + - regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, - pModal-> - bswMargin[i]); - REG_RMW_FIELD(ah, - AR_PHY_GAIN_2GHZ + - regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN1_DB, - pModal-> - bswAtten[i]); - REG_RMW_FIELD(ah, - AR_PHY_GAIN_2GHZ + - regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, - pModal-> - xatten2Margin[i]); - REG_RMW_FIELD(ah, - AR_PHY_GAIN_2GHZ + - regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN2_DB, - pModal-> - xatten2Db[i]); - } else { - REG_WRITE(ah, - AR_PHY_GAIN_2GHZ + - regChainOffset, - (REG_READ(ah, - AR_PHY_GAIN_2GHZ + - regChainOffset) & - ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) - | SM(pModal-> - bswMargin[i], - AR_PHY_GAIN_2GHZ_BSW_MARGIN)); - REG_WRITE(ah, - AR_PHY_GAIN_2GHZ + - regChainOffset, - (REG_READ(ah, - AR_PHY_GAIN_2GHZ + - regChainOffset) & - ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) - | SM(pModal->bswAtten[i], - AR_PHY_GAIN_2GHZ_BSW_ATTEN)); - } - } - if (AR_SREV_9280_10_OR_LATER(ah)) { - REG_RMW_FIELD(ah, - AR_PHY_RXGAIN + - regChainOffset, - AR9280_PHY_RXGAIN_TXRX_ATTEN, - txRxAttenLocal); - REG_RMW_FIELD(ah, - AR_PHY_RXGAIN + - regChainOffset, - AR9280_PHY_RXGAIN_TXRX_MARGIN, - pModal->rxTxMarginCh[i]); - } else { - REG_WRITE(ah, - AR_PHY_RXGAIN + regChainOffset, - (REG_READ(ah, - AR_PHY_RXGAIN + - regChainOffset) & - ~AR_PHY_RXGAIN_TXRX_ATTEN) | - SM(txRxAttenLocal, - AR_PHY_RXGAIN_TXRX_ATTEN)); - REG_WRITE(ah, - AR_PHY_GAIN_2GHZ + - regChainOffset, - (REG_READ(ah, - AR_PHY_GAIN_2GHZ + - regChainOffset) & - ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | - SM(pModal->rxTxMarginCh[i], - AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); - } - } + if (IS_CHAN_2GHZ(chan)) { + pCalBChans = pEepData->calFreqPier2G; + numPiers = AR5416_NUM_2G_CAL_PIERS; + } else { + pCalBChans = pEepData->calFreqPier5G; + numPiers = AR5416_NUM_5G_CAL_PIERS; } - if (AR_SREV_9280_10_OR_LATER(ah)) { - if (IS_CHAN_2GHZ(chan)) { - ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, - AR_AN_RF2G1_CH0_OB, - AR_AN_RF2G1_CH0_OB_S, - pModal->ob); - ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, - AR_AN_RF2G1_CH0_DB, - AR_AN_RF2G1_CH0_DB_S, - pModal->db); - ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, - AR_AN_RF2G1_CH1_OB, - AR_AN_RF2G1_CH1_OB_S, - pModal->ob_ch1); - ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, - AR_AN_RF2G1_CH1_DB, - AR_AN_RF2G1_CH1_DB_S, - pModal->db_ch1); - } else { - ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, - AR_AN_RF5G1_CH0_OB5, - AR_AN_RF5G1_CH0_OB5_S, - pModal->ob); - ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, - AR_AN_RF5G1_CH0_DB5, - AR_AN_RF5G1_CH0_DB5_S, - pModal->db); - ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, - AR_AN_RF5G1_CH1_OB5, - AR_AN_RF5G1_CH1_OB5_S, - pModal->ob_ch1); - ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, - AR_AN_RF5G1_CH1_DB5, - AR_AN_RF5G1_CH1_DB5_S, - pModal->db_ch1); + numXpdGain = 0; + + for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { + if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { + if (numXpdGain >= AR5416_NUM_PD_GAINS) + break; + xpdGainValues[numXpdGain] = + (u16)(AR5416_PD_GAINS_IN_MASK - i); + numXpdGain++; } - ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, - AR_AN_TOP2_XPABIAS_LVL, - AR_AN_TOP2_XPABIAS_LVL_S, - pModal->xpaBiasLvl); - ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, - AR_AN_TOP2_LOCALBIAS, - AR_AN_TOP2_LOCALBIAS_S, - pModal->local_bias); - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "ForceXPAon: %d\n", - pModal->force_xpaon); - REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, - pModal->force_xpaon); } - REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, - pModal->switchSettling); - REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, - pModal->adcDesiredSize); + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, + (numXpdGain - 1) & 0x3); + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, + xpdGainValues[0]); + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, + xpdGainValues[1]); + REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, + xpdGainValues[2]); - if (!AR_SREV_9280_10_OR_LATER(ah)) - REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, - AR_PHY_DESIRED_SZ_PGA, - pModal->pgaDesiredSize); + for (i = 0; i < AR5416_MAX_CHAINS; i++) { + if (AR_SREV_5416_V20_OR_LATER(ah) && + (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && + (i != 0)) { + regChainOffset = (i == 1) ? 0x2000 : 0x1000; + } else + regChainOffset = i * 0x1000; - REG_WRITE(ah, AR_PHY_RF_CTL4, - SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) - | SM(pModal->txEndToXpaOff, - AR_PHY_RF_CTL4_TX_END_XPAB_OFF) - | SM(pModal->txFrameToXpaOn, - AR_PHY_RF_CTL4_FRAME_XPAA_ON) - | SM(pModal->txFrameToXpaOn, - AR_PHY_RF_CTL4_FRAME_XPAB_ON)); + if (pEepData->baseEepHeader.txMask & (1 << i)) { + if (IS_CHAN_2GHZ(chan)) + pRawDataset = pEepData->calPierData2G[i]; + else + pRawDataset = pEepData->calPierData5G[i]; - REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, - pModal->txEndToRxOn); - if (AR_SREV_9280_10_OR_LATER(ah)) { - REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, - pModal->thresh62); - REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, - AR_PHY_EXT_CCA0_THRESH62, - pModal->thresh62); - } else { - REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, - pModal->thresh62); - REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, - AR_PHY_EXT_CCA_THRESH62, - pModal->thresh62); - } + ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan, + pRawDataset, pCalBChans, + numPiers, pdGainOverlap_t2, + &tMinCalPower, gainBoundaries, + pdadcValues, numXpdGain); - if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) { - REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, - AR_PHY_TX_END_DATA_START, - pModal->txFrameToDataStart); - REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, - pModal->txFrameToPaOn); - } + if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { + REG_WRITE(ah, + AR_PHY_TPCRG5 + regChainOffset, + SM(pdGainOverlap_t2, + AR_PHY_TPCRG5_PD_GAIN_OVERLAP) + | SM(gainBoundaries[0], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) + | SM(gainBoundaries[1], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) + | SM(gainBoundaries[2], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) + | SM(gainBoundaries[3], + AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); + } - if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) { - if (IS_CHAN_HT40(chan)) - REG_RMW_FIELD(ah, AR_PHY_SETTLING, - AR_PHY_SETTLING_SWITCH, - pModal->swSettleHt40); - } + regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; + for (j = 0; j < 32; j++) { + reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | + ((pdadcValues[4 * j + 1] & 0xFF) << 8) | + ((pdadcValues[4 * j + 2] & 0xFF) << 16)| + ((pdadcValues[4 * j + 3] & 0xFF) << 24); + REG_WRITE(ah, regOffset, reg32); - if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) { - if (IS_CHAN_HT20(chan)) - REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, - eep->baseEepHeader.dacLpMode); - else if (eep->baseEepHeader.dacHiPwrMode_5G) - REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); - else - REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, - eep->baseEepHeader.dacLpMode); + DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, + "PDADC (%d,%4x): %4.4x %8.8x\n", + i, regChainOffset, regOffset, + reg32); + DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, + "PDADC: Chain %d | PDADC %3d " + "Value %3d | PDADC %3d Value %3d | " + "PDADC %3d Value %3d | PDADC %3d " + "Value %3d |\n", + i, 4 * j, pdadcValues[4 * j], + 4 * j + 1, pdadcValues[4 * j + 1], + 4 * j + 2, pdadcValues[4 * j + 2], + 4 * j + 3, + pdadcValues[4 * j + 3]); - REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, - pModal->miscBits >> 2); + regOffset += 4; + } + } } + *pTxPowerIndexOffset = 0; + return true; -#undef AR5416_VER_MASK } -static bool ath9k_hw_eeprom_set_4k_board_values(struct ath_hw *ah, - struct ath9k_channel *chan) +static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, + struct ath9k_channel *chan, + int16_t *ratesArray, + u16 cfgCtl, + u16 AntennaReduction, + u16 twiceMaxRegulatoryPower, + u16 powerLimit) { - struct modal_eep_4k_header *pModal; - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; - int regChainOffset; - u8 txRxAttenLocal; - u8 ob[5], db1[5], db2[5]; - u8 ant_div_control1, ant_div_control2; - u32 regVal; +#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ +#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; + static const u16 tpScaleReductionTable[5] = + { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; - pModal = &eep->modalHeader; + int i; + int16_t twiceLargestAntenna; + struct cal_ctl_data *rep; + struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { + 0, { 0, 0, 0, 0} + }; + struct cal_target_power_leg targetPowerOfdmExt = { + 0, { 0, 0, 0, 0} }, targetPowerCckExt = { + 0, { 0, 0, 0, 0 } + }; + struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { + 0, {0, 0, 0, 0} + }; + u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; + u16 ctlModesFor11a[] = + { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 }; + u16 ctlModesFor11g[] = + { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, + CTL_2GHT40 + }; + u16 numCtlModes, *pCtlMode, ctlMode, freq; + struct chan_centers centers; + int tx_chainmask; + u16 twiceMinEdgePower; - txRxAttenLocal = 23; + tx_chainmask = ah->ah_txchainmask; - REG_WRITE(ah, AR_PHY_SWITCH_COM, - ath9k_hw_get_eeprom_antenna_cfg(ah, chan)); + ath9k_hw_get_channel_centers(ah, chan, ¢ers); - regChainOffset = 0; - REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, - pModal->antCtrlChain[0]); + twiceLargestAntenna = max( + pEepData->modalHeader + [IS_CHAN_2GHZ(chan)].antennaGainCh[0], + pEepData->modalHeader + [IS_CHAN_2GHZ(chan)].antennaGainCh[1]); - REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, - (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & - ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | - AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | - SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | - SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); + twiceLargestAntenna = max((u8)twiceLargestAntenna, + pEepData->modalHeader + [IS_CHAN_2GHZ(chan)].antennaGainCh[2]); - if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= - AR5416_EEP_MINOR_VER_3) { - txRxAttenLocal = pModal->txRxAttenCh[0]; - REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); - REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); - REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, - pModal->xatten2Margin[0]); - REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, - AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); + twiceLargestAntenna = (int16_t)min(AntennaReduction - + twiceLargestAntenna, 0); + + maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; + + if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) { + maxRegAllowedPower -= + (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2); + } + + scaledPower = min(powerLimit, maxRegAllowedPower); + + switch (ar5416_get_ntxchains(tx_chainmask)) { + case 1: + break; + case 2: + scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; + break; + case 3: + scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; + break; + } + + scaledPower = max((u16)0, scaledPower); + + if (IS_CHAN_2GHZ(chan)) { + numCtlModes = ARRAY_SIZE(ctlModesFor11g) - + SUB_NUM_CTL_MODES_AT_2G_40; + pCtlMode = ctlModesFor11g; + + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPowerCck, + AR5416_NUM_2G_CCK_TARGET_POWERS, + &targetPowerCck, 4, false); + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPower2G, + AR5416_NUM_2G_20_TARGET_POWERS, + &targetPowerOfdm, 4, false); + ath9k_hw_get_target_powers(ah, chan, + pEepData->calTargetPower2GHT20, + AR5416_NUM_2G_20_TARGET_POWERS, + &targetPowerHt20, 8, false); + + if (IS_CHAN_HT40(chan)) { + numCtlModes = ARRAY_SIZE(ctlModesFor11g); + ath9k_hw_get_target_powers(ah, chan, + pEepData->calTargetPower2GHT40, + AR5416_NUM_2G_40_TARGET_POWERS, + &targetPowerHt40, 8, true); + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPowerCck, + AR5416_NUM_2G_CCK_TARGET_POWERS, + &targetPowerCckExt, 4, true); + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPower2G, + AR5416_NUM_2G_20_TARGET_POWERS, + &targetPowerOfdmExt, 4, true); + } + } else { + numCtlModes = ARRAY_SIZE(ctlModesFor11a) - + SUB_NUM_CTL_MODES_AT_5G_40; + pCtlMode = ctlModesFor11a; + + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPower5G, + AR5416_NUM_5G_20_TARGET_POWERS, + &targetPowerOfdm, 4, false); + ath9k_hw_get_target_powers(ah, chan, + pEepData->calTargetPower5GHT20, + AR5416_NUM_5G_20_TARGET_POWERS, + &targetPowerHt20, 8, false); + + if (IS_CHAN_HT40(chan)) { + numCtlModes = ARRAY_SIZE(ctlModesFor11a); + ath9k_hw_get_target_powers(ah, chan, + pEepData->calTargetPower5GHT40, + AR5416_NUM_5G_40_TARGET_POWERS, + &targetPowerHt40, 8, true); + ath9k_hw_get_legacy_target_powers(ah, chan, + pEepData->calTargetPower5G, + AR5416_NUM_5G_20_TARGET_POWERS, + &targetPowerOfdmExt, 4, true); + } } - REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, - AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); - REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, - AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); + for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { + bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || + (pCtlMode[ctlMode] == CTL_2GHT40); + if (isHt40CtlMode) + freq = centers.synth_center; + else if (pCtlMode[ctlMode] & EXT_ADDITIVE) + freq = centers.ext_center; + else + freq = centers.ctl_center; - if (AR_SREV_9285_11(ah)) - REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); + if (ah->eep_ops->get_eeprom_ver(ah) == 14 && + ah->eep_ops->get_eeprom_rev(ah) <= 2) + twiceMaxEdgePower = AR5416_MAX_RATE_POWER; - /* Initialize Ant Diversity settings from EEPROM */ - if (pModal->version == 3) { - ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf); - ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf); - regVal = REG_READ(ah, 0x99ac); - regVal &= (~(0x7f000000)); - regVal |= ((ant_div_control1 & 0x1) << 24); - regVal |= (((ant_div_control1 >> 1) & 0x1) << 29); - regVal |= (((ant_div_control1 >> 2) & 0x1) << 30); - regVal |= ((ant_div_control2 & 0x3) << 25); - regVal |= (((ant_div_control2 >> 2) & 0x3) << 27); - REG_WRITE(ah, 0x99ac, regVal); - regVal = REG_READ(ah, 0x99ac); - regVal = REG_READ(ah, 0xa208); - regVal &= (~(0x1 << 13)); - regVal |= (((ant_div_control1 >> 3) & 0x1) << 13); - REG_WRITE(ah, 0xa208, regVal); - regVal = REG_READ(ah, 0xa208); - } + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " + "EXT_ADDITIVE %d\n", + ctlMode, numCtlModes, isHt40CtlMode, + (pCtlMode[ctlMode] & EXT_ADDITIVE)); - if (pModal->version >= 2) { - ob[0] = (pModal->ob_01 & 0xf); - ob[1] = (pModal->ob_01 >> 4) & 0xf; - ob[2] = (pModal->ob_234 & 0xf); - ob[3] = ((pModal->ob_234 >> 4) & 0xf); - ob[4] = ((pModal->ob_234 >> 8) & 0xf); + for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " + "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " + "chan %d\n", + i, cfgCtl, pCtlMode[ctlMode], + pEepData->ctlIndex[i], chan->channel); - db1[0] = (pModal->db1_01 & 0xf); - db1[1] = ((pModal->db1_01 >> 4) & 0xf); - db1[2] = (pModal->db1_234 & 0xf); - db1[3] = ((pModal->db1_234 >> 4) & 0xf); - db1[4] = ((pModal->db1_234 >> 8) & 0xf); + if ((((cfgCtl & ~CTL_MODE_M) | + (pCtlMode[ctlMode] & CTL_MODE_M)) == + pEepData->ctlIndex[i]) || + (((cfgCtl & ~CTL_MODE_M) | + (pCtlMode[ctlMode] & CTL_MODE_M)) == + ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { + rep = &(pEepData->ctlData[i]); - db2[0] = (pModal->db2_01 & 0xf); - db2[1] = ((pModal->db2_01 >> 4) & 0xf); - db2[2] = (pModal->db2_234 & 0xf); - db2[3] = ((pModal->db2_234 >> 4) & 0xf); - db2[4] = ((pModal->db2_234 >> 8) & 0xf); + twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq, + rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], + IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); - } else if (pModal->version == 1) { + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + " MATCH-EE_IDX %d: ch %d is2 %d " + "2xMinEdge %d chainmask %d chains %d\n", + i, freq, IS_CHAN_2GHZ(chan), + twiceMinEdgePower, tx_chainmask, + ar5416_get_ntxchains + (tx_chainmask)); + if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { + twiceMaxEdgePower = min(twiceMaxEdgePower, + twiceMinEdgePower); + } else { + twiceMaxEdgePower = twiceMinEdgePower; + break; + } + } + } - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "EEPROM Model version is set to 1 \n"); - ob[0] = (pModal->ob_01 & 0xf); - ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf; - db1[0] = (pModal->db1_01 & 0xf); - db1[1] = db1[2] = db1[3] = - db1[4] = ((pModal->db1_01 >> 4) & 0xf); - db2[0] = (pModal->db2_01 & 0xf); - db2[1] = db2[2] = db2[3] = - db2[4] = ((pModal->db2_01 >> 4) & 0xf); - } else { - int i; - for (i = 0; i < 5; i++) { - ob[i] = pModal->ob_01; - db1[i] = pModal->db1_01; - db2[i] = pModal->db1_01; + minCtlPower = min(twiceMaxEdgePower, scaledPower); + + DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, + " SEL-Min ctlMode %d pCtlMode %d " + "2xMaxEdge %d sP %d minCtlPwr %d\n", + ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, + scaledPower, minCtlPower); + + switch (pCtlMode[ctlMode]) { + case CTL_11B: + for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { + targetPowerCck.tPow2x[i] = + min((u16)targetPowerCck.tPow2x[i], + minCtlPower); + } + break; + case CTL_11A: + case CTL_11G: + for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { + targetPowerOfdm.tPow2x[i] = + min((u16)targetPowerOfdm.tPow2x[i], + minCtlPower); + } + break; + case CTL_5GHT20: + case CTL_2GHT20: + for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { + targetPowerHt20.tPow2x[i] = + min((u16)targetPowerHt20.tPow2x[i], + minCtlPower); + } + break; + case CTL_11B_EXT: + targetPowerCckExt.tPow2x[0] = min((u16) + targetPowerCckExt.tPow2x[0], + minCtlPower); + break; + case CTL_11A_EXT: + case CTL_11G_EXT: + targetPowerOfdmExt.tPow2x[0] = min((u16) + targetPowerOfdmExt.tPow2x[0], + minCtlPower); + break; + case CTL_5GHT40: + case CTL_2GHT40: + for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { + targetPowerHt40.tPow2x[i] = + min((u16)targetPowerHt40.tPow2x[i], + minCtlPower); + } + break; + default: + break; } } - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]); - - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3, - AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]); + ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = + ratesArray[rate18mb] = ratesArray[rate24mb] = + targetPowerOfdm.tPow2x[0]; + ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; + ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; + ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; + ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]); - ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4, - AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]); + for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) + ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; + if (IS_CHAN_2GHZ(chan)) { + ratesArray[rate1l] = targetPowerCck.tPow2x[0]; + ratesArray[rate2s] = ratesArray[rate2l] = + targetPowerCck.tPow2x[1]; + ratesArray[rate5_5s] = ratesArray[rate5_5l] = + targetPowerCck.tPow2x[2]; + ; + ratesArray[rate11s] = ratesArray[rate11l] = + targetPowerCck.tPow2x[3]; + ; + } + if (IS_CHAN_HT40(chan)) { + for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { + ratesArray[rateHt40_0 + i] = + targetPowerHt40.tPow2x[i]; + } + ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; + ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; + ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; + if (IS_CHAN_2GHZ(chan)) { + ratesArray[rateExtCck] = + targetPowerCckExt.tPow2x[0]; + } + } + return true; +} - if (AR_SREV_9285_11(ah)) - REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT); +static int ath9k_hw_def_set_txpower(struct ath_hw *ah, + struct ath9k_channel *chan, + u16 cfgCtl, + u8 twiceAntennaReduction, + u8 twiceMaxRegulatoryPower, + u8 powerLimit) +{ + struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + struct modal_eep_header *pModal = + &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); + int16_t ratesArray[Ar5416RateSize]; + int16_t txPowerIndexOffset = 0; + u8 ht40PowerIncForPdadc = 2; + int i; - REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, - pModal->switchSettling); - REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, - pModal->adcDesiredSize); + memset(ratesArray, 0, sizeof(ratesArray)); - REG_WRITE(ah, AR_PHY_RF_CTL4, - SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | - SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | - SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | - SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); + if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= + AR5416_EEP_MINOR_VER_2) { + ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; + } - REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, - pModal->txEndToRxOn); - REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, - pModal->thresh62); - REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, - pModal->thresh62); + if (!ath9k_hw_set_def_power_per_rate_table(ah, chan, + &ratesArray[0], cfgCtl, + twiceAntennaReduction, + twiceMaxRegulatoryPower, + powerLimit)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "ath9k_hw_set_txpower: unable to set " + "tx power per rate table\n"); + return -EIO; + } - if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= - AR5416_EEP_MINOR_VER_2) { - REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START, - pModal->txFrameToDataStart); - REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, - pModal->txFrameToPaOn); + if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) { + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "ath9k_hw_set_txpower: unable to set power table\n"); + return -EIO; } - if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= - AR5416_EEP_MINOR_VER_3) { - if (IS_CHAN_HT40(chan)) - REG_RMW_FIELD(ah, AR_PHY_SETTLING, - AR_PHY_SETTLING_SWITCH, - pModal->swSettleHt40); + for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { + ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); + if (ratesArray[i] > AR5416_MAX_RATE_POWER) + ratesArray[i] = AR5416_MAX_RATE_POWER; } - return true; -} + if (AR_SREV_9280_10_OR_LATER(ah)) { + for (i = 0; i < Ar5416RateSize; i++) + ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; + } -static bool (*ath9k_eeprom_set_board_values[])(struct ath_hw *, - struct ath9k_channel *) = { - ath9k_hw_eeprom_set_def_board_values, - ath9k_hw_eeprom_set_4k_board_values -}; + REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, + ATH9K_POW_SM(ratesArray[rate18mb], 24) + | ATH9K_POW_SM(ratesArray[rate12mb], 16) + | ATH9K_POW_SM(ratesArray[rate9mb], 8) + | ATH9K_POW_SM(ratesArray[rate6mb], 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, + ATH9K_POW_SM(ratesArray[rate54mb], 24) + | ATH9K_POW_SM(ratesArray[rate48mb], 16) + | ATH9K_POW_SM(ratesArray[rate36mb], 8) + | ATH9K_POW_SM(ratesArray[rate24mb], 0)); -bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah, - struct ath9k_channel *chan) -{ - return ath9k_eeprom_set_board_values[ah->ah_eep_map](ah, chan); -} + if (IS_CHAN_2GHZ(chan)) { + REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, + ATH9K_POW_SM(ratesArray[rate2s], 24) + | ATH9K_POW_SM(ratesArray[rate2l], 16) + | ATH9K_POW_SM(ratesArray[rateXr], 8) + | ATH9K_POW_SM(ratesArray[rate1l], 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, + ATH9K_POW_SM(ratesArray[rate11s], 24) + | ATH9K_POW_SM(ratesArray[rate11l], 16) + | ATH9K_POW_SM(ratesArray[rate5_5s], 8) + | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); + } -static u16 ath9k_hw_get_def_eeprom_antenna_cfg(struct ath_hw *ah, - struct ath9k_channel *chan) -{ - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; - struct modal_eep_header *pModal = - &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, + ATH9K_POW_SM(ratesArray[rateHt20_3], 24) + | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) + | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) + | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, + ATH9K_POW_SM(ratesArray[rateHt20_7], 24) + | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) + | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) + | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); - return pModal->antCtrlCommon & 0xFFFF; -} + if (IS_CHAN_HT40(chan)) { + REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, + ATH9K_POW_SM(ratesArray[rateHt40_3] + + ht40PowerIncForPdadc, 24) + | ATH9K_POW_SM(ratesArray[rateHt40_2] + + ht40PowerIncForPdadc, 16) + | ATH9K_POW_SM(ratesArray[rateHt40_1] + + ht40PowerIncForPdadc, 8) + | ATH9K_POW_SM(ratesArray[rateHt40_0] + + ht40PowerIncForPdadc, 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, + ATH9K_POW_SM(ratesArray[rateHt40_7] + + ht40PowerIncForPdadc, 24) + | ATH9K_POW_SM(ratesArray[rateHt40_6] + + ht40PowerIncForPdadc, 16) + | ATH9K_POW_SM(ratesArray[rateHt40_5] + + ht40PowerIncForPdadc, 8) + | ATH9K_POW_SM(ratesArray[rateHt40_4] + + ht40PowerIncForPdadc, 0)); -static u16 ath9k_hw_get_4k_eeprom_antenna_cfg(struct ath_hw *ah, - struct ath9k_channel *chan) -{ - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; - struct modal_eep_4k_header *pModal = &eep->modalHeader; + REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, + ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) + | ATH9K_POW_SM(ratesArray[rateExtCck], 16) + | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) + | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); + } - return pModal->antCtrlCommon & 0xFFFF; -} + REG_WRITE(ah, AR_PHY_POWER_TX_SUB, + ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) + | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); -static u16 (*ath9k_get_eeprom_antenna_cfg[])(struct ath_hw *, - struct ath9k_channel *) = { - ath9k_hw_get_def_eeprom_antenna_cfg, - ath9k_hw_get_4k_eeprom_antenna_cfg -}; + i = rate6mb; -u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah, - struct ath9k_channel *chan) -{ - return ath9k_get_eeprom_antenna_cfg[ah->ah_eep_map](ah, chan); -} + if (IS_CHAN_HT40(chan)) + i = rateHt40_0; + else if (IS_CHAN_HT20(chan)) + i = rateHt20_0; -static u8 ath9k_hw_get_4k_num_ant_config(struct ath_hw *ah, - enum ieee80211_band freq_band) -{ - return 1; + if (AR_SREV_9280_10_OR_LATER(ah)) + ah->regulatory.max_power_level = + ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; + else + ah->regulatory.max_power_level = ratesArray[i]; + + return 0; } -static u8 ath9k_hw_get_def_num_ant_config(struct ath_hw *ah, +static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band) { struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; @@ -2548,24 +2636,21 @@ static u8 ath9k_hw_get_def_num_ant_config(struct ath_hw *ah, return num_ant_config; } -static u8 (*ath9k_get_num_ant_config[])(struct ath_hw *, - enum ieee80211_band) = { - ath9k_hw_get_def_num_ant_config, - ath9k_hw_get_4k_num_ant_config -}; - -u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah, - enum ieee80211_band freq_band) +static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah, + struct ath9k_channel *chan) { - return ath9k_get_num_ant_config[ah->ah_eep_map](ah, freq_band); + struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct modal_eep_header *pModal = + &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); + + return pModal->antCtrlCommon & 0xFFFF; } -u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz) +u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) { -#define EEP_MAP4K_SPURCHAN \ - (ah->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) #define EEP_DEF_SPURCHAN \ (ah->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) + u16 spur_val = AR_NO_SPUR; DPRINTF(ah->ah_sc, ATH_DBG_ANI, @@ -2581,142 +2666,45 @@ u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz) "Getting spur val from new loc. %d\n", spur_val); break; case SPUR_ENABLE_EEPROM: - if (ah->ah_eep_map == EEP_MAP_4KBITS) - spur_val = EEP_MAP4K_SPURCHAN; - else - spur_val = EEP_DEF_SPURCHAN; + spur_val = EEP_DEF_SPURCHAN; break; - } return spur_val; -#undef EEP_DEF_SPURCHAN -#undef EEP_MAP4K_SPURCHAN -} - -static u32 ath9k_hw_get_eeprom_4k(struct ath_hw *ah, - enum eeprom_param param) -{ - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; - struct modal_eep_4k_header *pModal = &eep->modalHeader; - struct base_eep_header_4k *pBase = &eep->baseEepHeader; - - switch (param) { - case EEP_NFTHRESH_2: - return pModal[1].noiseFloorThreshCh[0]; - case AR_EEPROM_MAC(0): - return pBase->macAddr[0] << 8 | pBase->macAddr[1]; - case AR_EEPROM_MAC(1): - return pBase->macAddr[2] << 8 | pBase->macAddr[3]; - case AR_EEPROM_MAC(2): - return pBase->macAddr[4] << 8 | pBase->macAddr[5]; - case EEP_REG_0: - return pBase->regDmn[0]; - case EEP_REG_1: - return pBase->regDmn[1]; - case EEP_OP_CAP: - return pBase->deviceCap; - case EEP_OP_MODE: - return pBase->opCapFlags; - case EEP_RF_SILENT: - return pBase->rfSilent; - case EEP_OB_2: - return pModal->ob_01; - case EEP_DB_2: - return pModal->db1_01; - case EEP_MINOR_REV: - return pBase->version & AR5416_EEP_VER_MINOR_MASK; - case EEP_TX_MASK: - return pBase->txMask; - case EEP_RX_MASK: - return pBase->rxMask; - default: - return 0; - } -} - -static u32 ath9k_hw_get_eeprom_def(struct ath_hw *ah, - enum eeprom_param param) -{ -#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; - struct modal_eep_header *pModal = eep->modalHeader; - struct base_eep_header *pBase = &eep->baseEepHeader; - switch (param) { - case EEP_NFTHRESH_5: - return pModal[0].noiseFloorThreshCh[0]; - case EEP_NFTHRESH_2: - return pModal[1].noiseFloorThreshCh[0]; - case AR_EEPROM_MAC(0): - return pBase->macAddr[0] << 8 | pBase->macAddr[1]; - case AR_EEPROM_MAC(1): - return pBase->macAddr[2] << 8 | pBase->macAddr[3]; - case AR_EEPROM_MAC(2): - return pBase->macAddr[4] << 8 | pBase->macAddr[5]; - case EEP_REG_0: - return pBase->regDmn[0]; - case EEP_REG_1: - return pBase->regDmn[1]; - case EEP_OP_CAP: - return pBase->deviceCap; - case EEP_OP_MODE: - return pBase->opCapFlags; - case EEP_RF_SILENT: - return pBase->rfSilent; - case EEP_OB_5: - return pModal[0].ob; - case EEP_DB_5: - return pModal[0].db; - case EEP_OB_2: - return pModal[1].ob; - case EEP_DB_2: - return pModal[1].db; - case EEP_MINOR_REV: - return AR5416_VER_MASK; - case EEP_TX_MASK: - return pBase->txMask; - case EEP_RX_MASK: - return pBase->rxMask; - case EEP_RXGAIN_TYPE: - return pBase->rxGainType; - case EEP_TXGAIN_TYPE: - return pBase->txGainType; - case EEP_DAC_HPWR_5G: - if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) - return pBase->dacHiPwrMode_5G; - else - return 0; - default: - return 0; - } -#undef AR5416_VER_MASK +#undef EEP_DEF_SPURCHAN } -static u32 (*ath9k_get_eeprom[])(struct ath_hw *, enum eeprom_param) = { - ath9k_hw_get_eeprom_def, - ath9k_hw_get_eeprom_4k +struct eeprom_ops eep_def_ops = { + .check_eeprom = ath9k_hw_def_check_eeprom, + .get_eeprom = ath9k_hw_def_get_eeprom, + .fill_eeprom = ath9k_hw_def_fill_eeprom, + .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver, + .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev, + .get_num_ant_config = ath9k_hw_def_get_num_ant_config, + .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg, + .set_board_values = ath9k_hw_def_set_board_values, + .set_addac = ath9k_hw_def_set_addac, + .set_txpower = ath9k_hw_def_set_txpower, + .get_spur_channel = ath9k_hw_def_get_spur_channel }; -u32 ath9k_hw_get_eeprom(struct ath_hw *ah, - enum eeprom_param param) -{ - return ath9k_get_eeprom[ah->ah_eep_map](ah, param); -} - int ath9k_hw_eeprom_attach(struct ath_hw *ah) { int status; - if (AR_SREV_9285(ah)) + if (AR_SREV_9285(ah)) { ah->ah_eep_map = EEP_MAP_4KBITS; - else + ah->eep_ops = &eep_4k_ops; + } else { ah->ah_eep_map = EEP_MAP_DEFAULT; + ah->eep_ops = &eep_def_ops; + } - if (!ath9k_hw_fill_eeprom(ah)) + if (!ah->eep_ops->fill_eeprom(ah)) return -EIO; - status = ath9k_hw_check_eeprom(ah); + status = ah->eep_ops->check_eeprom(ah); return status; } diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 47c8eea85e83..7a4266f29eaa 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -464,38 +464,10 @@ struct eeprom_ops { u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); }; -#define ar5416_get_eep_ver(_ah) \ - (((_ah)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) -#define ar5416_get_eep_rev(_ah) \ - (((_ah)->ah_eeprom.def.baseEepHeader.version) & 0xFFF) #define ar5416_get_ntxchains(_txchainmask) \ - (((_txchainmask >> 2) & 1) + \ + (((_txchainmask >> 2) & 1) + \ ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) -#define ar5416_get_eep4k_ver(_ah) \ - (((_ah)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) -#define ar5416_get_eep4k_rev(_ah) \ - (((_ah)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) - -int ath9k_hw_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, - u16 cfgCtl, u8 twiceAntennaReduction, - u8 twiceMaxRegulatoryPower, u8 powerLimit); -void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan); -bool ath9k_hw_set_power_per_rate_table(struct ath_hw *ah, - struct ath9k_channel *chan, int16_t *ratesArray, - u16 cfgCtl, u8 AntennaReduction, - u8 twiceMaxRegulatoryPower, u8 powerLimit); -bool ath9k_hw_set_power_cal_table(struct ath_hw *ah, - struct ath9k_channel *chan, - int16_t *pTxPowerIndexOffset); -bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah, - struct ath9k_channel *chan); -u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah, - struct ath9k_channel *chan); -u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah, - enum ieee80211_band freq_band); -u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz); -u32 ath9k_hw_get_eeprom(struct ath_hw *ah, enum eeprom_param param); int ath9k_hw_eeprom_attach(struct ath_hw *ah); #endif /* EEPROM_H */ diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index ba908e9f1a8e..f744d8cd8307 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -487,7 +487,7 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah) sum = 0; for (i = 0; i < 3; i++) { - eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i)); + eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); sum += eeval; ah->macaddr[2 * i] = eeval >> 8; ah->macaddr[2 * i + 1] = eeval & 0xff; @@ -506,8 +506,8 @@ static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) { u32 rxgain_type; - if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { - rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE); + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { + rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) INIT_INI_ARRAY(&ah->ah_iniModesRxGain, @@ -532,8 +532,8 @@ static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) { u32 txgain_type; - if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { - txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE); + if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { + txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) INIT_INI_ARRAY(&ah->ah_iniModesTxGain, @@ -1238,7 +1238,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, REG_WRITE(ah, AR_PHY(0), 0x00000007); REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); - ath9k_hw_set_addac(ah, chan); + ah->eep_ops->set_addac(ah, chan); if (AR_SREV_5416_V22_OR_LATER(ah)) { REG_WRITE_ARRAY(&ah->ah_iniAddac, 1, regWrites); @@ -1306,12 +1306,12 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ath9k_hw_set_regs(ah, chan, macmode); ath9k_hw_init_chain_masks(ah); - status = ath9k_hw_set_txpower(ah, chan, - ath9k_regd_get_ctl(ah, chan), - channel->max_antenna_gain * 2, - channel->max_power * 2, - min((u32) MAX_RATE_POWER, - (u32) ah->regulatory.power_limit)); + status = ah->eep_ops->set_txpower(ah, chan, + ath9k_regd_get_ctl(ah, chan), + channel->max_antenna_gain * 2, + channel->max_power * 2, + min((u32) MAX_RATE_POWER, + (u32) ah->regulatory.power_limit)); if (status != 0) { DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "error init'ing transmit power\n"); @@ -1632,12 +1632,12 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah, } } - if (ath9k_hw_set_txpower(ah, chan, - ath9k_regd_get_ctl(ah, chan), - channel->max_antenna_gain * 2, - channel->max_power * 2, - min((u32) MAX_RATE_POWER, - (u32) ah->regulatory.power_limit)) != 0) { + if (ah->eep_ops->set_txpower(ah, chan, + ath9k_regd_get_ctl(ah, chan), + channel->max_antenna_gain * 2, + channel->max_power * 2, + min((u32) MAX_RATE_POWER, + (u32) ah->regulatory.power_limit)) != 0) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "error init'ing transmit power\n"); return false; @@ -1703,7 +1703,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel ah->ah_config.spurmode = SPUR_ENABLE_EEPROM; for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { - cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); if (is2GHz) cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; @@ -1946,7 +1946,7 @@ static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan memset(&mask_p, 0, sizeof(int8_t) * 123); for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { - cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz); + cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); if (AR_NO_SPUR == cur_bb_spur) break; cur_bb_spur = cur_bb_spur - (chan->channel * 10); @@ -2211,7 +2211,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, else ath9k_hw_spur_mitigate(ah, chan); - if (!ath9k_hw_eeprom_set_board_values(ah, chan)) { + if (!ah->eep_ops->set_board_values(ah, chan)) { DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "error setting board options\n"); return -EIO; @@ -3092,14 +3092,14 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) struct ath9k_hw_capabilities *pCap = &ah->ah_caps; u16 capField = 0, eeval; - eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0); + eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); ah->regulatory.current_rd = eeval; - eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1); + eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); ah->regulatory.current_rd_ext = eeval; - capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP); + capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); if (ah->ah_opmode != NL80211_IFTYPE_AP && ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { @@ -3112,7 +3112,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) "regdomain mapped to 0x%x\n", ah->regulatory.current_rd); } - eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE); + eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); if (eeval & AR5416_OPFLAGS_11A) { @@ -3146,11 +3146,11 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) } } - pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK); + pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); if ((ah->ah_isPciExpress) || (eeval & AR5416_OPFLAGS_11A)) { pCap->rx_chainmask = - ath9k_hw_get_eeprom(ah, EEP_RX_MASK); + ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); } else { pCap->rx_chainmask = (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7; @@ -3226,7 +3226,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) - ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT); + ah->ah_rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { ah->ah_rfkill_gpio = MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); @@ -3266,9 +3266,9 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; pCap->num_antcfg_5ghz = - ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); + ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); pCap->num_antcfg_2ghz = - ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); + ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) { pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX; @@ -3613,12 +3613,12 @@ bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER); - if (ath9k_hw_set_txpower(ah, chan, - ath9k_regd_get_ctl(ah, chan), - channel->max_antenna_gain * 2, - channel->max_power * 2, - min((u32) MAX_RATE_POWER, - (u32) ah->regulatory.power_limit)) != 0) + if (ah->eep_ops->set_txpower(ah, chan, + ath9k_regd_get_ctl(ah, chan), + channel->max_antenna_gain * 2, + channel->max_power * 2, + min((u32) MAX_RATE_POWER, + (u32) ah->regulatory.power_limit)) != 0) return false; return true; diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index 84914e205892..f8f46db665c2 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -430,6 +430,7 @@ struct ath_hw { struct ar5416_eeprom_def def; struct ar5416_eeprom_4k map4k; } ah_eeprom; + const struct eeprom_ops *eep_ops; bool sw_mgmt_crypto; bool ah_isPciExpress; diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c index da4165b8d6be..5a42969b35a6 100644 --- a/drivers/net/wireless/ath9k/phy.c +++ b/drivers/net/wireless/ath9k/phy.c @@ -205,7 +205,7 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, if (AR_SREV_9280_10_OR_LATER(ah)) return true; - eepMinorRev = ath9k_hw_get_eeprom(ah, EEP_MINOR_REV); + eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); RF_BANK_SETUP(ah->ah_analogBank0Data, &ah->ah_iniBank0, 1); @@ -225,15 +225,15 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, if (eepMinorRev >= 2) { if (IS_CHAN_2GHZ(chan)) { - ob2GHz = ath9k_hw_get_eeprom(ah, EEP_OB_2); - db2GHz = ath9k_hw_get_eeprom(ah, EEP_DB_2); + ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); + db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ob2GHz, 3, 197, 0); ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, db2GHz, 3, 194, 0); } else { - ob5GHz = ath9k_hw_get_eeprom(ah, EEP_OB_5); - db5GHz = ath9k_hw_get_eeprom(ah, EEP_DB_5); + ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); + db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, ob5GHz, 3, 203, 0); ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, -- cgit v1.2.3 From 2660b81a378ab227b78c4cc618453fa7e19a7c7b Mon Sep 17 00:00:00 2001 From: Sujith Date: Mon, 9 Feb 2009 13:27:26 +0530 Subject: ath9k: Remove all the useless ah_ variable prefixes Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/ani.c | 186 +++++------ drivers/net/wireless/ath9k/ani.h | 6 +- drivers/net/wireless/ath9k/ath9k.h | 6 +- drivers/net/wireless/ath9k/beacon.c | 26 +- drivers/net/wireless/ath9k/calib.c | 122 ++++---- drivers/net/wireless/ath9k/calib.h | 14 +- drivers/net/wireless/ath9k/eeprom.c | 102 +++--- drivers/net/wireless/ath9k/eeprom.h | 2 +- drivers/net/wireless/ath9k/hw.c | 602 ++++++++++++++++++------------------ drivers/net/wireless/ath9k/hw.h | 216 +++++++------ drivers/net/wireless/ath9k/mac.c | 94 +++--- drivers/net/wireless/ath9k/main.c | 92 +++--- drivers/net/wireless/ath9k/pci.c | 4 +- drivers/net/wireless/ath9k/phy.c | 176 +++++------ drivers/net/wireless/ath9k/phy.h | 2 +- drivers/net/wireless/ath9k/rc.c | 12 +- drivers/net/wireless/ath9k/recv.c | 18 +- drivers/net/wireless/ath9k/xmit.c | 6 +- 18 files changed, 841 insertions(+), 845 deletions(-) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c index 6bd2d5766019..d4df7e611df5 100644 --- a/drivers/net/wireless/ath9k/ani.c +++ b/drivers/net/wireless/ath9k/ani.c @@ -21,12 +21,12 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, { int i; - for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { - if (ah->ah_ani[i].c && - ah->ah_ani[i].c->channel == chan->channel) + for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { + if (ah->ani[i].c && + ah->ani[i].c->channel == chan->channel) return i; - if (ah->ah_ani[i].c == NULL) { - ah->ah_ani[i].c = chan; + if (ah->ani[i].c == NULL) { + ah->ani[i].c = chan; return i; } } @@ -40,37 +40,37 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, static bool ath9k_hw_ani_control(struct ath_hw *ah, enum ath9k_ani_cmd cmd, int param) { - struct ar5416AniState *aniState = ah->ah_curani; + struct ar5416AniState *aniState = ah->curani; - switch (cmd & ah->ah_ani_function) { + switch (cmd & ah->ani_function) { case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{ u32 level = param; - if (level >= ARRAY_SIZE(ah->ah_totalSizeDesired)) { + if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "level out of range (%u > %u)\n", level, - (unsigned)ARRAY_SIZE(ah->ah_totalSizeDesired)); + (unsigned)ARRAY_SIZE(ah->totalSizeDesired)); return false; } REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_TOT_DES, - ah->ah_totalSizeDesired[level]); + ah->totalSizeDesired[level]); REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_LOW, - ah->ah_coarseLow[level]); + ah->coarse_low[level]); REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1, AR_PHY_AGC_CTL1_COARSE_HIGH, - ah->ah_coarseHigh[level]); + ah->coarse_high[level]); REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, AR_PHY_FIND_SIG_FIRPWR, - ah->ah_firpwr[level]); + ah->firpwr[level]); if (level > aniState->noiseImmunityLevel) - ah->ah_stats.ast_ani_niup++; + ah->stats.ast_ani_niup++; else if (level < aniState->noiseImmunityLevel) - ah->ah_stats.ast_ani_nidown++; + ah->stats.ast_ani_nidown++; aniState->noiseImmunityLevel = level; break; } @@ -124,9 +124,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, if (!on != aniState->ofdmWeakSigDetectOff) { if (on) - ah->ah_stats.ast_ani_ofdmon++; + ah->stats.ast_ani_ofdmon++; else - ah->ah_stats.ast_ani_ofdmoff++; + ah->stats.ast_ani_ofdmoff++; aniState->ofdmWeakSigDetectOff = !on; } break; @@ -140,9 +140,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, weakSigThrCck[high]); if (high != aniState->cckWeakSigThreshold) { if (high) - ah->ah_stats.ast_ani_cckhigh++; + ah->stats.ast_ani_cckhigh++; else - ah->ah_stats.ast_ani_ccklow++; + ah->stats.ast_ani_ccklow++; aniState->cckWeakSigThreshold = high; } break; @@ -162,9 +162,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, AR_PHY_FIND_SIG_FIRSTEP, firstep[level]); if (level > aniState->firstepLevel) - ah->ah_stats.ast_ani_stepup++; + ah->stats.ast_ani_stepup++; else if (level < aniState->firstepLevel) - ah->ah_stats.ast_ani_stepdown++; + ah->stats.ast_ani_stepdown++; aniState->firstepLevel = level; break; } @@ -185,9 +185,9 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah, AR_PHY_TIMING5_CYCPWR_THR1, cycpwrThr1[level]); if (level > aniState->spurImmunityLevel) - ah->ah_stats.ast_ani_spurup++; + ah->stats.ast_ani_spurup++; else if (level < aniState->spurImmunityLevel) - ah->ah_stats.ast_ani_spurdown++; + ah->stats.ast_ani_spurdown++; aniState->spurImmunityLevel = level; break; } @@ -235,10 +235,10 @@ static void ath9k_ani_restart(struct ath_hw *ah) if (!DO_ANI(ah)) return; - aniState = ah->ah_curani; + aniState = ah->curani; aniState->listenTime = 0; - if (ah->ah_hasHwPhyCounters) { + if (ah->has_hw_phycounters) { if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { aniState->ofdmPhyErrBase = 0; DPRINTF(ah->ah_sc, ATH_DBG_ANI, @@ -279,7 +279,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) if (!DO_ANI(ah)) return; - aniState = ah->ah_curani; + aniState = ah->curani; if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, @@ -295,7 +295,7 @@ static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hw *ah) } } - if (ah->ah_opmode == NL80211_IFTYPE_AP) { + if (ah->opmode == NL80211_IFTYPE_AP) { if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel + 1); @@ -350,14 +350,14 @@ static void ath9k_hw_ani_cck_err_trigger(struct ath_hw *ah) if (!DO_ANI(ah)) return; - aniState = ah->ah_curani; + aniState = ah->curani; if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) { if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, aniState->noiseImmunityLevel + 1)) { return; } } - if (ah->ah_opmode == NL80211_IFTYPE_AP) { + if (ah->opmode == NL80211_IFTYPE_AP) { if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) { ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel + 1); @@ -383,9 +383,9 @@ static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah) struct ar5416AniState *aniState; int32_t rssi; - aniState = ah->ah_curani; + aniState = ah->curani; - if (ah->ah_opmode == NL80211_IFTYPE_AP) { + if (ah->opmode == NL80211_IFTYPE_AP) { if (aniState->firstepLevel > 0) { if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel - 1)) @@ -441,11 +441,11 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah) rxFrameCount = REG_READ(ah, AR_RFCNT); cycleCount = REG_READ(ah, AR_CCCNT); - aniState = ah->ah_curani; + aniState = ah->curani; if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) { listenTime = 0; - ah->ah_stats.ast_ani_lzero++; + ah->stats.ast_ani_lzero++; } else { int32_t ccdelta = cycleCount - aniState->cycleCount; int32_t rfdelta = rxFrameCount - aniState->rxFrameCount; @@ -462,21 +462,21 @@ static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah) void ath9k_ani_reset(struct ath_hw *ah) { struct ar5416AniState *aniState; - struct ath9k_channel *chan = ah->ah_curchan; + struct ath9k_channel *chan = ah->curchan; int index; if (!DO_ANI(ah)) return; index = ath9k_hw_get_ani_channel_idx(ah, chan); - aniState = &ah->ah_ani[index]; - ah->ah_curani = aniState; + aniState = &ah->ani[index]; + ah->curani = aniState; - if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION - && ah->ah_opmode != NL80211_IFTYPE_ADHOC) { + if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION + && ah->opmode != NL80211_IFTYPE_ADHOC) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, - "Reset ANI state opmode %u\n", ah->ah_opmode); - ah->ah_stats.ast_ani_reset++; + "Reset ANI state opmode %u\n", ah->opmode); + ah->stats.ast_ani_reset++; ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0); ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0); @@ -489,15 +489,15 @@ void ath9k_ani_reset(struct ath_hw *ah) ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) | ATH9K_RX_FILTER_PHYERR); - if (ah->ah_opmode == NL80211_IFTYPE_AP) { - ah->ah_curani->ofdmTrigHigh = - ah->ah_config.ofdm_trig_high; - ah->ah_curani->ofdmTrigLow = - ah->ah_config.ofdm_trig_low; - ah->ah_curani->cckTrigHigh = - ah->ah_config.cck_trig_high; - ah->ah_curani->cckTrigLow = - ah->ah_config.cck_trig_low; + if (ah->opmode == NL80211_IFTYPE_AP) { + ah->curani->ofdmTrigHigh = + ah->config.ofdm_trig_high; + ah->curani->ofdmTrigLow = + ah->config.ofdm_trig_low; + ah->curani->cckTrigHigh = + ah->config.cck_trig_high; + ah->curani->cckTrigLow = + ah->config.cck_trig_low; } ath9k_ani_restart(ah); return; @@ -518,7 +518,7 @@ void ath9k_ani_reset(struct ath_hw *ah) if (aniState->firstepLevel != 0) ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, aniState->firstepLevel); - if (ah->ah_hasHwPhyCounters) { + if (ah->has_hw_phycounters) { ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) & ~ATH9K_RX_FILTER_PHYERR); ath9k_ani_restart(ah); @@ -542,19 +542,19 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, if (!DO_ANI(ah)) return; - aniState = ah->ah_curani; - ah->ah_stats.ast_nodestats = *stats; + aniState = ah->curani; + ah->stats.ast_nodestats = *stats; listenTime = ath9k_hw_ani_get_listen_time(ah); if (listenTime < 0) { - ah->ah_stats.ast_ani_lneg++; + ah->stats.ast_ani_lneg++; ath9k_ani_restart(ah); return; } aniState->listenTime += listenTime; - if (ah->ah_hasHwPhyCounters) { + if (ah->has_hw_phycounters) { u32 phyCnt1, phyCnt2; u32 ofdmPhyErrCnt, cckPhyErrCnt; @@ -591,24 +591,24 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, } ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; - ah->ah_stats.ast_ani_ofdmerrs += + ah->stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount; aniState->ofdmPhyErrCount = ofdmPhyErrCnt; cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; - ah->ah_stats.ast_ani_cckerrs += + ah->stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount; aniState->cckPhyErrCount = cckPhyErrCnt; } - if (aniState->listenTime > 5 * ah->ah_aniPeriod) { + if (aniState->listenTime > 5 * ah->aniperiod) { if (aniState->ofdmPhyErrCount <= aniState->listenTime * aniState->ofdmTrigLow / 1000 && aniState->cckPhyErrCount <= aniState->listenTime * aniState->cckTrigLow / 1000) ath9k_hw_ani_lower_immunity(ah); ath9k_ani_restart(ah); - } else if (aniState->listenTime > ah->ah_aniPeriod) { + } else if (aniState->listenTime > ah->aniperiod) { if (aniState->ofdmPhyErrCount > aniState->listenTime * aniState->ofdmTrigHigh / 1000) { ath9k_hw_ani_ofdm_err_trigger(ah); @@ -624,7 +624,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, bool ath9k_hw_phycounters(struct ath_hw *ah) { - return ah->ah_hasHwPhyCounters ? true : false; + return ah->has_hw_phycounters ? true : false; } void ath9k_enable_mib_counters(struct ath_hw *ah) @@ -712,7 +712,7 @@ void ath9k_hw_procmibevent(struct ath_hw *ah, /* Clear the mib counters and save them in the stats */ ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); - ah->ah_stats.ast_nodestats = *stats; + ah->stats.ast_nodestats = *stats; if (!DO_ANI(ah)) return; @@ -722,17 +722,17 @@ void ath9k_hw_procmibevent(struct ath_hw *ah, phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) || ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) { - struct ar5416AniState *aniState = ah->ah_curani; + struct ar5416AniState *aniState = ah->curani; u32 ofdmPhyErrCnt, cckPhyErrCnt; /* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */ ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase; - ah->ah_stats.ast_ani_ofdmerrs += + ah->stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount; aniState->ofdmPhyErrCount = ofdmPhyErrCnt; cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase; - ah->ah_stats.ast_ani_cckerrs += + ah->stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount; aniState->cckPhyErrCount = cckPhyErrCnt; @@ -761,10 +761,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah) const int firpwr[] = { -78, -78, -78, -78, -80 }; for (i = 0; i < 5; i++) { - ah->ah_totalSizeDesired[i] = totalSizeDesired[i]; - ah->ah_coarseHigh[i] = coarseHigh[i]; - ah->ah_coarseLow[i] = coarseLow[i]; - ah->ah_firpwr[i] = firpwr[i]; + ah->totalSizeDesired[i] = totalSizeDesired[i]; + ah->coarse_high[i] = coarseHigh[i]; + ah->coarse_low[i] = coarseLow[i]; + ah->firpwr[i] = firpwr[i]; } } @@ -774,50 +774,50 @@ void ath9k_hw_ani_attach(struct ath_hw *ah) DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n"); - ah->ah_hasHwPhyCounters = 1; - - memset(ah->ah_ani, 0, sizeof(ah->ah_ani)); - for (i = 0; i < ARRAY_SIZE(ah->ah_ani); i++) { - ah->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; - ah->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; - ah->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; - ah->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; - ah->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; - ah->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; - ah->ah_ani[i].ofdmWeakSigDetectOff = + ah->has_hw_phycounters = 1; + + memset(ah->ani, 0, sizeof(ah->ani)); + for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { + ah->ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH; + ah->ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW; + ah->ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH; + ah->ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW; + ah->ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH; + ah->ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW; + ah->ani[i].ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; - ah->ah_ani[i].cckWeakSigThreshold = + ah->ani[i].cckWeakSigThreshold = ATH9K_ANI_CCK_WEAK_SIG_THR; - ah->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; - ah->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; - if (ah->ah_hasHwPhyCounters) { - ah->ah_ani[i].ofdmPhyErrBase = + ah->ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; + ah->ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL; + if (ah->has_hw_phycounters) { + ah->ani[i].ofdmPhyErrBase = AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH; - ah->ah_ani[i].cckPhyErrBase = + ah->ani[i].cckPhyErrBase = AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; } } - if (ah->ah_hasHwPhyCounters) { + if (ah->has_hw_phycounters) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting OfdmErrBase = 0x%08x\n", - ah->ah_ani[0].ofdmPhyErrBase); + ah->ani[0].ofdmPhyErrBase); DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", - ah->ah_ani[0].cckPhyErrBase); + ah->ani[0].cckPhyErrBase); - REG_WRITE(ah, AR_PHY_ERR_1, ah->ah_ani[0].ofdmPhyErrBase); - REG_WRITE(ah, AR_PHY_ERR_2, ah->ah_ani[0].cckPhyErrBase); + REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase); + REG_WRITE(ah, AR_PHY_ERR_2, ah->ani[0].cckPhyErrBase); ath9k_enable_mib_counters(ah); } - ah->ah_aniPeriod = ATH9K_ANI_PERIOD; - if (ah->ah_config.enable_ani) - ah->ah_procPhyErr |= HAL_PROCESS_ANI; + ah->aniperiod = ATH9K_ANI_PERIOD; + if (ah->config.enable_ani) + ah->proc_phyerr |= HAL_PROCESS_ANI; } void ath9k_hw_ani_detach(struct ath_hw *ah) { DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n"); - if (ah->ah_hasHwPhyCounters) { + if (ah->has_hw_phycounters) { ath9k_hw_disable_mib_counters(ah); REG_WRITE(ah, AR_PHY_ERR_1, 0); REG_WRITE(ah, AR_PHY_ERR_2, 0); diff --git a/drivers/net/wireless/ath9k/ani.h b/drivers/net/wireless/ath9k/ani.h index 7e9ca9519799..7315761f6d74 100644 --- a/drivers/net/wireless/ath9k/ani.h +++ b/drivers/net/wireless/ath9k/ani.h @@ -20,12 +20,12 @@ #define HAL_PROCESS_ANI 0x00000001 #define ATH9K_RSSI_EP_MULTIPLIER (1<<7) -#define DO_ANI(ah) (((ah)->ah_procPhyErr & HAL_PROCESS_ANI)) +#define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI)) #define HAL_EP_RND(x, mul) \ ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) #define BEACON_RSSI(ahp) \ - HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \ + HAL_EP_RND(ahp->stats.ast_nodestats.ns_avgbrssi, \ ATH9K_RSSI_EP_MULTIPLIER) #define ATH9K_ANI_OFDM_TRIG_HIGH 500 @@ -118,7 +118,7 @@ struct ar5416Stats { struct ath9k_mib_stats ast_mibstats; struct ath9k_node_stats ast_nodestats; }; -#define ah_mibStats ah_stats.ast_mibstats +#define ah_mibStats stats.ast_mibstats void ath9k_ani_reset(struct ath_hw *ah); void ath9k_hw_ani_monitor(struct ath_hw *ah, diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index 91140b7214b1..0b0f82c83ffc 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h @@ -670,8 +670,8 @@ static inline void ath_ahb_exit(void) {}; static inline void ath9k_ps_wakeup(struct ath_softc *sc) { if (atomic_inc_return(&sc->ps_usecount) == 1) - if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) { - sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode; + if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) { + sc->sc_ah->restore_mode = sc->sc_ah->power_mode; ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); } } @@ -681,6 +681,6 @@ static inline void ath9k_ps_restore(struct ath_softc *sc) if (atomic_dec_and_test(&sc->ps_usecount)) if (sc->hw->conf.flags & IEEE80211_CONF_PS) ath9k_hw_setpower(sc->sc_ah, - sc->sc_ah->ah_restore_mode); + sc->sc_ah->restore_mode); } #endif /* ATH9K_H */ diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c index 19ec4e8791b4..2e2ef3529135 100644 --- a/drivers/net/wireless/ath9k/beacon.c +++ b/drivers/net/wireless/ath9k/beacon.c @@ -27,7 +27,7 @@ static int ath_beaconq_config(struct ath_softc *sc) struct ath9k_tx_queue_info qi; ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi); - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) { /* Always burst out beacon and CAB traffic. */ qi.tqi_aifs = 1; qi.tqi_cwmin = 0; @@ -82,8 +82,8 @@ static void ath_beacon_setup(struct ath_softc *sc, flags = ATH9K_TXDESC_NOACK; - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC && - (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC && + (ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) { ds->ds_link = bf->bf_daddr; /* self-linked */ flags |= ATH9K_TXDESC_VEOL; /* Let hardware handle antenna switching. */ @@ -310,8 +310,8 @@ int ath_beacon_alloc(struct ath_softc *sc, int if_id) struct ath_buf, list); list_del(&avp->av_bcbuf->list); - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || - !(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_AP || + !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) { int slot; /* * Assign the vif to a beacon xmit slot. As @@ -631,7 +631,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) avp = (void *)vif->drv_priv; opmode = avp->av_opmode; } else { - opmode = sc->sc_ah->ah_opmode; + opmode = sc->sc_ah->opmode; } memset(&conf, 0, sizeof(struct ath_beacon_config)); @@ -647,7 +647,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) nexttbtt = TSF_TO_TU(sc->beacon.bc_tstamp >> 32, sc->beacon.bc_tstamp); /* XXX conditionalize multi-bss support? */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) { /* * For multi-bss ap support beacons are either staggered * evenly over N slots or burst together. For the former @@ -670,7 +670,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) nexttbtt, intval, conf.beacon_interval); /* Check for NL80211_IFTYPE_AP and sc_nostabeacons for WDS client */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) { struct ath9k_beacon_state bs; u64 tsf; u32 tsftu; @@ -789,7 +789,7 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) ath9k_hw_set_interrupts(ah, 0); if (nexttbtt == intval) intval |= ATH9K_BEACON_RESET_TSF; - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) { /* * Pull nexttbtt forward to reflect the current * TSF @@ -818,10 +818,10 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) * deal with things. */ intval |= ATH9K_BEACON_ENA; - if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) + if (!(ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) sc->imask |= ATH9K_INT_SWBA; ath_beaconq_config(sc); - } else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { + } else if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) { /* * In AP mode we enable the beacon timers and * SWBA interrupts to prepare beacon frames. @@ -837,8 +837,8 @@ void ath_beacon_config(struct ath_softc *sc, int if_id) * When using a self-linked beacon descriptor in * ibss mode load it once here. */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC && - (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) + if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC && + (ah->caps.hw_caps & ATH9K_HW_CAP_VEOL)) ath_beacon_start_adhoc(sc, 0); } } diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c index 7e70a81e21de..1fc3a08e85c6 100644 --- a/drivers/net/wireless/ath9k/calib.c +++ b/drivers/net/wireless/ath9k/calib.c @@ -229,13 +229,13 @@ static void ath9k_hw_reset_calibration(struct ath_hw *ah, currCal->calState = CAL_RUNNING; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ah->ah_Meas0.sign[i] = 0; - ah->ah_Meas1.sign[i] = 0; - ah->ah_Meas2.sign[i] = 0; - ah->ah_Meas3.sign[i] = 0; + ah->meas0.sign[i] = 0; + ah->meas1.sign[i] = 0; + ah->meas2.sign[i] = 0; + ah->meas3.sign[i] = 0; } - ah->ah_CalSamples = 0; + ah->cal_samples = 0; } static void ath9k_hw_per_calibration(struct ath_hw *ah, @@ -251,9 +251,9 @@ static void ath9k_hw_per_calibration(struct ath_hw *ah, AR_PHY_TIMING_CTRL4_DO_CAL)) { currCal->calData->calCollect(ah); - ah->ah_CalSamples++; + ah->cal_samples++; - if (ah->ah_CalSamples >= currCal->calData->calNumSamples) { + if (ah->cal_samples >= currCal->calData->calNumSamples) { int i, numChains = 0; for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (rxchainmask & (1 << i)) @@ -279,7 +279,7 @@ static bool ath9k_hw_iscal_supported(struct ath_hw *ah, { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - switch (calType & ah->ah_suppCals) { + switch (calType & ah->supp_cals) { case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ return true; case ADC_GAIN_CAL: @@ -297,17 +297,17 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah) int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ah->ah_totalPowerMeasI[i] += + ah->totalPowerMeasI[i] += REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ah->ah_totalPowerMeasQ[i] += + ah->totalPowerMeasQ[i] += REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ah->ah_totalIqCorrMeas[i] += + ah->totalIqCorrMeas[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", - ah->ah_CalSamples, i, ah->ah_totalPowerMeasI[i], - ah->ah_totalPowerMeasQ[i], - ah->ah_totalIqCorrMeas[i]); + ah->cal_samples, i, ah->totalPowerMeasI[i], + ah->totalPowerMeasQ[i], + ah->totalIqCorrMeas[i]); } } @@ -316,23 +316,23 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah) int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ah->ah_totalAdcIOddPhase[i] += + ah->totalAdcIOddPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ah->ah_totalAdcIEvenPhase[i] += + ah->totalAdcIEvenPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ah->ah_totalAdcQOddPhase[i] += + ah->totalAdcQOddPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); - ah->ah_totalAdcQEvenPhase[i] += + ah->totalAdcQEvenPhase[i] += REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "oddq=0x%08x; evenq=0x%08x;\n", - ah->ah_CalSamples, i, - ah->ah_totalAdcIOddPhase[i], - ah->ah_totalAdcIEvenPhase[i], - ah->ah_totalAdcQOddPhase[i], - ah->ah_totalAdcQEvenPhase[i]); + ah->cal_samples, i, + ah->totalAdcIOddPhase[i], + ah->totalAdcIEvenPhase[i], + ah->totalAdcQOddPhase[i], + ah->totalAdcQEvenPhase[i]); } } @@ -341,23 +341,23 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah) int i; for (i = 0; i < AR5416_MAX_CHAINS; i++) { - ah->ah_totalAdcDcOffsetIOddPhase[i] += + ah->totalAdcDcOffsetIOddPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); - ah->ah_totalAdcDcOffsetIEvenPhase[i] += + ah->totalAdcDcOffsetIEvenPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); - ah->ah_totalAdcDcOffsetQOddPhase[i] += + ah->totalAdcDcOffsetQOddPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); - ah->ah_totalAdcDcOffsetQEvenPhase[i] += + ah->totalAdcDcOffsetQEvenPhase[i] += (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " "oddq=0x%08x; evenq=0x%08x;\n", - ah->ah_CalSamples, i, - ah->ah_totalAdcDcOffsetIOddPhase[i], - ah->ah_totalAdcDcOffsetIEvenPhase[i], - ah->ah_totalAdcDcOffsetQOddPhase[i], - ah->ah_totalAdcDcOffsetQEvenPhase[i]); + ah->cal_samples, i, + ah->totalAdcDcOffsetIOddPhase[i], + ah->totalAdcDcOffsetIEvenPhase[i], + ah->totalAdcDcOffsetQOddPhase[i], + ah->totalAdcDcOffsetQEvenPhase[i]); } } @@ -369,9 +369,9 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) int iqCorrNeg, i; for (i = 0; i < numChains; i++) { - powerMeasI = ah->ah_totalPowerMeasI[i]; - powerMeasQ = ah->ah_totalPowerMeasQ[i]; - iqCorrMeas = ah->ah_totalIqCorrMeas[i]; + powerMeasI = ah->totalPowerMeasI[i]; + powerMeasQ = ah->totalPowerMeasQ[i]; + iqCorrMeas = ah->totalIqCorrMeas[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting IQ Cal and Correction for Chain %d\n", @@ -379,7 +379,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Orignal: Chn %diq_corr_meas = 0x%08x\n", - i, ah->ah_totalIqCorrMeas[i]); + i, ah->totalIqCorrMeas[i]); iqCorrNeg = 0; @@ -443,10 +443,10 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) u32 qGainMismatch, iGainMismatch, val, i; for (i = 0; i < numChains; i++) { - iOddMeasOffset = ah->ah_totalAdcIOddPhase[i]; - iEvenMeasOffset = ah->ah_totalAdcIEvenPhase[i]; - qOddMeasOffset = ah->ah_totalAdcQOddPhase[i]; - qEvenMeasOffset = ah->ah_totalAdcQEvenPhase[i]; + iOddMeasOffset = ah->totalAdcIOddPhase[i]; + iEvenMeasOffset = ah->totalAdcIEvenPhase[i]; + qOddMeasOffset = ah->totalAdcQOddPhase[i]; + qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting ADC Gain Cal for Chain %d\n", i); @@ -499,15 +499,15 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) u32 iOddMeasOffset, iEvenMeasOffset, val, i; int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; const struct hal_percal_data *calData = - ah->ah_cal_list_curr->calData; + ah->cal_list_curr->calData; u32 numSamples = (1 << (calData->calCountMax + 5)) * calData->calNumSamples; for (i = 0; i < numChains; i++) { - iOddMeasOffset = ah->ah_totalAdcDcOffsetIOddPhase[i]; - iEvenMeasOffset = ah->ah_totalAdcDcOffsetIEvenPhase[i]; - qOddMeasOffset = ah->ah_totalAdcDcOffsetQOddPhase[i]; - qEvenMeasOffset = ah->ah_totalAdcDcOffsetQEvenPhase[i]; + iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i]; + iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i]; + qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; + qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Starting ADC DC Offset Cal for Chain %d\n", i); @@ -555,9 +555,9 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) bool ath9k_hw_reset_calvalid(struct ath_hw *ah) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - struct hal_cal_list *currCal = ah->ah_cal_list_curr; + struct hal_cal_list *currCal = ah->cal_list_curr; - if (!ah->ah_curchan) + if (!ah->curchan) return true; if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah)) @@ -580,7 +580,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah) "Resetting Cal %d state for channel %u\n", currCal->calData->calType, conf->channel->center_freq); - ah->ah_curchan->CalValid &= ~currCal->calData->calType; + ah->curchan->CalValid &= ~currCal->calData->calType; currCal->calState = CAL_WAITING; return false; @@ -722,7 +722,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, bool longcal, bool *isCalDone) { - struct hal_cal_list *currCal = ah->ah_cal_list_curr; + struct hal_cal_list *currCal = ah->cal_list_curr; *isCalDone = true; @@ -732,7 +732,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, isCalDone); if (*isCalDone) { - ah->ah_cal_list_curr = currCal = currCal->calNext; + ah->cal_list_curr = currCal = currCal->calNext; if (currCal->calState == CAL_WAITING) { *isCalDone = false; @@ -743,7 +743,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, if (longcal) { ath9k_hw_getnf(ah, chan); - ath9k_hw_loadnf(ah, ah->ah_curchan); + ath9k_hw_loadnf(ah, ah->curchan); ath9k_hw_start_nfcal(ah); if (chan->channelFlags & CHANNEL_CW_INT) @@ -869,32 +869,32 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF); - ah->ah_cal_list = ah->ah_cal_list_last = ah->ah_cal_list_curr = NULL; + ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { - INIT_CAL(&ah->ah_adcGainCalData); - INSERT_CAL(ah, &ah->ah_adcGainCalData); + INIT_CAL(&ah->adcgain_caldata); + INSERT_CAL(ah, &ah->adcgain_caldata); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling ADC Gain Calibration.\n"); } if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { - INIT_CAL(&ah->ah_adcDcCalData); - INSERT_CAL(ah, &ah->ah_adcDcCalData); + INIT_CAL(&ah->adcdc_caldata); + INSERT_CAL(ah, &ah->adcdc_caldata); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling ADC DC Calibration.\n"); } if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { - INIT_CAL(&ah->ah_iqCalData); - INSERT_CAL(ah, &ah->ah_iqCalData); + INIT_CAL(&ah->iq_caldata); + INSERT_CAL(ah, &ah->iq_caldata); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "enabling IQ Calibration.\n"); } - ah->ah_cal_list_curr = ah->ah_cal_list; + ah->cal_list_curr = ah->cal_list; - if (ah->ah_cal_list_curr) - ath9k_hw_reset_calibration(ah, ah->ah_cal_list_curr); + if (ah->cal_list_curr) + ath9k_hw_reset_calibration(ah, ah->cal_list_curr); } chan->CalValid = 0; diff --git a/drivers/net/wireless/ath9k/calib.h b/drivers/net/wireless/ath9k/calib.h index e2c614098545..d2448f049c1d 100644 --- a/drivers/net/wireless/ath9k/calib.h +++ b/drivers/net/wireless/ath9k/calib.h @@ -56,14 +56,14 @@ struct ar5416IniArray { #define INSERT_CAL(_ahp, _perCal) \ do { \ - if ((_ahp)->ah_cal_list_last == NULL) { \ - (_ahp)->ah_cal_list = \ - (_ahp)->ah_cal_list_last = (_perCal); \ - ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ + if ((_ahp)->cal_list_last == NULL) { \ + (_ahp)->cal_list = \ + (_ahp)->cal_list_last = (_perCal); \ + ((_ahp)->cal_list_last)->calNext = (_perCal); \ } else { \ - ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \ - (_ahp)->ah_cal_list_last = (_perCal); \ - (_perCal)->calNext = (_ahp)->ah_cal_list; \ + ((_ahp)->cal_list_last)->calNext = (_perCal); \ + (_ahp)->cal_list_last = (_perCal); \ + (_perCal)->calNext = (_ahp)->cal_list; \ } \ } while (0) diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index 2e604e1fb3e1..c0359ad2bc7b 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -27,7 +27,7 @@ static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, REG_WRITE(ah, reg, regVal); - if (ah->ah_config.analog_shiftreg) + if (ah->config.analog_shiftreg) udelay(100); return; @@ -268,18 +268,18 @@ static u16 ath9k_hw_get_max_edge_power(u16 freq, static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) { - return ((ah->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF); + return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF); } static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah) { - return ((ah->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF); + return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF); } static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) { #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; u16 *eep_data; int addr, eep_start_loc = 0; @@ -308,7 +308,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) { #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) struct ar5416_eeprom_4k *eep = - (struct ar5416_eeprom_4k *) &ah->ah_eeprom.map4k; + (struct ar5416_eeprom_4k *) &ah->eeprom.map4k; u16 *eepdata, temp, magic, magic2; u32 sum = 0, el; bool need_swap = false; @@ -332,7 +332,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) if (magic2 == AR5416_EEPROM_MAGIC) { need_swap = true; - eepdata = (u16 *) (&ah->ah_eeprom); + eepdata = (u16 *) (&ah->eeprom); for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { temp = swab16(*eepdata); @@ -359,16 +359,16 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) need_swap ? "True" : "False"); if (need_swap) - el = swab16(ah->ah_eeprom.map4k.baseEepHeader.length); + el = swab16(ah->eeprom.map4k.baseEepHeader.length); else - el = ah->ah_eeprom.map4k.baseEepHeader.length; + el = ah->eeprom.map4k.baseEepHeader.length; if (el > sizeof(struct ar5416_eeprom_def)) el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); else el = el / sizeof(u16); - eepdata = (u16 *)(&ah->ah_eeprom); + eepdata = (u16 *)(&ah->eeprom); for (i = 0; i < el; i++) sum ^= *eepdata++; @@ -433,7 +433,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, enum eeprom_param param) { - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; struct modal_eep_4k_header *pModal = &eep->modalHeader; struct base_eep_header_4k *pBase = &eep->baseEepHeader; @@ -643,7 +643,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) { - struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; struct cal_data_per_freq_4k *pRawDataset; u8 *pCalBChans = NULL; u16 pdGainOverlap_t2; @@ -692,7 +692,7 @@ static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (AR_SREV_5416_V20_OR_LATER(ah) && - (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && + (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0)) { regChainOffset = (i == 1) ? 0x2000 : 0x1000; } else @@ -763,7 +763,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, u16 twiceMaxRegulatoryPower, u16 powerLimit) { - struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; static const u16 tpScaleReductionTable[5] = { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; @@ -791,7 +791,7 @@ static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, int tx_chainmask; u16 twiceMinEdgePower; - tx_chainmask = ah->ah_txchainmask; + tx_chainmask = ah->txchainmask; ath9k_hw_get_channel_centers(ah, chan, ¢ers); @@ -997,7 +997,7 @@ static int ath9k_hw_4k_set_txpower(struct ath_hw *ah, u8 twiceMaxRegulatoryPower, u8 powerLimit) { - struct ar5416_eeprom_4k *pEepData = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; struct modal_eep_4k_header *pModal = &pEepData->modalHeader; int16_t ratesArray[Ar5416RateSize]; int16_t txPowerIndexOffset = 0; @@ -1121,7 +1121,7 @@ static void ath9k_hw_4k_set_addac(struct ath_hw *ah, struct ath9k_channel *chan) { struct modal_eep_4k_header *pModal; - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; u8 biaslevel; if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) @@ -1134,8 +1134,8 @@ static void ath9k_hw_4k_set_addac(struct ath_hw *ah, if (pModal->xpaBiasLvl != 0xff) { biaslevel = pModal->xpaBiasLvl; - INI_RA(&ah->ah_iniAddac, 7, 1) = - (INI_RA(&ah->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; + INI_RA(&ah->iniAddac, 7, 1) = + (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; } } @@ -1143,7 +1143,7 @@ static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { struct modal_eep_4k_header *pModal; - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; int regChainOffset; u8 txRxAttenLocal; u8 ob[5], db1[5], db2[5]; @@ -1328,7 +1328,7 @@ static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah, static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ar5416_eeprom_4k *eep = &ah->ah_eeprom.map4k; + struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; struct modal_eep_4k_header *pModal = &eep->modalHeader; return pModal->antCtrlCommon & 0xFFFF; @@ -1343,19 +1343,19 @@ static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah, u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) { #define EEP_MAP4K_SPURCHAN \ - (ah->ah_eeprom.map4k.modalHeader.spurChans[i].spurChan) + (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) u16 spur_val = AR_NO_SPUR; DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Getting spur idx %d is2Ghz. %d val %x\n", - i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); + i, is2GHz, ah->config.spurchans[i][is2GHz]); - switch (ah->ah_config.spurmode) { + switch (ah->config.spurmode) { case SPUR_DISABLE: break; case SPUR_ENABLE_IOCTL: - spur_val = ah->ah_config.spurchans[i][is2GHz]; + spur_val = ah->config.spurchans[i][is2GHz]; DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Getting spur val from new loc. %d\n", spur_val); break; @@ -1389,18 +1389,18 @@ struct eeprom_ops eep_4k_ops = { static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah) { - return ((ah->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF); + return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF); } static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah) { - return ((ah->ah_eeprom.def.baseEepHeader.version) & 0xFFF); + return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF); } static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) { #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16)) - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; u16 *eep_data; int addr, ar5416_eep_start_loc = 0x100; @@ -1422,7 +1422,7 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) { struct ar5416_eeprom_def *eep = - (struct ar5416_eeprom_def *) &ah->ah_eeprom.def; + (struct ar5416_eeprom_def *) &ah->eeprom.def; u16 *eepdata, temp, magic, magic2; u32 sum = 0, el; bool need_swap = false; @@ -1446,7 +1446,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) if (magic2 == AR5416_EEPROM_MAGIC) { size = sizeof(struct ar5416_eeprom_def); need_swap = true; - eepdata = (u16 *) (&ah->ah_eeprom); + eepdata = (u16 *) (&ah->eeprom); for (addr = 0; addr < size / sizeof(u16); addr++) { temp = swab16(*eepdata); @@ -1473,16 +1473,16 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) need_swap ? "True" : "False"); if (need_swap) - el = swab16(ah->ah_eeprom.def.baseEepHeader.length); + el = swab16(ah->eeprom.def.baseEepHeader.length); else - el = ah->ah_eeprom.def.baseEepHeader.length; + el = ah->eeprom.def.baseEepHeader.length; if (el > sizeof(struct ar5416_eeprom_def)) el = sizeof(struct ar5416_eeprom_def) / sizeof(u16); else el = el / sizeof(u16); - eepdata = (u16 *)(&ah->ah_eeprom); + eepdata = (u16 *)(&ah->eeprom); for (i = 0; i < el; i++) sum ^= *eepdata++; @@ -1551,7 +1551,7 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, enum eeprom_param param) { #define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; struct modal_eep_header *pModal = eep->modalHeader; struct base_eep_header *pBase = &eep->baseEepHeader; @@ -1611,7 +1611,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, { #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) struct modal_eep_header *pModal; - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; int i, regChainOffset; u8 txRxAttenLocal; @@ -1629,7 +1629,7 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, } if (AR_SREV_5416_V20_OR_LATER(ah) && - (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) + (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0)) regChainOffset = (i == 1) ? 0x2000 : 0x1000; else @@ -1855,7 +1855,7 @@ static void ath9k_hw_def_set_addac(struct ath_hw *ah, { #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt]) struct modal_eep_header *pModal; - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; u8 biaslevel; if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) @@ -1895,10 +1895,10 @@ static void ath9k_hw_def_set_addac(struct ath_hw *ah, } if (IS_CHAN_2GHZ(chan)) { - INI_RA(&ah->ah_iniAddac, 7, 1) = (INI_RA(&ah->ah_iniAddac, + INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; } else { - INI_RA(&ah->ah_iniAddac, 6, 1) = (INI_RA(&ah->ah_iniAddac, + INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac, 6, 1) & (~0xc0)) | biaslevel << 6; } #undef XPA_LVL_FREQ @@ -2073,7 +2073,7 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) { - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; struct cal_data_per_freq *pRawDataset; u8 *pCalBChans = NULL; u16 pdGainOverlap_t2; @@ -2129,7 +2129,7 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, for (i = 0; i < AR5416_MAX_CHAINS; i++) { if (AR_SREV_5416_V20_OR_LATER(ah) && - (ah->ah_rxchainmask == 5 || ah->ah_txchainmask == 5) && + (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0)) { regChainOffset = (i == 1) ? 0x2000 : 0x1000; } else @@ -2206,7 +2206,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; static const u16 tpScaleReductionTable[5] = { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; @@ -2236,7 +2236,7 @@ static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, int tx_chainmask; u16 twiceMinEdgePower; - tx_chainmask = ah->ah_txchainmask; + tx_chainmask = ah->txchainmask; ath9k_hw_get_channel_centers(ah, chan, ¢ers); @@ -2493,7 +2493,7 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, u8 twiceMaxRegulatoryPower, u8 powerLimit) { - struct ar5416_eeprom_def *pEepData = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; struct modal_eep_header *pModal = &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); int16_t ratesArray[Ar5416RateSize]; @@ -2621,7 +2621,7 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah, enum ieee80211_band freq_band) { - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; struct modal_eep_header *pModal = &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]); struct base_eep_header *pBase = &eep->baseEepHeader; @@ -2639,7 +2639,7 @@ static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah, static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah, struct ath9k_channel *chan) { - struct ar5416_eeprom_def *eep = &ah->ah_eeprom.def; + struct ar5416_eeprom_def *eep = &ah->eeprom.def; struct modal_eep_header *pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); @@ -2649,19 +2649,19 @@ static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah, u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) { #define EEP_DEF_SPURCHAN \ - (ah->ah_eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) + (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan) u16 spur_val = AR_NO_SPUR; DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Getting spur idx %d is2Ghz. %d val %x\n", - i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); + i, is2GHz, ah->config.spurchans[i][is2GHz]); - switch (ah->ah_config.spurmode) { + switch (ah->config.spurmode) { case SPUR_DISABLE: break; case SPUR_ENABLE_IOCTL: - spur_val = ah->ah_config.spurchans[i][is2GHz]; + spur_val = ah->config.spurchans[i][is2GHz]; DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Getting spur val from new loc. %d\n", spur_val); break; @@ -2694,10 +2694,10 @@ int ath9k_hw_eeprom_attach(struct ath_hw *ah) int status; if (AR_SREV_9285(ah)) { - ah->ah_eep_map = EEP_MAP_4KBITS; + ah->eep_map = EEP_MAP_4KBITS; ah->eep_ops = &eep_4k_ops; } else { - ah->ah_eep_map = EEP_MAP_DEFAULT; + ah->eep_map = EEP_MAP_DEFAULT; ah->eep_ops = &eep_def_ops; } diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 7a4266f29eaa..99863b570441 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -441,7 +441,7 @@ struct ath9k_country_entry { u8 iso[3]; }; -enum hal_eep_map { +enum ath9k_eep_map { EEP_MAP_DEFAULT = 0x0, EEP_MAP_4KBITS, EEP_MAP_MAX diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index f744d8cd8307..72ca1c8ff090 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -45,7 +45,7 @@ static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - if (!ah->ah_curchan) /* should really check for CCK instead */ + if (!ah->curchan) /* should really check for CCK instead */ return clks / ATH9K_CLOCK_RATE_CCK; if (conf->channel->band == IEEE80211_BAND_2GHZ) return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM; @@ -67,7 +67,7 @@ static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) { struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; - if (!ah->ah_curchan) /* should really check for CCK instead */ + if (!ah->curchan) /* should really check for CCK instead */ return usecs *ATH9K_CLOCK_RATE_CCK; if (conf->channel->band == IEEE80211_BAND_2GHZ) return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; @@ -118,7 +118,7 @@ bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; if (flags & CHANNEL_5GHZ) { *low = pCap->low_5ghz_chan; @@ -155,15 +155,15 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah, txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); break; case WLAN_RC_PHY_OFDM: - if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) { + if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; numBits = OFDM_PLCP_BITS + (frameLen << 3); numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); txTime = OFDM_SIFS_TIME_QUARTER + OFDM_PREAMBLE_TIME_QUARTER + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); - } else if (ah->ah_curchan && - IS_CHAN_HALF_RATE(ah->ah_curchan)) { + } else if (ah->curchan && + IS_CHAN_HALF_RATE(ah->curchan)) { bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; numBits = OFDM_PLCP_BITS + (frameLen << 3); numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); @@ -216,7 +216,7 @@ void ath9k_hw_get_channel_centers(struct ath_hw *ah, centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); centers->ext_center = centers->synth_center + (extoff * - ((ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? + ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ? HT40_CHANNEL_CENTER_SHIFT : 15)); } @@ -235,7 +235,7 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah) ah->hw_version.macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); - ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; + ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; } else { if (!AR_SREV_9100(ah)) ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); @@ -243,7 +243,7 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah) ah->hw_version.macRev = val & AR_SREV_REVISION; if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) - ah->ah_isPciExpress = true; + ah->is_pciexpress = true; } } @@ -355,40 +355,40 @@ static void ath9k_hw_set_defaults(struct ath_hw *ah) { int i; - ah->ah_config.dma_beacon_response_time = 2; - ah->ah_config.sw_beacon_response_time = 10; - ah->ah_config.additional_swba_backoff = 0; - ah->ah_config.ack_6mb = 0x0; - ah->ah_config.cwm_ignore_extcca = 0; - ah->ah_config.pcie_powersave_enable = 0; - ah->ah_config.pcie_l1skp_enable = 0; - ah->ah_config.pcie_clock_req = 0; - ah->ah_config.pcie_power_reset = 0x100; - ah->ah_config.pcie_restore = 0; - ah->ah_config.pcie_waen = 0; - ah->ah_config.analog_shiftreg = 1; - ah->ah_config.ht_enable = 1; - ah->ah_config.ofdm_trig_low = 200; - ah->ah_config.ofdm_trig_high = 500; - ah->ah_config.cck_trig_high = 200; - ah->ah_config.cck_trig_low = 100; - ah->ah_config.enable_ani = 1; - ah->ah_config.noise_immunity_level = 4; - ah->ah_config.ofdm_weaksignal_det = 1; - ah->ah_config.cck_weaksignal_thr = 0; - ah->ah_config.spur_immunity_level = 2; - ah->ah_config.firstep_level = 0; - ah->ah_config.rssi_thr_high = 40; - ah->ah_config.rssi_thr_low = 7; - ah->ah_config.diversity_control = 0; - ah->ah_config.antenna_switch_swap = 0; + ah->config.dma_beacon_response_time = 2; + ah->config.sw_beacon_response_time = 10; + ah->config.additional_swba_backoff = 0; + ah->config.ack_6mb = 0x0; + ah->config.cwm_ignore_extcca = 0; + ah->config.pcie_powersave_enable = 0; + ah->config.pcie_l1skp_enable = 0; + ah->config.pcie_clock_req = 0; + ah->config.pcie_power_reset = 0x100; + ah->config.pcie_restore = 0; + ah->config.pcie_waen = 0; + ah->config.analog_shiftreg = 1; + ah->config.ht_enable = 1; + ah->config.ofdm_trig_low = 200; + ah->config.ofdm_trig_high = 500; + ah->config.cck_trig_high = 200; + ah->config.cck_trig_low = 100; + ah->config.enable_ani = 1; + ah->config.noise_immunity_level = 4; + ah->config.ofdm_weaksignal_det = 1; + ah->config.cck_weaksignal_thr = 0; + ah->config.spur_immunity_level = 2; + ah->config.firstep_level = 0; + ah->config.rssi_thr_high = 40; + ah->config.rssi_thr_low = 7; + ah->config.diversity_control = 0; + ah->config.antenna_switch_swap = 0; for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { - ah->ah_config.spurchans[i][0] = AR_NO_SPUR; - ah->ah_config.spurchans[i][1] = AR_NO_SPUR; + ah->config.spurchans[i][0] = AR_NO_SPUR; + ah->config.spurchans[i][1] = AR_NO_SPUR; } - ah->ah_config.intr_mitigation = 1; + ah->config.intr_mitigation = 1; } static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc, @@ -418,19 +418,19 @@ static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc, ah->regulatory.power_limit = MAX_RATE_POWER; ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX; - ah->ah_atimWindow = 0; - ah->ah_diversityControl = ah->ah_config.diversity_control; - ah->ah_antennaSwitchSwap = - ah->ah_config.antenna_switch_swap; - ah->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; - ah->ah_beaconInterval = 100; - ah->ah_enable32kHzClock = DONT_USE_32KHZ; - ah->ah_slottime = (u32) -1; - ah->ah_acktimeout = (u32) -1; - ah->ah_ctstimeout = (u32) -1; - ah->ah_globaltxtimeout = (u32) -1; - - ah->ah_gBeaconRate = 0; + ah->atim_window = 0; + ah->diversity_control = ah->config.diversity_control; + ah->antenna_switch_swap = + ah->config.antenna_switch_swap; + ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; + ah->beacon_interval = 100; + ah->enable_32kHz_clock = DONT_USE_32KHZ; + ah->slottime = (u32) -1; + ah->acktimeout = (u32) -1; + ah->ctstimeout = (u32) -1; + ah->globaltxtimeout = (u32) -1; + + ah->gbeacon_rate = 0; return ah; } @@ -510,19 +510,19 @@ static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) - INIT_INI_ARRAY(&ah->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9280Modes_backoff_13db_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) - INIT_INI_ARRAY(&ah->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9280Modes_backoff_23db_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); else - INIT_INI_ARRAY(&ah->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9280Modes_original_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); } else { - INIT_INI_ARRAY(&ah->ah_iniModesRxGain, + INIT_INI_ARRAY(&ah->iniModesRxGain, ar9280Modes_original_rxgain_9280_2, ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); } @@ -536,15 +536,15 @@ static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) - INIT_INI_ARRAY(&ah->ah_iniModesTxGain, + INIT_INI_ARRAY(&ah->iniModesTxGain, ar9280Modes_high_power_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); else - INIT_INI_ARRAY(&ah->ah_iniModesTxGain, + INIT_INI_ARRAY(&ah->iniModesTxGain, ar9280Modes_original_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); } else { - INIT_INI_ARRAY(&ah->ah_iniModesTxGain, + INIT_INI_ARRAY(&ah->iniModesTxGain, ar9280Modes_original_tx_gain_9280_2, ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); } @@ -592,8 +592,8 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ath9k_hw_set_defaults(ah); - if (ah->ah_config.intr_mitigation != 0) - ah->ah_intrMitigation = true; + if (ah->config.intr_mitigation != 0) + ah->intr_mitigation = true; if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n"); @@ -607,18 +607,18 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, goto bad; } - if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) { + if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) { - ah->ah_config.serialize_regmode = + ah->config.serialize_regmode = SER_REG_MODE_ON; } else { - ah->ah_config.serialize_regmode = + ah->config.serialize_regmode = SER_REG_MODE_OFF; } } DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n", - ah->ah_config.serialize_regmode); + ah->config.serialize_regmode); if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) && (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) && @@ -633,41 +633,41 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, } if (AR_SREV_9100(ah)) { - ah->ah_iqCalData.calData = &iq_cal_multi_sample; - ah->ah_suppCals = IQ_MISMATCH_CAL; - ah->ah_isPciExpress = false; + ah->iq_caldata.calData = &iq_cal_multi_sample; + ah->supp_cals = IQ_MISMATCH_CAL; + ah->is_pciexpress = false; } ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); if (AR_SREV_9160_10_OR_LATER(ah)) { if (AR_SREV_9280_10_OR_LATER(ah)) { - ah->ah_iqCalData.calData = &iq_cal_single_sample; - ah->ah_adcGainCalData.calData = + ah->iq_caldata.calData = &iq_cal_single_sample; + ah->adcgain_caldata.calData = &adc_gain_cal_single_sample; - ah->ah_adcDcCalData.calData = + ah->adcdc_caldata.calData = &adc_dc_cal_single_sample; - ah->ah_adcDcCalInitData.calData = + ah->adcdc_calinitdata.calData = &adc_init_dc_cal; } else { - ah->ah_iqCalData.calData = &iq_cal_multi_sample; - ah->ah_adcGainCalData.calData = + ah->iq_caldata.calData = &iq_cal_multi_sample; + ah->adcgain_caldata.calData = &adc_gain_cal_multi_sample; - ah->ah_adcDcCalData.calData = + ah->adcdc_caldata.calData = &adc_dc_cal_multi_sample; - ah->ah_adcDcCalInitData.calData = + ah->adcdc_calinitdata.calData = &adc_init_dc_cal; } - ah->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; + ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; } if (AR_SREV_9160(ah)) { - ah->ah_config.enable_ani = 1; - ah->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | + ah->config.enable_ani = 1; + ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL | ATH9K_ANI_FIRSTEP_LEVEL); } else { - ah->ah_ani_function = ATH9K_ANI_ALL; + ah->ani_function = ATH9K_ANI_ALL; if (AR_SREV_9280_10_OR_LATER(ah)) { - ah->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; + ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; } } @@ -676,137 +676,137 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ah->hw_version.macVersion, ah->hw_version.macRev); if (AR_SREV_9285_12_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285_1_2, + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, ARRAY_SIZE(ar9285Modes_9285_1_2), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285_1_2, + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, ARRAY_SIZE(ar9285Common_9285_1_2), 2); - if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + if (ah->config.pcie_clock_req) { + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9285PciePhy_clkreq_off_L1_9285_1_2, ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); } else { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9285PciePhy_clkreq_always_on_L1_9285_1_2, ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), 2); } } else if (AR_SREV_9285_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar9285Modes_9285, + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285, ARRAY_SIZE(ar9285Modes_9285), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar9285Common_9285, + INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285, ARRAY_SIZE(ar9285Common_9285), 2); - if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + if (ah->config.pcie_clock_req) { + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9285PciePhy_clkreq_off_L1_9285, ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); } else { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9285PciePhy_clkreq_always_on_L1_9285, ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); } } else if (AR_SREV_9280_20_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280_2, + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, ARRAY_SIZE(ar9280Modes_9280_2), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280_2, + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, ARRAY_SIZE(ar9280Common_9280_2), 2); - if (ah->ah_config.pcie_clock_req) { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + if (ah->config.pcie_clock_req) { + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9280PciePhy_clkreq_off_L1_9280, ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); } else { - INIT_INI_ARRAY(&ah->ah_iniPcieSerdes, + INIT_INI_ARRAY(&ah->iniPcieSerdes, ar9280PciePhy_clkreq_always_on_L1_9280, ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); } - INIT_INI_ARRAY(&ah->ah_iniModesAdditional, + INIT_INI_ARRAY(&ah->iniModesAdditional, ar9280Modes_fast_clock_9280_2, ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); } else if (AR_SREV_9280_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar9280Modes_9280, + INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280, ARRAY_SIZE(ar9280Modes_9280), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar9280Common_9280, + INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280, ARRAY_SIZE(ar9280Common_9280), 2); } else if (AR_SREV_9160_10_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9160, + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, ARRAY_SIZE(ar5416Modes_9160), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9160, + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, ARRAY_SIZE(ar5416Common_9160), 2); - INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9160, + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, ARRAY_SIZE(ar5416Bank0_9160), 2); - INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9160, + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, ARRAY_SIZE(ar5416BB_RfGain_9160), 3); - INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9160, + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, ARRAY_SIZE(ar5416Bank1_9160), 2); - INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9160, + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, ARRAY_SIZE(ar5416Bank2_9160), 2); - INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9160, + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, ARRAY_SIZE(ar5416Bank3_9160), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9160, + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, ARRAY_SIZE(ar5416Bank6_9160), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9160, + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, ARRAY_SIZE(ar5416Bank6TPC_9160), 3); - INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9160, + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, ARRAY_SIZE(ar5416Bank7_9160), 2); if (AR_SREV_9160_11(ah)) { - INIT_INI_ARRAY(&ah->ah_iniAddac, + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_91601_1, ARRAY_SIZE(ar5416Addac_91601_1), 2); } else { - INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9160, + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, ARRAY_SIZE(ar5416Addac_9160), 2); } } else if (AR_SREV_9100_OR_LATER(ah)) { - INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes_9100, + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, ARRAY_SIZE(ar5416Modes_9100), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common_9100, + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, ARRAY_SIZE(ar5416Common_9100), 2); - INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0_9100, + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, ARRAY_SIZE(ar5416Bank0_9100), 2); - INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain_9100, + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, ARRAY_SIZE(ar5416BB_RfGain_9100), 3); - INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1_9100, + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, ARRAY_SIZE(ar5416Bank1_9100), 2); - INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2_9100, + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, ARRAY_SIZE(ar5416Bank2_9100), 2); - INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3_9100, + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, ARRAY_SIZE(ar5416Bank3_9100), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6_9100, + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, ARRAY_SIZE(ar5416Bank6_9100), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC_9100, + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, ARRAY_SIZE(ar5416Bank6TPC_9100), 3); - INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7_9100, + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, ARRAY_SIZE(ar5416Bank7_9100), 2); - INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac_9100, + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, ARRAY_SIZE(ar5416Addac_9100), 2); } else { - INIT_INI_ARRAY(&ah->ah_iniModes, ar5416Modes, + INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, ARRAY_SIZE(ar5416Modes), 6); - INIT_INI_ARRAY(&ah->ah_iniCommon, ar5416Common, + INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, ARRAY_SIZE(ar5416Common), 2); - INIT_INI_ARRAY(&ah->ah_iniBank0, ar5416Bank0, + INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, ARRAY_SIZE(ar5416Bank0), 2); - INIT_INI_ARRAY(&ah->ah_iniBB_RfGain, ar5416BB_RfGain, + INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, ARRAY_SIZE(ar5416BB_RfGain), 3); - INIT_INI_ARRAY(&ah->ah_iniBank1, ar5416Bank1, + INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, ARRAY_SIZE(ar5416Bank1), 2); - INIT_INI_ARRAY(&ah->ah_iniBank2, ar5416Bank2, + INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, ARRAY_SIZE(ar5416Bank2), 2); - INIT_INI_ARRAY(&ah->ah_iniBank3, ar5416Bank3, + INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, ARRAY_SIZE(ar5416Bank3), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6, ar5416Bank6, + INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, ARRAY_SIZE(ar5416Bank6), 3); - INIT_INI_ARRAY(&ah->ah_iniBank6TPC, ar5416Bank6TPC, + INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, ARRAY_SIZE(ar5416Bank6TPC), 3); - INIT_INI_ARRAY(&ah->ah_iniBank7, ar5416Bank7, + INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, ARRAY_SIZE(ar5416Bank7), 2); - INIT_INI_ARRAY(&ah->ah_iniAddac, ar5416Addac, + INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, ARRAY_SIZE(ar5416Addac), 2); } - if (ah->ah_isPciExpress) + if (ah->is_pciexpress) ath9k_hw_configpcipowersave(ah, 0); else ath9k_hw_disablepcie(ah); @@ -824,15 +824,15 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ath9k_hw_init_txgain_ini(ah); if (ah->hw_version.devid == AR9280_DEVID_PCI) { - for (i = 0; i < ah->ah_iniModes.ia_rows; i++) { - u32 reg = INI_RA(&ah->ah_iniModes, i, 0); + for (i = 0; i < ah->iniModes.ia_rows; i++) { + u32 reg = INI_RA(&ah->iniModes, i, 0); - for (j = 1; j < ah->ah_iniModes.ia_columns; j++) { - u32 val = INI_RA(&ah->ah_iniModes, i, j); + for (j = 1; j < ah->iniModes.ia_columns; j++) { + u32 val = INI_RA(&ah->iniModes, i, j); - INI_RA(&ah->ah_iniModes, i, j) = + INI_RA(&ah->iniModes, i, j) = ath9k_hw_ini_fixup(ah, - &ah->ah_eeprom.def, + &ah->eeprom.def, reg, val); } } @@ -853,9 +853,9 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, } if (AR_SREV_9285(ah)) - ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S); + ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); else - ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S); + ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); ath9k_init_nfcal_hist_buffer(ah); @@ -974,8 +974,8 @@ static void ath9k_hw_init_chain_masks(struct ath_hw *ah) { int rx_chainmask, tx_chainmask; - rx_chainmask = ah->ah_rxchainmask; - tx_chainmask = ah->ah_txchainmask; + rx_chainmask = ah->rxchainmask; + tx_chainmask = ah->txchainmask; switch (rx_chainmask) { case 0x5: @@ -1010,23 +1010,23 @@ static void ath9k_hw_init_chain_masks(struct ath_hw *ah) static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, enum nl80211_iftype opmode) { - ah->ah_maskReg = AR_IMR_TXERR | + ah->mask_reg = AR_IMR_TXERR | AR_IMR_TXURN | AR_IMR_RXERR | AR_IMR_RXORN | AR_IMR_BCNMISC; - if (ah->ah_intrMitigation) - ah->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; + if (ah->intr_mitigation) + ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; else - ah->ah_maskReg |= AR_IMR_RXOK; + ah->mask_reg |= AR_IMR_RXOK; - ah->ah_maskReg |= AR_IMR_TXOK; + ah->mask_reg |= AR_IMR_TXOK; if (opmode == NL80211_IFTYPE_AP) - ah->ah_maskReg |= AR_IMR_MIB; + ah->mask_reg |= AR_IMR_MIB; - REG_WRITE(ah, AR_IMR, ah->ah_maskReg); + REG_WRITE(ah, AR_IMR, ah->mask_reg); REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT); if (!AR_SREV_9100(ah)) { @@ -1040,12 +1040,12 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) { if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); - ah->ah_acktimeout = (u32) -1; + ah->acktimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us)); - ah->ah_acktimeout = us; + ah->acktimeout = us; return true; } } @@ -1054,12 +1054,12 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) { if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); - ah->ah_ctstimeout = (u32) -1; + ah->ctstimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us)); - ah->ah_ctstimeout = us; + ah->ctstimeout = us; return true; } } @@ -1069,31 +1069,31 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) if (tu > 0xFFFF) { DPRINTF(ah->ah_sc, ATH_DBG_XMIT, "bad global tx timeout %u\n", tu); - ah->ah_globaltxtimeout = (u32) -1; + ah->globaltxtimeout = (u32) -1; return false; } else { REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); - ah->ah_globaltxtimeout = tu; + ah->globaltxtimeout = tu; return true; } } static void ath9k_hw_init_user_settings(struct ath_hw *ah) { - DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->ah_miscMode 0x%x\n", - ah->ah_miscMode); + DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n", + ah->misc_mode); - if (ah->ah_miscMode != 0) + if (ah->misc_mode != 0) REG_WRITE(ah, AR_PCU_MISC, - REG_READ(ah, AR_PCU_MISC) | ah->ah_miscMode); - if (ah->ah_slottime != (u32) -1) - ath9k_hw_setslottime(ah, ah->ah_slottime); - if (ah->ah_acktimeout != (u32) -1) - ath9k_hw_set_ack_timeout(ah, ah->ah_acktimeout); - if (ah->ah_ctstimeout != (u32) -1) - ath9k_hw_set_cts_timeout(ah, ah->ah_ctstimeout); - if (ah->ah_globaltxtimeout != (u32) -1) - ath9k_hw_set_global_txtimeout(ah, ah->ah_globaltxtimeout); + REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); + if (ah->slottime != (u32) -1) + ath9k_hw_setslottime(ah, ah->slottime); + if (ah->acktimeout != (u32) -1) + ath9k_hw_set_ack_timeout(ah, ah->acktimeout); + if (ah->ctstimeout != (u32) -1) + ath9k_hw_set_cts_timeout(ah, ah->ctstimeout); + if (ah->globaltxtimeout != (u32) -1) + ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); } const char *ath9k_hw_probe(u16 vendorid, u16 devid) @@ -1194,7 +1194,7 @@ static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, struct ar5416_eeprom_def *pEepData, u32 reg, u32 value) { - if (ah->ah_eep_map == EEP_MAP_4KBITS) + if (ah->eep_map == EEP_MAP_4KBITS) return value; else return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); @@ -1241,34 +1241,34 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ah->eep_ops->set_addac(ah, chan); if (AR_SREV_5416_V22_OR_LATER(ah)) { - REG_WRITE_ARRAY(&ah->ah_iniAddac, 1, regWrites); + REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites); } else { struct ar5416IniArray temp; u32 addacSize = - sizeof(u32) * ah->ah_iniAddac.ia_rows * - ah->ah_iniAddac.ia_columns; + sizeof(u32) * ah->iniAddac.ia_rows * + ah->iniAddac.ia_columns; - memcpy(ah->ah_addac5416_21, - ah->ah_iniAddac.ia_array, addacSize); + memcpy(ah->addac5416_21, + ah->iniAddac.ia_array, addacSize); - (ah->ah_addac5416_21)[31 * ah->ah_iniAddac.ia_columns + 1] = 0; + (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0; - temp.ia_array = ah->ah_addac5416_21; - temp.ia_columns = ah->ah_iniAddac.ia_columns; - temp.ia_rows = ah->ah_iniAddac.ia_rows; + temp.ia_array = ah->addac5416_21; + temp.ia_columns = ah->iniAddac.ia_columns; + temp.ia_rows = ah->iniAddac.ia_rows; REG_WRITE_ARRAY(&temp, 1, regWrites); } REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); - for (i = 0; i < ah->ah_iniModes.ia_rows; i++) { - u32 reg = INI_RA(&ah->ah_iniModes, i, 0); - u32 val = INI_RA(&ah->ah_iniModes, i, modesIndex); + for (i = 0; i < ah->iniModes.ia_rows; i++) { + u32 reg = INI_RA(&ah->iniModes, i, 0); + u32 val = INI_RA(&ah->iniModes, i, modesIndex); REG_WRITE(ah, reg, val); if (reg >= 0x7800 && reg < 0x78a0 - && ah->ah_config.analog_shiftreg) { + && ah->config.analog_shiftreg) { udelay(100); } @@ -1276,19 +1276,19 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, } if (AR_SREV_9280(ah)) - REG_WRITE_ARRAY(&ah->ah_iniModesRxGain, modesIndex, regWrites); + REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); if (AR_SREV_9280(ah)) - REG_WRITE_ARRAY(&ah->ah_iniModesTxGain, modesIndex, regWrites); + REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); - for (i = 0; i < ah->ah_iniCommon.ia_rows; i++) { - u32 reg = INI_RA(&ah->ah_iniCommon, i, 0); - u32 val = INI_RA(&ah->ah_iniCommon, i, 1); + for (i = 0; i < ah->iniCommon.ia_rows; i++) { + u32 reg = INI_RA(&ah->iniCommon, i, 0); + u32 val = INI_RA(&ah->iniCommon, i, 1); REG_WRITE(ah, reg, val); if (reg >= 0x7800 && reg < 0x78a0 - && ah->ah_config.analog_shiftreg) { + && ah->config.analog_shiftreg) { udelay(100); } @@ -1298,7 +1298,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites); if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) { - REG_WRITE_ARRAY(&ah->ah_iniModesAdditional, modesIndex, + REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex, regWrites); } @@ -1366,7 +1366,7 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah) regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); - REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel); + REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); @@ -1566,7 +1566,7 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, (chan->chanmode == CHANNEL_G_HT40PLUS)) phymode |= AR_PHY_FC_DYN2040_PRI_CH; - if (ah->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25) + if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25) phymode |= AR_PHY_FC_DYN2040_EXT_CH; } REG_WRITE(ah, AR_PHY_TURBO, phymode); @@ -1586,7 +1586,7 @@ static bool ath9k_hw_chip_reset(struct ath_hw *ah, if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) return false; - ah->ah_chipFullSleep = false; + ah->chip_fullsleep = false; ath9k_hw_init_pll(ah, chan); ath9k_hw_set_rfmode(ah, chan); @@ -1701,7 +1701,7 @@ static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel ath9k_hw_get_channel_centers(ah, chan, ¢ers); freq = centers.synth_center; - ah->ah_config.spurmode = SPUR_ENABLE_EEPROM; + ah->config.spurmode = SPUR_ENABLE_EEPROM; for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); @@ -2123,21 +2123,21 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, { u32 saveLedState; struct ath_softc *sc = ah->ah_sc; - struct ath9k_channel *curchan = ah->ah_curchan; + struct ath9k_channel *curchan = ah->curchan; u32 saveDefAntenna; u32 macStaId1; int i, rx_chainmask, r; - ah->ah_extprotspacing = sc->ht_extprotspacing; - ah->ah_txchainmask = sc->tx_chainmask; - ah->ah_rxchainmask = sc->rx_chainmask; + ah->extprotspacing = sc->ht_extprotspacing; + ah->txchainmask = sc->tx_chainmask; + ah->rxchainmask = sc->rx_chainmask; if (AR_SREV_9285(ah)) { - ah->ah_txchainmask &= 0x1; - ah->ah_rxchainmask &= 0x1; + ah->txchainmask &= 0x1; + ah->rxchainmask &= 0x1; } else if (AR_SREV_9280(ah)) { - ah->ah_txchainmask &= 0x3; - ah->ah_rxchainmask &= 0x3; + ah->txchainmask &= 0x3; + ah->rxchainmask &= 0x3; } if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) @@ -2147,16 +2147,16 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, ath9k_hw_getnf(ah, curchan); if (bChannelChange && - (ah->ah_chipFullSleep != true) && - (ah->ah_curchan != NULL) && - (chan->channel != ah->ah_curchan->channel) && + (ah->chip_fullsleep != true) && + (ah->curchan != NULL) && + (chan->channel != ah->curchan->channel) && ((chan->channelFlags & CHANNEL_ALL) == - (ah->ah_curchan->channelFlags & CHANNEL_ALL)) && + (ah->curchan->channelFlags & CHANNEL_ALL)) && (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) && - !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) { + !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) { if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) { - ath9k_hw_loadnf(ah, ah->ah_curchan); + ath9k_hw_loadnf(ah, ah->curchan); ath9k_hw_start_nfcal(ah); return 0; } @@ -2223,10 +2223,10 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4) | macStaId1 | AR_STA_ID1_RTS_USE_DEF - | (ah->ah_config. + | (ah->config. ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) - | ah->ah_staId1Defaults); - ath9k_hw_set_operating_mode(ah, ah->ah_opmode); + | ah->sta_id1_defaults); + ath9k_hw_set_operating_mode(ah, ah->opmode); REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask)); REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4)); @@ -2252,15 +2252,15 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, for (i = 0; i < AR_NUM_DCU; i++) REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); - ah->ah_intrTxqs = 0; - for (i = 0; i < ah->ah_caps.total_queues; i++) + ah->intr_txqs = 0; + for (i = 0; i < ah->caps.total_queues; i++) ath9k_hw_resettxqueue(ah, i); - ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode); + ath9k_hw_init_interrupt_masks(ah, ah->opmode); ath9k_hw_init_qos(ah); #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) - if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) ath9k_enable_rfkill(ah); #endif ath9k_hw_init_user_settings(ah); @@ -2272,7 +2272,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, REG_WRITE(ah, AR_OBS, 8); - if (ah->ah_intrMitigation) { + if (ah->intr_mitigation) { REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); @@ -2283,7 +2283,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, if (!ath9k_hw_init_cal(ah, chan)) return -EIO;; - rx_chainmask = ah->ah_rxchainmask; + rx_chainmask = ah->rxchainmask; if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) { REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask); REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask); @@ -2321,7 +2321,7 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) { u32 keyType; - if (entry >= ah->ah_caps.keycache_size) { + if (entry >= ah->caps.keycache_size) { DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, "entry %u out of range\n", entry); return false; @@ -2348,7 +2348,7 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) } - if (ah->ah_curchan == NULL) + if (ah->curchan == NULL) return true; return true; @@ -2358,7 +2358,7 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) { u32 macHi, macLo; - if (entry >= ah->ah_caps.keycache_size) { + if (entry >= ah->caps.keycache_size) { DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE, "entry %u out of range\n", entry); return false; @@ -2386,7 +2386,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, const struct ath9k_keyval *k, const u8 *mac, int xorKey) { - const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + const struct ath9k_hw_capabilities *pCap = &ah->caps; u32 key0, key1, key2, key3, key4; u32 keyType; u32 xorMask = xorKey ? @@ -2462,7 +2462,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); (void) ath9k_hw_keysetmac(ah, entry, mac); - if (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) { + if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { u32 mic0, mic1, mic2, mic3, mic4; mic0 = get_unaligned_le32(k->kv_mic + 0); @@ -2506,7 +2506,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, (void) ath9k_hw_keysetmac(ah, entry, mac); } - if (ah->ah_curchan == NULL) + if (ah->curchan == NULL) return true; return true; @@ -2514,7 +2514,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) { - if (entry < ah->ah_caps.keycache_size) { + if (entry < ah->caps.keycache_size) { u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); if (val & AR_KEYTABLE_VALID) return true; @@ -2544,7 +2544,7 @@ static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) { REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); if (setChip) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { REG_WRITE(ah, AR_RTC_FORCE_WAKE, @@ -2608,7 +2608,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) }; DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n", - modes[ah->ah_power_mode], modes[mode], + modes[ah->power_mode], modes[mode], setChip ? "set chip " : ""); switch (mode) { @@ -2617,7 +2617,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) break; case ATH9K_PM_FULL_SLEEP: ath9k_set_power_sleep(ah, setChip); - ah->ah_chipFullSleep = true; + ah->chip_fullsleep = true; break; case ATH9K_PM_NETWORK_SLEEP: ath9k_set_power_network_sleep(ah, setChip); @@ -2627,7 +2627,7 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) "Unknown power mode %u\n", mode); return false; } - ah->ah_power_mode = mode; + ah->power_mode = mode; return status; } @@ -2636,19 +2636,19 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) { u8 i; - if (ah->ah_isPciExpress != true) + if (ah->is_pciexpress != true) return; - if (ah->ah_config.pcie_powersave_enable == 2) + if (ah->config.pcie_powersave_enable == 2) return; if (restore) return; if (AR_SREV_9280_20_OR_LATER(ah)) { - for (i = 0; i < ah->ah_iniPcieSerdes.ia_rows; i++) { - REG_WRITE(ah, INI_RA(&ah->ah_iniPcieSerdes, i, 0), - INI_RA(&ah->ah_iniPcieSerdes, i, 1)); + for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { + REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), + INI_RA(&ah->iniPcieSerdes, i, 1)); } udelay(1000); } else if (AR_SREV_9280(ah) && @@ -2660,7 +2660,7 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); - if (ah->ah_config.pcie_clock_req) + if (ah->config.pcie_clock_req) REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); else REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); @@ -2687,8 +2687,8 @@ void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore) REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); - if (ah->ah_config.pcie_waen) { - REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen); + if (ah->config.pcie_waen) { + REG_WRITE(ah, AR_WA, ah->config.pcie_waen); } else { if (AR_SREV_9285(ah)) REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); @@ -2726,7 +2726,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) { u32 isr = 0; u32 mask2 = 0; - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; u32 sync_cause = 0; bool fatal_int = false; @@ -2776,7 +2776,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) *masked = isr & ATH9K_INT_COMMON; - if (ah->ah_intrMitigation) { + if (ah->intr_mitigation) { if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) *masked |= ATH9K_INT_RX; } @@ -2791,12 +2791,12 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) *masked |= ATH9K_INT_TX; s0_s = REG_READ(ah, AR_ISR_S0_S); - ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); - ah->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); + ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); s1_s = REG_READ(ah, AR_ISR_S1_S); - ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); - ah->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); + ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); } if (isr & AR_ISR_RXORN) { @@ -2855,14 +2855,14 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah) { - return ah->ah_maskReg; + return ah->mask_reg; } enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) { - u32 omask = ah->ah_maskReg; + u32 omask = ah->mask_reg; u32 mask, mask2; - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); @@ -2883,18 +2883,18 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) mask2 = 0; if (ints & ATH9K_INT_TX) { - if (ah->ah_txOkInterruptMask) + if (ah->txok_interrupt_mask) mask |= AR_IMR_TXOK; - if (ah->ah_txDescInterruptMask) + if (ah->txdesc_interrupt_mask) mask |= AR_IMR_TXDESC; - if (ah->ah_txErrInterruptMask) + if (ah->txerr_interrupt_mask) mask |= AR_IMR_TXERR; - if (ah->ah_txEolInterruptMask) + if (ah->txeol_interrupt_mask) mask |= AR_IMR_TXEOL; } if (ints & ATH9K_INT_RX) { mask |= AR_IMR_RXERR; - if (ah->ah_intrMitigation) + if (ah->intr_mitigation) mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; else mask |= AR_IMR_RXOK | AR_IMR_RXDESC; @@ -2932,7 +2932,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); REG_WRITE(ah, AR_IMR_S2, mask | mask2); - ah->ah_maskReg = ints; + ah->mask_reg = ints; if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { if (ints & ATH9K_INT_TIM_TIMER) @@ -2970,9 +2970,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) { int flags = 0; - ah->ah_beaconInterval = beacon_period; + ah->beacon_interval = beacon_period; - switch (ah->ah_opmode) { + switch (ah->opmode) { case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_MONITOR: REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); @@ -2985,18 +2985,18 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); REG_WRITE(ah, AR_NEXT_NDP_TIMER, TU_TO_USEC(next_beacon + - (ah->ah_atimWindow ? ah-> - ah_atimWindow : 1))); + (ah->atim_window ? ah-> + atim_window : 1))); flags |= AR_NDP_TIMER_EN; case NL80211_IFTYPE_AP: REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, TU_TO_USEC(next_beacon - - ah->ah_config. + ah->config. dma_beacon_response_time)); REG_WRITE(ah, AR_NEXT_SWBA, TU_TO_USEC(next_beacon - - ah->ah_config. + ah->config. sw_beacon_response_time)); flags |= AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; @@ -3004,7 +3004,7 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) default: DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: unsupported opmode: %d\n", - __func__, ah->ah_opmode); + __func__, ah->opmode); return; break; } @@ -3027,7 +3027,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, const struct ath9k_beacon_state *bs) { u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); @@ -3089,7 +3089,7 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, bool ath9k_hw_fill_cap_info(struct ath_hw *ah) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; u16 capField = 0, eeval; eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); @@ -3101,7 +3101,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); - if (ah->ah_opmode != NL80211_IFTYPE_AP && + if (ah->opmode != NL80211_IFTYPE_AP && ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { if (ah->regulatory.current_rd == 0x64 || ah->regulatory.current_rd == 0x65) @@ -3117,7 +3117,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) if (eeval & AR5416_OPFLAGS_11A) { set_bit(ATH9K_MODE_11A, pCap->wireless_modes); - if (ah->ah_config.ht_enable) { + if (ah->config.ht_enable) { if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) set_bit(ATH9K_MODE_11NA_HT20, pCap->wireless_modes); @@ -3133,7 +3133,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) if (eeval & AR5416_OPFLAGS_11G) { set_bit(ATH9K_MODE_11B, pCap->wireless_modes); set_bit(ATH9K_MODE_11G, pCap->wireless_modes); - if (ah->ah_config.ht_enable) { + if (ah->config.ht_enable) { if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) set_bit(ATH9K_MODE_11NG_HT20, pCap->wireless_modes); @@ -3147,7 +3147,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) } pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); - if ((ah->ah_isPciExpress) + if ((ah->is_pciexpress) || (eeval & AR5416_OPFLAGS_11A)) { pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); @@ -3157,7 +3157,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) } if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) - ah->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA; + ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; pCap->low_2ghz_chan = 2312; pCap->high_2ghz_chan = 2732; @@ -3175,7 +3175,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD; - if (ah->ah_config.ht_enable) + if (ah->config.ht_enable) pCap->hw_caps |= ATH9K_HW_CAP_HT; else pCap->hw_caps &= ~ATH9K_HW_CAP_HT; @@ -3226,12 +3226,12 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) - ah->ah_rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); - if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) { - ah->ah_rfkill_gpio = - MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL); - ah->ah_rfkill_polarity = - MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY); + ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); + if (ah->rfsilent & EEP_RFSILENT_ENABLED) { + ah->rfkill_gpio = + MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); + ah->rfkill_polarity = + MS(ah->rfsilent, EEP_RFSILENT_POLARITY); pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; } @@ -3272,8 +3272,8 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) { pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX; - ah->ah_btactive_gpio = 6; - ah->ah_wlanactive_gpio = 5; + ah->btactive_gpio = 6; + ah->wlanactive_gpio = 5; } return true; @@ -3282,7 +3282,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, u32 capability, u32 *result) { - const struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + const struct ath9k_hw_capabilities *pCap = &ah->caps; switch (type) { case ATH9K_CAP_CIPHER: @@ -3302,17 +3302,17 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, case 0: return true; case 1: - return (ah->ah_staId1Defaults & + return (ah->sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE) ? true : false; } case ATH9K_CAP_TKIP_SPLIT: - return (ah->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ? + return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? false : true; case ATH9K_CAP_WME_TKIPMIC: return 0; case ATH9K_CAP_PHYCOUNTERS: - return ah->ah_hasHwPhyCounters ? 0 : -ENXIO; + return ah->has_hw_phycounters ? 0 : -ENXIO; case ATH9K_CAP_DIVERSITY: return (REG_READ(ah, AR_PHY_CCK_DETECT) & AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? @@ -3327,14 +3327,14 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { return false; } else { - return (ah->ah_staId1Defaults & + return (ah->sta_id1_defaults & AR_STA_ID1_MCAST_KSRCH) ? true : false; } } return false; case ATH9K_CAP_TSF_ADJUST: - return (ah->ah_miscMode & AR_PCU_TX_ADD_TSF) ? + return (ah->misc_mode & AR_PCU_TX_ADD_TSF) ? true : false; case ATH9K_CAP_RFSILENT: if (capability == 3) @@ -3373,10 +3373,10 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, switch (type) { case ATH9K_CAP_TKIP_MIC: if (setting) - ah->ah_staId1Defaults |= + ah->sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; else - ah->ah_staId1Defaults &= + ah->sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; return true; case ATH9K_CAP_DIVERSITY: @@ -3389,15 +3389,15 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, return true; case ATH9K_CAP_MCAST_KEYSRCH: if (setting) - ah->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH; + ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; else - ah->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH; + ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; return true; case ATH9K_CAP_TSF_ADJUST: if (setting) - ah->ah_miscMode |= AR_PCU_TX_ADD_TSF; + ah->misc_mode |= AR_PCU_TX_ADD_TSF; else - ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; + ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; return true; default: return false; @@ -3440,7 +3440,7 @@ void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) { u32 gpio_shift; - ASSERT(gpio < ah->ah_caps.num_gpio_pins); + ASSERT(gpio < ah->caps.num_gpio_pins); gpio_shift = gpio << 1; @@ -3455,7 +3455,7 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) #define MS_REG_READ(x, y) \ (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) - if (gpio >= ah->ah_caps.num_gpio_pins) + if (gpio >= ah->caps.num_gpio_pins) return 0xffffffff; if (AR_SREV_9285_10_OR_LATER(ah)) @@ -3496,7 +3496,7 @@ void ath9k_enable_rfkill(struct ath_hw *ah) REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, AR_GPIO_INPUT_MUX2_RFSILENT); - ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio); + ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); } #endif @@ -3534,7 +3534,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hw *ah, *antenna_cfgd = true; break; case ATH9K_ANT_FIXED_B: - if (ah->ah_caps.tx_chainmask > + if (ah->caps.tx_chainmask > ATH9K_ANTENNA1_CHAINMASK) { *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK; } @@ -3550,7 +3550,7 @@ bool ath9k_hw_setantennaswitch(struct ath_hw *ah, break; } } else { - ah->ah_diversityControl = settings; + ah->diversity_control = settings; } return true; @@ -3608,7 +3608,7 @@ bool ath9k_hw_disable(struct ath_hw *ah) bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) { - struct ath9k_channel *chan = ah->ah_curchan; + struct ath9k_channel *chan = ah->curchan; struct ieee80211_channel *channel = chan->chan; ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER); @@ -3631,7 +3631,7 @@ void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) void ath9k_hw_setopmode(struct ath_hw *ah) { - ath9k_hw_set_operating_mode(ah, ah->ah_opmode); + ath9k_hw_set_operating_mode(ah, ah->opmode); } void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) @@ -3690,9 +3690,9 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah) bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) { if (setting) - ah->ah_miscMode |= AR_PCU_TX_ADD_TSF; + ah->misc_mode |= AR_PCU_TX_ADD_TSF; else - ah->ah_miscMode &= ~AR_PCU_TX_ADD_TSF; + ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; return true; } @@ -3701,11 +3701,11 @@ bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) { if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); - ah->ah_slottime = (u32) -1; + ah->slottime = (u32) -1; return false; } else { REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us)); - ah->ah_slottime = us; + ah->slottime = us; return true; } } @@ -3715,7 +3715,7 @@ void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode) u32 macmode; if (mode == ATH9K_HT_MACMODE_2040 && - !ah->ah_config.cwm_ignore_extcca) + !ah->config.cwm_ignore_extcca) macmode = AR_2040_JOINED_RX_CLEAR; else macmode = 0; @@ -3740,12 +3740,12 @@ void ath9k_hw_btcoex_enable(struct ath_hw *ah) /* Set input mux for bt_active to gpio pin */ REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, AR_GPIO_INPUT_MUX1_BT_ACTIVE, - ah->ah_btactive_gpio); + ah->btactive_gpio); /* Configure the desired gpio port for input */ - ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio); + ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio); /* Configure the desired GPIO port for TX_FRAME output */ - ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio, + ath9k_hw_cfg_output(ah, ah->wlanactive_gpio, AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); } diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index f8f46db665c2..82111636c693 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -420,152 +420,148 @@ struct ath9k_hw_version { struct ath_hw { struct ath_softc *ah_sc; struct ath9k_hw_version hw_version; - struct ath9k_ops_config ah_config; - struct ath9k_hw_capabilities ah_caps; + struct ath9k_ops_config config; + struct ath9k_hw_capabilities caps; struct ath9k_regulatory regulatory; - struct ath9k_channel ah_channels[38]; - struct ath9k_channel *ah_curchan; + struct ath9k_channel channels[38]; + struct ath9k_channel *curchan; union { struct ar5416_eeprom_def def; struct ar5416_eeprom_4k map4k; - } ah_eeprom; + } eeprom; const struct eeprom_ops *eep_ops; + enum ath9k_eep_map eep_map; bool sw_mgmt_crypto; - bool ah_isPciExpress; + bool is_pciexpress; u8 macaddr[ETH_ALEN]; - u16 ah_txTrigLevel; - u16 ah_rfsilent; - u32 ah_rfkill_gpio; - u32 ah_rfkill_polarity; - u32 ah_btactive_gpio; - u32 ah_wlanactive_gpio; + u16 tx_trig_level; + u16 rfsilent; + u32 rfkill_gpio; + u32 rfkill_polarity; + u32 btactive_gpio; + u32 wlanactive_gpio; u32 ah_flags; - enum nl80211_iftype ah_opmode; - enum ath9k_power_mode ah_power_mode; - enum ath9k_power_mode ah_restore_mode; + enum nl80211_iftype opmode; + enum ath9k_power_mode power_mode; + enum ath9k_power_mode restore_mode; struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; - struct ar5416Stats ah_stats; - struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES]; - - int16_t ah_curchanRadIndex; - u32 ah_maskReg; - u32 ah_txOkInterruptMask; - u32 ah_txErrInterruptMask; - u32 ah_txDescInterruptMask; - u32 ah_txEolInterruptMask; - u32 ah_txUrnInterruptMask; - bool ah_chipFullSleep; - u32 ah_atimWindow; - u16 ah_antennaSwitchSwap; - enum ath9k_ant_setting ah_diversityControl; + struct ar5416Stats stats; + struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; + + int16_t curchan_rad_index; + u32 mask_reg; + u32 txok_interrupt_mask; + u32 txerr_interrupt_mask; + u32 txdesc_interrupt_mask; + u32 txeol_interrupt_mask; + u32 txurn_interrupt_mask; + bool chip_fullsleep; + u32 atim_window; + u16 antenna_switch_swap; + enum ath9k_ant_setting diversity_control; /* Calibration */ - enum hal_cal_types ah_suppCals; - struct hal_cal_list ah_iqCalData; - struct hal_cal_list ah_adcGainCalData; - struct hal_cal_list ah_adcDcCalInitData; - struct hal_cal_list ah_adcDcCalData; - struct hal_cal_list *ah_cal_list; - struct hal_cal_list *ah_cal_list_last; - struct hal_cal_list *ah_cal_list_curr; -#define ah_totalPowerMeasI ah_Meas0.unsign -#define ah_totalPowerMeasQ ah_Meas1.unsign -#define ah_totalIqCorrMeas ah_Meas2.sign -#define ah_totalAdcIOddPhase ah_Meas0.unsign -#define ah_totalAdcIEvenPhase ah_Meas1.unsign -#define ah_totalAdcQOddPhase ah_Meas2.unsign -#define ah_totalAdcQEvenPhase ah_Meas3.unsign -#define ah_totalAdcDcOffsetIOddPhase ah_Meas0.sign -#define ah_totalAdcDcOffsetIEvenPhase ah_Meas1.sign -#define ah_totalAdcDcOffsetQOddPhase ah_Meas2.sign -#define ah_totalAdcDcOffsetQEvenPhase ah_Meas3.sign + enum hal_cal_types supp_cals; + struct hal_cal_list iq_caldata; + struct hal_cal_list adcgain_caldata; + struct hal_cal_list adcdc_calinitdata; + struct hal_cal_list adcdc_caldata; + struct hal_cal_list *cal_list; + struct hal_cal_list *cal_list_last; + struct hal_cal_list *cal_list_curr; +#define totalPowerMeasI meas0.unsign +#define totalPowerMeasQ meas1.unsign +#define totalIqCorrMeas meas2.sign +#define totalAdcIOddPhase meas0.unsign +#define totalAdcIEvenPhase meas1.unsign +#define totalAdcQOddPhase meas2.unsign +#define totalAdcQEvenPhase meas3.unsign +#define totalAdcDcOffsetIOddPhase meas0.sign +#define totalAdcDcOffsetIEvenPhase meas1.sign +#define totalAdcDcOffsetQOddPhase meas2.sign +#define totalAdcDcOffsetQEvenPhase meas3.sign union { u32 unsign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS]; - } ah_Meas0; + } meas0; union { u32 unsign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS]; - } ah_Meas1; + } meas1; union { u32 unsign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS]; - } ah_Meas2; + } meas2; union { u32 unsign[AR5416_MAX_CHAINS]; int32_t sign[AR5416_MAX_CHAINS]; - } ah_Meas3; - u16 ah_CalSamples; + } meas3; + u16 cal_samples; - u32 ah_staId1Defaults; - u32 ah_miscMode; + u32 sta_id1_defaults; + u32 misc_mode; enum { AUTO_32KHZ, USE_32KHZ, DONT_USE_32KHZ, - } ah_enable32kHzClock; + } enable_32kHz_clock; /* RF */ - u32 *ah_analogBank0Data; - u32 *ah_analogBank1Data; - u32 *ah_analogBank2Data; - u32 *ah_analogBank3Data; - u32 *ah_analogBank6Data; - u32 *ah_analogBank6TPCData; - u32 *ah_analogBank7Data; - u32 *ah_addac5416_21; - u32 *ah_bank6Temp; - - int16_t ah_txPowerIndexOffset; - u32 ah_beaconInterval; - u32 ah_slottime; - u32 ah_acktimeout; - u32 ah_ctstimeout; - u32 ah_globaltxtimeout; - u8 ah_gBeaconRate; - u32 ah_gpioSelect; - u32 ah_polarity; - u32 ah_gpioBit; + u32 *analogBank0Data; + u32 *analogBank1Data; + u32 *analogBank2Data; + u32 *analogBank3Data; + u32 *analogBank6Data; + u32 *analogBank6TPCData; + u32 *analogBank7Data; + u32 *addac5416_21; + u32 *bank6Temp; + + int16_t txpower_indexoffset; + u32 beacon_interval; + u32 slottime; + u32 acktimeout; + u32 ctstimeout; + u32 globaltxtimeout; + u8 gbeacon_rate; /* ANI */ - u32 ah_procPhyErr; - bool ah_hasHwPhyCounters; - u32 ah_aniPeriod; - struct ar5416AniState *ah_curani; - struct ar5416AniState ah_ani[255]; - int ah_totalSizeDesired[5]; - int ah_coarseHigh[5]; - int ah_coarseLow[5]; - int ah_firpwr[5]; - enum ath9k_ani_cmd ah_ani_function; - - u32 ah_intrTxqs; - bool ah_intrMitigation; - enum ath9k_ht_extprotspacing ah_extprotspacing; - u8 ah_txchainmask; - u8 ah_rxchainmask; - - struct ar5416IniArray ah_iniModes; - struct ar5416IniArray ah_iniCommon; - struct ar5416IniArray ah_iniBank0; - struct ar5416IniArray ah_iniBB_RfGain; - struct ar5416IniArray ah_iniBank1; - struct ar5416IniArray ah_iniBank2; - struct ar5416IniArray ah_iniBank3; - struct ar5416IniArray ah_iniBank6; - struct ar5416IniArray ah_iniBank6TPC; - struct ar5416IniArray ah_iniBank7; - struct ar5416IniArray ah_iniAddac; - struct ar5416IniArray ah_iniPcieSerdes; - struct ar5416IniArray ah_iniModesAdditional; - struct ar5416IniArray ah_iniModesRxGain; - struct ar5416IniArray ah_iniModesTxGain; - /* To indicate EEPROM mapping used */ - enum hal_eep_map ah_eep_map; + u32 proc_phyerr; + bool has_hw_phycounters; + u32 aniperiod; + struct ar5416AniState *curani; + struct ar5416AniState ani[255]; + int totalSizeDesired[5]; + int coarse_high[5]; + int coarse_low[5]; + int firpwr[5]; + enum ath9k_ani_cmd ani_function; + + u32 intr_txqs; + bool intr_mitigation; + enum ath9k_ht_extprotspacing extprotspacing; + u8 txchainmask; + u8 rxchainmask; + + struct ar5416IniArray iniModes; + struct ar5416IniArray iniCommon; + struct ar5416IniArray iniBank0; + struct ar5416IniArray iniBB_RfGain; + struct ar5416IniArray iniBank1; + struct ar5416IniArray iniBank2; + struct ar5416IniArray iniBank3; + struct ar5416IniArray iniBank6; + struct ar5416IniArray iniBank6TPC; + struct ar5416IniArray iniBank7; + struct ar5416IniArray iniAddac; + struct ar5416IniArray iniPcieSerdes; + struct ar5416IniArray iniModesAdditional; + struct ar5416IniArray iniModesRxGain; + struct ar5416IniArray iniModesTxGain; }; /* Attach, Detach, Reset */ diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c index ac2071444017..f32c622db6e7 100644 --- a/drivers/net/wireless/ath9k/mac.c +++ b/drivers/net/wireless/ath9k/mac.c @@ -21,18 +21,18 @@ static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, { DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", - ah->ah_txOkInterruptMask, ah->ah_txErrInterruptMask, - ah->ah_txDescInterruptMask, ah->ah_txEolInterruptMask, - ah->ah_txUrnInterruptMask); + ah->txok_interrupt_mask, ah->txerr_interrupt_mask, + ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, + ah->txurn_interrupt_mask); REG_WRITE(ah, AR_IMR_S0, - SM(ah->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK) - | SM(ah->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)); + SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) + | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC)); REG_WRITE(ah, AR_IMR_S1, - SM(ah->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR) - | SM(ah->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)); + SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) + | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL)); REG_RMW_FIELD(ah, AR_IMR_S2, - AR_IMR_S2_QCU_TXURN, ah->ah_txUrnInterruptMask); + AR_IMR_S2_QCU_TXURN, ah->txurn_interrupt_mask); } u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q) @@ -75,10 +75,10 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) u32 txcfg, curLevel, newLevel; enum ath9k_int omask; - if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD) + if (ah->tx_trig_level >= MAX_TX_FIFO_THRESHOLD) return false; - omask = ath9k_hw_set_interrupts(ah, ah->ah_maskReg & ~ATH9K_INT_GLOBAL); + omask = ath9k_hw_set_interrupts(ah, ah->mask_reg & ~ATH9K_INT_GLOBAL); txcfg = REG_READ(ah, AR_TXCFG); curLevel = MS(txcfg, AR_FTRIG); @@ -94,7 +94,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel) ath9k_hw_set_interrupts(ah, omask); - ah->ah_txTrigLevel = newLevel; + ah->tx_trig_level = newLevel; return newLevel != curLevel; } @@ -104,7 +104,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) #define ATH9K_TX_STOP_DMA_TIMEOUT 4000 /* usec */ #define ATH9K_TIME_QUANTUM 100 /* usec */ - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_tx_queue_info *qi; u32 tsfLow, j, wait; u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; @@ -114,7 +114,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q) return false; } - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -296,7 +296,7 @@ void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds, { struct ar5416_desc *ads = AR5416DESC(ds); - txPower += ah->ah_txPowerIndexOffset; + txPower += ah->txpower_indexoffset; if (txPower > 63) txPower = 63; @@ -442,15 +442,15 @@ void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds, void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs) { - *txqs &= ah->ah_intrTxqs; - ah->ah_intrTxqs &= ~(*txqs); + *txqs &= ah->intr_txqs; + ah->intr_txqs &= ~(*txqs); } bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, const struct ath9k_tx_queue_info *qinfo) { u32 cw; - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_tx_queue_info *qi; if (q >= pCap->total_queues) { @@ -458,7 +458,7 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, return false; } - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -517,7 +517,7 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, struct ath9k_tx_queue_info *qinfo) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_tx_queue_info *qi; if (q >= pCap->total_queues) { @@ -525,7 +525,7 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, return false; } - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue\n"); return false; @@ -553,7 +553,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, const struct ath9k_tx_queue_info *qinfo) { struct ath9k_tx_queue_info *qi; - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; int q; switch (type) { @@ -571,7 +571,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, break; case ATH9K_TX_QUEUE_DATA: for (q = 0; q < pCap->total_queues; q++) - if (ah->ah_txq[q].tqi_type == + if (ah->txq[q].tqi_type == ATH9K_TX_QUEUE_INACTIVE) break; if (q == pCap->total_queues) { @@ -587,7 +587,7 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "queue %u\n", q); - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "tx queue %u already active\n", q); @@ -616,14 +616,14 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; struct ath9k_tx_queue_info *qi; if (q >= pCap->total_queues) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "invalid queue num %u\n", q); return false; } - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); return false; @@ -632,11 +632,11 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "release queue %u\n", q); qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; - ah->ah_txOkInterruptMask &= ~(1 << q); - ah->ah_txErrInterruptMask &= ~(1 << q); - ah->ah_txDescInterruptMask &= ~(1 << q); - ah->ah_txEolInterruptMask &= ~(1 << q); - ah->ah_txUrnInterruptMask &= ~(1 << q); + ah->txok_interrupt_mask &= ~(1 << q); + ah->txerr_interrupt_mask &= ~(1 << q); + ah->txdesc_interrupt_mask &= ~(1 << q); + ah->txeol_interrupt_mask &= ~(1 << q); + ah->txurn_interrupt_mask &= ~(1 << q); ath9k_hw_set_txq_interrupts(ah, qi); return true; @@ -644,8 +644,8 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q) bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) { - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; - struct ath9k_channel *chan = ah->ah_curchan; + struct ath9k_hw_capabilities *pCap = &ah->caps; + struct ath9k_channel *chan = ah->curchan; struct ath9k_tx_queue_info *qi; u32 cwMin, chanCwMin, value; @@ -654,7 +654,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) return false; } - qi = &ah->ah_txq[q]; + qi = &ah->txq[q]; if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "inactive queue %u\n", q); return true; @@ -742,9 +742,9 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) | AR_Q_MISC_CBR_INCR_DIS1 | AR_Q_MISC_CBR_INCR_DIS0); value = (qi->tqi_readyTime - - (ah->ah_config.sw_beacon_response_time - - ah->ah_config.dma_beacon_response_time) - - ah->ah_config.additional_swba_backoff) * 1024; + (ah->config.sw_beacon_response_time - + ah->config.dma_beacon_response_time) - + ah->config.additional_swba_backoff) * 1024; REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_EN); REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q)) @@ -772,25 +772,25 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q) } if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE) - ah->ah_txOkInterruptMask |= 1 << q; + ah->txok_interrupt_mask |= 1 << q; else - ah->ah_txOkInterruptMask &= ~(1 << q); + ah->txok_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE) - ah->ah_txErrInterruptMask |= 1 << q; + ah->txerr_interrupt_mask |= 1 << q; else - ah->ah_txErrInterruptMask &= ~(1 << q); + ah->txerr_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE) - ah->ah_txDescInterruptMask |= 1 << q; + ah->txdesc_interrupt_mask |= 1 << q; else - ah->ah_txDescInterruptMask &= ~(1 << q); + ah->txdesc_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE) - ah->ah_txEolInterruptMask |= 1 << q; + ah->txeol_interrupt_mask |= 1 << q; else - ah->ah_txEolInterruptMask &= ~(1 << q); + ah->txeol_interrupt_mask &= ~(1 << q); if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE) - ah->ah_txUrnInterruptMask |= 1 << q; + ah->txurn_interrupt_mask |= 1 << q; else - ah->ah_txUrnInterruptMask &= ~(1 << q); + ah->txurn_interrupt_mask &= ~(1 << q); ath9k_hw_set_txq_interrupts(ah, qi); return true; @@ -865,7 +865,7 @@ bool ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, u32 size, u32 flags) { struct ar5416_desc *ads = AR5416DESC(ds); - struct ath9k_hw_capabilities *pCap = &ah->ah_caps; + struct ath9k_hw_capabilities *pCap = &ah->caps; ads->ds_ctl1 = size & AR_BufLen; if (flags & ATH9K_RXDESC_INTREQ) diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index a50f989abd6c..fc3460f8f7fc 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c @@ -267,7 +267,7 @@ static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan) DPRINTF(sc, ATH_DBG_CONFIG, "(%u MHz) -> (%u MHz), chanwidth: %d\n", - sc->sc_ah->ah_curchan->channel, + sc->sc_ah->curchan->channel, channel->center_freq, sc->tx_chan_width); spin_lock_bh(&sc->sc_resetlock); @@ -363,30 +363,30 @@ static void ath_ani_calibrate(unsigned long data) /* Call ANI routine if necessary */ if (aniflag) ath9k_hw_ani_monitor(ah, &sc->nodestats, - ah->ah_curchan); + ah->curchan); /* Perform calibration if necessary */ if (longcal || shortcal) { bool iscaldone = false; - if (ath9k_hw_calibrate(ah, ah->ah_curchan, + if (ath9k_hw_calibrate(ah, ah->curchan, sc->rx_chainmask, longcal, &iscaldone)) { if (longcal) sc->ani.noise_floor = ath9k_hw_getchan_noise(ah, - ah->ah_curchan); + ah->curchan); DPRINTF(sc, ATH_DBG_ANI, "calibrate chan %u/%x nf: %d\n", - ah->ah_curchan->channel, - ah->ah_curchan->channelFlags, + ah->curchan->channel, + ah->curchan->channelFlags, sc->ani.noise_floor); } else { DPRINTF(sc, ATH_DBG_ANY, "calibrate chan %u/%x failed\n", - ah->ah_curchan->channel, - ah->ah_curchan->channelFlags); + ah->curchan->channel, + ah->curchan->channelFlags); } sc->ani.caldone = iscaldone; } @@ -398,7 +398,7 @@ static void ath_ani_calibrate(unsigned long data) * short calibration and long calibration. */ cal_interval = ATH_LONG_CALINTERVAL; - if (sc->sc_ah->ah_config.enable_ani) + if (sc->sc_ah->config.enable_ani) cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); if (!sc->ani.caldone) cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL); @@ -416,9 +416,9 @@ static void ath_update_chainmask(struct ath_softc *sc, int is_ht) { sc->sc_flags |= SC_OP_CHAINMASK_UPDATE; if (is_ht || - (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { - sc->tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask; - sc->rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask; + (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { + sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask; + sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask; } else { sc->tx_chainmask = 1; sc->rx_chainmask = 1; @@ -564,7 +564,7 @@ irqreturn_t ath_isr(int irq, void *dev) ath9k_hw_set_interrupts(ah, sc->imask); } if (status & ATH9K_INT_TIM_TIMER) { - if (!(ah->ah_caps.hw_caps & + if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { /* Clear RxAbort bit so that we can * receive frames */ @@ -1098,7 +1098,7 @@ static void ath_radio_enable(struct ath_softc *sc) ath9k_ps_wakeup(sc); spin_lock_bh(&sc->sc_resetlock); - r = ath9k_hw_reset(ah, ah->ah_curchan, false); + r = ath9k_hw_reset(ah, ah->curchan, false); if (r) { DPRINTF(sc, ATH_DBG_FATAL, @@ -1151,7 +1151,7 @@ static void ath_radio_disable(struct ath_softc *sc) ath_flushrecv(sc); /* flush recv queue */ spin_lock_bh(&sc->sc_resetlock); - r = ath9k_hw_reset(ah, ah->ah_curchan, false); + r = ath9k_hw_reset(ah, ah->curchan, false); if (r) { DPRINTF(sc, ATH_DBG_FATAL, "Unable to reset channel %u (%uMhz) " @@ -1169,8 +1169,8 @@ static bool ath_is_rfkill_set(struct ath_softc *sc) { struct ath_hw *ah = sc->sc_ah; - return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) == - ah->ah_rfkill_polarity; + return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) == + ah->rfkill_polarity; } /* h/w rfkill poll function */ @@ -1267,7 +1267,7 @@ static int ath_init_sw_rfkill(struct ath_softc *sc) /* Deinitialize rfkill */ static void ath_deinit_rfkill(struct ath_softc *sc) { - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) { @@ -1279,7 +1279,7 @@ static void ath_deinit_rfkill(struct ath_softc *sc) static int ath_start_rfkill_poll(struct ath_softc *sc) { - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll, 0); @@ -1380,7 +1380,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) sc->sc_ah = ah; /* Get the hardware key cache size. */ - sc->keymax = ah->ah_caps.keycache_size; + sc->keymax = ah->caps.keycache_size; if (sc->keymax > ATH_KEYMAX) { DPRINTF(sc, ATH_DBG_KEYCACHE, "Warning, using only %u entries in %u key cache\n", @@ -1399,7 +1399,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) goto bad; /* default to MONITOR mode */ - sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR; + sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; /* Setup rate tables */ @@ -1502,18 +1502,18 @@ static int ath_init(u16 devid, struct ath_softc *sc) sc->config.txpowlimit = ATH_TXPOWER_MAX; /* 11n Capabilities */ - if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { + if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) { sc->sc_flags |= SC_OP_TXAGGR; sc->sc_flags |= SC_OP_RXAGGR; } - sc->tx_chainmask = ah->ah_caps.tx_chainmask; - sc->rx_chainmask = ah->ah_caps.rx_chainmask; + sc->tx_chainmask = ah->caps.tx_chainmask; + sc->rx_chainmask = ah->caps.rx_chainmask; ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); sc->rx.defant = ath9k_hw_getdefantenna(ah); - if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { + if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); ATH_SET_VIF_BSSID_MASK(sc->bssidmask); ath9k_hw_setbssidmask(sc); @@ -1537,7 +1537,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) sc->sbands[IEEE80211_BAND_2GHZ].n_channels = ARRAY_SIZE(ath9k_2ghz_chantable); - if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) { + if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) { sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable; sc->sbands[IEEE80211_BAND_5GHZ].bitrates = sc->rates[IEEE80211_BAND_5GHZ]; @@ -1546,7 +1546,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) ARRAY_SIZE(ath9k_5ghz_chantable); } - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX) ath9k_hw_btcoex_enable(sc->sc_ah); return 0; @@ -1603,14 +1603,14 @@ int ath_attach(u16 devid, struct ath_softc *sc) hw->rate_control_algorithm = "ath9k_rate_control"; - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); - if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) + if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); } hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ]; - if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) + if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &sc->sbands[IEEE80211_BAND_5GHZ]; @@ -1625,7 +1625,7 @@ int ath_attach(u16 devid, struct ath_softc *sc) #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) /* Initialze h/w Rfkill */ - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll); /* Initialize s/w rfkill */ @@ -1681,7 +1681,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx) ath_flushrecv(sc); spin_lock_bh(&sc->sc_resetlock); - r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false); + r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); if (r) DPRINTF(sc, ATH_DBG_FATAL, "Unable to reset hardware; reset status %u\n", r); @@ -1755,7 +1755,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, * descriptors that cross the 4K page boundary. Assume * one skipped descriptor per 4K page. */ - if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { u32 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); u32 dma_len; @@ -1795,7 +1795,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, bf->bf_desc = ds; bf->bf_daddr = DS2PHYS(dd, ds); - if (!(sc->sc_ah->ah_caps.hw_caps & + if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { /* * Skip descriptor addresses which can cause 4KB @@ -1939,7 +1939,7 @@ static int ath9k_start(struct ieee80211_hw *hw) pos = curchan->hw_value; - init_channel = &sc->sc_ah->ah_channels[pos]; + init_channel = &sc->sc_ah->channels[pos]; ath9k_update_ichannel(sc, init_channel); /* Reset SERDES registers */ @@ -1989,10 +1989,10 @@ static int ath9k_start(struct ieee80211_hw *hw) | ATH9K_INT_RXEOL | ATH9K_INT_RXORN | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT) sc->imask |= ATH9K_INT_GTT; - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) sc->imask |= ATH9K_INT_CST; ath_cache_conf_rate(sc, &hw->conf); @@ -2092,7 +2092,7 @@ static void ath9k_stop(struct ieee80211_hw *hw) sc->rx.rxlink = NULL; #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); #endif /* disable HAL and put h/w to sleep */ @@ -2149,7 +2149,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, sc->nvifs++; /* Set the device opmode */ - sc->sc_ah->ah_opmode = ic_opmode; + sc->sc_ah->opmode = ic_opmode; /* * Enable MIB interrupts when there are hardware phy counters. @@ -2165,7 +2165,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw, * that does, if not overridden by configuration, * enable the TIM interrupt when operating as station. */ - if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) && + if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) && (conf->type == NL80211_IFTYPE_STATION) && !sc->config.swBeaconProcess) sc->imask |= ATH9K_INT_TIM; @@ -2198,8 +2198,8 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw, del_timer_sync(&sc->ani.timer); /* Reclaim beacon resources */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || - sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_AP || + sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) { ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); ath_beacon_return(sc, avp); } @@ -2248,11 +2248,11 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed) curchan->center_freq); /* XXX: remove me eventualy */ - ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]); + ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]); ath_update_chainmask(sc, conf_is_ht(conf)); - if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) { + if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) { DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n"); mutex_unlock(&sc->mutex); return -EINVAL; @@ -2280,8 +2280,8 @@ static int ath9k_config_interface(struct ieee80211_hw *hw, /* TODO: Need to decide which hw opmode to use for multi-interface * cases */ if (vif->type == NL80211_IFTYPE_AP && - ah->ah_opmode != NL80211_IFTYPE_AP) { - ah->ah_opmode = NL80211_IFTYPE_STATION; + ah->opmode != NL80211_IFTYPE_AP) { + ah->opmode = NL80211_IFTYPE_STATION; ath9k_hw_setopmode(ah); memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN); sc->curaid = 0; diff --git a/drivers/net/wireless/ath9k/pci.c b/drivers/net/wireless/ath9k/pci.c index eac8db742602..c28afe42b269 100644 --- a/drivers/net/wireless/ath9k/pci.c +++ b/drivers/net/wireless/ath9k/pci.c @@ -228,7 +228,7 @@ static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); #endif @@ -269,7 +269,7 @@ static int ath_pci_resume(struct pci_dev *pdev) * check the h/w rfkill state on resume * and start the rfkill poll timer */ - if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) + if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll, 0); #endif diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c index 5a42969b35a6..52aa2a7abe7a 100644 --- a/drivers/net/wireless/ath9k/phy.c +++ b/drivers/net/wireless/ath9k/phy.c @@ -20,7 +20,7 @@ void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, u32 freqIndex, int regWrites) { - REG_WRITE_ARRAY(&ah->ah_iniBB_RfGain, freqIndex, regWrites); + REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites); } bool @@ -90,8 +90,8 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) REG_WRITE(ah, AR_PHY(0x37), reg32); - ah->ah_curchan = chan; - ah->ah_curchanRadIndex = -1; + ah->curchan = chan; + ah->curchan_rad_index = -1; return true; } @@ -160,8 +160,8 @@ ath9k_hw_ar9280_set_channel(struct ath_hw *ah, REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); - ah->ah_curchan = chan; - ah->ah_curchanRadIndex = -1; + ah->curchan = chan; + ah->curchan_rad_index = -1; return true; } @@ -207,19 +207,19 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV); - RF_BANK_SETUP(ah->ah_analogBank0Data, &ah->ah_iniBank0, 1); + RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1); - RF_BANK_SETUP(ah->ah_analogBank1Data, &ah->ah_iniBank1, 1); + RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1); - RF_BANK_SETUP(ah->ah_analogBank2Data, &ah->ah_iniBank2, 1); + RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1); - RF_BANK_SETUP(ah->ah_analogBank3Data, &ah->ah_iniBank3, + RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3, modesIndex); { int i; - for (i = 0; i < ah->ah_iniBank6TPC.ia_rows; i++) { - ah->ah_analogBank6Data[i] = - INI_RA(&ah->ah_iniBank6TPC, i, modesIndex); + for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) { + ah->analogBank6Data[i] = + INI_RA(&ah->iniBank6TPC, i, modesIndex); } } @@ -227,33 +227,33 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, if (IS_CHAN_2GHZ(chan)) { ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); - ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->analogBank6Data, ob2GHz, 3, 197, 0); - ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->analogBank6Data, db2GHz, 3, 194, 0); } else { ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); - ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->analogBank6Data, ob5GHz, 3, 203, 0); - ath9k_phy_modify_rx_buffer(ah->ah_analogBank6Data, + ath9k_phy_modify_rx_buffer(ah->analogBank6Data, db5GHz, 3, 200, 0); } } - RF_BANK_SETUP(ah->ah_analogBank7Data, &ah->ah_iniBank7, 1); + RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank0, ah->ah_analogBank0Data, + REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data, regWrites); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank1, ah->ah_analogBank1Data, + REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data, regWrites); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank2, ah->ah_analogBank2Data, + REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data, regWrites); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank3, ah->ah_analogBank3Data, + REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data, regWrites); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank6TPC, ah->ah_analogBank6Data, + REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data, regWrites); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank7, ah->ah_analogBank7Data, + REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data, regWrites); return true; @@ -262,99 +262,99 @@ ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, void ath9k_hw_rfdetach(struct ath_hw *ah) { - if (ah->ah_analogBank0Data != NULL) { - kfree(ah->ah_analogBank0Data); - ah->ah_analogBank0Data = NULL; + if (ah->analogBank0Data != NULL) { + kfree(ah->analogBank0Data); + ah->analogBank0Data = NULL; } - if (ah->ah_analogBank1Data != NULL) { - kfree(ah->ah_analogBank1Data); - ah->ah_analogBank1Data = NULL; + if (ah->analogBank1Data != NULL) { + kfree(ah->analogBank1Data); + ah->analogBank1Data = NULL; } - if (ah->ah_analogBank2Data != NULL) { - kfree(ah->ah_analogBank2Data); - ah->ah_analogBank2Data = NULL; + if (ah->analogBank2Data != NULL) { + kfree(ah->analogBank2Data); + ah->analogBank2Data = NULL; } - if (ah->ah_analogBank3Data != NULL) { - kfree(ah->ah_analogBank3Data); - ah->ah_analogBank3Data = NULL; + if (ah->analogBank3Data != NULL) { + kfree(ah->analogBank3Data); + ah->analogBank3Data = NULL; } - if (ah->ah_analogBank6Data != NULL) { - kfree(ah->ah_analogBank6Data); - ah->ah_analogBank6Data = NULL; + if (ah->analogBank6Data != NULL) { + kfree(ah->analogBank6Data); + ah->analogBank6Data = NULL; } - if (ah->ah_analogBank6TPCData != NULL) { - kfree(ah->ah_analogBank6TPCData); - ah->ah_analogBank6TPCData = NULL; + if (ah->analogBank6TPCData != NULL) { + kfree(ah->analogBank6TPCData); + ah->analogBank6TPCData = NULL; } - if (ah->ah_analogBank7Data != NULL) { - kfree(ah->ah_analogBank7Data); - ah->ah_analogBank7Data = NULL; + if (ah->analogBank7Data != NULL) { + kfree(ah->analogBank7Data); + ah->analogBank7Data = NULL; } - if (ah->ah_addac5416_21 != NULL) { - kfree(ah->ah_addac5416_21); - ah->ah_addac5416_21 = NULL; + if (ah->addac5416_21 != NULL) { + kfree(ah->addac5416_21); + ah->addac5416_21 = NULL; } - if (ah->ah_bank6Temp != NULL) { - kfree(ah->ah_bank6Temp); - ah->ah_bank6Temp = NULL; + if (ah->bank6Temp != NULL) { + kfree(ah->bank6Temp); + ah->bank6Temp = NULL; } } bool ath9k_hw_init_rf(struct ath_hw *ah, int *status) { if (!AR_SREV_9280_10_OR_LATER(ah)) { - ah->ah_analogBank0Data = + ah->analogBank0Data = kzalloc((sizeof(u32) * - ah->ah_iniBank0.ia_rows), GFP_KERNEL); - ah->ah_analogBank1Data = + ah->iniBank0.ia_rows), GFP_KERNEL); + ah->analogBank1Data = kzalloc((sizeof(u32) * - ah->ah_iniBank1.ia_rows), GFP_KERNEL); - ah->ah_analogBank2Data = + ah->iniBank1.ia_rows), GFP_KERNEL); + ah->analogBank2Data = kzalloc((sizeof(u32) * - ah->ah_iniBank2.ia_rows), GFP_KERNEL); - ah->ah_analogBank3Data = + ah->iniBank2.ia_rows), GFP_KERNEL); + ah->analogBank3Data = kzalloc((sizeof(u32) * - ah->ah_iniBank3.ia_rows), GFP_KERNEL); - ah->ah_analogBank6Data = + ah->iniBank3.ia_rows), GFP_KERNEL); + ah->analogBank6Data = kzalloc((sizeof(u32) * - ah->ah_iniBank6.ia_rows), GFP_KERNEL); - ah->ah_analogBank6TPCData = + ah->iniBank6.ia_rows), GFP_KERNEL); + ah->analogBank6TPCData = kzalloc((sizeof(u32) * - ah->ah_iniBank6TPC.ia_rows), GFP_KERNEL); - ah->ah_analogBank7Data = + ah->iniBank6TPC.ia_rows), GFP_KERNEL); + ah->analogBank7Data = kzalloc((sizeof(u32) * - ah->ah_iniBank7.ia_rows), GFP_KERNEL); - - if (ah->ah_analogBank0Data == NULL - || ah->ah_analogBank1Data == NULL - || ah->ah_analogBank2Data == NULL - || ah->ah_analogBank3Data == NULL - || ah->ah_analogBank6Data == NULL - || ah->ah_analogBank6TPCData == NULL - || ah->ah_analogBank7Data == NULL) { + ah->iniBank7.ia_rows), GFP_KERNEL); + + if (ah->analogBank0Data == NULL + || ah->analogBank1Data == NULL + || ah->analogBank2Data == NULL + || ah->analogBank3Data == NULL + || ah->analogBank6Data == NULL + || ah->analogBank6TPCData == NULL + || ah->analogBank7Data == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Cannot allocate RF banks\n"); *status = -ENOMEM; return false; } - ah->ah_addac5416_21 = + ah->addac5416_21 = kzalloc((sizeof(u32) * - ah->ah_iniAddac.ia_rows * - ah->ah_iniAddac.ia_columns), GFP_KERNEL); - if (ah->ah_addac5416_21 == NULL) { + ah->iniAddac.ia_rows * + ah->iniAddac.ia_columns), GFP_KERNEL); + if (ah->addac5416_21 == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, - "Cannot allocate ah_addac5416_21\n"); + "Cannot allocate addac5416_21\n"); *status = -ENOMEM; return false; } - ah->ah_bank6Temp = + ah->bank6Temp = kzalloc((sizeof(u32) * - ah->ah_iniBank6.ia_rows), GFP_KERNEL); - if (ah->ah_bank6Temp == NULL) { + ah->iniBank6.ia_rows), GFP_KERNEL); + if (ah->bank6Temp == NULL) { DPRINTF(ah->ah_sc, ATH_DBG_FATAL, - "Cannot allocate ah_bank6Temp\n"); + "Cannot allocate bank6Temp\n"); *status = -ENOMEM; return false; } @@ -368,19 +368,19 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) { int i, regWrites = 0; u32 bank6SelMask; - u32 *bank6Temp = ah->ah_bank6Temp; + u32 *bank6Temp = ah->bank6Temp; - switch (ah->ah_diversityControl) { + switch (ah->diversity_control) { case ATH9K_ANT_FIXED_A: bank6SelMask = (ah-> - ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : + antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_0 : REDUCE_CHAIN_1; break; case ATH9K_ANT_FIXED_B: bank6SelMask = (ah-> - ah_antennaSwitchSwap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : + antenna_switch_swap & ANTSWAP_AB) ? REDUCE_CHAIN_1 : REDUCE_CHAIN_0; break; case ATH9K_ANT_VARIABLE: @@ -391,8 +391,8 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) break; } - for (i = 0; i < ah->ah_iniBank6.ia_rows; i++) - bank6Temp[i] = ah->ah_analogBank6Data[i]; + for (i = 0; i < ah->iniBank6.ia_rows; i++) + bank6Temp[i] = ah->analogBank6Data[i]; REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); @@ -406,7 +406,7 @@ ath9k_hw_decrease_chain_power(struct ath_hw *ah, struct ath9k_channel *chan) ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 246, 0); ath9k_phy_modify_rx_buffer(bank6Temp, 1, 1, 247, 0); - REG_WRITE_RF_ARRAY(&ah->ah_iniBank6, bank6Temp, regWrites); + REG_WRITE_RF_ARRAY(&ah->iniBank6, bank6Temp, regWrites); REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); #ifdef ALTER_SWITCH diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h index 71a7f5af7004..837a598a7ae5 100644 --- a/drivers/net/wireless/ath9k/phy.h +++ b/drivers/net/wireless/ath9k/phy.h @@ -533,7 +533,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, #define ATH9K_KEY_XOR 0xaa #define ATH9K_IS_MIC_ENABLED(ah) \ - ((ah)->ah_staId1Defaults & AR_STA_ID1_CRPT_MIC_ENABLE) + ((ah)->sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE) #define ANTSWAP_AB 0x0001 #define REDUCE_CHAIN_0 0x00000050 diff --git a/drivers/net/wireless/ath9k/rc.c b/drivers/net/wireless/ath9k/rc.c index 060a7cf6f75a..a4e863191766 100644 --- a/drivers/net/wireless/ath9k/rc.c +++ b/drivers/net/wireless/ath9k/rc.c @@ -1394,13 +1394,13 @@ static void ath_rc_init(struct ath_softc *sc, u8 i, j, k, hi = 0, hthi = 0; /* FIXME: Adhoc */ - if ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) || - (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)) { + if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) || + (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)) { bool is_cw_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40; rate_table = ath_choose_rate_table(sc, sband->band, sta->ht_cap.ht_supported, is_cw_40); - } else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { + } else if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) { /* cur_rate_table would be set on init through config() */ rate_table = sc->cur_rate_table; } @@ -1412,7 +1412,7 @@ static void ath_rc_init(struct ath_softc *sc, if (sta->ht_cap.ht_supported) { ath_rc_priv->ht_cap = WLAN_RC_HT_FLAG; - if (sc->sc_ah->ah_caps.tx_chainmask != 1) + if (sc->sc_ah->caps.tx_chainmask != 1) ath_rc_priv->ht_cap |= WLAN_RC_DS_FLAG; if (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) ath_rc_priv->ht_cap |= WLAN_RC_40_FLAG; @@ -1519,7 +1519,7 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband, */ if (tx_info_priv->tx.ts_flags & (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN) && - ((sc->sc_ah->ah_txTrigLevel) >= ath_rc_priv->tx_triglevel_max)) { + ((sc->sc_ah->tx_trig_level) >= ath_rc_priv->tx_triglevel_max)) { tx_status = 1; is_underrun = 1; } @@ -1628,7 +1628,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp } rate_priv->rssi_down_time = jiffies_to_msecs(jiffies); - rate_priv->tx_triglevel_max = sc->sc_ah->ah_caps.tx_triglevel_max; + rate_priv->tx_triglevel_max = sc->sc_ah->caps.tx_triglevel_max; return rate_priv; } diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c index 7c011b1ba333..08f676af894f 100644 --- a/drivers/net/wireless/ath9k/recv.c +++ b/drivers/net/wireless/ath9k/recv.c @@ -135,7 +135,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, * discard the frame. Enable this if you want to see * error frames in Monitor mode. */ - if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_MONITOR) + if (sc->sc_ah->opmode != NL80211_IFTYPE_MONITOR) goto rx_next; } else if (ds->ds_rxstat.rs_status != 0) { if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) @@ -161,7 +161,7 @@ static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, * decryption and MIC failures. For monitor mode, * we also ignore the CRC error. */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR) { + if (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR) { if (ds->ds_rxstat.rs_status & ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | ATH9K_RXERR_CRC)) @@ -241,7 +241,7 @@ static void ath_opmode_init(struct ath_softc *sc) ath9k_hw_setrxfilter(ah, rfilt); /* configure bssid mask */ - if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) + if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) ath9k_hw_setbssidmask(sc); /* configure operational mode */ @@ -360,13 +360,13 @@ u32 ath_calcrxfilter(struct ath_softc *sc) | ATH9K_RX_FILTER_MCAST; /* If not a STA, enable processing of Probe Requests */ - if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_STATION) + if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) rfilt |= ATH9K_RX_FILTER_PROBEREQ; /* Can't set HOSTAP into promiscous mode */ - if (((sc->sc_ah->ah_opmode != NL80211_IFTYPE_AP) && + if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) && (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || - (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR)) { + (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) { rfilt |= ATH9K_RX_FILTER_PROM; /* ??? To prevent from sending ACK */ rfilt &= ~ATH9K_RX_FILTER_UCAST; @@ -375,13 +375,13 @@ u32 ath_calcrxfilter(struct ath_softc *sc) if (sc->rx.rxfilter & FIF_CONTROL) rfilt |= ATH9K_RX_FILTER_CONTROL; - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION || - sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) + if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION || + sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) rfilt |= ATH9K_RX_FILTER_BEACON; /* If in HOSTAP mode, want to enable reception of PSPOLL frames & beacon frames */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) + if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL); return rfilt; diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c index 3fff3344b2ee..3f70b1e58ae4 100644 --- a/drivers/net/wireless/ath9k/xmit.c +++ b/drivers/net/wireless/ath9k/xmit.c @@ -308,7 +308,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, * when perform internal reset in this routine. * Only enable reset in STA mode for now. */ - if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) + if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) needreset = 1; } } @@ -1072,7 +1072,7 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); spin_lock_bh(&sc->sc_resetlock); - r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, true); + r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); if (r) DPRINTF(sc, ATH_DBG_FATAL, "Unable to reset hardware; reset status %u\n", @@ -1477,7 +1477,7 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) } /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ - if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->ah_caps.rts_aggr_limit)) + if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) flags &= ~(ATH9K_TXDESC_RTSENA); for (i = 0; i < 4; i++) { -- cgit v1.2.3 From e421c7b35c17752dbe6d26d910eb2d6814073355 Mon Sep 17 00:00:00 2001 From: Sujith Date: Thu, 12 Feb 2009 10:06:36 +0530 Subject: ath9k: Store the correct max TX power level This patch fixes a bug where the max power level was being calculated incorrectly. Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/eeprom.c | 15 +++++++++++++++ drivers/net/wireless/ath9k/eeprom.h | 3 +++ 2 files changed, 18 insertions(+) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index b55e9920a5d4..34e9d818fadd 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -2615,6 +2615,21 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, else ah->regulatory.max_power_level = ratesArray[i]; + switch(ar5416_get_ntxchains(ah->txchainmask)) { + case 1: + break; + case 2: + ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN; + break; + case 3: + ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; + break; + default: + DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, + "Invalid chainmask configuration\n"); + break; + } + return 0; } diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 99863b570441..b7c656c84ba3 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -75,6 +75,9 @@ #define SUB_NUM_CTL_MODES_AT_5G_40 2 #define SUB_NUM_CTL_MODES_AT_2G_40 3 +#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ +#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ + #define AR_EEPROM_MAC(i) (0x1d+(i)) #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) -- cgit v1.2.3 From fec0de1110e58ed39647e484bff8437e4185158d Mon Sep 17 00:00:00 2001 From: Sujith Date: Thu, 12 Feb 2009 10:06:43 +0530 Subject: ath9k: Fix rd_ext EEPROM capability for AR9285 AR9285 chipsets have a different EEPROM layout, handle this appropriately when populating the rd_ext capability. Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/eeprom.h | 12 ++++++++++++ drivers/net/wireless/ath9k/hw.c | 3 ++- 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index b7c656c84ba3..5c0d6c339fe9 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -78,6 +78,18 @@ #define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ #define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ +/* + * For AR9285 and later chipsets, the following bits are not being programmed + * in EEPROM and so need to be enabled always. + * + * Bit 0: en_fcc_mid + * Bit 1: en_jap_mid + * Bit 2: en_fcc_dfs_ht40 + * Bit 3: en_jap_ht40 + * Bit 4: en_jap_dfs_ht40 + */ +#define AR9285_RDEXT_DEFAULT 0x1F + #define AR_EEPROM_MAC(i) (0x1d+(i)) #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index cad8e39c201e..55d5a7440942 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -3128,10 +3128,11 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) u16 capField = 0, eeval; eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); - ah->regulatory.current_rd = eeval; eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); + if (AR_SREV_9285_10_OR_LATER(ah)) + eeval |= AR9285_RDEXT_DEFAULT; ah->regulatory.current_rd_ext = eeval; capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); -- cgit v1.2.3 From 06d0f0663e11cab4ec5f2c143a118d71a12fbbe9 Mon Sep 17 00:00:00 2001 From: Sujith Date: Thu, 12 Feb 2009 10:06:45 +0530 Subject: ath9k: Enable Fractional N mode This patch enables Fractional N mode for all channel if the EEPROM says so, and also fixes the INI only when the device is not a 2 GHz only capable device. Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/eeprom.c | 7 +++++++ drivers/net/wireless/ath9k/eeprom.h | 6 +++++- drivers/net/wireless/ath9k/hw.c | 18 ++++++++++-------- drivers/net/wireless/ath9k/phy.c | 19 +++++++++++++------ 4 files changed, 35 insertions(+), 15 deletions(-) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index 34e9d818fadd..68de89d7986f 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -466,6 +466,8 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, return pBase->txMask; case EEP_RX_MASK: return pBase->rxMask; + case EEP_FRAC_N_5G: + return 0; default: return 0; } @@ -1599,6 +1601,11 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, return pBase->dacHiPwrMode_5G; else return 0; + case EEP_FRAC_N_5G: + if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22) + return pBase->frac_n_5g; + else + return 0; default: return 0; } diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 5c0d6c339fe9..60cb23de97c6 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -125,6 +125,7 @@ #define AR5416_EEP_MINOR_VER_17 0x11 #define AR5416_EEP_MINOR_VER_19 0x13 #define AR5416_EEP_MINOR_VER_20 0x14 +#define AR5416_EEP_MINOR_VER_22 0x16 #define AR5416_NUM_5G_CAL_PIERS 8 #define AR5416_NUM_2G_CAL_PIERS 4 @@ -188,6 +189,7 @@ enum eeprom_param { EEP_RXGAIN_TYPE, EEP_TXGAIN_TYPE, EEP_DAC_HPWR_5G, + EEP_FRAC_N_5G }; enum ar5416_rates { @@ -232,7 +234,9 @@ struct base_eep_header { u8 txGainType; u8 rcChainMask; u8 desiredScaleCCK; - u8 futureBase_3[23]; + u8 power_table_offset; + u8 frac_n_5g; + u8 futureBase_3[21]; } __packed; struct base_eep_header_4k { diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 55d5a7440942..6939e4142325 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -823,7 +823,16 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, if (AR_SREV_9280_20(ah)) ath9k_hw_init_txgain_ini(ah); - if (ah->hw_version.devid == AR9280_DEVID_PCI) { + if (!ath9k_hw_fill_cap_info(ah)) { + DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n"); + ecode = -EINVAL; + goto bad; + } + + if ((ah->hw_version.devid == AR9280_DEVID_PCI) && + test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) { + + /* EEPROM Fixup */ for (i = 0; i < ah->iniModes.ia_rows; i++) { u32 reg = INI_RA(&ah->iniModes, i, 0); @@ -838,13 +847,6 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, } } - if (!ath9k_hw_fill_cap_info(ah)) { - DPRINTF(sc, ATH_DBG_RESET, - "failed ath9k_hw_fill_cap_info\n"); - ecode = -EINVAL; - goto bad; - } - ecode = ath9k_hw_init_macaddr(ah); if (ecode != 0) { DPRINTF(sc, ATH_DBG_RESET, diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c index 52aa2a7abe7a..e1494bae0f9f 100644 --- a/drivers/net/wireless/ath9k/phy.c +++ b/drivers/net/wireless/ath9k/phy.c @@ -132,20 +132,27 @@ ath9k_hw_ar9280_set_channel(struct ath_hw *ah, bMode = 0; fracMode = 0; - if ((freq % 20) == 0) { - aModeRefSel = 3; - } else if ((freq % 10) == 0) { - aModeRefSel = 2; - } else { + switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { + case 0: + if ((freq % 20) == 0) { + aModeRefSel = 3; + } else if ((freq % 10) == 0) { + aModeRefSel = 2; + } + if (aModeRefSel) + break; + case 1: + default: aModeRefSel = 0; - fracMode = 1; refDivA = 1; channelSel = (freq * 0x8000) / 15; REG_RMW_FIELD(ah, AR_AN_SYNTH9, AR_AN_SYNTH9_REFDIVA, refDivA); + } + if (!fracMode) { ndiv = (freq * (refDivA >> aModeRefSel)) / 60; channelSel = ndiv & 0x1ff; -- cgit v1.2.3 From 8bd1d07f9345750bd4d767e6c1600919672f98ba Mon Sep 17 00:00:00 2001 From: Senthil Balasubramanian Date: Thu, 12 Feb 2009 13:57:03 +0530 Subject: ath9k: Add open loop control support This patch adds Open Loop Control support for Atheros chipsets that supports open loop power control. Signed-off-by: Senthil Balasubramanian Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/calib.c | 31 ++++++ drivers/net/wireless/ath9k/eeprom.c | 210 ++++++++++++++++++++++++++++++------ drivers/net/wireless/ath9k/eeprom.h | 13 ++- drivers/net/wireless/ath9k/hw.c | 26 ++++- drivers/net/wireless/ath9k/hw.h | 7 +- drivers/net/wireless/ath9k/phy.h | 25 +++++ drivers/net/wireless/ath9k/rc.c | 4 +- 7 files changed, 277 insertions(+), 39 deletions(-) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c index a7ce8c5d48f5..e5abe6564ca7 100644 --- a/drivers/net/wireless/ath9k/calib.c +++ b/drivers/net/wireless/ath9k/calib.c @@ -718,10 +718,39 @@ s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan) return nf; } +static void ath9k_olc_temp_compensation(struct ath_hw *ah) +{ + u32 rddata, i; + int delta, currPDADC, regval; + + rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); + + currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); + + if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G)) + delta = (currPDADC - ah->initPDADC + 4) / 8; + else + delta = (currPDADC - ah->initPDADC + 5) / 10; + + if (delta != ah->PDADCdelta) { + ah->PDADCdelta = delta; + for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) { + regval = ah->originalGain[i] - delta; + if (regval < 0) + regval = 0; + + REG_RMW_FIELD(ah, AR_PHY_TX_GAIN_TBL1 + i * 4, + AR_PHY_TX_GAIN, regval); + } + } +} + bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, bool longcal, bool *isCalDone) { +#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ + ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) struct hal_cal_list *currCal = ah->cal_list_curr; *isCalDone = true; @@ -742,6 +771,8 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, } if (longcal) { + if (OLC_FOR_AR9280_20_LATER) + ath9k_olc_temp_compensation(ah); ath9k_hw_getnf(ah, chan); ath9k_hw_loadnf(ah, ah->curchan); ath9k_hw_start_nfcal(ah); diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index b6f9c31ddfcf..fff7a1b6fbf2 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -179,6 +179,69 @@ static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, } } +static void ath9k_get_txgain_index(struct ath_hw *ah, + struct ath9k_channel *chan, + struct calDataPerFreqOpLoop *rawDatasetOpLoop, + u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx) +{ + u8 pcdac, i = 0; + u16 idxL = 0, idxR = 0, numPiers; + bool match; + struct chan_centers centers; + + ath9k_hw_get_channel_centers(ah, chan, ¢ers); + + for (numPiers = 0; numPiers < availPiers; numPiers++) + if (calChans[numPiers] == AR5416_BCHAN_UNUSED) + break; + + match = ath9k_hw_get_lower_upper_index( + (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)), + calChans, numPiers, &idxL, &idxR); + if (match) { + pcdac = rawDatasetOpLoop[idxL].pcdac[0][0]; + *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0]; + } else { + pcdac = rawDatasetOpLoop[idxR].pcdac[0][0]; + *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] + + rawDatasetOpLoop[idxR].pwrPdg[0][0])/2; + } + + while (pcdac > ah->originalGain[i] && + i < (AR9280_TX_GAIN_TABLE_SIZE - 1)) + i++; + + *pcdacIdx = i; + return; +} + +static void ath9k_olc_get_pdadcs(struct ath_hw *ah, + u32 initTxGain, + int txPower, + u8 *pPDADCValues) +{ + u32 i; + u32 offset; + + REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0, + AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); + REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1, + AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3); + + REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7, + AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain); + + offset = txPower; + for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++) + if (i < offset) + pPDADCValues[i] = 0x0; + else + pPDADCValues[i] = 0xFF; +} + + + + static void ath9k_hw_get_target_powers(struct ath_hw *ah, struct ath9k_channel *chan, struct cal_target_power_ht *powInfo, @@ -1596,6 +1659,16 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, return pBase->rxGainType; case EEP_TXGAIN_TYPE: return pBase->txGainType; + case EEP_OL_PWRCTRL: + if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19) + return pBase->openLoopPwrCntl ? true : false; + else + return false; + case EEP_RC_CHAIN_MASK: + if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19) + return pBase->rcChainMask; + else + return 0; case EEP_DAC_HPWR_5G: if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) return pBase->dacHiPwrMode_5G; @@ -1839,8 +1912,15 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, pModal->swSettleHt40); } + if (AR_SREV_9280_20_OR_LATER(ah) && + AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19) + REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, + AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK, + pModal->miscBits); + + if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) { - if (IS_CHAN_HT20(chan)) + if (IS_CHAN_2GHZ(chan)) REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, eep->baseEepHeader.dacLpMode); else if (eep->baseEepHeader.dacHiPwrMode_5G) @@ -1851,6 +1931,10 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, pModal->miscBits >> 2); + + REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, + AR_PHY_TX_DESIRED_SCALE_CCK, + eep->baseEepHeader.desiredScaleCCK); } return true; @@ -2080,6 +2164,12 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) { +#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ + ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) +#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x) +#define SM_PDGAIN_B(x, y) \ + SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y) + struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; struct cal_data_per_freq *pRawDataset; u8 *pCalBChans = NULL; @@ -2113,6 +2203,12 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, numPiers = AR5416_NUM_5G_CAL_PIERS; } + if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) { + pRawDataset = pEepData->calPierData2G[0]; + ah->initPDADC = ((struct calDataPerFreqOpLoop *) + pRawDataset)->vpdPdg[0][0]; + } + numXpdGain = 0; for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { @@ -2148,25 +2244,45 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, else pRawDataset = pEepData->calPierData5G[i]; - ath9k_hw_get_def_gain_boundaries_pdadcs(ah, chan, - pRawDataset, pCalBChans, - numPiers, pdGainOverlap_t2, - &tMinCalPower, gainBoundaries, - pdadcValues, numXpdGain); + + if (OLC_FOR_AR9280_20_LATER) { + u8 pcdacIdx; + u8 txPower; + + ath9k_get_txgain_index(ah, chan, + (struct calDataPerFreqOpLoop *)pRawDataset, + pCalBChans, numPiers, &txPower, &pcdacIdx); + ath9k_olc_get_pdadcs(ah, pcdacIdx, + txPower/2, pdadcValues); + } else { + ath9k_hw_get_def_gain_boundaries_pdadcs(ah, + chan, pRawDataset, + pCalBChans, numPiers, + pdGainOverlap_t2, + &tMinCalPower, + gainBoundaries, + pdadcValues, + numXpdGain); + } if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { - REG_WRITE(ah, - AR_PHY_TPCRG5 + regChainOffset, - SM(pdGainOverlap_t2, - AR_PHY_TPCRG5_PD_GAIN_OVERLAP) - | SM(gainBoundaries[0], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) - | SM(gainBoundaries[1], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) - | SM(gainBoundaries[2], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) - | SM(gainBoundaries[3], - AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); + if (OLC_FOR_AR9280_20_LATER) { + REG_WRITE(ah, + AR_PHY_TPCRG5 + regChainOffset, + SM(0x6, + AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | + SM_PD_GAIN(1) | SM_PD_GAIN(2) | + SM_PD_GAIN(3) | SM_PD_GAIN(4)); + } else { + REG_WRITE(ah, + AR_PHY_TPCRG5 + regChainOffset, + SM(pdGainOverlap_t2, + AR_PHY_TPCRG5_PD_GAIN_OVERLAP)| + SM_PDGAIN_B(0, 1) | + SM_PDGAIN_B(1, 2) | + SM_PDGAIN_B(2, 3) | + SM_PDGAIN_B(3, 4)); + } } regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; @@ -2200,6 +2316,8 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, *pTxPowerIndexOffset = 0; return true; +#undef SM_PD_GAIN +#undef SM_PDGAIN_B } static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, @@ -2500,13 +2618,14 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, u8 twiceMaxRegulatoryPower, u8 powerLimit) { +#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta) struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; struct modal_eep_header *pModal = &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); int16_t ratesArray[Ar5416RateSize]; int16_t txPowerIndexOffset = 0; u8 ht40PowerIncForPdadc = 2; - int i; + int i, cck_ofdm_delta = 0; memset(ratesArray, 0, sizeof(ratesArray)); @@ -2555,16 +2674,30 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, | ATH9K_POW_SM(ratesArray[rate24mb], 0)); if (IS_CHAN_2GHZ(chan)) { - REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, - ATH9K_POW_SM(ratesArray[rate2s], 24) - | ATH9K_POW_SM(ratesArray[rate2l], 16) - | ATH9K_POW_SM(ratesArray[rateXr], 8) - | ATH9K_POW_SM(ratesArray[rate1l], 0)); - REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, - ATH9K_POW_SM(ratesArray[rate11s], 24) - | ATH9K_POW_SM(ratesArray[rate11l], 16) - | ATH9K_POW_SM(ratesArray[rate5_5s], 8) - | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); + if (OLC_FOR_AR9280_20_LATER) { + cck_ofdm_delta = 2; + REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, + ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24) + | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16) + | ATH9K_POW_SM(ratesArray[rateXr], 8) + | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, + ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24) + | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16) + | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8) + | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0)); + } else { + REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, + ATH9K_POW_SM(ratesArray[rate2s], 24) + | ATH9K_POW_SM(ratesArray[rate2l], 16) + | ATH9K_POW_SM(ratesArray[rateXr], 8) + | ATH9K_POW_SM(ratesArray[rate1l], 0)); + REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, + ATH9K_POW_SM(ratesArray[rate11s], 24) + | ATH9K_POW_SM(ratesArray[rate11l], 16) + | ATH9K_POW_SM(ratesArray[rate5_5s], 8) + | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); + } } REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, @@ -2597,12 +2730,19 @@ static int ath9k_hw_def_set_txpower(struct ath_hw *ah, ht40PowerIncForPdadc, 8) | ATH9K_POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0)); - - REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, - ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) - | ATH9K_POW_SM(ratesArray[rateExtCck], 16) - | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) - | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); + if (OLC_FOR_AR9280_20_LATER) { + REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, + ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) + | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16) + | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) + | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0)); + } else { + REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, + ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) + | ATH9K_POW_SM(ratesArray[rateExtCck], 16) + | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) + | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); + } } REG_WRITE(ah, AR_PHY_POWER_TX_SUB, diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 60cb23de97c6..2cfea5d56d10 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -168,6 +168,8 @@ #define AR5416_EEP4K_PD_GAIN_ICEPTS 5 #define AR5416_EEP4K_MAX_CHAINS 1 +#define AR9280_TX_GAIN_TABLE_SIZE 22 + enum eeprom_param { EEP_NFTHRESH_5, EEP_NFTHRESH_2, @@ -188,6 +190,8 @@ enum eeprom_param { EEP_RX_MASK, EEP_RXGAIN_TYPE, EEP_TXGAIN_TYPE, + EEP_OL_PWRCTRL, + EEP_RC_CHAIN_MASK, EEP_DAC_HPWR_5G, EEP_FRAC_N_5G }; @@ -229,7 +233,7 @@ struct base_eep_header { u8 futureBase_1[2]; u8 rxGainType; u8 dacHiPwrMode_5G; - u8 futureBase_2; + u8 openLoopPwrCntl; u8 dacLpMode; u8 txGainType; u8 rcChainMask; @@ -310,6 +314,13 @@ struct modal_eep_header { struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; } __packed; +struct calDataPerFreqOpLoop { + u8 pwrPdg[2][5]; + u8 vpdPdg[2][5]; + u8 pcdac[2][5]; + u8 empty[2][5]; +} __packed; + struct modal_eep_4k_header { u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; u32 antCtrlCommon; diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 4af1aac16785..e33c53fb6b7e 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -1202,10 +1202,23 @@ static u32 ath9k_hw_ini_fixup(struct ath_hw *ah, return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value); } +static void ath9k_olc_init(struct ath_hw *ah) +{ + u32 i; + + for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) + ah->originalGain[i] = + MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), + AR_PHY_TX_GAIN); + ah->PDADCdelta = 0; +} + static int ath9k_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan, enum ath9k_ht_macmode macmode) { +#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ + ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) int i, regWrites = 0; struct ieee80211_channel *channel = chan->chan; u32 modesIndex, freqIndex; @@ -1308,6 +1321,9 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, ath9k_hw_set_regs(ah, chan, macmode); ath9k_hw_init_chain_masks(ah); + if (OLC_FOR_AR9280_20_LATER) + ath9k_olc_init(ah); + status = ah->eep_ops->set_txpower(ah, chan, ath9k_regd_get_ctl(ah, chan), channel->max_antenna_gain * 2, @@ -1515,6 +1531,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) AR_RTC_FORCE_WAKE_ON_INT); REG_WRITE(ah, AR_RTC_RESET, 0); + udelay(2); REG_WRITE(ah, AR_RTC_RESET, 1); if (!ath9k_hw_wait(ah, @@ -1582,7 +1599,10 @@ static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan, static bool ath9k_hw_chip_reset(struct ath_hw *ah, struct ath9k_channel *chan) { - if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) + if (OLC_FOR_AR9280_20_LATER) { + if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) + return false; + } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) return false; if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) @@ -3404,6 +3424,10 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, return 0; } return false; + case ATH9K_CAP_DS: + return (AR_SREV_9280_20_OR_LATER(ah) && + (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) + ? false : true; default: return false; } diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index 587a78db748d..08469d9525bc 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -162,7 +162,8 @@ enum ath9k_capability_type { ATH9K_CAP_WME_TKIPMIC, ATH9K_CAP_RFSILENT, ATH9K_CAP_ANT_CFG_2GHZ, - ATH9K_CAP_ANT_CFG_5GHZ + ATH9K_CAP_ANT_CFG_5GHZ, + ATH9K_CAP_DS }; struct ath9k_hw_capabilities { @@ -551,6 +552,10 @@ struct ath_hw { u8 txchainmask; u8 rxchainmask; + u32 originalGain[22]; + int initPDADC; + int PDADCdelta; + struct ar5416IniArray iniModes; struct ar5416IniArray iniCommon; struct ar5416IniArray iniBank0; diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h index 4758c37e4b88..3dbdd54be4e9 100644 --- a/drivers/net/wireless/ath9k/phy.h +++ b/drivers/net/wireless/ath9k/phy.h @@ -387,6 +387,8 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, #define AR_PHY_CCK_TX_CTRL 0xA204 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 +#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C +#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 #define AR_PHY_CCK_DETECT 0xA208 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F @@ -444,6 +446,29 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20 +#define AR_PHY_TX_PWRCTRL4 0xa264 +#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001 +#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0 +#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE +#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1 + +#define AR_PHY_TX_PWRCTRL6_0 0xa270 +#define AR_PHY_TX_PWRCTRL6_1 0xb270 +#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000 +#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24 + +#define AR_PHY_TX_PWRCTRL7 0xa274 +#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000 +#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19 + +#define AR_PHY_TX_PWRCTRL9 0xa27C +#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 +#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 + +#define AR_PHY_TX_GAIN_TBL1 0xa300 +#define AR_PHY_TX_GAIN 0x0007F000 +#define AR_PHY_TX_GAIN_S 12 + #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 #define AR_PHY_MASK2_M_31_45 0xa3a4 #define AR_PHY_MASK2_M_16_30 0xa3a8 diff --git a/drivers/net/wireless/ath9k/rc.c b/drivers/net/wireless/ath9k/rc.c index a4e863191766..6b4731c24736 100644 --- a/drivers/net/wireless/ath9k/rc.c +++ b/drivers/net/wireless/ath9k/rc.c @@ -1392,6 +1392,7 @@ static void ath_rc_init(struct ath_softc *sc, struct ath_rateset *rateset = &ath_rc_priv->neg_rates; u8 *ht_mcs = (u8 *)&ath_rc_priv->neg_ht_rates; u8 i, j, k, hi = 0, hthi = 0; + struct ath_hw *ah = sc->sc_ah; /* FIXME: Adhoc */ if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) || @@ -1412,7 +1413,8 @@ static void ath_rc_init(struct ath_softc *sc, if (sta->ht_cap.ht_supported) { ath_rc_priv->ht_cap = WLAN_RC_HT_FLAG; - if (sc->sc_ah->caps.tx_chainmask != 1) + if (sc->sc_ah->caps.tx_chainmask != 1 && + ath9k_hw_getcapability(ah, ATH9K_CAP_DS, 0, NULL)) ath_rc_priv->ht_cap |= WLAN_RC_DS_FLAG; if (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40) ath_rc_priv->ht_cap |= WLAN_RC_40_FLAG; -- cgit v1.2.3 From d9ae96d94a9117fa8d80dd4881f5835f9112c449 Mon Sep 17 00:00:00 2001 From: Sujith Date: Fri, 20 Feb 2009 15:13:13 +0530 Subject: ath9k: Remove multiple macro occurrences OLC_FOR_AR9280_20_LATER is defined in multiple places, move it to a common location. Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/calib.c | 2 -- drivers/net/wireless/ath9k/eeprom.c | 2 -- drivers/net/wireless/ath9k/eeprom.h | 3 +++ drivers/net/wireless/ath9k/hw.c | 2 -- 4 files changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c index 93c6e1f72353..1c074c059b5c 100644 --- a/drivers/net/wireless/ath9k/calib.c +++ b/drivers/net/wireless/ath9k/calib.c @@ -749,8 +749,6 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, u8 rxchainmask, bool longcal, bool *isCalDone) { -#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ - ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) struct hal_cal_list *currCal = ah->cal_list_curr; *isCalDone = true; diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index fff7a1b6fbf2..02d0b919ee3d 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -2164,8 +2164,6 @@ static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *pTxPowerIndexOffset) { -#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ - ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x) #define SM_PDGAIN_B(x, y) \ SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y) diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 2cfea5d56d10..6296e3eff10b 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -95,6 +95,9 @@ #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) +#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ + ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) + #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 #define AR_EEPROM_RFSILENT_POLARITY 0x0002 diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 2c0173a3cce0..6f2e92ec77ae 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -1219,8 +1219,6 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, struct ath9k_channel *chan, enum ath9k_ht_macmode macmode) { -#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ - ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) int i, regWrites = 0; struct ieee80211_channel *channel = chan->chan; u32 modesIndex, freqIndex; -- cgit v1.2.3 From 4e845168380a5954dd8702be5229e3e1b477ed81 Mon Sep 17 00:00:00 2001 From: Senthil Balasubramanian Date: Fri, 6 Mar 2009 11:24:10 +0530 Subject: ath9k: INI update for AR9285 and periodic PA offset caliberation This patch updates the initvalues for AR9285 chipset and also adds periodic PA offset caliberation. Signed-off-by: Senthil Balasubramanian Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/calib.c | 145 ++++++++++++++++++++++------------ drivers/net/wireless/ath9k/eeprom.h | 2 +- drivers/net/wireless/ath9k/hw.c | 20 ++++- drivers/net/wireless/ath9k/initvals.h | 107 +++++++++++++++++-------- drivers/net/wireless/ath9k/phy.h | 4 + 5 files changed, 195 insertions(+), 83 deletions(-) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c index 1c074c059b5c..a652e9bb16de 100644 --- a/drivers/net/wireless/ath9k/calib.c +++ b/drivers/net/wireless/ath9k/calib.c @@ -745,43 +745,6 @@ static void ath9k_olc_temp_compensation(struct ath_hw *ah) } } -bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, - u8 rxchainmask, bool longcal, - bool *isCalDone) -{ - struct hal_cal_list *currCal = ah->cal_list_curr; - - *isCalDone = true; - - if (currCal && - (currCal->calState == CAL_RUNNING || - currCal->calState == CAL_WAITING)) { - ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, - isCalDone); - if (*isCalDone) { - ah->cal_list_curr = currCal = currCal->calNext; - - if (currCal->calState == CAL_WAITING) { - *isCalDone = false; - ath9k_hw_reset_calibration(ah, currCal); - } - } - } - - if (longcal) { - if (OLC_FOR_AR9280_20_LATER) - ath9k_olc_temp_compensation(ah); - ath9k_hw_getnf(ah, chan); - ath9k_hw_loadnf(ah, ah->curchan); - ath9k_hw_start_nfcal(ah); - - if (chan->channelFlags & CHANNEL_CW_INT) - chan->channelFlags &= ~CHANNEL_CW_INT; - } - - return true; -} - static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah) { @@ -877,22 +840,104 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah) } +bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, + u8 rxchainmask, bool longcal, + bool *isCalDone) +{ + struct hal_cal_list *currCal = ah->cal_list_curr; + + *isCalDone = true; + + if (currCal && + (currCal->calState == CAL_RUNNING || + currCal->calState == CAL_WAITING)) { + ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, + isCalDone); + if (*isCalDone) { + ah->cal_list_curr = currCal = currCal->calNext; + + if (currCal->calState == CAL_WAITING) { + *isCalDone = false; + ath9k_hw_reset_calibration(ah, currCal); + } + } + } + + if (longcal) { + if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah)) + ath9k_hw_9285_pa_cal(ah); + + if (OLC_FOR_AR9280_20_LATER) + ath9k_olc_temp_compensation(ah); + ath9k_hw_getnf(ah, chan); + ath9k_hw_loadnf(ah, ah->curchan); + ath9k_hw_start_nfcal(ah); + + if (chan->channelFlags & CHANNEL_CW_INT) + chan->channelFlags &= ~CHANNEL_CW_INT; + } + + return true; +} + +bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) +{ + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); + if (chan->channelFlags & CHANNEL_HT20) { + REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); + REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, + AR_PHY_AGC_CONTROL_FLTR_CAL); + REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, + AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { + DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset " + "calibration failed to complete in " + "1ms; noisy ??\n"); + return false; + } + REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); + } + REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); + REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); + if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, + 0, AH_WAIT_TIMEOUT)) { + DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration " + "failed to complete in 1ms; noisy ??\n"); + return false; + } + + REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); + REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); + REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); + + return true; +} + bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) { - if (AR_SREV_9280_10_OR_LATER(ah)) { + if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) { + if (!ar9285_clc(ah, chan)) + return false; + } else if (AR_SREV_9280_10_OR_LATER(ah)) { REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); /* Kick off the cal */ REG_WRITE(ah, AR_PHY_AGC_CONTROL, - REG_READ(ah, AR_PHY_AGC_CONTROL) | - AR_PHY_AGC_CONTROL_CAL); + REG_READ(ah, AR_PHY_AGC_CONTROL) | + AR_PHY_AGC_CONTROL_CAL); if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, - AR_PHY_AGC_CONTROL_CAL, 0, - AH_WAIT_TIMEOUT)) { + AR_PHY_AGC_CONTROL_CAL, 0, + AH_WAIT_TIMEOUT)) { DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration failed to complete in 1ms; " "noisy environment?\n"); @@ -906,11 +951,11 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, /* Calibrate the AGC */ REG_WRITE(ah, AR_PHY_AGC_CONTROL, - REG_READ(ah, AR_PHY_AGC_CONTROL) | - AR_PHY_AGC_CONTROL_CAL); + REG_READ(ah, AR_PHY_AGC_CONTROL) | + AR_PHY_AGC_CONTROL_CAL); if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, - 0, AH_WAIT_TIMEOUT)) { + 0, AH_WAIT_TIMEOUT)) { DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration failed to complete in 1ms; " "noisy environment?\n"); @@ -928,8 +973,8 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, /* Do NF Calibration */ REG_WRITE(ah, AR_PHY_AGC_CONTROL, - REG_READ(ah, AR_PHY_AGC_CONTROL) | - AR_PHY_AGC_CONTROL_NF); + REG_READ(ah, AR_PHY_AGC_CONTROL) | + AR_PHY_AGC_CONTROL_NF); ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; @@ -938,19 +983,19 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, INIT_CAL(&ah->adcgain_caldata); INSERT_CAL(ah, &ah->adcgain_caldata); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, - "enabling ADC Gain Calibration.\n"); + "enabling ADC Gain Calibration.\n"); } if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { INIT_CAL(&ah->adcdc_caldata); INSERT_CAL(ah, &ah->adcdc_caldata); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, - "enabling ADC DC Calibration.\n"); + "enabling ADC DC Calibration.\n"); } if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { INIT_CAL(&ah->iq_caldata); INSERT_CAL(ah, &ah->iq_caldata); DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, - "enabling IQ Calibration.\n"); + "enabling IQ Calibration.\n"); } ah->cal_list_curr = ah->cal_list; diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 6296e3eff10b..d6f6108f63c7 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -261,7 +261,7 @@ struct base_eep_header_4k { u16 deviceCap; u32 binBuildNumber; u8 deviceType; - u8 futureBase[1]; + u8 txGainType; } __packed; diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index eb750a503999..cdc9d15e8419 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -678,6 +678,7 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, ah->hw_version.macVersion, ah->hw_version.macRev); if (AR_SREV_9285_12_OR_LATER(ah)) { + INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, ARRAY_SIZE(ar9285Modes_9285_1_2), 6); INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, @@ -817,6 +818,22 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, if (ecode != 0) goto bad; + if (AR_SREV_9285_12_OR_LATER(ah)) { + u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); + + /* txgain table */ + if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { + INIT_INI_ARRAY(&ah->iniModesTxGain, + ar9285Modes_high_power_tx_gain_9285_1_2, + ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6); + } else { + INIT_INI_ARRAY(&ah->iniModesTxGain, + ar9285Modes_original_tx_gain_9285_1_2, + ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6); + } + + } + /* rxgain table */ if (AR_SREV_9280_20(ah)) ath9k_hw_init_rxgain_ini(ah); @@ -1293,7 +1310,8 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, if (AR_SREV_9280(ah)) REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites); - if (AR_SREV_9280(ah)) + if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) && + AR_SREV_9285_12_OR_LATER(ah))) REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); for (i = 0; i < ah->iniCommon.ia_rows; i++) { diff --git a/drivers/net/wireless/ath9k/initvals.h b/drivers/net/wireless/ath9k/initvals.h index d49236368a1c..c32bc3b00d95 100644 --- a/drivers/net/wireless/ath9k/initvals.h +++ b/drivers/net/wireless/ath9k/initvals.h @@ -4121,6 +4121,7 @@ static const u_int32_t ar9285PciePhy_clkreq_off_L1_9285[][2] = { {0x00004044, 0x00000000 }, }; +/* AR9285 v1_2 PCI Register Writes. Created: 03/04/09 */ static const u_int32_t ar9285Modes_9285_1_2[][6] = { { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, @@ -4155,7 +4156,7 @@ static const u_int32_t ar9285Modes_9285_1_2[][6] = { { 0x000099bc, 0x00000600, 0x00000600, 0x00000c00, 0x00000c00, 0x00000c00 }, { 0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4 }, { 0x000099c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77 }, - { 0x000099c8, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329, 0x60f65329 }, + { 0x000099c8, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329, 0x6af65329 }, { 0x000099cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8 }, { 0x000099d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, 0x00046384 }, { 0x000099d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, @@ -4421,25 +4422,6 @@ static const u_int32_t ar9285Modes_9285_1_2[][6] = { { 0x0000a21c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a }, { 0x0000a230, 0x00000000, 0x00000000, 0x00000210, 0x00000108, 0x00000000 }, { 0x0000a250, 0x0004f000, 0x0004f000, 0x0004a000, 0x0004a000, 0x0004a000 }, - { 0x0000a274, 0x0a81c652, 0x0a81c652, 0x0a820652, 0x0a820652, 0x0a82a652 }, - { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, - { 0x0000a304, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 }, - { 0x0000a308, 0x00000000, 0x00000000, 0x00010408, 0x00010408, 0x00000000 }, - { 0x0000a30c, 0x00000000, 0x00000000, 0x0001860a, 0x0001860a, 0x00000000 }, - { 0x0000a310, 0x00000000, 0x00000000, 0x00020818, 0x00020818, 0x00000000 }, - { 0x0000a314, 0x00000000, 0x00000000, 0x00024858, 0x00024858, 0x00000000 }, - { 0x0000a318, 0x00000000, 0x00000000, 0x00026859, 0x00026859, 0x00000000 }, - { 0x0000a31c, 0x00000000, 0x00000000, 0x0002985b, 0x0002985b, 0x00000000 }, - { 0x0000a320, 0x00000000, 0x00000000, 0x0002b89a, 0x0002b89a, 0x00000000 }, - { 0x0000a324, 0x00000000, 0x00000000, 0x0002d89b, 0x0002d89b, 0x00000000 }, - { 0x0000a328, 0x00000000, 0x00000000, 0x0002f89c, 0x0002f89c, 0x00000000 }, - { 0x0000a32c, 0x00000000, 0x00000000, 0x0003189d, 0x0003189d, 0x00000000 }, - { 0x0000a330, 0x00000000, 0x00000000, 0x0003389e, 0x0003389e, 0x00000000 }, - { 0x0000a334, 0x00000000, 0x00000000, 0x000368de, 0x000368de, 0x00000000 }, - { 0x0000a338, 0x00000000, 0x00000000, 0x0003891e, 0x0003891e, 0x00000000 }, - { 0x0000a33c, 0x00000000, 0x00000000, 0x0003a95e, 0x0003a95e, 0x00000000 }, - { 0x0000a340, 0x00000000, 0x00000000, 0x0003e9df, 0x0003e9df, 0x00000000 }, - { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, { 0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e }, }; @@ -4569,7 +4551,7 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = { { 0x00008110, 0x00000168 }, { 0x00008118, 0x000100aa }, { 0x0000811c, 0x00003210 }, - { 0x00008120, 0x08f04800 }, + { 0x00008120, 0x08f04810 }, { 0x00008124, 0x00000000 }, { 0x00008128, 0x00000000 }, { 0x0000812c, 0x00000000 }, @@ -4585,7 +4567,7 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = { { 0x00008178, 0x00000100 }, { 0x0000817c, 0x00000000 }, { 0x000081c0, 0x00000000 }, - { 0x000081d0, 0x00003210 }, + { 0x000081d0, 0x0000320a }, { 0x000081ec, 0x00000000 }, { 0x000081f0, 0x00000000 }, { 0x000081f4, 0x00000000 }, @@ -4709,8 +4691,6 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = { { 0x0000a268, 0x00000000 }, { 0x0000a26c, 0x0ebae9e6 }, { 0x0000d270, 0x0d820820 }, - { 0x0000a278, 0x318c6318 }, - { 0x0000a27c, 0x050c0318 }, { 0x0000d35c, 0x07ffffef }, { 0x0000d360, 0x0fffffe7 }, { 0x0000d364, 0x17ffffe5 }, @@ -4725,8 +4705,6 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = { { 0x0000a388, 0x0c000000 }, { 0x0000a38c, 0x20202020 }, { 0x0000a390, 0x20202020 }, - { 0x0000a394, 0x318c6318 }, - { 0x0000a398, 0x00000318 }, { 0x0000a39c, 0x00000001 }, { 0x0000a3a0, 0x00000000 }, { 0x0000a3a4, 0x00000000 }, @@ -4741,8 +4719,6 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = { { 0x0000a3cc, 0x20202020 }, { 0x0000a3d0, 0x20202020 }, { 0x0000a3d4, 0x20202020 }, - { 0x0000a3dc, 0x318c6318 }, - { 0x0000a3e0, 0x00000318 }, { 0x0000a3e4, 0x00000000 }, { 0x0000a3e8, 0x18c43433 }, { 0x0000a3ec, 0x00f70081 }, @@ -4753,13 +4729,11 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = { { 0x00007810, 0x71c0d388 }, { 0x00007814, 0x924934a8 }, { 0x0000781c, 0x00000000 }, - { 0x00007820, 0x00000c04 }, { 0x00007824, 0x00d86fff }, { 0x00007828, 0x26d2491b }, { 0x0000782c, 0x6e36d97b }, { 0x00007830, 0xedb6d96e }, { 0x00007834, 0x71400087 }, - { 0x00007838, 0xfac68801 }, { 0x0000783c, 0x0001fffe }, { 0x00007840, 0xffeb1a20 }, { 0x00007844, 0x000c0db6 }, @@ -4772,10 +4746,81 @@ static const u_int32_t ar9285Common_9285_1_2[][2] = { { 0x00007860, 0x21084210 }, { 0x00007864, 0xf7d7ffde }, { 0x00007868, 0xc2034080 }, - { 0x0000786c, 0x48609eb4 }, { 0x00007870, 0x10142c00 }, }; +static const u_int32_t ar9285Modes_high_power_tx_gain_9285_1_2[][6] = { + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000a304, 0x00000000, 0x00000000, 0x00005200, 0x00005200, 0x00000000 }, + { 0x0000a308, 0x00000000, 0x00000000, 0x00007201, 0x00007201, 0x00000000 }, + { 0x0000a30c, 0x00000000, 0x00000000, 0x0000b240, 0x0000b240, 0x00000000 }, + { 0x0000a310, 0x00000000, 0x00000000, 0x0000d241, 0x0000d241, 0x00000000 }, + { 0x0000a314, 0x00000000, 0x00000000, 0x0000f440, 0x0000f440, 0x00000000 }, + { 0x0000a318, 0x00000000, 0x00000000, 0x00014640, 0x00014640, 0x00000000 }, + { 0x0000a31c, 0x00000000, 0x00000000, 0x00018680, 0x00018680, 0x00000000 }, + { 0x0000a320, 0x00000000, 0x00000000, 0x00019841, 0x00019841, 0x00000000 }, + { 0x0000a324, 0x00000000, 0x00000000, 0x0001ca40, 0x0001ca40, 0x00000000 }, + { 0x0000a328, 0x00000000, 0x00000000, 0x0001fa80, 0x0001fa80, 0x00000000 }, + { 0x0000a32c, 0x00000000, 0x00000000, 0x00023ac0, 0x00023ac0, 0x00000000 }, + { 0x0000a330, 0x00000000, 0x00000000, 0x0002ab40, 0x0002ab40, 0x00000000 }, + { 0x0000a334, 0x00000000, 0x00000000, 0x00033d82, 0x00033d82, 0x00000000 }, + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 }, + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 }, + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x00007838, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803, 0xfac68803 }, + { 0x0000786c, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe, 0x08609ebe }, + { 0x00007820, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00, 0x00000c00 }, + { 0x0000a274, 0x0a22a652, 0x0a22a652, 0x0a21a652, 0x0a21a652, 0x0a22a652 }, + { 0x0000a278, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce }, + { 0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce }, + { 0x0000a394, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce }, + { 0x0000a398, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce }, + { 0x0000a3dc, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce }, + { 0x0000a3e0, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce }, +}; + +static const u_int32_t ar9285Modes_original_tx_gain_9285_1_2[][6] = { + /* Address 5G-HT20 5G-HT40 2G-HT40 2G-HT20 Turbo */ + { 0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000 }, + { 0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000 }, + { 0x0000a30c, 0x00000000, 0x00000000, 0x00019608, 0x00019608, 0x00000000 }, + { 0x0000a310, 0x00000000, 0x00000000, 0x00022618, 0x00022618, 0x00000000 }, + { 0x0000a314, 0x00000000, 0x00000000, 0x0002a6c9, 0x0002a6c9, 0x00000000 }, + { 0x0000a318, 0x00000000, 0x00000000, 0x00031710, 0x00031710, 0x00000000 }, + { 0x0000a31c, 0x00000000, 0x00000000, 0x00035718, 0x00035718, 0x00000000 }, + { 0x0000a320, 0x00000000, 0x00000000, 0x00038758, 0x00038758, 0x00000000 }, + { 0x0000a324, 0x00000000, 0x00000000, 0x0003c75a, 0x0003c75a, 0x00000000 }, + { 0x0000a328, 0x00000000, 0x00000000, 0x0004075c, 0x0004075c, 0x00000000 }, + { 0x0000a32c, 0x00000000, 0x00000000, 0x0004475e, 0x0004475e, 0x00000000 }, + { 0x0000a330, 0x00000000, 0x00000000, 0x0004679f, 0x0004679f, 0x00000000 }, + { 0x0000a334, 0x00000000, 0x00000000, 0x000487df, 0x000487df, 0x00000000 }, + { 0x0000a338, 0x0003891e, 0x0003891e, 0x0003891e, 0x0003891e, 0x00000000 }, + { 0x0000a33c, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x0003a95e, 0x00000000 }, + { 0x0000a340, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x0000a344, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x0000a348, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x0000a34c, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x0000a350, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x0000a354, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x0003e9df, 0x00000000 }, + { 0x00007838, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801, 0xfac68801 }, + { 0x0000786c, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4, 0x48609eb4 }, + { 0x00007820, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04, 0x00000c04 }, + { 0x0000a274, 0x0a21c652, 0x0a21c652, 0x0a21a652, 0x0a21a652, 0x0a22a652 }, + { 0x0000a278, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c }, + { 0x0000a27c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c, 0x050e039c }, + { 0x0000a394, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c }, + { 0x0000a398, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c }, + { 0x0000a3dc, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c, 0x39ce739c }, + { 0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c }, +}; + static const u_int32_t ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = { {0x00004040, 0x9248fd00 }, {0x00004040, 0x24924924 }, diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h index 6222e32c7748..1eac8c707342 100644 --- a/drivers/net/wireless/ath9k/phy.h +++ b/drivers/net/wireless/ath9k/phy.h @@ -446,6 +446,9 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 +#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 + #define AR_PHY_TX_PWRCTRL4 0xa264 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0 @@ -513,6 +516,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, /* Carrier leak calibration control, do it after AGC calibration */ #define AR_PHY_CL_CAL_CTL 0xA358 #define AR_PHY_CL_CAL_ENABLE 0x00000002 +#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 #define AR_PHY_POWER_TX_RATE5 0xA38C #define AR_PHY_POWER_TX_RATE6 0xA390 -- cgit v1.2.3 From 355363fcf7daded4a48308b54d6b86bea4f8bb6d Mon Sep 17 00:00:00 2001 From: Sujith Date: Fri, 13 Mar 2009 08:56:02 +0530 Subject: ath9k: Move AR5416_VER_MASK to a common location Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/eeprom.c | 4 ---- drivers/net/wireless/ath9k/eeprom.h | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index 6c9bc5fdb04a..49dee238c683 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -1588,7 +1588,6 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, enum eeprom_param param) { -#define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK) struct ar5416_eeprom_def *eep = &ah->eeprom.def; struct modal_eep_header *pModal = eep->modalHeader; struct base_eep_header *pBase = &eep->baseEepHeader; @@ -1655,14 +1654,12 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, default: return 0; } -#undef AR5416_VER_MASK } /* XXX: Clean me up, make me more legible */ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { -#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) struct modal_eep_header *pModal; struct ar5416_eeprom_def *eep = &ah->eeprom.def; int i, regChainOffset; @@ -1910,7 +1907,6 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, } return true; -#undef AR5416_VER_MASK } static void ath9k_hw_def_set_addac(struct ath_hw *ah, diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index d6f6108f63c7..0a4b22a554d2 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -95,6 +95,7 @@ #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) +#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) -- cgit v1.2.3 From d6509151bd3e952b7d157ea4dbae23279d427e95 Mon Sep 17 00:00:00 2001 From: Sujith Date: Fri, 13 Mar 2009 08:56:05 +0530 Subject: ath9k: Change return type for set_board_values() We always return true, checking for 'false' return value is bogus anyway, so fix this. Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/eeprom.c | 8 ++------ drivers/net/wireless/ath9k/eeprom.h | 2 +- drivers/net/wireless/ath9k/hw.c | 6 +----- 3 files changed, 4 insertions(+), 12 deletions(-) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index c3bb1968bb5e..973b576c0ad8 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -1232,7 +1232,7 @@ static void ath9k_hw_4k_set_gain(struct ath_hw *ah, REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); } -static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah, +static void ath9k_hw_4k_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { struct modal_eep_4k_header *pModal; @@ -1378,8 +1378,6 @@ static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); } - - return true; } static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah, @@ -1718,7 +1716,7 @@ static void ath9k_hw_def_set_gain(struct ath_hw *ah, } } -static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, +static void ath9k_hw_def_set_board_values(struct ath_hw *ah, struct ath9k_channel *chan) { struct modal_eep_header *pModal; @@ -1884,8 +1882,6 @@ static bool ath9k_hw_def_set_board_values(struct ath_hw *ah, AR_PHY_TX_DESIRED_SCALE_CCK, eep->baseEepHeader.desiredScaleCCK); } - - return true; } static void ath9k_hw_def_set_addac(struct ath_hw *ah, diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 0a4b22a554d2..8e5b880d445d 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -490,7 +490,7 @@ struct eeprom_ops { u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band); u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw, struct ath9k_channel *chan); - bool (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); + void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); int (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, u16 cfgCtl, u8 twiceAntennaReduction, diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 3dd054b21f5a..78e5763f7c1a 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -2277,11 +2277,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, else ath9k_hw_spur_mitigate(ah, chan); - if (!ah->eep_ops->set_board_values(ah, chan)) { - DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, - "error setting board options\n"); - return -EIO; - } + ah->eep_ops->set_board_values(ah, chan); ath9k_hw_decrease_chain_power(ah, chan); -- cgit v1.2.3 From cee075a24eec64f1f5b2b3b14753b2d4b8ecce55 Mon Sep 17 00:00:00 2001 From: Sujith Date: Fri, 13 Mar 2009 09:07:23 +0530 Subject: ath9k: Update copyright in all the files How time flies. Signed-off-by: Sujith Signed-off-by: John W. Linville --- drivers/net/wireless/ath9k/ahb.c | 2 +- drivers/net/wireless/ath9k/ani.c | 2 +- drivers/net/wireless/ath9k/ani.h | 2 +- drivers/net/wireless/ath9k/ath9k.h | 2 +- drivers/net/wireless/ath9k/beacon.c | 2 +- drivers/net/wireless/ath9k/calib.c | 2 +- drivers/net/wireless/ath9k/calib.h | 2 +- drivers/net/wireless/ath9k/debug.c | 2 +- drivers/net/wireless/ath9k/debug.h | 2 +- drivers/net/wireless/ath9k/eeprom.c | 2 +- drivers/net/wireless/ath9k/eeprom.h | 2 +- drivers/net/wireless/ath9k/hw.c | 2 +- drivers/net/wireless/ath9k/hw.h | 2 +- drivers/net/wireless/ath9k/initvals.h | 2 +- drivers/net/wireless/ath9k/mac.c | 2 +- drivers/net/wireless/ath9k/mac.h | 2 +- drivers/net/wireless/ath9k/main.c | 2 +- drivers/net/wireless/ath9k/pci.c | 2 +- drivers/net/wireless/ath9k/phy.c | 2 +- drivers/net/wireless/ath9k/phy.h | 2 +- drivers/net/wireless/ath9k/rc.c | 2 +- drivers/net/wireless/ath9k/rc.h | 2 +- drivers/net/wireless/ath9k/recv.c | 2 +- drivers/net/wireless/ath9k/reg.h | 2 +- drivers/net/wireless/ath9k/regd.c | 2 +- drivers/net/wireless/ath9k/regd.h | 2 +- drivers/net/wireless/ath9k/regd_common.h | 2 +- drivers/net/wireless/ath9k/xmit.c | 2 +- 28 files changed, 28 insertions(+), 28 deletions(-) (limited to 'drivers/net/wireless/ath9k/eeprom.h') diff --git a/drivers/net/wireless/ath9k/ahb.c b/drivers/net/wireless/ath9k/ahb.c index 00cc7bb01f2e..0e65c51ba176 100644 --- a/drivers/net/wireless/ath9k/ahb.c +++ b/drivers/net/wireless/ath9k/ahb.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * Copyright (c) 2009 Gabor Juhos * Copyright (c) 2009 Imre Kaloz * diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c index a39eb760cbb7..6c5e887d50d7 100644 --- a/drivers/net/wireless/ath9k/ani.c +++ b/drivers/net/wireless/ath9k/ani.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/ani.h b/drivers/net/wireless/ath9k/ani.h index 7315761f6d74..08b4e7ed5ff0 100644 --- a/drivers/net/wireless/ath9k/ani.h +++ b/drivers/net/wireless/ath9k/ani.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index 5afd244ea6a3..2b0256455118 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c index 3fd1b86a9b39..e5b007196ca1 100644 --- a/drivers/net/wireless/ath9k/beacon.c +++ b/drivers/net/wireless/ath9k/beacon.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c index c9446fb6b153..e2d62e97131c 100644 --- a/drivers/net/wireless/ath9k/calib.c +++ b/drivers/net/wireless/ath9k/calib.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/calib.h b/drivers/net/wireless/ath9k/calib.h index 32589e0c5018..1c74bd50700d 100644 --- a/drivers/net/wireless/ath9k/calib.h +++ b/drivers/net/wireless/ath9k/calib.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/debug.c b/drivers/net/wireless/ath9k/debug.c index 82573cadb1ab..fdf9528fa49b 100644 --- a/drivers/net/wireless/ath9k/debug.c +++ b/drivers/net/wireless/ath9k/debug.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/debug.h b/drivers/net/wireless/ath9k/debug.h index 065268b8568f..7b0e5419d2bc 100644 --- a/drivers/net/wireless/ath9k/debug.h +++ b/drivers/net/wireless/ath9k/debug.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c index d7b9cf4e8eba..ffc36b0361c7 100644 --- a/drivers/net/wireless/ath9k/eeprom.c +++ b/drivers/net/wireless/ath9k/eeprom.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h index 8e5b880d445d..25b68c881ff1 100644 --- a/drivers/net/wireless/ath9k/eeprom.h +++ b/drivers/net/wireless/ath9k/eeprom.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 78e5763f7c1a..15e4d422cad4 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index dc681f011fdf..0b594e0ee260 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/initvals.h b/drivers/net/wireless/ath9k/initvals.h index 1d60c3706f1c..e2f0a34b79a1 100644 --- a/drivers/net/wireless/ath9k/initvals.h +++ b/drivers/net/wireless/ath9k/initvals.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c index f757bc7eec68..e0a6dee45839 100644 --- a/drivers/net/wireless/ath9k/mac.c +++ b/drivers/net/wireless/ath9k/mac.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/mac.h b/drivers/net/wireless/ath9k/mac.h index a75f65dae1d7..1176bce8b76c 100644 --- a/drivers/net/wireless/ath9k/mac.h +++ b/drivers/net/wireless/ath9k/mac.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index 8db75f6de53e..7d27eed78af4 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/pci.c b/drivers/net/wireless/ath9k/pci.c index 53572d96cdb6..6dbc58580abb 100644 --- a/drivers/net/wireless/ath9k/pci.c +++ b/drivers/net/wireless/ath9k/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c index e1494bae0f9f..8bcba906929a 100644 --- a/drivers/net/wireless/ath9k/phy.c +++ b/drivers/net/wireless/ath9k/phy.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/phy.h b/drivers/net/wireless/ath9k/phy.h index 1eac8c707342..0f7f8e0c9c95 100644 --- a/drivers/net/wireless/ath9k/phy.h +++ b/drivers/net/wireless/ath9k/phy.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/rc.c b/drivers/net/wireless/ath9k/rc.c index 74bc4e64b030..6c2fd395bc38 100644 --- a/drivers/net/wireless/ath9k/rc.c +++ b/drivers/net/wireless/ath9k/rc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2004 Video54 Technologies, Inc. - * Copyright (c) 2004-2008 Atheros Communications, Inc. + * Copyright (c) 2004-2009 Atheros Communications, Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/rc.h b/drivers/net/wireless/ath9k/rc.h index db9b0b9a3431..199a3ce57d64 100644 --- a/drivers/net/wireless/ath9k/rc.h +++ b/drivers/net/wireless/ath9k/rc.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2004 Sam Leffler, Errno Consulting * Copyright (c) 2004 Video54 Technologies, Inc. - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c index 0bba17662a1f..917bac7af6f6 100644 --- a/drivers/net/wireless/ath9k/recv.c +++ b/drivers/net/wireless/ath9k/recv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/reg.h b/drivers/net/wireless/ath9k/reg.h index d86e90e38173..52605246679f 100644 --- a/drivers/net/wireless/ath9k/reg.h +++ b/drivers/net/wireless/ath9k/reg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/regd.c b/drivers/net/wireless/ath9k/regd.c index b8f9b6d6bec4..4ca625102291 100644 --- a/drivers/net/wireless/ath9k/regd.c +++ b/drivers/net/wireless/ath9k/regd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/regd.h b/drivers/net/wireless/ath9k/regd.h index 8f885f3bc8df..9f5fbd4eea7a 100644 --- a/drivers/net/wireless/ath9k/regd.h +++ b/drivers/net/wireless/ath9k/regd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/regd_common.h b/drivers/net/wireless/ath9k/regd_common.h index b41d0002f3fe..4d0e298cd1c7 100644 --- a/drivers/net/wireless/ath9k/regd_common.h +++ b/drivers/net/wireless/ath9k/regd_common.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c index 0aae8f349ff0..8968abe7f485 100644 --- a/drivers/net/wireless/ath9k/xmit.c +++ b/drivers/net/wireless/ath9k/xmit.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2008 Atheros Communications Inc. + * Copyright (c) 2008-2009 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above -- cgit v1.2.3