From 4353594eb0980c80e24ebb20d9c871ff95b3b789 Mon Sep 17 00:00:00 2001 From: Rajat Jain Date: Tue, 21 Dec 2021 17:21:05 -0800 Subject: PCI: Use DWORD accesses for LTR, L1 SS to avoid erratum Some devices have an erratum such that they only support DWORD accesses to some registers. E.g., this Bayhub O2 device ([VID:DID] = [0x1217:0x8621]) only supports DWORD accesses to LTR latency registers and L1 PM substates control registers: https://github.com/rajatxjain/public_shared/blob/main/OZ711LV2_appnote.pdf The L1 PM substate control registers are DWORD sized, and hence their access in the kernel is already DWORD sized, so we don't need to do anything for them. However, the LTR registers being WORD sized, are in need of a solution. Convert the WORD sized accesses to these registers into DWORD sized accesses while saving and restoring them. Link: https://lore.kernel.org/r/20211222012105.3438916-1-rajatja@google.com Signed-off-by: Rajat Jain Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/pci/pcie') diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 52c74682601a..71296ee59581 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -496,6 +496,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link, encode_l12_threshold(l1_2_threshold, &scale, &value); ctl1 |= t_common_mode << 8 | scale << 29 | value << 16; + /* Some broken devices only support dword access to L1 SS */ pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1); pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2); pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1); -- cgit v1.2.3