From 9b44b0b09decfbe388131a345ba780c57240a7a9 Mon Sep 17 00:00:00 2001 From: Joerg Roedel Date: Tue, 11 Jul 2017 15:48:00 -0500 Subject: PCI: Mark AMD Stoney GPU ATS as broken ATS is broken on this hardware and causes IOMMU stalls and system failure. Disable ATS on these devices to make them usable again with IOMMU enabled. Note that the commit in the Fixes tag is not buggy; it just uncovers the problem in the hardware by increasing the ATS flush rate. Link: https://lists.linuxfoundation.org/pipermail/iommu/2017-March/020836.html Link: https://bugzilla.redhat.com/show_bug.cgi?id=1409201 Fixes: b1516a14657a ("iommu/amd: Implement flush queue") Signed-off-by: Joerg Roedel Signed-off-by: Bjorn Helgaas Acked-by: Alex Deucher --- drivers/pci/quirks.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers/pci/quirks.c') diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 6967c6b4cf6b..15ee4e9af633 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4681,3 +4681,18 @@ static void quirk_intel_no_flr(struct pci_dev *dev) } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); + +#ifdef CONFIG_PCI_ATS +/* + * Some devices have a broken ATS implementation causing IOMMU stalls. + * Don't use ATS for those devices. + */ +static void quirk_no_ats(struct pci_dev *pdev) +{ + dev_info(&pdev->dev, "disabling ATS (broken on this device)\n"); + pdev->ats_cap = 0; +} + +/* AMD Stoney platform GPU */ +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats); +#endif /* CONFIG_PCI_ATS */ -- cgit v1.2.3 From a0418aa262dfbe4011df85c8d40993bf21d53cd2 Mon Sep 17 00:00:00 2001 From: Feng Kan Date: Thu, 10 Aug 2017 16:06:33 -0500 Subject: PCI: Add ACS quirk for APM X-Gene devices The APM X-Gene PCIe root port does not support ACS at this point. However, the hardware provides isolation and source validation through the SMMU. The stream ID generated by the PCIe ports contain both the bus/device/ function number as well as the port ID in its 3 most significant bits. Turn on ACS but disable all the peer-to-peer features. Signed-off-by: Feng Kan Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Williamson Acked-by: Tanmay Inamdar --- drivers/pci/quirks.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/pci/quirks.c') diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 15ee4e9af633..92bea8accc35 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4137,6 +4137,18 @@ static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) return acs_flags ? 0 : 1; } +static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) +{ + /* + * X-Gene root matching this quirk do not allow peer-to-peer + * transactions with others, allowing masking out these bits as if they + * were unimplemented in the ACS capability. + */ + acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); + + return acs_flags ? 0 : 1; +} + /* * Many Intel PCH root ports do provide ACS-like features to disable peer * transactions and validate bus numbers in requests, but do not provide an @@ -4385,6 +4397,8 @@ static const struct pci_dev_acs_enabled { { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ /* Cavium ThunderX */ { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, + /* APM X-Gene */ + { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, { 0 } }; -- cgit v1.2.3