From 69c32972d59388c041268e8206e8eb1acff29b9a Mon Sep 17 00:00:00 2001 From: "Kulkarni, Ganapatrao" Date: Thu, 6 Dec 2018 11:51:31 +0000 Subject: drivers/perf: Add Cavium ThunderX2 SoC UNCORE PMU driver This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4 counters. All counters lack overflow interrupt and are sampled periodically. Reviewed-by: Suzuki K Poulose Signed-off-by: Ganapatrao Kulkarni [will: consistent enum cpuhp_state naming] Signed-off-by: Will Deacon --- drivers/perf/Makefile | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/perf/Makefile') diff --git a/drivers/perf/Makefile b/drivers/perf/Makefile index b3902bd37d53..909f27fd9db3 100644 --- a/drivers/perf/Makefile +++ b/drivers/perf/Makefile @@ -7,5 +7,6 @@ obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o obj-$(CONFIG_HISI_PMU) += hisilicon/ obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o +obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o -- cgit v1.2.3