From b95637e2da155cb3111d008e3c5d641b4dcf5000 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Fri, 9 Jul 2021 18:45:23 +0900 Subject: phy: samsung-ufs: move phy-exynos7-ufs header Instead of using exynos7 ufs definition in phy-exynos7-ufs.h, we should put it into phy-exynos7-ufs.c to be included different objects or units. Suggested-by: Krzysztof Kozlowski Signed-off-by: Chanho Park Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210709094524.110193-2-chanho61.park@samsung.com Signed-off-by: Vinod Koul --- drivers/phy/samsung/Makefile | 4 +- drivers/phy/samsung/phy-exynos7-ufs.c | 77 +++++++++++++++++++++++++++++++++ drivers/phy/samsung/phy-exynos7-ufs.h | 81 ----------------------------------- drivers/phy/samsung/phy-samsung-ufs.h | 5 ++- 4 files changed, 84 insertions(+), 83 deletions(-) create mode 100644 drivers/phy/samsung/phy-exynos7-ufs.c delete mode 100644 drivers/phy/samsung/phy-exynos7-ufs.h (limited to 'drivers/phy/samsung') diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile index 3959100fe8a2..68518ae30c1b 100644 --- a/drivers/phy/samsung/Makefile +++ b/drivers/phy/samsung/Makefile @@ -2,7 +2,9 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o -obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-samsung-ufs.o +obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-exynos-ufs.o +phy-exynos-ufs-y += phy-samsung-ufs.o +phy-exynos-ufs-y += phy-exynos7-ufs.o obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o phy-exynos-usb2-y += phy-samsung-usb2.o phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c new file mode 100644 index 000000000000..7c9008e163db --- /dev/null +++ b/drivers/phy/samsung/phy-exynos7-ufs.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UFS PHY driver data for Samsung EXYNOS7 SoC + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd. + */ + +#include "phy-samsung-ufs.h" + +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720 +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 +#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) + +/* Calibration for phy initialization */ +static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = { + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY), + END_UFS_PHY_CFG +}; + +/* Calibration for HS mode series A/B */ +static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = { + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY), + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY), + PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY), + /* Setting order: 1st(0x16, 2nd(0x15) */ + PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY), + PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY), + PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A), + PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B), + PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A), + PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B), + PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A), + PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B), + END_UFS_PHY_CFG +}; + +/* Calibration for HS mode series A/B atfer PMC */ +static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = { + PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY), + PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY), + END_UFS_PHY_CFG +}; + +static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = { + [CFG_PRE_INIT] = exynos7_pre_init_cfg, + [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg, + [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg, +}; + +const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = { + .cfg = exynos7_ufs_phy_cfgs, + .isol = { + .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL, + .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK, + .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN, + }, + .has_symbol_clk = 1, +}; diff --git a/drivers/phy/samsung/phy-exynos7-ufs.h b/drivers/phy/samsung/phy-exynos7-ufs.h deleted file mode 100644 index 518923141958..000000000000 --- a/drivers/phy/samsung/phy-exynos7-ufs.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * UFS PHY driver data for Samsung EXYNOS7 SoC - * - * Copyright (C) 2020 Samsung Electronics Co., Ltd. - */ -#ifndef _PHY_EXYNOS7_UFS_H_ -#define _PHY_EXYNOS7_UFS_H_ - -#include "phy-samsung-ufs.h" - -#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720 -#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 -#define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) - -/* Calibration for phy initialization */ -static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = { - PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), - PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY), - PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY), - PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY), - PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY), - END_UFS_PHY_CFG -}; - -/* Calibration for HS mode series A/B */ -static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = { - PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY), - PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY), - PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY), - /* Setting order: 1st(0x16, 2nd(0x15) */ - PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY), - PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY), - PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY), - PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY), - PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY), - PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY), - PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A), - PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B), - PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY), - PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY), - PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A), - PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B), - PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A), - PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B), - END_UFS_PHY_CFG -}; - -/* Calibration for HS mode series A/B atfer PMC */ -static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = { - PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY), - PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY), - END_UFS_PHY_CFG -}; - -static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = { - [CFG_PRE_INIT] = exynos7_pre_init_cfg, - [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg, - [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg, -}; - -static struct samsung_ufs_phy_drvdata exynos7_ufs_phy = { - .cfg = exynos7_ufs_phy_cfgs, - .isol = { - .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL, - .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK, - .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN, - }, - .has_symbol_clk = 1, -}; - -#endif /* _PHY_EXYNOS7_UFS_H_ */ diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h index 5de78710524c..5ab6ca6fa187 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.h +++ b/drivers/phy/samsung/phy-samsung-ufs.h @@ -10,6 +10,9 @@ #ifndef _PHY_SAMSUNG_UFS_ #define _PHY_SAMSUNG_UFS_ +#include +#include + #define PHY_COMN_BLK 1 #define PHY_TRSV_BLK 2 #define END_UFS_PHY_CFG { 0 } @@ -134,6 +137,6 @@ static inline void samsung_ufs_phy_ctrl_isol( phy->isol->mask, isol ? 0 : phy->isol->en); } -#include "phy-exynos7-ufs.h" +extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy; #endif /* _PHY_SAMSUNG_UFS_ */ -- cgit v1.2.3