From 0a69452e03564c5eaf99f729de398cd94ee90851 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Sat, 17 Apr 2021 13:29:46 +0200 Subject: soc: rockchip: power-domain: Add a meaningful power domain name Add the power domains names to the power domain info struct so we have meaningful name for every power domain. Signed-off-by: Elaine Zhang Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210417112952.8516-10-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/pm_domains.c | 221 ++++++++++++++++++++------------------ 1 file changed, 114 insertions(+), 107 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 54eb6cfc5d5b..1d1b06672861 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -29,6 +29,7 @@ #include struct rockchip_domain_info { + const char *name; int pwr_mask; int status_mask; int req_mask; @@ -85,8 +86,9 @@ struct rockchip_pmu { #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) -#define DOMAIN(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_mask = (pwr), \ .status_mask = (status), \ .req_mask = (req), \ @@ -95,8 +97,9 @@ struct rockchip_pmu { .active_wakeup = (wakeup), \ } -#define DOMAIN_M(pwr, status, req, idle, ack, wakeup) \ +#define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ { \ + .name = _name, \ .pwr_w_mask = (pwr) << 16, \ .pwr_mask = (pwr), \ .status_mask = (status), \ @@ -107,8 +110,9 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_RK3036(req, ack, idle, wakeup) \ +#define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ { \ + .name = _name, \ .req_mask = (req), \ .req_w_mask = (req) << 16, \ .ack_mask = (ack), \ @@ -116,20 +120,20 @@ struct rockchip_pmu { .active_wakeup = wakeup, \ } -#define DOMAIN_PX30(pwr, status, req, wakeup) \ - DOMAIN_M(pwr, status, req, (req) << 16, req, wakeup) +#define DOMAIN_PX30(name, pwr, status, req, wakeup) \ + DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3288(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, (req) << 16, wakeup) +#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) -#define DOMAIN_RK3328(pwr, status, req, wakeup) \ - DOMAIN_M(pwr, pwr, req, (req) << 10, req, wakeup) +#define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) -#define DOMAIN_RK3368(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, (req) << 16, req, wakeup) +#define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) -#define DOMAIN_RK3399(pwr, status, req, wakeup) \ - DOMAIN(pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ + DOMAIN(name, pwr, status, req, req, req, wakeup) static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { @@ -490,7 +494,10 @@ static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, goto err_unprepare_clocks; } - pd->genpd.name = node->name; + if (pd->info->name) + pd->genpd.name = pd->info->name; + else + pd->genpd.name = kbasename(node->full_name); pd->genpd.power_off = rockchip_pd_power_off; pd->genpd.power_on = rockchip_pd_power_on; pd->genpd.attach_dev = rockchip_pd_attach_dev; @@ -716,129 +723,129 @@ err_out: } static const struct rockchip_domain_info px30_pm_domains[] = { - [PX30_PD_USB] = DOMAIN_PX30(BIT(5), BIT(5), BIT(10), false), - [PX30_PD_SDCARD] = DOMAIN_PX30(BIT(8), BIT(8), BIT(9), false), - [PX30_PD_GMAC] = DOMAIN_PX30(BIT(10), BIT(10), BIT(6), false), - [PX30_PD_MMC_NAND] = DOMAIN_PX30(BIT(11), BIT(11), BIT(5), false), - [PX30_PD_VPU] = DOMAIN_PX30(BIT(12), BIT(12), BIT(14), false), - [PX30_PD_VO] = DOMAIN_PX30(BIT(13), BIT(13), BIT(7), false), - [PX30_PD_VI] = DOMAIN_PX30(BIT(14), BIT(14), BIT(8), false), - [PX30_PD_GPU] = DOMAIN_PX30(BIT(15), BIT(15), BIT(2), false), + [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), + [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), + [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), + [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), + [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), + [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), + [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), + [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3036_pm_domains[] = { - [RK3036_PD_MSCH] = DOMAIN_RK3036(BIT(14), BIT(23), BIT(30), true), - [RK3036_PD_CORE] = DOMAIN_RK3036(BIT(13), BIT(17), BIT(24), false), - [RK3036_PD_PERI] = DOMAIN_RK3036(BIT(12), BIT(18), BIT(25), false), - [RK3036_PD_VIO] = DOMAIN_RK3036(BIT(11), BIT(19), BIT(26), false), - [RK3036_PD_VPU] = DOMAIN_RK3036(BIT(10), BIT(20), BIT(27), false), - [RK3036_PD_GPU] = DOMAIN_RK3036(BIT(9), BIT(21), BIT(28), false), - [RK3036_PD_SYS] = DOMAIN_RK3036(BIT(8), BIT(22), BIT(29), false), + [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), + [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), + [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), + [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), + [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), + [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), + [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), }; static const struct rockchip_domain_info rk3066_pm_domains[] = { - [RK3066_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3066_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3066_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3066_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3066_PD_CPU] = DOMAIN(0, BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3128_pm_domains[] = { - [RK3128_PD_CORE] = DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false), - [RK3128_PD_MSCH] = DOMAIN_RK3288(0, 0, BIT(6), true), - [RK3128_PD_VIO] = DOMAIN_RK3288(BIT(3), BIT(3), BIT(2), false), - [RK3128_PD_VIDEO] = DOMAIN_RK3288(BIT(2), BIT(2), BIT(1), false), - [RK3128_PD_GPU] = DOMAIN_RK3288(BIT(1), BIT(1), BIT(3), false), + [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), + [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), + [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), + [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), + [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), }; static const struct rockchip_domain_info rk3188_pm_domains[] = { - [RK3188_PD_GPU] = DOMAIN(BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), - [RK3188_PD_VIDEO] = DOMAIN(BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), - [RK3188_PD_VIO] = DOMAIN(BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), - [RK3188_PD_PERI] = DOMAIN(BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), - [RK3188_PD_CPU] = DOMAIN(BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), + [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), + [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), + [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), + [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), + [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), }; static const struct rockchip_domain_info rk3228_pm_domains[] = { - [RK3228_PD_CORE] = DOMAIN_RK3036(BIT(0), BIT(0), BIT(16), true), - [RK3228_PD_MSCH] = DOMAIN_RK3036(BIT(1), BIT(1), BIT(17), true), - [RK3228_PD_BUS] = DOMAIN_RK3036(BIT(2), BIT(2), BIT(18), true), - [RK3228_PD_SYS] = DOMAIN_RK3036(BIT(3), BIT(3), BIT(19), true), - [RK3228_PD_VIO] = DOMAIN_RK3036(BIT(4), BIT(4), BIT(20), false), - [RK3228_PD_VOP] = DOMAIN_RK3036(BIT(5), BIT(5), BIT(21), false), - [RK3228_PD_VPU] = DOMAIN_RK3036(BIT(6), BIT(6), BIT(22), false), - [RK3228_PD_RKVDEC] = DOMAIN_RK3036(BIT(7), BIT(7), BIT(23), false), - [RK3228_PD_GPU] = DOMAIN_RK3036(BIT(8), BIT(8), BIT(24), false), - [RK3228_PD_PERI] = DOMAIN_RK3036(BIT(9), BIT(9), BIT(25), true), - [RK3228_PD_GMAC] = DOMAIN_RK3036(BIT(10), BIT(10), BIT(26), false), + [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), + [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), + [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), + [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), + [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), + [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), + [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), + [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), + [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), + [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), + [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), }; static const struct rockchip_domain_info rk3288_pm_domains[] = { - [RK3288_PD_VIO] = DOMAIN_RK3288(BIT(7), BIT(7), BIT(4), false), - [RK3288_PD_HEVC] = DOMAIN_RK3288(BIT(14), BIT(10), BIT(9), false), - [RK3288_PD_VIDEO] = DOMAIN_RK3288(BIT(8), BIT(8), BIT(3), false), - [RK3288_PD_GPU] = DOMAIN_RK3288(BIT(9), BIT(9), BIT(2), false), + [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), + [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), + [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), + [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), }; static const struct rockchip_domain_info rk3328_pm_domains[] = { - [RK3328_PD_CORE] = DOMAIN_RK3328(0, BIT(0), BIT(0), false), - [RK3328_PD_GPU] = DOMAIN_RK3328(0, BIT(1), BIT(1), false), - [RK3328_PD_BUS] = DOMAIN_RK3328(0, BIT(2), BIT(2), true), - [RK3328_PD_MSCH] = DOMAIN_RK3328(0, BIT(3), BIT(3), true), - [RK3328_PD_PERI] = DOMAIN_RK3328(0, BIT(4), BIT(4), true), - [RK3328_PD_VIDEO] = DOMAIN_RK3328(0, BIT(5), BIT(5), false), - [RK3328_PD_HEVC] = DOMAIN_RK3328(0, BIT(6), BIT(6), false), - [RK3328_PD_VIO] = DOMAIN_RK3328(0, BIT(8), BIT(8), false), - [RK3328_PD_VPU] = DOMAIN_RK3328(0, BIT(9), BIT(9), false), + [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), + [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), + [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), + [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), + [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), + [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), + [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), + [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), + [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), }; static const struct rockchip_domain_info rk3366_pm_domains[] = { - [RK3366_PD_PERI] = DOMAIN_RK3368(BIT(10), BIT(10), BIT(6), true), - [RK3366_PD_VIO] = DOMAIN_RK3368(BIT(14), BIT(14), BIT(8), false), - [RK3366_PD_VIDEO] = DOMAIN_RK3368(BIT(13), BIT(13), BIT(7), false), - [RK3366_PD_RKVDEC] = DOMAIN_RK3368(BIT(11), BIT(11), BIT(7), false), - [RK3366_PD_WIFIBT] = DOMAIN_RK3368(BIT(8), BIT(8), BIT(9), false), - [RK3366_PD_VPU] = DOMAIN_RK3368(BIT(12), BIT(12), BIT(7), false), - [RK3366_PD_GPU] = DOMAIN_RK3368(BIT(15), BIT(15), BIT(2), false), + [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), + [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), + [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), + [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), + [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), + [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), + [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), }; static const struct rockchip_domain_info rk3368_pm_domains[] = { - [RK3368_PD_PERI] = DOMAIN_RK3368(BIT(13), BIT(12), BIT(6), true), - [RK3368_PD_VIO] = DOMAIN_RK3368(BIT(15), BIT(14), BIT(8), false), - [RK3368_PD_VIDEO] = DOMAIN_RK3368(BIT(14), BIT(13), BIT(7), false), - [RK3368_PD_GPU_0] = DOMAIN_RK3368(BIT(16), BIT(15), BIT(2), false), - [RK3368_PD_GPU_1] = DOMAIN_RK3368(BIT(17), BIT(16), BIT(2), false), + [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), + [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), + [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), + [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), + [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), }; static const struct rockchip_domain_info rk3399_pm_domains[] = { - [RK3399_PD_TCPD0] = DOMAIN_RK3399(BIT(8), BIT(8), 0, false), - [RK3399_PD_TCPD1] = DOMAIN_RK3399(BIT(9), BIT(9), 0, false), - [RK3399_PD_CCI] = DOMAIN_RK3399(BIT(10), BIT(10), 0, true), - [RK3399_PD_CCI0] = DOMAIN_RK3399(0, 0, BIT(15), true), - [RK3399_PD_CCI1] = DOMAIN_RK3399(0, 0, BIT(16), true), - [RK3399_PD_PERILP] = DOMAIN_RK3399(BIT(11), BIT(11), BIT(1), true), - [RK3399_PD_PERIHP] = DOMAIN_RK3399(BIT(12), BIT(12), BIT(2), true), - [RK3399_PD_CENTER] = DOMAIN_RK3399(BIT(13), BIT(13), BIT(14), true), - [RK3399_PD_VIO] = DOMAIN_RK3399(BIT(14), BIT(14), BIT(17), false), - [RK3399_PD_GPU] = DOMAIN_RK3399(BIT(15), BIT(15), BIT(0), false), - [RK3399_PD_VCODEC] = DOMAIN_RK3399(BIT(16), BIT(16), BIT(3), false), - [RK3399_PD_VDU] = DOMAIN_RK3399(BIT(17), BIT(17), BIT(4), false), - [RK3399_PD_RGA] = DOMAIN_RK3399(BIT(18), BIT(18), BIT(5), false), - [RK3399_PD_IEP] = DOMAIN_RK3399(BIT(19), BIT(19), BIT(6), false), - [RK3399_PD_VO] = DOMAIN_RK3399(BIT(20), BIT(20), 0, false), - [RK3399_PD_VOPB] = DOMAIN_RK3399(0, 0, BIT(7), false), - [RK3399_PD_VOPL] = DOMAIN_RK3399(0, 0, BIT(8), false), - [RK3399_PD_ISP0] = DOMAIN_RK3399(BIT(22), BIT(22), BIT(9), false), - [RK3399_PD_ISP1] = DOMAIN_RK3399(BIT(23), BIT(23), BIT(10), false), - [RK3399_PD_HDCP] = DOMAIN_RK3399(BIT(24), BIT(24), BIT(11), false), - [RK3399_PD_GMAC] = DOMAIN_RK3399(BIT(25), BIT(25), BIT(23), true), - [RK3399_PD_EMMC] = DOMAIN_RK3399(BIT(26), BIT(26), BIT(24), true), - [RK3399_PD_USB3] = DOMAIN_RK3399(BIT(27), BIT(27), BIT(12), true), - [RK3399_PD_EDP] = DOMAIN_RK3399(BIT(28), BIT(28), BIT(22), false), - [RK3399_PD_GIC] = DOMAIN_RK3399(BIT(29), BIT(29), BIT(27), true), - [RK3399_PD_SD] = DOMAIN_RK3399(BIT(30), BIT(30), BIT(28), true), - [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true), + [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), + [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), + [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), + [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), + [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), + [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), + [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), + [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), + [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), + [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), + [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), + [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), + [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), + [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), + [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), + [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), + [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), + [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), + [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), + [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), + [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), + [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), + [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), + [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), + [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), + [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), + [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; static const struct rockchip_pmu_info px30_pmu = { -- cgit v1.2.3 From c1f512182c54dc87efd2f7ac19f16a49ff8bb19e Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Wed, 31 Mar 2021 16:39:59 +0800 Subject: soc: bcm: brcmstb: remove unused variable 'brcmstb_machine_match' Fix the following clang warning: drivers/soc/bcm/brcmstb/common.c:17:34: warning: unused variable 'brcmstb_machine_match' [-Wunused-const-variable]. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/common.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/brcmstb/common.c b/drivers/soc/bcm/brcmstb/common.c index e87dfc6660f3..2a010881f4b6 100644 --- a/drivers/soc/bcm/brcmstb/common.c +++ b/drivers/soc/bcm/brcmstb/common.c @@ -14,11 +14,6 @@ static u32 family_id; static u32 product_id; -static const struct of_device_id brcmstb_machine_match[] = { - { .compatible = "brcm,brcmstb", }, - { } -}; - u32 brcmstb_get_family_id(void) { return family_id; -- cgit v1.2.3 From 1782c87b44a0b1a527f01a6a184677c58ccbf9c7 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Sat, 17 Apr 2021 13:29:52 +0200 Subject: soc: rockchip: power-domain: add rk3568 powerdomains Add power-domains found on rk3568 socs. Signed-off-by: Elaine Zhang Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20210417112952.8516-16-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/pm_domains.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c index 1d1b06672861..0868b7d406fb 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c @@ -27,6 +27,7 @@ #include #include #include +#include struct rockchip_domain_info { const char *name; @@ -135,6 +136,9 @@ struct rockchip_pmu { #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ DOMAIN(name, pwr, status, req, req, req, wakeup) +#define DOMAIN_RK3568(name, pwr, req, wakeup) \ + DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) + static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) { struct rockchip_pmu *pmu = pd->pmu; @@ -848,6 +852,18 @@ static const struct rockchip_domain_info rk3399_pm_domains[] = { [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), }; +static const struct rockchip_domain_info rk3568_pm_domains[] = { + [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), + [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), + [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false), + [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false), + [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false), + [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false), + [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false), + [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false), + [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false), +}; + static const struct rockchip_pmu_info px30_pmu = { .pwr_offset = 0x18, .status_offset = 0x20, @@ -983,6 +999,17 @@ static const struct rockchip_pmu_info rk3399_pmu = { .domain_info = rk3399_pm_domains, }; +static const struct rockchip_pmu_info rk3568_pmu = { + .pwr_offset = 0xa0, + .status_offset = 0x98, + .req_offset = 0x50, + .idle_offset = 0x68, + .ack_offset = 0x60, + + .num_domains = ARRAY_SIZE(rk3568_pm_domains), + .domain_info = rk3568_pm_domains, +}; + static const struct of_device_id rockchip_pm_domain_dt_match[] = { { .compatible = "rockchip,px30-power-controller", @@ -1028,6 +1055,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = { .compatible = "rockchip,rk3399-power-controller", .data = (void *)&rk3399_pmu, }, + { + .compatible = "rockchip,rk3568-power-controller", + .data = (void *)&rk3568_pmu, + }, { /* sentinel */ }, }; -- cgit v1.2.3 From ba96de3ae5a7e2121cac80053b277eb2ab51a0ae Mon Sep 17 00:00:00 2001 From: Zou Wei Date: Tue, 11 May 2021 11:55:50 +0800 Subject: soc: mediatek: add missing MODULE_DEVICE_TABLE This patch adds missing MODULE_DEVICE_TABLE definition which generates correct modalias for automatic loading of this driver when it is built as an external module. Reported-by: Hulk Robot Signed-off-by: Zou Wei Link: https://lore.kernel.org/r/1620705350-104687-1-git-send-email-zou_wei@huawei.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-devapc.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c index f1cea041dc5a..7c65ad3d1f8a 100644 --- a/drivers/soc/mediatek/mtk-devapc.c +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -234,6 +234,7 @@ static const struct of_device_id mtk_devapc_dt_match[] = { }, { }, }; +MODULE_DEVICE_TABLE(of, mtk_devapc_dt_match); static int mtk_devapc_probe(struct platform_device *pdev) { -- cgit v1.2.3 From 4ed57c97b414a2e285ce46e41e8387b51961cd64 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:33 +0800 Subject: soc: imx: gpcv2: move to more ideomatic error handling in probe Switch to "goto out..." error handling in domain driver probe to avoid repeating all the error paths. Tested-by: Frieder Schrempf Reviewed-by: Marek Vasut Reviewed-by: Frieder Schrempf Tested-by: Adam Ford Signed-off-by: Lucas Stach Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index db7e7fc321b1..512e6f4acafd 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -502,18 +502,23 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) ret = pm_genpd_init(&domain->genpd, NULL, true); if (ret) { dev_err(domain->dev, "Failed to init power domain\n"); - imx_pgc_put_clocks(domain); - return ret; + goto out_put_clocks; } ret = of_genpd_add_provider_simple(domain->dev->of_node, &domain->genpd); if (ret) { dev_err(domain->dev, "Failed to add genpd provider\n"); - pm_genpd_remove(&domain->genpd); - imx_pgc_put_clocks(domain); + goto out_genpd_remove; } + return 0; + +out_genpd_remove: + pm_genpd_remove(&domain->genpd); +out_put_clocks: + imx_pgc_put_clocks(domain); + return ret; } -- cgit v1.2.3 From 4ac6317a3701007df4837dcd8036b21d6a049327 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:34 +0800 Subject: soc: imx: gpcv2: move domain mapping to domain driver probe As long as the power domain driver is active we want power control over the domain (which is what the mapping bit requests), so there is no point in whacking it for every power control action, simply set the bit in driver probe and clear it when the driver is removed. Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Signed-off-by: Lucas Stach Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 512e6f4acafd..552d3e6bee52 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -140,14 +140,11 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd, int i, ret = 0; u32 pxx_req; - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, domain->bits.map); - if (has_regulator && on) { ret = regulator_enable(domain->regulator); if (ret) { dev_err(domain->dev, "failed to enable regulator\n"); - goto unmap; + return ret; } } @@ -203,9 +200,7 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd, /* Preserve earlier error code */ ret = ret ?: err; } -unmap: - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, 0); + return ret; } @@ -499,10 +494,13 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) if (ret) return dev_err_probe(domain->dev, ret, "Failed to get domain's clocks\n"); + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, domain->bits.map); + ret = pm_genpd_init(&domain->genpd, NULL, true); if (ret) { dev_err(domain->dev, "Failed to init power domain\n"); - goto out_put_clocks; + goto out_domain_unmap; } ret = of_genpd_add_provider_simple(domain->dev->of_node, @@ -516,7 +514,9 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) out_genpd_remove: pm_genpd_remove(&domain->genpd); -out_put_clocks: +out_domain_unmap: + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); imx_pgc_put_clocks(domain); return ret; @@ -528,6 +528,10 @@ static int imx_pgc_domain_remove(struct platform_device *pdev) of_genpd_del_provider(domain->dev->of_node); pm_genpd_remove(&domain->genpd); + + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); + imx_pgc_put_clocks(domain); return 0; -- cgit v1.2.3 From cbca0b4fd21123fc10fb23101fd4f29f5de88574 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:35 +0800 Subject: soc: imx: gpcv2: switch to clk_bulk_* API Use clk_bulk API to simplify the code a bit. Also add some error checking to the clk_prepare_enable calls. Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Signed-off-by: Lucas Stach Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 60 ++++++++++--------------------------------------- 1 file changed, 12 insertions(+), 48 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 552d3e6bee52..4222b6e87e7c 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -100,13 +100,11 @@ #define GPC_PGC_CTRL_PCR BIT(0) -#define GPC_CLK_MAX 6 - struct imx_pgc_domain { struct generic_pm_domain genpd; struct regmap *regmap; struct regulator *regulator; - struct clk *clk[GPC_CLK_MAX]; + struct clk_bulk_data *clks; int num_clks; unsigned int pgc; @@ -149,8 +147,12 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd, } /* Enable reset clocks for all devices in the domain */ - for (i = 0; i < domain->num_clks; i++) - clk_prepare_enable(domain->clk[i]); + ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); + if (ret) { + dev_err(domain->dev, "failed to enable reset clocks\n"); + regulator_disable(domain->regulator); + return ret; + } if (enable_power_control) regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), @@ -187,8 +189,7 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd, GPC_PGC_CTRL_PCR, 0); /* Disable reset clocks for all devices in the domain */ - for (i = 0; i < domain->num_clks; i++) - clk_disable_unprepare(domain->clk[i]); + clk_bulk_disable_unprepare(domain->num_clks, domain->clks); if (has_regulator && !on) { int err; @@ -438,41 +439,6 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = { .reg_access_table = &imx8m_access_table, }; -static int imx_pgc_get_clocks(struct imx_pgc_domain *domain) -{ - int i, ret; - - for (i = 0; ; i++) { - struct clk *clk = of_clk_get(domain->dev->of_node, i); - if (IS_ERR(clk)) - break; - if (i >= GPC_CLK_MAX) { - dev_err(domain->dev, "more than %d clocks\n", - GPC_CLK_MAX); - ret = -EINVAL; - goto clk_err; - } - domain->clk[i] = clk; - } - domain->num_clks = i; - - return 0; - -clk_err: - while (i--) - clk_put(domain->clk[i]); - - return ret; -} - -static void imx_pgc_put_clocks(struct imx_pgc_domain *domain) -{ - int i; - - for (i = domain->num_clks - 1; i >= 0; i--) - clk_put(domain->clk[i]); -} - static int imx_pgc_domain_probe(struct platform_device *pdev) { struct imx_pgc_domain *domain = pdev->dev.platform_data; @@ -490,9 +456,10 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) domain->voltage, domain->voltage); } - ret = imx_pgc_get_clocks(domain); - if (ret) - return dev_err_probe(domain->dev, ret, "Failed to get domain's clocks\n"); + domain->num_clks = devm_clk_bulk_get_all(domain->dev, &domain->clks); + if (domain->num_clks < 0) + return dev_err_probe(domain->dev, domain->num_clks, + "Failed to get domain's clocks\n"); regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, domain->bits.map, domain->bits.map); @@ -517,7 +484,6 @@ out_genpd_remove: out_domain_unmap: regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, domain->bits.map, 0); - imx_pgc_put_clocks(domain); return ret; } @@ -532,8 +498,6 @@ static int imx_pgc_domain_remove(struct platform_device *pdev) regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, domain->bits.map, 0); - imx_pgc_put_clocks(domain); - return 0; } -- cgit v1.2.3 From 256f07edbdd27d4eb0088eb895669e04f4012f9c Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:36 +0800 Subject: soc: imx: gpcv2: split power up and power down sequence control The current mixed function to control both power up and power down sequences is very hard to follow and already contains some sequence errors like triggering the ADB400 handshake at the wrong time due to this. Split the function into two, which results in slightly more code, but is way easier to get right. Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Signed-off-by: Lucas Stach Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 141 +++++++++++++++++++++++++++++------------------- 1 file changed, 86 insertions(+), 55 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 4222b6e87e7c..bcf1f338b0bf 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -125,20 +125,19 @@ struct imx_pgc_domain_data { const struct regmap_access_table *reg_access_table; }; -static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd, - bool on) +static inline struct imx_pgc_domain * +to_imx_pgc_domain(struct generic_pm_domain *genpd) { - struct imx_pgc_domain *domain = container_of(genpd, - struct imx_pgc_domain, - genpd); - unsigned int offset = on ? - GPC_PU_PGC_SW_PUP_REQ : GPC_PU_PGC_SW_PDN_REQ; - const bool enable_power_control = !on; - const bool has_regulator = !IS_ERR(domain->regulator); - int i, ret = 0; - u32 pxx_req; - - if (has_regulator && on) { + return container_of(genpd, struct imx_pgc_domain, genpd); +} + +static int imx_pgc_power_up(struct generic_pm_domain *genpd) +{ + struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); + u32 reg_val; + int ret; + + if (!IS_ERR(domain->regulator)) { ret = regulator_enable(domain->regulator); if (ret) { dev_err(domain->dev, "failed to enable regulator\n"); @@ -150,69 +149,101 @@ static int imx_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd, ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); if (ret) { dev_err(domain->dev, "failed to enable reset clocks\n"); - regulator_disable(domain->regulator); - return ret; + goto out_regulator_disable; } - if (enable_power_control) - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); - - if (domain->bits.hsk) - regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, - domain->bits.hsk, on ? domain->bits.hsk : 0); - - regmap_update_bits(domain->regmap, offset, + /* request the domain to power up */ + regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, domain->bits.pxx, domain->bits.pxx); - /* * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait * for PUP_REQ/PDN_REQ bit to be cleared */ - ret = regmap_read_poll_timeout(domain->regmap, offset, pxx_req, - !(pxx_req & domain->bits.pxx), + ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, + reg_val, !(reg_val & domain->bits.pxx), 0, USEC_PER_MSEC); if (ret) { dev_err(domain->dev, "failed to command PGC\n"); - /* - * If we were in a process of enabling a - * domain and failed we might as well disable - * the regulator we just enabled. And if it - * was the opposite situation and we failed to - * power down -- keep the regulator on - */ - on = !on; + goto out_clk_disable; } - if (enable_power_control) - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, 0); + /* disable power control */ + regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR); + + /* request the ADB400 to power up */ + if (domain->bits.hsk) + regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, + domain->bits.hsk, domain->bits.hsk); /* Disable reset clocks for all devices in the domain */ clk_bulk_disable_unprepare(domain->num_clks, domain->clks); - if (has_regulator && !on) { - int err; + return 0; - err = regulator_disable(domain->regulator); - if (err) - dev_err(domain->dev, - "failed to disable regulator: %d\n", err); - /* Preserve earlier error code */ - ret = ret ?: err; - } +out_clk_disable: + clk_bulk_disable_unprepare(domain->num_clks, domain->clks); +out_regulator_disable: + if (!IS_ERR(domain->regulator)) + regulator_disable(domain->regulator); return ret; } -static int imx_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd) +static int imx_pgc_power_down(struct generic_pm_domain *genpd) { - return imx_gpc_pu_pgc_sw_pxx_req(genpd, true); -} + struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); + u32 reg_val; + int ret; -static int imx_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd) -{ - return imx_gpc_pu_pgc_sw_pxx_req(genpd, false); + /* Enable reset clocks for all devices in the domain */ + ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); + if (ret) { + dev_err(domain->dev, "failed to enable reset clocks\n"); + return ret; + } + + /* request the ADB400 to power down */ + if (domain->bits.hsk) + regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK, + domain->bits.hsk); + + /* enable power control */ + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + + /* request the domain to power down */ + regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, + domain->bits.pxx, domain->bits.pxx); + /* + * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait + * for PUP_REQ/PDN_REQ bit to be cleared + */ + ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, + reg_val, !(reg_val & domain->bits.pxx), + 0, USEC_PER_MSEC); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto out_clk_disable; + } + + /* Disable reset clocks for all devices in the domain */ + clk_bulk_disable_unprepare(domain->num_clks, domain->clks); + + if (!IS_ERR(domain->regulator)) { + ret = regulator_disable(domain->regulator); + if (ret) { + dev_err(domain->dev, "failed to disable regulator\n"); + return ret; + } + } + + return 0; + +out_clk_disable: + clk_bulk_disable_unprepare(domain->num_clks, domain->clks); + + return ret; } static const struct imx_pgc_domain imx7_pgc_domains[] = { @@ -590,8 +621,8 @@ static int imx_gpcv2_probe(struct platform_device *pdev) domain = pd_pdev->dev.platform_data; domain->regmap = regmap; - domain->genpd.power_on = imx_gpc_pu_pgc_sw_pup_req; - domain->genpd.power_off = imx_gpc_pu_pgc_sw_pdn_req; + domain->genpd.power_on = imx_pgc_power_up; + domain->genpd.power_off = imx_pgc_power_down; pd_pdev->dev.parent = dev; pd_pdev->dev.of_node = np; -- cgit v1.2.3 From 58d268619aa941c39056f2c7464edb52d6b6b811 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:37 +0800 Subject: soc: imx: gpcv2: wait for ADB400 handshake New reference manuals show that there is actually a status bit for the ADB400 handshake. Add a poll loop to wait for the ADB400 to acknowledge our request. [Peng Fan: i.MX8MM has blk ctl module, the handshake can only finish after setting blk ctl. The blk ctl driver will set the bus clk bit and the handshake will finish there. we just add a delay and suppose the handshake will finish after that.] Tested-by: Frieder Schrempf Signed-off-by: Lucas Stach Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 47 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 39 insertions(+), 8 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index bcf1f338b0bf..c449cd0e1499 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -69,6 +69,9 @@ #define GPC_PU_PWRHSK 0x1fc +#define IMX8M_GPU_HSK_PWRDNACKN BIT(26) +#define IMX8M_VPU_HSK_PWRDNACKN BIT(25) +#define IMX8M_DISP_HSK_PWRDNACKN BIT(24) #define IMX8M_GPU_HSK_PWRDNREQN BIT(6) #define IMX8M_VPU_HSK_PWRDNREQN BIT(5) #define IMX8M_DISP_HSK_PWRDNREQN BIT(4) @@ -112,7 +115,8 @@ struct imx_pgc_domain { const struct { u32 pxx; u32 map; - u32 hsk; + u32 hskreq; + u32 hskack; } bits; const int voltage; @@ -172,9 +176,23 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) GPC_PGC_CTRL_PCR); /* request the ADB400 to power up */ - if (domain->bits.hsk) + if (domain->bits.hskreq) { regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, - domain->bits.hsk, domain->bits.hsk); + domain->bits.hskreq, domain->bits.hskreq); + + /* + * ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val, + * (reg_val & domain->bits.hskack), 0, + * USEC_PER_MSEC); + * Technically we need the commented code to wait handshake. But that needs + * the BLK-CTL module BUS clk-en bit being set. + * + * There is a separate BLK-CTL module and we will have such a driver for it, + * that driver will set the BUS clk-en bit and handshake will be triggered + * automatically there. Just add a delay and suppose the handshake finish + * after that. + */ + } /* Disable reset clocks for all devices in the domain */ clk_bulk_disable_unprepare(domain->num_clks, domain->clks); @@ -204,9 +222,19 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) } /* request the ADB400 to power down */ - if (domain->bits.hsk) + if (domain->bits.hskreq) { regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK, - domain->bits.hsk); + domain->bits.hskreq); + + ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, + reg_val, + !(reg_val & domain->bits.hskack), + 0, USEC_PER_MSEC); + if (ret) { + dev_err(domain->dev, "failed to power down ADB400\n"); + goto out_clk_disable; + } + } /* enable power control */ regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), @@ -369,7 +397,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .bits = { .pxx = IMX8M_GPU_SW_Pxx_REQ, .map = IMX8M_GPU_A53_DOMAIN, - .hsk = IMX8M_GPU_HSK_PWRDNREQN, + .hskreq = IMX8M_GPU_HSK_PWRDNREQN, + .hskack = IMX8M_GPU_HSK_PWRDNACKN, }, .pgc = IMX8M_PGC_GPU, }, @@ -381,7 +410,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .bits = { .pxx = IMX8M_VPU_SW_Pxx_REQ, .map = IMX8M_VPU_A53_DOMAIN, - .hsk = IMX8M_VPU_HSK_PWRDNREQN, + .hskreq = IMX8M_VPU_HSK_PWRDNREQN, + .hskack = IMX8M_VPU_HSK_PWRDNACKN, }, .pgc = IMX8M_PGC_VPU, }, @@ -393,7 +423,8 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .bits = { .pxx = IMX8M_DISP_SW_Pxx_REQ, .map = IMX8M_DISP_A53_DOMAIN, - .hsk = IMX8M_DISP_HSK_PWRDNREQN, + .hskreq = IMX8M_DISP_HSK_PWRDNREQN, + .hskack = IMX8M_DISP_HSK_PWRDNACKN, }, .pgc = IMX8M_PGC_DISP, }, -- cgit v1.2.3 From 1382eb1967d74fb40c3c9e8c6f6030c4c0ecc040 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:38 +0800 Subject: soc: imx: gpcv2: add runtime PM support for power-domains This allows to nest domains into other power domains and have the parent domain powered up/down as required by the child domains. Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Signed-off-by: Lucas Stach Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index c449cd0e1499..800287abdbea 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -141,11 +142,17 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) u32 reg_val; int ret; + ret = pm_runtime_get_sync(domain->dev); + if (ret < 0) { + pm_runtime_put_noidle(domain->dev); + return ret; + } + if (!IS_ERR(domain->regulator)) { ret = regulator_enable(domain->regulator); if (ret) { dev_err(domain->dev, "failed to enable regulator\n"); - return ret; + goto out_put_pm; } } @@ -204,6 +211,8 @@ out_clk_disable: out_regulator_disable: if (!IS_ERR(domain->regulator)) regulator_disable(domain->regulator); +out_put_pm: + pm_runtime_put(domain->dev); return ret; } @@ -266,6 +275,8 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) } } + pm_runtime_put(domain->dev); + return 0; out_clk_disable: @@ -523,6 +534,8 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) return dev_err_probe(domain->dev, domain->num_clks, "Failed to get domain's clocks\n"); + pm_runtime_enable(domain->dev); + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, domain->bits.map, domain->bits.map); @@ -546,6 +559,7 @@ out_genpd_remove: out_domain_unmap: regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, domain->bits.map, 0); + pm_runtime_disable(domain->dev); return ret; } @@ -560,6 +574,8 @@ static int imx_pgc_domain_remove(struct platform_device *pdev) regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, domain->bits.map, 0); + pm_runtime_disable(domain->dev); + return 0; } -- cgit v1.2.3 From c0ce75395f8d088ba56dcec3218c628ef2bb6d73 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:39 +0800 Subject: soc: imx: gpcv2: allow domains without power-sequence control Some of the PGC domains only control the handshake with the ADB400 and don't have any power sequence controls. Make such domains work by allowing the pxx and map bits to be empty and skip all actions using those controls. Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Signed-off-by: Lucas Stach Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 89 +++++++++++++++++++++++++++---------------------- 1 file changed, 49 insertions(+), 40 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 800287abdbea..fdf759a7c865 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -163,24 +163,27 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) goto out_regulator_disable; } - /* request the domain to power up */ - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, - domain->bits.pxx, domain->bits.pxx); - /* - * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait - * for PUP_REQ/PDN_REQ bit to be cleared - */ - ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, - reg_val, !(reg_val & domain->bits.pxx), - 0, USEC_PER_MSEC); - if (ret) { - dev_err(domain->dev, "failed to command PGC\n"); - goto out_clk_disable; - } + if (domain->bits.pxx) { + /* request the domain to power up */ + regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, + domain->bits.pxx, domain->bits.pxx); + /* + * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait + * for PUP_REQ/PDN_REQ bit to be cleared + */ + ret = regmap_read_poll_timeout(domain->regmap, + GPC_PU_PGC_SW_PUP_REQ, reg_val, + !(reg_val & domain->bits.pxx), + 0, USEC_PER_MSEC); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto out_clk_disable; + } - /* disable power control */ - regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR); + /* disable power control */ + regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR); + } /* request the ADB400 to power up */ if (domain->bits.hskreq) { @@ -245,23 +248,26 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) } } - /* enable power control */ - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); - - /* request the domain to power down */ - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, - domain->bits.pxx, domain->bits.pxx); - /* - * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait - * for PUP_REQ/PDN_REQ bit to be cleared - */ - ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, - reg_val, !(reg_val & domain->bits.pxx), - 0, USEC_PER_MSEC); - if (ret) { - dev_err(domain->dev, "failed to command PGC\n"); - goto out_clk_disable; + if (domain->bits.pxx) { + /* enable power control */ + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + + /* request the domain to power down */ + regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, + domain->bits.pxx, domain->bits.pxx); + /* + * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait + * for PUP_REQ/PDN_REQ bit to be cleared + */ + ret = regmap_read_poll_timeout(domain->regmap, + GPC_PU_PGC_SW_PDN_REQ, reg_val, + !(reg_val & domain->bits.pxx), + 0, USEC_PER_MSEC); + if (ret) { + dev_err(domain->dev, "failed to command PGC\n"); + goto out_clk_disable; + } } /* Disable reset clocks for all devices in the domain */ @@ -536,8 +542,9 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) pm_runtime_enable(domain->dev); - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, domain->bits.map); + if (domain->bits.map) + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, domain->bits.map); ret = pm_genpd_init(&domain->genpd, NULL, true); if (ret) { @@ -557,8 +564,9 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) out_genpd_remove: pm_genpd_remove(&domain->genpd); out_domain_unmap: - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, 0); + if (domain->bits.map) + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); pm_runtime_disable(domain->dev); return ret; @@ -571,8 +579,9 @@ static int imx_pgc_domain_remove(struct platform_device *pdev) of_genpd_del_provider(domain->dev->of_node); pm_genpd_remove(&domain->genpd); - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, - domain->bits.map, 0); + if (domain->bits.map) + regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING, + domain->bits.map, 0); pm_runtime_disable(domain->dev); -- cgit v1.2.3 From fe58c887fb8ca25adab62fae20632d8423a00a91 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:41 +0800 Subject: soc: imx: gpcv2: add support for optional resets Normally the reset for the devices inside the power domain is triggered automatically from the PGC in the power-up sequencing, however on i.MX8MM this doesn't work for the GPU power domains. Add support for triggering the reset explicitly during the power up sequencing. Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Signed-off-by: Lucas Stach Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index fdf759a7c865..04ce64326c19 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -108,6 +109,7 @@ struct imx_pgc_domain { struct generic_pm_domain genpd; struct regmap *regmap; struct regulator *regulator; + struct reset_control *reset; struct clk_bulk_data *clks; int num_clks; @@ -163,6 +165,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) goto out_regulator_disable; } + reset_control_assert(domain->reset); + if (domain->bits.pxx) { /* request the domain to power up */ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, @@ -185,6 +189,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) GPC_PGC_CTRL_PCR); } + /* delay for reset to propagate */ + udelay(5); + + reset_control_deassert(domain->reset); + /* request the ADB400 to power up */ if (domain->bits.hskreq) { regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, @@ -540,6 +549,11 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) return dev_err_probe(domain->dev, domain->num_clks, "Failed to get domain's clocks\n"); + domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev); + if (IS_ERR(domain->reset)) + return dev_err_probe(domain->dev, PTR_ERR(domain->reset), + "Failed to get domain's resets\n"); + pm_runtime_enable(domain->dev); if (domain->bits.map) -- cgit v1.2.3 From eec220565b7852d017f936fbc18a7864d2179593 Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Sun, 23 May 2021 23:20:37 +0200 Subject: soc: qcom: socinfo: Add missing SoC ID for SM6125 Add SM6125 SoC ID to the soc_id struct Signed-off-by: Martin Botka Link: https://lore.kernel.org/r/20210523212038.736445-2-martin.botka@somainline.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index f6cfb79338f0..c52145e92f03 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -254,6 +254,7 @@ static const struct soc_id soc_id[] = { { 350, "SDA632" }, { 351, "SDA450" }, { 356, "SM8250" }, + { 394, "SM6125" }, { 402, "IPQ6018" }, { 425, "SC7180" }, { 455, "QRB5165" }, -- cgit v1.2.3 From e365257547ec789a8b54e7b33bbb9e0f5506de74 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 17 May 2021 14:00:34 +0200 Subject: soc: qcom: socinfo: Add remaining IPQ6018 family ID-s ID for IPQ6018 was previously added, but ID-s for rest of the family are missing. So, lets add those based on downstream driver. Signed-off-by: Robert Marko Reviewed-by: Kathiravan T Link: https://lore.kernel.org/r/20210517120034.3975027-1-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index c52145e92f03..6d38f4b603bd 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -256,7 +256,11 @@ static const struct soc_id soc_id[] = { { 356, "SM8250" }, { 394, "SM6125" }, { 402, "IPQ6018" }, + { 403, "IPQ6028" }, + { 421, "IPQ6000" }, + { 422, "IPQ6010" }, { 425, "SC7180" }, + { 453, "IPQ6005" }, { 455, "QRB5165" }, }; -- cgit v1.2.3 From 055c9aff76b776634b1ee50397d65f8fe1550c1a Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Sun, 23 May 2021 23:15:52 +0200 Subject: soc: qcom: smd-rpm: Add SM6125 compatible Add a compatible for SM6125 Signed-off-by: Martin Botka Link: https://lore.kernel.org/r/20210523211556.731976-1-martin.botka@somainline.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smd-rpm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index b93218cb50b5..53d0adb4d8c8 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -241,6 +241,7 @@ static const struct of_device_id qcom_smd_rpm_of_match[] = { { .compatible = "qcom,rpm-msm8996" }, { .compatible = "qcom,rpm-msm8998" }, { .compatible = "qcom,rpm-sdm660" }, + { .compatible = "qcom,rpm-sm6125" }, { .compatible = "qcom,rpm-qcs404" }, {} }; -- cgit v1.2.3 From 3b1a0582482c81682960aafe69c87660e4fdf3be Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 20 Jan 2021 14:50:37 -0800 Subject: soc: qcom: rpmhpd: Add SC8180X Add the power domains exposed by RPMH in the Qualcomm SC8180X platform. Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20210120225037.1611353-2-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmhpd.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index bb21c4f1c0c4..2daa17ba54a3 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -271,9 +271,30 @@ static const struct rpmhpd_desc sc7280_desc = { .num_pds = ARRAY_SIZE(sc7280_rpmhpds), }; +/* SC8180x RPMH powerdomains */ +static struct rpmhpd *sc8180x_rpmhpds[] = { + [SC8180X_CX] = &sdm845_cx, + [SC8180X_CX_AO] = &sdm845_cx_ao, + [SC8180X_EBI] = &sdm845_ebi, + [SC8180X_GFX] = &sdm845_gfx, + [SC8180X_LCX] = &sdm845_lcx, + [SC8180X_LMX] = &sdm845_lmx, + [SC8180X_MMCX] = &sm8150_mmcx, + [SC8180X_MMCX_AO] = &sm8150_mmcx_ao, + [SC8180X_MSS] = &sdm845_mss, + [SC8180X_MX] = &sdm845_mx, + [SC8180X_MX_AO] = &sdm845_mx_ao, +}; + +static const struct rpmhpd_desc sc8180x_desc = { + .rpmhpds = sc8180x_rpmhpds, + .num_pds = ARRAY_SIZE(sc8180x_rpmhpds), +}; + static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,sc7180-rpmhpd", .data = &sc7180_desc }, { .compatible = "qcom,sc7280-rpmhpd", .data = &sc7280_desc }, + { .compatible = "qcom,sc8180x-rpmhpd", .data = &sc8180x_desc }, { .compatible = "qcom,sdm845-rpmhpd", .data = &sdm845_desc }, { .compatible = "qcom,sdx55-rpmhpd", .data = &sdx55_desc}, { .compatible = "qcom,sm8150-rpmhpd", .data = &sm8150_desc }, -- cgit v1.2.3 From 9bf8257fefc9d14f589c2a933ba1193cc1912200 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 4 May 2021 22:36:13 +0200 Subject: soc: qcom: socinfo: Add more IDs Add the IDs for the following families of chips: 8064, 8226, 8610, 8625Q Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20210504203612.95056-1-luca@z3ntu.xyz Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 6d38f4b603bd..e3fc56c0f2cd 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -195,11 +195,30 @@ static const struct soc_id soc_id[] = { { 139, "APQ8060AB" }, { 140, "MSM8260AB" }, { 141, "MSM8660AB" }, + { 145, "MSM8626" }, + { 147, "MSM8610" }, + { 153, "APQ8064AB" }, + { 158, "MSM8226" }, + { 159, "MSM8526" }, + { 161, "MSM8110" }, + { 162, "MSM8210" }, + { 163, "MSM8810" }, + { 164, "MSM8212" }, + { 165, "MSM8612" }, + { 166, "MSM8112" }, + { 168, "MSM8225Q" }, + { 169, "MSM8625Q" }, + { 170, "MSM8125Q" }, + { 172, "APQ8064AA" }, { 178, "APQ8084" }, { 184, "APQ8074" }, { 185, "MSM8274" }, { 186, "MSM8674" }, { 194, "MSM8974PRO" }, + { 198, "MSM8126" }, + { 199, "APQ8026" }, + { 200, "MSM8926" }, + { 205, "MSM8326" }, { 206, "MSM8916" }, { 207, "MSM8994" }, { 208, "APQ8074-AA" }, @@ -213,6 +232,14 @@ static const struct soc_id soc_id[] = { { 216, "MSM8674PRO" }, { 217, "MSM8974-AA" }, { 218, "MSM8974-AB" }, + { 219, "APQ8028" }, + { 220, "MSM8128" }, + { 221, "MSM8228" }, + { 222, "MSM8528" }, + { 223, "MSM8628" }, + { 224, "MSM8928" }, + { 225, "MSM8510" }, + { 226, "MSM8512" }, { 233, "MSM8936" }, { 239, "MSM8939" }, { 240, "APQ8036" }, -- cgit v1.2.3 From 47f87c628055748ad509b2a580fb3135598f7a6d Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:43 +0800 Subject: soc: imx: gpcv2: add support for i.MX8MM power domains This adds support for the power domains found on i.MX8MM. The 2D and 3D GPU domains are abstracted as a single domain in the driver, as they can't be powered up/down individually due to a shared reset. Tested-by: Frieder Schrempf Reviewed-by: Frieder Schrempf Signed-off-by: Lucas Stach Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 168 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 04ce64326c19..d676e65e8c16 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -19,6 +19,7 @@ #include #include #include +#include #define GPC_LPCR_A_CORE_BSC 0x000 @@ -44,6 +45,19 @@ #define IMX8M_PCIE1_A53_DOMAIN BIT(3) #define IMX8M_MIPI_A53_DOMAIN BIT(2) +#define IMX8MM_VPUH1_A53_DOMAIN BIT(15) +#define IMX8MM_VPUG2_A53_DOMAIN BIT(14) +#define IMX8MM_VPUG1_A53_DOMAIN BIT(13) +#define IMX8MM_DISPMIX_A53_DOMAIN BIT(12) +#define IMX8MM_VPUMIX_A53_DOMAIN BIT(10) +#define IMX8MM_GPUMIX_A53_DOMAIN BIT(9) +#define IMX8MM_GPU_A53_DOMAIN (BIT(8) | BIT(11)) +#define IMX8MM_DDR1_A53_DOMAIN BIT(7) +#define IMX8MM_OTG2_A53_DOMAIN BIT(5) +#define IMX8MM_OTG1_A53_DOMAIN BIT(4) +#define IMX8MM_PCIE_A53_DOMAIN BIT(3) +#define IMX8MM_MIPI_A53_DOMAIN BIT(2) + #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 #define GPC_PU_PGC_SW_PDN_REQ 0x104 @@ -67,6 +81,19 @@ #define IMX8M_PCIE1_SW_Pxx_REQ BIT(1) #define IMX8M_MIPI_SW_Pxx_REQ BIT(0) +#define IMX8MM_VPUH1_SW_Pxx_REQ BIT(13) +#define IMX8MM_VPUG2_SW_Pxx_REQ BIT(12) +#define IMX8MM_VPUG1_SW_Pxx_REQ BIT(11) +#define IMX8MM_DISPMIX_SW_Pxx_REQ BIT(10) +#define IMX8MM_VPUMIX_SW_Pxx_REQ BIT(8) +#define IMX8MM_GPUMIX_SW_Pxx_REQ BIT(7) +#define IMX8MM_GPU_SW_Pxx_REQ (BIT(6) | BIT(9)) +#define IMX8MM_DDR1_SW_Pxx_REQ BIT(5) +#define IMX8MM_OTG2_SW_Pxx_REQ BIT(3) +#define IMX8MM_OTG1_SW_Pxx_REQ BIT(2) +#define IMX8MM_PCIE_SW_Pxx_REQ BIT(1) +#define IMX8MM_MIPI_SW_Pxx_REQ BIT(0) + #define GPC_M4_PU_PDN_FLG 0x1bc #define GPC_PU_PWRHSK 0x1fc @@ -78,6 +105,17 @@ #define IMX8M_VPU_HSK_PWRDNREQN BIT(5) #define IMX8M_DISP_HSK_PWRDNREQN BIT(4) + +#define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29) +#define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28)) +#define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26) +#define IMX8MM_DISPMIX_HSK_PWRDNACKN BIT(25) +#define IMX8MM_HSIO_HSK_PWRDNACKN (BIT(23) | BIT(24)) +#define IMX8MM_GPUMIX_HSK_PWRDNREQN BIT(11) +#define IMX8MM_GPU_HSK_PWRDNREQN (BIT(9) | BIT(10)) +#define IMX8MM_VPUMIX_HSK_PWRDNREQN BIT(8) +#define IMX8MM_DISPMIX_HSK_PWRDNREQN BIT(7) +#define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6)) /* * The PGC offset values in Reference Manual * (Rev. 1, 01/2018 and the older ones) GPC chapter's @@ -100,6 +138,20 @@ #define IMX8M_PGC_MIPI_CSI2 28 #define IMX8M_PGC_PCIE2 29 +#define IMX8MM_PGC_MIPI 16 +#define IMX8MM_PGC_PCIE 17 +#define IMX8MM_PGC_OTG1 18 +#define IMX8MM_PGC_OTG2 19 +#define IMX8MM_PGC_DDR1 21 +#define IMX8MM_PGC_GPU2D 22 +#define IMX8MM_PGC_GPUMIX 23 +#define IMX8MM_PGC_VPUMIX 24 +#define IMX8MM_PGC_GPU3D 25 +#define IMX8MM_PGC_DISPMIX 26 +#define IMX8MM_PGC_VPUG1 27 +#define IMX8MM_PGC_VPUG2 28 +#define IMX8MM_PGC_VPUH1 29 + #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) @@ -527,6 +579,121 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = { .reg_access_table = &imx8m_access_table, }; +static const struct imx_pgc_domain imx8mm_pgc_domains[] = { + [IMX8MM_POWER_DOMAIN_HSIOMIX] = { + .genpd = { + .name = "hsiomix", + }, + .bits = { + .pxx = 0, /* no power sequence control */ + .map = 0, /* no power sequence control */ + .hskreq = IMX8MM_HSIO_HSK_PWRDNREQN, + .hskack = IMX8MM_HSIO_HSK_PWRDNACKN, + }, + }, + + [IMX8MM_POWER_DOMAIN_PCIE] = { + .genpd = { + .name = "pcie", + }, + .bits = { + .pxx = IMX8MM_PCIE_SW_Pxx_REQ, + .map = IMX8MM_PCIE_A53_DOMAIN, + }, + .pgc = IMX8MM_PGC_PCIE, + }, + + [IMX8MM_POWER_DOMAIN_OTG1] = { + .genpd = { + .name = "usb-otg1", + }, + .bits = { + .pxx = IMX8MM_OTG1_SW_Pxx_REQ, + .map = IMX8MM_OTG1_A53_DOMAIN, + }, + .pgc = IMX8MM_PGC_OTG1, + }, + + [IMX8MM_POWER_DOMAIN_OTG2] = { + .genpd = { + .name = "usb-otg2", + }, + .bits = { + .pxx = IMX8MM_OTG2_SW_Pxx_REQ, + .map = IMX8MM_OTG2_A53_DOMAIN, + }, + .pgc = IMX8MM_PGC_OTG2, + }, + + [IMX8MM_POWER_DOMAIN_GPUMIX] = { + .genpd = { + .name = "gpumix", + }, + .bits = { + .pxx = IMX8MM_GPUMIX_SW_Pxx_REQ, + .map = IMX8MM_GPUMIX_A53_DOMAIN, + .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN, + .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN, + }, + .pgc = IMX8MM_PGC_GPUMIX, + }, + + [IMX8MM_POWER_DOMAIN_GPU] = { + .genpd = { + .name = "gpu", + }, + .bits = { + .pxx = IMX8MM_GPU_SW_Pxx_REQ, + .map = IMX8MM_GPU_A53_DOMAIN, + .hskreq = IMX8MM_GPU_HSK_PWRDNREQN, + .hskack = IMX8MM_GPU_HSK_PWRDNACKN, + }, + .pgc = IMX8MM_PGC_GPU2D, + }, +}; + +static const struct regmap_range imx8mm_yes_ranges[] = { + regmap_reg_range(GPC_LPCR_A_CORE_BSC, + GPC_PU_PWRHSK), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_MIPI), + GPC_PGC_SR(IMX8MM_PGC_MIPI)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_PCIE), + GPC_PGC_SR(IMX8MM_PGC_PCIE)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG1), + GPC_PGC_SR(IMX8MM_PGC_OTG1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_OTG2), + GPC_PGC_SR(IMX8MM_PGC_OTG2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DDR1), + GPC_PGC_SR(IMX8MM_PGC_DDR1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU2D), + GPC_PGC_SR(IMX8MM_PGC_GPU2D)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPUMIX), + GPC_PGC_SR(IMX8MM_PGC_GPUMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUMIX), + GPC_PGC_SR(IMX8MM_PGC_VPUMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_GPU3D), + GPC_PGC_SR(IMX8MM_PGC_GPU3D)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_DISPMIX), + GPC_PGC_SR(IMX8MM_PGC_DISPMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG1), + GPC_PGC_SR(IMX8MM_PGC_VPUG1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUG2), + GPC_PGC_SR(IMX8MM_PGC_VPUG2)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MM_PGC_VPUH1), + GPC_PGC_SR(IMX8MM_PGC_VPUH1)), +}; + +static const struct regmap_access_table imx8mm_access_table = { + .yes_ranges = imx8mm_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(imx8mm_yes_ranges), +}; + +static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = { + .domains = imx8mm_pgc_domains, + .domains_num = ARRAY_SIZE(imx8mm_pgc_domains), + .reg_access_table = &imx8mm_access_table, +}; + static int imx_pgc_domain_probe(struct platform_device *pdev) { struct imx_pgc_domain *domain = pdev->dev.platform_data; @@ -710,6 +877,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) static const struct of_device_id imx_gpcv2_dt_ids[] = { { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, }, + { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, }, { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, }, { } }; -- cgit v1.2.3 From a36cc1e512e9b9152a340e34d4d7b6dd7f31de3f Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Mon, 10 May 2021 12:00:44 +0800 Subject: soc: imx: gpcv2: Add support for missing i.MX8MM VPU/DISPMIX power domains With the BLK-CTL driver now in place, let's add the missing domains. Tested-by: Frieder Schrempf Signed-off-by: Lucas Stach Signed-off-by: Frieder Schrempf Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index d676e65e8c16..2490757f759d 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -650,6 +650,76 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { }, .pgc = IMX8MM_PGC_GPU2D, }, + + [IMX8MM_POWER_DOMAIN_VPUMIX] = { + .genpd = { + .name = "vpumix", + }, + .bits = { + .pxx = IMX8MM_VPUMIX_SW_Pxx_REQ, + .map = IMX8MM_VPUMIX_A53_DOMAIN, + .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN, + .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN, + }, + .pgc = IMX8MM_PGC_VPUMIX, + }, + + [IMX8MM_POWER_DOMAIN_VPUG1] = { + .genpd = { + .name = "vpu-g1", + }, + .bits = { + .pxx = IMX8MM_VPUG1_SW_Pxx_REQ, + .map = IMX8MM_VPUG1_A53_DOMAIN, + }, + .pgc = IMX8MM_PGC_VPUG1, + }, + + [IMX8MM_POWER_DOMAIN_VPUG2] = { + .genpd = { + .name = "vpu-g2", + }, + .bits = { + .pxx = IMX8MM_VPUG2_SW_Pxx_REQ, + .map = IMX8MM_VPUG2_A53_DOMAIN, + }, + .pgc = IMX8MM_PGC_VPUG2, + }, + + [IMX8MM_POWER_DOMAIN_VPUH1] = { + .genpd = { + .name = "vpu-h1", + }, + .bits = { + .pxx = IMX8MM_VPUH1_SW_Pxx_REQ, + .map = IMX8MM_VPUH1_A53_DOMAIN, + }, + .pgc = IMX8MM_PGC_VPUH1, + }, + + [IMX8MM_POWER_DOMAIN_DISPMIX] = { + .genpd = { + .name = "dispmix", + }, + .bits = { + .pxx = IMX8MM_DISPMIX_SW_Pxx_REQ, + .map = IMX8MM_DISPMIX_A53_DOMAIN, + .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN, + .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN, + }, + .pgc = IMX8MM_PGC_DISPMIX, + }, + + [IMX8MM_POWER_DOMAIN_MIPI] = { + .genpd = { + .name = "mipi", + }, + .bits = { + .pxx = IMX8MM_MIPI_SW_Pxx_REQ, + .map = IMX8MM_MIPI_A53_DOMAIN, + }, + .pgc = IMX8MM_PGC_MIPI, + }, }; static const struct regmap_range imx8mm_yes_ranges[] = { -- cgit v1.2.3 From acad945dc22efb867c0a1fa5911361bc746ec05a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 10 May 2021 12:00:45 +0800 Subject: soc: imx: gpcv2: move reset assert after requesting domain power up The i.MX8MM VPU power up sequence is a bit special, it must follow: 1. request power up 2. reset assert 3. reset deassert This change in this patch will not affect other domains, because the power domain default is in asserted state, unless bootloader deassert the reset. It also applies to GPU power domain. Reviewed-by: Frieder Schrempf Tested-by: Frieder Schrempf Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 2490757f759d..35bbb1bc5159 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -217,8 +217,6 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) goto out_regulator_disable; } - reset_control_assert(domain->reset); - if (domain->bits.pxx) { /* request the domain to power up */ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, @@ -241,6 +239,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) GPC_PGC_CTRL_PCR); } + reset_control_assert(domain->reset); + /* delay for reset to propagate */ udelay(5); -- cgit v1.2.3 From 7fda2b0bfbd98e554be9dbbdf930c34674438c85 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 26 May 2021 22:08:43 +0200 Subject: soc: qcom: socinfo: import PMIC IDs from pmic-spmi The driver in drivers/mfd/qcom-spmi-pmic.c has a more complete and more up-to-date list of PMICs with the respective IDs. Use those names for socinfo. Some IDs seem to have been assigned to multiple PMICs so keep that in the name as well. Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20210526200843.127916-1-luca@z3ntu.xyz Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index e3fc56c0f2cd..b2f049faa3df 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -70,21 +70,33 @@ static const char *const socinfo_image_names[] = { static const char *const pmic_models[] = { [0] = "Unknown PMIC model", + [1] = "PM8941", + [2] = "PM8841", + [3] = "PM8019", + [4] = "PM8226", + [5] = "PM8110", + [6] = "PMA8084", + [7] = "PMI8962", + [8] = "PMD9635", [9] = "PM8994", + [10] = "PMI8994", [11] = "PM8916", - [13] = "PM8058", + [12] = "PM8004", + [13] = "PM8909/PM8058", [14] = "PM8028", [15] = "PM8901", - [16] = "PM8027", - [17] = "ISL9519", + [16] = "PM8950/PM8027", + [17] = "PMI8950/ISL9519", [18] = "PM8921", [19] = "PM8018", - [20] = "PM8015", - [21] = "PM8014", + [20] = "PM8998/PM8015", + [21] = "PMI8998/PM8014", [22] = "PM8821", [23] = "PM8038", - [24] = "PM8922", + [24] = "PM8005/PM8922", [25] = "PM8917", + [26] = "PM660L", + [27] = "PM660", [30] = "PM8150", [31] = "PM8150L", [32] = "PM8150B", -- cgit v1.2.3 From e93e6bef7930cc23b878b6768f617c479f1a5c50 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 17 May 2021 22:21:15 +0200 Subject: soc: amlogic: meson-ee-pwrc: Rename "get_power" to "is_powered_off" The name "get_power" is used within the Meson EE power controller driver to indicate whether a power domain is turned on or off. With the original "get_power" naming the result was: - true = powered off - false = powered on Rename "get_power" to "is_powered_off" to make the naming consistent with the third argument to pm_genpd_init. Also this naming is easier to understand when reading the code without looking at the implementation of "get_power". Signed-off-by: Martin Blumenstingl Reviewed-by: Kevin Hilman Link: https://lore.kernel.org/r/20210517202115.1004065-1-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong --- drivers/soc/amlogic/meson-ee-pwrc.c | 46 ++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 23 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c index 50bf5d2b828b..2be3afe6c2e3 100644 --- a/drivers/soc/amlogic/meson-ee-pwrc.c +++ b/drivers/soc/amlogic/meson-ee-pwrc.c @@ -68,7 +68,7 @@ struct meson_ee_pwrc_domain_desc { struct meson_ee_pwrc_top_domain *top_pd; unsigned int mem_pd_count; struct meson_ee_pwrc_mem_domain *mem_pd; - bool (*get_power)(struct meson_ee_pwrc_domain *pwrc_domain); + bool (*is_powered_off)(struct meson_ee_pwrc_domain *pwrc_domain); }; struct meson_ee_pwrc_domain_data { @@ -217,7 +217,7 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) }, }; -#define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks) \ +#define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \ { \ .name = __name, \ .reset_names_count = __resets, \ @@ -225,46 +225,46 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = { .top_pd = __top_pd, \ .mem_pd_count = ARRAY_SIZE(__mem), \ .mem_pd = __mem, \ - .get_power = __get_power, \ + .is_powered_off = __is_pwr_off, \ } -#define TOP_PD(__name, __top_pd, __mem, __get_power) \ +#define TOP_PD(__name, __top_pd, __mem, __is_pwr_off) \ { \ .name = __name, \ .top_pd = __top_pd, \ .mem_pd_count = ARRAY_SIZE(__mem), \ .mem_pd = __mem, \ - .get_power = __get_power, \ + .is_powered_off = __is_pwr_off, \ } #define MEM_PD(__name, __mem) \ TOP_PD(__name, NULL, __mem, NULL) -static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain); +static bool pwrc_ee_is_powered_off(struct meson_ee_pwrc_domain *pwrc_domain); static struct meson_ee_pwrc_domain_desc axg_pwrc_domains[] = { [PWRC_AXG_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, axg_pwrc_mem_vpu, - pwrc_ee_get_power, 5, 2), + pwrc_ee_is_powered_off, 5, 2), [PWRC_AXG_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), [PWRC_AXG_AUDIO_ID] = MEM_PD("AUDIO", axg_pwrc_mem_audio), }; static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = { [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu, - pwrc_ee_get_power, 11, 2), + pwrc_ee_is_powered_off, 11, 2), [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), }; static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = { [PWRC_GXBB_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, gxbb_pwrc_mem_vpu, - pwrc_ee_get_power, 12, 2), + pwrc_ee_is_powered_off, 12, 2), [PWRC_GXBB_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), }; static struct meson_ee_pwrc_domain_desc meson8_pwrc_domains[] = { [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu, - meson8_pwrc_mem_vpu, pwrc_ee_get_power, - 0, 1), + meson8_pwrc_mem_vpu, + pwrc_ee_is_powered_off, 0, 1), [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM", meson_pwrc_mem_eth), [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM", @@ -273,8 +273,8 @@ static struct meson_ee_pwrc_domain_desc meson8_pwrc_domains[] = { static struct meson_ee_pwrc_domain_desc meson8b_pwrc_domains[] = { [PWRC_MESON8_VPU_ID] = VPU_PD("VPU", &meson8_pwrc_vpu, - meson8_pwrc_mem_vpu, pwrc_ee_get_power, - 11, 1), + meson8_pwrc_mem_vpu, + pwrc_ee_is_powered_off, 11, 1), [PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM", meson_pwrc_mem_eth), [PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM", @@ -283,15 +283,15 @@ static struct meson_ee_pwrc_domain_desc meson8b_pwrc_domains[] = { static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = { [PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu, - pwrc_ee_get_power, 11, 2), + pwrc_ee_is_powered_off, 11, 2), [PWRC_SM1_NNA_ID] = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna, - pwrc_ee_get_power), + pwrc_ee_is_powered_off), [PWRC_SM1_USB_ID] = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb, - pwrc_ee_get_power), + pwrc_ee_is_powered_off), [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie, - pwrc_ee_get_power), + pwrc_ee_is_powered_off), [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d, - pwrc_ee_get_power), + pwrc_ee_is_powered_off), [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio), [PWRC_SM1_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth), }; @@ -314,7 +314,7 @@ struct meson_ee_pwrc { struct genpd_onecell_data xlate; }; -static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain) +static bool pwrc_ee_is_powered_off(struct meson_ee_pwrc_domain *pwrc_domain) { u32 reg; @@ -445,7 +445,7 @@ static int meson_ee_pwrc_init_domain(struct platform_device *pdev, * we need to power the domain off, otherwise the internal clocks * prepare/enable counters won't be in sync. */ - if (dom->num_clks && dom->desc.get_power && !dom->desc.get_power(dom)) { + if (dom->num_clks && dom->desc.is_powered_off && !dom->desc.is_powered_off(dom)) { ret = clk_bulk_prepare_enable(dom->num_clks, dom->clks); if (ret) return ret; @@ -456,8 +456,8 @@ static int meson_ee_pwrc_init_domain(struct platform_device *pdev, return ret; } else { ret = pm_genpd_init(&dom->base, NULL, - (dom->desc.get_power ? - dom->desc.get_power(dom) : true)); + (dom->desc.is_powered_off ? + dom->desc.is_powered_off(dom) : true)); if (ret) return ret; } @@ -536,7 +536,7 @@ static void meson_ee_pwrc_shutdown(struct platform_device *pdev) for (i = 0 ; i < pwrc->xlate.num_domains ; ++i) { struct meson_ee_pwrc_domain *dom = &pwrc->domains[i]; - if (dom->desc.get_power && !dom->desc.get_power(dom)) + if (dom->desc.is_powered_off && !dom->desc.is_powered_off(dom)) meson_ee_pwrc_off(&dom->base); } } -- cgit v1.2.3 From d8ea59e7e3d166098e6ecb81f84e7f4c5760325c Mon Sep 17 00:00:00 2001 From: Bartosz Dudziak Date: Sun, 2 May 2021 14:20:25 +0200 Subject: soc: qcom: smd-rpm: Add MSM8226 compatible Add a compatible for the RPM on the Qualcomm MSM8226 platform. Signed-off-by: Bartosz Dudziak Link: https://lore.kernel.org/r/20210502122027.9351-3-bartosz.dudziak@snejp.pl Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smd-rpm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index 53d0adb4d8c8..bc0be1d4be5f 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -233,6 +233,7 @@ static void qcom_smd_rpm_remove(struct rpmsg_device *rpdev) static const struct of_device_id qcom_smd_rpm_of_match[] = { { .compatible = "qcom,rpm-apq8084" }, { .compatible = "qcom,rpm-ipq6018" }, + { .compatible = "qcom,rpm-msm8226" }, { .compatible = "qcom,rpm-msm8916" }, { .compatible = "qcom,rpm-msm8936" }, { .compatible = "qcom,rpm-msm8974" }, -- cgit v1.2.3 From eed6ff1bb2da65067d928f4ab322c7d75f944fa4 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Tue, 1 Jun 2021 11:59:04 +0800 Subject: soc: mtk-pm-domains: do not register smi node as syscon Mediatek requires mmsys clocks to be unprepared during suspend, otherwise system has chances to hang. syscon_regmap_lookup_by_phandle_optional() will attach and prepare the first clock in smi node, leading to additional prepare to the clock which is not balanced with the prepare/unprepare pair in resume/suspend callbacks. If a power domain node requests an smi node and the smi node's first clock is an mmsys clock, it will results in an unstable suspend resume. Fixes: f414854c8843 ("soc: mediatek: pm-domains: Add SMI block as bus protection block") Signed-off-by: Hsin-Yi Wang Reviewed-by: chun-jie.chen Reviewed-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20210601035905.2970384-2-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pm-domains.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 0af00efa0ef8..22fa52f0e86e 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -297,6 +297,7 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no const struct scpsys_domain_data *domain_data; struct scpsys_domain *pd; struct device_node *root_node = scpsys->dev->of_node; + struct device_node *smi_node; struct property *prop; const char *clk_name; int i, ret, num_clks; @@ -352,9 +353,13 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no if (IS_ERR(pd->infracfg)) return ERR_CAST(pd->infracfg); - pd->smi = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,smi"); - if (IS_ERR(pd->smi)) - return ERR_CAST(pd->smi); + smi_node = of_parse_phandle(node, "mediatek,smi", 0); + if (smi_node) { + pd->smi = device_node_to_regmap(smi_node); + of_node_put(smi_node); + if (IS_ERR(pd->smi)) + return ERR_CAST(pd->smi); + } num_clks = of_clk_get_parent_count(node); if (num_clks > 0) { -- cgit v1.2.3 From f0fce06e345dc4f75c1cdd21840780f5fe2df1f3 Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Tue, 1 Jun 2021 11:59:03 +0800 Subject: soc: mtk-pm-domains: Fix the clock prepared issue In this new power domain driver, when adding one power domain it will prepare the dependent clocks at the same. So we only do clk_bulk_enable/disable control during power ON/OFF. When system suspend, the pm runtime framework will forcely power off power domains. However, the dependent clocks are disabled but kept prepared. In MediaTek clock drivers, PLL would be turned ON when we do clk_bulk_prepare control. Clock hierarchy: PLL --> DIV_CK --> CLK_MUX (may be dependent clocks) --> SUBSYS_CG (may be dependent clocks) It will lead some unexpected clock states during system suspend. This patch will fix by doing prepare_enable/disable_unprepare on dependent clocks at the same time while we are going to power on/off any power domain. Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains") Signed-off-by: Weiyi Lu Signed-off-by: Hsin-Yi Wang Reviewed-by: chun-jie.chen Reviewed-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20210601035905.2970384-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pm-domains.c | 31 ++++++++----------------------- 1 file changed, 8 insertions(+), 23 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 22fa52f0e86e..b762bc40f56b 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -211,7 +211,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) if (ret) return ret; - ret = clk_bulk_enable(pd->num_clks, pd->clks); + ret = clk_bulk_prepare_enable(pd->num_clks, pd->clks); if (ret) goto err_reg; @@ -229,7 +229,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); - ret = clk_bulk_enable(pd->num_subsys_clks, pd->subsys_clks); + ret = clk_bulk_prepare_enable(pd->num_subsys_clks, pd->subsys_clks); if (ret) goto err_pwr_ack; @@ -246,9 +246,9 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) err_disable_sram: scpsys_sram_disable(pd); err_disable_subsys_clks: - clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks); + clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); err_pwr_ack: - clk_bulk_disable(pd->num_clks, pd->clks); + clk_bulk_disable_unprepare(pd->num_clks, pd->clks); err_reg: scpsys_regulator_disable(pd->supply); return ret; @@ -269,7 +269,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) if (ret < 0) return ret; - clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks); + clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks); /* subsys power off */ regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); @@ -284,7 +284,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) if (ret < 0) return ret; - clk_bulk_disable(pd->num_clks, pd->clks); + clk_bulk_disable_unprepare(pd->num_clks, pd->clks); scpsys_regulator_disable(pd->supply); @@ -410,14 +410,6 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no pd->subsys_clks[i].clk = clk; } - ret = clk_bulk_prepare(pd->num_clks, pd->clks); - if (ret) - goto err_put_subsys_clocks; - - ret = clk_bulk_prepare(pd->num_subsys_clks, pd->subsys_clks); - if (ret) - goto err_unprepare_clocks; - /* * Initially turn on all domains to make the domains usable * with !CONFIG_PM and to get the hardware in sync with the @@ -432,7 +424,7 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no ret = scpsys_power_on(&pd->genpd); if (ret < 0) { dev_err(scpsys->dev, "%pOF: failed to power on domain: %d\n", node, ret); - goto err_unprepare_clocks; + goto err_put_subsys_clocks; } } @@ -440,7 +432,7 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no ret = -EINVAL; dev_err(scpsys->dev, "power domain with id %d already exists, check your device-tree\n", id); - goto err_unprepare_subsys_clocks; + goto err_put_subsys_clocks; } if (!pd->data->name) @@ -460,10 +452,6 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no return scpsys->pd_data.domains[id]; -err_unprepare_subsys_clocks: - clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks); -err_unprepare_clocks: - clk_bulk_unprepare(pd->num_clks, pd->clks); err_put_subsys_clocks: clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks); err_put_clocks: @@ -542,10 +530,7 @@ static void scpsys_remove_one_domain(struct scpsys_domain *pd) "failed to remove domain '%s' : %d - state may be inconsistent\n", pd->genpd.name, ret); - clk_bulk_unprepare(pd->num_clks, pd->clks); clk_bulk_put(pd->num_clks, pd->clks); - - clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks); clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks); } -- cgit v1.2.3 From e88edc977b00cc467d598e4ea5091b8bb4a7f78d Mon Sep 17 00:00:00 2001 From: Henry Chen Date: Wed, 2 Jun 2021 19:20:50 +0800 Subject: soc: mediatek: pwrap: add pwrap driver for MT8195 SoC MT8195 are highly integrated SoC and use PMIC_MT6359 for power management. This patch adds pwrap master driver to access PMIC_MT6359. Signed-off-by: Henry Chen Link: https://lore.kernel.org/r/20210602112050.12338-3-james.lo@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pmic-wrap.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index e4de75f35c33..952bc554f443 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -961,6 +961,23 @@ static int mt8183_regs[] = { [PWRAP_WACS2_VLDCLR] = 0xC28, }; +static int mt8195_regs[] = { + [PWRAP_INIT_DONE2] = 0x0, + [PWRAP_STAUPD_CTRL] = 0x4C, + [PWRAP_TIMER_EN] = 0x3E4, + [PWRAP_INT_EN] = 0x420, + [PWRAP_INT_FLG] = 0x428, + [PWRAP_INT_CLR] = 0x42C, + [PWRAP_INT1_EN] = 0x450, + [PWRAP_INT1_FLG] = 0x458, + [PWRAP_INT1_CLR] = 0x45C, + [PWRAP_WACS2_CMD] = 0x880, + [PWRAP_SWINF_2_WDATA_31_0] = 0x884, + [PWRAP_SWINF_2_RDATA_31_0] = 0x894, + [PWRAP_WACS2_VLDCLR] = 0x8A4, + [PWRAP_WACS2_RDATA] = 0x8A8, +}; + static int mt8516_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -1066,6 +1083,7 @@ enum pwrap_type { PWRAP_MT8135, PWRAP_MT8173, PWRAP_MT8183, + PWRAP_MT8195, PWRAP_MT8516, }; @@ -1525,6 +1543,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) break; case PWRAP_MT6873: case PWRAP_MT8183: + case PWRAP_MT8195: break; } @@ -2025,6 +2044,19 @@ static const struct pmic_wrapper_type pwrap_mt8183 = { .init_soc_specific = pwrap_mt8183_init_soc_specific, }; +static struct pmic_wrapper_type pwrap_mt8195 = { + .regs = mt8195_regs, + .type = PWRAP_MT8195, + .arb_en_all = 0x777f, /* NEED CONFIRM */ + .int_en_all = 0x180000, /* NEED CONFIRM */ + .int1_en_all = 0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = NULL, +}; + static struct pmic_wrapper_type pwrap_mt8516 = { .regs = mt8516_regs, .type = PWRAP_MT8516, @@ -2065,6 +2097,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = { }, { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183, + }, { + .compatible = "mediatek,mt8195-pwrap", + .data = &pwrap_mt8195, }, { .compatible = "mediatek,mt8516-pwrap", .data = &pwrap_mt8516, -- cgit v1.2.3 From a9c7d88d23ad244ba45397d7ba792d4ddf9643bf Mon Sep 17 00:00:00 2001 From: Qiheng Lin Date: Fri, 4 Jun 2021 13:04:06 -0700 Subject: PM: AVS: remove redundant dev_err call in omap_sr_probe() There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Reported-by: Hulk Robot Reviewed-by: Nishanth Menon Signed-off-by: Qiheng Lin Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/smartreflex.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/ti/smartreflex.c b/drivers/soc/ti/smartreflex.c index 5376f3d22f31..06cbee5fd254 100644 --- a/drivers/soc/ti/smartreflex.c +++ b/drivers/soc/ti/smartreflex.c @@ -846,10 +846,8 @@ static int omap_sr_probe(struct platform_device *pdev) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); sr_info->base = devm_ioremap_resource(&pdev->dev, mem); - if (IS_ERR(sr_info->base)) { - dev_err(&pdev->dev, "%s: ioremap fail\n", __func__); + if (IS_ERR(sr_info->base)) return PTR_ERR(sr_info->base); - } irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -- cgit v1.2.3 From 536e23c607edf0e13092887b92e0d5c7d29462b4 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Fri, 4 Jun 2021 13:04:13 -0700 Subject: soc: ti: wkup_m3_ipc: Remove redundant error printing in wkup_m3_ipc_probe() When devm_ioremap_resource() fails, a clear enough error message will be printed by its subfunction __devm_ioremap_resource(). The error information contains the device name, failure cause, and possibly resource information. Therefore, remove the error printing here to simplify code and reduce the binary size. Reported-by: Hulk Robot Signed-off-by: Zhen Lei Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/wkup_m3_ipc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index c3e2161df732..09abd17065ba 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -445,10 +445,8 @@ static int wkup_m3_ipc_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); m3_ipc->ipc_mem_base = devm_ioremap_resource(dev, res); - if (IS_ERR(m3_ipc->ipc_mem_base)) { - dev_err(dev, "could not ioremap ipc_mem\n"); + if (IS_ERR(m3_ipc->ipc_mem_base)) return PTR_ERR(m3_ipc->ipc_mem_base); - } irq = platform_get_irq(pdev, 0); if (!irq) { -- cgit v1.2.3 From f3b154529fb89e9feae18d5e9da40559172d8d19 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 9 Jun 2021 16:32:23 +0100 Subject: soc: renesas: Add ARCH_R9A07G044 for the new RZ/G2L SoC's Add ARCH_R9A07G044 as a configuration symbol for the new Renesas RZ/G2L SoC variants. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20210609153230.6967-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index b70bbc38efc6..71b44c31b012 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -279,6 +279,11 @@ config ARCH_R8A774B1 help This enables support for the Renesas RZ/G2N SoC. +config ARCH_R9A07G044 + bool "ARM64 Platform support for RZ/G2L" + help + This enables support for the Renesas RZ/G2L SoC variants. + endif # ARM64 config RST_RCAR -- cgit v1.2.3 From 187cd57db09355fd169c661fa1c44bda06b013e8 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 9 Jun 2021 17:37:16 +0100 Subject: soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's Add support for reading the LSI DEVID register which is present in SYSC block of RZ/G2{L,LC} SoC's. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20210609163717.3083-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/renesas-soc.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 0f8eff4a641a..8310fce7714e 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -56,6 +56,10 @@ static const struct renesas_family fam_rzg2 __initconst __maybe_unused = { .reg = 0xfff00044, /* PRR (Product Register) */ }; +static const struct renesas_family fam_rzg2l __initconst __maybe_unused = { + .name = "RZ/G2L", +}; + static const struct renesas_family fam_shmobile __initconst __maybe_unused = { .name = "SH-Mobile", .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */ @@ -64,7 +68,7 @@ static const struct renesas_family fam_shmobile __initconst __maybe_unused = { struct renesas_soc { const struct renesas_family *family; - u8 id; + u32 id; }; static const struct renesas_soc soc_rz_a1h __initconst __maybe_unused = { @@ -131,6 +135,11 @@ static const struct renesas_soc soc_rz_g2h __initconst __maybe_unused = { .id = 0x4f, }; +static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = { + .family = &fam_rzg2l, + .id = 0x841c447, +}; + static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = { .family = &fam_rcar_gen1, }; @@ -299,6 +308,9 @@ static const struct of_device_id renesas_socs[] __initconst = { #ifdef CONFIG_ARCH_R8A779A0 { .compatible = "renesas,r8a779a0", .data = &soc_rcar_v3u }, #endif +#if defined(CONFIG_ARCH_R9A07G044) + { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l }, +#endif #ifdef CONFIG_ARCH_SH73A0 { .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 }, #endif @@ -348,6 +360,25 @@ static int __init renesas_soc_init(void) goto done; } + np = of_find_compatible_node(NULL, NULL, "renesas,r9a07g044-sysc"); + if (np) { + chipid = of_iomap(np, 0); + of_node_put(np); + + if (chipid) { + product = readl(chipid + 0x0a04); + iounmap(chipid); + + if (soc->id && (product & 0xfffffff) != soc->id) { + pr_warn("SoC mismatch (product = 0x%x)\n", + product); + return -ENODEV; + } + } + + goto done; + } + /* Try PRR first, then hardcoded fallback */ np = of_find_compatible_node(NULL, NULL, "renesas,prr"); if (np) { -- cgit v1.2.3 From af32011f76b759d68a6e3005d450ef7b82e1479a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 31 Jan 2021 02:32:32 +0100 Subject: soc: qcom: rpmpd: Add MDM9607 RPM Power Domains This SoC while being from 8916 era, makes use of the newer-style, floor-level management, instead of the older floor-corner. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210131013233.54666-1-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/power/qcom,rpmpd.yaml | 1 + drivers/soc/qcom/rpmpd.c | 22 ++++++++++++++++++++++ include/dt-bindings/power/qcom-rpmpd.h | 8 ++++++++ 3 files changed, 31 insertions(+) (limited to 'drivers/soc') diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index c01bb5f0d6ea..4807b560f00d 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,mdm9607-rpmpd - qcom,msm8916-rpmpd - qcom,msm8939-rpmpd - qcom,msm8976-rpmpd diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 27733b0e7fca..0b532a892d60 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -118,6 +118,27 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); +/* mdm9607 RPM Power Domains */ +DEFINE_RPMPD_PAIR(mdm9607, vddcx, vddcx_ao, SMPA, LEVEL, 3); +DEFINE_RPMPD_VFL(mdm9607, vddcx_vfl, SMPA, 3); + +DEFINE_RPMPD_PAIR(mdm9607, vddmx, vddmx_ao, LDOA, LEVEL, 12); +DEFINE_RPMPD_VFL(mdm9607, vddmx_vfl, LDOA, 12); +static struct rpmpd *mdm9607_rpmpds[] = { + [MDM9607_VDDCX] = &mdm9607_vddcx, + [MDM9607_VDDCX_AO] = &mdm9607_vddcx_ao, + [MDM9607_VDDCX_VFL] = &mdm9607_vddcx_vfl, + [MDM9607_VDDMX] = &mdm9607_vddmx, + [MDM9607_VDDMX_AO] = &mdm9607_vddmx_ao, + [MDM9607_VDDMX_VFL] = &mdm9607_vddmx_vfl, +}; + +static const struct rpmpd_desc mdm9607_desc = { + .rpmpds = mdm9607_rpmpds, + .num_pds = ARRAY_SIZE(mdm9607_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO, +}; + /* msm8939 RPM Power Domains */ DEFINE_RPMPD_PAIR(msm8939, vddmd, vddmd_ao, SMPA, CORNER, 1); DEFINE_RPMPD_VFC(msm8939, vddmd_vfc, SMPA, 1); @@ -326,6 +347,7 @@ static const struct rpmpd_desc sdm660_desc = { }; static const struct of_device_id rpmpd_match_table[] = { + { .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc }, { .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc }, { .compatible = "qcom,msm8939-rpmpd", .data = &msm8939_desc }, { .compatible = "qcom,msm8976-rpmpd", .data = &msm8976_desc }, diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 93c134f3724d..8b5708bb9671 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -108,6 +108,14 @@ #define RPMH_REGULATOR_LEVEL_TURBO 384 #define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +/* MDM9607 Power Domains */ +#define MDM9607_VDDCX 0 +#define MDM9607_VDDCX_AO 1 +#define MDM9607_VDDCX_VFL 2 +#define MDM9607_VDDMX 3 +#define MDM9607_VDDMX_AO 4 +#define MDM9607_VDDMX_VFL 5 + /* MSM8939 Power Domains */ #define MSM8939_VDDMDCX 0 #define MSM8939_VDDMDCX_AO 1 -- cgit v1.2.3 From 2a53b9d47b13ae8816ce5a7e5adeb77009d2ca4d Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 24 May 2021 20:07:29 -0500 Subject: soc: imx: gpcv2: add support for i.MX8MN power domains This adds support for the power domains founds on i.MX8MN. The Nano has fewer domains than the Mini, and the access to some of these domains is different than that of the Mini, the Mini power domains cannot be reused. Signed-off-by: Adam Ford Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 92 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 35bbb1bc5159..34a9ac1f2b9b 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -20,6 +20,7 @@ #include #include #include +#include #define GPC_LPCR_A_CORE_BSC 0x000 @@ -58,6 +59,12 @@ #define IMX8MM_PCIE_A53_DOMAIN BIT(3) #define IMX8MM_MIPI_A53_DOMAIN BIT(2) +#define IMX8MN_DISPMIX_A53_DOMAIN BIT(12) +#define IMX8MN_GPUMIX_A53_DOMAIN BIT(9) +#define IMX8MN_DDR1_A53_DOMAIN BIT(7) +#define IMX8MN_OTG1_A53_DOMAIN BIT(4) +#define IMX8MN_MIPI_A53_DOMAIN BIT(2) + #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 #define GPC_PU_PGC_SW_PDN_REQ 0x104 @@ -94,6 +101,12 @@ #define IMX8MM_PCIE_SW_Pxx_REQ BIT(1) #define IMX8MM_MIPI_SW_Pxx_REQ BIT(0) +#define IMX8MN_DISPMIX_SW_Pxx_REQ BIT(10) +#define IMX8MN_GPUMIX_SW_Pxx_REQ BIT(7) +#define IMX8MN_DDR1_SW_Pxx_REQ BIT(5) +#define IMX8MN_OTG1_SW_Pxx_REQ BIT(2) +#define IMX8MN_MIPI_SW_Pxx_REQ BIT(0) + #define GPC_M4_PU_PDN_FLG 0x1bc #define GPC_PU_PWRHSK 0x1fc @@ -116,6 +129,14 @@ #define IMX8MM_VPUMIX_HSK_PWRDNREQN BIT(8) #define IMX8MM_DISPMIX_HSK_PWRDNREQN BIT(7) #define IMX8MM_HSIO_HSK_PWRDNREQN (BIT(5) | BIT(6)) + +#define IMX8MN_GPUMIX_HSK_PWRDNACKN (BIT(29) | BIT(27)) +#define IMX8MN_DISPMIX_HSK_PWRDNACKN BIT(25) +#define IMX8MN_HSIO_HSK_PWRDNACKN BIT(23) +#define IMX8MN_GPUMIX_HSK_PWRDNREQN (BIT(11) | BIT(9)) +#define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7) +#define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5) + /* * The PGC offset values in Reference Manual * (Rev. 1, 01/2018 and the older ones) GPC chapter's @@ -152,6 +173,12 @@ #define IMX8MM_PGC_VPUG2 28 #define IMX8MM_PGC_VPUH1 29 +#define IMX8MN_PGC_MIPI 16 +#define IMX8MN_PGC_OTG1 18 +#define IMX8MN_PGC_DDR1 21 +#define IMX8MN_PGC_GPUMIX 23 +#define IMX8MN_PGC_DISPMIX 26 + #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) @@ -764,6 +791,70 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = { .reg_access_table = &imx8mm_access_table, }; +static const struct imx_pgc_domain imx8mn_pgc_domains[] = { + [IMX8MN_POWER_DOMAIN_HSIOMIX] = { + .genpd = { + .name = "hsiomix", + }, + .bits = { + .pxx = 0, /* no power sequence control */ + .map = 0, /* no power sequence control */ + .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN, + .hskack = IMX8MN_HSIO_HSK_PWRDNACKN, + }, + }, + + [IMX8MN_POWER_DOMAIN_OTG1] = { + .genpd = { + .name = "usb-otg1", + }, + .bits = { + .pxx = IMX8MN_OTG1_SW_Pxx_REQ, + .map = IMX8MN_OTG1_A53_DOMAIN, + }, + .pgc = IMX8MN_PGC_OTG1, + }, + + [IMX8MN_POWER_DOMAIN_GPUMIX] = { + .genpd = { + .name = "gpumix", + }, + .bits = { + .pxx = IMX8MN_GPUMIX_SW_Pxx_REQ, + .map = IMX8MN_GPUMIX_A53_DOMAIN, + .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN, + .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN, + }, + .pgc = IMX8MN_PGC_GPUMIX, + }, +}; + +static const struct regmap_range imx8mn_yes_ranges[] = { + regmap_reg_range(GPC_LPCR_A_CORE_BSC, + GPC_PU_PWRHSK), + regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_MIPI), + GPC_PGC_SR(IMX8MN_PGC_MIPI)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_OTG1), + GPC_PGC_SR(IMX8MN_PGC_OTG1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DDR1), + GPC_PGC_SR(IMX8MN_PGC_DDR1)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_GPUMIX), + GPC_PGC_SR(IMX8MN_PGC_GPUMIX)), + regmap_reg_range(GPC_PGC_CTRL(IMX8MN_PGC_DISPMIX), + GPC_PGC_SR(IMX8MN_PGC_DISPMIX)), +}; + +static const struct regmap_access_table imx8mn_access_table = { + .yes_ranges = imx8mn_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(imx8mn_yes_ranges), +}; + +static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = { + .domains = imx8mn_pgc_domains, + .domains_num = ARRAY_SIZE(imx8mn_pgc_domains), + .reg_access_table = &imx8mn_access_table, +}; + static int imx_pgc_domain_probe(struct platform_device *pdev) { struct imx_pgc_domain *domain = pdev->dev.platform_data; @@ -948,6 +1039,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev) static const struct of_device_id imx_gpcv2_dt_ids[] = { { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, }, { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, }, + { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, }, { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, }, { } }; -- cgit v1.2.3