From fb6d1d3b25d254602fa3318cd5b874f79ad9f3b7 Mon Sep 17 00:00:00 2001 From: Bilal Wasim Date: Thu, 1 Jul 2021 11:40:22 +0200 Subject: soc: mediatek: pm-domains: Use correct mask for bus_prot_clr When "bus_prot_reg_update" is true, the driver should use INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus protection. However, the driver does not use this mask for clearing bus protection which causes failure when booting the imgtec gpu. Corrected and tested with mt8173 chromebook. Signed-off-by: Bilal Wasim Signed-off-by: Enric Balletbo i Serra Reviewed-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210701114012.RESEND.1.I27436c29c3bede46dcf86df696f48683662d1ec1@changeid Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pm-domains.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 21a4e113bbec..c5ac649ae51b 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -60,7 +60,7 @@ #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ INFRA_TOPAXI_PROTECTEN, \ - INFRA_TOPAXI_PROTECTEN_CLR, \ + INFRA_TOPAXI_PROTECTEN, \ INFRA_TOPAXI_PROTECTSTA1) struct scpsys_bus_prot_data { -- cgit v1.2.3 From 114956518c85f4e93c298749b35b46b2e78a2ec9 Mon Sep 17 00:00:00 2001 From: Bilal Wasim Date: Thu, 1 Jul 2021 11:40:23 +0200 Subject: soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD The mfg_async power domain in mt8173 is used to power up imgtec gpu. This domain requires the da9211 regulator to be enabled before the power domain can be enabled successfully. Signed-off-by: Bilal Wasim Signed-off-by: Enric Balletbo i Serra Reviewed-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210701114012.RESEND.2.I2e1bf1b589f9138ba6f89791ed9f1e9f3ddd0a5d@changeid Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8173-pm-domains.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h index 654c717e5467..714fa92575df 100644 --- a/drivers/soc/mediatek/mt8173-pm-domains.h +++ b/drivers/soc/mediatek/mt8173-pm-domains.h @@ -71,6 +71,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .ctl_offs = SPM_MFG_ASYNC_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = 0, + .caps = MTK_SCPD_DOMAIN_SUPPLY, }, [MT8173_POWER_DOMAIN_MFG_2D] = { .name = "mfg_2d", -- cgit v1.2.3 From 2a1c55d4762dd34a8b0f2e36fb01b7b16b60735b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 8 Feb 2021 15:38:55 +0100 Subject: soc: rockchip: ROCKCHIP_GRF should not default to y, unconditionally Merely enabling CONFIG_COMPILE_TEST should not enable additional code. To fix this, restrict the automatic enabling of ROCKCHIP_GRF to ARCH_ROCKCHIP, and ask the user in case of compile-testing. Fixes: 4c58063d4258f6be ("soc: rockchip: add driver handling grf setup") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20210208143855.418374-1-geert+renesas@glider.be Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/rockchip/Kconfig b/drivers/soc/rockchip/Kconfig index 2c13bf4dd5db..25eb2c1e31bb 100644 --- a/drivers/soc/rockchip/Kconfig +++ b/drivers/soc/rockchip/Kconfig @@ -6,8 +6,8 @@ if ARCH_ROCKCHIP || COMPILE_TEST # config ROCKCHIP_GRF - bool - default y + bool "Rockchip General Register Files support" if COMPILE_TEST + default y if ARCH_ROCKCHIP help The General Register Files are a central component providing special additional settings registers for a lot of soc-components. -- cgit v1.2.3 From d63486dd8e0bf843949c184843137e03bca5b8b4 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 9 Jul 2021 10:41:42 -0700 Subject: soc: qcom: aoss: Add generic compatible It seems we don't need platform specific implementation for the AOSS QMP, so let's introduce a generic compatible to avoid having to update the driver for each platform. Reviewed-by: Sibi Sankar Tested-by: Sibi Sankar Link: https://lore.kernel.org/r/20210709174142.1274554-4-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom_aoss.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 934fcc4d2b05..92a1af70a649 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -602,6 +602,7 @@ static const struct of_device_id qmp_dt_match[] = { { .compatible = "qcom,sm8150-aoss-qmp", }, { .compatible = "qcom,sm8250-aoss-qmp", }, { .compatible = "qcom,sm8350-aoss-qmp", }, + { .compatible = "qcom,aoss-qmp", }, {} }; MODULE_DEVICE_TABLE(of, qmp_dt_match); -- cgit v1.2.3 From d43b3a989bc8c06fd4bbb69a7500d180db2d68e8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 2 Jul 2021 17:54:15 -0700 Subject: soc: qcom: rpmhpd: Use corner in power_off rpmhpd_aggregate_corner() takes a corner as parameter, but in rpmhpd_power_off() the code requests the level of the first corner instead. In all (known) current cases the first corner has level 0, so this change should be a nop, but in case that there's a power domain with a non-zero lowest level this makes sure that rpmhpd_power_off() actually requests the lowest level - which is the closest to "power off" we can get. While touching the code, also skip the unnecessary zero-initialization of "ret". Fixes: 279b7e8a62cc ("soc: qcom: rpmhpd: Add RPMh power domain driver") Reviewed-by: Rajendra Nayak Reviewed-by: Stephen Boyd Reviewed-by: Sibi Sankar Tested-by: Sibi Sankar Link: https://lore.kernel.org/r/20210703005416.2668319-2-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmhpd.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 2daa17ba54a3..fa209b479ab3 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -403,12 +403,11 @@ static int rpmhpd_power_on(struct generic_pm_domain *domain) static int rpmhpd_power_off(struct generic_pm_domain *domain) { struct rpmhpd *pd = domain_to_rpmhpd(domain); - int ret = 0; + int ret; mutex_lock(&rpmhpd_lock); - ret = rpmhpd_aggregate_corner(pd, pd->level[0]); - + ret = rpmhpd_aggregate_corner(pd, 0); if (!ret) pd->enabled = false; -- cgit v1.2.3 From 0d361b0ac1ad99ecbe401a4eacdeb844dcdf86a2 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Sun, 27 Jun 2021 20:01:50 -0700 Subject: soc: qcom: socinfo: Don't print anything if nothing found Let's skip printing anything if there's nothing to see. This makes it so the file length is 0 instead of 1, for the newline, and helps scripts figure out if there's anything to see in these files. Cc: Sai Prakash Ranjan Cc: Douglas Anderson Cc: Dmitry Baryshkov Reviewed-by: Douglas Anderson Reviewed-by: Sai Prakash Ranjan Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20210628030150.2627905-1-swboyd@chromium.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index b2f049faa3df..9faf48302f4b 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -417,8 +417,8 @@ QCOM_OPEN(chip_id, qcom_show_chip_id); static int show_image_##type(struct seq_file *seq, void *p) \ { \ struct smem_image_version *image_version = seq->private; \ - seq_puts(seq, image_version->type); \ - seq_putc(seq, '\n'); \ + if (image_version->type[0] != '\0') \ + seq_printf(seq, "%s\n", image_version->type); \ return 0; \ } \ static int open_image_##type(struct inode *inode, struct file *file) \ -- cgit v1.2.3 From a89f355e469dcda129c2522be4fdba00c1c74c83 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 29 Jun 2021 21:02:49 +0530 Subject: soc: qcom: aoss: Fix the out of bound usage of cooling_devs In "qmp_cooling_devices_register", the count value is initially QMP_NUM_COOLING_RESOURCES, which is 2. Based on the initial count value, the memory for cooling_devs is allocated. Then while calling the "qmp_cooling_device_add" function, count value is post-incremented for each child node. This makes the out of bound access to the cooling_dev array. Fix it by passing the QMP_NUM_COOLING_RESOURCES definition to devm_kzalloc() and initializing the count to 0. While at it, let's also free the memory allocated to cooling_dev if no cooling device is found in DT and during unroll phase. Cc: stable@vger.kernel.org # 5.4 Fixes: 05589b30b21a ("soc: qcom: Extend AOSS QMP driver to support resources that are used to wake up the SoC.") Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20210629153249.73428-1-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom_aoss.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 92a1af70a649..536c3e4114fb 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -476,12 +476,12 @@ static int qmp_cooling_device_add(struct qmp *qmp, static int qmp_cooling_devices_register(struct qmp *qmp) { struct device_node *np, *child; - int count = QMP_NUM_COOLING_RESOURCES; + int count = 0; int ret; np = qmp->dev->of_node; - qmp->cooling_devs = devm_kcalloc(qmp->dev, count, + qmp->cooling_devs = devm_kcalloc(qmp->dev, QMP_NUM_COOLING_RESOURCES, sizeof(*qmp->cooling_devs), GFP_KERNEL); @@ -497,12 +497,16 @@ static int qmp_cooling_devices_register(struct qmp *qmp) goto unroll; } + if (!count) + devm_kfree(qmp->dev, qmp->cooling_devs); + return 0; unroll: while (--count >= 0) thermal_cooling_device_unregister (qmp->cooling_devs[count].cdev); + devm_kfree(qmp->dev, qmp->cooling_devs); return ret; } -- cgit v1.2.3 From 18785c94ab6357338cf4aa872aabacbcc7178e83 Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sun, 27 Jun 2021 21:59:27 +0300 Subject: drivers: soc: qcom: rpmpd: Add SM6115 RPM Power Domains The SM4250/6115 have 4 rpm power domains, ported from downstream DT. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20210627185927.695411-6-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmpd.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 0b532a892d60..dbf494e92574 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -346,6 +346,33 @@ static const struct rpmpd_desc sdm660_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; +/* sm4250/6115 RPM Power domains */ +DEFINE_RPMPD_PAIR(sm6115, vddcx, vddcx_ao, RWCX, LEVEL, 0); +DEFINE_RPMPD_VFL(sm6115, vddcx_vfl, RWCX, 0); + +DEFINE_RPMPD_PAIR(sm6115, vddmx, vddmx_ao, RWMX, LEVEL, 0); +DEFINE_RPMPD_VFL(sm6115, vddmx_vfl, RWMX, 0); + +DEFINE_RPMPD_LEVEL(sm6115, vdd_lpi_cx, RWLC, 0); +DEFINE_RPMPD_LEVEL(sm6115, vdd_lpi_mx, RWLM, 0); + +static struct rpmpd *sm6115_rpmpds[] = { + [SM6115_VDDCX] = &sm6115_vddcx, + [SM6115_VDDCX_AO] = &sm6115_vddcx_ao, + [SM6115_VDDCX_VFL] = &sm6115_vddcx_vfl, + [SM6115_VDDMX] = &sm6115_vddmx, + [SM6115_VDDMX_AO] = &sm6115_vddmx_ao, + [SM6115_VDDMX_VFL] = &sm6115_vddmx_vfl, + [SM6115_VDD_LPI_CX] = &sm6115_vdd_lpi_cx, + [SM6115_VDD_LPI_MX] = &sm6115_vdd_lpi_mx, +}; + +static const struct rpmpd_desc sm6115_desc = { + .rpmpds = sm6115_rpmpds, + .num_pds = ARRAY_SIZE(sm6115_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO_NO_CPR, +}; + static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc }, { .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc }, @@ -356,6 +383,7 @@ static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,msm8998-rpmpd", .data = &msm8998_desc }, { .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc }, { .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc }, + { .compatible = "qcom,sm6115-rpmpd", .data = &sm6115_desc }, { } }; MODULE_DEVICE_TABLE(of, rpmpd_match_table); -- cgit v1.2.3 From bfe6b5590ce6cab81b3ee51b4541bd1d0b18b3b2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 19 Jul 2021 17:38:33 +0200 Subject: soc: renesas: Identify R-Car H3e-2G and M3e-2G Add support for identifying the R-Car H3e-2G (R8A779M1) and R-Car M3e-2G (R8A779M3) SoCs. As these are different gradings of the already supported R-Car H3 ES3.0 (R8A77951) and M3-W+ (R8A77961) SoCs, support for them is enabled through the existing ARCH_R8A77951 and ARCH_R8A77961 configuration symbols. Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/42b4578ab4739cb48ec3aed0a447fc40c34de1e5.1626708063.git.geert+renesas@glider.be --- drivers/soc/renesas/Kconfig | 2 ++ drivers/soc/renesas/renesas-soc.c | 4 ++++ 2 files changed, 6 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 71b44c31b012..07e0ecd64319 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -208,6 +208,7 @@ config ARCH_R8A77951 help This enables support for the Renesas R-Car H3 SoC (revisions 2.0 and later). + This includes different gradings like R-Car H3e-2G. config ARCH_R8A77965 bool "ARM64 Platform support for R-Car M3-N" @@ -229,6 +230,7 @@ config ARCH_R8A77961 select SYSC_R8A77961 help This enables support for the Renesas R-Car M3-W+ SoC. + This includes different gradings like R-Car M3e-2G. config ARCH_R8A77980 bool "ARM64 Platform support for R-Car V3H" diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 8310fce7714e..dab9f5a0aad0 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -284,11 +284,15 @@ static const struct of_device_id renesas_socs[] __initconst = { #if defined(CONFIG_ARCH_R8A77950) || defined(CONFIG_ARCH_R8A77951) { .compatible = "renesas,r8a7795", .data = &soc_rcar_h3 }, #endif +#ifdef CONFIG_ARCH_R8A77951 + { .compatible = "renesas,r8a779m1", .data = &soc_rcar_h3 }, +#endif #ifdef CONFIG_ARCH_R8A77960 { .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w }, #endif #ifdef CONFIG_ARCH_R8A77961 { .compatible = "renesas,r8a77961", .data = &soc_rcar_m3_w }, + { .compatible = "renesas,r8a779m3", .data = &soc_rcar_m3_w }, #endif #ifdef CONFIG_ARCH_R8A77965 { .compatible = "renesas,r8a77965", .data = &soc_rcar_m3_n }, -- cgit v1.2.3 From 6feba6a62c577e98bd9214b73c17860166ac8b91 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Fri, 21 May 2021 13:44:53 -0700 Subject: PM: AVS: qcom-cpr: Use nvmem_cell_read_variable_le_u32() Let's delete the private function cpr_read_efuse() since it does the basically the same thing as the new API call nvmem_cell_read_variable_le_u32(). Differences between the new API call and the old private function: * less error printing (I assume this is OK). * will give an error if the value doesn't fit in 32-bits (the old code would have truncated silently). Reviewed-by: Bjorn Andersson Acked-by: Niklas Cassel Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20210521134437.v2.1.Id1c70158722750aec0673d60c12e46a9c66bbfed@changeid Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/cpr.c | 43 +++++-------------------------------------- 1 file changed, 5 insertions(+), 38 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/cpr.c b/drivers/soc/qcom/cpr.c index b24cc77d1889..4ce8e816154f 100644 --- a/drivers/soc/qcom/cpr.c +++ b/drivers/soc/qcom/cpr.c @@ -801,38 +801,6 @@ unlock: return ret; } -static int cpr_read_efuse(struct device *dev, const char *cname, u32 *data) -{ - struct nvmem_cell *cell; - ssize_t len; - char *ret; - int i; - - *data = 0; - - cell = nvmem_cell_get(dev, cname); - if (IS_ERR(cell)) { - if (PTR_ERR(cell) != -EPROBE_DEFER) - dev_err(dev, "undefined cell %s\n", cname); - return PTR_ERR(cell); - } - - ret = nvmem_cell_read(cell, &len); - nvmem_cell_put(cell); - if (IS_ERR(ret)) { - dev_err(dev, "can't read cell %s\n", cname); - return PTR_ERR(ret); - } - - for (i = 0; i < len; i++) - *data |= ret[i] << (8 * i); - - kfree(ret); - dev_dbg(dev, "efuse read(%s) = %x, bytes %zd\n", cname, *data, len); - - return 0; -} - static int cpr_populate_ring_osc_idx(struct cpr_drv *drv) { @@ -843,8 +811,7 @@ cpr_populate_ring_osc_idx(struct cpr_drv *drv) int ret; for (; fuse < end; fuse++, fuses++) { - ret = cpr_read_efuse(drv->dev, fuses->ring_osc, - &data); + ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->ring_osc, &data); if (ret) return ret; fuse->ring_osc_idx = data; @@ -863,7 +830,7 @@ static int cpr_read_fuse_uV(const struct cpr_desc *desc, u32 bits = 0; int ret; - ret = cpr_read_efuse(drv->dev, init_v_efuse, &bits); + ret = nvmem_cell_read_variable_le_u32(drv->dev, init_v_efuse, &bits); if (ret) return ret; @@ -932,7 +899,7 @@ static int cpr_fuse_corner_init(struct cpr_drv *drv) } /* Populate target quotient by scaling */ - ret = cpr_read_efuse(drv->dev, fuses->quotient, &fuse->quot); + ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->quotient, &fuse->quot); if (ret) return ret; @@ -1001,7 +968,7 @@ static int cpr_calculate_scaling(const char *quot_offset, prev_fuse = fuse - 1; if (quot_offset) { - ret = cpr_read_efuse(drv->dev, quot_offset, "_diff); + ret = nvmem_cell_read_variable_le_u32(drv->dev, quot_offset, "_diff); if (ret) return ret; @@ -1701,7 +1668,7 @@ static int cpr_probe(struct platform_device *pdev) * initialized after attaching to the power domain, * since it depends on the CPU's OPP table. */ - ret = cpr_read_efuse(dev, "cpr_fuse_revision", &cpr_rev); + ret = nvmem_cell_read_variable_le_u32(dev, "cpr_fuse_revision", &cpr_rev); if (ret) return ret; -- cgit v1.2.3 From 7bdcead7a75e3eab5e711c2da78c2a0360e7f2a4 Mon Sep 17 00:00:00 2001 From: CK Hu Date: Thu, 29 Jul 2021 09:05:49 +0200 Subject: soc: mmsys: mediatek: add mask to mmsys routes SOUT has many bits and need to be cleared before set new value. Write only could do the clear, but for MOUT, it clears bits that should not be cleared. So use a mask to reset only the needed bits. this fixes HDMI issues on MT7623/BPI-R2 since 5.13 Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers") Signed-off-by: Frank Wunderlich Signed-off-by: CK Hu Reviewed-by: Chun-Kuang Hu Reviewed-by: Hsin-Yi Wang Link: https://lore.kernel.org/r/20210729070549.5514-1-linux@fw-web.de Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8183-mmsys.h | 21 ++++-- drivers/soc/mediatek/mtk-mmsys.c | 7 +- drivers/soc/mediatek/mtk-mmsys.h | 133 +++++++++++++++++++++++++----------- 3 files changed, 112 insertions(+), 49 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h index 579dfc8dc8fc..9dee485807c9 100644 --- a/drivers/soc/mediatek/mt8183-mmsys.h +++ b/drivers/soc/mediatek/mt8183-mmsys.h @@ -28,25 +28,32 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, - MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L + MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L, + MT8183_OVL0_MOUT_EN_OVL0_2L }, { DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, - MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 + MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0, + MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 }, { DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1, - MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1 + MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1, + MT8183_OVL1_2L_MOUT_EN_RDMA1 }, { DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, - MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0 + MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0, + MT8183_DITHER0_MOUT_IN_DSI0 }, { DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, - MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L + MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L, + MT8183_DISP_PATH0_SEL_IN_OVL0_2L }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1 + MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1, + MT8183_DPI0_SEL_IN_RDMA1 }, { DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, - MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0 + MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0, + MT8183_RDMA0_SOUT_COLOR0 } }; diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 080660ef11bf..0f949896fd06 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -68,7 +68,9 @@ void mtk_mmsys_ddp_connect(struct device *dev, for (i = 0; i < mmsys->data->num_routes; i++) if (cur == routes[i].from_comp && next == routes[i].to_comp) { - reg = readl_relaxed(mmsys->regs + routes[i].addr) | routes[i].val; + reg = readl_relaxed(mmsys->regs + routes[i].addr); + reg &= ~routes[i].mask; + reg |= routes[i].val; writel_relaxed(reg, mmsys->regs + routes[i].addr); } } @@ -85,7 +87,8 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, for (i = 0; i < mmsys->data->num_routes; i++) if (cur == routes[i].from_comp && next == routes[i].to_comp) { - reg = readl_relaxed(mmsys->regs + routes[i].addr) & ~routes[i].val; + reg = readl_relaxed(mmsys->regs + routes[i].addr); + reg &= ~routes[i].mask; writel_relaxed(reg, mmsys->regs + routes[i].addr); } } diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index a760a34e6eca..5f3e2bf0c40b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -35,41 +35,54 @@ #define RDMA0_SOUT_DSI1 0x1 #define RDMA0_SOUT_DSI2 0x4 #define RDMA0_SOUT_DSI3 0x5 +#define RDMA0_SOUT_MASK 0x7 #define RDMA1_SOUT_DPI0 0x2 #define RDMA1_SOUT_DPI1 0x3 #define RDMA1_SOUT_DSI1 0x1 #define RDMA1_SOUT_DSI2 0x4 #define RDMA1_SOUT_DSI3 0x5 +#define RDMA1_SOUT_MASK 0x7 #define RDMA2_SOUT_DPI0 0x2 #define RDMA2_SOUT_DPI1 0x3 #define RDMA2_SOUT_DSI1 0x1 #define RDMA2_SOUT_DSI2 0x4 #define RDMA2_SOUT_DSI3 0x5 +#define RDMA2_SOUT_MASK 0x7 #define DPI0_SEL_IN_RDMA1 0x1 #define DPI0_SEL_IN_RDMA2 0x3 +#define DPI0_SEL_IN_MASK 0x3 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) #define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DPI1_SEL_IN_MASK (0x3 << 8) #define DSI0_SEL_IN_RDMA1 0x1 #define DSI0_SEL_IN_RDMA2 0x4 +#define DSI0_SEL_IN_MASK 0x7 #define DSI1_SEL_IN_RDMA1 0x1 #define DSI1_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_MASK 0x7 #define DSI2_SEL_IN_RDMA1 (0x1 << 16) #define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI2_SEL_IN_MASK (0x7 << 16) #define DSI3_SEL_IN_RDMA1 (0x1 << 16) #define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_MASK (0x7 << 16) #define COLOR1_SEL_IN_OVL1 0x1 #define OVL_MOUT_EN_RDMA 0x1 #define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 #define BLS_TO_DPI_RDMA1_TO_DSI 0x2 +#define BLS_RDMA1_DSI_DPI_MASK 0xf #define DSI_SEL_IN_BLS 0x0 #define DPI_SEL_IN_BLS 0x0 +#define DPI_SEL_IN_MASK 0x1 #define DSI_SEL_IN_RDMA 0x1 +#define DSI_SEL_IN_MASK 0x1 struct mtk_mmsys_routes { u32 from_comp; u32 to_comp; u32 addr; + u32 mask; u32 val; }; @@ -91,124 +104,164 @@ struct mtk_mmsys_driver_data { static const struct mtk_mmsys_routes mmsys_default_routing_table[] = { { DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0, - DISP_REG_CONFIG_OUT_SEL, BLS_TO_DSI_RDMA1_TO_DPI1 + DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK, + BLS_TO_DSI_RDMA1_TO_DPI1 }, { DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0, - DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_BLS + DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK, + DSI_SEL_IN_BLS }, { DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, - DISP_REG_CONFIG_OUT_SEL, BLS_TO_DPI_RDMA1_TO_DSI + DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK, + BLS_TO_DPI_RDMA1_TO_DSI }, { DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, - DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_RDMA + DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK, + DSI_SEL_IN_RDMA }, { DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0, - DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_BLS + DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK, + DPI_SEL_IN_BLS }, { DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1, - DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1 + DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1, + GAMMA_MOUT_EN_RDMA1 }, { DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0, - DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0 + DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0, + OD_MOUT_EN_RDMA0 }, { DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1, - DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1 + DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1, + OD1_MOUT_EN_RDMA1 }, { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, - DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0 + DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, + OVL0_MOUT_EN_COLOR0 }, { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, - DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0 + DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0, + COLOR0_SEL_IN_OVL0 }, { DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, - DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA + DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA, + OVL_MOUT_EN_RDMA }, { DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, - DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1 + DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1, + OVL1_MOUT_EN_COLOR1 }, { DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1, - DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1 + DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1, + COLOR1_SEL_IN_OVL1 }, { DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0, - DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI0 + DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, + RDMA0_SOUT_DPI0 }, { DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1, - DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DPI1 + DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, + RDMA0_SOUT_DPI1 }, { DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1, - DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI1 + DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, + RDMA0_SOUT_DSI1 }, { DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2, - DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI2 + DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, + RDMA0_SOUT_DSI2 }, { DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3, - DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_DSI3 + DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK, + RDMA0_SOUT_DSI3 }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI0 + DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, + RDMA1_SOUT_DPI0 }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, - DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA1 + DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK, + DPI0_SEL_IN_RDMA1 }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1, - DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DPI1 + DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, + RDMA1_SOUT_DPI1 }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1, - DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA1 + DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK, + DPI1_SEL_IN_RDMA1 }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0, - DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA1 + DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK, + DSI0_SEL_IN_RDMA1 }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1, - DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI1 + DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, + RDMA1_SOUT_DSI1 }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1, - DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA1 + DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK, + DSI1_SEL_IN_RDMA1 }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2, - DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI2 + DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, + RDMA1_SOUT_DSI2 }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2, - DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA1 + DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK, + DSI2_SEL_IN_RDMA1 }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3, - DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_DSI3 + DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK, + RDMA1_SOUT_DSI3 }, { DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3, - DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA1 + DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK, + DSI3_SEL_IN_RDMA1 }, { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0, - DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI0 + DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, + RDMA2_SOUT_DPI0 }, { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0, - DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_RDMA2 + DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK, + DPI0_SEL_IN_RDMA2 }, { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1, - DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DPI1 + DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, + RDMA2_SOUT_DPI1 }, { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1, - DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_RDMA2 + DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK, + DPI1_SEL_IN_RDMA2 }, { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0, - DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_RDMA2 + DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK, + DSI0_SEL_IN_RDMA2 }, { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1, - DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI1 + DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, + RDMA2_SOUT_DSI1 }, { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1, - DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_RDMA2 + DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK, + DSI1_SEL_IN_RDMA2 }, { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2, - DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI2 + DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, + RDMA2_SOUT_DSI2 }, { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2, - DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_RDMA2 + DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK, + DSI2_SEL_IN_RDMA2 }, { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, - DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_DSI3 + DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK, + RDMA2_SOUT_DSI3 }, { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, - DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_RDMA2 + DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK, + DSI3_SEL_IN_RDMA2 } }; -- cgit v1.2.3 From cb531cab62a19e97d8de0a2c9935daed93ec3736 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 25 Jun 2021 10:52:09 +0530 Subject: soc: qcom: geni: move GENI_IF_DISABLE_RO to common header GENI_IF_DISABLE_RO is used by geni spi driver as well to check the status if GENI, so move this to common header qcom-geni-se.h Reviewed-by: Bjorn Andersson Signed-off-by: Vinod Koul Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20210625052213.32260-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom-geni-se.c | 1 - include/linux/qcom-geni-se.h | 4 ++++ 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 5bdfb1565c14..fe666ea0c487 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -104,7 +104,6 @@ static const char * const icc_path_names[] = {"qup-core", "qup-config", #define GENI_OUTPUT_CTRL 0x24 #define GENI_CGC_CTRL 0x28 #define GENI_CLK_CTRL_RO 0x60 -#define GENI_IF_DISABLE_RO 0x64 #define GENI_FW_S_REVISION_RO 0x6c #define SE_GENI_BYTE_GRAN 0x254 #define SE_GENI_TX_PACKING_CFG0 0x260 diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h index 7c811eebcaab..5114e2144b17 100644 --- a/include/linux/qcom-geni-se.h +++ b/include/linux/qcom-geni-se.h @@ -63,6 +63,7 @@ struct geni_se { #define SE_GENI_STATUS 0x40 #define GENI_SER_M_CLK_CFG 0x48 #define GENI_SER_S_CLK_CFG 0x4c +#define GENI_IF_DISABLE_RO 0x64 #define GENI_FW_REVISION_RO 0x68 #define SE_GENI_CLK_SEL 0x7c #define SE_GENI_DMA_MODE_EN 0x258 @@ -105,6 +106,9 @@ struct geni_se { #define CLK_DIV_MSK GENMASK(15, 4) #define CLK_DIV_SHFT 4 +/* GENI_IF_DISABLE_RO fields */ +#define FIFO_IF_DISABLE (BIT(0)) + /* GENI_FW_REVISION_RO fields */ #define FW_REV_PROTOCOL_MSK GENMASK(15, 8) #define FW_REV_PROTOCOL_SHFT 8 -- cgit v1.2.3 From 0fa8266294754978da34d7ea785d621f51d939f2 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 25 Jun 2021 10:52:10 +0530 Subject: soc: qcom: geni: Add support for gpi dma GPI DMA is one of the DMA modes supported on geni, this adds support to enable that mode Also do better documentation of the enum geni_se_xfer_mode. Signed-off-by: Vinod Koul Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20210625052213.32260-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom-geni-se.c | 29 ++++++++++++++++++++++++++++- include/linux/qcom-geni-se.h | 15 ++++++++++++++- 2 files changed, 42 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index fe666ea0c487..7d649d2cf31e 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -321,6 +321,30 @@ static void geni_se_select_dma_mode(struct geni_se *se) writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); } +static void geni_se_select_gpi_mode(struct geni_se *se) +{ + u32 val; + + geni_se_irq_clear(se); + + writel(0, se->base + SE_IRQ_EN); + + val = readl(se->base + SE_GENI_S_IRQ_EN); + val &= ~S_CMD_DONE_EN; + writel(val, se->base + SE_GENI_S_IRQ_EN); + + val = readl(se->base + SE_GENI_M_IRQ_EN); + val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | + M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); + writel(val, se->base + SE_GENI_M_IRQ_EN); + + writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN); + + val = readl(se->base + SE_GSI_EVENT_EN); + val |= (DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVENT_EN); + writel(val, se->base + SE_GSI_EVENT_EN); +} + /** * geni_se_select_mode() - Select the serial engine transfer mode * @se: Pointer to the concerned serial engine. @@ -328,7 +352,7 @@ static void geni_se_select_dma_mode(struct geni_se *se) */ void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode) { - WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA); + WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA && mode != GENI_GPI_DMA); switch (mode) { case GENI_SE_FIFO: @@ -337,6 +361,9 @@ void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode) case GENI_SE_DMA: geni_se_select_dma_mode(se); break; + case GENI_GPI_DMA: + geni_se_select_gpi_mode(se); + break; case GENI_SE_INVALID: default: break; diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h index 5114e2144b17..f5672785c0c4 100644 --- a/include/linux/qcom-geni-se.h +++ b/include/linux/qcom-geni-se.h @@ -8,11 +8,24 @@ #include -/* Transfer mode supported by GENI Serial Engines */ +/** + * enum geni_se_xfer_mode: Transfer modes supported by Serial Engines + * + * @GENI_SE_INVALID: Invalid mode + * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO + * by programmed IO method + * @GENI_SE_DMA: Serial Engine DMA mode. Data is transferred + * with SE by DMAengine internal to SE + * @GENI_GPI_DMA: GPI DMA mode. Data is transferred using a DMAengine + * configured by a firmware residing on a GSI engine. This DMA name is + * interchangeably used as GSI or GPI which seem to imply the same DMAengine + */ + enum geni_se_xfer_mode { GENI_SE_INVALID, GENI_SE_FIFO, GENI_SE_DMA, + GENI_GPI_DMA, }; /* Protocols supported by GENI Serial Engines */ -- cgit v1.2.3 From 593cb55b4cdd18a2946efd67c29ec4c6081dea8f Mon Sep 17 00:00:00 2001 From: Iskren Chernev Date: Sat, 31 Jul 2021 19:48:27 +0300 Subject: soc: qcom: smd-rpm: Add SM6115 compatible Add a compatible for SM6115 Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20210731164827.2756798-3-iskren.chernev@gmail.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smd-rpm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index bc0be1d4be5f..dfdd4f20f5fd 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -242,6 +242,7 @@ static const struct of_device_id qcom_smd_rpm_of_match[] = { { .compatible = "qcom,rpm-msm8996" }, { .compatible = "qcom,rpm-msm8998" }, { .compatible = "qcom,rpm-sdm660" }, + { .compatible = "qcom,rpm-sm6115" }, { .compatible = "qcom,rpm-sm6125" }, { .compatible = "qcom,rpm-qcs404" }, {} -- cgit v1.2.3 From ad68c620b7b296aab9cbe61802e329c04fde8385 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 15 Mar 2021 09:44:55 -0500 Subject: soc: qcom: mdt_loader: be more informative on errors In __qcom_mdt_load() there are cases where an error occurs that cause a message to be printed. In some of those cases the errno value can be helpful to understand exactly what caused the problem. Print the errno (as well as the firmware file name) where it is helpful, and in a few cases reword the error message. Consistently use the private fw_name for the file name. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20210315144455.1770492-1-elder@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/mdt_loader.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index eba7f76f9d61..bda170d7b4a2 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -166,6 +166,8 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, metadata = qcom_mdt_read_metadata(fw, &metadata_len); if (IS_ERR(metadata)) { ret = PTR_ERR(metadata); + dev_err(dev, "error %d reading firmware %s metadata\n", + ret, fw_name); goto out; } @@ -173,7 +175,9 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, kfree(metadata); if (ret) { - dev_err(dev, "invalid firmware metadata\n"); + /* Invalid firmware metadata */ + dev_err(dev, "error %d initializing firmware %s\n", + ret, fw_name); goto out; } } @@ -199,7 +203,9 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); if (ret) { - dev_err(dev, "unable to setup relocation\n"); + /* Unable to set up relocation */ + dev_err(dev, "error %d setting up firmware %s\n", + ret, fw_name); goto out; } } @@ -243,9 +249,8 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, if (phdr->p_filesz && phdr->p_offset < fw->size) { /* Firmware is large enough to be non-split */ if (phdr->p_offset + phdr->p_filesz > fw->size) { - dev_err(dev, - "failed to load segment %d from truncated file %s\n", - i, firmware); + dev_err(dev, "file %s segment %d would be truncated\n", + fw_name, i); ret = -EINVAL; break; } @@ -257,7 +262,8 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, ret = request_firmware_into_buf(&seg_fw, fw_name, dev, ptr, phdr->p_filesz); if (ret) { - dev_err(dev, "failed to load %s\n", fw_name); + dev_err(dev, "error %d loading %s\n", + ret, fw_name); break; } -- cgit v1.2.3 From c73a6852b42c8c80cc46590dbbcfa6c448fdbc63 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 12 Jul 2021 15:57:02 +0200 Subject: soc: qcom: smsm: Implement support for get_irqchip_state At the moment there is no way for drivers to get the current state of the interrupt signal reported by a remote processor. The irqchip API has generic functionality for this, using irq_get_irqchip_state(). Implement support for getting the IRQCHIP_STATE_LINE_LEVEL by reading the remote state and checking the bit for the specified IRQ. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210712135703.324748-1-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smsm.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index 1d3d5e3ec2b0..a48f9db98836 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -299,11 +299,28 @@ static int smsm_set_irq_type(struct irq_data *irqd, unsigned int type) return 0; } +static int smsm_get_irqchip_state(struct irq_data *irqd, + enum irqchip_irq_state which, bool *state) +{ + struct smsm_entry *entry = irq_data_get_irq_chip_data(irqd); + irq_hw_number_t irq = irqd_to_hwirq(irqd); + u32 val; + + if (which != IRQCHIP_STATE_LINE_LEVEL) + return -EINVAL; + + val = readl(entry->remote_state); + *state = !!(val & BIT(irq)); + + return 0; +} + static struct irq_chip smsm_irq_chip = { .name = "smsm", .irq_mask = smsm_mask_irq, .irq_unmask = smsm_unmask_irq, .irq_set_type = smsm_set_irq_type, + .irq_get_irqchip_state = smsm_get_irqchip_state, }; /** -- cgit v1.2.3 From e3d4571955050736bbf3eda0a9538a09d9fcfce8 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 12 Jul 2021 15:57:03 +0200 Subject: soc: qcom: smsm: Fix missed interrupts if state changes while masked The SMSM driver detects interrupt edges by tracking the last state it has seen (and has triggered the interrupt handler for). This works fine, but only if the interrupt does not change state while masked. For example, if an interrupt is unmasked while the state is HIGH, the stored last_value for that interrupt might still be LOW. Then, when the remote processor triggers smsm_intr() we assume that nothing has changed, even though the state might have changed from HIGH to LOW. Attempt to fix this by checking the current remote state before unmasking an IRQ. Use atomic operations to avoid the interrupt handler from interfering with the unmask function. This fixes modem crashes in some edge cases with the BAM-DMUX driver. Specifically, the BAM-DMUX interrupt handler is not called for the HIGH -> LOW smsm state transition if the BAM-DMUX driver is loaded (and therefore unmasks the interrupt) after the modem was already started: qcom-q6v5-mss 4080000.remoteproc: fatal error received: a2_task.c:3188: Assert FALSE failed: A2 DL PER deadlock timer expired waiting for Apps ACK Fixes: c97c4090ff72 ("soc: qcom: smsm: Add driver for Qualcomm SMSM") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210712135703.324748-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smsm.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index a48f9db98836..ef15d014c03a 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -109,7 +109,7 @@ struct smsm_entry { DECLARE_BITMAP(irq_enabled, 32); DECLARE_BITMAP(irq_rising, 32); DECLARE_BITMAP(irq_falling, 32); - u32 last_value; + unsigned long last_value; u32 *remote_state; u32 *subscription; @@ -204,8 +204,7 @@ static irqreturn_t smsm_intr(int irq, void *data) u32 val; val = readl(entry->remote_state); - changed = val ^ entry->last_value; - entry->last_value = val; + changed = val ^ xchg(&entry->last_value, val); for_each_set_bit(i, entry->irq_enabled, 32) { if (!(changed & BIT(i))) @@ -264,6 +263,12 @@ static void smsm_unmask_irq(struct irq_data *irqd) struct qcom_smsm *smsm = entry->smsm; u32 val; + /* Make sure our last cached state is up-to-date */ + if (readl(entry->remote_state) & BIT(irq)) + set_bit(irq, &entry->last_value); + else + clear_bit(irq, &entry->last_value); + set_bit(irq, entry->irq_enabled); if (entry->subscription) { -- cgit v1.2.3 From bc3fc5c05100712fa56418f4e3e38f30e6e6f1e7 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 19 May 2021 18:18:46 +0200 Subject: soc: mediatek: mmsys: add MT8365 support Add DSI mmsys connections for the MT8365 SoC. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210519161847.3747352-3-fparent@baylibre.com [mb: take the mask field into account] Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8365-mmsys.h | 60 +++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 +++++++ 2 files changed, 71 insertions(+) create mode 100644 drivers/soc/mediatek/mt8365-mmsys.h (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h new file mode 100644 index 000000000000..690e3fe2dee0 --- /dev/null +++ b/drivers/soc/mediatek/mt8365-mmsys.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8365_MMSYS_H +#define __SOC_MEDIATEK_MT8365_MMSYS_H + +#define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0xf3c +#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL 0xf4c +#define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xf50 +#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xf54 +#define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN 0xf60 +#define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0xf64 +#define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf68 + +#define MT8365_RDMA0_SOUT_COLOR0 0x1 +#define MT8365_DITHER_MOUT_EN_DSI0 0x1 +#define MT8365_DSI0_SEL_IN_DITHER 0x1 +#define MT8365_RDMA0_SEL_IN_OVL0 0x0 +#define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 0x0 +#define MT8365_DISP_COLOR_SEL_IN_COLOR0 0x0 +#define MT8365_OVL0_MOUT_PATH0_SEL BIT(0) + +static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, + MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL + }, + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN, + MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0 + }, + { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL, + MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0 + }, + { + DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR, + MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, + MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0 + }, + { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN, + MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0 + }, + { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, + MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER + }, + { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN, + MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0 + }, +}; + +#endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 0f949896fd06..a78e88f27b62 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -13,6 +13,7 @@ #include "mtk-mmsys.h" #include "mt8167-mmsys.h" #include "mt8183-mmsys.h" +#include "mt8365-mmsys.h" static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", @@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), }; +static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { + .clk_driver = "clk-mt8365-mm", + .routes = mt8365_mmsys_routing_table, + .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -160,6 +167,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8365-mmsys", + .data = &mt8365_mmsys_driver_data, + }, { } }; -- cgit v1.2.3 From 25423731956b3d72bc35d336227c88ada49148e8 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 25 Jun 2021 08:24:48 +0200 Subject: soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing The UFOE (data compression engine) component needs to be enabled to have the imgtec gpu driver working. If we don't enable it we see a black screen. Looks like when we switched to use and array for setting the routing registers in commit 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers") we missed to add this component in the new routing table, it was present before that commit, so fix it by adding this component in the mt8173 routing table. Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers") Signed-off-by: Enric Balletbo i Serra Tested-by: Eizan Miyamoto Cc: Link: https://lore.kernel.org/r/20210625062448.3462177-1-enric.balletbo@collabora.com [mb: taking into account mask value] Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 5f3e2bf0c40b..9e2b81bd38db 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -262,6 +262,10 @@ static const struct mtk_mmsys_routes mmsys_default_routing_table[] = { DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3, DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK, DSI3_SEL_IN_RDMA2 + }, { + DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0, + DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0, + UFOE_MOUT_EN_DSI0 } }; -- cgit v1.2.3 From 22ea87ef3f22742cf2d3dcd31379be3b5612e282 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 9 Aug 2021 11:27:34 -0500 Subject: soc: ti: pruss: Enable support for ICSSG subsystems on K3 AM64x SoCs The K3 AM64x family of SoCs have a similar version of the PRU-ICSS (ICSSG) processor subsystem present on K3 J721E and K3 AM65x SR2.0 SoCs. These SoCs contain typically two ICSSG instances named ICSSG0 and ICSSG1. The two ICSSGs are identical to each other for the most part with minor SoC integration differences and capabilities. SGMII mode is not supported at all on these SoCs (unlike specific instances on AM65x, J721E). The ICSSG1 also has limited pins connected on some sub-modules compared to ICSSG0. There is no change in the Interrupt Controller w.r.t either of AM65x or J721E SoCs. All other integration aspects are also very similar to the existing SoCs. The existing pruss platform driver has been updated to support these similar ICSSG instances through a new AM64x specific compatible. Signed-off-by: Suman Anna Reviewed-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/pruss.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index f22ac1edbdd0..49da387d7749 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -338,6 +338,7 @@ static const struct of_device_id pruss_of_match[] = { { .compatible = "ti,k2g-pruss" }, { .compatible = "ti,am654-icssg", .data = &am65x_j721e_pruss_data, }, { .compatible = "ti,j721e-icssg", .data = &am65x_j721e_pruss_data, }, + { .compatible = "ti,am642-icssg", .data = &am65x_j721e_pruss_data, }, {}, }; MODULE_DEVICE_TABLE(of, pruss_of_match); -- cgit v1.2.3 From ed4520d6a10bbc1d6fdebf325f0395995ce634cf Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 9 Aug 2021 11:27:47 -0500 Subject: soc: ti: Remove pm_runtime_irq_safe() usage for smartreflex For the smartreflex device, we need to disable smartreflex on SoC idle, and have been using pm_runtime_irq_safe() to do that. But we want to remove the irq_safe usage as PM runtime takes a permanent usage count on the parent device with it. In order to remove the need for pm_runtime_irq_safe(), let's gate the clock directly in the driver. This removes the need to call PM runtime during idle, and allows us to switch to using CPU_PM in the following patch. Note that the smartreflex interconnect target module is configured for smart idle, but the clock does not have autoidle capability, and needs to be gated manually. If the clock supported autoidle, we would not need to even gate the clock. With this change, we can now remove the related quirk flags for ti-sysc also. Signed-off-by: Tony Lindgren Signed-off-by: Santosh Shilimkar --- drivers/bus/ti-sysc.c | 6 ++--- drivers/soc/ti/smartreflex.c | 52 +++++++++++++++++---------------------- include/linux/power/smartreflex.h | 2 ++ 3 files changed, 26 insertions(+), 34 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 38cb116ed433..f87783a5489a 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1444,10 +1444,6 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, SYSC_QUIRK_LEGACY_IDLE), - SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, - SYSC_QUIRK_LEGACY_IDLE), - SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, - SYSC_QUIRK_LEGACY_IDLE), SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, @@ -1583,6 +1579,8 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), + SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0), + SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0), SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), diff --git a/drivers/soc/ti/smartreflex.c b/drivers/soc/ti/smartreflex.c index 06cbee5fd254..b5b2fa538d5c 100644 --- a/drivers/soc/ti/smartreflex.c +++ b/drivers/soc/ti/smartreflex.c @@ -126,23 +126,13 @@ static irqreturn_t sr_interrupt(int irq, void *data) static void sr_set_clk_length(struct omap_sr *sr) { - struct clk *fck; u32 fclk_speed; /* Try interconnect target module fck first if it already exists */ - fck = clk_get(sr->pdev->dev.parent, "fck"); - if (IS_ERR(fck)) { - fck = clk_get(&sr->pdev->dev, "fck"); - if (IS_ERR(fck)) { - dev_err(&sr->pdev->dev, - "%s: unable to get fck for device %s\n", - __func__, dev_name(&sr->pdev->dev)); - return; - } - } + if (IS_ERR(sr->fck)) + return; - fclk_speed = clk_get_rate(fck); - clk_put(fck); + fclk_speed = clk_get_rate(sr->fck); switch (fclk_speed) { case 12000000: @@ -587,21 +577,25 @@ int sr_enable(struct omap_sr *sr, unsigned long volt) /* errminlimit is opp dependent and hence linked to voltage */ sr->err_minlimit = nvalue_row->errminlimit; - pm_runtime_get_sync(&sr->pdev->dev); + clk_enable(sr->fck); /* Check if SR is already enabled. If yes do nothing */ if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) - return 0; + goto out_enabled; /* Configure SR */ ret = sr_class->configure(sr); if (ret) - return ret; + goto out_enabled; sr_write_reg(sr, NVALUERECIPROCAL, nvalue_row->nvalue); /* SRCONFIG - enable SR */ sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE); + +out_enabled: + sr->enabled = 1; + return 0; } @@ -621,7 +615,7 @@ void sr_disable(struct omap_sr *sr) } /* Check if SR clocks are already disabled. If yes do nothing */ - if (pm_runtime_suspended(&sr->pdev->dev)) + if (!sr->enabled) return; /* @@ -642,7 +636,8 @@ void sr_disable(struct omap_sr *sr) } } - pm_runtime_put_sync_suspend(&sr->pdev->dev); + clk_disable(sr->fck); + sr->enabled = 0; } /** @@ -851,8 +846,12 @@ static int omap_sr_probe(struct platform_device *pdev) irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + sr_info->fck = devm_clk_get(pdev->dev.parent, "fck"); + if (IS_ERR(sr_info->fck)) + return PTR_ERR(sr_info->fck); + clk_prepare(sr_info->fck); + pm_runtime_enable(&pdev->dev); - pm_runtime_irq_safe(&pdev->dev); snprintf(sr_info->name, SMARTREFLEX_NAME_LEN, "%s", pdata->name); @@ -878,12 +877,6 @@ static int omap_sr_probe(struct platform_device *pdev) list_add(&sr_info->node, &sr_list); - ret = pm_runtime_get_sync(&pdev->dev); - if (ret < 0) { - pm_runtime_put_noidle(&pdev->dev); - goto err_list_del; - } - /* * Call into late init to do initializations that require * both sr driver and sr class driver to be initiallized. @@ -933,16 +926,13 @@ static int omap_sr_probe(struct platform_device *pdev) } - pm_runtime_put_sync(&pdev->dev); - return ret; err_debugfs: debugfs_remove_recursive(sr_info->dbg_dir); err_list_del: list_del(&sr_info->node); - - pm_runtime_put_sync(&pdev->dev); + clk_unprepare(sr_info->fck); return ret; } @@ -950,6 +940,7 @@ err_list_del: static int omap_sr_remove(struct platform_device *pdev) { struct omap_sr_data *pdata = pdev->dev.platform_data; + struct device *dev = &pdev->dev; struct omap_sr *sr_info; if (!pdata) { @@ -968,7 +959,8 @@ static int omap_sr_remove(struct platform_device *pdev) sr_stop_vddautocomp(sr_info); debugfs_remove_recursive(sr_info->dbg_dir); - pm_runtime_disable(&pdev->dev); + pm_runtime_disable(dev); + clk_unprepare(sr_info->fck); list_del(&sr_info->node); return 0; } diff --git a/include/linux/power/smartreflex.h b/include/linux/power/smartreflex.h index 971c9264179e..167b9b040091 100644 --- a/include/linux/power/smartreflex.h +++ b/include/linux/power/smartreflex.h @@ -155,6 +155,7 @@ struct omap_sr { struct voltagedomain *voltdm; struct dentry *dbg_dir; unsigned int irq; + struct clk *fck; int srid; int ip_type; int nvalue_count; @@ -169,6 +170,7 @@ struct omap_sr { u32 senp_mod; u32 senn_mod; void __iomem *base; + unsigned long enabled:1; }; /** -- cgit v1.2.3 From 158a9b47a491dd73e73a306e962d4c9a01270132 Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Tue, 27 Jul 2021 17:28:54 +0800 Subject: soc/tegra: bpmp: Remove unused including Remove including that don't need it. V1->V2: Split the patch in two Signed-off-by: Cai Huoqing Acked-by: Randy Dunlap Signed-off-by: Thierry Reding --- drivers/soc/tegra/powergate-bpmp.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/powergate-bpmp.c b/drivers/soc/tegra/powergate-bpmp.c index 06c792bafca5..8eaf50d0b6af 100644 --- a/drivers/soc/tegra/powergate-bpmp.c +++ b/drivers/soc/tegra/powergate-bpmp.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include -- cgit v1.2.3 From 9c93ccfc86f2cdeab8a34408759abad594e439b9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 19 Jul 2021 00:27:05 +0300 Subject: soc/tegra: pmc: Prevent racing with cpuilde driver Both PMC and cpuidle drivers are probed at the same init level and cpuidle depends on the PMC suspend mode. Add new default suspend mode that indicates whether PMC driver has been probed and reset the mode in a case of deferred probe of the PMC driver. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- arch/arm/mach-tegra/pm.c | 2 +- arch/arm/mach-tegra/pm.h | 6 ------ arch/arm/mach-tegra/tegra.c | 2 -- drivers/soc/tegra/pmc.c | 14 +++++++++++++- include/soc/tegra/pm.h | 6 ++++++ 5 files changed, 20 insertions(+), 10 deletions(-) (limited to 'drivers/soc') diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 6452ebf68d40..b21f51b8e19e 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -403,7 +403,7 @@ static const struct platform_suspend_ops tegra_suspend_ops = { .enter = tegra_suspend_enter, }; -void __init tegra_init_suspend(void) +void tegra_pm_init_suspend(void) { enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 81525f5f4a44..e63f96de2825 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -25,10 +25,4 @@ void tegra30_sleep_core_init(void); extern void (*tegra_tear_down_cpu)(void); -#ifdef CONFIG_PM_SLEEP -void tegra_init_suspend(void); -#else -static inline void tegra_init_suspend(void) {} -#endif - #endif /* _MACH_TEGRA_PM_H_ */ diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index c011359bcdb4..ab5008f35803 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -84,8 +84,6 @@ static void __init tegra_dt_init(void) static void __init tegra_dt_init_late(void) { - tegra_init_suspend(); - if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && of_machine_is_compatible("compal,paz00")) tegra_paz00_wifikill_init(); diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index ea62f84d1c8b..50091c4ec948 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -436,7 +436,7 @@ struct tegra_pmc { static struct tegra_pmc *pmc = &(struct tegra_pmc) { .base = NULL, - .suspend_mode = TEGRA_SUSPEND_NONE, + .suspend_mode = TEGRA_SUSPEND_NOT_READY, }; static inline struct tegra_powergate * @@ -1812,6 +1812,7 @@ static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) u32 value, values[2]; if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { + pmc->suspend_mode = TEGRA_SUSPEND_NONE; } else { switch (value) { case 0: @@ -2785,6 +2786,11 @@ static int tegra_pmc_regmap_init(struct tegra_pmc *pmc) return 0; } +static void tegra_pmc_reset_suspend_mode(void *data) +{ + pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; +} + static int tegra_pmc_probe(struct platform_device *pdev) { void __iomem *base; @@ -2803,6 +2809,11 @@ static int tegra_pmc_probe(struct platform_device *pdev) if (err < 0) return err; + err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode, + NULL); + if (err) + return err; + /* take over the memory region from the early initialization */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); @@ -2909,6 +2920,7 @@ static int tegra_pmc_probe(struct platform_device *pdev) tegra_pmc_clock_register(pmc, pdev->dev.of_node); platform_set_drvdata(pdev, pmc); + tegra_pm_init_suspend(); return 0; diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h index 08477d7bfab9..433878927026 100644 --- a/include/soc/tegra/pm.h +++ b/include/soc/tegra/pm.h @@ -14,6 +14,7 @@ enum tegra_suspend_mode { TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */ TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */ TEGRA_MAX_SUSPEND_MODE, + TEGRA_SUSPEND_NOT_READY, }; #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) @@ -28,6 +29,7 @@ void tegra_pm_clear_cpu_in_lp2(void); void tegra_pm_set_cpu_in_lp2(void); int tegra_pm_enter_lp2(void); int tegra_pm_park_secondary_cpu(unsigned long cpu); +void tegra_pm_init_suspend(void); #else static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode) @@ -61,6 +63,10 @@ static inline int tegra_pm_park_secondary_cpu(unsigned long cpu) { return -ENOTSUPP; } + +static inline void tegra_pm_init_suspend(void) +{ +} #endif /* CONFIG_PM_SLEEP */ #endif /* __SOC_TEGRA_PM_H__ */ -- cgit v1.2.3 From a65a4ea1563218b401a9a638a198e2b8165e967a Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Tue, 3 Aug 2021 01:13:33 +0300 Subject: soc/tegra: fuse: Clear fuse->clk on driver probe failure The fuse->clk must be cleared if FUSE driver fails to probe, otherwise tegra_fuse_readl() will crash. It's unlikely to happen in practice, nevertheless let's correct it for completeness. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 3d9da3d359da..2434c570b53c 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -246,6 +246,7 @@ static int tegra_fuse_probe(struct platform_device *pdev) return 0; restore: + fuse->clk = NULL; fuse->base = base; return err; } -- cgit v1.2.3 From 24a15252ff049ca76bdcc51dd445503b88b2c6df Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Tue, 3 Aug 2021 01:13:34 +0300 Subject: soc/tegra: fuse: Add runtime PM support The Tegra FUSE belongs to the core power domain and we're going to enable GENPD support for the core domain. Now FUSE device must be resumed using runtime PM API in order to initialize the FUSE power state. Add runtime PM support to the FUSE driver. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 30 ++++++++++++++++++++++++++++++ drivers/soc/tegra/fuse/fuse-tegra20.c | 10 ++++++---- drivers/soc/tegra/fuse/fuse-tegra30.c | 9 ++++----- 3 files changed, 40 insertions(+), 9 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 2434c570b53c..747237865aff 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -210,6 +211,8 @@ static int tegra_fuse_probe(struct platform_device *pdev) platform_set_drvdata(pdev, fuse); fuse->dev = &pdev->dev; + pm_runtime_enable(&pdev->dev); + if (fuse->soc->probe) { err = fuse->soc->probe(fuse); if (err < 0) @@ -248,13 +251,40 @@ static int tegra_fuse_probe(struct platform_device *pdev) restore: fuse->clk = NULL; fuse->base = base; + pm_runtime_disable(&pdev->dev); return err; } +static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev) +{ + int err; + + err = clk_prepare_enable(fuse->clk); + if (err < 0) { + dev_err(dev, "failed to enable FUSE clock: %d\n", err); + return err; + } + + return 0; +} + +static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev) +{ + clk_disable_unprepare(fuse->clk); + + return 0; +} + +static const struct dev_pm_ops tegra_fuse_pm = { + SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume, + NULL) +}; + static struct platform_driver tegra_fuse_driver = { .driver = { .name = "tegra-fuse", .of_match_table = tegra_fuse_match, + .pm = &tegra_fuse_pm, .suppress_bind_attrs = true, }, .probe = tegra_fuse_probe, diff --git a/drivers/soc/tegra/fuse/fuse-tegra20.c b/drivers/soc/tegra/fuse/fuse-tegra20.c index 16aaa28573ac..cd6a273707fe 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra20.c +++ b/drivers/soc/tegra/fuse/fuse-tegra20.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -46,6 +47,10 @@ static u32 tegra20_fuse_read(struct tegra_fuse *fuse, unsigned int offset) u32 value = 0; int err; + err = pm_runtime_resume_and_get(fuse->dev); + if (err) + return err; + mutex_lock(&fuse->apbdma.lock); fuse->apbdma.config.src_addr = fuse->phys + FUSE_BEGIN + offset; @@ -66,8 +71,6 @@ static u32 tegra20_fuse_read(struct tegra_fuse *fuse, unsigned int offset) reinit_completion(&fuse->apbdma.wait); - clk_prepare_enable(fuse->clk); - dmaengine_submit(dma_desc); dma_async_issue_pending(fuse->apbdma.chan); time_left = wait_for_completion_timeout(&fuse->apbdma.wait, @@ -78,10 +81,9 @@ static u32 tegra20_fuse_read(struct tegra_fuse *fuse, unsigned int offset) else value = *fuse->apbdma.virt; - clk_disable_unprepare(fuse->clk); - out: mutex_unlock(&fuse->apbdma.lock); + pm_runtime_put(fuse->dev); return value; } diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index c1aa7815bd6e..dd03565a39a4 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -52,15 +53,13 @@ static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset) u32 value; int err; - err = clk_prepare_enable(fuse->clk); - if (err < 0) { - dev_err(fuse->dev, "failed to enable FUSE clock: %d\n", err); + err = pm_runtime_resume_and_get(fuse->dev); + if (err) return 0; - } value = readl_relaxed(fuse->base + FUSE_BEGIN + offset); - clk_disable_unprepare(fuse->clk); + pm_runtime_put(fuse->dev); return value; } -- cgit v1.2.3 From 59c6fceb2ecc382c3d20508a235b539bf23af1f0 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Tue, 3 Aug 2021 01:13:35 +0300 Subject: soc/tegra: fuse: Enable fuse clock on suspend for Tegra124 The FUSE clock should be enabled during suspend on Tegra124. Currently clk driver enables it on all SoCs, but FUSE may require a higher core voltage on Tegra30 while enabled. Move the quirk into the FUSE driver and make it specific to Tegra124. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 29 +++++++++++++++++++++++++++++ drivers/soc/tegra/fuse/fuse-tegra20.c | 1 + drivers/soc/tegra/fuse/fuse-tegra30.c | 7 +++++++ drivers/soc/tegra/fuse/fuse.h | 2 ++ 4 files changed, 39 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 747237865aff..f2151815db58 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -275,9 +275,38 @@ static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev) return 0; } +static int __maybe_unused tegra_fuse_suspend(struct device *dev) +{ + int ret; + + /* + * Critical for RAM re-repair operation, which must occur on resume + * from LP1 system suspend and as part of CCPLEX cluster switching. + */ + if (fuse->soc->clk_suspend_on) + ret = pm_runtime_resume_and_get(dev); + else + ret = pm_runtime_force_suspend(dev); + + return ret; +} + +static int __maybe_unused tegra_fuse_resume(struct device *dev) +{ + int ret = 0; + + if (fuse->soc->clk_suspend_on) + pm_runtime_put(dev); + else + ret = pm_runtime_force_resume(dev); + + return ret; +} + static const struct dev_pm_ops tegra_fuse_pm = { SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume) }; static struct platform_driver tegra_fuse_driver = { diff --git a/drivers/soc/tegra/fuse/fuse-tegra20.c b/drivers/soc/tegra/fuse/fuse-tegra20.c index cd6a273707fe..8ec9fc5e5e4b 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra20.c +++ b/drivers/soc/tegra/fuse/fuse-tegra20.c @@ -167,4 +167,5 @@ const struct tegra_fuse_soc tegra20_fuse_soc = { .probe = tegra20_fuse_probe, .info = &tegra20_fuse_info, .soc_attr_group = &tegra_soc_attr_group, + .clk_suspend_on = false, }; diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index dd03565a39a4..b071d433d74f 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -112,6 +112,7 @@ const struct tegra_fuse_soc tegra30_fuse_soc = { .speedo_init = tegra30_init_speedo_data, .info = &tegra30_fuse_info, .soc_attr_group = &tegra_soc_attr_group, + .clk_suspend_on = false, }; #endif @@ -127,6 +128,7 @@ const struct tegra_fuse_soc tegra114_fuse_soc = { .speedo_init = tegra114_init_speedo_data, .info = &tegra114_fuse_info, .soc_attr_group = &tegra_soc_attr_group, + .clk_suspend_on = false, }; #endif @@ -208,6 +210,7 @@ const struct tegra_fuse_soc tegra124_fuse_soc = { .lookups = tegra124_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra124_fuse_lookups), .soc_attr_group = &tegra_soc_attr_group, + .clk_suspend_on = true, }; #endif @@ -294,6 +297,7 @@ const struct tegra_fuse_soc tegra210_fuse_soc = { .lookups = tegra210_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra210_fuse_lookups), .soc_attr_group = &tegra_soc_attr_group, + .clk_suspend_on = false, }; #endif @@ -324,6 +328,7 @@ const struct tegra_fuse_soc tegra186_fuse_soc = { .lookups = tegra186_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra186_fuse_lookups), .soc_attr_group = &tegra_soc_attr_group, + .clk_suspend_on = false, }; #endif @@ -354,6 +359,7 @@ const struct tegra_fuse_soc tegra194_fuse_soc = { .lookups = tegra194_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra194_fuse_lookups), .soc_attr_group = &tegra194_soc_attr_group, + .clk_suspend_on = false, }; #endif @@ -384,5 +390,6 @@ const struct tegra_fuse_soc tegra234_fuse_soc = { .lookups = tegra234_fuse_lookups, .num_lookups = ARRAY_SIZE(tegra234_fuse_lookups), .soc_attr_group = &tegra194_soc_attr_group, + .clk_suspend_on = false, }; #endif diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h index e057a58e2060..de58feba0435 100644 --- a/drivers/soc/tegra/fuse/fuse.h +++ b/drivers/soc/tegra/fuse/fuse.h @@ -34,6 +34,8 @@ struct tegra_fuse_soc { unsigned int num_lookups; const struct attribute_group *soc_attr_group; + + bool clk_suspend_on; }; struct tegra_fuse { -- cgit v1.2.3 From 148bcca9ad0488d623aa36b21ac152bb056a1ae4 Mon Sep 17 00:00:00 2001 From: Len Baker Date: Sun, 8 Aug 2021 14:50:11 +0200 Subject: soc: renesas: Prefer memcpy() over strcpy() strcpy() performs no bounds checking on the destination buffer. This could result in linear overflows beyond the end of the buffer, leading to all kinds of misbehaviors. So, use memcpy() as a safe replacement. This is a previous step in the path to remove the strcpy() function entirely from the kernel. Signed-off-by: Len Baker Link: https://lore.kernel.org/r/20210808125012.4715-3-len.baker@gmx.com Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/r8a779a0-sysc.c | 6 ++++-- drivers/soc/renesas/rcar-sysc.c | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/renesas/r8a779a0-sysc.c b/drivers/soc/renesas/r8a779a0-sysc.c index d464ffa1be33..7410b9fa9846 100644 --- a/drivers/soc/renesas/r8a779a0-sysc.c +++ b/drivers/soc/renesas/r8a779a0-sysc.c @@ -404,19 +404,21 @@ static int __init r8a779a0_sysc_pd_init(void) for (i = 0; i < info->num_areas; i++) { const struct r8a779a0_sysc_area *area = &info->areas[i]; struct r8a779a0_sysc_pd *pd; + size_t n; if (!area->name) { /* Skip NULLified area */ continue; } - pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL); + n = strlen(area->name) + 1; + pd = kzalloc(sizeof(*pd) + n, GFP_KERNEL); if (!pd) { error = -ENOMEM; goto out_put; } - strcpy(pd->name, area->name); + memcpy(pd->name, area->name, n); pd->genpd.name = pd->name; pd->pdr = area->pdr; pd->flags = area->flags; diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c index 53387a72ca00..b0a80de34c98 100644 --- a/drivers/soc/renesas/rcar-sysc.c +++ b/drivers/soc/renesas/rcar-sysc.c @@ -396,19 +396,21 @@ static int __init rcar_sysc_pd_init(void) for (i = 0; i < info->num_areas; i++) { const struct rcar_sysc_area *area = &info->areas[i]; struct rcar_sysc_pd *pd; + size_t n; if (!area->name) { /* Skip NULLified area */ continue; } - pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL); + n = strlen(area->name) + 1; + pd = kzalloc(sizeof(*pd) + n, GFP_KERNEL); if (!pd) { error = -ENOMEM; goto out_put; } - strcpy(pd->name, area->name); + memcpy(pd->name, area->name, n); pd->genpd.name = pd->name; pd->ch.chan_offs = area->chan_offs; pd->ch.chan_bit = area->chan_bit; -- cgit v1.2.3 From 28b05a64e47cbceebb8a5f3f643033148d5c06c3 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Thu, 5 Aug 2021 14:01:02 +0200 Subject: soc: rockchip: io-domain: add rk3568 support The io-domain registers on RK3568 SoCs have three separated bits to enable/disable the 1.8v/2.5v/3.3v power. This patch make the write to be a operation, allow rk3568 uses a private register set function. Since the 2.5v mode hasn't been fully validated yet, the driver only sets 1.8v [enable] + 3.3v [disable] for 1.8v mode 1.8v [disable] + 3.3v [enable] for 3.3v mode There is not register order requirement which has been cleared by our IC team. For future reference the full usage matrix including the 2.5V setting is: case V33 V25 V18 result 0 0 0 0 IO safe, but cannot work 1 0 0 1 IO require 1.8V, should < 1.98V, otherwise IO may damage 2 0 1 0 IO require 2.5V, should < 2.75V, otherwise IO may damage 3 0 1 1 Invalid state, should avoid 4 1 0 0 IO require 3.3V, should < 3.63V, otherwise IO may damage 5 1 0 1 IO require 1.8V, should < 1.98V, otherwise IO may damage 6 1 1 0 IO require 2.5V, should < 2.75V, otherwise IO may damage 7 1 1 1 Invalid state, should avoid Signed-off-by: Jianqun Xu Tested-by: Peter Geis [added mode clarification from Jay] Link: https://lore.kernel.org/r/20210805120107.27007-3-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/io-domain.c | 88 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 80 insertions(+), 8 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c index cf8182fc3642..13c446fd33a9 100644 --- a/drivers/soc/rockchip/io-domain.c +++ b/drivers/soc/rockchip/io-domain.c @@ -51,13 +51,11 @@ #define RK3399_PMUGRF_CON0_VSEL BIT(8) #define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9 -struct rockchip_iodomain; +#define RK3568_PMU_GRF_IO_VSEL0 (0x0140) +#define RK3568_PMU_GRF_IO_VSEL1 (0x0144) +#define RK3568_PMU_GRF_IO_VSEL2 (0x0148) -struct rockchip_iodomain_soc_data { - int grf_offset; - const char *supply_names[MAX_SUPPLIES]; - void (*init)(struct rockchip_iodomain *iod); -}; +struct rockchip_iodomain; struct rockchip_iodomain_supply { struct rockchip_iodomain *iod; @@ -66,13 +64,62 @@ struct rockchip_iodomain_supply { int idx; }; +struct rockchip_iodomain_soc_data { + int grf_offset; + const char *supply_names[MAX_SUPPLIES]; + void (*init)(struct rockchip_iodomain *iod); + int (*write)(struct rockchip_iodomain_supply *supply, int uV); +}; + struct rockchip_iodomain { struct device *dev; struct regmap *grf; const struct rockchip_iodomain_soc_data *soc_data; struct rockchip_iodomain_supply supplies[MAX_SUPPLIES]; + int (*write)(struct rockchip_iodomain_supply *supply, int uV); }; +static int rk3568_iodomain_write(struct rockchip_iodomain_supply *supply, int uV) +{ + struct rockchip_iodomain *iod = supply->iod; + u32 is_3v3 = uV > MAX_VOLTAGE_1_8; + u32 val0, val1; + int b; + + switch (supply->idx) { + case 0: /* pmuio1 */ + break; + case 1: /* pmuio2 */ + b = supply->idx; + val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); + b = supply->idx + 4; + val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0); + + regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val0); + regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val1); + break; + case 3: /* vccio2 */ + break; + case 2: /* vccio1 */ + case 4: /* vccio3 */ + case 5: /* vccio4 */ + case 6: /* vccio5 */ + case 7: /* vccio6 */ + case 8: /* vccio7 */ + b = supply->idx - 1; + val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b)); + val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0); + + regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL0, val0); + regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL1, val1); + break; + default: + return -EINVAL; + }; + + return 0; +} + static int rockchip_iodomain_write(struct rockchip_iodomain_supply *supply, int uV) { @@ -136,7 +183,7 @@ static int rockchip_iodomain_notify(struct notifier_block *nb, return NOTIFY_BAD; } - ret = rockchip_iodomain_write(supply, uV); + ret = supply->iod->write(supply, uV); if (ret && event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE) return NOTIFY_BAD; @@ -398,6 +445,22 @@ static const struct rockchip_iodomain_soc_data soc_data_rk3399_pmu = { .init = rk3399_pmu_iodomain_init, }; +static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = { + .grf_offset = 0x140, + .supply_names = { + "pmuio1", + "pmuio2", + "vccio1", + "vccio2", + "vccio3", + "vccio4", + "vccio5", + "vccio6", + "vccio7", + }, + .write = rk3568_iodomain_write, +}; + static const struct rockchip_iodomain_soc_data soc_data_rv1108 = { .grf_offset = 0x404, .supply_names = { @@ -469,6 +532,10 @@ static const struct of_device_id rockchip_iodomain_match[] = { .compatible = "rockchip,rk3399-pmu-io-voltage-domain", .data = &soc_data_rk3399_pmu }, + { + .compatible = "rockchip,rk3568-pmu-io-voltage-domain", + .data = &soc_data_rk3568_pmu + }, { .compatible = "rockchip,rv1108-io-voltage-domain", .data = &soc_data_rv1108 @@ -502,6 +569,11 @@ static int rockchip_iodomain_probe(struct platform_device *pdev) match = of_match_node(rockchip_iodomain_match, np); iod->soc_data = match->data; + if (iod->soc_data->write) + iod->write = iod->soc_data->write; + else + iod->write = rockchip_iodomain_write; + parent = pdev->dev.parent; if (parent && parent->of_node) { iod->grf = syscon_node_to_regmap(parent->of_node); @@ -562,7 +634,7 @@ static int rockchip_iodomain_probe(struct platform_device *pdev) supply->reg = reg; supply->nb.notifier_call = rockchip_iodomain_notify; - ret = rockchip_iodomain_write(supply, uV); + ret = iod->write(supply, uV); if (ret) { supply->reg = NULL; goto unreg_notify; -- cgit v1.2.3 From 9e5747c57807ad8a04c356340190cfdd0bd54111 Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Thu, 19 Aug 2021 16:29:09 +0800 Subject: soc: rockchip: io-domain: Remove unneeded semicolon Fix the following coccicheck warnings: ./drivers/soc/rockchip/io-domain.c:118:2-3: Unneeded semicolon. Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong Link: https://lore.kernel.org/r/1629361749-97977-1-git-send-email-jiapeng.chong@linux.alibaba.com Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/io-domain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c index 13c446fd33a9..9df513d1219b 100644 --- a/drivers/soc/rockchip/io-domain.c +++ b/drivers/soc/rockchip/io-domain.c @@ -115,7 +115,7 @@ static int rk3568_iodomain_write(struct rockchip_iodomain_supply *supply, int uV break; default: return -EINVAL; - }; + } return 0; } -- cgit v1.2.3