From 3e0cf4d3fc2985beee011e9a1bbb8374fc02c0a0 Mon Sep 17 00:00:00 2001 From: Sunny Luo Date: Thu, 12 Mar 2020 14:31:25 +0100 Subject: spi: meson-spicc: add a linear clock divider support The SPICC controller in Meson-AXG SoC is capable of using a linear clock divider to reach a much fine tuned range of clocks, while the old controller only use a power of two clock divider, result at a more coarse clock range. Also convert the clock registration into Common Clock Framework. Signed-off-by: Neil Armstrong Signed-off-by: Yixun Lan Signed-off-by: Sunny Luo Link: https://lore.kernel.org/r/20200312133131.26430-4-narmstrong@baylibre.com Signed-off-by: Mark Brown --- drivers/spi/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/spi/Kconfig') diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c33ca96b44de..efce98e9844e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -428,6 +428,7 @@ config SPI_FSL_ESPI config SPI_MESON_SPICC tristate "Amlogic Meson SPICC controller" + depends on COMMON_CLK depends on ARCH_MESON || COMPILE_TEST help This enables master mode support for the SPICC (SPI communication -- cgit v1.2.3