From 5dfff995f9cb21c2910e40f5d4da53473356a792 Mon Sep 17 00:00:00 2001 From: Suresh Gupta Date: Mon, 24 Jun 2019 15:22:16 +0800 Subject: usb: phy: Workaround for USB erratum-A005728 PHY_CLK_VALID bit for UTMI PHY in USBDR does not set even if PHY is providing valid clock. Workaround for this involves resetting of PHY and check PHY_CLK_VALID bit multiple times. If PHY_CLK_VALID bit is still not set even after 5 retries, it would be safe to deaclare that PHY clock is not available. This erratum is applicable for USBDR less then ver 2.4. Signed-off-by: Suresh Gupta Signed-off-by: Yinbo Zhu Link: https://lore.kernel.org/r/20190624072219.15258-2-yinbo.zhu@nxp.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/ehci-fsl.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/usb/host/ehci-fsl.h') diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h index cbc422032e50..9d18c6e6ab27 100644 --- a/drivers/usb/host/ehci-fsl.h +++ b/drivers/usb/host/ehci-fsl.h @@ -50,4 +50,7 @@ #define UTMI_PHY_EN (1<<9) #define ULPI_PHY_CLK_SEL (1<<10) #define PHY_CLK_VALID (1<<17) + +/* Retry count for checking UTMI PHY CLK validity */ +#define UTMI_PHY_CLK_VALID_CHK_RETRY 5 #endif /* _EHCI_FSL_H */ -- cgit v1.2.3