From 5aaee69d7fe02d1ffb76b6a31a588efa5f2742e3 Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Wed, 12 Dec 2012 10:37:03 +0200 Subject: OMAPDSS: DISPC: get dss clock rate from dss driver Dispc currently gets dispc's fck with clk_get() and uses clk_get_rate() to get the rate for scaling calculations. This causes a problem with common clock framework, as omapdss uses the dispc functions inside a spinlock, and common clock framework uses a mutex in clk_get_rate(). Looking at the DSS clock tree, the above use of the dispc fck is not quite correct. The DSS_FCLK from PRCM goes to DSS core block, which has a mux to select the clock for DISPC from various options, so the current use of dispc fck bypasses that. Fortunately we never change the dispc clock mux for now. To fix the issue with clk_get_rate(), this patch caches the dss clock rate in dss.c when it is set. Dispc will then ask for the clock rate from dss. While this is not very elegant, it does fix the issue, and it's not totally wrong when considering that the dispc fck actually comes via dss. In the future we should probably look into common clock framework and see if that could be used to represent the DSS clock tree properly. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dss.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/video/omap2/dss/dss.c') diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c index 833f1627dc76..054c2a22b3f1 100644 --- a/drivers/video/omap2/dss/dss.c +++ b/drivers/video/omap2/dss/dss.c @@ -77,6 +77,7 @@ static struct { struct clk *dpll4_m4_ck; struct clk *dss_clk; + unsigned long dss_clk_rate; unsigned long cache_req_pck; unsigned long cache_prate; @@ -489,6 +490,10 @@ int dss_set_clock_div(struct dss_clock_info *cinfo) return -EINVAL; } + dss.dss_clk_rate = clk_get_rate(dss.dss_clk); + + WARN_ONCE(dss.dss_clk_rate != cinfo->fck, "clk rate mismatch"); + DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div); return 0; @@ -502,6 +507,11 @@ unsigned long dss_get_dpll4_rate(void) return 0; } +unsigned long dss_get_dispc_clk_rate(void) +{ + return dss.dss_clk_rate; +} + static int dss_setup_default_clock(void) { unsigned long max_dss_fck, prate; @@ -953,6 +963,8 @@ static int __init omap_dsshw_probe(struct platform_device *pdev) if (r) goto err_runtime_get; + dss.dss_clk_rate = clk_get_rate(dss.dss_clk); + /* Select DPLL */ REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); -- cgit v1.2.3