From 26b7a78c55fbc0e23a7dc19e89fd50f200efc002 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 28 Dec 2006 10:31:48 +0900 Subject: sh: Lazy dcache writeback optimizations. This converts the lazy dcache handling to the model described in Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a bonus, this slightly cuts down on the cache flushing frequency. With that and the PTEA handling out of the way, the update_mmu_cache() implementations can be consolidated, and we no longer have to worry about which configuration the cache is in for the SH7705 case. And finally, explicitly disable the lazy writeback on SMP (SH-4A). Signed-off-by: Paul Mundt --- include/asm-sh/pgtable.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include/asm-sh/pgtable.h') diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h index eba14184baf3..3721a4412cea 100644 --- a/include/asm-sh/pgtable.h +++ b/include/asm-sh/pgtable.h @@ -583,11 +583,6 @@ struct mm_struct; extern unsigned int kobjsize(const void *objp); #endif /* !CONFIG_MMU */ -#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) -#define __HAVE_ARCH_PTEP_GET_AND_CLEAR -extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep); -#endif - extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; extern void paging_init(void); -- cgit v1.2.3