From ff297b8c081bdc60507eaeb1838996e0c67141c8 Mon Sep 17 00:00:00 2001 From: Muli Ben-Yehuda Date: Sat, 21 Jul 2007 17:10:50 +0200 Subject: x86_64: introduce chipset specific ops Calgary and CalIOC2 share most of the same logic. Introduce struct cal_chipset_ops for quirks and tce flush logic which are [akpm@linux-foundation.org: make calgary_chip_ops static] Signed-off-by: Muli Ben-Yehuda Signed-off-by: Andrew Morton Signed-off-by: Andi Kleen Signed-off-by: Linus Torvalds --- include/asm-x86_64/calgary.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'include/asm-x86_64') diff --git a/include/asm-x86_64/calgary.h b/include/asm-x86_64/calgary.h index 4d5747a0923c..458ab19a70f0 100644 --- a/include/asm-x86_64/calgary.h +++ b/include/asm-x86_64/calgary.h @@ -1,7 +1,7 @@ /* * Derived from include/asm-powerpc/iommu.h * - * Copyright (C) IBM Corporation, 2006 + * Copyright IBM Corporation, 2006-2007 * * Author: Jon Mason * Author: Muli Ben-Yehuda @@ -31,6 +31,7 @@ #include struct iommu_table { + struct cal_chipset_ops *chip_ops; /* chipset specific funcs */ unsigned long it_base; /* mapped address of tce table */ unsigned long it_hint; /* Hint for next alloc */ unsigned long *it_map; /* A simple allocation bitmap for now */ @@ -42,6 +43,11 @@ struct iommu_table { unsigned char it_busno; /* Bus number this table belongs to */ }; +struct cal_chipset_ops { + void (*handle_quirks)(struct iommu_table *tbl, struct pci_dev *dev); + void (*tce_cache_blast)(struct iommu_table *tbl); +}; + #define TCE_TABLE_SIZE_UNSPECIFIED ~0 #define TCE_TABLE_SIZE_64K 0 #define TCE_TABLE_SIZE_128K 1 -- cgit v1.2.3