From 18df02fb79cb20ba4de1e02e1df41ba83f8b9bec Mon Sep 17 00:00:00 2001 From: Daniel Mack <daniel@zonque.org> Date: Sun, 17 Jun 2018 14:05:34 +0200 Subject: dts: clk: add devicetree bindings for MAX9485 This patch adds the devicetree bindings for MAX9485, a programmable audio clock generator. Signed-off-by: Daniel Mack <daniel@zonque.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> --- include/dt-bindings/clock/maxim,max9485.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 include/dt-bindings/clock/maxim,max9485.h (limited to 'include/dt-bindings/clock') diff --git a/include/dt-bindings/clock/maxim,max9485.h b/include/dt-bindings/clock/maxim,max9485.h new file mode 100644 index 000000000000..185b09ce1869 --- /dev/null +++ b/include/dt-bindings/clock/maxim,max9485.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2018 Daniel Mack + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_MAX9485_CLK_H +#define __DT_BINDINGS_MAX9485_CLK_H + +#define MAX9485_MCLKOUT 0 +#define MAX9485_CLKOUT 1 +#define MAX9485_CLKOUT1 2 +#define MAX9485_CLKOUT2 3 + +#endif /* __DT_BINDINGS_MAX9485_CLK_H */ -- cgit v1.2.3 From fc20654389364a55eeab837244b24f8da75009f6 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik <robert.jarzmik@free.fr> Date: Wed, 27 Jun 2018 21:41:23 +0200 Subject: clk: pxa: export 32kHz PLL This clock is especially used by the RTC driver, so export it so that devicetree users can use it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@kernel.org> --- drivers/clk/pxa/clk-pxa25x.c | 6 ++++-- drivers/clk/pxa/clk-pxa27x.c | 7 ++++--- drivers/clk/pxa/clk-pxa3xx.c | 7 ++++--- include/dt-bindings/clock/pxa-clock.h | 3 ++- 4 files changed, 14 insertions(+), 9 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/pxa/clk-pxa25x.c b/drivers/clk/pxa/clk-pxa25x.c index 6416c1f8e632..e88f8e01fe3a 100644 --- a/drivers/clk/pxa/clk-pxa25x.c +++ b/drivers/clk/pxa/clk-pxa25x.c @@ -292,8 +292,10 @@ static void __init pxa25x_register_plls(void) { clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL, CLK_GET_RATE_NOCACHE, 3686400); - clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, - CLK_GET_RATE_NOCACHE, 32768); + clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL, + clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, + CLK_GET_RATE_NOCACHE, + 32768)); clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0); clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz", 0, 26, 1); diff --git a/drivers/clk/pxa/clk-pxa27x.c b/drivers/clk/pxa/clk-pxa27x.c index 25a30194d27a..d40b63e7bbce 100644 --- a/drivers/clk/pxa/clk-pxa27x.c +++ b/drivers/clk/pxa/clk-pxa27x.c @@ -314,9 +314,10 @@ static void __init pxa27x_register_plls(void) clk_register_fixed_rate(NULL, "osc_13mhz", NULL, CLK_GET_RATE_NOCACHE, 13 * MHz); - clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, - CLK_GET_RATE_NOCACHE, - 32768 * KHz); + clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL, + clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, + CLK_GET_RATE_NOCACHE, + 32768 * KHz)); clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0); clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1); } diff --git a/drivers/clk/pxa/clk-pxa3xx.c b/drivers/clk/pxa/clk-pxa3xx.c index 2d126df2bccd..7aa120c3bd08 100644 --- a/drivers/clk/pxa/clk-pxa3xx.c +++ b/drivers/clk/pxa/clk-pxa3xx.c @@ -286,9 +286,10 @@ static void __init pxa3xx_register_plls(void) clk_register_fixed_rate(NULL, "osc_13mhz", NULL, CLK_GET_RATE_NOCACHE, 13 * MHz); - clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, - CLK_GET_RATE_NOCACHE, - 32768); + clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL, + clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, + CLK_GET_RATE_NOCACHE, + 32768)); clk_register_fixed_rate(NULL, "ring_osc_120mhz", NULL, CLK_GET_RATE_NOCACHE, 120 * MHz); diff --git a/include/dt-bindings/clock/pxa-clock.h b/include/dt-bindings/clock/pxa-clock.h index e65803b1dc7e..0b0fd2b01538 100644 --- a/include/dt-bindings/clock/pxa-clock.h +++ b/include/dt-bindings/clock/pxa-clock.h @@ -72,6 +72,7 @@ #define CLK_USIM 58 #define CLK_USIM1 59 #define CLK_USMI0 60 -#define CLK_MAX 61 +#define CLK_OSC32k768 61 +#define CLK_MAX 62 #endif -- cgit v1.2.3 From cd88259a7215e0737f8ef2c2842f41922ae87d8d Mon Sep 17 00:00:00 2001 From: Lei YU <mine260309@gmail.com> Date: Tue, 26 Jun 2018 09:55:25 +0800 Subject: clk: aspeed: Fix SDCLK name The SDCLK was named SDCLKCLK, and no one has used this yet. Fix it. Signed-off-by: Lei YU <mine260309@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> --- drivers/clk/clk-aspeed.c | 2 +- include/dt-bindings/clock/aspeed-clock.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 38b366b00c57..f49c6842c604 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -109,7 +109,7 @@ static const struct aspeed_gate_data aspeed_gates[] = { [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */ [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */ - [ASPEED_CLK_GATE_SDCLKCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ + [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ }; diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 44761849fcbe..f43738607d77 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -25,7 +25,7 @@ #define ASPEED_CLK_GATE_RSACLK 19 #define ASPEED_CLK_GATE_UART3CLK 20 #define ASPEED_CLK_GATE_UART4CLK 21 -#define ASPEED_CLK_GATE_SDCLKCLK 22 +#define ASPEED_CLK_GATE_SDCLK 22 #define ASPEED_CLK_GATE_LHCCLK 23 #define ASPEED_CLK_HPLL 24 #define ASPEED_CLK_AHB 25 -- cgit v1.2.3 From 9d8108f9f3cb996a9677223fcd1feeb1f3e05566 Mon Sep 17 00:00:00 2001 From: Anson Huang <Anson.Huang@nxp.com> Date: Fri, 22 Jun 2018 14:32:33 +0800 Subject: clk: imx6sll: add GPIO LPCGs According to Reference Manual Rev.0, 06/2017, there are GPIO LPCGs defined in CCM CCGRs, add them into clock tree. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> --- drivers/clk/imx/clk-imx6sll.c | 6 ++++++ include/dt-bindings/clock/imx6sll-clock.h | 9 ++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings/clock') diff --git a/drivers/clk/imx/clk-imx6sll.c b/drivers/clk/imx/clk-imx6sll.c index 3651c77fbabe..627064597af9 100644 --- a/drivers/clk/imx/clk-imx6sll.c +++ b/drivers/clk/imx/clk-imx6sll.c @@ -253,6 +253,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) clks[IMX6SLL_CLK_DCP] = imx_clk_gate2("dcp", "ahb", base + 0x68, 10); clks[IMX6SLL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28); clks[IMX6SLL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28); + clks[IMX6SLL_CLK_GPIO2] = imx_clk_gate2("gpio2", "ipg", base + 0x68, 30); /* CCGR1 */ clks[IMX6SLL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); @@ -267,13 +268,17 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) clks[IMX6SLL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22); clks[IMX6SLL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24); clks[IMX6SLL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24); + clks[IMX6SLL_CLK_GPIO1] = imx_clk_gate2("gpio1", "ipg", base + 0x6c, 26); + clks[IMX6SLL_CLK_GPIO5] = imx_clk_gate2("gpio5", "ipg", base + 0x6c, 30); /* CCGR2 */ + clks[IMX6SLL_CLK_GPIO6] = imx_clk_gate2("gpio6", "ipg", base + 0x70, 0); clks[IMX6SLL_CLK_CSI] = imx_clk_gate2("csi", "axi", base + 0x70, 2); clks[IMX6SLL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); clks[IMX6SLL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); clks[IMX6SLL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); clks[IMX6SLL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); + clks[IMX6SLL_CLK_GPIO3] = imx_clk_gate2("gpio3", "ipg", base + 0x70, 26); clks[IMX6SLL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28); clks[IMX6SLL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30); @@ -283,6 +288,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) clks[IMX6SLL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_aclk", "axi", base + 0x74, 4); clks[IMX6SLL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_podf", base + 0x74, 4); clks[IMX6SLL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10); + clks[IMX6SLL_CLK_GPIO4] = imx_clk_gate2("gpio4", "ipg", base + 0x74, 12); clks[IMX6SLL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16); clks[IMX6SLL_CLK_MMDC_P0_FAST] = imx_clk_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20, CLK_IS_CRITICAL); clks[IMX6SLL_CLK_MMDC_P0_IPG] = imx_clk_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL); diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h index 151111e68f4f..1036475f997d 100644 --- a/include/dt-bindings/clock/imx6sll-clock.h +++ b/include/dt-bindings/clock/imx6sll-clock.h @@ -197,6 +197,13 @@ #define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 #define IMX6SLL_CLK_EXTERN_AUDIO 172 -#define IMX6SLL_CLK_END 173 +#define IMX6SLL_CLK_GPIO1 173 +#define IMX6SLL_CLK_GPIO2 174 +#define IMX6SLL_CLK_GPIO3 175 +#define IMX6SLL_CLK_GPIO4 176 +#define IMX6SLL_CLK_GPIO5 177 +#define IMX6SLL_CLK_GPIO6 178 + +#define IMX6SLL_CLK_END 179 #endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ -- cgit v1.2.3