From 4585945bf1d348d006f7270beea3dae09fee3413 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Mon, 30 Nov 2015 22:07:53 +0100 Subject: clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output The configurable hdmi_ref output of the PLL block is derived from the tvdpll_594m clock signal via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module. Signed-off-by: Philipp Zabel Acked-by: James Liao Acked-by: Stephen Boyd --- include/dt-bindings/clock/mt8173-clk.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index 7956ba1bc974..6094bf7e50ab 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -176,7 +176,8 @@ #define CLK_APMIXED_LVDSPLL 13 #define CLK_APMIXED_MSDCPLL2 14 #define CLK_APMIXED_REF2USB_TX 15 -#define CLK_APMIXED_NR_CLK 16 +#define CLK_APMIXED_HDMI_REF 16 +#define CLK_APMIXED_NR_CLK 17 /* INFRA_SYS */ -- cgit v1.2.3