From 2d5f60afd2b6fa9c583c4f01989f734e00e090ae Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 12 Sep 2019 16:26:07 +0300 Subject: dt-bindings: clk: add omap5 iva clkctrl definitions OMAP5 device contains an IVA subsystem (Image and Video Accelerator.) IVA subsystem clkctrl definitions are currently missing, so add them. Signed-off-by: Tero Kristo --- include/dt-bindings/clock/omap5.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h index e5411938983c..ba672064ccb4 100644 --- a/include/dt-bindings/clock/omap5.h +++ b/include/dt-bindings/clock/omap5.h @@ -86,6 +86,10 @@ #define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) #define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) +/* iva clocks */ +#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) +#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) + /* dss clocks */ #define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -- cgit v1.2.3 From 5b468cc4b88073356f79cf779207d64b65a914f0 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 10 Oct 2019 12:36:54 +1030 Subject: dt-bindings: clock: Add AST2500 RMII RCLK definitions The AST2500 has an explicit gate for the RMII RCLK for each of the two MACs. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Joel Stanley --- include/dt-bindings/clock/aspeed-clock.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index f43738607d77..9ff4f6e4558c 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -39,6 +39,8 @@ #define ASPEED_CLK_BCLK 33 #define ASPEED_CLK_MPLL 34 #define ASPEED_CLK_24M 35 +#define ASPEED_CLK_MAC1RCLK 36 +#define ASPEED_CLK_MAC2RCLK 37 #define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_MCTP 1 -- cgit v1.2.3 From d8d9ad83a497f78edd4016df0919a49628dcafbc Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 10 Oct 2019 12:37:24 +1030 Subject: dt-bindings: clock: Add AST2600 RMII RCLK gate definitions The AST2600 has an explicit gate for the RMII RCLK for each of the four MACs. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Acked-by: Rob Herring Signed-off-by: Joel Stanley --- include/dt-bindings/clock/ast2600-clock.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 38074a5f7296..62b9520a00fd 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -83,6 +83,10 @@ #define ASPEED_CLK_MAC12 64 #define ASPEED_CLK_MAC34 65 #define ASPEED_CLK_USBPHY_40M 66 +#define ASPEED_CLK_MAC1RCLK 67 +#define ASPEED_CLK_MAC2RCLK 68 +#define ASPEED_CLK_MAC3RCLK 69 +#define ASPEED_CLK_MAC4RCLK 70 /* Only list resets here that are not part of a gate */ #define ASPEED_RESET_ADC 55 -- cgit v1.2.3 From 4441b57ec27e35a86337b3197c62b3d6be9695b2 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Thu, 24 Oct 2019 00:13:28 +0200 Subject: clk: sunxi-ng: h3: Export MBUS clock MBUS clock will be referenced in MBUS controller node. Export it. Acked-by: Maxime Ripard Acked-by: Rob Herring Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard --- drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 4 ---- include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +- 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'include/dt-bindings') diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h index b6e2680ef354..d8c38447e11b 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h @@ -48,10 +48,6 @@ /* Some more module clocks are exported */ -#define CLK_MBUS 113 - -/* And the GPU module clock is exported */ - #define CLK_NUMBER_H3 (CLK_GPU + 1) #define CLK_NUMBER_H5 (CLK_BUS_SCR1 + 1) diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h index c5f7e9a70968..30d2d15373a2 100644 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h @@ -143,7 +143,7 @@ #define CLK_AVS 110 #define CLK_HDMI 111 #define CLK_HDMI_DDC 112 - +#define CLK_MBUS 113 #define CLK_GPU 114 /* New clocks imported in H5 */ -- cgit v1.2.3 From 6cdef2738db031bfd06e3bc1c7d3c8cd16846d9e Mon Sep 17 00:00:00 2001 From: Govind Singh Date: Fri, 11 Oct 2019 18:59:28 +0530 Subject: clk: qcom: Add Q6SSTOP clock controller for QCS404 Add support for the Q6SSTOP clock control used on qcs404 based devices. This would allow wcss remoteproc driver to control the required WCSS Q6SSTOP clock/reset controls to bring the subsystem out of reset and shutdown the WCSS Q6DSP. Signed-off-by: Govind Singh Link: https://lkml.kernel.org/r/20191011132928.9388-3-govinds@codeaurora.org [sboyd@kernel.org: Sort makefile] Signed-off-by: Stephen Boyd --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/q6sstop-qcs404.c | 223 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h | 18 ++ 4 files changed, 250 insertions(+) create mode 100644 drivers/clk/qcom/q6sstop-qcs404.c create mode 100644 include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h (limited to 'include/dt-bindings') diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 32dbb4f09492..5e2ef37168f7 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -248,6 +248,14 @@ config QCS_TURING_404 Support for the Turing Clock Controller on QCS404, provides clocks and resets for the Turing subsystem. +config QCS_Q6SSTOP_404 + tristate "QCS404 Q6SSTOP Clock Controller" + select QCS_GCC_404 + help + Support for the Q6SSTOP clock controller on QCS404 devices. + Say Y if you want to use the Q6SSTOP branch clocks of the WCSS clock + controller to reset the Q6SSTOP subsystem. + config SDM_GCC_845 tristate "SDM845 Global Clock Controller" select QCOM_GDSC diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 4a813b4055d0..5ba05e2066c2 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o +obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o diff --git a/drivers/clk/qcom/q6sstop-qcs404.c b/drivers/clk/qcom/q6sstop-qcs404.c new file mode 100644 index 000000000000..723f932fbf7d --- /dev/null +++ b/drivers/clk/qcom/q6sstop-qcs404.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-regmap.h" +#include "clk-branch.h" +#include "common.h" +#include "reset.h" + +static struct clk_branch lcc_ahbfabric_cbc_clk = { + .halt_reg = 0x1b004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1b004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_ahbfabric_cbc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lcc_q6ss_ahbs_cbc_clk = { + .halt_reg = 0x22000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x22000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_q6ss_ahbs_cbc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lcc_q6ss_tcm_slave_cbc_clk = { + .halt_reg = 0x1c000, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x1c000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_q6ss_tcm_slave_cbc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lcc_q6ss_ahbm_cbc_clk = { + .halt_reg = 0x22004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x22004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_q6ss_ahbm_cbc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lcc_q6ss_axim_cbc_clk = { + .halt_reg = 0x1c004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x1c004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_q6ss_axim_cbc_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lcc_q6ss_bcr_sleep_clk = { + .halt_reg = 0x6004, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x6004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "lcc_q6ss_bcr_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +/* TCSR clock */ +static struct clk_branch tcsr_lcc_csr_cbcr_clk = { + .halt_reg = 0x8008, + .halt_check = BRANCH_VOTED, + .clkr = { + .enable_reg = 0x8008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "tcsr_lcc_csr_cbcr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct regmap_config q6sstop_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static struct clk_regmap *q6sstop_qcs404_clocks[] = { + [LCC_AHBFABRIC_CBC_CLK] = &lcc_ahbfabric_cbc_clk.clkr, + [LCC_Q6SS_AHBS_CBC_CLK] = &lcc_q6ss_ahbs_cbc_clk.clkr, + [LCC_Q6SS_TCM_SLAVE_CBC_CLK] = &lcc_q6ss_tcm_slave_cbc_clk.clkr, + [LCC_Q6SS_AHBM_CBC_CLK] = &lcc_q6ss_ahbm_cbc_clk.clkr, + [LCC_Q6SS_AXIM_CBC_CLK] = &lcc_q6ss_axim_cbc_clk.clkr, + [LCC_Q6SS_BCR_SLEEP_CLK] = &lcc_q6ss_bcr_sleep_clk.clkr, +}; + +static const struct qcom_reset_map q6sstop_qcs404_resets[] = { + [Q6SSTOP_BCR_RESET] = { 0x6000 }, +}; + +static const struct qcom_cc_desc q6sstop_qcs404_desc = { + .config = &q6sstop_regmap_config, + .clks = q6sstop_qcs404_clocks, + .num_clks = ARRAY_SIZE(q6sstop_qcs404_clocks), + .resets = q6sstop_qcs404_resets, + .num_resets = ARRAY_SIZE(q6sstop_qcs404_resets), +}; + +static struct clk_regmap *tcsr_qcs404_clocks[] = { + [TCSR_Q6SS_LCC_CBCR_CLK] = &tcsr_lcc_csr_cbcr_clk.clkr, +}; + +static const struct qcom_cc_desc tcsr_qcs404_desc = { + .config = &q6sstop_regmap_config, + .clks = tcsr_qcs404_clocks, + .num_clks = ARRAY_SIZE(tcsr_qcs404_clocks), +}; + +static const struct of_device_id q6sstopcc_qcs404_match_table[] = { + { .compatible = "qcom,qcs404-q6sstopcc" }, + { } +}; +MODULE_DEVICE_TABLE(of, q6sstopcc_qcs404_match_table); + +static int q6sstopcc_qcs404_probe(struct platform_device *pdev) +{ + const struct qcom_cc_desc *desc; + int ret; + + pm_runtime_enable(&pdev->dev); + ret = pm_clk_create(&pdev->dev); + if (ret) + goto disable_pm_runtime; + + ret = pm_clk_add(&pdev->dev, NULL); + if (ret < 0) { + dev_err(&pdev->dev, "failed to acquire iface clock\n"); + goto destroy_pm_clk; + } + + q6sstop_regmap_config.name = "q6sstop_tcsr"; + desc = &tcsr_qcs404_desc; + + ret = qcom_cc_probe_by_index(pdev, 1, desc); + if (ret) + goto destroy_pm_clk; + + q6sstop_regmap_config.name = "q6sstop_cc"; + desc = &q6sstop_qcs404_desc; + + ret = qcom_cc_probe_by_index(pdev, 0, desc); + if (ret) + goto destroy_pm_clk; + + return 0; + +destroy_pm_clk: + pm_clk_destroy(&pdev->dev); + +disable_pm_runtime: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int q6sstopcc_qcs404_remove(struct platform_device *pdev) +{ + pm_clk_destroy(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct dev_pm_ops q6sstopcc_pm_ops = { + SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static struct platform_driver q6sstopcc_qcs404_driver = { + .probe = q6sstopcc_qcs404_probe, + .remove = q6sstopcc_qcs404_remove, + .driver = { + .name = "qcs404-q6sstopcc", + .of_match_table = q6sstopcc_qcs404_match_table, + .pm = &q6sstopcc_pm_ops, + }, +}; + +module_platform_driver(q6sstopcc_qcs404_driver); + +MODULE_DESCRIPTION("QTI QCS404 Q6SSTOP Clock Controller Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h b/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h new file mode 100644 index 000000000000..c6f5290f0914 --- /dev/null +++ b/include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H +#define _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H + +#define LCC_AHBFABRIC_CBC_CLK 0 +#define LCC_Q6SS_AHBS_CBC_CLK 1 +#define LCC_Q6SS_TCM_SLAVE_CBC_CLK 2 +#define LCC_Q6SS_AHBM_CBC_CLK 3 +#define LCC_Q6SS_AXIM_CBC_CLK 4 +#define LCC_Q6SS_BCR_SLEEP_CLK 5 +#define TCSR_Q6SS_LCC_CBCR_CLK 6 + +#define Q6SSTOP_BCR_RESET 1 +#endif -- cgit v1.2.3 From 8b9e0562f330ac20f0e77c0feb38cc7953274d7f Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 14 Oct 2019 15:53:07 +0530 Subject: dt-bindings: clock: Add sc7180 GCC clock binding Add device tree bindings for global clock subsystem clock controller for Qualcomm Technology Inc's SC7180 SoCs. Signed-off-by: Taniya Das Link: https://lkml.kernel.org/r/20191014102308.27441-5-tdas@codeaurora.org Reviewed-by: Rob Herring [sboyd@kernel.org: Reword subject to make sc7180 specific, sort compatible] Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gcc.yaml | 14 ++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 +++++++++++++++++++++ 2 files changed, 169 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,gcc-sc7180.h (limited to 'include/dt-bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index b3ef1e24e91a..e73a56fb60ca 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -33,6 +33,7 @@ properties: - qcom,gcc-msm8998 - qcom,gcc-mdm9615 - qcom,gcc-qcs404 + - qcom,gcc-sc7180 - qcom,gcc-sdm630 - qcom,gcc-sdm660 - qcom,gcc-sdm845 @@ -118,6 +119,7 @@ else: contains: enum: - qcom,gcc-sm8150 + - qcom,gcc-sc7180 then: required: - clocks @@ -171,4 +173,16 @@ examples: #reset-cells = <1>; #power-domain-cells = <1>; }; + + # Example of GCC with clock nodes properties for SC7180: + - | + clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0x100000 0x1f0000>; + clocks = <&rpmhcc 0>, <&rpmhcc 1>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; ... diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h new file mode 100644 index 000000000000..e8029b2e92d7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H + +/* GCC clocks */ +#define GCC_GPLL0_MAIN_DIV_CDIV 0 +#define GPLL0 1 +#define GPLL0_OUT_EVEN 2 +#define GPLL1 3 +#define GPLL4 4 +#define GPLL6 5 +#define GPLL7 6 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 7 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8 +#define GCC_BOOT_ROM_AHB_CLK 9 +#define GCC_CAMERA_AHB_CLK 10 +#define GCC_CAMERA_HF_AXI_CLK 11 +#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12 +#define GCC_CAMERA_XO_CLK 13 +#define GCC_CE1_AHB_CLK 14 +#define GCC_CE1_AXI_CLK 15 +#define GCC_CE1_CLK 16 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 +#define GCC_CPUSS_AHB_CLK 18 +#define GCC_CPUSS_AHB_CLK_SRC 19 +#define GCC_CPUSS_GNOC_CLK 20 +#define GCC_CPUSS_RBCPR_CLK 21 +#define GCC_DDRSS_GPU_AXI_CLK 22 +#define GCC_DISP_AHB_CLK 23 +#define GCC_DISP_GPLL0_CLK_SRC 24 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 25 +#define GCC_DISP_HF_AXI_CLK 26 +#define GCC_DISP_THROTTLE_HF_AXI_CLK 27 +#define GCC_DISP_XO_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP1_CLK_SRC 30 +#define GCC_GP2_CLK 31 +#define GCC_GP2_CLK_SRC 32 +#define GCC_GP3_CLK 33 +#define GCC_GP3_CLK_SRC 34 +#define GCC_GPU_CFG_AHB_CLK 35 +#define GCC_GPU_GPLL0_CLK_SRC 36 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 37 +#define GCC_GPU_MEMNOC_GFX_CLK 38 +#define GCC_GPU_SNOC_DVM_GFX_CLK 39 +#define GCC_NPU_AXI_CLK 40 +#define GCC_NPU_BWMON_AXI_CLK 41 +#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42 +#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43 +#define GCC_NPU_CFG_AHB_CLK 44 +#define GCC_NPU_DMA_CLK 45 +#define GCC_NPU_GPLL0_CLK_SRC 46 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 47 +#define GCC_PDM2_CLK 48 +#define GCC_PDM2_CLK_SRC 49 +#define GCC_PDM_AHB_CLK 50 +#define GCC_PDM_XO4_CLK 51 +#define GCC_PRNG_AHB_CLK 52 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53 +#define GCC_QSPI_CORE_CLK 54 +#define GCC_QSPI_CORE_CLK_SRC 55 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56 +#define GCC_QUPV3_WRAP0_CORE_CLK 57 +#define GCC_QUPV3_WRAP0_S0_CLK 58 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59 +#define GCC_QUPV3_WRAP0_S1_CLK 60 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61 +#define GCC_QUPV3_WRAP0_S2_CLK 62 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63 +#define GCC_QUPV3_WRAP0_S3_CLK 64 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65 +#define GCC_QUPV3_WRAP0_S4_CLK 66 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67 +#define GCC_QUPV3_WRAP0_S5_CLK 68 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70 +#define GCC_QUPV3_WRAP1_CORE_CLK 71 +#define GCC_QUPV3_WRAP1_S0_CLK 72 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73 +#define GCC_QUPV3_WRAP1_S1_CLK 74 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75 +#define GCC_QUPV3_WRAP1_S2_CLK 76 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77 +#define GCC_QUPV3_WRAP1_S3_CLK 78 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79 +#define GCC_QUPV3_WRAP1_S4_CLK 80 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81 +#define GCC_QUPV3_WRAP1_S5_CLK 82 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87 +#define GCC_SDCC1_AHB_CLK 88 +#define GCC_SDCC1_APPS_CLK 89 +#define GCC_SDCC1_APPS_CLK_SRC 90 +#define GCC_SDCC1_ICE_CORE_CLK 91 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 92 +#define GCC_SDCC2_AHB_CLK 93 +#define GCC_SDCC2_APPS_CLK 94 +#define GCC_SDCC2_APPS_CLK_SRC 95 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96 +#define GCC_UFS_MEM_CLKREF_CLK 97 +#define GCC_UFS_PHY_AHB_CLK 98 +#define GCC_UFS_PHY_AXI_CLK 99 +#define GCC_UFS_PHY_AXI_CLK_SRC 100 +#define GCC_UFS_PHY_ICE_CORE_CLK 101 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 +#define GCC_UFS_PHY_PHY_AUX_CLK 103 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108 +#define GCC_USB30_PRIM_MASTER_CLK 109 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 +#define GCC_USB30_PRIM_SLEEP_CLK 113 +#define GCC_USB3_PRIM_CLKREF_CLK 114 +#define GCC_USB3_PRIM_PHY_AUX_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119 +#define GCC_VIDEO_AHB_CLK 120 +#define GCC_VIDEO_AXI_CLK 121 +#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122 +#define GCC_VIDEO_THROTTLE_AXI_CLK 123 +#define GCC_VIDEO_XO_CLK 124 + +/* GCC resets */ +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_UFS_PHY_BCR 2 +#define GCC_USB30_PRIM_BCR 3 +#define GCC_USB3_DP_PHY_PRIM_BCR 4 +#define GCC_USB3_DP_PHY_SEC_BCR 5 +#define GCC_USB3_PHY_PRIM_BCR 6 +#define GCC_USB3_PHY_SEC_BCR 7 +#define GCC_USB3PHY_PHY_PRIM_BCR 8 +#define GCC_USB3PHY_PHY_SEC_BCR 9 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10 + +/* GCC GDSCRs */ +#define UFS_PHY_GDSC 0 +#define USB30_PRIM_GDSC 1 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3 + +#endif -- cgit v1.2.3 From 95183d381a4445cb5e3edbc678a4b6267e50a738 Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Thu, 7 Nov 2019 11:21:36 -0800 Subject: clk: qcom: Enumerate clocks and reset needed to boot the 8998 modem We need to control five additional clocks and a reset inorder to boot the modem on msm8998. If we can boot the modem, we have a place to run the wlan firmware and get wifi up and running. Signed-off-by: Jeffrey Hugo Link: https://lkml.kernel.org/r/20191107192136.5880-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-msm8998.c | 72 ++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-msm8998.h | 6 +++ 2 files changed, 78 insertions(+) (limited to 'include/dt-bindings') diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c index 091acd59c1d6..cf31b5d03270 100644 --- a/drivers/clk/qcom/gcc-msm8998.c +++ b/drivers/clk/qcom/gcc-msm8998.c @@ -1266,6 +1266,72 @@ static struct clk_branch gcc_bimc_mss_q6_axi_clk = { }, }; +static struct clk_branch gcc_mss_cfg_ahb_clk = { + .halt_reg = 0x8a000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8a000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_snoc_axi_clk = { + .halt_reg = 0x8a03c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8a03c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_snoc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { + .halt_reg = 0x8a004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8a004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_mnoc_bimc_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x38004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x38004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mss_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x5200c, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mss_gpll0_div_clk_src", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_blsp1_ahb_clk = { .halt_reg = 0x17004, .halt_check = BRANCH_HALT_VOTED, @@ -2832,6 +2898,11 @@ static struct clk_regmap *gcc_msm8998_clocks[] = { [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr, [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr, [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, + [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, + [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr, }; static struct gdsc *gcc_msm8998_gdscs[] = { @@ -2928,6 +2999,7 @@ static const struct qcom_reset_map gcc_msm8998_resets[] = { [GCC_GPU_BCR] = { 0x71000 }, [GCC_SPSS_BCR] = { 0x72000 }, [GCC_OBT_ODT_BCR] = { 0x73000 }, + [GCC_MSS_RESTART] = { 0x79000 }, [GCC_VS_BCR] = { 0x7a000 }, [GCC_MSS_VS_RESET] = { 0x7a100 }, [GCC_GPU_VS_RESET] = { 0x7a104 }, diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index ab376262fcea..de1d8a1f5966 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -177,6 +177,11 @@ #define GCC_UFS_CLKREF_CLK 168 #define GCC_PCIE_CLKREF_CLK 169 #define GCC_RX1_USB2_CLKREF_CLK 170 +#define GCC_MSS_CFG_AHB_CLK 171 +#define GCC_BOOT_ROM_AHB_CLK 172 +#define GCC_MSS_GPLL0_DIV_CLK_SRC 173 +#define GCC_MSS_SNOC_AXI_CLK 174 +#define GCC_MSS_MNOC_BIMC_AXI_CLK 175 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 @@ -290,5 +295,6 @@ #define GCC_MSMPU_BCR 105 #define GCC_QUSB2PHY_PRIM_BCR 106 #define GCC_QUSB2PHY_SEC_BCR 107 +#define GCC_MSS_RESTART 108 #endif -- cgit v1.2.3