From df06230106e95347ec613f1707a704b04737c59b Mon Sep 17 00:00:00 2001 From: Dmitry Shmidt Date: Wed, 10 Jun 2020 10:30:11 +0200 Subject: dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs This adds the Neural Network Accelerator IP source clocks. Signed-off-by: Dmitry Shmidt Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200610083012.5024-2-narmstrong@baylibre.com --- include/dt-bindings/clock/g12a-clkc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index b0d65d73db96..40d49940d8a8 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -145,5 +145,7 @@ #define CLKID_CPU3_CLK 255 #define CLKID_SPICC0_SCLK 258 #define CLKID_SPICC1_SCLK 261 +#define CLKID_NNA_AXI_CLK 264 +#define CLKID_NNA_CORE_CLK 267 #endif /* __G12A_CLKC_H */ -- cgit v1.2.3 From 018e4308349dbf32f4d971cbe72f4f3d6b1c217a Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 1 Jun 2020 16:06:07 -0700 Subject: clk: imx: vf610: add CAAM clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Vybrid Security RM, CCM_CCGR11[CG176] can be used to gate CAAM ipg clock. Signed-off-by: Horia Geantă Signed-off-by: Andrey Smirnov Cc: Chris Healy Cc: Shawn Guo Cc: Fabio Estevam Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-imx@nxp.com Tested-by: Chris Healy Signed-off-by: Shawn Guo --- drivers/clk/imx/clk-vf610.c | 1 + include/dt-bindings/clock/vf610-clock.h | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c index cd04e7dc1878..5129ef8e1d6e 100644 --- a/drivers/clk/imx/clk-vf610.c +++ b/drivers/clk/imx/clk-vf610.c @@ -438,6 +438,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7)); clk[VF610_CLK_DAP] = imx_clk_gate("dap", "platform_bus", CCM_CCSR, 24); clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(5)); + clk[VF610_CLK_CAAM] = imx_clk_gate2("caam", "ipg_bus", CCM_CCGR11, CCM_CCGRx_CGn(0)); imx_check_clocks(clk, ARRAY_SIZE(clk)); diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h index 95394f35a74a..0f2d60e884dc 100644 --- a/include/dt-bindings/clock/vf610-clock.h +++ b/include/dt-bindings/clock/vf610-clock.h @@ -195,6 +195,7 @@ #define VF610_CLK_WKPU 186 #define VF610_CLK_TCON0 187 #define VF610_CLK_TCON1 188 -#define VF610_CLK_END 189 +#define VF610_CLK_CAAM 189 +#define VF610_CLK_END 190 #endif /* __DT_BINDINGS_CLOCK_VF610_H */ -- cgit v1.2.3 From e24779649c840ce1ecb638a30e7c821075630184 Mon Sep 17 00:00:00 2001 From: Marian-Cristian Rotariu Date: Tue, 7 Jul 2020 17:18:04 +0100 Subject: dt-bindings: power: Add r8a774e1 SYSC power domain definitions This patch adds power domain indices for the RZ/G2H (r8a774e1) SoC. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/power/r8a774e1-sysc.h | 36 +++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 include/dt-bindings/power/r8a774e1-sysc.h (limited to 'include') diff --git a/include/dt-bindings/power/r8a774e1-sysc.h b/include/dt-bindings/power/r8a774e1-sysc.h new file mode 100644 index 000000000000..7edb8161db36 --- /dev/null +++ b/include/dt-bindings/power/r8a774e1-sysc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774E1_PD_CA57_CPU0 0 +#define R8A774E1_PD_CA57_CPU1 1 +#define R8A774E1_PD_CA57_CPU2 2 +#define R8A774E1_PD_CA57_CPU3 3 +#define R8A774E1_PD_CA53_CPU0 5 +#define R8A774E1_PD_CA53_CPU1 6 +#define R8A774E1_PD_CA53_CPU2 7 +#define R8A774E1_PD_CA53_CPU3 8 +#define R8A774E1_PD_A3VP 9 +#define R8A774E1_PD_CA57_SCU 12 +#define R8A774E1_PD_A3VC 14 +#define R8A774E1_PD_3DG_A 17 +#define R8A774E1_PD_3DG_B 18 +#define R8A774E1_PD_3DG_C 19 +#define R8A774E1_PD_3DG_D 20 +#define R8A774E1_PD_CA53_SCU 21 +#define R8A774E1_PD_3DG_E 22 +#define R8A774E1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774E1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */ -- cgit v1.2.3 From ef1c9924287d11660cfc7900aeeeb4732188743e Mon Sep 17 00:00:00 2001 From: Marian-Cristian Rotariu Date: Tue, 7 Jul 2020 17:18:09 +0100 Subject: clk: renesas: Add r8a774e1 CPG Core Clock Definitions Add all RZ/G2H Clock Pulse Generator Core Clock Outputs, as listed in Table 11.2 ("List of Clocks [RZ/G2H]") of the RZ/G2H Hardware User's Manual. Signed-off-by: Marian-Cristian Rotariu Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/1594138692-16816-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/r8a774e1-cpg-mssr.h | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 include/dt-bindings/clock/r8a774e1-cpg-mssr.h (limited to 'include') diff --git a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h new file mode 100644 index 000000000000..b2fc1d1c3c47 --- /dev/null +++ b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ + +#include + +/* R8A774E1 CPG Core Clocks */ +#define R8A774E1_CLK_Z 0 +#define R8A774E1_CLK_Z2 1 +#define R8A774E1_CLK_ZG 2 +#define R8A774E1_CLK_ZTR 3 +#define R8A774E1_CLK_ZTRD2 4 +#define R8A774E1_CLK_ZT 5 +#define R8A774E1_CLK_ZX 6 +#define R8A774E1_CLK_S0D1 7 +#define R8A774E1_CLK_S0D2 8 +#define R8A774E1_CLK_S0D3 9 +#define R8A774E1_CLK_S0D4 10 +#define R8A774E1_CLK_S0D6 11 +#define R8A774E1_CLK_S0D8 12 +#define R8A774E1_CLK_S0D12 13 +#define R8A774E1_CLK_S1D2 14 +#define R8A774E1_CLK_S1D4 15 +#define R8A774E1_CLK_S2D1 16 +#define R8A774E1_CLK_S2D2 17 +#define R8A774E1_CLK_S2D4 18 +#define R8A774E1_CLK_S3D1 19 +#define R8A774E1_CLK_S3D2 20 +#define R8A774E1_CLK_S3D4 21 +#define R8A774E1_CLK_LB 22 +#define R8A774E1_CLK_CL 23 +#define R8A774E1_CLK_ZB3 24 +#define R8A774E1_CLK_ZB3D2 25 +#define R8A774E1_CLK_ZB3D4 26 +#define R8A774E1_CLK_CR 27 +#define R8A774E1_CLK_CRD2 28 +#define R8A774E1_CLK_SD0H 29 +#define R8A774E1_CLK_SD0 30 +#define R8A774E1_CLK_SD1H 31 +#define R8A774E1_CLK_SD1 32 +#define R8A774E1_CLK_SD2H 33 +#define R8A774E1_CLK_SD2 34 +#define R8A774E1_CLK_SD3H 35 +#define R8A774E1_CLK_SD3 36 +#define R8A774E1_CLK_RPC 37 +#define R8A774E1_CLK_RPCD2 38 +#define R8A774E1_CLK_MSO 39 +#define R8A774E1_CLK_HDMI 40 +#define R8A774E1_CLK_CSI0 41 +#define R8A774E1_CLK_CP 42 +#define R8A774E1_CLK_CPEX 43 +#define R8A774E1_CLK_R 44 +#define R8A774E1_CLK_OSC 45 +#define R8A774E1_CLK_CANFD 46 + +#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */ -- cgit v1.2.3