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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/microchip,ksz.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip KSZ Series Ethernet switches
maintainers:
- Marek Vasut <marex@denx.de>
- Woojung Huh <Woojung.Huh@microchip.com>
allOf:
- $ref: /schemas/spi/spi-peripheral-props.yaml#
properties:
# See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional
# required and optional properties.
compatible:
enum:
- microchip,ksz8765
- microchip,ksz8794
- microchip,ksz8795
- microchip,ksz8863
- microchip,ksz8864 # 4-port version of KSZ8895 family switch
- microchip,ksz8873
- microchip,ksz8895 # 5-port version of KSZ8895 family switch
- microchip,ksz9477
- microchip,ksz9897
- microchip,ksz9896
- microchip,ksz9567
- microchip,ksz8565
- microchip,ksz9893
- microchip,ksz9563
- microchip,ksz8563
- microchip,ksz8567
- microchip,lan9646
reset-gpios:
description:
Should be a gpio specifier for a reset line.
maxItems: 1
wakeup-source: true
microchip,synclko-125:
$ref: /schemas/types.yaml#/definitions/flag
description:
Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
microchip,synclko-disable:
$ref: /schemas/types.yaml#/definitions/flag
description:
Set if the output SYNCLKO clock should be disabled. Do not mix with
microchip,synclko-125.
microchip,pme-active-high:
$ref: /schemas/types.yaml#/definitions/flag
description:
Indicates if the PME pin polarity is active-high.
microchip,io-drive-strength-microamp:
description:
IO Pad Drive Strength
enum: [8000, 16000]
default: 16000
microchip,hi-drive-strength-microamp:
description:
High Speed Drive Strength. Controls drive strength of GMII / RGMII /
MII / RMII (except TX_CLK/REFCLKI, COL and CRS) and CLKO_25_125 lines.
enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
default: 24000
microchip,lo-drive-strength-microamp:
description:
Low Speed Drive Strength. Controls drive strength of TX_CLK / REFCLKI,
COL, CRS, LEDs, PME_N, NTRP_N, SDO and SDI/SDA/MDIO lines.
enum: [2000, 4000, 8000, 12000, 16000, 20000, 24000, 28000]
default: 8000
interrupts:
maxItems: 1
mdio:
$ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
properties:
mdio-parent-bus:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle pointing to the MDIO bus controller connected to the
secondary MDIO interface. This property should be used when
the internal MDIO bus is accessed via a secondary MDIO
interface rather than the primary management interface.
patternProperties:
"^ethernet-phy@[0-9a-f]$":
type: object
$ref: /schemas/net/ethernet-phy.yaml#
unevaluatedProperties: false
description:
Integrated PHY node
required:
- compatible
- reg
if:
not:
properties:
compatible:
enum:
- microchip,ksz8863
- microchip,ksz8873
then:
$ref: dsa.yaml#/$defs/ethernet-ports
else:
patternProperties:
"^(ethernet-)?ports$":
patternProperties:
"^(ethernet-)?port@[0-2]$":
$ref: dsa-port.yaml#
unevaluatedProperties: false
properties:
microchip,rmii-clk-internal:
$ref: /schemas/types.yaml#/definitions/flag
description:
When ksz88x3 is acting as clock provier (via REFCLKO) it
can select between internal and external RMII reference
clock. Internal reference clock means that the clock for
the RMII of ksz88x3 is provided by the ksz88x3 internally
and the REFCLKI pin is unconnected. For the external
reference clock, the clock needs to be fed back to ksz88x3
via REFCLKI.
If microchip,rmii-clk-internal is set, ksz88x3 will provide
rmii reference clock internally, otherwise reference clock
should be provided externally.
dependencies:
microchip,rmii-clk-internal: [ethernet]
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
// Ethernet switch connected via SPI to the host, CPU port wired to eth0:
eth0 {
fixed-link {
speed = <1000>;
full-duplex;
};
};
spi {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pinctrl_spi_ksz>;
cs-gpios = <&pioC 25 0>;
ksz9477: switch@0 {
compatible = "microchip,ksz9477";
reg = <0>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
spi-max-frequency = <44000000>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@4 {
reg = <4>;
label = "lan5";
};
port@5 {
reg = <5>;
ethernet = <ð0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
ksz8565: switch@1 {
compatible = "microchip,ksz8565";
reg = <1>;
spi-max-frequency = <44000000>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan1";
};
port@1 {
reg = <1>;
label = "lan2";
};
port@2 {
reg = <2>;
label = "lan3";
};
port@3 {
reg = <3>;
label = "lan4";
};
port@6 {
reg = <6>;
ethernet = <ð0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
...
|
