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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PCIe Root Port Bridge Controller
maintainers:
- Daire McNamara <daire.mcnamara@microchip.com>
allOf:
- $ref: plda,xpressrich3-axi-common.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#
properties:
compatible:
const: microchip,pcie-host-1.0 # PolarFire
reg:
minItems: 3
reg-names:
minItems: 3
clocks:
description:
Fabric Interface Controllers, FICs, are the interface between the FPGA
fabric and the core complex on PolarFire SoC. The FICs require two clocks,
one from each side of the interface. The "FIC clocks" described by this
property are on the core complex side & communication through a FIC is not
possible unless it's corresponding clock is enabled. A clock must be
enabled for each of the interfaces the root port is connected through.
This could in theory be all 4 interfaces, one interface or any combination
in between.
minItems: 1
items:
- description: FIC0's clock
- description: FIC1's clock
- description: FIC2's clock
- description: FIC3's clock
clock-names:
description:
As any FIC connection combination is possible, the names should match the
order in the clocks property and take the form "ficN" where N is a number
0-3
minItems: 1
maxItems: 4
items:
pattern: '^fic[0-3]$'
ranges:
minItems: 1
maxItems: 3
dma-ranges:
minItems: 1
maxItems: 6
unevaluatedProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pcie0: pcie@2030000000 {
compatible = "microchip,pcie-host-1.0";
reg = <0x0 0x70000000 0x0 0x08000000>,
<0x0 0x43008000 0x0 0x00002000>,
<0x0 0x4300a000 0x0 0x00002000>;
reg-names = "cfg", "bridge", "ctrl";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupts = <119>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
interrupt-parent = <&plic0>;
msi-parent = <&pcie0>;
msi-controller;
bus-range = <0x00 0x7f>;
ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
pcie_intc0: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
};
|
