summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/exynos4x12.dtsi
blob: 1917c829e64e6ef487fe12e732313354377a6f49 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
/*
 * Samsung's Exynos4x12 SoCs device tree source
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
 * based board files can include this file and provide values for board specfic
 * bindings.
 *
 * Note: This file does not include device nodes for all the controllers in
 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
 * nodes can be added to this file.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include "exynos4.dtsi"
#include "exynos4x12-pinctrl.dtsi"

/ {
	aliases {
		pinctrl0 = &pinctrl_0;
		pinctrl1 = &pinctrl_1;
		pinctrl2 = &pinctrl_2;
		pinctrl3 = &pinctrl_3;
		fimc-lite0 = &fimc_lite_0;
		fimc-lite1 = &fimc_lite_1;
		mshc0 = &mshc_0;
	};

	pd_isp: isp-power-domain@10023CA0 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10023CA0 0x20>;
	};

	clock: clock-controller@10030000 {
		compatible = "samsung,exynos4412-clock";
		reg = <0x10030000 0x20000>;
		#clock-cells = <1>;
	};

	pinctrl_0: pinctrl@11400000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x11400000 0x1000>;
		interrupts = <0 47 0>;
	};

	pinctrl_1: pinctrl@11000000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x11000000 0x1000>;
		interrupts = <0 46 0>;

		wakup_eint: wakeup-interrupt-controller {
			compatible = "samsung,exynos4210-wakeup-eint";
			interrupt-parent = <&gic>;
			interrupts = <0 32 0>;
		};
	};

	pinctrl_2: pinctrl@03860000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x03860000 0x1000>;
		interrupt-parent = <&combiner>;
		interrupts = <10 0>;
	};

	pinctrl_3: pinctrl@106E0000 {
		compatible = "samsung,exynos4x12-pinctrl";
		reg = <0x106E0000 0x1000>;
		interrupts = <0 72 0>;
	};

	g2d@10800000 {
		compatible = "samsung,exynos4212-g2d";
		reg = <0x10800000 0x1000>;
		interrupts = <0 89 0>;
		clocks = <&clock 177>, <&clock 277>;
		clock-names = "sclk_fimg2d", "fimg2d";
		status = "disabled";
	};

	camera {
		clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
		clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";

		fimc_0: fimc@11800000 {
			compatible = "samsung,exynos4212-fimc";
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,cam-if;
		};

		fimc_1: fimc@11810000 {
			compatible = "samsung,exynos4212-fimc";
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,cam-if;
		};

		fimc_2: fimc@11820000 {
			compatible = "samsung,exynos4212-fimc";
			samsung,pix-limits = <4224 8192 1920 4224>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,lcd-wb;
			samsung,cam-if;
		};

		fimc_3: fimc@11830000 {
			compatible = "samsung,exynos4212-fimc";
			samsung,pix-limits = <1920 8192 1366 1920>;
			samsung,rotators = <0>;
			samsung,mainscaler-ext;
			samsung,isp-wb;
			samsung,lcd-wb;
		};

		fimc_lite_0: fimc-lite@12390000 {
			compatible = "samsung,exynos4212-fimc-lite";
			reg = <0x12390000 0x1000>;
			interrupts = <0 105 0>;
			samsung,power-domain = <&pd_isp>;
			clocks = <&clock 353>;
			clock-names = "flite";
			status = "disabled";
		};

		fimc_lite_1: fimc-lite@123A0000 {
			compatible = "samsung,exynos4212-fimc-lite";
			reg = <0x123A0000 0x1000>;
			interrupts = <0 106 0>;
			samsung,power-domain = <&pd_isp>;
			clocks = <&clock 354>;
			clock-names = "flite";
			status = "disabled";
		};

		fimc_is: fimc-is@12000000 {
			compatible = "samsung,exynos4212-fimc-is", "simple-bus";
			reg = <0x12000000 0x260000>;
			interrupts = <0 90 0>, <0 95 0>;
			samsung,power-domain = <&pd_isp>;
			clocks = <&clock 353>, <&clock 354>, <&clock 355>,
				<&clock 356>, <&clock 17>, <&clock 357>,
				<&clock 358>, <&clock 359>, <&clock 360>,
				<&clock 450>,<&clock 451>, <&clock 452>,
				<&clock 453>, <&clock 176>, <&clock 13>,
				<&clock 454>, <&clock 395>, <&clock 455>;
			clock-names = "lite0", "lite1", "ppmuispx",
				      "ppmuispmx", "mpll", "isp",
				      "drc", "fd", "mcuisp",
				      "ispdiv0", "ispdiv1", "mcuispdiv0",
				      "mcuispdiv1", "uart", "aclk200",
				      "div_aclk200", "aclk400mcuisp",
				      "div_aclk400mcuisp";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			status = "disabled";

			pmu {
				reg = <0x10020000 0x3000>;
			};

			i2c1_isp: i2c-isp@12140000 {
				compatible = "samsung,exynos4212-i2c-isp";
				reg = <0x12140000 0x100>;
				clocks = <&clock 370>;
				clock-names = "i2c_isp";
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};
	};

	mshc_0: mmc@12550000 {
		compatible = "samsung,exynos4412-dw-mshc";
		reg = <0x12550000 0x1000>;
		interrupts = <0 77 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		fifo-depth = <0x80>;
		clocks = <&clock 301>, <&clock 149>;
		clock-names = "biu", "ciu";
		status = "disabled";
	};
};