summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/imx51.dtsi
blob: 768e6da594a2198df85a1c04efccbef3ace2cf8f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 * Copyright 2011 Linaro Ltd.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include "skeleton.dtsi"
#include "imx51-pinfunc.h"

/ {
	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
	};

	tzic: tz-interrupt-controller@e0000000 {
		compatible = "fsl,imx51-tzic", "fsl,tzic";
		interrupt-controller;
		#interrupt-cells = <1>;
		reg = <0xe0000000 0x4000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		ckil {
			compatible = "fsl,imx-ckil", "fixed-clock";
			clock-frequency = <32768>;
		};

		ckih1 {
			compatible = "fsl,imx-ckih1", "fixed-clock";
			clock-frequency = <22579200>;
		};

		ckih2 {
			compatible = "fsl,imx-ckih2", "fixed-clock";
			clock-frequency = <0>;
		};

		osc {
			compatible = "fsl,imx-osc", "fixed-clock";
			clock-frequency = <24000000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a8";
			reg = <0>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clks 24>;
			clock-names = "cpu";
			operating-points = <
				/* kHz  uV (No regulator support) */
				160000  0
				800000  0
			>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&tzic>;
		ranges;

		ipu: ipu@40000000 {
			#crtc-cells = <1>;
			compatible = "fsl,imx51-ipu";
			reg = <0x40000000 0x20000000>;
			interrupts = <11 10>;
			clocks = <&clks 59>, <&clks 110>, <&clks 61>;
			clock-names = "bus", "di0", "di1";
			resets = <&src 2>;
		};

		aips@70000000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x70000000 0x10000000>;
			ranges;

			spba@70000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x70000000 0x40000>;
				ranges;

				esdhc1: esdhc@70004000 {
					compatible = "fsl,imx51-esdhc";
					reg = <0x70004000 0x4000>;
					interrupts = <1>;
					clocks = <&clks 44>, <&clks 0>, <&clks 71>;
					clock-names = "ipg", "ahb", "per";
					status = "disabled";
				};

				esdhc2: esdhc@70008000 {
					compatible = "fsl,imx51-esdhc";
					reg = <0x70008000 0x4000>;
					interrupts = <2>;
					clocks = <&clks 45>, <&clks 0>, <&clks 72>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				uart3: serial@7000c000 {
					compatible = "fsl,imx51-uart", "fsl,imx21-uart";
					reg = <0x7000c000 0x4000>;
					interrupts = <33>;
					clocks = <&clks 32>, <&clks 33>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi1: ecspi@70010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx51-ecspi";
					reg = <0x70010000 0x4000>;
					interrupts = <36>;
					clocks = <&clks 51>, <&clks 52>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ssi2: ssi@70014000 {
					compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
					reg = <0x70014000 0x4000>;
					interrupts = <30>;
					clocks = <&clks 49>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					status = "disabled";
				};

				esdhc3: esdhc@70020000 {
					compatible = "fsl,imx51-esdhc";
					reg = <0x70020000 0x4000>;
					interrupts = <3>;
					clocks = <&clks 46>, <&clks 0>, <&clks 73>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};

				esdhc4: esdhc@70024000 {
					compatible = "fsl,imx51-esdhc";
					reg = <0x70024000 0x4000>;
					interrupts = <4>;
					clocks = <&clks 47>, <&clks 0>, <&clks 74>;
					clock-names = "ipg", "ahb", "per";
					bus-width = <4>;
					status = "disabled";
				};
			};

			usbotg: usb@73f80000 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80000 0x0200>;
				interrupts = <18>;
				fsl,usbmisc = <&usbmisc 0>;
				status = "disabled";
			};

			usbh1: usb@73f80200 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80200 0x0200>;
				interrupts = <14>;
				fsl,usbmisc = <&usbmisc 1>;
				status = "disabled";
			};

			usbh2: usb@73f80400 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80400 0x0200>;
				interrupts = <16>;
				fsl,usbmisc = <&usbmisc 2>;
				status = "disabled";
			};

			usbh3: usb@73f80600 {
				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
				reg = <0x73f80600 0x0200>;
				interrupts = <17>;
				fsl,usbmisc = <&usbmisc 3>;
				status = "disabled";
			};

			usbmisc: usbmisc@73f80800 {
				#index-cells = <1>;
				compatible = "fsl,imx51-usbmisc";
				reg = <0x73f80800 0x200>;
			};

			gpio1: gpio@73f84000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f84000 0x4000>;
				interrupts = <50 51>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@73f88000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f88000 0x4000>;
				interrupts = <52 53>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@73f8c000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f8c000 0x4000>;
				interrupts = <54 55>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@73f90000 {
				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
				reg = <0x73f90000 0x4000>;
				interrupts = <56 57>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			kpp: kpp@73f94000 {
				compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
				reg = <0x73f94000 0x4000>;
				interrupts = <60>;
				clocks = <&clks 0>;
				status = "disabled";
			};

			wdog1: wdog@73f98000 {
				compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
				reg = <0x73f98000 0x4000>;
				interrupts = <58>;
				clocks = <&clks 0>;
			};

			wdog2: wdog@73f9c000 {
				compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
				reg = <0x73f9c000 0x4000>;
				interrupts = <59>;
				clocks = <&clks 0>;
				status = "disabled";
			};

			gpt: timer@73fa0000 {
				compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
				reg = <0x73fa0000 0x4000>;
				interrupts = <39>;
				clocks = <&clks 36>, <&clks 41>;
				clock-names = "ipg", "per";
			};

			iomuxc: iomuxc@73fa8000 {
				compatible = "fsl,imx51-iomuxc";
				reg = <0x73fa8000 0x4000>;

				audmux {
					pinctrl_audmux_1: audmuxgrp-1 {
						fsl,pins = <
							MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
							MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
							MX51_PAD_AUD3_BB_CK__AUD3_TXC  0x80000000
							MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
						>;
					};
				};

				fec {
					pinctrl_fec_1: fecgrp-1 {
						fsl,pins = <
							MX51_PAD_EIM_EB2__FEC_MDIO	   0x80000000
							MX51_PAD_EIM_EB3__FEC_RDATA1	   0x80000000
							MX51_PAD_EIM_CS2__FEC_RDATA2	   0x80000000
							MX51_PAD_EIM_CS3__FEC_RDATA3	   0x80000000
							MX51_PAD_EIM_CS4__FEC_RX_ER	   0x80000000
							MX51_PAD_EIM_CS5__FEC_CRS	   0x80000000
							MX51_PAD_NANDF_RB2__FEC_COL	   0x80000000
							MX51_PAD_NANDF_RB3__FEC_RX_CLK	   0x80000000
							MX51_PAD_NANDF_D9__FEC_RDATA0	   0x80000000
							MX51_PAD_NANDF_D8__FEC_TDATA0	   0x80000000
							MX51_PAD_NANDF_CS2__FEC_TX_ER	   0x80000000
							MX51_PAD_NANDF_CS3__FEC_MDC	   0x80000000
							MX51_PAD_NANDF_CS4__FEC_TDATA1	   0x80000000
							MX51_PAD_NANDF_CS5__FEC_TDATA2	   0x80000000
							MX51_PAD_NANDF_CS6__FEC_TDATA3	   0x80000000
							MX51_PAD_NANDF_CS7__FEC_TX_EN	   0x80000000
							MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
						>;
					};

					pinctrl_fec_2: fecgrp-2 {
						fsl,pins = <
							MX51_PAD_DI_GP3__FEC_TX_ER	  0x80000000
							MX51_PAD_DI2_PIN4__FEC_CRS	  0x80000000
							MX51_PAD_DI2_PIN2__FEC_MDC	  0x80000000
							MX51_PAD_DI2_PIN3__FEC_MDIO	  0x80000000
							MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
							MX51_PAD_DI_GP4__FEC_RDATA2	  0x80000000
							MX51_PAD_DISP2_DAT0__FEC_RDATA3   0x80000000
							MX51_PAD_DISP2_DAT1__FEC_RX_ER	  0x80000000
							MX51_PAD_DISP2_DAT6__FEC_TDATA1	  0x80000000
							MX51_PAD_DISP2_DAT7__FEC_TDATA2	  0x80000000
							MX51_PAD_DISP2_DAT8__FEC_TDATA3	  0x80000000
							MX51_PAD_DISP2_DAT9__FEC_TX_EN	  0x80000000
							MX51_PAD_DISP2_DAT10__FEC_COL	  0x80000000
							MX51_PAD_DISP2_DAT11__FEC_RX_CLK  0x80000000
							MX51_PAD_DISP2_DAT12__FEC_RX_DV	  0x80000000
							MX51_PAD_DISP2_DAT13__FEC_TX_CLK  0x80000000
							MX51_PAD_DISP2_DAT14__FEC_RDATA0  0x80000000
							MX51_PAD_DISP2_DAT15__FEC_TDATA0  0x80000000
						>;
					};
				};

				ecspi1 {
					pinctrl_ecspi1_1: ecspi1grp-1 {
						fsl,pins = <
							MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
							MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
							MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
						>;
					};
				};

				ecspi2 {
					pinctrl_ecspi2_1: ecspi2grp-1 {
						fsl,pins = <
							MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
							MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
							MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
						>;
					};
				};

				esdhc1 {
					pinctrl_esdhc1_1: esdhc1grp-1 {
						fsl,pins = <
							MX51_PAD_SD1_CMD__SD1_CMD     0x400020d5
							MX51_PAD_SD1_CLK__SD1_CLK     0x20d5
							MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
							MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
							MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
							MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
						>;
					};
				};

				esdhc2 {
					pinctrl_esdhc2_1: esdhc2grp-1 {
						fsl,pins = <
							MX51_PAD_SD2_CMD__SD2_CMD     0x400020d5
							MX51_PAD_SD2_CLK__SD2_CLK     0x20d5
							MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
							MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
							MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
							MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
						>;
					};
				};

				i2c2 {
					pinctrl_i2c2_1: i2c2grp-1 {
						fsl,pins = <
							MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
							MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
						>;
					};

					pinctrl_i2c2_2: i2c2grp-2 {
						fsl,pins = <
							MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
							MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
						>;
					};
				};

				ipu_disp1 {
					pinctrl_ipu_disp1_1: ipudisp1grp-1 {
						fsl,pins = <
							MX51_PAD_DISP1_DAT0__DISP1_DAT0	  0x5
							MX51_PAD_DISP1_DAT1__DISP1_DAT1   0x5
							MX51_PAD_DISP1_DAT2__DISP1_DAT2   0x5
							MX51_PAD_DISP1_DAT3__DISP1_DAT3   0x5
							MX51_PAD_DISP1_DAT4__DISP1_DAT4   0x5
							MX51_PAD_DISP1_DAT5__DISP1_DAT5   0x5
							MX51_PAD_DISP1_DAT6__DISP1_DAT6   0x5
							MX51_PAD_DISP1_DAT7__DISP1_DAT7   0x5
							MX51_PAD_DISP1_DAT8__DISP1_DAT8   0x5
							MX51_PAD_DISP1_DAT9__DISP1_DAT9   0x5
							MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
							MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
							MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
							MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
							MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
							MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
							MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
							MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
							MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
							MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
							MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
							MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
							MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
							MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
							MX51_PAD_DI1_PIN2__DI1_PIN2	  0x5 /* hsync */
							MX51_PAD_DI1_PIN3__DI1_PIN3	  0x5 /* vsync */
						>;
					};
				};

				ipu_disp2 {
					pinctrl_ipu_disp2_1: ipudisp2grp-1 {
						fsl,pins = <
							MX51_PAD_DISP2_DAT0__DISP2_DAT0     0x5
							MX51_PAD_DISP2_DAT1__DISP2_DAT1     0x5
							MX51_PAD_DISP2_DAT2__DISP2_DAT2     0x5
							MX51_PAD_DISP2_DAT3__DISP2_DAT3     0x5
							MX51_PAD_DISP2_DAT4__DISP2_DAT4     0x5
							MX51_PAD_DISP2_DAT5__DISP2_DAT5     0x5
							MX51_PAD_DISP2_DAT6__DISP2_DAT6     0x5
							MX51_PAD_DISP2_DAT7__DISP2_DAT7     0x5
							MX51_PAD_DISP2_DAT8__DISP2_DAT8     0x5
							MX51_PAD_DISP2_DAT9__DISP2_DAT9     0x5
							MX51_PAD_DISP2_DAT10__DISP2_DAT10   0x5
							MX51_PAD_DISP2_DAT11__DISP2_DAT11   0x5
							MX51_PAD_DISP2_DAT12__DISP2_DAT12   0x5
							MX51_PAD_DISP2_DAT13__DISP2_DAT13   0x5
							MX51_PAD_DISP2_DAT14__DISP2_DAT14   0x5
							MX51_PAD_DISP2_DAT15__DISP2_DAT15   0x5
							MX51_PAD_DI2_PIN2__DI2_PIN2	    0x5 /* hsync */
							MX51_PAD_DI2_PIN3__DI2_PIN3	    0x5 /* vsync */
							MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
							MX51_PAD_DI_GP4__DI2_PIN15	    0x5
						>;
					};
				};

				pata {
					pinctrl_pata_1: patagrp-1 {
						fsl,pins = <
							MX51_PAD_NANDF_WE_B__PATA_DIOW		0x2004
							MX51_PAD_NANDF_RE_B__PATA_DIOR		0x2004
							MX51_PAD_NANDF_ALE__PATA_BUFFER_EN	0x2004
							MX51_PAD_NANDF_CLE__PATA_RESET_B	0x2004
							MX51_PAD_NANDF_WP_B__PATA_DMACK		0x2004
							MX51_PAD_NANDF_RB0__PATA_DMARQ		0x2004
							MX51_PAD_NANDF_RB1__PATA_IORDY		0x2004
							MX51_PAD_GPIO_NAND__PATA_INTRQ		0x2004
							MX51_PAD_NANDF_CS2__PATA_CS_0		0x2004
							MX51_PAD_NANDF_CS3__PATA_CS_1		0x2004
							MX51_PAD_NANDF_CS4__PATA_DA_0		0x2004
							MX51_PAD_NANDF_CS5__PATA_DA_1		0x2004
							MX51_PAD_NANDF_CS6__PATA_DA_2		0x2004
							MX51_PAD_NANDF_D15__PATA_DATA15		0x2004
							MX51_PAD_NANDF_D14__PATA_DATA14		0x2004
							MX51_PAD_NANDF_D13__PATA_DATA13		0x2004
							MX51_PAD_NANDF_D12__PATA_DATA12		0x2004
							MX51_PAD_NANDF_D11__PATA_DATA11		0x2004
							MX51_PAD_NANDF_D10__PATA_DATA10		0x2004
							MX51_PAD_NANDF_D9__PATA_DATA9		0x2004
							MX51_PAD_NANDF_D8__PATA_DATA8		0x2004
							MX51_PAD_NANDF_D7__PATA_DATA7		0x2004
							MX51_PAD_NANDF_D6__PATA_DATA6		0x2004
							MX51_PAD_NANDF_D5__PATA_DATA5		0x2004
							MX51_PAD_NANDF_D4__PATA_DATA4		0x2004
							MX51_PAD_NANDF_D3__PATA_DATA3		0x2004
							MX51_PAD_NANDF_D2__PATA_DATA2		0x2004
							MX51_PAD_NANDF_D1__PATA_DATA1		0x2004
							MX51_PAD_NANDF_D0__PATA_DATA0		0x2004
						>;
					};
				};

				uart1 {
					pinctrl_uart1_1: uart1grp-1 {
						fsl,pins = <
							MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
							MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
							MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
							MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
						>;
					};
				};

				uart2 {
					pinctrl_uart2_1: uart2grp-1 {
						fsl,pins = <
							MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
							MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
						>;
					};
				};

				uart3 {
					pinctrl_uart3_1: uart3grp-1 {
						fsl,pins = <
							MX51_PAD_EIM_D25__UART3_RXD 0x1c5
							MX51_PAD_EIM_D26__UART3_TXD 0x1c5
							MX51_PAD_EIM_D27__UART3_RTS 0x1c5
							MX51_PAD_EIM_D24__UART3_CTS 0x1c5
						>;
					};

					pinctrl_uart3_2: uart3grp-2 {
						fsl,pins = <
							MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
							MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
						>;
					};
				};

				kpp {
					pinctrl_kpp_1: kppgrp-1 {
						fsl,pins = <
							MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
							MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
							MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
							MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
							MX51_PAD_KEY_COL0__KEY_COL0 0xe8
							MX51_PAD_KEY_COL1__KEY_COL1 0xe8
							MX51_PAD_KEY_COL2__KEY_COL2 0xe8
							MX51_PAD_KEY_COL3__KEY_COL3 0xe8
						>;
					};
				};
			};

			pwm1: pwm@73fb4000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
				reg = <0x73fb4000 0x4000>;
				clocks = <&clks 37>, <&clks 38>;
				clock-names = "ipg", "per";
				interrupts = <61>;
			};

			pwm2: pwm@73fb8000 {
				#pwm-cells = <2>;
				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
				reg = <0x73fb8000 0x4000>;
				clocks = <&clks 39>, <&clks 40>;
				clock-names = "ipg", "per";
				interrupts = <94>;
			};

			uart1: serial@73fbc000 {
				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
				reg = <0x73fbc000 0x4000>;
				interrupts = <31>;
				clocks = <&clks 28>, <&clks 29>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart2: serial@73fc0000 {
				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
				reg = <0x73fc0000 0x4000>;
				interrupts = <32>;
				clocks = <&clks 30>, <&clks 31>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			src: src@73fd0000 {
				compatible = "fsl,imx51-src";
				reg = <0x73fd0000 0x4000>;
				#reset-cells = <1>;
			};

			clks: ccm@73fd4000{
				compatible = "fsl,imx51-ccm";
				reg = <0x73fd4000 0x4000>;
				interrupts = <0 71 0x04 0 72 0x04>;
				#clock-cells = <1>;
			};
		};

		aips@80000000 {	/* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x80000000 0x10000000>;
			ranges;

			ecspi2: ecspi@83fac000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-ecspi";
				reg = <0x83fac000 0x4000>;
				interrupts = <37>;
				clocks = <&clks 53>, <&clks 54>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			sdma: sdma@83fb0000 {
				compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
				reg = <0x83fb0000 0x4000>;
				interrupts = <6>;
				clocks = <&clks 56>, <&clks 56>;
				clock-names = "ipg", "ahb";
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
			};

			cspi: cspi@83fc0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
				reg = <0x83fc0000 0x4000>;
				interrupts = <38>;
				clocks = <&clks 55>, <&clks 55>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c2: i2c@83fc4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
				reg = <0x83fc4000 0x4000>;
				interrupts = <63>;
				clocks = <&clks 35>;
				status = "disabled";
			};

			i2c1: i2c@83fc8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
				reg = <0x83fc8000 0x4000>;
				interrupts = <62>;
				clocks = <&clks 34>;
				status = "disabled";
			};

			ssi1: ssi@83fcc000 {
				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
				reg = <0x83fcc000 0x4000>;
				interrupts = <29>;
				clocks = <&clks 48>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			audmux: audmux@83fd0000 {
				compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
				reg = <0x83fd0000 0x4000>;
				status = "disabled";
			};

			nfc: nand@83fdb000 {
				compatible = "fsl,imx51-nand";
				reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
				interrupts = <8>;
				clocks = <&clks 60>;
				status = "disabled";
			};

			pata: pata@83fe0000 {
				compatible = "fsl,imx51-pata", "fsl,imx27-pata";
				reg = <0x83fe0000 0x4000>;
				interrupts = <70>;
				clocks = <&clks 161>;
				status = "disabled";
			};

			ssi3: ssi@83fe8000 {
				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
				reg = <0x83fe8000 0x4000>;
				interrupts = <96>;
				clocks = <&clks 50>;
				fsl,fifo-depth = <15>;
				fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
				status = "disabled";
			};

			fec: ethernet@83fec000 {
				compatible = "fsl,imx51-fec", "fsl,imx27-fec";
				reg = <0x83fec000 0x4000>;
				interrupts = <87>;
				clocks = <&clks 42>, <&clks 42>, <&clks 42>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};
		};
	};
};