path: root/arch/arm/boot/dts/imx6sx-sdb.dtsi

/*
 * Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sx.dtsi"

/ {
	model = "Freescale i.MX6 SoloX SDB Board";
	compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";

	chosen {
		stdout-path = &uart1;
	};

	memory@80000000 {
		reg = <0x80000000 0x40000000>;
	};

	backlight_display: backlight-display {
		compatible = "pwm-backlight";
		pwms = <&pwm3 0 5000000>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		volume-up {
			label = "Volume Up";
			gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_VOLUMEUP>;
			wakeup-source;
		};

		volume-down {
			label = "Volume Down";
			gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_VOLUMEDOWN>;
			wakeup-source;
		};
	};

	vcc_sd3: regulator-vcc-sd3 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_vcc_sd3>;
		regulator-name = "VCC_SD3";
		regulator-min-microvolt = <3000000>;
		regulator-max-microvolt = <3000000>;
		gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb_otg1>;
		regulator-name = "usb_otg1_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb_otg2>;
		regulator-name = "usb_otg2_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_psu_5v: regulator-psu-5v {
		compatible = "regulator-fixed";
		regulator-name = "PSU-5V0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_lcd_3v3: regulator-lcd-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "lcd-3v3";
		gpio = <&gpio3 27 0>;
		enable-active-high;
	};

	reg_peri_3v3: regulator-peri-3v3 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_peri_3v3>;
		regulator-name = "peri_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

	reg_enet_3v3: regulator-enet-3v3 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_enet_3v3>;
		regulator-name = "enet_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
	};

	reg_pcie_gpio: regulator-pcie-gpio {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pcie_reg>;
		regulator-name = "MPCIE_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_lcd_5v: regulator-lcd-5v {
		compatible = "regulator-fixed";
		regulator-name = "lcd-5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	sound {
		compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
		model = "wm8962-audio";
		ssi-controller = <&ssi2>;
		audio-codec = <&codec>;
		audio-routing =
			"Headphone Jack", "HPOUTL",
			"Headphone Jack", "HPOUTR",
			"Ext Spk", "SPKOUTL",
			"Ext Spk", "SPKOUTR",
			"AMIC", "MICBIAS",
			"IN3R", "AMIC";
		mux-int-port = <2>;
		mux-ext-port = <6>;
	};

	panel {
		compatible = "sii,43wvf1g";
		backlight = <&backlight_display>;
		dvdd-supply = <&reg_lcd_3v3>;
		avdd-supply = <&reg_lcd_5v>;

		port {
			panel_in: endpoint {
				remote-endpoint = <&display_out>;
			};
		};
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-supply = <&reg_enet_3v3>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			reg = <1>;
		};

		ethphy2: ethernet-phy@2 {
			reg = <2>;
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy2>;
	status = "okay";
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	codec: wm8962@1a {
		compatible = "wlf,wm8962";
		reg = <0x1a>;
		clocks = <&clks IMX6SX_CLK_AUDIO>;
		DCVDD-supply = <&vgen4_reg>;
		DBVDD-supply = <&vgen4_reg>;
		AVDD-supply = <&vgen4_reg>;
		CPVDD-supply = <&vgen4_reg>;
		MICVDD-supply = <&vgen3_reg>;
		PLLVDD-supply = <&vgen4_reg>;
		SPKVDD1-supply = <&reg_psu_5v>;
		SPKVDD2-supply = <&reg_psu_5v>;
	};
};

&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie>;
	reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
	vpcie-supply = <&reg_pcie_gpio>;
	status = "okay";
};

&lcdif1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lcd>;
	status = "okay";

	port {
		display_out: endpoint {
			remote-endpoint = <&panel_in>;
		};
	};
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
	status = "okay";
};

&snvs_poweroff {
	status = "okay";
};

&sai1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "disabled";
};

&ssi2 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart5 { /* for bluetooth */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart5>;
	uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1_id>;
	status = "okay";
};

&usbotg2 {
	vbus-supply = <&reg_usb_otg2_vbus>;
	dr_mode = "host";
	status = "okay";
};

&usbphy1 {
	fsl,tx-d-cal = <106>;
};

&usbphy2 {
	fsl,tx-d-cal = <106>;
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	non-removable;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&vcc_sd3>;
	status = "okay";
};

&usdhc4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc4>;
	cd-gpios = <&gpio6 21 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
};

&iomuxc {
	imx6x-sdb {
		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC	0x130b0
				MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS	0x130b0
				MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD	0x120b0
				MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD	0x130b0
				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK	0x130b0
			>;
		};

		pinctrl_enet1: enet1grp {
			fsl,pins = <
				MX6SX_PAD_ENET1_MDIO__ENET1_MDIO	0xa0b1
				MX6SX_PAD_ENET1_MDC__ENET1_MDC		0xa0b1
				MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC	0xa0b1
				MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0	0xa0b1
				MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1	0xa0b1
				MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2	0xa0b1
				MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3	0xa0b1
				MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN	0xa0b1
				MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK	0x3081
				MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0	0x3081
				MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1	0x3081
				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2	0x3081
				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3	0x3081
				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN	0x3081
				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91
			>;
		};

		pinctrl_enet_3v3: enet3v3grp {
			fsl,pins = <
				MX6SX_PAD_ENET2_COL__GPIO2_IO_6		0x80000000
			>;
		};

		pinctrl_enet2: enet2grp {
			fsl,pins = <
				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC	0xa0b9
				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0	0xa0b1
				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1	0xa0b1
				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2	0xa0b1
				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3	0xa0b1
				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN	0xa0b1
				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK	0x3081
				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0	0x3081
				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1	0x3081
				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2	0x3081
				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3	0x3081
				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN	0x3081
			>;
		};

		pinctrl_gpio_keys: gpio_keysgrp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
				MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO01__I2C1_SDA		0x4001b8b1
				MX6SX_PAD_GPIO1_IO00__I2C1_SCL		0x4001b8b1
			>;
		};

		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX6SX_PAD_KEY_ROW4__I2C3_SDA		0x4001b8b1
				MX6SX_PAD_KEY_COL4__I2C3_SCL		0x4001b8b1
			>;
		};

		pinctrl_i2c4: i2c4grp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA07__I2C4_SDA		0x4001b8b1
				MX6SX_PAD_CSI_DATA06__I2C4_SCL		0x4001b8b1
			>;
		};

		pinctrl_lcd: lcdgrp {
			fsl,pins = <
				MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
				MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
				MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
				MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
				MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
				MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
				MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
				MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
				MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
				MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
				MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
				MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
				MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
				MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
				MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
				MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
				MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
				MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
				MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
				MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
				MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
				MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
				MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
				MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
				MX6SX_PAD_LCD1_CLK__LCDIF1_CLK	0x4001b0b0
				MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
				MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
				MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
				MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
			>;
		};

		pinctrl_pcie: pciegrp {
			fsl,pins = <
				MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
			>;
		};

		pinctrl_pcie_reg: pciereggrp {
			fsl,pins = <
				MX6SX_PAD_ENET1_CRS__GPIO2_IO_1	0x10b0
			>;
		};

		pinctrl_peri_3v3: peri3v3grp {
			fsl,pins = <
				MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16	0x80000000
			>;
		};

		pinctrl_pwm3: pwm3grp-1 {
			fsl,pins = <
				MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
			>;
		};

		pinctrl_qspi2: qspi2grp {
			fsl,pins = <
				MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
				MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70f1
				MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70f1
				MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70f1
				MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70f1
				MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70f1
				MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70f1
				MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70f1
				MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70f1
				MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70f1
				MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70f1
				MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70f1
			>;
		};

		pinctrl_vcc_sd3: vccsd3grp {
			fsl,pins = <
				MX6SX_PAD_KEY_COL1__GPIO2_IO_11		0x17059
			>;
		};

		pinctrl_sai1: sai1grp {
			fsl,pins = <
				MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK	0x130b0
				MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC	0x130b0
				MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0	0x120b0
				MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0	0x130b0
				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK	0x130b0
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1
				MX6SX_PAD_GPIO1_IO05__UART1_RX		0x1b0b1
			>;
		};

		pinctrl_uart5: uart5grp {
			fsl,pins = <
				MX6SX_PAD_KEY_ROW3__UART5_RX		0x1b0b1
				MX6SX_PAD_KEY_COL3__UART5_TX		0x1b0b1
				MX6SX_PAD_KEY_ROW2__UART5_CTS_B		0x1b0b1
				MX6SX_PAD_KEY_COL2__UART5_RTS_B		0x1b0b1
			>;
		};

		pinctrl_usb_otg1: usbotg1grp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9	0x10b0
			>;
		};

		pinctrl_usb_otg1_id: usbotg1idgrp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID	0x17059
			>;
		};

		pinctrl_usb_otg2: usbot2ggrp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12	0x10b0
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6SX_PAD_SD2_CMD__USDHC2_CMD		0x17059
				MX6SX_PAD_SD2_CLK__USDHC2_CLK		0x10059
				MX6SX_PAD_SD2_DATA0__USDHC2_DATA0	0x17059
				MX6SX_PAD_SD2_DATA1__USDHC2_DATA1	0x17059
				MX6SX_PAD_SD2_DATA2__USDHC2_DATA2	0x17059
				MX6SX_PAD_SD2_DATA3__USDHC2_DATA3	0x17059
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x17059
				MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x10059
				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x17059
				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x17059
				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x17059
				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x17059
				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x17059
				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x17059
				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x17059
				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x17059
				MX6SX_PAD_KEY_COL0__GPIO2_IO_10		0x17059 /* CD */
				MX6SX_PAD_KEY_ROW0__GPIO2_IO_15		0x17059 /* WP */
			>;
		};

		pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
			fsl,pins = <
				MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x170b9
				MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x100b9
				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x170b9
				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x170b9
				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x170b9
				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x170b9
				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x170b9
				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x170b9
				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x170b9
				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x170b9
			>;
		};

		pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
			fsl,pins = <
				MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x170f9
				MX6SX_PAD_SD3_CLK__USDHC3_CLK		0x100f9
				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0	0x170f9
				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1	0x170f9
				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2	0x170f9
				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3	0x170f9
				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4	0x170f9
				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x170f9
				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x170f9
				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x170f9
			>;
		};

		pinctrl_usdhc4: usdhc4grp {
			fsl,pins = <
				MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x17059
				MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x10059
				MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x17059
				MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x17059
				MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x17059
				MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x17059
				MX6SX_PAD_SD4_DATA7__GPIO6_IO_21	0x17059 /* CD */
				MX6SX_PAD_SD4_DATA6__GPIO6_IO_20	0x17059 /* WP */
			>;
		};

		pinctrl_wdog: wdoggrp {
			fsl,pins = <
				MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
			>;
		};
	};
};