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|
/dts-v1/;
#include "skeleton.dtsi"
#include <dt-bindings/clock/qcom,gcc-apq8084.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm APQ 8084";
compatible = "qcom,apq8084";
interrupt-parent = <&intc>;
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
smem_mem: smem_region@fa00000 {
reg = <0xfa00000 0x200000>;
no-map;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "qcom,krait";
reg = <0>;
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
cpu-idle-states = <&CPU_SPC>;
};
cpu@1 {
device_type = "cpu";
compatible = "qcom,krait";
reg = <1>;
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
cpu-idle-states = <&CPU_SPC>;
};
cpu@2 {
device_type = "cpu";
compatible = "qcom,krait";
reg = <2>;
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
cpu-idle-states = <&CPU_SPC>;
};
cpu@3 {
device_type = "cpu";
compatible = "qcom,krait";
reg = <3>;
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
cpu-idle-states = <&CPU_SPC>;
};
L2: l2-cache {
compatible = "qcom,arch-cache";
cache-level = <2>;
qcom,saw = <&saw_l2>;
};
idle-states {
CPU_SPC: spc {
compatible = "qcom,idle-state-spc",
"arm,idle-state";
entry-latency-us = <150>;
exit-latency-us = <200>;
min-residency-us = <2000>;
};
};
};
firmware {
scm {
compatible = "qcom,scm";
clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
clock-names = "core", "bus", "iface";
};
};
cpu-pmu {
compatible = "qcom,krait-pmu";
interrupts = <1 7 0xf04>;
};
clocks {
xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
<1 3 0xf08>,
<1 4 0xf08>,
<1 1 0xf08>;
clock-frequency = <19200000>;
};
smem {
compatible = "qcom,smem";
qcom,rpm-msg-ram = <&rpm_msg_ram>;
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
intc: interrupt-controller@f9000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0xf9000000 0x1000>,
<0xf9002000 0x1000>;
};
apcs: syscon@f9011000 {
compatible = "syscon";
reg = <0xf9011000 0x1000>;
};
timer@f9020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0xf9020000 0x1000>;
clock-frequency = <19200000>;
frame@f9021000 {
frame-number = <0>;
interrupts = <0 8 0x4>,
<0 7 0x4>;
reg = <0xf9021000 0x1000>,
<0xf9022000 0x1000>;
};
frame@f9023000 {
frame-number = <1>;
interrupts = <0 9 0x4>;
reg = <0xf9023000 0x1000>;
status = "disabled";
};
frame@f9024000 {
frame-number = <2>;
interrupts = <0 10 0x4>;
reg = <0xf9024000 0x1000>;
status = "disabled";
};
frame@f9025000 {
frame-number = <3>;
interrupts = <0 11 0x4>;
reg = <0xf9025000 0x1000>;
status = "disabled";
};
frame@f9026000 {
frame-number = <4>;
interrupts = <0 12 0x4>;
reg = <0xf9026000 0x1000>;
status = "disabled";
};
frame@f9027000 {
frame-number = <5>;
interrupts = <0 13 0x4>;
reg = <0xf9027000 0x1000>;
status = "disabled";
};
frame@f9028000 {
frame-number = <6>;
interrupts = <0 14 0x4>;
reg = <0xf9028000 0x1000>;
status = "disabled";
};
};
saw0: power-controller@f9089000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
};
saw1: power-controller@f9099000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
};
saw2: power-controller@f90a9000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
};
saw3: power-controller@f90b9000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
};
saw_l2: power-controller@f9012000 {
compatible = "qcom,saw2";
reg = <0xf9012000 0x1000>;
regulator;
};
acc0: clock-controller@f9088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9088000 0x1000>,
<0xf9008000 0x1000>;
};
acc1: clock-controller@f9098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf9098000 0x1000>,
<0xf9008000 0x1000>;
};
acc2: clock-controller@f90a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90a8000 0x1000>,
<0xf9008000 0x1000>;
};
acc3: clock-controller@f90b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0xf90b8000 0x1000>,
<0xf9008000 0x1000>;
};
restart@fc4ab000 {
compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>;
};
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-apq8084";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x4000>;
};
tcsr_mutex_regs: syscon@fd484000 {
compatible = "syscon";
reg = <0xfd484000 0x2000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x80>;
#hwlock-cells = <1>;
};
rpm_msg_ram: memory@fc428000 {
compatible = "qcom,rpm-msg-ram";
reg = <0xfc428000 0x4000>;
};
tlmm: pinctrl@fd510000 {
compatible = "qcom,apq8084-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
};
blsp2_uart2: serial@f995e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf995e000 0x1000>;
interrupts = <0 114 0x0>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
sdhci@f9824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
sdhci@f98a4900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
spmi_bus: spmi@fc4cf000 {
compatible = "qcom,spmi-pmic-arb";
reg-names = "core", "intr", "cnfg";
reg = <0xfc4cf000 0x1000>,
<0xfc4cb000 0x1000>,
<0xfc4ca000 0x1000>;
interrupt-names = "periph_irq";
interrupts = <0 190 0>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
};
smd {
compatible = "qcom,smd";
rpm {
interrupts = <0 168 1>;
qcom,ipc = <&apcs 8 0>;
qcom,smd-edge = <15>;
rpm_requests {
compatible = "qcom,rpm-apq8084";
qcom,smd-channels = "rpm_requests";
pma8084-regulators {
compatible = "qcom,rpm-pma8084-regulators";
pma8084_s1: s1 {};
pma8084_s2: s2 {};
pma8084_s3: s3 {};
pma8084_s4: s4 {};
pma8084_s5: s5 {};
pma8084_s6: s6 {};
pma8084_s7: s7 {};
pma8084_s8: s8 {};
pma8084_s9: s9 {};
pma8084_s10: s10 {};
pma8084_s11: s11 {};
pma8084_s12: s12 {};
pma8084_l1: l1 {};
pma8084_l2: l2 {};
pma8084_l3: l3 {};
pma8084_l4: l4 {};
pma8084_l5: l5 {};
pma8084_l6: l6 {};
pma8084_l7: l7 {};
pma8084_l8: l8 {};
pma8084_l9: l9 {};
pma8084_l10: l10 {};
pma8084_l11: l11 {};
pma8084_l12: l12 {};
pma8084_l13: l13 {};
pma8084_l14: l14 {};
pma8084_l15: l15 {};
pma8084_l16: l16 {};
pma8084_l17: l17 {};
pma8084_l18: l18 {};
pma8084_l19: l19 {};
pma8084_l20: l20 {};
pma8084_l21: l21 {};
pma8084_l22: l22 {};
pma8084_l23: l23 {};
pma8084_l24: l24 {};
pma8084_l25: l25 {};
pma8084_l26: l26 {};
pma8084_l27: l27 {};
pma8084_lvs1: lvs1 {};
pma8084_lvs2: lvs2 {};
pma8084_lvs3: lvs3 {};
pma8084_lvs4: lvs4 {};
pma8084_5vs1: 5vs1 {};
};
};
};
};
};
|
