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/*
* Device Tree Source for the RZ/A1H RSK board
*
* Copyright (C) 2016 Renesas Electronics
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r7s72100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
model = "RSKRZA1";
compatible = "renesas,rskrza1", "renesas,r7s72100";
aliases {
serial0 = &scif2;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
memory@8000000 {
device_type = "memory";
reg = <0x08000000 0x02000000>;
};
lbsc {
#address-cells = <1>;
#size-cells = <1>;
};
leds {
status = "okay";
compatible = "gpio-leds";
led0 {
gpios = <&port7 1 GPIO_ACTIVE_LOW>;
};
};
};
&extal_clk {
clock-frequency = <13330000>;
};
&usb_x1_clk {
clock-frequency = <48000000>;
};
&rtc_x1_clk {
clock-frequency = <32768>;
};
&pinctrl {
/* Serial Console */
scif2_pins: serial2 {
pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
<RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
};
/* Ethernet */
ether_pins: ether {
/* Ethernet on Ports 1,2,3,5 */
pinmux = <RZA1_PINMUX(1, 14, 4)>, /* ET_COL */
<RZA1_PINMUX(5, 9, 2)>, /* ET_MDC */
<RZA1_PINMUX(3, 3, 2)>, /* ET_MDIO */
<RZA1_PINMUX(3, 4, 2)>, /* ET_RXCLK */
<RZA1_PINMUX(3, 5, 2)>, /* ET_RXER */
<RZA1_PINMUX(3, 6, 2)>, /* ET_RXDV */
<RZA1_PINMUX(2, 0, 2)>, /* ET_TXCLK */
<RZA1_PINMUX(2, 1, 2)>, /* ET_TXER */
<RZA1_PINMUX(2, 2, 2)>, /* ET_TXEN */
<RZA1_PINMUX(2, 3, 2)>, /* ET_CRS */
<RZA1_PINMUX(2, 4, 2)>, /* ET_TXD0 */
<RZA1_PINMUX(2, 5, 2)>, /* ET_TXD1 */
<RZA1_PINMUX(2, 6, 2)>, /* ET_TXD2 */
<RZA1_PINMUX(2, 7, 2)>, /* ET_TXD3 */
<RZA1_PINMUX(2, 8, 2)>, /* ET_RXD0 */
<RZA1_PINMUX(2, 9, 2)>, /* ET_RXD1 */
<RZA1_PINMUX(2, 10, 2)>, /* ET_RXD2 */
<RZA1_PINMUX(2, 11, 2)>; /* ET_RXD3 */
};
/* SDHI ch1 on CN1 */
sdhi1_pins: sdhi1 {
pinmux = <RZA1_PINMUX(3, 8, 7)>, /* SD_CD_1 */
<RZA1_PINMUX(3, 9, 7)>, /* SD_WP_1 */
<RZA1_PINMUX(3, 10, 7)>, /* SD_D1_1 */
<RZA1_PINMUX(3, 11, 7)>, /* SD_D0_1 */
<RZA1_PINMUX(3, 12, 7)>, /* SD_CLK_1 */
<RZA1_PINMUX(3, 13, 7)>, /* SD_CMD_1 */
<RZA1_PINMUX(3, 14, 7)>, /* SD_D3_1 */
<RZA1_PINMUX(3, 15, 7)>; /* SD_D2_1 */
};
};
&mtu2 {
status = "okay";
};
ðer {
pinctrl-names = "default";
pinctrl-0 = <ðer_pins>;
status = "okay";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&sdhi1 {
pinctrl-names = "default";
pinctrl-0 = <&sdhi1_pins>;
bus-width = <4>;
status = "okay";
};
&ostm0 {
status = "okay";
};
&ostm1 {
status = "okay";
};
&rtc {
status = "okay";
};
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
status = "okay";
};
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