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/*
* Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
*/
/include/ "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0x00000000 0x04000000>,
<0x08000000 0x04000000>;
};
L2: l2-cache {
compatible = "arm,l210-cache";
reg = <0x10210000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <30>;
cache-unified;
cache-level = <2>;
};
mtu0 {
/* Nomadik system timer */
reg = <0x101e2000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <4>;
};
mtu1 {
/* Secondary timer */
reg = <0x101e3000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <5>;
};
/* A NAND flash of 128 MiB */
fsmc: flash@40000000 {
compatible = "stericsson,fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x10100000 0x1000>, /* FSMC Register*/
<0x40000000 0x2000>, /* NAND Base DATA */
<0x41000000 0x2000>, /* NAND Base ADDR */
<0x40800000 0x2000>; /* NAND Base CMD */
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
status = "okay";
partition@0 {
label = "X-Loader(NAND)";
reg = <0x0 0x40000>;
};
partition@40000 {
label = "MemInit(NAND)";
reg = <0x40000 0x40000>;
};
partition@80000 {
label = "BootLoader(NAND)";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "Kernel zImage(NAND)";
reg = <0x280000 0x300000>;
};
partition@580000 {
label = "Root Filesystem(NAND)";
reg = <0x580000 0x1600000>;
};
partition@1b80000 {
label = "User Filesystem(NAND)";
reg = <0x1b80000 0x6480000>;
};
};
amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
vica: intc@0x10140000 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10140000 0x20>;
};
vicb: intc@0x10140020 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10140020 0x20>;
};
uart0: uart@101fd000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101fd000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <12>;
};
uart1: uart@101fb000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101fb000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <17>;
};
uart2: uart@101f2000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f2000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <28>;
status = "disabled";
};
rng: rng@101b0000 {
compatible = "arm,primecell";
reg = <0x101b0000 0x1000>;
};
rtc: rtc@101e8000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x101e8000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <10>;
};
};
};
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