summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/stm32mp157c-ev1.dts
blob: 372bc2ea6b92192422368bf8413fe62849321d08 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
 */
/dts-v1/;

#include "stm32mp157c-ed1.dts"

/ {
	model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
	compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &uart4;
		ethernet0 = &ethernet0;
	};
};

&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii";
	max-speed = <1000>;
	phy-handle = <&phy0>;

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&cec {
	pinctrl-names = "default";
	pinctrl-0 = <&cec_pins_a>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_pins_a>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";
};

&i2c5 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c5_pins_a>;
	i2c-scl-rising-time-ns = <185>;
	i2c-scl-falling-time-ns = <20>;
	status = "okay";
};

&m_can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&m_can1_pins_a>;
	status = "okay";
};

&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>;
	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	flash0: mx66l51235l@0 {
		reg = <0>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <108000000>;
		#address-cells = <1>;
		#size-cells = <1>;
	};

	flash1: mx66l51235l@1 {
		reg = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <108000000>;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_pins_a>;
	status = "disabled";
};

&timers2 {
	status = "disabled";
	pwm {
		pinctrl-0 = <&pwm2_pins_a>;
		pinctrl-names = "default";
		status = "okay";
	};
	timer@1 {
		status = "okay";
	};
};

&timers8 {
	status = "disabled";
	pwm {
		pinctrl-0 = <&pwm8_pins_a>;
		pinctrl-names = "default";
		status = "okay";
	};
	timer@7 {
		status = "okay";
	};
};

&timers12 {
	status = "disabled";
	pwm {
		pinctrl-0 = <&pwm12_pins_a>;
		pinctrl-names = "default";
		status = "okay";
	};
	timer@11 {
		status = "okay";
	};
};

&usbh_ehci {
	phys = <&usbphyc_port0>;
	phy-names = "usb";
	status = "okay";
};

&usbotg_hs {
	dr_mode = "peripheral";
	phys = <&usbphyc_port1 0>;
	phy-names = "usb2-phy";
	status = "okay";
};

&usbphyc {
	status = "okay";
};